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ASoC: Drop unused state parameter from CODEC suspend callback
[deliverable/linux.git] / sound / soc / codecs / wm8978.c
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0d34e915
GL		 1/*
2 * wm8978.c -- WM8978 ALSA SoC Audio Codec driver
3 *
4 * Copyright (C) 2009-2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
5 * Copyright (C) 2007 Carlos Munoz <carlos@kenati.com>
6 * Copyright 2006-2009 Wolfson Microelectronics PLC.
7 * Based on wm8974 and wm8990 by Liam Girdwood <lrg@slimlogic.co.uk>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/delay.h>
19#include <linux/pm.h>
20#include <linux/i2c.h>
5a0e3ad6 21#include <linux/slab.h>
0d34e915
GL		 22#include <sound/core.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
0d34e915
GL		 26#include <sound/initval.h>
27#include <sound/tlv.h>
28#include <asm/div64.h>
29
30#include "wm8978.h"
31
0d34e915
GL		 32/* wm8978 register cache. Note that register 0 is not included in the cache. */
33static const u16 wm8978_reg[WM8978_CACHEREGNUM] = {
34 0x0000, 0x0000, 0x0000, 0x0000, /* 0x00...0x03 */
35 0x0050, 0x0000, 0x0140, 0x0000, /* 0x04...0x07 */
36 0x0000, 0x0000, 0x0000, 0x00ff, /* 0x08...0x0b */
37 0x00ff, 0x0000, 0x0100, 0x00ff, /* 0x0c...0x0f */
38 0x00ff, 0x0000, 0x012c, 0x002c, /* 0x10...0x13 */
39 0x002c, 0x002c, 0x002c, 0x0000, /* 0x14...0x17 */
40 0x0032, 0x0000, 0x0000, 0x0000, /* 0x18...0x1b */
41 0x0000, 0x0000, 0x0000, 0x0000, /* 0x1c...0x1f */
42 0x0038, 0x000b, 0x0032, 0x0000, /* 0x20...0x23 */
43 0x0008, 0x000c, 0x0093, 0x00e9, /* 0x24...0x27 */
44 0x0000, 0x0000, 0x0000, 0x0000, /* 0x28...0x2b */
45 0x0033, 0x0010, 0x0010, 0x0100, /* 0x2c...0x2f */
46 0x0100, 0x0002, 0x0001, 0x0001, /* 0x30...0x33 */
47 0x0039, 0x0039, 0x0039, 0x0039, /* 0x34...0x37 */
48 0x0001, 0x0001, /* 0x38...0x3b */
49};
50
51/* codec private data */
52struct wm8978_priv {
f0fba2ad 53 enum snd_soc_control_type control_type;
0d34e915
GL		 54 unsigned int f_pllout;
55 unsigned int f_mclk;
56 unsigned int f_256fs;
57 unsigned int f_opclk;
b0580913 58 int mclk_idx;
0d34e915 59 enum wm8978_sysclk_src sysclk;
0d34e915
GL		 60};
61
62static const char *wm8978_companding[] = {"Off", "NC", "u-law", "A-law"};
63static const char *wm8978_eqmode[] = {"Capture", "Playback"};
64static const char *wm8978_bw[] = {"Narrow", "Wide"};
65static const char *wm8978_eq1[] = {"80Hz", "105Hz", "135Hz", "175Hz"};
66static const char *wm8978_eq2[] = {"230Hz", "300Hz", "385Hz", "500Hz"};
67static const char *wm8978_eq3[] = {"650Hz", "850Hz", "1.1kHz", "1.4kHz"};
68static const char *wm8978_eq4[] = {"1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz"};
69static const char *wm8978_eq5[] = {"5.3kHz", "6.9kHz", "9kHz", "11.7kHz"};
70static const char *wm8978_alc3[] = {"ALC", "Limiter"};
71static const char *wm8978_alc1[] = {"Off", "Right", "Left", "Both"};
72
73static const SOC_ENUM_SINGLE_DECL(adc_compand, WM8978_COMPANDING_CONTROL, 1,
74 wm8978_companding);
75static const SOC_ENUM_SINGLE_DECL(dac_compand, WM8978_COMPANDING_CONTROL, 3,
76 wm8978_companding);
77static const SOC_ENUM_SINGLE_DECL(eqmode, WM8978_EQ1, 8, wm8978_eqmode);
78static const SOC_ENUM_SINGLE_DECL(eq1, WM8978_EQ1, 5, wm8978_eq1);
79static const SOC_ENUM_SINGLE_DECL(eq2bw, WM8978_EQ2, 8, wm8978_bw);
80static const SOC_ENUM_SINGLE_DECL(eq2, WM8978_EQ2, 5, wm8978_eq2);
81static const SOC_ENUM_SINGLE_DECL(eq3bw, WM8978_EQ3, 8, wm8978_bw);
82static const SOC_ENUM_SINGLE_DECL(eq3, WM8978_EQ3, 5, wm8978_eq3);
83static const SOC_ENUM_SINGLE_DECL(eq4bw, WM8978_EQ4, 8, wm8978_bw);
84static const SOC_ENUM_SINGLE_DECL(eq4, WM8978_EQ4, 5, wm8978_eq4);
85static const SOC_ENUM_SINGLE_DECL(eq5, WM8978_EQ5, 5, wm8978_eq5);
86static const SOC_ENUM_SINGLE_DECL(alc3, WM8978_ALC_CONTROL_3, 8, wm8978_alc3);
87static const SOC_ENUM_SINGLE_DECL(alc1, WM8978_ALC_CONTROL_1, 7, wm8978_alc1);
88
89static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1);
90static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
91static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1200, 75, 0);
92static const DECLARE_TLV_DB_SCALE(spk_tlv, -5700, 100, 0);
93static const DECLARE_TLV_DB_SCALE(boost_tlv, -1500, 300, 1);
1916a2aa 94static const DECLARE_TLV_DB_SCALE(limiter_tlv, 0, 100, 0);
0d34e915
GL		 95
96static const struct snd_kcontrol_new wm8978_snd_controls[] = {
97
98 SOC_SINGLE("Digital Loopback Switch",
99 WM8978_COMPANDING_CONTROL, 0, 1, 0),
100
101 SOC_ENUM("ADC Companding", adc_compand),
102 SOC_ENUM("DAC Companding", dac_compand),
103
104 SOC_DOUBLE("DAC Inversion Switch", WM8978_DAC_CONTROL, 0, 1, 1, 0),
105
106 SOC_DOUBLE_R_TLV("PCM Volume",
107 WM8978_LEFT_DAC_DIGITAL_VOLUME, WM8978_RIGHT_DAC_DIGITAL_VOLUME,
108 0, 255, 0, digital_tlv),
109
110 SOC_SINGLE("High Pass Filter Switch", WM8978_ADC_CONTROL, 8, 1, 0),
111 SOC_SINGLE("High Pass Cut Off", WM8978_ADC_CONTROL, 4, 7, 0),
112 SOC_DOUBLE("ADC Inversion Switch", WM8978_ADC_CONTROL, 0, 1, 1, 0),
113
114 SOC_DOUBLE_R_TLV("ADC Volume",
115 WM8978_LEFT_ADC_DIGITAL_VOLUME, WM8978_RIGHT_ADC_DIGITAL_VOLUME,
116 0, 255, 0, digital_tlv),
117
118 SOC_ENUM("Equaliser Function", eqmode),
119 SOC_ENUM("EQ1 Cut Off", eq1),
120 SOC_SINGLE_TLV("EQ1 Volume", WM8978_EQ1, 0, 24, 1, eq_tlv),
121
122 SOC_ENUM("Equaliser EQ2 Bandwith", eq2bw),
123 SOC_ENUM("EQ2 Cut Off", eq2),
124 SOC_SINGLE_TLV("EQ2 Volume", WM8978_EQ2, 0, 24, 1, eq_tlv),
125
126 SOC_ENUM("Equaliser EQ3 Bandwith", eq3bw),
127 SOC_ENUM("EQ3 Cut Off", eq3),
128 SOC_SINGLE_TLV("EQ3 Volume", WM8978_EQ3, 0, 24, 1, eq_tlv),
129
130 SOC_ENUM("Equaliser EQ4 Bandwith", eq4bw),
131 SOC_ENUM("EQ4 Cut Off", eq4),
132 SOC_SINGLE_TLV("EQ4 Volume", WM8978_EQ4, 0, 24, 1, eq_tlv),
133
134 SOC_ENUM("EQ5 Cut Off", eq5),
135 SOC_SINGLE_TLV("EQ5 Volume", WM8978_EQ5, 0, 24, 1, eq_tlv),
136
137 SOC_SINGLE("DAC Playback Limiter Switch",
138 WM8978_DAC_LIMITER_1, 8, 1, 0),
139 SOC_SINGLE("DAC Playback Limiter Decay",
140 WM8978_DAC_LIMITER_1, 4, 15, 0),
141 SOC_SINGLE("DAC Playback Limiter Attack",
142 WM8978_DAC_LIMITER_1, 0, 15, 0),
143
144 SOC_SINGLE("DAC Playback Limiter Threshold",
145 WM8978_DAC_LIMITER_2, 4, 7, 0),
1916a2aa
MB		 146 SOC_SINGLE_TLV("DAC Playback Limiter Volume",
147 WM8978_DAC_LIMITER_2, 0, 12, 0, limiter_tlv),
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GL		 148
149 SOC_ENUM("ALC Enable Switch", alc1),
150 SOC_SINGLE("ALC Capture Min Gain", WM8978_ALC_CONTROL_1, 0, 7, 0),
151 SOC_SINGLE("ALC Capture Max Gain", WM8978_ALC_CONTROL_1, 3, 7, 0),
152
c8fb034c 153 SOC_SINGLE("ALC Capture Hold", WM8978_ALC_CONTROL_2, 4, 10, 0),
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GL		 154 SOC_SINGLE("ALC Capture Target", WM8978_ALC_CONTROL_2, 0, 15, 0),
155
156 SOC_ENUM("ALC Capture Mode", alc3),
c8fb034c
MB		 157 SOC_SINGLE("ALC Capture Decay", WM8978_ALC_CONTROL_3, 4, 10, 0),
158 SOC_SINGLE("ALC Capture Attack", WM8978_ALC_CONTROL_3, 0, 10, 0),
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GL		 159
160 SOC_SINGLE("ALC Capture Noise Gate Switch", WM8978_NOISE_GATE, 3, 1, 0),
161 SOC_SINGLE("ALC Capture Noise Gate Threshold",
162 WM8978_NOISE_GATE, 0, 7, 0),
163
164 SOC_DOUBLE_R("Capture PGA ZC Switch",
165 WM8978_LEFT_INP_PGA_CONTROL, WM8978_RIGHT_INP_PGA_CONTROL,
166 7, 1, 0),
167
168 /* OUT1 - Headphones */
169 SOC_DOUBLE_R("Headphone Playback ZC Switch",
170 WM8978_LOUT1_HP_CONTROL, WM8978_ROUT1_HP_CONTROL, 7, 1, 0),
171
172 SOC_DOUBLE_R_TLV("Headphone Playback Volume",
173 WM8978_LOUT1_HP_CONTROL, WM8978_ROUT1_HP_CONTROL,
174 0, 63, 0, spk_tlv),
175
176 /* OUT2 - Speakers */
177 SOC_DOUBLE_R("Speaker Playback ZC Switch",
178 WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL, 7, 1, 0),
179
180 SOC_DOUBLE_R_TLV("Speaker Playback Volume",
181 WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL,
182 0, 63, 0, spk_tlv),
183
184 /* OUT3/4 - Line Output */
185 SOC_DOUBLE_R("Line Playback Switch",
186 WM8978_OUT3_MIXER_CONTROL, WM8978_OUT4_MIXER_CONTROL, 6, 1, 1),
187
188 /* Mixer #3: Boost (Input) mixer */
189 SOC_DOUBLE_R("PGA Boost (+20dB)",
190 WM8978_LEFT_ADC_BOOST_CONTROL, WM8978_RIGHT_ADC_BOOST_CONTROL,
191 8, 1, 0),
192 SOC_DOUBLE_R_TLV("L2/R2 Boost Volume",
193 WM8978_LEFT_ADC_BOOST_CONTROL, WM8978_RIGHT_ADC_BOOST_CONTROL,
194 4, 7, 0, boost_tlv),
195 SOC_DOUBLE_R_TLV("Aux Boost Volume",
196 WM8978_LEFT_ADC_BOOST_CONTROL, WM8978_RIGHT_ADC_BOOST_CONTROL,
197 0, 7, 0, boost_tlv),
198
199 /* Input PGA volume */
200 SOC_DOUBLE_R_TLV("Input PGA Volume",
201 WM8978_LEFT_INP_PGA_CONTROL, WM8978_RIGHT_INP_PGA_CONTROL,
202 0, 63, 0, inpga_tlv),
203
204 /* Headphone */
205 SOC_DOUBLE_R("Headphone Switch",
206 WM8978_LOUT1_HP_CONTROL, WM8978_ROUT1_HP_CONTROL, 6, 1, 1),
207
208 /* Speaker */
209 SOC_DOUBLE_R("Speaker Switch",
210 WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL, 6, 1, 1),
b2c3e923
GL		 211
212 /* DAC / ADC oversampling */
c8fb034c
MB		 213 SOC_SINGLE("DAC 128x Oversampling Switch", WM8978_DAC_CONTROL,
214 5, 1, 0),
215 SOC_SINGLE("ADC 128x Oversampling Switch", WM8978_ADC_CONTROL,
216 5, 1, 0),
0d34e915
GL		 217};
218
219/* Mixer #1: Output (OUT1, OUT2) Mixer: mix AUX, Input mixer output and DAC */
220static const struct snd_kcontrol_new wm8978_left_out_mixer[] = {
221 SOC_DAPM_SINGLE("Line Bypass Switch", WM8978_LEFT_MIXER_CONTROL, 1, 1, 0),
222 SOC_DAPM_SINGLE("Aux Playback Switch", WM8978_LEFT_MIXER_CONTROL, 5, 1, 0),
223 SOC_DAPM_SINGLE("PCM Playback Switch", WM8978_LEFT_MIXER_CONTROL, 0, 1, 0),
224};
225
226static const struct snd_kcontrol_new wm8978_right_out_mixer[] = {
227 SOC_DAPM_SINGLE("Line Bypass Switch", WM8978_RIGHT_MIXER_CONTROL, 1, 1, 0),
228 SOC_DAPM_SINGLE("Aux Playback Switch", WM8978_RIGHT_MIXER_CONTROL, 5, 1, 0),
229 SOC_DAPM_SINGLE("PCM Playback Switch", WM8978_RIGHT_MIXER_CONTROL, 0, 1, 0),
230};
231
232/* OUT3/OUT4 Mixer not implemented */
233
234/* Mixer #2: Input PGA Mute */
235static const struct snd_kcontrol_new wm8978_left_input_mixer[] = {
236 SOC_DAPM_SINGLE("L2 Switch", WM8978_INPUT_CONTROL, 2, 1, 0),
237 SOC_DAPM_SINGLE("MicN Switch", WM8978_INPUT_CONTROL, 1, 1, 0),
238 SOC_DAPM_SINGLE("MicP Switch", WM8978_INPUT_CONTROL, 0, 1, 0),
239};
240static const struct snd_kcontrol_new wm8978_right_input_mixer[] = {
241 SOC_DAPM_SINGLE("R2 Switch", WM8978_INPUT_CONTROL, 6, 1, 0),
242 SOC_DAPM_SINGLE("MicN Switch", WM8978_INPUT_CONTROL, 5, 1, 0),
243 SOC_DAPM_SINGLE("MicP Switch", WM8978_INPUT_CONTROL, 4, 1, 0),
244};
245
246static const struct snd_soc_dapm_widget wm8978_dapm_widgets[] = {
247 SND_SOC_DAPM_DAC("Left DAC", "Left HiFi Playback",
248 WM8978_POWER_MANAGEMENT_3, 0, 0),
249 SND_SOC_DAPM_DAC("Right DAC", "Right HiFi Playback",
250 WM8978_POWER_MANAGEMENT_3, 1, 0),
251 SND_SOC_DAPM_ADC("Left ADC", "Left HiFi Capture",
252 WM8978_POWER_MANAGEMENT_2, 0, 0),
253 SND_SOC_DAPM_ADC("Right ADC", "Right HiFi Capture",
254 WM8978_POWER_MANAGEMENT_2, 1, 0),
255
256 /* Mixer #1: OUT1,2 */
257 SOC_MIXER_ARRAY("Left Output Mixer", WM8978_POWER_MANAGEMENT_3,
258 2, 0, wm8978_left_out_mixer),
259 SOC_MIXER_ARRAY("Right Output Mixer", WM8978_POWER_MANAGEMENT_3,
260 3, 0, wm8978_right_out_mixer),
261
262 SOC_MIXER_ARRAY("Left Input Mixer", WM8978_POWER_MANAGEMENT_2,
263 2, 0, wm8978_left_input_mixer),
264 SOC_MIXER_ARRAY("Right Input Mixer", WM8978_POWER_MANAGEMENT_2,
265 3, 0, wm8978_right_input_mixer),
266
267 SND_SOC_DAPM_PGA("Left Boost Mixer", WM8978_POWER_MANAGEMENT_2,
268 4, 0, NULL, 0),
269 SND_SOC_DAPM_PGA("Right Boost Mixer", WM8978_POWER_MANAGEMENT_2,
270 5, 0, NULL, 0),
271
272 SND_SOC_DAPM_PGA("Left Capture PGA", WM8978_LEFT_INP_PGA_CONTROL,
273 6, 1, NULL, 0),
274 SND_SOC_DAPM_PGA("Right Capture PGA", WM8978_RIGHT_INP_PGA_CONTROL,
275 6, 1, NULL, 0),
276
277 SND_SOC_DAPM_PGA("Left Headphone Out", WM8978_POWER_MANAGEMENT_2,
278 7, 0, NULL, 0),
279 SND_SOC_DAPM_PGA("Right Headphone Out", WM8978_POWER_MANAGEMENT_2,
280 8, 0, NULL, 0),
281
282 SND_SOC_DAPM_PGA("Left Speaker Out", WM8978_POWER_MANAGEMENT_3,
283 6, 0, NULL, 0),
284 SND_SOC_DAPM_PGA("Right Speaker Out", WM8978_POWER_MANAGEMENT_3,
285 5, 0, NULL, 0),
286
287 SND_SOC_DAPM_MIXER("OUT4 VMID", WM8978_POWER_MANAGEMENT_3,
288 8, 0, NULL, 0),
289
290 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8978_POWER_MANAGEMENT_1, 4, 0),
291
292 SND_SOC_DAPM_INPUT("LMICN"),
293 SND_SOC_DAPM_INPUT("LMICP"),
294 SND_SOC_DAPM_INPUT("RMICN"),
295 SND_SOC_DAPM_INPUT("RMICP"),
296 SND_SOC_DAPM_INPUT("LAUX"),
297 SND_SOC_DAPM_INPUT("RAUX"),
298 SND_SOC_DAPM_INPUT("L2"),
299 SND_SOC_DAPM_INPUT("R2"),
300 SND_SOC_DAPM_OUTPUT("LHP"),
301 SND_SOC_DAPM_OUTPUT("RHP"),
302 SND_SOC_DAPM_OUTPUT("LSPK"),
303 SND_SOC_DAPM_OUTPUT("RSPK"),
304};
305
306static const struct snd_soc_dapm_route audio_map[] = {
307 /* Output mixer */
308 {"Right Output Mixer", "PCM Playback Switch", "Right DAC"},
309 {"Right Output Mixer", "Aux Playback Switch", "RAUX"},
310 {"Right Output Mixer", "Line Bypass Switch", "Right Boost Mixer"},
311
312 {"Left Output Mixer", "PCM Playback Switch", "Left DAC"},
313 {"Left Output Mixer", "Aux Playback Switch", "LAUX"},
314 {"Left Output Mixer", "Line Bypass Switch", "Left Boost Mixer"},
315
316 /* Outputs */
317 {"Right Headphone Out", NULL, "Right Output Mixer"},
318 {"RHP", NULL, "Right Headphone Out"},
319
320 {"Left Headphone Out", NULL, "Left Output Mixer"},
321 {"LHP", NULL, "Left Headphone Out"},
322
323 {"Right Speaker Out", NULL, "Right Output Mixer"},
324 {"RSPK", NULL, "Right Speaker Out"},
325
326 {"Left Speaker Out", NULL, "Left Output Mixer"},
327 {"LSPK", NULL, "Left Speaker Out"},
328
329 /* Boost Mixer */
330 {"Right ADC", NULL, "Right Boost Mixer"},
331
332 {"Right Boost Mixer", NULL, "RAUX"},
333 {"Right Boost Mixer", NULL, "Right Capture PGA"},
334 {"Right Boost Mixer", NULL, "R2"},
335
336 {"Left ADC", NULL, "Left Boost Mixer"},
337
338 {"Left Boost Mixer", NULL, "LAUX"},
339 {"Left Boost Mixer", NULL, "Left Capture PGA"},
340 {"Left Boost Mixer", NULL, "L2"},
341
342 /* Input PGA */
343 {"Right Capture PGA", NULL, "Right Input Mixer"},
344 {"Left Capture PGA", NULL, "Left Input Mixer"},
345
346 {"Right Input Mixer", "R2 Switch", "R2"},
347 {"Right Input Mixer", "MicN Switch", "RMICN"},
348 {"Right Input Mixer", "MicP Switch", "RMICP"},
349
350 {"Left Input Mixer", "L2 Switch", "L2"},
351 {"Left Input Mixer", "MicN Switch", "LMICN"},
352 {"Left Input Mixer", "MicP Switch", "LMICP"},
353};
354
355static int wm8978_add_widgets(struct snd_soc_codec *codec)
356{
ce6120cc 357 struct snd_soc_dapm_context *dapm = &codec->dapm;
0d34e915 358
ce6120cc
LG		 359 snd_soc_dapm_new_controls(dapm, wm8978_dapm_widgets,
360 ARRAY_SIZE(wm8978_dapm_widgets));
0d34e915 361 /* set up the WM8978 audio map */
ce6120cc 362 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
0d34e915
GL		 363
364 return 0;
365}
366
367/* PLL divisors */
368struct wm8978_pll_div {
369 u32 k;
370 u8 n;
371 u8 div2;
372};
373
374#define FIXED_PLL_SIZE (1 << 24)
375
f0fba2ad
LG		 376static void pll_factors(struct snd_soc_codec *codec,
377 struct wm8978_pll_div *pll_div, unsigned int target, unsigned int source)
0d34e915
GL		 378{
379 u64 k_part;
380 unsigned int k, n_div, n_mod;
381
382 n_div = target / source;
383 if (n_div < 6) {
384 source >>= 1;
385 pll_div->div2 = 1;
386 n_div = target / source;
387 } else {
388 pll_div->div2 = 0;
389 }
390
391 if (n_div < 6 || n_div > 12)
f0fba2ad 392 dev_warn(codec->dev,
0d34e915
GL		 393 "WM8978 N value exceeds recommended range! N = %u\n",
394 n_div);
395
396 pll_div->n = n_div;
397 n_mod = target - source * n_div;
398 k_part = FIXED_PLL_SIZE * (long long)n_mod + source / 2;
399
400 do_div(k_part, source);
401
402 k = k_part & 0xFFFFFFFF;
403
404 pll_div->k = k;
405}
b0580913
GL		 406
407/* MCLK dividers */
408static const int mclk_numerator[] = {1, 3, 2, 3, 4, 6, 8, 12};
409static const int mclk_denominator[] = {1, 2, 1, 1, 1, 1, 1, 1};
410
411/*
412 * find index >= idx, such that, for a given f_out,
413 * 3 * f_mclk / 4 <= f_PLLOUT < 13 * f_mclk / 4
414 * f_out can be f_256fs or f_opclk, currently only used for f_256fs. Can be
415 * generalised for f_opclk with suitable coefficient arrays, but currently
416 * the OPCLK divisor is calculated directly, not iteratively.
417 */
418static int wm8978_enum_mclk(unsigned int f_out, unsigned int f_mclk,
419 unsigned int *f_pllout)
420{
421 int i;
422
423 for (i = 0; i < ARRAY_SIZE(mclk_numerator); i++) {
424 unsigned int f_pllout_x4 = 4 * f_out * mclk_numerator[i] /
425 mclk_denominator[i];
426 if (3 * f_mclk <= f_pllout_x4 && f_pllout_x4 < 13 * f_mclk) {
427 *f_pllout = f_pllout_x4 / 4;
428 return i;
429 }
430 }
431
432 return -EINVAL;
433}
434
0d34e915
GL		 435/*
436 * Calculate internal frequencies and dividers, according to Figure 40
437 * "PLL and Clock Select Circuit" in WM8978 datasheet Rev. 2.6
438 */
439static int wm8978_configure_pll(struct snd_soc_codec *codec)
440{
b2c812e2 441 struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec);
0d34e915
GL		 442 struct wm8978_pll_div pll_div;
443 unsigned int f_opclk = wm8978->f_opclk, f_mclk = wm8978->f_mclk,
444 f_256fs = wm8978->f_256fs;
b0580913 445 unsigned int f2;
0d34e915
GL		 446
447 if (!f_mclk)
448 return -EINVAL;
449
450 if (f_opclk) {
b0580913
GL		 451 unsigned int opclk_div;
452 /* Cannot set up MCLK divider now, do later */
453 wm8978->mclk_idx = -1;
454
0d34e915
GL		 455 /*
456 * The user needs OPCLK. Choose OPCLKDIV to put
457 * 6 <= R = f2 / f1 < 13, 1 <= OPCLKDIV <= 4.
458 * f_opclk = f_mclk * prescale * R / 4 / OPCLKDIV, where
459 * prescale = 1, or prescale = 2. Prescale is calculated inside
460 * pll_factors(). We have to select f_PLLOUT, such that
461 * f_mclk * 3 / 4 <= f_PLLOUT < f_mclk * 13 / 4. Must be
462 * f_mclk * 3 / 16 <= f_opclk < f_mclk * 13 / 4.
463 */
464 if (16 * f_opclk < 3 * f_mclk || 4 * f_opclk >= 13 * f_mclk)
465 return -EINVAL;
466
467 if (4 * f_opclk < 3 * f_mclk)
468 /* Have to use OPCLKDIV */
469 opclk_div = (3 * f_mclk / 4 + f_opclk - 1) / f_opclk;
470 else
471 opclk_div = 1;
472
473 dev_dbg(codec->dev, "%s: OPCLKDIV=%d\n", __func__, opclk_div);
474
475 snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 0x30,
476 (opclk_div - 1) << 4);
477
478 wm8978->f_pllout = f_opclk * opclk_div;
479 } else if (f_256fs) {
480 /*
b0580913 481 * Not using OPCLK, but PLL is used for the codec, choose R:
0d34e915
GL		 482 * 6 <= R = f2 / f1 < 13, to put 1 <= MCLKDIV <= 12.
483 * f_256fs = f_mclk * prescale * R / 4 / MCLKDIV, where
484 * prescale = 1, or prescale = 2. Prescale is calculated inside
485 * pll_factors(). We have to select f_PLLOUT, such that
486 * f_mclk * 3 / 4 <= f_PLLOUT < f_mclk * 13 / 4. Must be
487 * f_mclk * 3 / 48 <= f_256fs < f_mclk * 13 / 4. This means MCLK
488 * must be 3.781MHz <= f_MCLK <= 32.768MHz
489 */
b0580913
GL		 490 int idx = wm8978_enum_mclk(f_256fs, f_mclk, &wm8978->f_pllout);
491 if (idx < 0)
492 return idx;
0d34e915 493
b0580913 494 wm8978->mclk_idx = idx;
0d34e915
GL		 495
496 /* GPIO1 into default mode as input - before configuring PLL */
497 snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 7, 0);
498 } else {
499 return -EINVAL;
500 }
501
502 f2 = wm8978->f_pllout * 4;
503
504 dev_dbg(codec->dev, "%s: f_MCLK=%uHz, f_PLLOUT=%uHz\n", __func__,
505 wm8978->f_mclk, wm8978->f_pllout);
506
f0fba2ad 507 pll_factors(codec, &pll_div, f2, wm8978->f_mclk);
0d34e915
GL		 508
509 dev_dbg(codec->dev, "%s: calculated PLL N=0x%x, K=0x%x, div2=%d\n",
510 __func__, pll_div.n, pll_div.k, pll_div.div2);
511
512 /* Turn PLL off for configuration... */
513 snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0);
514
515 snd_soc_write(codec, WM8978_PLL_N, (pll_div.div2 << 4) | pll_div.n);
516 snd_soc_write(codec, WM8978_PLL_K1, pll_div.k >> 18);
517 snd_soc_write(codec, WM8978_PLL_K2, (pll_div.k >> 9) & 0x1ff);
518 snd_soc_write(codec, WM8978_PLL_K3, pll_div.k & 0x1ff);
519
520 /* ...and on again */
521 snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0x20);
522
523 if (f_opclk)
524 /* Output PLL (OPCLK) to GPIO1 */
525 snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 7, 4);
526
527 return 0;
528}
529
530/*
531 * Configure WM8978 clock dividers.
532 */
533static int wm8978_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
534 int div_id, int div)
535{
536 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 537 struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec);
0d34e915
GL		 538 int ret = 0;
539
540 switch (div_id) {
541 case WM8978_OPCLKRATE:
542 wm8978->f_opclk = div;
543
544 if (wm8978->f_mclk)
b0580913
GL		 545 /*
546 * We know the MCLK frequency, the user has requested
547 * OPCLK, configure the PLL based on that and start it
548 * and OPCLK immediately. We will configure PLL to match
549 * user-requested OPCLK frquency as good as possible.
550 * In fact, it is likely, that matching the sampling
551 * rate, when it becomes known, is more important, and
552 * we will not be reconfiguring PLL then, because we
553 * must not interrupt OPCLK. But it should be fine,
554 * because typically the user will request OPCLK to run
555 * at 256fs or 512fs, and for these cases we will also
556 * find an exact MCLK divider configuration - it will
557 * be equal to or double the OPCLK divisor.
558 */
0d34e915
GL		 559 ret = wm8978_configure_pll(codec);
560 break;
0d34e915
GL		 561 case WM8978_BCLKDIV:
562 if (div & ~0x1c)
563 return -EINVAL;
564 snd_soc_update_bits(codec, WM8978_CLOCKING, 0x1c, div);
565 break;
566 default:
567 return -EINVAL;
568 }
569
570 dev_dbg(codec->dev, "%s: ID %d, value %u\n", __func__, div_id, div);
571
572 return ret;
573}
574
575/*
576 * @freq: when .set_pll() us not used, freq is codec MCLK input frequency
577 */
578static int wm8978_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id,
579 unsigned int freq, int dir)
580{
581 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 582 struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec);
0d34e915
GL		 583 int ret = 0;
584
585 dev_dbg(codec->dev, "%s: ID %d, freq %u\n", __func__, clk_id, freq);
586
587 if (freq) {
588 wm8978->f_mclk = freq;
589
590 /* Even if MCLK is used for system clock, might have to drive OPCLK */
591 if (wm8978->f_opclk)
592 ret = wm8978_configure_pll(codec);
593
594 /* Our sysclk is fixed to 256 * fs, will configure in .hw_params() */
595
596 if (!ret)
597 wm8978->sysclk = clk_id;
598 }
599
600 if (wm8978->sysclk == WM8978_PLL && (!freq || clk_id == WM8978_MCLK)) {
601 /* Clock CODEC directly from MCLK */
602 snd_soc_update_bits(codec, WM8978_CLOCKING, 0x100, 0);
603
604 /* GPIO1 into default mode as input - before configuring PLL */
605 snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 7, 0);
606
607 /* Turn off PLL */
608 snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0);
609 wm8978->sysclk = WM8978_MCLK;
610 wm8978->f_pllout = 0;
611 wm8978->f_opclk = 0;
612 }
613
614 return ret;
615}
616
617/*
618 * Set ADC and Voice DAC format.
619 */
620static int wm8978_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
621{
622 struct snd_soc_codec *codec = codec_dai->codec;
623 /*
624 * BCLK polarity mask = 0x100, LRC clock polarity mask = 0x80,
625 * Data Format mask = 0x18: all will be calculated anew
626 */
627 u16 iface = snd_soc_read(codec, WM8978_AUDIO_INTERFACE) & ~0x198;
628 u16 clk = snd_soc_read(codec, WM8978_CLOCKING);
629
630 dev_dbg(codec->dev, "%s\n", __func__);
631
632 /* set master/slave audio interface */
633 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
634 case SND_SOC_DAIFMT_CBM_CFM:
635 clk |= 1;
636 break;
637 case SND_SOC_DAIFMT_CBS_CFS:
638 clk &= ~1;
639 break;
640 default:
641 return -EINVAL;
642 }
643
644 /* interface format */
645 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
646 case SND_SOC_DAIFMT_I2S:
647 iface |= 0x10;
648 break;
649 case SND_SOC_DAIFMT_RIGHT_J:
650 break;
651 case SND_SOC_DAIFMT_LEFT_J:
652 iface |= 0x8;
653 break;
654 case SND_SOC_DAIFMT_DSP_A:
655 iface |= 0x18;
656 break;
657 default:
658 return -EINVAL;
659 }
660
661 /* clock inversion */
662 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
663 case SND_SOC_DAIFMT_NB_NF:
664 break;
665 case SND_SOC_DAIFMT_IB_IF:
666 iface |= 0x180;
667 break;
668 case SND_SOC_DAIFMT_IB_NF:
669 iface |= 0x100;
670 break;
671 case SND_SOC_DAIFMT_NB_IF:
672 iface |= 0x80;
673 break;
674 default:
675 return -EINVAL;
676 }
677
678 snd_soc_write(codec, WM8978_AUDIO_INTERFACE, iface);
679 snd_soc_write(codec, WM8978_CLOCKING, clk);
680
681 return 0;
682}
683
0d34e915
GL		 684/*
685 * Set PCM DAI bit size and sample rate.
686 */
687static int wm8978_hw_params(struct snd_pcm_substream *substream,
688 struct snd_pcm_hw_params *params,
689 struct snd_soc_dai *dai)
690{
691 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 692 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 693 struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec);
0d34e915
GL		 694 /* Word length mask = 0x60 */
695 u16 iface_ctl = snd_soc_read(codec, WM8978_AUDIO_INTERFACE) & ~0x60;
696 /* Sampling rate mask = 0xe (for filters) */
697 u16 add_ctl = snd_soc_read(codec, WM8978_ADDITIONAL_CONTROL) & ~0xe;
698 u16 clking = snd_soc_read(codec, WM8978_CLOCKING);
699 enum wm8978_sysclk_src current_clk_id = clking & 0x100 ?
700 WM8978_PLL : WM8978_MCLK;
701 unsigned int f_sel, diff, diff_best = INT_MAX;
702 int i, best = 0;
703
704 if (!wm8978->f_mclk)
705 return -EINVAL;
706
707 /* bit size */
708 switch (params_format(params)) {
709 case SNDRV_PCM_FORMAT_S16_LE:
710 break;
711 case SNDRV_PCM_FORMAT_S20_3LE:
712 iface_ctl |= 0x20;
713 break;
714 case SNDRV_PCM_FORMAT_S24_LE:
715 iface_ctl |= 0x40;
716 break;
717 case SNDRV_PCM_FORMAT_S32_LE:
718 iface_ctl |= 0x60;
719 break;
720 }
721
722 /* filter coefficient */
723 switch (params_rate(params)) {
724 case 8000:
725 add_ctl |= 0x5 << 1;
726 break;
727 case 11025:
728 add_ctl |= 0x4 << 1;
729 break;
730 case 16000:
731 add_ctl |= 0x3 << 1;
732 break;
733 case 22050:
734 add_ctl |= 0x2 << 1;
735 break;
736 case 32000:
737 add_ctl |= 0x1 << 1;
738 break;
739 case 44100:
740 case 48000:
741 break;
742 }
743
744 /* Sampling rate is known now, can configure the MCLK divider */
745 wm8978->f_256fs = params_rate(params) * 256;
746
747 if (wm8978->sysclk == WM8978_MCLK) {
b0580913 748 wm8978->mclk_idx = -1;
0d34e915
GL		 749 f_sel = wm8978->f_mclk;
750 } else {
751 if (!wm8978->f_pllout) {
b0580913 752 /* We only enter here, if OPCLK is not used */
0d34e915
GL		 753 int ret = wm8978_configure_pll(codec);
754 if (ret < 0)
755 return ret;
756 }
757 f_sel = wm8978->f_pllout;
758 }
759
b0580913
GL		 760 if (wm8978->mclk_idx < 0) {
761 /* Either MCLK is used directly, or OPCLK is used */
762 if (f_sel < wm8978->f_256fs || f_sel > 12 * wm8978->f_256fs)
763 return -EINVAL;
0d34e915 764
b0580913
GL		 765 for (i = 0; i < ARRAY_SIZE(mclk_numerator); i++) {
766 diff = abs(wm8978->f_256fs * 3 -
767 f_sel * 3 * mclk_denominator[i] / mclk_numerator[i]);
0d34e915 768
b0580913
GL		 769 if (diff < diff_best) {
770 diff_best = diff;
771 best = i;
772 }
0d34e915 773
b0580913
GL		 774 if (!diff)
775 break;
776 }
777 } else {
778 /* OPCLK not used, codec driven by PLL */
779 best = wm8978->mclk_idx;
780 diff = 0;
0d34e915
GL		 781 }
782
783 if (diff)
b0580913
GL		 784 dev_warn(codec->dev, "Imprecise sampling rate: %uHz%s\n",
785 f_sel * mclk_denominator[best] / mclk_numerator[best] / 256,
786 wm8978->sysclk == WM8978_MCLK ?
787 ", consider using PLL" : "");
0d34e915
GL		 788
789 dev_dbg(codec->dev, "%s: fmt %d, rate %u, MCLK divisor #%d\n", __func__,
790 params_format(params), params_rate(params), best);
791
792 /* MCLK divisor mask = 0xe0 */
793 snd_soc_update_bits(codec, WM8978_CLOCKING, 0xe0, best << 5);
794
795 snd_soc_write(codec, WM8978_AUDIO_INTERFACE, iface_ctl);
796 snd_soc_write(codec, WM8978_ADDITIONAL_CONTROL, add_ctl);
797
798 if (wm8978->sysclk != current_clk_id) {
799 if (wm8978->sysclk == WM8978_PLL)
800 /* Run CODEC from PLL instead of MCLK */
801 snd_soc_update_bits(codec, WM8978_CLOCKING,
802 0x100, 0x100);
803 else
804 /* Clock CODEC directly from MCLK */
805 snd_soc_update_bits(codec, WM8978_CLOCKING, 0x100, 0);
806 }
807
808 return 0;
809}
810
811static int wm8978_mute(struct snd_soc_dai *dai, int mute)
812{
813 struct snd_soc_codec *codec = dai->codec;
814
815 dev_dbg(codec->dev, "%s: %d\n", __func__, mute);
816
817 if (mute)
818 snd_soc_update_bits(codec, WM8978_DAC_CONTROL, 0x40, 0x40);
819 else
820 snd_soc_update_bits(codec, WM8978_DAC_CONTROL, 0x40, 0);
821
822 return 0;
823}
824
825static int wm8978_set_bias_level(struct snd_soc_codec *codec,
826 enum snd_soc_bias_level level)
827{
828 u16 power1 = snd_soc_read(codec, WM8978_POWER_MANAGEMENT_1) & ~3;
829
830 switch (level) {
831 case SND_SOC_BIAS_ON:
832 case SND_SOC_BIAS_PREPARE:
833 power1 |= 1; /* VMID 75k */
834 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1, power1);
835 break;
836 case SND_SOC_BIAS_STANDBY:
837 /* bit 3: enable bias, bit 2: enable I/O tie off buffer */
838 power1 |= 0xc;
839
ce6120cc 840 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
0d34e915
GL		 841 /* Initial cap charge at VMID 5k */
842 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1,
843 power1 | 0x3);
844 mdelay(100);
845 }
846
847 power1 |= 0x2; /* VMID 500k */
848 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1, power1);
849 break;
850 case SND_SOC_BIAS_OFF:
851 /* Preserve PLL - OPCLK may be used by someone */
852 snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, ~0x20, 0);
853 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_2, 0);
854 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_3, 0);
855 break;
856 }
857
858 dev_dbg(codec->dev, "%s: %d, %x\n", __func__, level, power1);
859
ce6120cc 860 codec->dapm.bias_level = level;
0d34e915
GL		 861 return 0;
862}
863
864#define WM8978_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
865 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
866
85e7652d 867static const struct snd_soc_dai_ops wm8978_dai_ops = {
0d34e915
GL		 868 .hw_params = wm8978_hw_params,
869 .digital_mute = wm8978_mute,
870 .set_fmt = wm8978_set_dai_fmt,
871 .set_clkdiv = wm8978_set_dai_clkdiv,
872 .set_sysclk = wm8978_set_dai_sysclk,
873};
874
875/* Also supports 12kHz */
f0fba2ad
LG		 876static struct snd_soc_dai_driver wm8978_dai = {
877 .name = "wm8978-hifi",
0d34e915
GL		 878 .playback = {
879 .stream_name = "Playback",
880 .channels_min = 1,
881 .channels_max = 2,
882 .rates = SNDRV_PCM_RATE_8000_48000,
883 .formats = WM8978_FORMATS,
884 },
885 .capture = {
886 .stream_name = "Capture",
887 .channels_min = 1,
888 .channels_max = 2,
889 .rates = SNDRV_PCM_RATE_8000_48000,
890 .formats = WM8978_FORMATS,
891 },
892 .ops = &wm8978_dai_ops,
893};
0d34e915 894
84b315ee 895static int wm8978_suspend(struct snd_soc_codec *codec)
0d34e915 896{
0d34e915
GL		 897 wm8978_set_bias_level(codec, SND_SOC_BIAS_OFF);
898 /* Also switch PLL off */
899 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1, 0);
0d34e915
GL		 900
901 return 0;
902}
903
f0fba2ad 904static int wm8978_resume(struct snd_soc_codec *codec)
0d34e915 905{
b2c812e2 906 struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec);
0d34e915
GL		 907 int i;
908 u16 *cache = codec->reg_cache;
909
0d34e915
GL		 910 /* Sync reg_cache with the hardware */
911 for (i = 0; i < ARRAY_SIZE(wm8978_reg); i++) {
912 if (i == WM8978_RESET)
913 continue;
914 if (cache[i] != wm8978_reg[i])
915 snd_soc_write(codec, i, cache[i]);
916 }
917
918 wm8978_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
919
920 if (wm8978->f_pllout)
921 /* Switch PLL on */
922 snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0x20);
923
924 return 0;
925}
926
0d34e915
GL		 927/*
928 * These registers contain an "update" bit - bit 8. This means, for example,
929 * that one can write new DAC digital volume for both channels, but only when
930 * the update bit is set, will also the volume be updated - simultaneously for
931 * both channels.
932 */
933static const int update_reg[] = {
934 WM8978_LEFT_DAC_DIGITAL_VOLUME,
935 WM8978_RIGHT_DAC_DIGITAL_VOLUME,
936 WM8978_LEFT_ADC_DIGITAL_VOLUME,
937 WM8978_RIGHT_ADC_DIGITAL_VOLUME,
938 WM8978_LEFT_INP_PGA_CONTROL,
939 WM8978_RIGHT_INP_PGA_CONTROL,
940 WM8978_LOUT1_HP_CONTROL,
941 WM8978_ROUT1_HP_CONTROL,
942 WM8978_LOUT2_SPK_CONTROL,
943 WM8978_ROUT2_SPK_CONTROL,
944};
945
f0fba2ad 946static int wm8978_probe(struct snd_soc_codec *codec)
0d34e915 947{
f0fba2ad
LG		 948 struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec);
949 int ret = 0, i;
0d34e915
GL		 950
951 /*
952 * Set default system clock to PLL, it is more precise, this is also the
953 * default hardware setting
954 */
955 wm8978->sysclk = WM8978_PLL;
0d34e915
GL		 956 ret = snd_soc_codec_set_cache_io(codec, 7, 9, SND_SOC_I2C);
957 if (ret < 0) {
958 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
f0fba2ad 959 return ret;
0d34e915
GL		 960 }
961
0d34e915
GL		 962 /*
963 * Set the update bit in all registers, that have one. This way all
964 * writes to those registers will also cause the update bit to be
965 * written.
966 */
967 for (i = 0; i < ARRAY_SIZE(update_reg); i++)
a1b3b5ee 968 snd_soc_update_bits(codec, update_reg[i], 0x100, 0x100);
0d34e915
GL		 969
970 /* Reset the codec */
971 ret = snd_soc_write(codec, WM8978_RESET, 0);
972 if (ret < 0) {
973 dev_err(codec->dev, "Failed to issue reset\n");
f0fba2ad 974 return ret;
0d34e915
GL		 975 }
976
0d34e915
GL		 977 wm8978_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
978
f0fba2ad
LG		 979 snd_soc_add_controls(codec, wm8978_snd_controls,
980 ARRAY_SIZE(wm8978_snd_controls));
981 wm8978_add_widgets(codec);
0d34e915
GL		 982
983 return 0;
0d34e915
GL		 984}
985
f0fba2ad
LG		 986/* power down chip */
987static int wm8978_remove(struct snd_soc_codec *codec)
0d34e915 988{
f0fba2ad
LG		 989 wm8978_set_bias_level(codec, SND_SOC_BIAS_OFF);
990 return 0;
0d34e915
GL		 991}
992
f0fba2ad
LG		 993static struct snd_soc_codec_driver soc_codec_dev_wm8978 = {
994 .probe = wm8978_probe,
995 .remove = wm8978_remove,
996 .suspend = wm8978_suspend,
997 .resume = wm8978_resume,
998 .set_bias_level = wm8978_set_bias_level,
999 .reg_cache_size = ARRAY_SIZE(wm8978_reg),
1000 .reg_word_size = sizeof(u16),
1001 .reg_cache_default = wm8978_reg,
1002};
1003
1004#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
0d34e915
GL		 1005static __devinit int wm8978_i2c_probe(struct i2c_client *i2c,
1006 const struct i2c_device_id *id)
1007{
1008 struct wm8978_priv *wm8978;
f0fba2ad 1009 int ret;
0d34e915
GL		 1010
1011 wm8978 = kzalloc(sizeof(struct wm8978_priv), GFP_KERNEL);
1012 if (wm8978 == NULL)
1013 return -ENOMEM;
1014
0d34e915 1015 i2c_set_clientdata(i2c, wm8978);
0d34e915 1016
f0fba2ad
LG		 1017 ret = snd_soc_register_codec(&i2c->dev,
1018 &soc_codec_dev_wm8978, &wm8978_dai, 1);
d484366b
AL		 1019 if (ret < 0)
1020 kfree(wm8978);
d484366b 1021 return ret;
0d34e915
GL		 1022}
1023
1024static __devexit int wm8978_i2c_remove(struct i2c_client *client)
1025{
f0fba2ad
LG		 1026 snd_soc_unregister_codec(&client->dev);
1027 kfree(i2c_get_clientdata(client));
0d34e915
GL		 1028 return 0;
1029}
1030
1031static const struct i2c_device_id wm8978_i2c_id[] = {
1032 { "wm8978", 0 },
1033 { }
1034};
1035MODULE_DEVICE_TABLE(i2c, wm8978_i2c_id);
1036
1037static struct i2c_driver wm8978_i2c_driver = {
1038 .driver = {
5250a503 1039 .name = "wm8978",
0d34e915
GL		 1040 .owner = THIS_MODULE,
1041 },
1042 .probe = wm8978_i2c_probe,
1043 .remove = __devexit_p(wm8978_i2c_remove),
1044 .id_table = wm8978_i2c_id,
1045};
f0fba2ad 1046#endif
0d34e915
GL		 1047
1048static int __init wm8978_modinit(void)
1049{
f0fba2ad
LG		 1050 int ret = 0;
1051#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1052 ret = i2c_add_driver(&wm8978_i2c_driver);
1053 if (ret != 0) {
1054 printk(KERN_ERR "Failed to register WM8978 I2C driver: %d\n",
1055 ret);
1056 }
1057#endif
1058 return ret;
0d34e915
GL		 1059}
1060module_init(wm8978_modinit);
1061
1062static void __exit wm8978_exit(void)
1063{
f0fba2ad 1064#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
0d34e915 1065 i2c_del_driver(&wm8978_i2c_driver);
f0fba2ad 1066#endif
0d34e915
GL		 1067}
1068module_exit(wm8978_exit);
1069
1070MODULE_DESCRIPTION("ASoC WM8978 codec driver");
1071MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
1072MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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