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ASoC: Use DC servo startup mode when not doing DCS correction
[deliverable/linux.git] / sound / soc / codecs / wm8994.c
CommitLineData
9e6e96a1
MB		 1/*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
21#include <linux/regulator/consumer.h>
5a0e3ad6 22#include <linux/slab.h>
9e6e96a1
MB		 23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/soc.h>
9e6e96a1
MB		 27#include <sound/initval.h>
28#include <sound/tlv.h>
29
30#include <linux/mfd/wm8994/core.h>
31#include <linux/mfd/wm8994/registers.h>
32#include <linux/mfd/wm8994/pdata.h>
33#include <linux/mfd/wm8994/gpio.h>
34
35#include "wm8994.h"
36#include "wm_hubs.h"
37
9e6e96a1
MB		 38struct fll_config {
39 int src;
40 int in;
41 int out;
42};
43
44#define WM8994_NUM_DRC 3
45#define WM8994_NUM_EQ 3
46
47static int wm8994_drc_base[] = {
48 WM8994_AIF1_DRC1_1,
49 WM8994_AIF1_DRC2_1,
50 WM8994_AIF2_DRC_1,
51};
52
53static int wm8994_retune_mobile_base[] = {
54 WM8994_AIF1_DAC1_EQ_GAINS_1,
55 WM8994_AIF1_DAC2_EQ_GAINS_1,
56 WM8994_AIF2_EQ_GAINS_1,
57};
58
59#define WM8994_REG_CACHE_SIZE 0x621
60
88766984
MB		 61struct wm8994_micdet {
62 struct snd_soc_jack *jack;
63 int det;
64 int shrt;
65};
66
9e6e96a1
MB		 67/* codec private data */
68struct wm8994_priv {
69 struct wm_hubs_data hubs;
f0fba2ad
LG		 70 enum snd_soc_control_type control_type;
71 void *control_data;
72 struct snd_soc_codec *codec;
9e6e96a1
MB		 73 u16 reg_cache[WM8994_REG_CACHE_SIZE + 1];
74 int sysclk[2];
75 int sysclk_rate[2];
76 int mclk[2];
77 int aifclk[2];
78 struct fll_config fll[2], fll_suspend[2];
79
80 int dac_rates[2];
81 int lrclk_shared[2];
82
83 /* Platform dependant DRC configuration */
84 const char **drc_texts;
85 int drc_cfg[WM8994_NUM_DRC];
86 struct soc_enum drc_enum;
87
88 /* Platform dependant ReTune mobile configuration */
89 int num_retune_mobile_texts;
90 const char **retune_mobile_texts;
91 int retune_mobile_cfg[WM8994_NUM_EQ];
92 struct soc_enum retune_mobile_enum;
93
88766984
MB		 94 struct wm8994_micdet micdet[2];
95
b6b05691 96 int revision;
9e6e96a1
MB		 97 struct wm8994_pdata *pdata;
98};
99
9e6e96a1
MB		 100static int wm8994_readable(unsigned int reg)
101{
e88ff1e6
MB		 102 switch (reg) {
103 case WM8994_GPIO_1:
104 case WM8994_GPIO_2:
105 case WM8994_GPIO_3:
106 case WM8994_GPIO_4:
107 case WM8994_GPIO_5:
108 case WM8994_GPIO_6:
109 case WM8994_GPIO_7:
110 case WM8994_GPIO_8:
111 case WM8994_GPIO_9:
112 case WM8994_GPIO_10:
113 case WM8994_GPIO_11:
114 case WM8994_INTERRUPT_STATUS_1:
115 case WM8994_INTERRUPT_STATUS_2:
116 case WM8994_INTERRUPT_RAW_STATUS_2:
117 return 1;
118 default:
119 break;
120 }
121
7b306dae 122 if (reg >= WM8994_CACHE_SIZE)
9e6e96a1 123 return 0;
7b306dae 124 return wm8994_access_masks[reg].readable != 0;
9e6e96a1
MB		 125}
126
127static int wm8994_volatile(unsigned int reg)
128{
129 if (reg >= WM8994_REG_CACHE_SIZE)
130 return 1;
131
132 switch (reg) {
133 case WM8994_SOFTWARE_RESET:
134 case WM8994_CHIP_REVISION:
135 case WM8994_DC_SERVO_1:
136 case WM8994_DC_SERVO_READBACK:
137 case WM8994_RATE_STATUS:
138 case WM8994_LDO_1:
139 case WM8994_LDO_2:
140 return 1;
141 default:
142 return 0;
143 }
144}
145
146static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
147 unsigned int value)
148{
b2c812e2 149 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 150
151 BUG_ON(reg > WM8994_MAX_REGISTER);
152
153 if (!wm8994_volatile(reg))
154 wm8994->reg_cache[reg] = value;
155
156 return wm8994_reg_write(codec->control_data, reg, value);
157}
158
159static unsigned int wm8994_read(struct snd_soc_codec *codec,
160 unsigned int reg)
161{
162 u16 *reg_cache = codec->reg_cache;
163
164 BUG_ON(reg > WM8994_MAX_REGISTER);
165
166 if (wm8994_volatile(reg))
167 return wm8994_reg_read(codec->control_data, reg);
168 else
169 return reg_cache[reg];
170}
171
172static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
173{
b2c812e2 174 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 175 int rate;
176 int reg1 = 0;
177 int offset;
178
179 if (aif)
180 offset = 4;
181 else
182 offset = 0;
183
184 switch (wm8994->sysclk[aif]) {
185 case WM8994_SYSCLK_MCLK1:
186 rate = wm8994->mclk[0];
187 break;
188
189 case WM8994_SYSCLK_MCLK2:
190 reg1 |= 0x8;
191 rate = wm8994->mclk[1];
192 break;
193
194 case WM8994_SYSCLK_FLL1:
195 reg1 |= 0x10;
196 rate = wm8994->fll[0].out;
197 break;
198
199 case WM8994_SYSCLK_FLL2:
200 reg1 |= 0x18;
201 rate = wm8994->fll[1].out;
202 break;
203
204 default:
205 return -EINVAL;
206 }
207
208 if (rate >= 13500000) {
209 rate /= 2;
210 reg1 |= WM8994_AIF1CLK_DIV;
211
212 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
213 aif + 1, rate);
214 }
5e5e2bef
MB		 215
216 if (rate && rate < 3000000)
217 dev_warn(codec->dev, "AIF%dCLK is %dHz, should be >=3MHz for optimal performance\n",
218 aif + 1, rate);
219
9e6e96a1
MB		 220 wm8994->aifclk[aif] = rate;
221
222 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
223 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
224 reg1);
225
226 return 0;
227}
228
229static int configure_clock(struct snd_soc_codec *codec)
230{
b2c812e2 231 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 232 int old, new;
233
234 /* Bring up the AIF clocks first */
235 configure_aif_clock(codec, 0);
236 configure_aif_clock(codec, 1);
237
238 /* Then switch CLK_SYS over to the higher of them; a change
239 * can only happen as a result of a clocking change which can
240 * only be made outside of DAPM so we can safely redo the
241 * clocking.
242 */
243
244 /* If they're equal it doesn't matter which is used */
245 if (wm8994->aifclk[0] == wm8994->aifclk[1])
246 return 0;
247
248 if (wm8994->aifclk[0] < wm8994->aifclk[1])
249 new = WM8994_SYSCLK_SRC;
250 else
251 new = 0;
252
253 old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC;
254
255 /* If there's no change then we're done. */
256 if (old == new)
257 return 0;
258
259 snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new);
260
ce6120cc 261 snd_soc_dapm_sync(&codec->dapm);
9e6e96a1
MB		 262
263 return 0;
264}
265
266static int check_clk_sys(struct snd_soc_dapm_widget *source,
267 struct snd_soc_dapm_widget *sink)
268{
269 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
270 const char *clk;
271
272 /* Check what we're currently using for CLK_SYS */
273 if (reg & WM8994_SYSCLK_SRC)
274 clk = "AIF2CLK";
275 else
276 clk = "AIF1CLK";
277
278 return strcmp(source->name, clk) == 0;
279}
280
281static const char *sidetone_hpf_text[] = {
282 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
283};
284
285static const struct soc_enum sidetone_hpf =
286 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
287
288static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
289static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
290static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
291static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
292static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
293
294#define WM8994_DRC_SWITCH(xname, reg, shift) \
295{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
296 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
297 .put = wm8994_put_drc_sw, \
298 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
299
300static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
301 struct snd_ctl_elem_value *ucontrol)
302{
303 struct soc_mixer_control *mc =
304 (struct soc_mixer_control *)kcontrol->private_value;
305 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
306 int mask, ret;
307
308 /* Can't enable both ADC and DAC paths simultaneously */
309 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
310 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
311 WM8994_AIF1ADC1R_DRC_ENA_MASK;
312 else
313 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
314
315 ret = snd_soc_read(codec, mc->reg);
316 if (ret < 0)
317 return ret;
318 if (ret & mask)
319 return -EINVAL;
320
321 return snd_soc_put_volsw(kcontrol, ucontrol);
322}
323
9e6e96a1
MB		 324static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
325{
b2c812e2 326 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 327 struct wm8994_pdata *pdata = wm8994->pdata;
328 int base = wm8994_drc_base[drc];
329 int cfg = wm8994->drc_cfg[drc];
330 int save, i;
331
332 /* Save any enables; the configuration should clear them. */
333 save = snd_soc_read(codec, base);
334 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
335 WM8994_AIF1ADC1R_DRC_ENA;
336
337 for (i = 0; i < WM8994_DRC_REGS; i++)
338 snd_soc_update_bits(codec, base + i, 0xffff,
339 pdata->drc_cfgs[cfg].regs[i]);
340
341 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
342 WM8994_AIF1ADC1L_DRC_ENA |
343 WM8994_AIF1ADC1R_DRC_ENA, save);
344}
345
346/* Icky as hell but saves code duplication */
347static int wm8994_get_drc(const char *name)
348{
349 if (strcmp(name, "AIF1DRC1 Mode") == 0)
350 return 0;
351 if (strcmp(name, "AIF1DRC2 Mode") == 0)
352 return 1;
353 if (strcmp(name, "AIF2DRC Mode") == 0)
354 return 2;
355 return -EINVAL;
356}
357
358static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
359 struct snd_ctl_elem_value *ucontrol)
360{
361 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 362 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 363 struct wm8994_pdata *pdata = wm8994->pdata;
364 int drc = wm8994_get_drc(kcontrol->id.name);
365 int value = ucontrol->value.integer.value[0];
366
367 if (drc < 0)
368 return drc;
369
370 if (value >= pdata->num_drc_cfgs)
371 return -EINVAL;
372
373 wm8994->drc_cfg[drc] = value;
374
375 wm8994_set_drc(codec, drc);
376
377 return 0;
378}
379
380static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
381 struct snd_ctl_elem_value *ucontrol)
382{
383 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 384 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 385 int drc = wm8994_get_drc(kcontrol->id.name);
386
387 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
388
389 return 0;
390}
391
392static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
393{
b2c812e2 394 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 395 struct wm8994_pdata *pdata = wm8994->pdata;
396 int base = wm8994_retune_mobile_base[block];
397 int iface, best, best_val, save, i, cfg;
398
399 if (!pdata || !wm8994->num_retune_mobile_texts)
400 return;
401
402 switch (block) {
403 case 0:
404 case 1:
405 iface = 0;
406 break;
407 case 2:
408 iface = 1;
409 break;
410 default:
411 return;
412 }
413
414 /* Find the version of the currently selected configuration
415 * with the nearest sample rate. */
416 cfg = wm8994->retune_mobile_cfg[block];
417 best = 0;
418 best_val = INT_MAX;
419 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
420 if (strcmp(pdata->retune_mobile_cfgs[i].name,
421 wm8994->retune_mobile_texts[cfg]) == 0 &&
422 abs(pdata->retune_mobile_cfgs[i].rate
423 - wm8994->dac_rates[iface]) < best_val) {
424 best = i;
425 best_val = abs(pdata->retune_mobile_cfgs[i].rate
426 - wm8994->dac_rates[iface]);
427 }
428 }
429
430 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
431 block,
432 pdata->retune_mobile_cfgs[best].name,
433 pdata->retune_mobile_cfgs[best].rate,
434 wm8994->dac_rates[iface]);
435
436 /* The EQ will be disabled while reconfiguring it, remember the
437 * current configuration.
438 */
439 save = snd_soc_read(codec, base);
440 save &= WM8994_AIF1DAC1_EQ_ENA;
441
442 for (i = 0; i < WM8994_EQ_REGS; i++)
443 snd_soc_update_bits(codec, base + i, 0xffff,
444 pdata->retune_mobile_cfgs[best].regs[i]);
445
446 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
447}
448
449/* Icky as hell but saves code duplication */
450static int wm8994_get_retune_mobile_block(const char *name)
451{
452 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
453 return 0;
454 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
455 return 1;
456 if (strcmp(name, "AIF2 EQ Mode") == 0)
457 return 2;
458 return -EINVAL;
459}
460
461static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
462 struct snd_ctl_elem_value *ucontrol)
463{
464 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 465 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 466 struct wm8994_pdata *pdata = wm8994->pdata;
467 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
468 int value = ucontrol->value.integer.value[0];
469
470 if (block < 0)
471 return block;
472
473 if (value >= pdata->num_retune_mobile_cfgs)
474 return -EINVAL;
475
476 wm8994->retune_mobile_cfg[block] = value;
477
478 wm8994_set_retune_mobile(codec, block);
479
480 return 0;
481}
482
483static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
484 struct snd_ctl_elem_value *ucontrol)
485{
486 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 487 struct wm8994_priv *wm8994 =snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 488 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
489
490 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
491
492 return 0;
493}
494
96b101ef 495static const char *aif_chan_src_text[] = {
f554885f
MB		 496 "Left", "Right"
497};
498
96b101ef
MB		 499static const struct soc_enum aif1adcl_src =
500 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
501
502static const struct soc_enum aif1adcr_src =
503 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
504
505static const struct soc_enum aif2adcl_src =
506 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
507
508static const struct soc_enum aif2adcr_src =
509 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
510
f554885f 511static const struct soc_enum aif1dacl_src =
96b101ef 512 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 513
514static const struct soc_enum aif1dacr_src =
96b101ef 515 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f
MB		 516
517static const struct soc_enum aif2dacl_src =
96b101ef 518 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 519
520static const struct soc_enum aif2dacr_src =
96b101ef 521 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f 522
9e6e96a1
MB		 523static const struct snd_kcontrol_new wm8994_snd_controls[] = {
524SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
525 WM8994_AIF1_ADC1_RIGHT_VOLUME,
526 1, 119, 0, digital_tlv),
527SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
528 WM8994_AIF1_ADC2_RIGHT_VOLUME,
529 1, 119, 0, digital_tlv),
530SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
531 WM8994_AIF2_ADC_RIGHT_VOLUME,
532 1, 119, 0, digital_tlv),
533
96b101ef
MB		 534SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
535SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
536SOC_ENUM("AIF2ADCL Source", aif1adcl_src),
537SOC_ENUM("AIF2ADCR Source", aif1adcr_src),
538
f554885f
MB		 539SOC_ENUM("AIF1DACL Source", aif1dacl_src),
540SOC_ENUM("AIF1DACR Source", aif1dacr_src),
541SOC_ENUM("AIF2DACL Source", aif1dacl_src),
542SOC_ENUM("AIF2DACR Source", aif1dacr_src),
543
9e6e96a1
MB		 544SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
545 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
546SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
547 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
548SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
549 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
550
551SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
552SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
553
554SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
555SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
556SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
557
558WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
559WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
560WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
561
562WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
563WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
564WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
565
566WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
567WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
568WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
569
570SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
571 5, 12, 0, st_tlv),
572SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
573 0, 12, 0, st_tlv),
574SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
575 5, 12, 0, st_tlv),
576SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
577 0, 12, 0, st_tlv),
578SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
579SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
580
581SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
582 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
583SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
584 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
585
586SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
587 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
588SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
589 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
590
591SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
592 6, 1, 1, wm_hubs_spkmix_tlv),
593SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
594 2, 1, 1, wm_hubs_spkmix_tlv),
595
596SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
597 6, 1, 1, wm_hubs_spkmix_tlv),
598SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
599 2, 1, 1, wm_hubs_spkmix_tlv),
600
601SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
602 10, 15, 0, wm8994_3d_tlv),
603SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
604 8, 1, 0),
605SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
606 10, 15, 0, wm8994_3d_tlv),
607SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
608 8, 1, 0),
609SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
610 10, 15, 0, wm8994_3d_tlv),
611SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
612 8, 1, 0),
613};
614
615static const struct snd_kcontrol_new wm8994_eq_controls[] = {
616SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
617 eq_tlv),
618SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
619 eq_tlv),
620SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
621 eq_tlv),
622SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
623 eq_tlv),
624SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
625 eq_tlv),
626
627SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
628 eq_tlv),
629SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
630 eq_tlv),
631SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
632 eq_tlv),
633SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
634 eq_tlv),
635SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
636 eq_tlv),
637
638SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
639 eq_tlv),
640SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
641 eq_tlv),
642SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
643 eq_tlv),
644SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
645 eq_tlv),
646SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
647 eq_tlv),
648};
649
650static int clk_sys_event(struct snd_soc_dapm_widget *w,
651 struct snd_kcontrol *kcontrol, int event)
652{
653 struct snd_soc_codec *codec = w->codec;
654
655 switch (event) {
656 case SND_SOC_DAPM_PRE_PMU:
657 return configure_clock(codec);
658
659 case SND_SOC_DAPM_POST_PMD:
660 configure_clock(codec);
661 break;
662 }
663
664 return 0;
665}
666
667static void wm8994_update_class_w(struct snd_soc_codec *codec)
668{
fec6dd83 669 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 670 int enable = 1;
671 int source = 0; /* GCC flow analysis can't track enable */
672 int reg, reg_r;
673
674 /* Only support direct DAC->headphone paths */
675 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
676 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
ee839a21 677 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
9e6e96a1
MB		 678 enable = 0;
679 }
680
681 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
682 if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
ee839a21 683 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
9e6e96a1
MB		 684 enable = 0;
685 }
686
687 /* We also need the same setting for L/R and only one path */
688 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
689 switch (reg) {
690 case WM8994_AIF2DACL_TO_DAC1L:
ee839a21 691 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
9e6e96a1
MB		 692 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
693 break;
694 case WM8994_AIF1DAC2L_TO_DAC1L:
ee839a21 695 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
9e6e96a1
MB		 696 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
697 break;
698 case WM8994_AIF1DAC1L_TO_DAC1L:
ee839a21 699 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
9e6e96a1
MB		 700 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
701 break;
702 default:
ee839a21 703 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
9e6e96a1
MB		 704 enable = 0;
705 break;
706 }
707
708 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
709 if (reg_r != reg) {
ee839a21 710 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
9e6e96a1
MB		 711 enable = 0;
712 }
713
714 if (enable) {
715 dev_dbg(codec->dev, "Class W enabled\n");
716 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
717 WM8994_CP_DYN_PWR |
718 WM8994_CP_DYN_SRC_SEL_MASK,
719 source | WM8994_CP_DYN_PWR);
fec6dd83 720 wm8994->hubs.class_w = true;
9e6e96a1
MB		 721
722 } else {
723 dev_dbg(codec->dev, "Class W disabled\n");
724 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
725 WM8994_CP_DYN_PWR, 0);
fec6dd83 726 wm8994->hubs.class_w = false;
9e6e96a1
MB		 727 }
728}
729
730static const char *hp_mux_text[] = {
731 "Mixer",
732 "DAC",
733};
734
735#define WM8994_HP_ENUM(xname, xenum) \
736{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
737 .info = snd_soc_info_enum_double, \
738 .get = snd_soc_dapm_get_enum_double, \
739 .put = wm8994_put_hp_enum, \
740 .private_value = (unsigned long)&xenum }
741
742static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
743 struct snd_ctl_elem_value *ucontrol)
744{
745 struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
746 struct snd_soc_codec *codec = w->codec;
747 int ret;
748
749 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
750
751 wm8994_update_class_w(codec);
752
753 return ret;
754}
755
756static const struct soc_enum hpl_enum =
757 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
758
759static const struct snd_kcontrol_new hpl_mux =
760 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
761
762static const struct soc_enum hpr_enum =
763 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
764
765static const struct snd_kcontrol_new hpr_mux =
766 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
767
768static const char *adc_mux_text[] = {
769 "ADC",
770 "DMIC",
771};
772
773static const struct soc_enum adc_enum =
774 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
775
776static const struct snd_kcontrol_new adcl_mux =
777 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
778
779static const struct snd_kcontrol_new adcr_mux =
780 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
781
782static const struct snd_kcontrol_new left_speaker_mixer[] = {
783SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
784SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
785SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
786SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
787SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
788};
789
790static const struct snd_kcontrol_new right_speaker_mixer[] = {
791SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
792SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
793SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
794SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
795SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
796};
797
798/* Debugging; dump chip status after DAPM transitions */
799static int post_ev(struct snd_soc_dapm_widget *w,
800 struct snd_kcontrol *kcontrol, int event)
801{
802 struct snd_soc_codec *codec = w->codec;
803 dev_dbg(codec->dev, "SRC status: %x\n",
804 snd_soc_read(codec,
805 WM8994_RATE_STATUS));
806 return 0;
807}
808
809static const struct snd_kcontrol_new aif1adc1l_mix[] = {
810SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
811 1, 1, 0),
812SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
813 0, 1, 0),
814};
815
816static const struct snd_kcontrol_new aif1adc1r_mix[] = {
817SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
818 1, 1, 0),
819SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
820 0, 1, 0),
821};
822
a3257ba8
MB		 823static const struct snd_kcontrol_new aif1adc2l_mix[] = {
824SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
825 1, 1, 0),
826SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
827 0, 1, 0),
828};
829
830static const struct snd_kcontrol_new aif1adc2r_mix[] = {
831SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
832 1, 1, 0),
833SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
834 0, 1, 0),
835};
836
9e6e96a1
MB		 837static const struct snd_kcontrol_new aif2dac2l_mix[] = {
838SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
839 5, 1, 0),
840SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
841 4, 1, 0),
842SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
843 2, 1, 0),
844SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
845 1, 1, 0),
846SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
847 0, 1, 0),
848};
849
850static const struct snd_kcontrol_new aif2dac2r_mix[] = {
851SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
852 5, 1, 0),
853SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
854 4, 1, 0),
855SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
856 2, 1, 0),
857SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
858 1, 1, 0),
859SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
860 0, 1, 0),
861};
862
863#define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
864{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
865 .info = snd_soc_info_volsw, \
866 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
867 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
868
869static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
870 struct snd_ctl_elem_value *ucontrol)
871{
872 struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
873 struct snd_soc_codec *codec = w->codec;
874 int ret;
875
876 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
877
878 wm8994_update_class_w(codec);
879
880 return ret;
881}
882
883static const struct snd_kcontrol_new dac1l_mix[] = {
884WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
885 5, 1, 0),
886WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
887 4, 1, 0),
888WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
889 2, 1, 0),
890WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
891 1, 1, 0),
892WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
893 0, 1, 0),
894};
895
896static const struct snd_kcontrol_new dac1r_mix[] = {
897WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
898 5, 1, 0),
899WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
900 4, 1, 0),
901WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
902 2, 1, 0),
903WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
904 1, 1, 0),
905WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
906 0, 1, 0),
907};
908
909static const char *sidetone_text[] = {
910 "ADC/DMIC1", "DMIC2",
911};
912
913static const struct soc_enum sidetone1_enum =
914 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
915
916static const struct snd_kcontrol_new sidetone1_mux =
917 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
918
919static const struct soc_enum sidetone2_enum =
920 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
921
922static const struct snd_kcontrol_new sidetone2_mux =
923 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
924
925static const char *aif1dac_text[] = {
926 "AIF1DACDAT", "AIF3DACDAT",
927};
928
929static const struct soc_enum aif1dac_enum =
930 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
931
932static const struct snd_kcontrol_new aif1dac_mux =
933 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
934
935static const char *aif2dac_text[] = {
936 "AIF2DACDAT", "AIF3DACDAT",
937};
938
939static const struct soc_enum aif2dac_enum =
940 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
941
942static const struct snd_kcontrol_new aif2dac_mux =
943 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
944
945static const char *aif2adc_text[] = {
946 "AIF2ADCDAT", "AIF3DACDAT",
947};
948
949static const struct soc_enum aif2adc_enum =
950 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
951
952static const struct snd_kcontrol_new aif2adc_mux =
953 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
954
955static const char *aif3adc_text[] = {
956 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT",
957};
958
959static const struct soc_enum aif3adc_enum =
960 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
961
962static const struct snd_kcontrol_new aif3adc_mux =
963 SOC_DAPM_ENUM("AIF3ADC Mux", aif3adc_enum);
964
965static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
966SND_SOC_DAPM_INPUT("DMIC1DAT"),
967SND_SOC_DAPM_INPUT("DMIC2DAT"),
66b47fdb 968SND_SOC_DAPM_INPUT("Clock"),
9e6e96a1
MB		 969
970SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
971 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
972
973SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
974SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
975SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
976
977SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
978SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
979
980SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture",
981 0, WM8994_POWER_MANAGEMENT_4, 9, 0),
982SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture",
983 0, WM8994_POWER_MANAGEMENT_4, 8, 0),
984SND_SOC_DAPM_AIF_IN("AIF1DAC1L", NULL, 0,
985 WM8994_POWER_MANAGEMENT_5, 9, 0),
986SND_SOC_DAPM_AIF_IN("AIF1DAC1R", NULL, 0,
987 WM8994_POWER_MANAGEMENT_5, 8, 0),
988
989SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture",
990 0, WM8994_POWER_MANAGEMENT_4, 11, 0),
991SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture",
992 0, WM8994_POWER_MANAGEMENT_4, 10, 0),
993SND_SOC_DAPM_AIF_IN("AIF1DAC2L", NULL, 0,
994 WM8994_POWER_MANAGEMENT_5, 11, 0),
995SND_SOC_DAPM_AIF_IN("AIF1DAC2R", NULL, 0,
996 WM8994_POWER_MANAGEMENT_5, 10, 0),
997
998SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
999 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1000SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1001 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1002
a3257ba8
MB		 1003SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1004 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1005SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1006 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1007
9e6e96a1
MB		 1008SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1009 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1010SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1011 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1012
1013SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1014SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1015
1016SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1017 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1018SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1019 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1020
1021SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1022 WM8994_POWER_MANAGEMENT_4, 13, 0),
1023SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1024 WM8994_POWER_MANAGEMENT_4, 12, 0),
1025SND_SOC_DAPM_AIF_IN("AIF2DACL", NULL, 0,
1026 WM8994_POWER_MANAGEMENT_5, 13, 0),
1027SND_SOC_DAPM_AIF_IN("AIF2DACR", NULL, 0,
1028 WM8994_POWER_MANAGEMENT_5, 12, 0),
1029
1030SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1031SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1032SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1033
1034SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1035SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1036SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1037SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &aif3adc_mux),
1038
1039SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1040SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1041
1042SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1043
1044SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1045SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1046SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1047SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1048
1049/* Power is done with the muxes since the ADC power also controls the
1050 * downsampling chain, the chip will automatically manage the analogue
1051 * specific portions.
1052 */
1053SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1054SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1055
1056SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1057SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1058
1059SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1060SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1061SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1062SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1063
1064SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1065SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1066
1067SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1068 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1069SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1070 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1071
1072SND_SOC_DAPM_POST("Debug log", post_ev),
1073};
1074
1075static const struct snd_soc_dapm_route intercon[] = {
1076
1077 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1078 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1079
1080 { "DSP1CLK", NULL, "CLK_SYS" },
1081 { "DSP2CLK", NULL, "CLK_SYS" },
1082 { "DSPINTCLK", NULL, "CLK_SYS" },
1083
1084 { "AIF1ADC1L", NULL, "AIF1CLK" },
1085 { "AIF1ADC1L", NULL, "DSP1CLK" },
1086 { "AIF1ADC1R", NULL, "AIF1CLK" },
1087 { "AIF1ADC1R", NULL, "DSP1CLK" },
1088 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1089
1090 { "AIF1DAC1L", NULL, "AIF1CLK" },
1091 { "AIF1DAC1L", NULL, "DSP1CLK" },
1092 { "AIF1DAC1R", NULL, "AIF1CLK" },
1093 { "AIF1DAC1R", NULL, "DSP1CLK" },
1094 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1095
1096 { "AIF1ADC2L", NULL, "AIF1CLK" },
1097 { "AIF1ADC2L", NULL, "DSP1CLK" },
1098 { "AIF1ADC2R", NULL, "AIF1CLK" },
1099 { "AIF1ADC2R", NULL, "DSP1CLK" },
1100 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1101
1102 { "AIF1DAC2L", NULL, "AIF1CLK" },
1103 { "AIF1DAC2L", NULL, "DSP1CLK" },
1104 { "AIF1DAC2R", NULL, "AIF1CLK" },
1105 { "AIF1DAC2R", NULL, "DSP1CLK" },
1106 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1107
1108 { "AIF2ADCL", NULL, "AIF2CLK" },
1109 { "AIF2ADCL", NULL, "DSP2CLK" },
1110 { "AIF2ADCR", NULL, "AIF2CLK" },
1111 { "AIF2ADCR", NULL, "DSP2CLK" },
1112 { "AIF2ADCR", NULL, "DSPINTCLK" },
1113
1114 { "AIF2DACL", NULL, "AIF2CLK" },
1115 { "AIF2DACL", NULL, "DSP2CLK" },
1116 { "AIF2DACR", NULL, "AIF2CLK" },
1117 { "AIF2DACR", NULL, "DSP2CLK" },
1118 { "AIF2DACR", NULL, "DSPINTCLK" },
1119
1120 { "DMIC1L", NULL, "DMIC1DAT" },
1121 { "DMIC1L", NULL, "CLK_SYS" },
1122 { "DMIC1R", NULL, "DMIC1DAT" },
1123 { "DMIC1R", NULL, "CLK_SYS" },
1124 { "DMIC2L", NULL, "DMIC2DAT" },
1125 { "DMIC2L", NULL, "CLK_SYS" },
1126 { "DMIC2R", NULL, "DMIC2DAT" },
1127 { "DMIC2R", NULL, "CLK_SYS" },
1128
1129 { "ADCL", NULL, "AIF1CLK" },
1130 { "ADCL", NULL, "DSP1CLK" },
1131 { "ADCL", NULL, "DSPINTCLK" },
1132
1133 { "ADCR", NULL, "AIF1CLK" },
1134 { "ADCR", NULL, "DSP1CLK" },
1135 { "ADCR", NULL, "DSPINTCLK" },
1136
1137 { "ADCL Mux", "ADC", "ADCL" },
1138 { "ADCL Mux", "DMIC", "DMIC1L" },
1139 { "ADCR Mux", "ADC", "ADCR" },
1140 { "ADCR Mux", "DMIC", "DMIC1R" },
1141
1142 { "DAC1L", NULL, "AIF1CLK" },
1143 { "DAC1L", NULL, "DSP1CLK" },
1144 { "DAC1L", NULL, "DSPINTCLK" },
1145
1146 { "DAC1R", NULL, "AIF1CLK" },
1147 { "DAC1R", NULL, "DSP1CLK" },
1148 { "DAC1R", NULL, "DSPINTCLK" },
1149
1150 { "DAC2L", NULL, "AIF2CLK" },
1151 { "DAC2L", NULL, "DSP2CLK" },
1152 { "DAC2L", NULL, "DSPINTCLK" },
1153
1154 { "DAC2R", NULL, "AIF2DACR" },
1155 { "DAC2R", NULL, "AIF2CLK" },
1156 { "DAC2R", NULL, "DSP2CLK" },
1157 { "DAC2R", NULL, "DSPINTCLK" },
1158
1159 { "TOCLK", NULL, "CLK_SYS" },
1160
1161 /* AIF1 outputs */
1162 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1163 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1164 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1165
1166 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1167 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1168 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1169
a3257ba8
MB		 1170 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1171 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1172 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1173
1174 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1175 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1176 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1177
9e6e96a1
MB		 1178 /* Pin level routing for AIF3 */
1179 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1180 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1181 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1182 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1183
1184 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1185 { "AIF2DACR", NULL, "AIF2DAC Mux" },
1186
1187 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1188 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1189 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1190 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1191 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1192 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1193 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1194
1195 /* DAC1 inputs */
1196 { "DAC1L", NULL, "DAC1L Mixer" },
1197 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1198 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1199 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1200 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1201 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1202
1203 { "DAC1R", NULL, "DAC1R Mixer" },
1204 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1205 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1206 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1207 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1208 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1209
1210 /* DAC2/AIF2 outputs */
1211 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1212 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1213 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1214 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1215 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1216 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1217 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1218
1219 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1220 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1221 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1222 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1223 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1224 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1225 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1226
1227 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1228
1229 /* AIF3 output */
1230 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1231 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1232 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1233 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1234 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1235 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1236 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1237 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1238
1239 /* Sidetone */
1240 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1241 { "Left Sidetone", "DMIC2", "DMIC2L" },
1242 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1243 { "Right Sidetone", "DMIC2", "DMIC2R" },
1244
1245 /* Output stages */
1246 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1247 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1248
1249 { "SPKL", "DAC1 Switch", "DAC1L" },
1250 { "SPKL", "DAC2 Switch", "DAC2L" },
1251
1252 { "SPKR", "DAC1 Switch", "DAC1R" },
1253 { "SPKR", "DAC2 Switch", "DAC2R" },
1254
1255 { "Left Headphone Mux", "DAC", "DAC1L" },
1256 { "Right Headphone Mux", "DAC", "DAC1R" },
1257};
1258
1259/* The size in bits of the FLL divide multiplied by 10
1260 * to allow rounding later */
1261#define FIXED_FLL_SIZE ((1 << 16) * 10)
1262
1263struct fll_div {
1264 u16 outdiv;
1265 u16 n;
1266 u16 k;
1267 u16 clk_ref_div;
1268 u16 fll_fratio;
1269};
1270
1271static int wm8994_get_fll_config(struct fll_div *fll,
1272 int freq_in, int freq_out)
1273{
1274 u64 Kpart;
1275 unsigned int K, Ndiv, Nmod;
1276
1277 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1278
1279 /* Scale the input frequency down to <= 13.5MHz */
1280 fll->clk_ref_div = 0;
1281 while (freq_in > 13500000) {
1282 fll->clk_ref_div++;
1283 freq_in /= 2;
1284
1285 if (fll->clk_ref_div > 3)
1286 return -EINVAL;
1287 }
1288 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1289
1290 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1291 fll->outdiv = 3;
1292 while (freq_out * (fll->outdiv + 1) < 90000000) {
1293 fll->outdiv++;
1294 if (fll->outdiv > 63)
1295 return -EINVAL;
1296 }
1297 freq_out *= fll->outdiv + 1;
1298 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1299
1300 if (freq_in > 1000000) {
1301 fll->fll_fratio = 0;
7d48a6ac
MB		 1302 } else if (freq_in > 256000) {
1303 fll->fll_fratio = 1;
1304 freq_in *= 2;
1305 } else if (freq_in > 128000) {
1306 fll->fll_fratio = 2;
1307 freq_in *= 4;
1308 } else if (freq_in > 64000) {
9e6e96a1
MB		 1309 fll->fll_fratio = 3;
1310 freq_in *= 8;
7d48a6ac
MB		 1311 } else {
1312 fll->fll_fratio = 4;
1313 freq_in *= 16;
9e6e96a1
MB		 1314 }
1315 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1316
1317 /* Now, calculate N.K */
1318 Ndiv = freq_out / freq_in;
1319
1320 fll->n = Ndiv;
1321 Nmod = freq_out % freq_in;
1322 pr_debug("Nmod=%d\n", Nmod);
1323
1324 /* Calculate fractional part - scale up so we can round. */
1325 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1326
1327 do_div(Kpart, freq_in);
1328
1329 K = Kpart & 0xFFFFFFFF;
1330
1331 if ((K % 10) >= 5)
1332 K += 5;
1333
1334 /* Move down to proper range now rounding is done */
1335 fll->k = K / 10;
1336
1337 pr_debug("N=%x K=%x\n", fll->n, fll->k);
1338
1339 return 0;
1340}
1341
f0fba2ad 1342static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
9e6e96a1
MB		 1343 unsigned int freq_in, unsigned int freq_out)
1344{
b2c812e2 1345 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 1346 int reg_offset, ret;
1347 struct fll_div fll;
1348 u16 reg, aif1, aif2;
1349
1350 aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1351 & WM8994_AIF1CLK_ENA;
1352
1353 aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1354 & WM8994_AIF2CLK_ENA;
1355
1356 switch (id) {
1357 case WM8994_FLL1:
1358 reg_offset = 0;
1359 id = 0;
1360 break;
1361 case WM8994_FLL2:
1362 reg_offset = 0x20;
1363 id = 1;
1364 break;
1365 default:
1366 return -EINVAL;
1367 }
1368
136ff2a2 1369 switch (src) {
7add84aa
MB		 1370 case 0:
1371 /* Allow no source specification when stopping */
1372 if (freq_out)
1373 return -EINVAL;
1374 break;
136ff2a2
MB		 1375 case WM8994_FLL_SRC_MCLK1:
1376 case WM8994_FLL_SRC_MCLK2:
1377 case WM8994_FLL_SRC_LRCLK:
1378 case WM8994_FLL_SRC_BCLK:
1379 break;
1380 default:
1381 return -EINVAL;
1382 }
1383
9e6e96a1
MB		 1384 /* Are we changing anything? */
1385 if (wm8994->fll[id].src == src &&
1386 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1387 return 0;
1388
1389 /* If we're stopping the FLL redo the old config - no
1390 * registers will actually be written but we avoid GCC flow
1391 * analysis bugs spewing warnings.
1392 */
1393 if (freq_out)
1394 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1395 else
1396 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1397 wm8994->fll[id].out);
1398 if (ret < 0)
1399 return ret;
1400
1401 /* Gate the AIF clocks while we reclock */
1402 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1403 WM8994_AIF1CLK_ENA, 0);
1404 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1405 WM8994_AIF2CLK_ENA, 0);
1406
1407 /* We always need to disable the FLL while reconfiguring */
1408 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1409 WM8994_FLL1_ENA, 0);
1410
1411 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1412 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1413 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1414 WM8994_FLL1_OUTDIV_MASK |
1415 WM8994_FLL1_FRATIO_MASK, reg);
1416
1417 snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1418
1419 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1420 WM8994_FLL1_N_MASK,
1421 fll.n << WM8994_FLL1_N_SHIFT);
1422
1423 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
136ff2a2
MB		 1424 WM8994_FLL1_REFCLK_DIV_MASK |
1425 WM8994_FLL1_REFCLK_SRC_MASK,
1426 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1427 (src - 1));
9e6e96a1
MB		 1428
1429 /* Enable (with fractional mode if required) */
1430 if (freq_out) {
1431 if (fll.k)
1432 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1433 else
1434 reg = WM8994_FLL1_ENA;
1435 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1436 WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1437 reg);
1438 }
1439
1440 wm8994->fll[id].in = freq_in;
1441 wm8994->fll[id].out = freq_out;
136ff2a2 1442 wm8994->fll[id].src = src;
9e6e96a1
MB		 1443
1444 /* Enable any gated AIF clocks */
1445 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1446 WM8994_AIF1CLK_ENA, aif1);
1447 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1448 WM8994_AIF2CLK_ENA, aif2);
1449
1450 configure_clock(codec);
1451
1452 return 0;
1453}
1454
f0fba2ad 1455
66b47fdb
MB		 1456static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1457
f0fba2ad
LG		 1458static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
1459 unsigned int freq_in, unsigned int freq_out)
1460{
1461 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
1462}
1463
9e6e96a1
MB		 1464static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
1465 int clk_id, unsigned int freq, int dir)
1466{
1467 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1468 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
66b47fdb 1469 int i;
9e6e96a1
MB		 1470
1471 switch (dai->id) {
1472 case 1:
1473 case 2:
1474 break;
1475
1476 default:
1477 /* AIF3 shares clocking with AIF1/2 */
1478 return -EINVAL;
1479 }
1480
1481 switch (clk_id) {
1482 case WM8994_SYSCLK_MCLK1:
1483 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
1484 wm8994->mclk[0] = freq;
1485 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
1486 dai->id, freq);
1487 break;
1488
1489 case WM8994_SYSCLK_MCLK2:
1490 /* TODO: Set GPIO AF */
1491 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
1492 wm8994->mclk[1] = freq;
1493 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
1494 dai->id, freq);
1495 break;
1496
1497 case WM8994_SYSCLK_FLL1:
1498 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
1499 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
1500 break;
1501
1502 case WM8994_SYSCLK_FLL2:
1503 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
1504 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
1505 break;
1506
66b47fdb
MB		 1507 case WM8994_SYSCLK_OPCLK:
1508 /* Special case - a division (times 10) is given and
1509 * no effect on main clocking.
1510 */
1511 if (freq) {
1512 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
1513 if (opclk_divs[i] == freq)
1514 break;
1515 if (i == ARRAY_SIZE(opclk_divs))
1516 return -EINVAL;
1517 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
1518 WM8994_OPCLK_DIV_MASK, i);
1519 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1520 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
1521 } else {
1522 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1523 WM8994_OPCLK_ENA, 0);
1524 }
1525
9e6e96a1
MB		 1526 default:
1527 return -EINVAL;
1528 }
1529
1530 configure_clock(codec);
1531
1532 return 0;
1533}
1534
1535static int wm8994_set_bias_level(struct snd_soc_codec *codec,
1536 enum snd_soc_bias_level level)
1537{
b6b05691
MB		 1538 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1539
9e6e96a1
MB		 1540 switch (level) {
1541 case SND_SOC_BIAS_ON:
1542 break;
1543
1544 case SND_SOC_BIAS_PREPARE:
1545 /* VMID=2x40k */
1546 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1547 WM8994_VMID_SEL_MASK, 0x2);
1548 break;
1549
1550 case SND_SOC_BIAS_STANDBY:
ce6120cc 1551 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
0c17b393
MB		 1552 /* Tweak DC servo and DSP configuration for
1553 * improved performance. */
b6b05691
MB		 1554 if (wm8994->revision < 4) {
1555 /* Tweak DC servo and DSP configuration for
1556 * improved performance. */
1557 snd_soc_write(codec, 0x102, 0x3);
1558 snd_soc_write(codec, 0x56, 0x3);
1559 snd_soc_write(codec, 0x817, 0);
1560 snd_soc_write(codec, 0x102, 0);
1561 }
9e6e96a1
MB		 1562
1563 /* Discharge LINEOUT1 & 2 */
1564 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
1565 WM8994_LINEOUT1_DISCH |
1566 WM8994_LINEOUT2_DISCH,
1567 WM8994_LINEOUT1_DISCH |
1568 WM8994_LINEOUT2_DISCH);
1569
1570 /* Startup bias, VMID ramp & buffer */
1571 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1572 WM8994_STARTUP_BIAS_ENA |
1573 WM8994_VMID_BUF_ENA |
1574 WM8994_VMID_RAMP_MASK,
1575 WM8994_STARTUP_BIAS_ENA |
1576 WM8994_VMID_BUF_ENA |
1577 (0x11 << WM8994_VMID_RAMP_SHIFT));
1578
1579 /* Main bias enable, VMID=2x40k */
1580 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1581 WM8994_BIAS_ENA |
1582 WM8994_VMID_SEL_MASK,
1583 WM8994_BIAS_ENA | 0x2);
1584
1585 msleep(20);
1586 }
1587
1588 /* VMID=2x500k */
1589 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1590 WM8994_VMID_SEL_MASK, 0x4);
1591
1592 break;
1593
1594 case SND_SOC_BIAS_OFF:
ce6120cc 1595 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
d522ffbf
MB		 1596 /* Switch over to startup biases */
1597 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1598 WM8994_BIAS_SRC |
1599 WM8994_STARTUP_BIAS_ENA |
1600 WM8994_VMID_BUF_ENA |
1601 WM8994_VMID_RAMP_MASK,
1602 WM8994_BIAS_SRC |
1603 WM8994_STARTUP_BIAS_ENA |
1604 WM8994_VMID_BUF_ENA |
1605 (1 << WM8994_VMID_RAMP_SHIFT));
9e6e96a1 1606
d522ffbf
MB		 1607 /* Disable main biases */
1608 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1609 WM8994_BIAS_ENA |
1610 WM8994_VMID_SEL_MASK, 0);
9e6e96a1 1611
d522ffbf
MB		 1612 /* Discharge line */
1613 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
1614 WM8994_LINEOUT1_DISCH |
1615 WM8994_LINEOUT2_DISCH,
1616 WM8994_LINEOUT1_DISCH |
1617 WM8994_LINEOUT2_DISCH);
9e6e96a1 1618
d522ffbf 1619 msleep(5);
9e6e96a1 1620
d522ffbf
MB		 1621 /* Switch off startup biases */
1622 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1623 WM8994_BIAS_SRC |
1624 WM8994_STARTUP_BIAS_ENA |
1625 WM8994_VMID_BUF_ENA |
1626 WM8994_VMID_RAMP_MASK, 0);
1627 }
9e6e96a1
MB		 1628 break;
1629 }
ce6120cc 1630 codec->dapm.bias_level = level;
9e6e96a1
MB		 1631 return 0;
1632}
1633
1634static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1635{
1636 struct snd_soc_codec *codec = dai->codec;
1637 int ms_reg;
1638 int aif1_reg;
1639 int ms = 0;
1640 int aif1 = 0;
1641
1642 switch (dai->id) {
1643 case 1:
1644 ms_reg = WM8994_AIF1_MASTER_SLAVE;
1645 aif1_reg = WM8994_AIF1_CONTROL_1;
1646 break;
1647 case 2:
1648 ms_reg = WM8994_AIF2_MASTER_SLAVE;
1649 aif1_reg = WM8994_AIF2_CONTROL_1;
1650 break;
1651 default:
1652 return -EINVAL;
1653 }
1654
1655 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1656 case SND_SOC_DAIFMT_CBS_CFS:
1657 break;
1658 case SND_SOC_DAIFMT_CBM_CFM:
1659 ms = WM8994_AIF1_MSTR;
1660 break;
1661 default:
1662 return -EINVAL;
1663 }
1664
1665 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1666 case SND_SOC_DAIFMT_DSP_B:
1667 aif1 |= WM8994_AIF1_LRCLK_INV;
1668 case SND_SOC_DAIFMT_DSP_A:
1669 aif1 |= 0x18;
1670 break;
1671 case SND_SOC_DAIFMT_I2S:
1672 aif1 |= 0x10;
1673 break;
1674 case SND_SOC_DAIFMT_RIGHT_J:
1675 break;
1676 case SND_SOC_DAIFMT_LEFT_J:
1677 aif1 |= 0x8;
1678 break;
1679 default:
1680 return -EINVAL;
1681 }
1682
1683 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1684 case SND_SOC_DAIFMT_DSP_A:
1685 case SND_SOC_DAIFMT_DSP_B:
1686 /* frame inversion not valid for DSP modes */
1687 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1688 case SND_SOC_DAIFMT_NB_NF:
1689 break;
1690 case SND_SOC_DAIFMT_IB_NF:
1691 aif1 |= WM8994_AIF1_BCLK_INV;
1692 break;
1693 default:
1694 return -EINVAL;
1695 }
1696 break;
1697
1698 case SND_SOC_DAIFMT_I2S:
1699 case SND_SOC_DAIFMT_RIGHT_J:
1700 case SND_SOC_DAIFMT_LEFT_J:
1701 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1702 case SND_SOC_DAIFMT_NB_NF:
1703 break;
1704 case SND_SOC_DAIFMT_IB_IF:
1705 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
1706 break;
1707 case SND_SOC_DAIFMT_IB_NF:
1708 aif1 |= WM8994_AIF1_BCLK_INV;
1709 break;
1710 case SND_SOC_DAIFMT_NB_IF:
1711 aif1 |= WM8994_AIF1_LRCLK_INV;
1712 break;
1713 default:
1714 return -EINVAL;
1715 }
1716 break;
1717 default:
1718 return -EINVAL;
1719 }
1720
1721 snd_soc_update_bits(codec, aif1_reg,
1722 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
1723 WM8994_AIF1_FMT_MASK,
1724 aif1);
1725 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
1726 ms);
1727
1728 return 0;
1729}
1730
1731static struct {
1732 int val, rate;
1733} srs[] = {
1734 { 0, 8000 },
1735 { 1, 11025 },
1736 { 2, 12000 },
1737 { 3, 16000 },
1738 { 4, 22050 },
1739 { 5, 24000 },
1740 { 6, 32000 },
1741 { 7, 44100 },
1742 { 8, 48000 },
1743 { 9, 88200 },
1744 { 10, 96000 },
1745};
1746
1747static int fs_ratios[] = {
1748 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
1749};
1750
1751static int bclk_divs[] = {
1752 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
1753 640, 880, 960, 1280, 1760, 1920
1754};
1755
1756static int wm8994_hw_params(struct snd_pcm_substream *substream,
1757 struct snd_pcm_hw_params *params,
1758 struct snd_soc_dai *dai)
1759{
1760 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1761 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 1762 int aif1_reg;
1763 int bclk_reg;
1764 int lrclk_reg;
1765 int rate_reg;
1766 int aif1 = 0;
1767 int bclk = 0;
1768 int lrclk = 0;
1769 int rate_val = 0;
1770 int id = dai->id - 1;
1771
1772 int i, cur_val, best_val, bclk_rate, best;
1773
1774 switch (dai->id) {
1775 case 1:
1776 aif1_reg = WM8994_AIF1_CONTROL_1;
1777 bclk_reg = WM8994_AIF1_BCLK;
1778 rate_reg = WM8994_AIF1_RATE;
1779 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 1780 wm8994->lrclk_shared[0]) {
9e6e96a1 1781 lrclk_reg = WM8994_AIF1DAC_LRCLK;
7d83d213 1782 } else {
9e6e96a1 1783 lrclk_reg = WM8994_AIF1ADC_LRCLK;
7d83d213
MB		 1784 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
1785 }
9e6e96a1
MB		 1786 break;
1787 case 2:
1788 aif1_reg = WM8994_AIF2_CONTROL_1;
1789 bclk_reg = WM8994_AIF2_BCLK;
1790 rate_reg = WM8994_AIF2_RATE;
1791 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 1792 wm8994->lrclk_shared[1]) {
9e6e96a1 1793 lrclk_reg = WM8994_AIF2DAC_LRCLK;
7d83d213 1794 } else {
9e6e96a1 1795 lrclk_reg = WM8994_AIF2ADC_LRCLK;
7d83d213
MB		 1796 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
1797 }
9e6e96a1
MB		 1798 break;
1799 default:
1800 return -EINVAL;
1801 }
1802
1803 bclk_rate = params_rate(params) * 2;
1804 switch (params_format(params)) {
1805 case SNDRV_PCM_FORMAT_S16_LE:
1806 bclk_rate *= 16;
1807 break;
1808 case SNDRV_PCM_FORMAT_S20_3LE:
1809 bclk_rate *= 20;
1810 aif1 |= 0x20;
1811 break;
1812 case SNDRV_PCM_FORMAT_S24_LE:
1813 bclk_rate *= 24;
1814 aif1 |= 0x40;
1815 break;
1816 case SNDRV_PCM_FORMAT_S32_LE:
1817 bclk_rate *= 32;
1818 aif1 |= 0x60;
1819 break;
1820 default:
1821 return -EINVAL;
1822 }
1823
1824 /* Try to find an appropriate sample rate; look for an exact match. */
1825 for (i = 0; i < ARRAY_SIZE(srs); i++)
1826 if (srs[i].rate == params_rate(params))
1827 break;
1828 if (i == ARRAY_SIZE(srs))
1829 return -EINVAL;
1830 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
1831
1832 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
1833 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
1834 dai->id, wm8994->aifclk[id], bclk_rate);
1835
1836 if (wm8994->aifclk[id] == 0) {
1837 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
1838 return -EINVAL;
1839 }
1840
1841 /* AIFCLK/fs ratio; look for a close match in either direction */
1842 best = 0;
1843 best_val = abs((fs_ratios[0] * params_rate(params))
1844 - wm8994->aifclk[id]);
1845 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
1846 cur_val = abs((fs_ratios[i] * params_rate(params))
1847 - wm8994->aifclk[id]);
1848 if (cur_val >= best_val)
1849 continue;
1850 best = i;
1851 best_val = cur_val;
1852 }
1853 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
1854 dai->id, fs_ratios[best]);
1855 rate_val |= best;
1856
1857 /* We may not get quite the right frequency if using
1858 * approximate clocks so look for the closest match that is
1859 * higher than the target (we need to ensure that there enough
1860 * BCLKs to clock out the samples).
1861 */
1862 best = 0;
1863 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
07cd8ada 1864 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
9e6e96a1
MB		 1865 if (cur_val < 0) /* BCLK table is sorted */
1866 break;
1867 best = i;
1868 }
07cd8ada 1869 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
9e6e96a1
MB		 1870 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
1871 bclk_divs[best], bclk_rate);
1872 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
1873
1874 lrclk = bclk_rate / params_rate(params);
1875 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
1876 lrclk, bclk_rate / lrclk);
1877
1878 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
1879 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
1880 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
1881 lrclk);
1882 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
1883 WM8994_AIF1CLK_RATE_MASK, rate_val);
1884
1885 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1886 switch (dai->id) {
1887 case 1:
1888 wm8994->dac_rates[0] = params_rate(params);
1889 wm8994_set_retune_mobile(codec, 0);
1890 wm8994_set_retune_mobile(codec, 1);
1891 break;
1892 case 2:
1893 wm8994->dac_rates[1] = params_rate(params);
1894 wm8994_set_retune_mobile(codec, 2);
1895 break;
1896 }
1897 }
1898
1899 return 0;
1900}
1901
1902static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
1903{
1904 struct snd_soc_codec *codec = codec_dai->codec;
1905 int mute_reg;
1906 int reg;
1907
1908 switch (codec_dai->id) {
1909 case 1:
1910 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
1911 break;
1912 case 2:
1913 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
1914 break;
1915 default:
1916 return -EINVAL;
1917 }
1918
1919 if (mute)
1920 reg = WM8994_AIF1DAC1_MUTE;
1921 else
1922 reg = 0;
1923
1924 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
1925
1926 return 0;
1927}
1928
778a76e2
MB		 1929static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
1930{
1931 struct snd_soc_codec *codec = codec_dai->codec;
1932 int reg, val, mask;
1933
1934 switch (codec_dai->id) {
1935 case 1:
1936 reg = WM8994_AIF1_MASTER_SLAVE;
1937 mask = WM8994_AIF1_TRI;
1938 break;
1939 case 2:
1940 reg = WM8994_AIF2_MASTER_SLAVE;
1941 mask = WM8994_AIF2_TRI;
1942 break;
1943 case 3:
1944 reg = WM8994_POWER_MANAGEMENT_6;
1945 mask = WM8994_AIF3_TRI;
1946 break;
1947 default:
1948 return -EINVAL;
1949 }
1950
1951 if (tristate)
1952 val = mask;
1953 else
1954 val = 0;
1955
1956 return snd_soc_update_bits(codec, reg, mask, reg);
1957}
1958
9e6e96a1
MB		 1959#define WM8994_RATES SNDRV_PCM_RATE_8000_96000
1960
1961#define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3079aed5 1962 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
9e6e96a1
MB		 1963
1964static struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
1965 .set_sysclk = wm8994_set_dai_sysclk,
1966 .set_fmt = wm8994_set_dai_fmt,
1967 .hw_params = wm8994_hw_params,
1968 .digital_mute = wm8994_aif_mute,
1969 .set_pll = wm8994_set_fll,
778a76e2 1970 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 1971};
1972
1973static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
1974 .set_sysclk = wm8994_set_dai_sysclk,
1975 .set_fmt = wm8994_set_dai_fmt,
1976 .hw_params = wm8994_hw_params,
1977 .digital_mute = wm8994_aif_mute,
1978 .set_pll = wm8994_set_fll,
778a76e2
MB		 1979 .set_tristate = wm8994_set_tristate,
1980};
1981
1982static struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
1983 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 1984};
1985
f0fba2ad 1986static struct snd_soc_dai_driver wm8994_dai[] = {
9e6e96a1 1987 {
f0fba2ad 1988 .name = "wm8994-aif1",
8c7f78b3 1989 .id = 1,
9e6e96a1
MB		 1990 .playback = {
1991 .stream_name = "AIF1 Playback",
1992 .channels_min = 2,
1993 .channels_max = 2,
1994 .rates = WM8994_RATES,
1995 .formats = WM8994_FORMATS,
1996 },
1997 .capture = {
1998 .stream_name = "AIF1 Capture",
1999 .channels_min = 2,
2000 .channels_max = 2,
2001 .rates = WM8994_RATES,
2002 .formats = WM8994_FORMATS,
2003 },
2004 .ops = &wm8994_aif1_dai_ops,
2005 },
2006 {
f0fba2ad 2007 .name = "wm8994-aif2",
8c7f78b3 2008 .id = 2,
9e6e96a1
MB		 2009 .playback = {
2010 .stream_name = "AIF2 Playback",
2011 .channels_min = 2,
2012 .channels_max = 2,
2013 .rates = WM8994_RATES,
2014 .formats = WM8994_FORMATS,
2015 },
2016 .capture = {
2017 .stream_name = "AIF2 Capture",
2018 .channels_min = 2,
2019 .channels_max = 2,
2020 .rates = WM8994_RATES,
2021 .formats = WM8994_FORMATS,
2022 },
2023 .ops = &wm8994_aif2_dai_ops,
2024 },
2025 {
f0fba2ad 2026 .name = "wm8994-aif3",
8c7f78b3 2027 .id = 3,
9e6e96a1
MB		 2028 .playback = {
2029 .stream_name = "AIF3 Playback",
2030 .channels_min = 2,
2031 .channels_max = 2,
2032 .rates = WM8994_RATES,
2033 .formats = WM8994_FORMATS,
2034 },
a8462bde 2035 .capture = {
9e6e96a1
MB		 2036 .stream_name = "AIF3 Capture",
2037 .channels_min = 2,
2038 .channels_max = 2,
2039 .rates = WM8994_RATES,
2040 .formats = WM8994_FORMATS,
2041 },
778a76e2 2042 .ops = &wm8994_aif3_dai_ops,
9e6e96a1
MB		 2043 }
2044};
9e6e96a1
MB		 2045
2046#ifdef CONFIG_PM
f0fba2ad 2047static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state)
9e6e96a1 2048{
b2c812e2 2049 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 2050 int i, ret;
2051
2052 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2053 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2054 sizeof(struct fll_config));
f0fba2ad 2055 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
9e6e96a1
MB		 2056 if (ret < 0)
2057 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2058 i + 1, ret);
2059 }
2060
2061 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2062
2063 return 0;
2064}
2065
f0fba2ad 2066static int wm8994_resume(struct snd_soc_codec *codec)
9e6e96a1 2067{
b2c812e2 2068 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 2069 u16 *reg_cache = codec->reg_cache;
2070 int i, ret;
2071
2072 /* Restore the registers */
2073 for (i = 1; i < ARRAY_SIZE(wm8994->reg_cache); i++) {
2074 switch (i) {
2075 case WM8994_LDO_1:
2076 case WM8994_LDO_2:
2077 case WM8994_SOFTWARE_RESET:
2078 /* Handled by other MFD drivers */
2079 continue;
2080 default:
2081 break;
2082 }
2083
7b306dae 2084 if (!wm8994_access_masks[i].writable)
9e6e96a1
MB		 2085 continue;
2086
2087 wm8994_reg_write(codec->control_data, i, reg_cache[i]);
2088 }
2089
2090 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2091
2092 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
6a2f1ee1
MB		 2093 if (!wm8994->fll_suspend[i].out)
2094 continue;
2095
f0fba2ad 2096 ret = _wm8994_set_fll(codec, i + 1,
9e6e96a1
MB		 2097 wm8994->fll_suspend[i].src,
2098 wm8994->fll_suspend[i].in,
2099 wm8994->fll_suspend[i].out);
2100 if (ret < 0)
2101 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2102 i + 1, ret);
2103 }
2104
2105 return 0;
2106}
2107#else
2108#define wm8994_suspend NULL
2109#define wm8994_resume NULL
2110#endif
2111
2112static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2113{
f0fba2ad 2114 struct snd_soc_codec *codec = wm8994->codec;
9e6e96a1
MB		 2115 struct wm8994_pdata *pdata = wm8994->pdata;
2116 struct snd_kcontrol_new controls[] = {
2117 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2118 wm8994->retune_mobile_enum,
2119 wm8994_get_retune_mobile_enum,
2120 wm8994_put_retune_mobile_enum),
2121 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2122 wm8994->retune_mobile_enum,
2123 wm8994_get_retune_mobile_enum,
2124 wm8994_put_retune_mobile_enum),
2125 SOC_ENUM_EXT("AIF2 EQ Mode",
2126 wm8994->retune_mobile_enum,
2127 wm8994_get_retune_mobile_enum,
2128 wm8994_put_retune_mobile_enum),
2129 };
2130 int ret, i, j;
2131 const char **t;
2132
2133 /* We need an array of texts for the enum API but the number
2134 * of texts is likely to be less than the number of
2135 * configurations due to the sample rate dependency of the
2136 * configurations. */
2137 wm8994->num_retune_mobile_texts = 0;
2138 wm8994->retune_mobile_texts = NULL;
2139 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2140 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2141 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2142 wm8994->retune_mobile_texts[j]) == 0)
2143 break;
2144 }
2145
2146 if (j != wm8994->num_retune_mobile_texts)
2147 continue;
2148
2149 /* Expand the array... */
2150 t = krealloc(wm8994->retune_mobile_texts,
2151 sizeof(char *) *
2152 (wm8994->num_retune_mobile_texts + 1),
2153 GFP_KERNEL);
2154 if (t == NULL)
2155 continue;
2156
2157 /* ...store the new entry... */
2158 t[wm8994->num_retune_mobile_texts] =
2159 pdata->retune_mobile_cfgs[i].name;
2160
2161 /* ...and remember the new version. */
2162 wm8994->num_retune_mobile_texts++;
2163 wm8994->retune_mobile_texts = t;
2164 }
2165
2166 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2167 wm8994->num_retune_mobile_texts);
2168
2169 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2170 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2171
f0fba2ad 2172 ret = snd_soc_add_controls(wm8994->codec, controls,
9e6e96a1
MB		 2173 ARRAY_SIZE(controls));
2174 if (ret != 0)
f0fba2ad 2175 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2176 "Failed to add ReTune Mobile controls: %d\n", ret);
2177}
2178
2179static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2180{
f0fba2ad 2181 struct snd_soc_codec *codec = wm8994->codec;
9e6e96a1
MB		 2182 struct wm8994_pdata *pdata = wm8994->pdata;
2183 int ret, i;
2184
2185 if (!pdata)
2186 return;
2187
2188 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2189 pdata->lineout2_diff,
2190 pdata->lineout1fb,
2191 pdata->lineout2fb,
2192 pdata->jd_scthr,
2193 pdata->jd_thr,
2194 pdata->micbias1_lvl,
2195 pdata->micbias2_lvl);
2196
2197 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2198
2199 if (pdata->num_drc_cfgs) {
2200 struct snd_kcontrol_new controls[] = {
2201 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2202 wm8994_get_drc_enum, wm8994_put_drc_enum),
2203 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2204 wm8994_get_drc_enum, wm8994_put_drc_enum),
2205 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2206 wm8994_get_drc_enum, wm8994_put_drc_enum),
2207 };
2208
2209 /* We need an array of texts for the enum API */
2210 wm8994->drc_texts = kmalloc(sizeof(char *)
2211 * pdata->num_drc_cfgs, GFP_KERNEL);
2212 if (!wm8994->drc_texts) {
f0fba2ad 2213 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2214 "Failed to allocate %d DRC config texts\n",
2215 pdata->num_drc_cfgs);
2216 return;
2217 }
2218
2219 for (i = 0; i < pdata->num_drc_cfgs; i++)
2220 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2221
2222 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2223 wm8994->drc_enum.texts = wm8994->drc_texts;
2224
f0fba2ad 2225 ret = snd_soc_add_controls(wm8994->codec, controls,
9e6e96a1
MB		 2226 ARRAY_SIZE(controls));
2227 if (ret != 0)
f0fba2ad 2228 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2229 "Failed to add DRC mode controls: %d\n", ret);
2230
2231 for (i = 0; i < WM8994_NUM_DRC; i++)
2232 wm8994_set_drc(codec, i);
2233 }
2234
2235 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2236 pdata->num_retune_mobile_cfgs);
2237
2238 if (pdata->num_retune_mobile_cfgs)
2239 wm8994_handle_retune_mobile_pdata(wm8994);
2240 else
f0fba2ad 2241 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
9e6e96a1
MB		 2242 ARRAY_SIZE(wm8994_eq_controls));
2243}
2244
88766984
MB		 2245/**
2246 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2247 *
2248 * @codec: WM8994 codec
2249 * @jack: jack to report detection events on
2250 * @micbias: microphone bias to detect on
2251 * @det: value to report for presence detection
2252 * @shrt: value to report for short detection
2253 *
2254 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
2255 * being used to bring out signals to the processor then only platform
5ab230a7 2256 * data configuration is needed for WM8994 and processor GPIOs should
88766984
MB		 2257 * be configured using snd_soc_jack_add_gpios() instead.
2258 *
2259 * Configuration of detection levels is available via the micbias1_lvl
2260 * and micbias2_lvl platform data members.
2261 */
2262int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2263 int micbias, int det, int shrt)
2264{
b2c812e2 2265 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
88766984
MB		 2266 struct wm8994_micdet *micdet;
2267 int reg;
2268
2269 switch (micbias) {
2270 case 1:
2271 micdet = &wm8994->micdet[0];
2272 break;
2273 case 2:
2274 micdet = &wm8994->micdet[1];
2275 break;
2276 default:
2277 return -EINVAL;
2278 }
2279
2280 dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
2281 micbias, det, shrt);
2282
2283 /* Store the configuration */
2284 micdet->jack = jack;
2285 micdet->det = det;
2286 micdet->shrt = shrt;
2287
2288 /* If either of the jacks is set up then enable detection */
2289 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2290 reg = WM8994_MICD_ENA;
2291 else
2292 reg = 0;
2293
2294 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
2295
2296 return 0;
2297}
2298EXPORT_SYMBOL_GPL(wm8994_mic_detect);
2299
2300static irqreturn_t wm8994_mic_irq(int irq, void *data)
2301{
2302 struct wm8994_priv *priv = data;
f0fba2ad 2303 struct snd_soc_codec *codec = priv->codec;
88766984
MB		 2304 int reg;
2305 int report;
2306
2307 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
2308 if (reg < 0) {
2309 dev_err(codec->dev, "Failed to read microphone status: %d\n",
2310 reg);
2311 return IRQ_HANDLED;
2312 }
2313
2314 dev_dbg(codec->dev, "Microphone status: %x\n", reg);
2315
2316 report = 0;
2317 if (reg & WM8994_MIC1_DET_STS)
2318 report |= priv->micdet[0].det;
2319 if (reg & WM8994_MIC1_SHRT_STS)
2320 report |= priv->micdet[0].shrt;
2321 snd_soc_jack_report(priv->micdet[0].jack, report,
2322 priv->micdet[0].det | priv->micdet[0].shrt);
2323
2324 report = 0;
2325 if (reg & WM8994_MIC2_DET_STS)
2326 report |= priv->micdet[1].det;
2327 if (reg & WM8994_MIC2_SHRT_STS)
2328 report |= priv->micdet[1].shrt;
2329 snd_soc_jack_report(priv->micdet[1].jack, report,
2330 priv->micdet[1].det | priv->micdet[1].shrt);
2331
2332 return IRQ_HANDLED;
2333}
2334
f0fba2ad 2335static int wm8994_codec_probe(struct snd_soc_codec *codec)
9e6e96a1 2336{
9e6e96a1 2337 struct wm8994_priv *wm8994;
ce6120cc 2338 struct snd_soc_dapm_context *dapm = &codec->dapm;
ec62dbd7 2339 int ret, i;
9e6e96a1 2340
f0fba2ad 2341 codec->control_data = dev_get_drvdata(codec->dev->parent);
9e6e96a1
MB		 2342
2343 wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
f0fba2ad 2344 if (wm8994 == NULL)
9e6e96a1 2345 return -ENOMEM;
b2c812e2 2346 snd_soc_codec_set_drvdata(codec, wm8994);
f0fba2ad 2347
11e713a0
MB		 2348 codec->reg_cache = &wm8994->reg_cache;
2349
f0fba2ad
LG		 2350 wm8994->pdata = dev_get_platdata(codec->dev->parent);
2351 wm8994->codec = codec;
9e6e96a1
MB		 2352
2353 /* Fill the cache with physical values we inherited; don't reset */
2354 ret = wm8994_bulk_read(codec->control_data, 0,
2355 ARRAY_SIZE(wm8994->reg_cache) - 1,
2356 codec->reg_cache);
2357 if (ret < 0) {
2358 dev_err(codec->dev, "Failed to fill register cache: %d\n",
2359 ret);
2360 goto err;
2361 }
2362
2363 /* Clear the cached values for unreadable/volatile registers to
2364 * avoid potential confusion.
2365 */
2366 for (i = 0; i < ARRAY_SIZE(wm8994->reg_cache); i++)
2367 if (wm8994_volatile(i) || !wm8994_readable(i))
2368 wm8994->reg_cache[i] = 0;
2369
2370 /* Set revision-specific configuration */
b6b05691
MB		 2371 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
2372 switch (wm8994->revision) {
9e6e96a1
MB		 2373 case 2:
2374 case 3:
2375 wm8994->hubs.dcs_codes = -5;
2376 wm8994->hubs.hp_startup_mode = 1;
8437f700 2377 wm8994->hubs.dcs_readback_mode = 1;
9e6e96a1
MB		 2378 break;
2379 default:
8437f700 2380 wm8994->hubs.dcs_readback_mode = 1;
9e6e96a1
MB		 2381 break;
2382 }
9e6e96a1 2383
88766984
MB		 2384 ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
2385 wm8994_mic_irq, "Mic 1 detect", wm8994);
2386 if (ret != 0)
f0fba2ad 2387 dev_warn(codec->dev,
88766984
MB		 2388 "Failed to request Mic1 detect IRQ: %d\n", ret);
2389
2390 ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT,
2391 wm8994_mic_irq, "Mic 1 short", wm8994);
2392 if (ret != 0)
f0fba2ad 2393 dev_warn(codec->dev,
88766984
MB		 2394 "Failed to request Mic1 short IRQ: %d\n", ret);
2395
2396 ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC2_DET,
2397 wm8994_mic_irq, "Mic 2 detect", wm8994);
2398 if (ret != 0)
f0fba2ad 2399 dev_warn(codec->dev,
88766984
MB		 2400 "Failed to request Mic2 detect IRQ: %d\n", ret);
2401
2402 ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT,
2403 wm8994_mic_irq, "Mic 2 short", wm8994);
2404 if (ret != 0)
f0fba2ad 2405 dev_warn(codec->dev,
88766984
MB		 2406 "Failed to request Mic2 short IRQ: %d\n", ret);
2407
9e6e96a1
MB		 2408 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
2409 * configured on init - if a system wants to do this dynamically
2410 * at runtime we can deal with that then.
2411 */
2412 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1);
2413 if (ret < 0) {
2414 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
88766984 2415 goto err_irq;
9e6e96a1
MB		 2416 }
2417 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
2418 wm8994->lrclk_shared[0] = 1;
2419 wm8994_dai[0].symmetric_rates = 1;
2420 } else {
2421 wm8994->lrclk_shared[0] = 0;
2422 }
2423
2424 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6);
2425 if (ret < 0) {
2426 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
88766984 2427 goto err_irq;
9e6e96a1
MB		 2428 }
2429 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
2430 wm8994->lrclk_shared[1] = 1;
2431 wm8994_dai[1].symmetric_rates = 1;
2432 } else {
2433 wm8994->lrclk_shared[1] = 0;
2434 }
2435
9e6e96a1
MB		 2436 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2437
9e6e96a1
MB		 2438 /* Latch volume updates (right only; we always do left then right). */
2439 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
2440 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
2441 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
2442 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
2443 snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
2444 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
2445 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
2446 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
2447 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
2448 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
2449 snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
2450 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
2451 snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
2452 WM8994_DAC1_VU, WM8994_DAC1_VU);
2453 snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
2454 WM8994_DAC2_VU, WM8994_DAC2_VU);
2455
2456 /* Set the low bit of the 3D stereo depth so TLV matches */
2457 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
2458 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
2459 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
2460 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
2461 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
2462 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
2463 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
2464 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
2465 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
2466
d1ce6b20
MB		 2467 /* Unconditionally enable AIF1 ADC TDM mode; it only affects
2468 * behaviour on idle TDM clock cycles. */
2469 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
2470 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
2471
9e6e96a1
MB		 2472 wm8994_update_class_w(codec);
2473
f0fba2ad 2474 wm8994_handle_pdata(wm8994);
9e6e96a1 2475
f0fba2ad
LG		 2476 wm_hubs_add_analogue_controls(codec);
2477 snd_soc_add_controls(codec, wm8994_snd_controls,
2478 ARRAY_SIZE(wm8994_snd_controls));
ce6120cc 2479 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
f0fba2ad
LG		 2480 ARRAY_SIZE(wm8994_dapm_widgets));
2481 wm_hubs_add_analogue_routes(codec, 0, 0);
ce6120cc 2482 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
9e6e96a1
MB		 2483
2484 return 0;
2485
88766984
MB		 2486err_irq:
2487 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
2488 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
2489 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
2490 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, wm8994);
9e6e96a1
MB		 2491err:
2492 kfree(wm8994);
2493 return ret;
2494}
2495
f0fba2ad 2496static int wm8994_codec_remove(struct snd_soc_codec *codec)
9e6e96a1 2497{
f0fba2ad 2498 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 2499
2500 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
f0fba2ad 2501
88766984
MB		 2502 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
2503 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
2504 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
2505 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, wm8994);
24fb2b11
AL		 2506 kfree(wm8994->retune_mobile_texts);
2507 kfree(wm8994->drc_texts);
9e6e96a1 2508 kfree(wm8994);
9e6e96a1
MB		 2509
2510 return 0;
2511}
2512
f0fba2ad
LG		 2513static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
2514 .probe = wm8994_codec_probe,
2515 .remove = wm8994_codec_remove,
2516 .suspend = wm8994_suspend,
2517 .resume = wm8994_resume,
2518 .read = wm8994_read,
2519 .write = wm8994_write,
eba19fdd
MB		 2520 .readable_register = wm8994_readable,
2521 .volatile_register = wm8994_volatile,
f0fba2ad
LG		 2522 .set_bias_level = wm8994_set_bias_level,
2523};
2524
2525static int __devinit wm8994_probe(struct platform_device *pdev)
2526{
2527 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
2528 wm8994_dai, ARRAY_SIZE(wm8994_dai));
2529}
2530
2531static int __devexit wm8994_remove(struct platform_device *pdev)
2532{
2533 snd_soc_unregister_codec(&pdev->dev);
2534 return 0;
2535}
2536
9e6e96a1
MB		 2537static struct platform_driver wm8994_codec_driver = {
2538 .driver = {
2539 .name = "wm8994-codec",
2540 .owner = THIS_MODULE,
2541 },
f0fba2ad
LG		 2542 .probe = wm8994_probe,
2543 .remove = __devexit_p(wm8994_remove),
9e6e96a1
MB		 2544};
2545
2546static __init int wm8994_init(void)
2547{
2548 return platform_driver_register(&wm8994_codec_driver);
2549}
2550module_init(wm8994_init);
2551
2552static __exit void wm8994_exit(void)
2553{
2554 platform_driver_unregister(&wm8994_codec_driver);
2555}
2556module_exit(wm8994_exit);
2557
2558
2559MODULE_DESCRIPTION("ASoC WM8994 driver");
2560MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2561MODULE_LICENSE("GPL");
2562MODULE_ALIAS("platform:wm8994-codec");
Linux kernel - Deliverables
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