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ASoC: Drop unused state parameter from CODEC suspend callback
[deliverable/linux.git] / sound / soc / codecs / wm8994.c
CommitLineData
9e6e96a1
MB		 1/*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
39fb51a1 21#include <linux/pm_runtime.h>
9e6e96a1 22#include <linux/regulator/consumer.h>
5a0e3ad6 23#include <linux/slab.h>
9e6e96a1 24#include <sound/core.h>
821edd2f 25#include <sound/jack.h>
9e6e96a1
MB		 26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
9e6e96a1
MB		 29#include <sound/initval.h>
30#include <sound/tlv.h>
2bbb5d66 31#include <trace/events/asoc.h>
9e6e96a1
MB		 32
33#include <linux/mfd/wm8994/core.h>
34#include <linux/mfd/wm8994/registers.h>
35#include <linux/mfd/wm8994/pdata.h>
36#include <linux/mfd/wm8994/gpio.h>
37
38#include "wm8994.h"
39#include "wm_hubs.h"
40
af6b6fe4
MB		 41#define WM1811_JACKDET_MODE_NONE 0x0000
42#define WM1811_JACKDET_MODE_JACK 0x0100
43#define WM1811_JACKDET_MODE_MIC 0x0080
44#define WM1811_JACKDET_MODE_AUDIO 0x0180
45
9e6e96a1
MB		 46#define WM8994_NUM_DRC 3
47#define WM8994_NUM_EQ 3
48
49static int wm8994_drc_base[] = {
50 WM8994_AIF1_DRC1_1,
51 WM8994_AIF1_DRC2_1,
52 WM8994_AIF2_DRC_1,
53};
54
55static int wm8994_retune_mobile_base[] = {
56 WM8994_AIF1_DAC1_EQ_GAINS_1,
57 WM8994_AIF1_DAC2_EQ_GAINS_1,
58 WM8994_AIF2_EQ_GAINS_1,
59};
60
b00adf76
MB		 61static void wm8958_default_micdet(u16 status, void *data);
62
af6b6fe4 63static const struct wm8958_micd_rate micdet_rates[] = {
b00adf76
MB		 64 { 32768, true, 1, 4 },
65 { 32768, false, 1, 1 },
604533de
MB		 66 { 44100 * 256, true, 7, 10 },
67 { 44100 * 256, false, 7, 10 },
b00adf76
MB		 68};
69
af6b6fe4
MB		 70static const struct wm8958_micd_rate jackdet_rates[] = {
71 { 32768, true, 0, 1 },
72 { 32768, false, 0, 1 },
73 { 44100 * 256, true, 7, 10 },
74 { 44100 * 256, false, 7, 10 },
75};
76
b00adf76
MB		 77static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
78{
79 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
80 int best, i, sysclk, val;
81 bool idle;
af6b6fe4
MB		 82 const struct wm8958_micd_rate *rates;
83 int num_rates;
b00adf76
MB		 84
85 if (wm8994->jack_cb != wm8958_default_micdet)
86 return;
87
88 idle = !wm8994->jack_mic;
89
90 sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
91 if (sysclk & WM8994_SYSCLK_SRC)
92 sysclk = wm8994->aifclk[1];
93 else
94 sysclk = wm8994->aifclk[0];
95
cd1707a9
MB		 96 if (wm8994->pdata && wm8994->pdata->micd_rates) {
97 rates = wm8994->pdata->micd_rates;
98 num_rates = wm8994->pdata->num_micd_rates;
99 } else if (wm8994->jackdet) {
af6b6fe4
MB		 100 rates = jackdet_rates;
101 num_rates = ARRAY_SIZE(jackdet_rates);
102 } else {
103 rates = micdet_rates;
104 num_rates = ARRAY_SIZE(micdet_rates);
105 }
106
b00adf76 107 best = 0;
af6b6fe4
MB		 108 for (i = 0; i < num_rates; i++) {
109 if (rates[i].idle != idle)
b00adf76 110 continue;
af6b6fe4
MB		 111 if (abs(rates[i].sysclk - sysclk) <
112 abs(rates[best].sysclk - sysclk))
b00adf76 113 best = i;
af6b6fe4 114 else if (rates[best].idle != idle)
b00adf76
MB		 115 best = i;
116 }
117
af6b6fe4
MB		 118 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
119 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
b00adf76
MB		 120
121 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
122 WM8958_MICD_BIAS_STARTTIME_MASK |
123 WM8958_MICD_RATE_MASK, val);
124}
125
d4754ec9 126static int wm8994_readable(struct snd_soc_codec *codec, unsigned int reg)
9e6e96a1 127{
af9af866 128 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 129 struct wm8994 *control = wm8994->wm8994;
af9af866 130
e88ff1e6
MB		 131 switch (reg) {
132 case WM8994_GPIO_1:
133 case WM8994_GPIO_2:
134 case WM8994_GPIO_3:
135 case WM8994_GPIO_4:
136 case WM8994_GPIO_5:
137 case WM8994_GPIO_6:
138 case WM8994_GPIO_7:
139 case WM8994_GPIO_8:
140 case WM8994_GPIO_9:
141 case WM8994_GPIO_10:
142 case WM8994_GPIO_11:
143 case WM8994_INTERRUPT_STATUS_1:
144 case WM8994_INTERRUPT_STATUS_2:
145 case WM8994_INTERRUPT_RAW_STATUS_2:
146 return 1;
af9af866
MB		 147
148 case WM8958_DSP2_PROGRAM:
149 case WM8958_DSP2_CONFIG:
150 case WM8958_DSP2_EXECCONTROL:
151 if (control->type == WM8958)
152 return 1;
153 else
154 return 0;
155
e88ff1e6
MB		 156 default:
157 break;
158 }
159
7b306dae 160 if (reg >= WM8994_CACHE_SIZE)
9e6e96a1 161 return 0;
7b306dae 162 return wm8994_access_masks[reg].readable != 0;
9e6e96a1
MB		 163}
164
d4754ec9 165static int wm8994_volatile(struct snd_soc_codec *codec, unsigned int reg)
9e6e96a1 166{
ca9aef50 167 if (reg >= WM8994_CACHE_SIZE)
9e6e96a1
MB		 168 return 1;
169
170 switch (reg) {
171 case WM8994_SOFTWARE_RESET:
172 case WM8994_CHIP_REVISION:
173 case WM8994_DC_SERVO_1:
174 case WM8994_DC_SERVO_READBACK:
175 case WM8994_RATE_STATUS:
176 case WM8994_LDO_1:
177 case WM8994_LDO_2:
d6addcc9 178 case WM8958_DSP2_EXECCONTROL:
821edd2f 179 case WM8958_MIC_DETECT_3:
79ef0abc 180 case WM8994_DC_SERVO_4E:
9e6e96a1
MB		 181 return 1;
182 default:
183 return 0;
184 }
185}
186
187static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
188 unsigned int value)
189{
ca9aef50 190 int ret;
9e6e96a1
MB		 191
192 BUG_ON(reg > WM8994_MAX_REGISTER);
193
d4754ec9 194 if (!wm8994_volatile(codec, reg)) {
ca9aef50
MB		 195 ret = snd_soc_cache_write(codec, reg, value);
196 if (ret != 0)
197 dev_err(codec->dev, "Cache write to %x failed: %d\n",
198 reg, ret);
199 }
9e6e96a1
MB		 200
201 return wm8994_reg_write(codec->control_data, reg, value);
202}
203
204static unsigned int wm8994_read(struct snd_soc_codec *codec,
205 unsigned int reg)
206{
ca9aef50
MB		 207 unsigned int val;
208 int ret;
9e6e96a1
MB		 209
210 BUG_ON(reg > WM8994_MAX_REGISTER);
211
d4754ec9 212 if (!wm8994_volatile(codec, reg) && wm8994_readable(codec, reg) &&
ca9aef50
MB		 213 reg < codec->driver->reg_cache_size) {
214 ret = snd_soc_cache_read(codec, reg, &val);
215 if (ret >= 0)
216 return val;
217 else
218 dev_err(codec->dev, "Cache read from %x failed: %d\n",
219 reg, ret);
220 }
221
222 return wm8994_reg_read(codec->control_data, reg);
9e6e96a1
MB		 223}
224
225static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
226{
b2c812e2 227 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 228 int rate;
229 int reg1 = 0;
230 int offset;
231
232 if (aif)
233 offset = 4;
234 else
235 offset = 0;
236
237 switch (wm8994->sysclk[aif]) {
238 case WM8994_SYSCLK_MCLK1:
239 rate = wm8994->mclk[0];
240 break;
241
242 case WM8994_SYSCLK_MCLK2:
243 reg1 |= 0x8;
244 rate = wm8994->mclk[1];
245 break;
246
247 case WM8994_SYSCLK_FLL1:
248 reg1 |= 0x10;
249 rate = wm8994->fll[0].out;
250 break;
251
252 case WM8994_SYSCLK_FLL2:
253 reg1 |= 0x18;
254 rate = wm8994->fll[1].out;
255 break;
256
257 default:
258 return -EINVAL;
259 }
260
261 if (rate >= 13500000) {
262 rate /= 2;
263 reg1 |= WM8994_AIF1CLK_DIV;
264
265 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
266 aif + 1, rate);
267 }
5e5e2bef 268
9e6e96a1
MB		 269 wm8994->aifclk[aif] = rate;
270
271 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
272 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
273 reg1);
274
275 return 0;
276}
277
278static int configure_clock(struct snd_soc_codec *codec)
279{
b2c812e2 280 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
04f45c49 281 int change, new;
9e6e96a1
MB		 282
283 /* Bring up the AIF clocks first */
284 configure_aif_clock(codec, 0);
285 configure_aif_clock(codec, 1);
286
287 /* Then switch CLK_SYS over to the higher of them; a change
288 * can only happen as a result of a clocking change which can
289 * only be made outside of DAPM so we can safely redo the
290 * clocking.
291 */
292
293 /* If they're equal it doesn't matter which is used */
b00adf76
MB		 294 if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
295 wm8958_micd_set_rate(codec);
9e6e96a1 296 return 0;
b00adf76 297 }
9e6e96a1
MB		 298
299 if (wm8994->aifclk[0] < wm8994->aifclk[1])
300 new = WM8994_SYSCLK_SRC;
301 else
302 new = 0;
303
04f45c49
AL		 304 change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
305 WM8994_SYSCLK_SRC, new);
52ac7ab2
MB		 306 if (change)
307 snd_soc_dapm_sync(&codec->dapm);
9e6e96a1 308
b00adf76
MB		 309 wm8958_micd_set_rate(codec);
310
9e6e96a1
MB		 311 return 0;
312}
313
314static int check_clk_sys(struct snd_soc_dapm_widget *source,
315 struct snd_soc_dapm_widget *sink)
316{
317 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
318 const char *clk;
319
320 /* Check what we're currently using for CLK_SYS */
321 if (reg & WM8994_SYSCLK_SRC)
322 clk = "AIF2CLK";
323 else
324 clk = "AIF1CLK";
325
326 return strcmp(source->name, clk) == 0;
327}
328
329static const char *sidetone_hpf_text[] = {
330 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
331};
332
333static const struct soc_enum sidetone_hpf =
334 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
335
146fd574
UK		 336static const char *adc_hpf_text[] = {
337 "HiFi", "Voice 1", "Voice 2", "Voice 3"
338};
339
340static const struct soc_enum aif1adc1_hpf =
341 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
342
343static const struct soc_enum aif1adc2_hpf =
344 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
345
346static const struct soc_enum aif2adc_hpf =
347 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
348
9e6e96a1
MB		 349static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
350static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
351static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
352static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
353static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
1ddc07d0 354static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
81204c84 355static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
9e6e96a1
MB		 356
357#define WM8994_DRC_SWITCH(xname, reg, shift) \
358{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
359 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
360 .put = wm8994_put_drc_sw, \
361 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
362
363static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
364 struct snd_ctl_elem_value *ucontrol)
365{
366 struct soc_mixer_control *mc =
367 (struct soc_mixer_control *)kcontrol->private_value;
368 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
369 int mask, ret;
370
371 /* Can't enable both ADC and DAC paths simultaneously */
372 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
373 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
374 WM8994_AIF1ADC1R_DRC_ENA_MASK;
375 else
376 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
377
378 ret = snd_soc_read(codec, mc->reg);
379 if (ret < 0)
380 return ret;
381 if (ret & mask)
382 return -EINVAL;
383
384 return snd_soc_put_volsw(kcontrol, ucontrol);
385}
386
9e6e96a1
MB		 387static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
388{
b2c812e2 389 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 390 struct wm8994_pdata *pdata = wm8994->pdata;
391 int base = wm8994_drc_base[drc];
392 int cfg = wm8994->drc_cfg[drc];
393 int save, i;
394
395 /* Save any enables; the configuration should clear them. */
396 save = snd_soc_read(codec, base);
397 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
398 WM8994_AIF1ADC1R_DRC_ENA;
399
400 for (i = 0; i < WM8994_DRC_REGS; i++)
401 snd_soc_update_bits(codec, base + i, 0xffff,
402 pdata->drc_cfgs[cfg].regs[i]);
403
404 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
405 WM8994_AIF1ADC1L_DRC_ENA |
406 WM8994_AIF1ADC1R_DRC_ENA, save);
407}
408
409/* Icky as hell but saves code duplication */
410static int wm8994_get_drc(const char *name)
411{
412 if (strcmp(name, "AIF1DRC1 Mode") == 0)
413 return 0;
414 if (strcmp(name, "AIF1DRC2 Mode") == 0)
415 return 1;
416 if (strcmp(name, "AIF2DRC Mode") == 0)
417 return 2;
418 return -EINVAL;
419}
420
421static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
422 struct snd_ctl_elem_value *ucontrol)
423{
424 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 425 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 426 struct wm8994_pdata *pdata = wm8994->pdata;
427 int drc = wm8994_get_drc(kcontrol->id.name);
428 int value = ucontrol->value.integer.value[0];
429
430 if (drc < 0)
431 return drc;
432
433 if (value >= pdata->num_drc_cfgs)
434 return -EINVAL;
435
436 wm8994->drc_cfg[drc] = value;
437
438 wm8994_set_drc(codec, drc);
439
440 return 0;
441}
442
443static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
444 struct snd_ctl_elem_value *ucontrol)
445{
446 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 447 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 448 int drc = wm8994_get_drc(kcontrol->id.name);
449
450 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
451
452 return 0;
453}
454
455static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
456{
b2c812e2 457 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 458 struct wm8994_pdata *pdata = wm8994->pdata;
459 int base = wm8994_retune_mobile_base[block];
460 int iface, best, best_val, save, i, cfg;
461
462 if (!pdata || !wm8994->num_retune_mobile_texts)
463 return;
464
465 switch (block) {
466 case 0:
467 case 1:
468 iface = 0;
469 break;
470 case 2:
471 iface = 1;
472 break;
473 default:
474 return;
475 }
476
477 /* Find the version of the currently selected configuration
478 * with the nearest sample rate. */
479 cfg = wm8994->retune_mobile_cfg[block];
480 best = 0;
481 best_val = INT_MAX;
482 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
483 if (strcmp(pdata->retune_mobile_cfgs[i].name,
484 wm8994->retune_mobile_texts[cfg]) == 0 &&
485 abs(pdata->retune_mobile_cfgs[i].rate
486 - wm8994->dac_rates[iface]) < best_val) {
487 best = i;
488 best_val = abs(pdata->retune_mobile_cfgs[i].rate
489 - wm8994->dac_rates[iface]);
490 }
491 }
492
493 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
494 block,
495 pdata->retune_mobile_cfgs[best].name,
496 pdata->retune_mobile_cfgs[best].rate,
497 wm8994->dac_rates[iface]);
498
499 /* The EQ will be disabled while reconfiguring it, remember the
500 * current configuration.
501 */
502 save = snd_soc_read(codec, base);
503 save &= WM8994_AIF1DAC1_EQ_ENA;
504
505 for (i = 0; i < WM8994_EQ_REGS; i++)
506 snd_soc_update_bits(codec, base + i, 0xffff,
507 pdata->retune_mobile_cfgs[best].regs[i]);
508
509 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
510}
511
512/* Icky as hell but saves code duplication */
513static int wm8994_get_retune_mobile_block(const char *name)
514{
515 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
516 return 0;
517 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
518 return 1;
519 if (strcmp(name, "AIF2 EQ Mode") == 0)
520 return 2;
521 return -EINVAL;
522}
523
524static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
525 struct snd_ctl_elem_value *ucontrol)
526{
527 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 528 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 529 struct wm8994_pdata *pdata = wm8994->pdata;
530 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
531 int value = ucontrol->value.integer.value[0];
532
533 if (block < 0)
534 return block;
535
536 if (value >= pdata->num_retune_mobile_cfgs)
537 return -EINVAL;
538
539 wm8994->retune_mobile_cfg[block] = value;
540
541 wm8994_set_retune_mobile(codec, block);
542
543 return 0;
544}
545
546static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
547 struct snd_ctl_elem_value *ucontrol)
548{
549 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
4a8d929d 550 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 551 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
552
553 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
554
555 return 0;
556}
557
96b101ef 558static const char *aif_chan_src_text[] = {
f554885f
MB		 559 "Left", "Right"
560};
561
96b101ef
MB		 562static const struct soc_enum aif1adcl_src =
563 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
564
565static const struct soc_enum aif1adcr_src =
566 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
567
568static const struct soc_enum aif2adcl_src =
569 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
570
571static const struct soc_enum aif2adcr_src =
572 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
573
f554885f 574static const struct soc_enum aif1dacl_src =
96b101ef 575 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 576
577static const struct soc_enum aif1dacr_src =
96b101ef 578 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f
MB		 579
580static const struct soc_enum aif2dacl_src =
96b101ef 581 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 582
583static const struct soc_enum aif2dacr_src =
96b101ef 584 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f 585
154b26aa
MB		 586static const char *osr_text[] = {
587 "Low Power", "High Performance",
588};
589
590static const struct soc_enum dac_osr =
591 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
592
593static const struct soc_enum adc_osr =
594 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
595
9e6e96a1
MB		 596static const struct snd_kcontrol_new wm8994_snd_controls[] = {
597SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
598 WM8994_AIF1_ADC1_RIGHT_VOLUME,
599 1, 119, 0, digital_tlv),
600SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
601 WM8994_AIF1_ADC2_RIGHT_VOLUME,
602 1, 119, 0, digital_tlv),
603SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
604 WM8994_AIF2_ADC_RIGHT_VOLUME,
605 1, 119, 0, digital_tlv),
606
96b101ef
MB		 607SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
608SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
49db7e7b
MB		 609SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
610SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
96b101ef 611
f554885f
MB		 612SOC_ENUM("AIF1DACL Source", aif1dacl_src),
613SOC_ENUM("AIF1DACR Source", aif1dacr_src),
49db7e7b
MB		 614SOC_ENUM("AIF2DACL Source", aif2dacl_src),
615SOC_ENUM("AIF2DACR Source", aif2dacr_src),
f554885f 616
9e6e96a1
MB		 617SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
618 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
619SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
620 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
621SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
622 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
623
624SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
625SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
626
627SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
628SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
629SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
630
631WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
632WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
633WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
634
635WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
636WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
637WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
638
639WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
640WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
641WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
642
643SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
644 5, 12, 0, st_tlv),
645SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
646 0, 12, 0, st_tlv),
647SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
648 5, 12, 0, st_tlv),
649SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
650 0, 12, 0, st_tlv),
651SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
652SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
653
146fd574
UK		 654SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
655SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
656
657SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
658SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
659
660SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
661SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
662
154b26aa
MB		 663SOC_ENUM("ADC OSR", adc_osr),
664SOC_ENUM("DAC OSR", dac_osr),
665
9e6e96a1
MB		 666SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
667 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
668SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
669 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
670
671SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
672 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
673SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
674 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
675
676SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
677 6, 1, 1, wm_hubs_spkmix_tlv),
678SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
679 2, 1, 1, wm_hubs_spkmix_tlv),
680
681SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
682 6, 1, 1, wm_hubs_spkmix_tlv),
683SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
684 2, 1, 1, wm_hubs_spkmix_tlv),
685
686SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
687 10, 15, 0, wm8994_3d_tlv),
458350b3 688SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
9e6e96a1
MB		 689 8, 1, 0),
690SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
691 10, 15, 0, wm8994_3d_tlv),
692SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
693 8, 1, 0),
458350b3 694SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1 695 10, 15, 0, wm8994_3d_tlv),
458350b3 696SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1
MB		 697 8, 1, 0),
698};
699
700static const struct snd_kcontrol_new wm8994_eq_controls[] = {
701SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
702 eq_tlv),
703SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
704 eq_tlv),
705SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
706 eq_tlv),
707SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
708 eq_tlv),
709SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
710 eq_tlv),
711
712SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
713 eq_tlv),
714SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
715 eq_tlv),
716SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
717 eq_tlv),
718SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
719 eq_tlv),
720SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
721 eq_tlv),
722
723SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
724 eq_tlv),
725SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
726 eq_tlv),
727SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
728 eq_tlv),
729SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
730 eq_tlv),
731SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
732 eq_tlv),
733};
734
1ddc07d0
MB		 735static const char *wm8958_ng_text[] = {
736 "30ms", "125ms", "250ms", "500ms",
737};
738
739static const struct soc_enum wm8958_aif1dac1_ng_hold =
740 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
741 WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
742
743static const struct soc_enum wm8958_aif1dac2_ng_hold =
744 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
745 WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
746
747static const struct soc_enum wm8958_aif2dac_ng_hold =
748 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
749 WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
750
c4431df0
MB		 751static const struct snd_kcontrol_new wm8958_snd_controls[] = {
752SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
1ddc07d0
MB		 753
754SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
755 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
756SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
757SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
758 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
759 7, 1, ng_tlv),
760
761SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
762 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
763SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
764SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
765 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
766 7, 1, ng_tlv),
767
768SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
769 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
770SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
771SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
772 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
773 7, 1, ng_tlv),
c4431df0
MB		 774};
775
81204c84
MB		 776static const struct snd_kcontrol_new wm1811_snd_controls[] = {
777SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
778 mixin_boost_tlv),
779SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
780 mixin_boost_tlv),
781};
782
af6b6fe4
MB		 783/* We run all mode setting through a function to enforce audio mode */
784static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
785{
786 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
787
788 if (wm8994->active_refcount)
789 mode = WM1811_JACKDET_MODE_AUDIO;
790
791 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
792 WM1811_JACKDET_MODE_MASK, mode);
793
794 if (mode == WM1811_JACKDET_MODE_MIC)
795 msleep(2);
796}
797
798static void active_reference(struct snd_soc_codec *codec)
799{
800 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
801
802 mutex_lock(&wm8994->accdet_lock);
803
804 wm8994->active_refcount++;
805
806 dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
807 wm8994->active_refcount);
808
809 if (wm8994->active_refcount == 1) {
810 /* If we're using jack detection go into audio mode */
811 if (wm8994->jackdet && wm8994->jack_cb) {
812 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
813 WM1811_JACKDET_MODE_MASK,
814 WM1811_JACKDET_MODE_AUDIO);
815 msleep(2);
816 }
817 }
818
819 mutex_unlock(&wm8994->accdet_lock);
820}
821
822static void active_dereference(struct snd_soc_codec *codec)
823{
824 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
825 u16 mode;
826
827 mutex_lock(&wm8994->accdet_lock);
828
829 wm8994->active_refcount--;
830
831 dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
832 wm8994->active_refcount);
833
834 if (wm8994->active_refcount == 0) {
835 /* Go into appropriate detection only mode */
836 if (wm8994->jackdet && wm8994->jack_cb) {
837 if (wm8994->jack_mic || wm8994->mic_detecting)
838 mode = WM1811_JACKDET_MODE_MIC;
839 else
840 mode = WM1811_JACKDET_MODE_JACK;
841
842 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
843 WM1811_JACKDET_MODE_MASK,
844 mode);
845 }
846 }
847
848 mutex_unlock(&wm8994->accdet_lock);
849}
850
9e6e96a1
MB		 851static int clk_sys_event(struct snd_soc_dapm_widget *w,
852 struct snd_kcontrol *kcontrol, int event)
853{
854 struct snd_soc_codec *codec = w->codec;
855
856 switch (event) {
857 case SND_SOC_DAPM_PRE_PMU:
858 return configure_clock(codec);
859
860 case SND_SOC_DAPM_POST_PMD:
861 configure_clock(codec);
862 break;
863 }
864
865 return 0;
866}
867
4b7ed83a
MB		 868static void vmid_reference(struct snd_soc_codec *codec)
869{
870 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
871
872 wm8994->vmid_refcount++;
873
874 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
875 wm8994->vmid_refcount);
876
877 if (wm8994->vmid_refcount == 1) {
878 /* Startup bias, VMID ramp & buffer */
879 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
880 WM8994_STARTUP_BIAS_ENA |
881 WM8994_VMID_BUF_ENA |
882 WM8994_VMID_RAMP_MASK,
883 WM8994_STARTUP_BIAS_ENA |
884 WM8994_VMID_BUF_ENA |
885 (0x11 << WM8994_VMID_RAMP_SHIFT));
886
887 /* Main bias enable, VMID=2x40k */
888 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
889 WM8994_BIAS_ENA |
890 WM8994_VMID_SEL_MASK,
891 WM8994_BIAS_ENA | 0x2);
892
893 msleep(20);
894 }
895}
896
897static void vmid_dereference(struct snd_soc_codec *codec)
898{
899 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
900
901 wm8994->vmid_refcount--;
902
903 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
904 wm8994->vmid_refcount);
905
906 if (wm8994->vmid_refcount == 0) {
907 /* Switch over to startup biases */
908 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
909 WM8994_BIAS_SRC |
910 WM8994_STARTUP_BIAS_ENA |
911 WM8994_VMID_BUF_ENA |
912 WM8994_VMID_RAMP_MASK,
913 WM8994_BIAS_SRC |
914 WM8994_STARTUP_BIAS_ENA |
915 WM8994_VMID_BUF_ENA |
916 (1 << WM8994_VMID_RAMP_SHIFT));
917
918 /* Disable main biases */
919 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
920 WM8994_BIAS_ENA |
921 WM8994_VMID_SEL_MASK, 0);
922
923 /* Discharge line */
924 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
925 WM8994_LINEOUT1_DISCH |
926 WM8994_LINEOUT2_DISCH,
927 WM8994_LINEOUT1_DISCH |
928 WM8994_LINEOUT2_DISCH);
929
930 msleep(5);
931
932 /* Switch off startup biases */
933 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
934 WM8994_BIAS_SRC |
935 WM8994_STARTUP_BIAS_ENA |
936 WM8994_VMID_BUF_ENA |
937 WM8994_VMID_RAMP_MASK, 0);
938 }
939}
940
941static int vmid_event(struct snd_soc_dapm_widget *w,
942 struct snd_kcontrol *kcontrol, int event)
943{
944 struct snd_soc_codec *codec = w->codec;
945
946 switch (event) {
947 case SND_SOC_DAPM_PRE_PMU:
948 vmid_reference(codec);
949 break;
950
951 case SND_SOC_DAPM_POST_PMD:
952 vmid_dereference(codec);
953 break;
954 }
955
956 return 0;
957}
958
9e6e96a1
MB		 959static void wm8994_update_class_w(struct snd_soc_codec *codec)
960{
fec6dd83 961 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 962 int enable = 1;
963 int source = 0; /* GCC flow analysis can't track enable */
964 int reg, reg_r;
965
966 /* Only support direct DAC->headphone paths */
967 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
968 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
ee839a21 969 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
9e6e96a1
MB		 970 enable = 0;
971 }
972
973 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
974 if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
ee839a21 975 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
9e6e96a1
MB		 976 enable = 0;
977 }
978
979 /* We also need the same setting for L/R and only one path */
980 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
981 switch (reg) {
982 case WM8994_AIF2DACL_TO_DAC1L:
ee839a21 983 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
9e6e96a1
MB		 984 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
985 break;
986 case WM8994_AIF1DAC2L_TO_DAC1L:
ee839a21 987 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
9e6e96a1
MB		 988 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
989 break;
990 case WM8994_AIF1DAC1L_TO_DAC1L:
ee839a21 991 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
9e6e96a1
MB		 992 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
993 break;
994 default:
ee839a21 995 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
9e6e96a1
MB		 996 enable = 0;
997 break;
998 }
999
1000 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
1001 if (reg_r != reg) {
ee839a21 1002 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
9e6e96a1
MB		 1003 enable = 0;
1004 }
1005
1006 if (enable) {
1007 dev_dbg(codec->dev, "Class W enabled\n");
1008 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1009 WM8994_CP_DYN_PWR |
1010 WM8994_CP_DYN_SRC_SEL_MASK,
1011 source | WM8994_CP_DYN_PWR);
fec6dd83 1012 wm8994->hubs.class_w = true;
9e6e96a1
MB		 1013
1014 } else {
1015 dev_dbg(codec->dev, "Class W disabled\n");
1016 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1017 WM8994_CP_DYN_PWR, 0);
fec6dd83 1018 wm8994->hubs.class_w = false;
9e6e96a1
MB		 1019 }
1020}
1021
173efa09
DP		 1022static int late_enable_ev(struct snd_soc_dapm_widget *w,
1023 struct snd_kcontrol *kcontrol, int event)
1024{
1025 struct snd_soc_codec *codec = w->codec;
1026 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1027
1028 switch (event) {
1029 case SND_SOC_DAPM_PRE_PMU:
a3cff81a 1030 if (wm8994->aif1clk_enable) {
173efa09
DP		 1031 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1032 WM8994_AIF1CLK_ENA_MASK,
1033 WM8994_AIF1CLK_ENA);
a3cff81a
DP		 1034 wm8994->aif1clk_enable = 0;
1035 }
1036 if (wm8994->aif2clk_enable) {
173efa09
DP		 1037 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1038 WM8994_AIF2CLK_ENA_MASK,
1039 WM8994_AIF2CLK_ENA);
a3cff81a
DP		 1040 wm8994->aif2clk_enable = 0;
1041 }
173efa09
DP		 1042 break;
1043 }
1044
c6b7b570
MB		 1045 /* We may also have postponed startup of DSP, handle that. */
1046 wm8958_aif_ev(w, kcontrol, event);
1047
173efa09
DP		 1048 return 0;
1049}
1050
1051static int late_disable_ev(struct snd_soc_dapm_widget *w,
1052 struct snd_kcontrol *kcontrol, int event)
1053{
1054 struct snd_soc_codec *codec = w->codec;
1055 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1056
1057 switch (event) {
1058 case SND_SOC_DAPM_POST_PMD:
a3cff81a 1059 if (wm8994->aif1clk_disable) {
173efa09
DP		 1060 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1061 WM8994_AIF1CLK_ENA_MASK, 0);
a3cff81a 1062 wm8994->aif1clk_disable = 0;
173efa09 1063 }
a3cff81a 1064 if (wm8994->aif2clk_disable) {
173efa09
DP		 1065 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1066 WM8994_AIF2CLK_ENA_MASK, 0);
a3cff81a 1067 wm8994->aif2clk_disable = 0;
173efa09
DP		 1068 }
1069 break;
1070 }
1071
1072 return 0;
1073}
1074
1075static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1076 struct snd_kcontrol *kcontrol, int event)
1077{
1078 struct snd_soc_codec *codec = w->codec;
1079 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1080
1081 switch (event) {
1082 case SND_SOC_DAPM_PRE_PMU:
1083 wm8994->aif1clk_enable = 1;
1084 break;
a3cff81a
DP		 1085 case SND_SOC_DAPM_POST_PMD:
1086 wm8994->aif1clk_disable = 1;
1087 break;
173efa09
DP		 1088 }
1089
1090 return 0;
1091}
1092
1093static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1094 struct snd_kcontrol *kcontrol, int event)
1095{
1096 struct snd_soc_codec *codec = w->codec;
1097 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1098
1099 switch (event) {
1100 case SND_SOC_DAPM_PRE_PMU:
1101 wm8994->aif2clk_enable = 1;
1102 break;
a3cff81a
DP		 1103 case SND_SOC_DAPM_POST_PMD:
1104 wm8994->aif2clk_disable = 1;
1105 break;
173efa09
DP		 1106 }
1107
1108 return 0;
1109}
1110
04d28681
DP		 1111static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1112 struct snd_kcontrol *kcontrol, int event)
1113{
1114 late_enable_ev(w, kcontrol, event);
1115 return 0;
1116}
1117
b462c6e6
DP		 1118static int micbias_ev(struct snd_soc_dapm_widget *w,
1119 struct snd_kcontrol *kcontrol, int event)
1120{
1121 late_enable_ev(w, kcontrol, event);
1122 return 0;
1123}
1124
c52fd021
DP		 1125static int dac_ev(struct snd_soc_dapm_widget *w,
1126 struct snd_kcontrol *kcontrol, int event)
1127{
1128 struct snd_soc_codec *codec = w->codec;
1129 unsigned int mask = 1 << w->shift;
1130
1131 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1132 mask, mask);
1133 return 0;
1134}
1135
9e6e96a1
MB		 1136static const char *hp_mux_text[] = {
1137 "Mixer",
1138 "DAC",
1139};
1140
1141#define WM8994_HP_ENUM(xname, xenum) \
1142{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1143 .info = snd_soc_info_enum_double, \
1144 .get = snd_soc_dapm_get_enum_double, \
1145 .put = wm8994_put_hp_enum, \
1146 .private_value = (unsigned long)&xenum }
1147
1148static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
1149 struct snd_ctl_elem_value *ucontrol)
1150{
9d03545d
JN		 1151 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1152 struct snd_soc_dapm_widget *w = wlist->widgets[0];
9e6e96a1
MB		 1153 struct snd_soc_codec *codec = w->codec;
1154 int ret;
1155
1156 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1157
1158 wm8994_update_class_w(codec);
1159
1160 return ret;
1161}
1162
1163static const struct soc_enum hpl_enum =
1164 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
1165
1166static const struct snd_kcontrol_new hpl_mux =
1167 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
1168
1169static const struct soc_enum hpr_enum =
1170 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
1171
1172static const struct snd_kcontrol_new hpr_mux =
1173 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
1174
1175static const char *adc_mux_text[] = {
1176 "ADC",
1177 "DMIC",
1178};
1179
1180static const struct soc_enum adc_enum =
1181 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1182
1183static const struct snd_kcontrol_new adcl_mux =
1184 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1185
1186static const struct snd_kcontrol_new adcr_mux =
1187 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1188
1189static const struct snd_kcontrol_new left_speaker_mixer[] = {
1190SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1191SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1192SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1193SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1194SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1195};
1196
1197static const struct snd_kcontrol_new right_speaker_mixer[] = {
1198SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1199SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1200SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1201SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1202SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1203};
1204
1205/* Debugging; dump chip status after DAPM transitions */
1206static int post_ev(struct snd_soc_dapm_widget *w,
1207 struct snd_kcontrol *kcontrol, int event)
1208{
1209 struct snd_soc_codec *codec = w->codec;
1210 dev_dbg(codec->dev, "SRC status: %x\n",
1211 snd_soc_read(codec,
1212 WM8994_RATE_STATUS));
1213 return 0;
1214}
1215
1216static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1217SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1218 1, 1, 0),
1219SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1220 0, 1, 0),
1221};
1222
1223static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1224SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1225 1, 1, 0),
1226SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1227 0, 1, 0),
1228};
1229
a3257ba8
MB		 1230static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1231SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1232 1, 1, 0),
1233SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1234 0, 1, 0),
1235};
1236
1237static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1238SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1239 1, 1, 0),
1240SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1241 0, 1, 0),
1242};
1243
9e6e96a1
MB		 1244static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1245SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1246 5, 1, 0),
1247SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1248 4, 1, 0),
1249SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1250 2, 1, 0),
1251SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1252 1, 1, 0),
1253SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1254 0, 1, 0),
1255};
1256
1257static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1258SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1259 5, 1, 0),
1260SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1261 4, 1, 0),
1262SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1263 2, 1, 0),
1264SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1265 1, 1, 0),
1266SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1267 0, 1, 0),
1268};
1269
1270#define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1271{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1272 .info = snd_soc_info_volsw, \
1273 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1274 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1275
1276static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1277 struct snd_ctl_elem_value *ucontrol)
1278{
9d03545d
JN		 1279 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1280 struct snd_soc_dapm_widget *w = wlist->widgets[0];
9e6e96a1
MB		 1281 struct snd_soc_codec *codec = w->codec;
1282 int ret;
1283
1284 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1285
1286 wm8994_update_class_w(codec);
1287
1288 return ret;
1289}
1290
1291static const struct snd_kcontrol_new dac1l_mix[] = {
1292WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1293 5, 1, 0),
1294WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1295 4, 1, 0),
1296WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1297 2, 1, 0),
1298WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1299 1, 1, 0),
1300WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1301 0, 1, 0),
1302};
1303
1304static const struct snd_kcontrol_new dac1r_mix[] = {
1305WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1306 5, 1, 0),
1307WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1308 4, 1, 0),
1309WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1310 2, 1, 0),
1311WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1312 1, 1, 0),
1313WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1314 0, 1, 0),
1315};
1316
1317static const char *sidetone_text[] = {
1318 "ADC/DMIC1", "DMIC2",
1319};
1320
1321static const struct soc_enum sidetone1_enum =
1322 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1323
1324static const struct snd_kcontrol_new sidetone1_mux =
1325 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1326
1327static const struct soc_enum sidetone2_enum =
1328 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1329
1330static const struct snd_kcontrol_new sidetone2_mux =
1331 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1332
1333static const char *aif1dac_text[] = {
1334 "AIF1DACDAT", "AIF3DACDAT",
1335};
1336
1337static const struct soc_enum aif1dac_enum =
1338 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1339
1340static const struct snd_kcontrol_new aif1dac_mux =
1341 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1342
1343static const char *aif2dac_text[] = {
1344 "AIF2DACDAT", "AIF3DACDAT",
1345};
1346
1347static const struct soc_enum aif2dac_enum =
1348 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1349
1350static const struct snd_kcontrol_new aif2dac_mux =
1351 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1352
1353static const char *aif2adc_text[] = {
1354 "AIF2ADCDAT", "AIF3DACDAT",
1355};
1356
1357static const struct soc_enum aif2adc_enum =
1358 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1359
1360static const struct snd_kcontrol_new aif2adc_mux =
1361 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1362
1363static const char *aif3adc_text[] = {
c4431df0 1364 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
9e6e96a1
MB		 1365};
1366
c4431df0 1367static const struct soc_enum wm8994_aif3adc_enum =
9e6e96a1
MB		 1368 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1369
c4431df0
MB		 1370static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1371 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1372
1373static const struct soc_enum wm8958_aif3adc_enum =
1374 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1375
1376static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1377 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1378
1379static const char *mono_pcm_out_text[] = {
1380 "None", "AIF2ADCL", "AIF2ADCR",
1381};
1382
1383static const struct soc_enum mono_pcm_out_enum =
1384 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1385
1386static const struct snd_kcontrol_new mono_pcm_out_mux =
1387 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1388
1389static const char *aif2dac_src_text[] = {
1390 "AIF2", "AIF3",
1391};
1392
1393/* Note that these two control shouldn't be simultaneously switched to AIF3 */
1394static const struct soc_enum aif2dacl_src_enum =
1395 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1396
1397static const struct snd_kcontrol_new aif2dacl_src_mux =
1398 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1399
1400static const struct soc_enum aif2dacr_src_enum =
1401 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1402
1403static const struct snd_kcontrol_new aif2dacr_src_mux =
1404 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
9e6e96a1 1405
173efa09
DP		 1406static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1407SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1408 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1409SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1410 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1411
1412SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1413 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1414SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1415 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1416SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1417 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1418SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1419 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
b70a51ba
MB		 1420SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1421 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1422
1423SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1424 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1425 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1426SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1427 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1428 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1429SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux,
1430 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1431SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux,
1432 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
173efa09
DP		 1433
1434SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1435};
1436
1437static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1438SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
b70a51ba
MB		 1439SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
1440SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1441SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1442 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1443SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1444 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1445SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1446SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
173efa09
DP		 1447};
1448
c52fd021
DP		 1449static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1450SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1451 dac_ev, SND_SOC_DAPM_PRE_PMU),
1452SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1453 dac_ev, SND_SOC_DAPM_PRE_PMU),
1454SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1455 dac_ev, SND_SOC_DAPM_PRE_PMU),
1456SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1457 dac_ev, SND_SOC_DAPM_PRE_PMU),
1458};
1459
1460static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1461SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
0627bd25 1462SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
c52fd021
DP		 1463SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1464SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1465};
1466
04d28681
DP		 1467static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1468SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1469 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1470SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1471 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1472};
1473
1474static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1475SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1476SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1477};
1478
9e6e96a1
MB		 1479static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1480SND_SOC_DAPM_INPUT("DMIC1DAT"),
1481SND_SOC_DAPM_INPUT("DMIC2DAT"),
66b47fdb 1482SND_SOC_DAPM_INPUT("Clock"),
9e6e96a1 1483
b462c6e6
DP		 1484SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1485 SND_SOC_DAPM_PRE_PMU),
4b7ed83a
MB		 1486SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1487 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
b462c6e6 1488
9e6e96a1
MB		 1489SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1490 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1491
1492SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1493SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1494SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1495
7f94de48 1496SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
9e6e96a1 1497 0, WM8994_POWER_MANAGEMENT_4, 9, 0),
7f94de48 1498SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
9e6e96a1 1499 0, WM8994_POWER_MANAGEMENT_4, 8, 0),
d6addcc9
MB		 1500SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1501 WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
b2822a8c 1502 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9
MB		 1503SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1504 WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
b2822a8c 1505 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1 1506
7f94de48 1507SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
9e6e96a1 1508 0, WM8994_POWER_MANAGEMENT_4, 11, 0),
7f94de48 1509SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
9e6e96a1 1510 0, WM8994_POWER_MANAGEMENT_4, 10, 0),
d6addcc9
MB		 1511SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1512 WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
b2822a8c 1513 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9
MB		 1514SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1515 WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
b2822a8c 1516 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1
MB		 1517
1518SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1519 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1520SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1521 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1522
a3257ba8
MB		 1523SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1524 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1525SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1526 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1527
9e6e96a1
MB		 1528SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1529 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1530SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1531 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1532
1533SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1534SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1535
1536SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1537 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1538SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1539 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1540
1541SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1542 WM8994_POWER_MANAGEMENT_4, 13, 0),
1543SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1544 WM8994_POWER_MANAGEMENT_4, 12, 0),
d6addcc9
MB		 1545SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1546 WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1547 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1548SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1549 WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1550 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
9e6e96a1
MB		 1551
1552SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1553SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
7f94de48 1554SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1555SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1556
1557SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1558SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1559SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
9e6e96a1
MB		 1560
1561SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
35024f49 1562SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1563
1564SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1565
1566SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1567SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1568SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1569SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1570
1571/* Power is done with the muxes since the ADC power also controls the
1572 * downsampling chain, the chip will automatically manage the analogue
1573 * specific portions.
1574 */
1575SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1576SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1577
9e6e96a1
MB		 1578SND_SOC_DAPM_POST("Debug log", post_ev),
1579};
1580
c4431df0
MB		 1581static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1582SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1583};
9e6e96a1 1584
c4431df0
MB		 1585static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1586SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1587SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1588SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1589SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1590};
1591
1592static const struct snd_soc_dapm_route intercon[] = {
9e6e96a1
MB		 1593 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1594 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1595
1596 { "DSP1CLK", NULL, "CLK_SYS" },
1597 { "DSP2CLK", NULL, "CLK_SYS" },
1598 { "DSPINTCLK", NULL, "CLK_SYS" },
1599
1600 { "AIF1ADC1L", NULL, "AIF1CLK" },
1601 { "AIF1ADC1L", NULL, "DSP1CLK" },
1602 { "AIF1ADC1R", NULL, "AIF1CLK" },
1603 { "AIF1ADC1R", NULL, "DSP1CLK" },
1604 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1605
1606 { "AIF1DAC1L", NULL, "AIF1CLK" },
1607 { "AIF1DAC1L", NULL, "DSP1CLK" },
1608 { "AIF1DAC1R", NULL, "AIF1CLK" },
1609 { "AIF1DAC1R", NULL, "DSP1CLK" },
1610 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1611
1612 { "AIF1ADC2L", NULL, "AIF1CLK" },
1613 { "AIF1ADC2L", NULL, "DSP1CLK" },
1614 { "AIF1ADC2R", NULL, "AIF1CLK" },
1615 { "AIF1ADC2R", NULL, "DSP1CLK" },
1616 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1617
1618 { "AIF1DAC2L", NULL, "AIF1CLK" },
1619 { "AIF1DAC2L", NULL, "DSP1CLK" },
1620 { "AIF1DAC2R", NULL, "AIF1CLK" },
1621 { "AIF1DAC2R", NULL, "DSP1CLK" },
1622 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1623
1624 { "AIF2ADCL", NULL, "AIF2CLK" },
1625 { "AIF2ADCL", NULL, "DSP2CLK" },
1626 { "AIF2ADCR", NULL, "AIF2CLK" },
1627 { "AIF2ADCR", NULL, "DSP2CLK" },
1628 { "AIF2ADCR", NULL, "DSPINTCLK" },
1629
1630 { "AIF2DACL", NULL, "AIF2CLK" },
1631 { "AIF2DACL", NULL, "DSP2CLK" },
1632 { "AIF2DACR", NULL, "AIF2CLK" },
1633 { "AIF2DACR", NULL, "DSP2CLK" },
1634 { "AIF2DACR", NULL, "DSPINTCLK" },
1635
1636 { "DMIC1L", NULL, "DMIC1DAT" },
1637 { "DMIC1L", NULL, "CLK_SYS" },
1638 { "DMIC1R", NULL, "DMIC1DAT" },
1639 { "DMIC1R", NULL, "CLK_SYS" },
1640 { "DMIC2L", NULL, "DMIC2DAT" },
1641 { "DMIC2L", NULL, "CLK_SYS" },
1642 { "DMIC2R", NULL, "DMIC2DAT" },
1643 { "DMIC2R", NULL, "CLK_SYS" },
1644
1645 { "ADCL", NULL, "AIF1CLK" },
1646 { "ADCL", NULL, "DSP1CLK" },
1647 { "ADCL", NULL, "DSPINTCLK" },
1648
1649 { "ADCR", NULL, "AIF1CLK" },
1650 { "ADCR", NULL, "DSP1CLK" },
1651 { "ADCR", NULL, "DSPINTCLK" },
1652
1653 { "ADCL Mux", "ADC", "ADCL" },
1654 { "ADCL Mux", "DMIC", "DMIC1L" },
1655 { "ADCR Mux", "ADC", "ADCR" },
1656 { "ADCR Mux", "DMIC", "DMIC1R" },
1657
1658 { "DAC1L", NULL, "AIF1CLK" },
1659 { "DAC1L", NULL, "DSP1CLK" },
1660 { "DAC1L", NULL, "DSPINTCLK" },
1661
1662 { "DAC1R", NULL, "AIF1CLK" },
1663 { "DAC1R", NULL, "DSP1CLK" },
1664 { "DAC1R", NULL, "DSPINTCLK" },
1665
1666 { "DAC2L", NULL, "AIF2CLK" },
1667 { "DAC2L", NULL, "DSP2CLK" },
1668 { "DAC2L", NULL, "DSPINTCLK" },
1669
1670 { "DAC2R", NULL, "AIF2DACR" },
1671 { "DAC2R", NULL, "AIF2CLK" },
1672 { "DAC2R", NULL, "DSP2CLK" },
1673 { "DAC2R", NULL, "DSPINTCLK" },
1674
1675 { "TOCLK", NULL, "CLK_SYS" },
1676
1677 /* AIF1 outputs */
1678 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1679 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1680 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1681
1682 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1683 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1684 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1685
a3257ba8
MB		 1686 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1687 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1688 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1689
1690 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1691 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1692 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1693
9e6e96a1
MB		 1694 /* Pin level routing for AIF3 */
1695 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1696 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1697 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1698 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1699
9e6e96a1
MB		 1700 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1701 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1702 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1703 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1704 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1705 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1706 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1707
1708 /* DAC1 inputs */
9e6e96a1
MB		 1709 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1710 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1711 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1712 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1713 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1714
9e6e96a1
MB		 1715 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1716 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1717 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1718 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1719 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1720
1721 /* DAC2/AIF2 outputs */
1722 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
9e6e96a1
MB		 1723 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1724 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1725 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1726 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1727 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1728
1729 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
9e6e96a1
MB		 1730 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1731 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1732 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1733 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1734 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1735
7f94de48
MB		 1736 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1737 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1738 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1739 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1740
9e6e96a1
MB		 1741 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1742
1743 /* AIF3 output */
1744 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1745 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1746 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1747 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1748 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1749 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1750 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1751 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1752
1753 /* Sidetone */
1754 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1755 { "Left Sidetone", "DMIC2", "DMIC2L" },
1756 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1757 { "Right Sidetone", "DMIC2", "DMIC2R" },
1758
1759 /* Output stages */
1760 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1761 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1762
1763 { "SPKL", "DAC1 Switch", "DAC1L" },
1764 { "SPKL", "DAC2 Switch", "DAC2L" },
1765
1766 { "SPKR", "DAC1 Switch", "DAC1R" },
1767 { "SPKR", "DAC2 Switch", "DAC2R" },
1768
1769 { "Left Headphone Mux", "DAC", "DAC1L" },
1770 { "Right Headphone Mux", "DAC", "DAC1R" },
1771};
1772
173efa09
DP		 1773static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1774 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1775 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1776 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1777 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1778 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1779 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1780 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1781 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1782};
1783
1784static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1785 { "DAC1L", NULL, "DAC1L Mixer" },
1786 { "DAC1R", NULL, "DAC1R Mixer" },
1787 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1788 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1789};
1790
6ed8f148
MB		 1791static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1792 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1793 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1794 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1795 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
b793eb60
MB		 1796 { "MICBIAS1", NULL, "CLK_SYS" },
1797 { "MICBIAS1", NULL, "MICBIAS Supply" },
1798 { "MICBIAS2", NULL, "CLK_SYS" },
1799 { "MICBIAS2", NULL, "MICBIAS Supply" },
6ed8f148
MB		 1800};
1801
c4431df0
MB		 1802static const struct snd_soc_dapm_route wm8994_intercon[] = {
1803 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1804 { "AIF2DACR", NULL, "AIF2DAC Mux" },
4e04adaf
MB		 1805 { "MICBIAS1", NULL, "VMID" },
1806 { "MICBIAS2", NULL, "VMID" },
c4431df0
MB		 1807};
1808
1809static const struct snd_soc_dapm_route wm8958_intercon[] = {
1810 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1811 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1812
1813 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1814 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1815 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1816 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1817
1818 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1819 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1820
1821 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1822};
1823
9e6e96a1
MB		 1824/* The size in bits of the FLL divide multiplied by 10
1825 * to allow rounding later */
1826#define FIXED_FLL_SIZE ((1 << 16) * 10)
1827
1828struct fll_div {
1829 u16 outdiv;
1830 u16 n;
1831 u16 k;
1832 u16 clk_ref_div;
1833 u16 fll_fratio;
1834};
1835
1836static int wm8994_get_fll_config(struct fll_div *fll,
1837 int freq_in, int freq_out)
1838{
1839 u64 Kpart;
1840 unsigned int K, Ndiv, Nmod;
1841
1842 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1843
1844 /* Scale the input frequency down to <= 13.5MHz */
1845 fll->clk_ref_div = 0;
1846 while (freq_in > 13500000) {
1847 fll->clk_ref_div++;
1848 freq_in /= 2;
1849
1850 if (fll->clk_ref_div > 3)
1851 return -EINVAL;
1852 }
1853 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1854
1855 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1856 fll->outdiv = 3;
1857 while (freq_out * (fll->outdiv + 1) < 90000000) {
1858 fll->outdiv++;
1859 if (fll->outdiv > 63)
1860 return -EINVAL;
1861 }
1862 freq_out *= fll->outdiv + 1;
1863 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1864
1865 if (freq_in > 1000000) {
1866 fll->fll_fratio = 0;
7d48a6ac
MB		 1867 } else if (freq_in > 256000) {
1868 fll->fll_fratio = 1;
1869 freq_in *= 2;
1870 } else if (freq_in > 128000) {
1871 fll->fll_fratio = 2;
1872 freq_in *= 4;
1873 } else if (freq_in > 64000) {
9e6e96a1
MB		 1874 fll->fll_fratio = 3;
1875 freq_in *= 8;
7d48a6ac
MB		 1876 } else {
1877 fll->fll_fratio = 4;
1878 freq_in *= 16;
9e6e96a1
MB		 1879 }
1880 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1881
1882 /* Now, calculate N.K */
1883 Ndiv = freq_out / freq_in;
1884
1885 fll->n = Ndiv;
1886 Nmod = freq_out % freq_in;
1887 pr_debug("Nmod=%d\n", Nmod);
1888
1889 /* Calculate fractional part - scale up so we can round. */
1890 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1891
1892 do_div(Kpart, freq_in);
1893
1894 K = Kpart & 0xFFFFFFFF;
1895
1896 if ((K % 10) >= 5)
1897 K += 5;
1898
1899 /* Move down to proper range now rounding is done */
1900 fll->k = K / 10;
1901
1902 pr_debug("N=%x K=%x\n", fll->n, fll->k);
1903
1904 return 0;
1905}
1906
f0fba2ad 1907static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
9e6e96a1
MB		 1908 unsigned int freq_in, unsigned int freq_out)
1909{
b2c812e2 1910 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 1911 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 1912 int reg_offset, ret;
1913 struct fll_div fll;
1914 u16 reg, aif1, aif2;
c7ebf932 1915 unsigned long timeout;
4b7ed83a 1916 bool was_enabled;
9e6e96a1
MB		 1917
1918 aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1919 & WM8994_AIF1CLK_ENA;
1920
1921 aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1922 & WM8994_AIF2CLK_ENA;
1923
1924 switch (id) {
1925 case WM8994_FLL1:
1926 reg_offset = 0;
1927 id = 0;
1928 break;
1929 case WM8994_FLL2:
1930 reg_offset = 0x20;
1931 id = 1;
1932 break;
1933 default:
1934 return -EINVAL;
1935 }
1936
4b7ed83a
MB		 1937 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
1938 was_enabled = reg & WM8994_FLL1_ENA;
1939
136ff2a2 1940 switch (src) {
7add84aa
MB		 1941 case 0:
1942 /* Allow no source specification when stopping */
1943 if (freq_out)
1944 return -EINVAL;
4514e899 1945 src = wm8994->fll[id].src;
7add84aa 1946 break;
136ff2a2
MB		 1947 case WM8994_FLL_SRC_MCLK1:
1948 case WM8994_FLL_SRC_MCLK2:
1949 case WM8994_FLL_SRC_LRCLK:
1950 case WM8994_FLL_SRC_BCLK:
1951 break;
1952 default:
1953 return -EINVAL;
1954 }
1955
9e6e96a1
MB		 1956 /* Are we changing anything? */
1957 if (wm8994->fll[id].src == src &&
1958 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1959 return 0;
1960
1961 /* If we're stopping the FLL redo the old config - no
1962 * registers will actually be written but we avoid GCC flow
1963 * analysis bugs spewing warnings.
1964 */
1965 if (freq_out)
1966 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1967 else
1968 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1969 wm8994->fll[id].out);
1970 if (ret < 0)
1971 return ret;
1972
1973 /* Gate the AIF clocks while we reclock */
1974 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1975 WM8994_AIF1CLK_ENA, 0);
1976 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1977 WM8994_AIF2CLK_ENA, 0);
1978
1979 /* We always need to disable the FLL while reconfiguring */
1980 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1981 WM8994_FLL1_ENA, 0);
1982
1983 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1984 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1985 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1986 WM8994_FLL1_OUTDIV_MASK |
1987 WM8994_FLL1_FRATIO_MASK, reg);
1988
1989 snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1990
1991 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1992 WM8994_FLL1_N_MASK,
1993 fll.n << WM8994_FLL1_N_SHIFT);
1994
1995 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
136ff2a2
MB		 1996 WM8994_FLL1_REFCLK_DIV_MASK |
1997 WM8994_FLL1_REFCLK_SRC_MASK,
1998 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1999 (src - 1));
9e6e96a1 2000
f0f5039c
MB		 2001 /* Clear any pending completion from a previous failure */
2002 try_wait_for_completion(&wm8994->fll_locked[id]);
2003
9e6e96a1
MB		 2004 /* Enable (with fractional mode if required) */
2005 if (freq_out) {
4b7ed83a
MB		 2006 /* Enable VMID if we need it */
2007 if (!was_enabled) {
af6b6fe4
MB		 2008 active_reference(codec);
2009
4b7ed83a
MB		 2010 switch (control->type) {
2011 case WM8994:
2012 vmid_reference(codec);
2013 break;
2014 case WM8958:
2015 if (wm8994->revision < 1)
2016 vmid_reference(codec);
2017 break;
2018 default:
2019 break;
2020 }
2021 }
2022
9e6e96a1
MB		 2023 if (fll.k)
2024 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
2025 else
2026 reg = WM8994_FLL1_ENA;
2027 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2028 WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
2029 reg);
8e9ddf81 2030
c7ebf932
MB		 2031 if (wm8994->fll_locked_irq) {
2032 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2033 msecs_to_jiffies(10));
2034 if (timeout == 0)
2035 dev_warn(codec->dev,
2036 "Timed out waiting for FLL lock\n");
2037 } else {
2038 msleep(5);
2039 }
4b7ed83a
MB		 2040 } else {
2041 if (was_enabled) {
2042 switch (control->type) {
2043 case WM8994:
2044 vmid_dereference(codec);
2045 break;
2046 case WM8958:
2047 if (wm8994->revision < 1)
2048 vmid_dereference(codec);
2049 break;
2050 default:
2051 break;
2052 }
af6b6fe4
MB		 2053
2054 active_dereference(codec);
4b7ed83a 2055 }
9e6e96a1
MB		 2056 }
2057
2058 wm8994->fll[id].in = freq_in;
2059 wm8994->fll[id].out = freq_out;
136ff2a2 2060 wm8994->fll[id].src = src;
9e6e96a1
MB		 2061
2062 /* Enable any gated AIF clocks */
2063 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
2064 WM8994_AIF1CLK_ENA, aif1);
2065 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
2066 WM8994_AIF2CLK_ENA, aif2);
2067
2068 configure_clock(codec);
2069
2070 return 0;
2071}
2072
c7ebf932
MB		 2073static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2074{
2075 struct completion *completion = data;
2076
2077 complete(completion);
2078
2079 return IRQ_HANDLED;
2080}
f0fba2ad 2081
66b47fdb
MB		 2082static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2083
f0fba2ad
LG		 2084static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2085 unsigned int freq_in, unsigned int freq_out)
2086{
2087 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2088}
2089
9e6e96a1
MB		 2090static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2091 int clk_id, unsigned int freq, int dir)
2092{
2093 struct snd_soc_codec *codec = dai->codec;
b2c812e2 2094 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
66b47fdb 2095 int i;
9e6e96a1
MB		 2096
2097 switch (dai->id) {
2098 case 1:
2099 case 2:
2100 break;
2101
2102 default:
2103 /* AIF3 shares clocking with AIF1/2 */
2104 return -EINVAL;
2105 }
2106
2107 switch (clk_id) {
2108 case WM8994_SYSCLK_MCLK1:
2109 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2110 wm8994->mclk[0] = freq;
2111 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2112 dai->id, freq);
2113 break;
2114
2115 case WM8994_SYSCLK_MCLK2:
2116 /* TODO: Set GPIO AF */
2117 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2118 wm8994->mclk[1] = freq;
2119 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2120 dai->id, freq);
2121 break;
2122
2123 case WM8994_SYSCLK_FLL1:
2124 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2125 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2126 break;
2127
2128 case WM8994_SYSCLK_FLL2:
2129 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2130 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2131 break;
2132
66b47fdb
MB		 2133 case WM8994_SYSCLK_OPCLK:
2134 /* Special case - a division (times 10) is given and
2135 * no effect on main clocking.
2136 */
2137 if (freq) {
2138 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2139 if (opclk_divs[i] == freq)
2140 break;
2141 if (i == ARRAY_SIZE(opclk_divs))
2142 return -EINVAL;
2143 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2144 WM8994_OPCLK_DIV_MASK, i);
2145 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2146 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2147 } else {
2148 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2149 WM8994_OPCLK_ENA, 0);
2150 }
2151
9e6e96a1
MB		 2152 default:
2153 return -EINVAL;
2154 }
2155
2156 configure_clock(codec);
2157
2158 return 0;
2159}
2160
2161static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2162 enum snd_soc_bias_level level)
2163{
b6b05691 2164 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2165 struct wm8994 *control = wm8994->wm8994;
b6b05691 2166
9e6e96a1
MB		 2167 switch (level) {
2168 case SND_SOC_BIAS_ON:
2169 break;
2170
2171 case SND_SOC_BIAS_PREPARE:
500fa30e
MB		 2172 /* MICBIAS into regulating mode */
2173 switch (control->type) {
2174 case WM8958:
2175 case WM1811:
2176 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2177 WM8958_MICB1_MODE, 0);
2178 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2179 WM8958_MICB2_MODE, 0);
2180 break;
2181 default:
2182 break;
2183 }
af6b6fe4
MB		 2184
2185 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2186 active_reference(codec);
9e6e96a1
MB		 2187 break;
2188
2189 case SND_SOC_BIAS_STANDBY:
ce6120cc 2190 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
39fb51a1
MB		 2191 pm_runtime_get_sync(codec->dev);
2192
8bc3c2c2
MB		 2193 switch (control->type) {
2194 case WM8994:
2195 if (wm8994->revision < 4) {
2196 /* Tweak DC servo and DSP
2197 * configuration for improved
2198 * performance. */
2199 snd_soc_write(codec, 0x102, 0x3);
2200 snd_soc_write(codec, 0x56, 0x3);
2201 snd_soc_write(codec, 0x817, 0);
2202 snd_soc_write(codec, 0x102, 0);
2203 }
2204 break;
2205
2206 case WM8958:
2207 if (wm8994->revision == 0) {
2208 /* Optimise performance for rev A */
2209 snd_soc_write(codec, 0x102, 0x3);
2210 snd_soc_write(codec, 0xcb, 0x81);
2211 snd_soc_write(codec, 0x817, 0);
2212 snd_soc_write(codec, 0x102, 0);
2213
2214 snd_soc_update_bits(codec,
2215 WM8958_CHARGE_PUMP_2,
2216 WM8958_CP_DISCH,
2217 WM8958_CP_DISCH);
2218 }
2219 break;
81204c84
MB		 2220
2221 case WM1811:
2222 if (wm8994->revision < 2) {
2223 snd_soc_write(codec, 0x102, 0x3);
2224 snd_soc_write(codec, 0x5d, 0x7e);
2225 snd_soc_write(codec, 0x5e, 0x0);
2226 snd_soc_write(codec, 0x102, 0x0);
2227 }
2228 break;
b6b05691 2229 }
9e6e96a1
MB		 2230
2231 /* Discharge LINEOUT1 & 2 */
2232 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2233 WM8994_LINEOUT1_DISCH |
2234 WM8994_LINEOUT2_DISCH,
2235 WM8994_LINEOUT1_DISCH |
2236 WM8994_LINEOUT2_DISCH);
9e6e96a1
MB		 2237 }
2238
af6b6fe4
MB		 2239 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2240 active_dereference(codec);
2241
500fa30e
MB		 2242 /* MICBIAS into bypass mode on newer devices */
2243 switch (control->type) {
2244 case WM8958:
2245 case WM1811:
2246 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2247 WM8958_MICB1_MODE,
2248 WM8958_MICB1_MODE);
2249 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2250 WM8958_MICB2_MODE,
2251 WM8958_MICB2_MODE);
2252 break;
2253 default:
2254 break;
2255 }
9e6e96a1
MB		 2256 break;
2257
2258 case SND_SOC_BIAS_OFF:
ce6120cc 2259 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
fbbf5920
MB		 2260 wm8994->cur_fw = NULL;
2261
39fb51a1 2262 pm_runtime_put(codec->dev);
d522ffbf 2263 }
9e6e96a1
MB		 2264 break;
2265 }
ce6120cc 2266 codec->dapm.bias_level = level;
af6b6fe4 2267
9e6e96a1
MB		 2268 return 0;
2269}
2270
2271static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2272{
2273 struct snd_soc_codec *codec = dai->codec;
2a8a856d
MB		 2274 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2275 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 2276 int ms_reg;
2277 int aif1_reg;
2278 int ms = 0;
2279 int aif1 = 0;
2280
2281 switch (dai->id) {
2282 case 1:
2283 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2284 aif1_reg = WM8994_AIF1_CONTROL_1;
2285 break;
2286 case 2:
2287 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2288 aif1_reg = WM8994_AIF2_CONTROL_1;
2289 break;
2290 default:
2291 return -EINVAL;
2292 }
2293
2294 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2295 case SND_SOC_DAIFMT_CBS_CFS:
2296 break;
2297 case SND_SOC_DAIFMT_CBM_CFM:
2298 ms = WM8994_AIF1_MSTR;
2299 break;
2300 default:
2301 return -EINVAL;
2302 }
2303
2304 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2305 case SND_SOC_DAIFMT_DSP_B:
2306 aif1 |= WM8994_AIF1_LRCLK_INV;
2307 case SND_SOC_DAIFMT_DSP_A:
2308 aif1 |= 0x18;
2309 break;
2310 case SND_SOC_DAIFMT_I2S:
2311 aif1 |= 0x10;
2312 break;
2313 case SND_SOC_DAIFMT_RIGHT_J:
2314 break;
2315 case SND_SOC_DAIFMT_LEFT_J:
2316 aif1 |= 0x8;
2317 break;
2318 default:
2319 return -EINVAL;
2320 }
2321
2322 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2323 case SND_SOC_DAIFMT_DSP_A:
2324 case SND_SOC_DAIFMT_DSP_B:
2325 /* frame inversion not valid for DSP modes */
2326 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2327 case SND_SOC_DAIFMT_NB_NF:
2328 break;
2329 case SND_SOC_DAIFMT_IB_NF:
2330 aif1 |= WM8994_AIF1_BCLK_INV;
2331 break;
2332 default:
2333 return -EINVAL;
2334 }
2335 break;
2336
2337 case SND_SOC_DAIFMT_I2S:
2338 case SND_SOC_DAIFMT_RIGHT_J:
2339 case SND_SOC_DAIFMT_LEFT_J:
2340 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2341 case SND_SOC_DAIFMT_NB_NF:
2342 break;
2343 case SND_SOC_DAIFMT_IB_IF:
2344 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2345 break;
2346 case SND_SOC_DAIFMT_IB_NF:
2347 aif1 |= WM8994_AIF1_BCLK_INV;
2348 break;
2349 case SND_SOC_DAIFMT_NB_IF:
2350 aif1 |= WM8994_AIF1_LRCLK_INV;
2351 break;
2352 default:
2353 return -EINVAL;
2354 }
2355 break;
2356 default:
2357 return -EINVAL;
2358 }
2359
c4431df0
MB		 2360 /* The AIF2 format configuration needs to be mirrored to AIF3
2361 * on WM8958 if it's in use so just do it all the time. */
81204c84
MB		 2362 switch (control->type) {
2363 case WM1811:
2364 case WM8958:
2365 if (dai->id == 2)
2366 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2367 WM8994_AIF1_LRCLK_INV |
2368 WM8958_AIF3_FMT_MASK, aif1);
2369 break;
2370
2371 default:
2372 break;
2373 }
c4431df0 2374
9e6e96a1
MB		 2375 snd_soc_update_bits(codec, aif1_reg,
2376 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2377 WM8994_AIF1_FMT_MASK,
2378 aif1);
2379 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2380 ms);
2381
2382 return 0;
2383}
2384
2385static struct {
2386 int val, rate;
2387} srs[] = {
2388 { 0, 8000 },
2389 { 1, 11025 },
2390 { 2, 12000 },
2391 { 3, 16000 },
2392 { 4, 22050 },
2393 { 5, 24000 },
2394 { 6, 32000 },
2395 { 7, 44100 },
2396 { 8, 48000 },
2397 { 9, 88200 },
2398 { 10, 96000 },
2399};
2400
2401static int fs_ratios[] = {
2402 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2403};
2404
2405static int bclk_divs[] = {
2406 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2407 640, 880, 960, 1280, 1760, 1920
2408};
2409
2410static int wm8994_hw_params(struct snd_pcm_substream *substream,
2411 struct snd_pcm_hw_params *params,
2412 struct snd_soc_dai *dai)
2413{
2414 struct snd_soc_codec *codec = dai->codec;
b2c812e2 2415 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1 2416 int aif1_reg;
b1e43d93 2417 int aif2_reg;
9e6e96a1
MB		 2418 int bclk_reg;
2419 int lrclk_reg;
2420 int rate_reg;
2421 int aif1 = 0;
b1e43d93 2422 int aif2 = 0;
9e6e96a1
MB		 2423 int bclk = 0;
2424 int lrclk = 0;
2425 int rate_val = 0;
2426 int id = dai->id - 1;
2427
2428 int i, cur_val, best_val, bclk_rate, best;
2429
2430 switch (dai->id) {
2431 case 1:
2432 aif1_reg = WM8994_AIF1_CONTROL_1;
b1e43d93 2433 aif2_reg = WM8994_AIF1_CONTROL_2;
9e6e96a1
MB		 2434 bclk_reg = WM8994_AIF1_BCLK;
2435 rate_reg = WM8994_AIF1_RATE;
2436 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2437 wm8994->lrclk_shared[0]) {
9e6e96a1 2438 lrclk_reg = WM8994_AIF1DAC_LRCLK;
7d83d213 2439 } else {
9e6e96a1 2440 lrclk_reg = WM8994_AIF1ADC_LRCLK;
7d83d213
MB		 2441 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2442 }
9e6e96a1
MB		 2443 break;
2444 case 2:
2445 aif1_reg = WM8994_AIF2_CONTROL_1;
b1e43d93 2446 aif2_reg = WM8994_AIF2_CONTROL_2;
9e6e96a1
MB		 2447 bclk_reg = WM8994_AIF2_BCLK;
2448 rate_reg = WM8994_AIF2_RATE;
2449 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2450 wm8994->lrclk_shared[1]) {
9e6e96a1 2451 lrclk_reg = WM8994_AIF2DAC_LRCLK;
7d83d213 2452 } else {
9e6e96a1 2453 lrclk_reg = WM8994_AIF2ADC_LRCLK;
7d83d213
MB		 2454 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2455 }
9e6e96a1
MB		 2456 break;
2457 default:
2458 return -EINVAL;
2459 }
2460
2461 bclk_rate = params_rate(params) * 2;
2462 switch (params_format(params)) {
2463 case SNDRV_PCM_FORMAT_S16_LE:
2464 bclk_rate *= 16;
2465 break;
2466 case SNDRV_PCM_FORMAT_S20_3LE:
2467 bclk_rate *= 20;
2468 aif1 |= 0x20;
2469 break;
2470 case SNDRV_PCM_FORMAT_S24_LE:
2471 bclk_rate *= 24;
2472 aif1 |= 0x40;
2473 break;
2474 case SNDRV_PCM_FORMAT_S32_LE:
2475 bclk_rate *= 32;
2476 aif1 |= 0x60;
2477 break;
2478 default:
2479 return -EINVAL;
2480 }
2481
2482 /* Try to find an appropriate sample rate; look for an exact match. */
2483 for (i = 0; i < ARRAY_SIZE(srs); i++)
2484 if (srs[i].rate == params_rate(params))
2485 break;
2486 if (i == ARRAY_SIZE(srs))
2487 return -EINVAL;
2488 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2489
2490 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2491 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2492 dai->id, wm8994->aifclk[id], bclk_rate);
2493
b1e43d93
MB		 2494 if (params_channels(params) == 1 &&
2495 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2496 aif2 |= WM8994_AIF1_MONO;
2497
9e6e96a1
MB		 2498 if (wm8994->aifclk[id] == 0) {
2499 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2500 return -EINVAL;
2501 }
2502
2503 /* AIFCLK/fs ratio; look for a close match in either direction */
2504 best = 0;
2505 best_val = abs((fs_ratios[0] * params_rate(params))
2506 - wm8994->aifclk[id]);
2507 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2508 cur_val = abs((fs_ratios[i] * params_rate(params))
2509 - wm8994->aifclk[id]);
2510 if (cur_val >= best_val)
2511 continue;
2512 best = i;
2513 best_val = cur_val;
2514 }
2515 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2516 dai->id, fs_ratios[best]);
2517 rate_val |= best;
2518
2519 /* We may not get quite the right frequency if using
2520 * approximate clocks so look for the closest match that is
2521 * higher than the target (we need to ensure that there enough
2522 * BCLKs to clock out the samples).
2523 */
2524 best = 0;
2525 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
07cd8ada 2526 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
9e6e96a1
MB		 2527 if (cur_val < 0) /* BCLK table is sorted */
2528 break;
2529 best = i;
2530 }
07cd8ada 2531 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
9e6e96a1
MB		 2532 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2533 bclk_divs[best], bclk_rate);
2534 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2535
2536 lrclk = bclk_rate / params_rate(params);
fc07ecd8
MB		 2537 if (!lrclk) {
2538 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2539 bclk_rate);
2540 return -EINVAL;
2541 }
9e6e96a1
MB		 2542 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2543 lrclk, bclk_rate / lrclk);
2544
2545 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
b1e43d93 2546 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
9e6e96a1
MB		 2547 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2548 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2549 lrclk);
2550 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2551 WM8994_AIF1CLK_RATE_MASK, rate_val);
2552
2553 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2554 switch (dai->id) {
2555 case 1:
2556 wm8994->dac_rates[0] = params_rate(params);
2557 wm8994_set_retune_mobile(codec, 0);
2558 wm8994_set_retune_mobile(codec, 1);
2559 break;
2560 case 2:
2561 wm8994->dac_rates[1] = params_rate(params);
2562 wm8994_set_retune_mobile(codec, 2);
2563 break;
2564 }
2565 }
2566
2567 return 0;
2568}
2569
c4431df0
MB		 2570static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2571 struct snd_pcm_hw_params *params,
2572 struct snd_soc_dai *dai)
2573{
2574 struct snd_soc_codec *codec = dai->codec;
2a8a856d
MB		 2575 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2576 struct wm8994 *control = wm8994->wm8994;
c4431df0
MB		 2577 int aif1_reg;
2578 int aif1 = 0;
2579
2580 switch (dai->id) {
2581 case 3:
2582 switch (control->type) {
81204c84 2583 case WM1811:
c4431df0
MB		 2584 case WM8958:
2585 aif1_reg = WM8958_AIF3_CONTROL_1;
2586 break;
2587 default:
2588 return 0;
2589 }
2590 default:
2591 return 0;
2592 }
2593
2594 switch (params_format(params)) {
2595 case SNDRV_PCM_FORMAT_S16_LE:
2596 break;
2597 case SNDRV_PCM_FORMAT_S20_3LE:
2598 aif1 |= 0x20;
2599 break;
2600 case SNDRV_PCM_FORMAT_S24_LE:
2601 aif1 |= 0x40;
2602 break;
2603 case SNDRV_PCM_FORMAT_S32_LE:
2604 aif1 |= 0x60;
2605 break;
2606 default:
2607 return -EINVAL;
2608 }
2609
2610 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2611}
2612
7d02173c
MB		 2613static void wm8994_aif_shutdown(struct snd_pcm_substream *substream,
2614 struct snd_soc_dai *dai)
2615{
2616 struct snd_soc_codec *codec = dai->codec;
2617 int rate_reg = 0;
2618
2619 switch (dai->id) {
2620 case 1:
2621 rate_reg = WM8994_AIF1_RATE;
2622 break;
2623 case 2:
c527e6aa 2624 rate_reg = WM8994_AIF2_RATE;
7d02173c
MB		 2625 break;
2626 default:
2627 break;
2628 }
2629
2630 /* If the DAI is idle then configure the divider tree for the
2631 * lowest output rate to save a little power if the clock is
2632 * still active (eg, because it is system clock).
2633 */
2634 if (rate_reg && !dai->playback_active && !dai->capture_active)
2635 snd_soc_update_bits(codec, rate_reg,
2636 WM8994_AIF1_SR_MASK |
2637 WM8994_AIF1CLK_RATE_MASK, 0x9);
2638}
2639
9e6e96a1
MB		 2640static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2641{
2642 struct snd_soc_codec *codec = codec_dai->codec;
2643 int mute_reg;
2644 int reg;
2645
2646 switch (codec_dai->id) {
2647 case 1:
2648 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2649 break;
2650 case 2:
2651 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2652 break;
2653 default:
2654 return -EINVAL;
2655 }
2656
2657 if (mute)
2658 reg = WM8994_AIF1DAC1_MUTE;
2659 else
2660 reg = 0;
2661
2662 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2663
2664 return 0;
2665}
2666
778a76e2
MB		 2667static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2668{
2669 struct snd_soc_codec *codec = codec_dai->codec;
2670 int reg, val, mask;
2671
2672 switch (codec_dai->id) {
2673 case 1:
2674 reg = WM8994_AIF1_MASTER_SLAVE;
2675 mask = WM8994_AIF1_TRI;
2676 break;
2677 case 2:
2678 reg = WM8994_AIF2_MASTER_SLAVE;
2679 mask = WM8994_AIF2_TRI;
2680 break;
2681 case 3:
2682 reg = WM8994_POWER_MANAGEMENT_6;
2683 mask = WM8994_AIF3_TRI;
2684 break;
2685 default:
2686 return -EINVAL;
2687 }
2688
2689 if (tristate)
2690 val = mask;
2691 else
2692 val = 0;
2693
78b3fb46 2694 return snd_soc_update_bits(codec, reg, mask, val);
778a76e2
MB		 2695}
2696
d09f3ecf
MB		 2697static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2698{
2699 struct snd_soc_codec *codec = dai->codec;
2700
2701 /* Disable the pulls on the AIF if we're using it to save power. */
2702 snd_soc_update_bits(codec, WM8994_GPIO_3,
2703 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2704 snd_soc_update_bits(codec, WM8994_GPIO_4,
2705 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2706 snd_soc_update_bits(codec, WM8994_GPIO_5,
2707 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2708
2709 return 0;
2710}
2711
9e6e96a1
MB		 2712#define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2713
2714#define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3079aed5 2715 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
9e6e96a1 2716
85e7652d 2717static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
9e6e96a1
MB		 2718 .set_sysclk = wm8994_set_dai_sysclk,
2719 .set_fmt = wm8994_set_dai_fmt,
2720 .hw_params = wm8994_hw_params,
7d02173c 2721 .shutdown = wm8994_aif_shutdown,
9e6e96a1
MB		 2722 .digital_mute = wm8994_aif_mute,
2723 .set_pll = wm8994_set_fll,
778a76e2 2724 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2725};
2726
85e7652d 2727static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
9e6e96a1
MB		 2728 .set_sysclk = wm8994_set_dai_sysclk,
2729 .set_fmt = wm8994_set_dai_fmt,
2730 .hw_params = wm8994_hw_params,
7d02173c 2731 .shutdown = wm8994_aif_shutdown,
9e6e96a1
MB		 2732 .digital_mute = wm8994_aif_mute,
2733 .set_pll = wm8994_set_fll,
778a76e2
MB		 2734 .set_tristate = wm8994_set_tristate,
2735};
2736
85e7652d 2737static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
c4431df0 2738 .hw_params = wm8994_aif3_hw_params,
778a76e2 2739 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2740};
2741
f0fba2ad 2742static struct snd_soc_dai_driver wm8994_dai[] = {
9e6e96a1 2743 {
f0fba2ad 2744 .name = "wm8994-aif1",
8c7f78b3 2745 .id = 1,
9e6e96a1
MB		 2746 .playback = {
2747 .stream_name = "AIF1 Playback",
b1e43d93 2748 .channels_min = 1,
9e6e96a1
MB		 2749 .channels_max = 2,
2750 .rates = WM8994_RATES,
2751 .formats = WM8994_FORMATS,
2752 },
2753 .capture = {
2754 .stream_name = "AIF1 Capture",
b1e43d93 2755 .channels_min = 1,
9e6e96a1
MB		 2756 .channels_max = 2,
2757 .rates = WM8994_RATES,
2758 .formats = WM8994_FORMATS,
2759 },
2760 .ops = &wm8994_aif1_dai_ops,
2761 },
2762 {
f0fba2ad 2763 .name = "wm8994-aif2",
8c7f78b3 2764 .id = 2,
9e6e96a1
MB		 2765 .playback = {
2766 .stream_name = "AIF2 Playback",
b1e43d93 2767 .channels_min = 1,
9e6e96a1
MB		 2768 .channels_max = 2,
2769 .rates = WM8994_RATES,
2770 .formats = WM8994_FORMATS,
2771 },
2772 .capture = {
2773 .stream_name = "AIF2 Capture",
b1e43d93 2774 .channels_min = 1,
9e6e96a1
MB		 2775 .channels_max = 2,
2776 .rates = WM8994_RATES,
2777 .formats = WM8994_FORMATS,
2778 },
d09f3ecf 2779 .probe = wm8994_aif2_probe,
9e6e96a1
MB		 2780 .ops = &wm8994_aif2_dai_ops,
2781 },
2782 {
f0fba2ad 2783 .name = "wm8994-aif3",
8c7f78b3 2784 .id = 3,
9e6e96a1
MB		 2785 .playback = {
2786 .stream_name = "AIF3 Playback",
b1e43d93 2787 .channels_min = 1,
9e6e96a1
MB		 2788 .channels_max = 2,
2789 .rates = WM8994_RATES,
2790 .formats = WM8994_FORMATS,
2791 },
a8462bde 2792 .capture = {
9e6e96a1 2793 .stream_name = "AIF3 Capture",
b1e43d93 2794 .channels_min = 1,
9e6e96a1
MB		 2795 .channels_max = 2,
2796 .rates = WM8994_RATES,
2797 .formats = WM8994_FORMATS,
2798 },
778a76e2 2799 .ops = &wm8994_aif3_dai_ops,
9e6e96a1
MB		 2800 }
2801};
9e6e96a1
MB		 2802
2803#ifdef CONFIG_PM
84b315ee 2804static int wm8994_suspend(struct snd_soc_codec *codec)
9e6e96a1 2805{
b2c812e2 2806 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2807 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 2808 int i, ret;
2809
ca629928
MB		 2810 switch (control->type) {
2811 case WM8994:
2812 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2813 break;
81204c84 2814 case WM1811:
af6b6fe4
MB		 2815 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2816 WM1811_JACKDET_MODE_MASK, 0);
2817 /* Fall through */
ca629928
MB		 2818 case WM8958:
2819 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2820 WM8958_MICD_ENA, 0);
2821 break;
2822 }
2823
9e6e96a1
MB		 2824 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2825 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
f701a2e5 2826 sizeof(struct wm8994_fll_config));
f0fba2ad 2827 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
9e6e96a1
MB		 2828 if (ret < 0)
2829 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2830 i + 1, ret);
2831 }
2832
2833 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2834
2835 return 0;
2836}
2837
f0fba2ad 2838static int wm8994_resume(struct snd_soc_codec *codec)
9e6e96a1 2839{
b2c812e2 2840 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2841 struct wm8994 *control = wm8994->wm8994;
9e6e96a1 2842 int i, ret;
c52fd021
DP		 2843 unsigned int val, mask;
2844
2845 if (wm8994->revision < 4) {
2846 /* force a HW read */
2847 val = wm8994_reg_read(codec->control_data,
2848 WM8994_POWER_MANAGEMENT_5);
2849
2850 /* modify the cache only */
2851 codec->cache_only = 1;
2852 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2853 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2854 val &= mask;
2855 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2856 mask, val);
2857 codec->cache_only = 0;
2858 }
9e6e96a1
MB		 2859
2860 /* Restore the registers */
ca9aef50
MB		 2861 ret = snd_soc_cache_sync(codec);
2862 if (ret != 0)
2863 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
9e6e96a1
MB		 2864
2865 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2866
2867 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
6a2f1ee1
MB		 2868 if (!wm8994->fll_suspend[i].out)
2869 continue;
2870
f0fba2ad 2871 ret = _wm8994_set_fll(codec, i + 1,
9e6e96a1
MB		 2872 wm8994->fll_suspend[i].src,
2873 wm8994->fll_suspend[i].in,
2874 wm8994->fll_suspend[i].out);
2875 if (ret < 0)
2876 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2877 i + 1, ret);
2878 }
2879
ca629928
MB		 2880 switch (control->type) {
2881 case WM8994:
2882 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2883 snd_soc_update_bits(codec, WM8994_MICBIAS,
2884 WM8994_MICD_ENA, WM8994_MICD_ENA);
2885 break;
81204c84 2886 case WM1811:
af6b6fe4
MB		 2887 if (wm8994->jackdet && wm8994->jack_cb) {
2888 /* Restart from idle */
2889 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2890 WM1811_JACKDET_MODE_MASK,
2891 WM1811_JACKDET_MODE_JACK);
2892 break;
2893 }
ca629928
MB		 2894 case WM8958:
2895 if (wm8994->jack_cb)
2896 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2897 WM8958_MICD_ENA, WM8958_MICD_ENA);
2898 break;
2899 }
2900
9e6e96a1
MB		 2901 return 0;
2902}
2903#else
2904#define wm8994_suspend NULL
2905#define wm8994_resume NULL
2906#endif
2907
2908static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2909{
f0fba2ad 2910 struct snd_soc_codec *codec = wm8994->codec;
9e6e96a1
MB		 2911 struct wm8994_pdata *pdata = wm8994->pdata;
2912 struct snd_kcontrol_new controls[] = {
2913 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2914 wm8994->retune_mobile_enum,
2915 wm8994_get_retune_mobile_enum,
2916 wm8994_put_retune_mobile_enum),
2917 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2918 wm8994->retune_mobile_enum,
2919 wm8994_get_retune_mobile_enum,
2920 wm8994_put_retune_mobile_enum),
2921 SOC_ENUM_EXT("AIF2 EQ Mode",
2922 wm8994->retune_mobile_enum,
2923 wm8994_get_retune_mobile_enum,
2924 wm8994_put_retune_mobile_enum),
2925 };
2926 int ret, i, j;
2927 const char **t;
2928
2929 /* We need an array of texts for the enum API but the number
2930 * of texts is likely to be less than the number of
2931 * configurations due to the sample rate dependency of the
2932 * configurations. */
2933 wm8994->num_retune_mobile_texts = 0;
2934 wm8994->retune_mobile_texts = NULL;
2935 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2936 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2937 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2938 wm8994->retune_mobile_texts[j]) == 0)
2939 break;
2940 }
2941
2942 if (j != wm8994->num_retune_mobile_texts)
2943 continue;
2944
2945 /* Expand the array... */
2946 t = krealloc(wm8994->retune_mobile_texts,
2947 sizeof(char *) *
2948 (wm8994->num_retune_mobile_texts + 1),
2949 GFP_KERNEL);
2950 if (t == NULL)
2951 continue;
2952
2953 /* ...store the new entry... */
2954 t[wm8994->num_retune_mobile_texts] =
2955 pdata->retune_mobile_cfgs[i].name;
2956
2957 /* ...and remember the new version. */
2958 wm8994->num_retune_mobile_texts++;
2959 wm8994->retune_mobile_texts = t;
2960 }
2961
2962 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2963 wm8994->num_retune_mobile_texts);
2964
2965 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2966 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2967
f0fba2ad 2968 ret = snd_soc_add_controls(wm8994->codec, controls,
9e6e96a1
MB		 2969 ARRAY_SIZE(controls));
2970 if (ret != 0)
f0fba2ad 2971 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2972 "Failed to add ReTune Mobile controls: %d\n", ret);
2973}
2974
2975static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2976{
f0fba2ad 2977 struct snd_soc_codec *codec = wm8994->codec;
9e6e96a1
MB		 2978 struct wm8994_pdata *pdata = wm8994->pdata;
2979 int ret, i;
2980
2981 if (!pdata)
2982 return;
2983
2984 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2985 pdata->lineout2_diff,
2986 pdata->lineout1fb,
2987 pdata->lineout2fb,
2988 pdata->jd_scthr,
2989 pdata->jd_thr,
2990 pdata->micbias1_lvl,
2991 pdata->micbias2_lvl);
2992
2993 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2994
2995 if (pdata->num_drc_cfgs) {
2996 struct snd_kcontrol_new controls[] = {
2997 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2998 wm8994_get_drc_enum, wm8994_put_drc_enum),
2999 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3000 wm8994_get_drc_enum, wm8994_put_drc_enum),
3001 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3002 wm8994_get_drc_enum, wm8994_put_drc_enum),
3003 };
3004
3005 /* We need an array of texts for the enum API */
7270cebe
MB		 3006 wm8994->drc_texts = devm_kzalloc(wm8994->codec->dev,
3007 sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
9e6e96a1 3008 if (!wm8994->drc_texts) {
f0fba2ad 3009 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 3010 "Failed to allocate %d DRC config texts\n",
3011 pdata->num_drc_cfgs);
3012 return;
3013 }
3014
3015 for (i = 0; i < pdata->num_drc_cfgs; i++)
3016 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3017
3018 wm8994->drc_enum.max = pdata->num_drc_cfgs;
3019 wm8994->drc_enum.texts = wm8994->drc_texts;
3020
f0fba2ad 3021 ret = snd_soc_add_controls(wm8994->codec, controls,
9e6e96a1
MB		 3022 ARRAY_SIZE(controls));
3023 if (ret != 0)
f0fba2ad 3024 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 3025 "Failed to add DRC mode controls: %d\n", ret);
3026
3027 for (i = 0; i < WM8994_NUM_DRC; i++)
3028 wm8994_set_drc(codec, i);
3029 }
3030
3031 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3032 pdata->num_retune_mobile_cfgs);
3033
3034 if (pdata->num_retune_mobile_cfgs)
3035 wm8994_handle_retune_mobile_pdata(wm8994);
3036 else
f0fba2ad 3037 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
9e6e96a1 3038 ARRAY_SIZE(wm8994_eq_controls));
48e028ec
MB		 3039
3040 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3041 if (pdata->micbias[i]) {
3042 snd_soc_write(codec, WM8958_MICBIAS1 + i,
3043 pdata->micbias[i] & 0xffff);
3044 }
3045 }
9e6e96a1
MB		 3046}
3047
88766984
MB		 3048/**
3049 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3050 *
3051 * @codec: WM8994 codec
3052 * @jack: jack to report detection events on
3053 * @micbias: microphone bias to detect on
3054 * @det: value to report for presence detection
3055 * @shrt: value to report for short detection
3056 *
3057 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3058 * being used to bring out signals to the processor then only platform
5ab230a7 3059 * data configuration is needed for WM8994 and processor GPIOs should
88766984
MB		 3060 * be configured using snd_soc_jack_add_gpios() instead.
3061 *
3062 * Configuration of detection levels is available via the micbias1_lvl
3063 * and micbias2_lvl platform data members.
3064 */
3065int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3066 int micbias, int det, int shrt)
3067{
b2c812e2 3068 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
88766984 3069 struct wm8994_micdet *micdet;
2a8a856d 3070 struct wm8994 *control = wm8994->wm8994;
88766984
MB		 3071 int reg;
3072
3a423157
MB		 3073 if (control->type != WM8994)
3074 return -EINVAL;
3075
88766984
MB		 3076 switch (micbias) {
3077 case 1:
3078 micdet = &wm8994->micdet[0];
3079 break;
3080 case 2:
3081 micdet = &wm8994->micdet[1];
3082 break;
3083 default:
3084 return -EINVAL;
3085 }
3086
3087 dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
3088 micbias, det, shrt);
3089
3090 /* Store the configuration */
3091 micdet->jack = jack;
3092 micdet->det = det;
3093 micdet->shrt = shrt;
3094
3095 /* If either of the jacks is set up then enable detection */
3096 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3097 reg = WM8994_MICD_ENA;
3098 else
3099 reg = 0;
3100
3101 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3102
3103 return 0;
3104}
3105EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3106
3107static irqreturn_t wm8994_mic_irq(int irq, void *data)
3108{
3109 struct wm8994_priv *priv = data;
f0fba2ad 3110 struct snd_soc_codec *codec = priv->codec;
88766984
MB		 3111 int reg;
3112 int report;
3113
7116f452 3114#ifndef CONFIG_SND_SOC_WM8994_MODULE
2bbb5d66 3115 trace_snd_soc_jack_irq(dev_name(codec->dev));
7116f452 3116#endif
2bbb5d66 3117
88766984
MB		 3118 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
3119 if (reg < 0) {
3120 dev_err(codec->dev, "Failed to read microphone status: %d\n",
3121 reg);
3122 return IRQ_HANDLED;
3123 }
3124
3125 dev_dbg(codec->dev, "Microphone status: %x\n", reg);
3126
3127 report = 0;
3128 if (reg & WM8994_MIC1_DET_STS)
3129 report |= priv->micdet[0].det;
3130 if (reg & WM8994_MIC1_SHRT_STS)
3131 report |= priv->micdet[0].shrt;
3132 snd_soc_jack_report(priv->micdet[0].jack, report,
3133 priv->micdet[0].det | priv->micdet[0].shrt);
3134
3135 report = 0;
3136 if (reg & WM8994_MIC2_DET_STS)
3137 report |= priv->micdet[1].det;
3138 if (reg & WM8994_MIC2_SHRT_STS)
3139 report |= priv->micdet[1].shrt;
3140 snd_soc_jack_report(priv->micdet[1].jack, report,
3141 priv->micdet[1].det | priv->micdet[1].shrt);
3142
3143 return IRQ_HANDLED;
3144}
3145
821edd2f
MB		 3146/* Default microphone detection handler for WM8958 - the user can
3147 * override this if they wish.
3148 */
3149static void wm8958_default_micdet(u16 status, void *data)
3150{
3151 struct snd_soc_codec *codec = data;
3152 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
4585790d 3153 int report;
821edd2f 3154
a1691343
MB		 3155 dev_dbg(codec->dev, "MICDET %x\n", status);
3156
af6b6fe4 3157 /* Either nothing present or just starting detection */
b00adf76 3158 if (!(status & WM8958_MICD_STS)) {
af6b6fe4
MB		 3159 if (!wm8994->jackdet) {
3160 /* If nothing present then clear our statuses */
3161 dev_dbg(codec->dev, "Detected open circuit\n");
3162 wm8994->jack_mic = false;
3163 wm8994->mic_detecting = true;
b00adf76 3164
af6b6fe4 3165 wm8958_micd_set_rate(codec);
b00adf76 3166
af6b6fe4
MB		 3167 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3168 wm8994->btn_mask |
3169 SND_JACK_HEADSET);
3170 }
b00adf76
MB		 3171 return;
3172 }
821edd2f 3173
b00adf76
MB		 3174 /* If the measurement is showing a high impedence we've got a
3175 * microphone.
3176 */
157a75e6 3177 if (wm8994->mic_detecting && (status & 0x600)) {
b00adf76
MB		 3178 dev_dbg(codec->dev, "Detected microphone\n");
3179
157a75e6 3180 wm8994->mic_detecting = false;
b00adf76
MB		 3181 wm8994->jack_mic = true;
3182
3183 wm8958_micd_set_rate(codec);
3184
3185 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3186 SND_JACK_HEADSET);
3187 }
821edd2f 3188
b00adf76 3189
157a75e6 3190 if (wm8994->mic_detecting && status & 0x4) {
b00adf76 3191 dev_dbg(codec->dev, "Detected headphone\n");
157a75e6 3192 wm8994->mic_detecting = false;
b00adf76
MB		 3193
3194 wm8958_micd_set_rate(codec);
3195
3196 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3197 SND_JACK_HEADSET);
af6b6fe4
MB		 3198
3199 /* If we have jackdet that will detect removal */
3200 if (wm8994->jackdet) {
3201 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3202 WM8958_MICD_ENA, 0);
3203
3204 wm1811_jackdet_set_mode(codec,
3205 WM1811_JACKDET_MODE_JACK);
3206 }
b00adf76
MB		 3207 }
3208
3209 /* Report short circuit as a button */
3210 if (wm8994->jack_mic) {
4585790d 3211 report = 0;
b00adf76 3212 if (status & 0x4)
4585790d
MB		 3213 report |= SND_JACK_BTN_0;
3214
3215 if (status & 0x8)
3216 report |= SND_JACK_BTN_1;
3217
3218 if (status & 0x10)
3219 report |= SND_JACK_BTN_2;
3220
3221 if (status & 0x20)
3222 report |= SND_JACK_BTN_3;
3223
3224 if (status & 0x40)
3225 report |= SND_JACK_BTN_4;
3226
3227 if (status & 0x80)
3228 report |= SND_JACK_BTN_5;
3229
3230 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3231 wm8994->btn_mask);
b00adf76 3232 }
821edd2f
MB		 3233}
3234
af6b6fe4
MB		 3235static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3236{
3237 struct wm8994_priv *wm8994 = data;
3238 struct snd_soc_codec *codec = wm8994->codec;
3239 int reg;
3240
3241 mutex_lock(&wm8994->accdet_lock);
3242
3243 reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3244 if (reg < 0) {
3245 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3246 mutex_unlock(&wm8994->accdet_lock);
3247 return IRQ_NONE;
3248 }
3249
3250 dev_dbg(codec->dev, "JACKDET %x\n", reg);
3251
3252 if (reg & WM1811_JACKDET_LVL) {
3253 dev_dbg(codec->dev, "Jack detected\n");
3254
3255 snd_soc_jack_report(wm8994->micdet[0].jack,
3256 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3257
3258 /*
3259 * Start off measument of microphone impedence to find
3260 * out what's actually there.
3261 */
3262 wm8994->mic_detecting = true;
3263 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
3264 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3265 WM8958_MICD_ENA, WM8958_MICD_ENA);
3266 } else {
3267 dev_dbg(codec->dev, "Jack not detected\n");
3268
3269 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3270 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3271 wm8994->btn_mask);
3272
3273 wm8994->mic_detecting = false;
3274 wm8994->jack_mic = false;
3275 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3276 WM8958_MICD_ENA, 0);
3277 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3278 }
3279
3280 mutex_unlock(&wm8994->accdet_lock);
3281
3282 return IRQ_HANDLED;
3283}
3284
821edd2f
MB		 3285/**
3286 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3287 *
3288 * @codec: WM8958 codec
3289 * @jack: jack to report detection events on
3290 *
3291 * Enable microphone detection functionality for the WM8958. By
3292 * default simple detection which supports the detection of up to 6
3293 * buttons plus video and microphone functionality is supported.
3294 *
3295 * The WM8958 has an advanced jack detection facility which is able to
3296 * support complex accessory detection, especially when used in
3297 * conjunction with external circuitry. In order to provide maximum
3298 * flexiblity a callback is provided which allows a completely custom
3299 * detection algorithm.
3300 */
3301int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3302 wm8958_micdet_cb cb, void *cb_data)
3303{
3304 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 3305 struct wm8994 *control = wm8994->wm8994;
4585790d 3306 u16 micd_lvl_sel;
821edd2f 3307
81204c84
MB		 3308 switch (control->type) {
3309 case WM1811:
3310 case WM8958:
3311 break;
3312 default:
821edd2f 3313 return -EINVAL;
81204c84 3314 }
821edd2f
MB		 3315
3316 if (jack) {
3317 if (!cb) {
3318 dev_dbg(codec->dev, "Using default micdet callback\n");
3319 cb = wm8958_default_micdet;
3320 cb_data = codec;
3321 }
3322
4cdf5e49
MB		 3323 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
3324
821edd2f
MB		 3325 wm8994->micdet[0].jack = jack;
3326 wm8994->jack_cb = cb;
3327 wm8994->jack_cb_data = cb_data;
3328
157a75e6 3329 wm8994->mic_detecting = true;
b00adf76
MB		 3330 wm8994->jack_mic = false;
3331
3332 wm8958_micd_set_rate(codec);
3333
4585790d
MB		 3334 /* Detect microphones and short circuits by default */
3335 if (wm8994->pdata->micd_lvl_sel)
3336 micd_lvl_sel = wm8994->pdata->micd_lvl_sel;
3337 else
3338 micd_lvl_sel = 0x41;
3339
3340 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3341 SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3342 SND_JACK_BTN_4 | SND_JACK_BTN_5;
3343
b00adf76 3344 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
4585790d 3345 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
b00adf76 3346
af6b6fe4
MB		 3347 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3348
3349 /*
3350 * If we can use jack detection start off with that,
3351 * otherwise jump straight to microphone detection.
3352 */
3353 if (wm8994->jackdet) {
3354 snd_soc_update_bits(codec, WM8994_LDO_1,
3355 WM8994_LDO1_DISCH, 0);
3356 wm1811_jackdet_set_mode(codec,
3357 WM1811_JACKDET_MODE_JACK);
3358 } else {
3359 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3360 WM8958_MICD_ENA, WM8958_MICD_ENA);
3361 }
3362
821edd2f
MB		 3363 } else {
3364 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3365 WM8958_MICD_ENA, 0);
4cdf5e49 3366 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
821edd2f
MB		 3367 }
3368
3369 return 0;
3370}
3371EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3372
3373static irqreturn_t wm8958_mic_irq(int irq, void *data)
3374{
3375 struct wm8994_priv *wm8994 = data;
3376 struct snd_soc_codec *codec = wm8994->codec;
19940b3d 3377 int reg, count;
821edd2f 3378
af6b6fe4
MB		 3379 mutex_lock(&wm8994->accdet_lock);
3380
3381 /*
3382 * Jack detection may have detected a removal simulataneously
3383 * with an update of the MICDET status; if so it will have
3384 * stopped detection and we can ignore this interrupt.
3385 */
3386 if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA)) {
3387 mutex_unlock(&wm8994->accdet_lock);
3388 return IRQ_HANDLED;
3389 }
3390
19940b3d
MB		 3391 /* We may occasionally read a detection without an impedence
3392 * range being provided - if that happens loop again.
3393 */
3394 count = 10;
3395 do {
3396 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3397 if (reg < 0) {
af6b6fe4 3398 mutex_unlock(&wm8994->accdet_lock);
19940b3d
MB		 3399 dev_err(codec->dev,
3400 "Failed to read mic detect status: %d\n",
3401 reg);
3402 return IRQ_NONE;
3403 }
821edd2f 3404
19940b3d
MB		 3405 if (!(reg & WM8958_MICD_VALID)) {
3406 dev_dbg(codec->dev, "Mic detect data not valid\n");
3407 goto out;
3408 }
3409
3410 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3411 break;
3412
3413 msleep(1);
3414 } while (count--);
3415
3416 if (count == 0)
3417 dev_warn(codec->dev, "No impedence range reported for jack\n");
821edd2f 3418
7116f452 3419#ifndef CONFIG_SND_SOC_WM8994_MODULE
2bbb5d66 3420 trace_snd_soc_jack_irq(dev_name(codec->dev));
7116f452 3421#endif
2bbb5d66 3422
821edd2f
MB		 3423 if (wm8994->jack_cb)
3424 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3425 else
3426 dev_warn(codec->dev, "Accessory detection with no callback\n");
3427
3428out:
af6b6fe4
MB		 3429 mutex_unlock(&wm8994->accdet_lock);
3430
821edd2f
MB		 3431 return IRQ_HANDLED;
3432}
3433
3b1af3f8
MB		 3434static irqreturn_t wm8994_fifo_error(int irq, void *data)
3435{
3436 struct snd_soc_codec *codec = data;
3437
3438 dev_err(codec->dev, "FIFO error\n");
3439
3440 return IRQ_HANDLED;
3441}
3442
f0b182b0
MB		 3443static irqreturn_t wm8994_temp_warn(int irq, void *data)
3444{
3445 struct snd_soc_codec *codec = data;
3446
3447 dev_err(codec->dev, "Thermal warning\n");
3448
3449 return IRQ_HANDLED;
3450}
3451
3452static irqreturn_t wm8994_temp_shut(int irq, void *data)
3453{
3454 struct snd_soc_codec *codec = data;
3455
3456 dev_crit(codec->dev, "Thermal shutdown\n");
3457
3458 return IRQ_HANDLED;
3459}
3460
f0fba2ad 3461static int wm8994_codec_probe(struct snd_soc_codec *codec)
9e6e96a1 3462{
3a423157 3463 struct wm8994 *control;
9e6e96a1 3464 struct wm8994_priv *wm8994;
ce6120cc 3465 struct snd_soc_dapm_context *dapm = &codec->dapm;
ec62dbd7 3466 int ret, i;
9e6e96a1 3467
f0fba2ad 3468 codec->control_data = dev_get_drvdata(codec->dev->parent);
3a423157 3469 control = codec->control_data;
9e6e96a1 3470
7270cebe
MB		 3471 wm8994 = devm_kzalloc(codec->dev, sizeof(struct wm8994_priv),
3472 GFP_KERNEL);
f0fba2ad 3473 if (wm8994 == NULL)
9e6e96a1 3474 return -ENOMEM;
b2c812e2 3475 snd_soc_codec_set_drvdata(codec, wm8994);
f0fba2ad 3476
2a8a856d
MB		 3477
3478 wm8994->wm8994 = dev_get_drvdata(codec->dev->parent);
f0fba2ad
LG		 3479 wm8994->pdata = dev_get_platdata(codec->dev->parent);
3480 wm8994->codec = codec;
9e6e96a1 3481
af6b6fe4
MB		 3482 mutex_init(&wm8994->accdet_lock);
3483
c7ebf932
MB		 3484 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3485 init_completion(&wm8994->fll_locked[i]);
3486
9b7c525d
MB		 3487 if (wm8994->pdata && wm8994->pdata->micdet_irq)
3488 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
3489 else if (wm8994->pdata && wm8994->pdata->irq_base)
3490 wm8994->micdet_irq = wm8994->pdata->irq_base +
3491 WM8994_IRQ_MIC1_DET;
3492
39fb51a1
MB		 3493 pm_runtime_enable(codec->dev);
3494 pm_runtime_resume(codec->dev);
3495
ca9aef50
MB		 3496 /* Read our current status back from the chip - we don't want to
3497 * reset as this may interfere with the GPIO or LDO operation. */
3498 for (i = 0; i < WM8994_CACHE_SIZE; i++) {
d4754ec9 3499 if (!wm8994_readable(codec, i) || wm8994_volatile(codec, i))
ca9aef50 3500 continue;
9e6e96a1 3501
ca9aef50
MB		 3502 ret = wm8994_reg_read(codec->control_data, i);
3503 if (ret <= 0)
3504 continue;
3505
3506 ret = snd_soc_cache_write(codec, i, ret);
3507 if (ret != 0) {
3508 dev_err(codec->dev,
3509 "Failed to initialise cache for 0x%x: %d\n",
3510 i, ret);
3511 goto err;
3512 }
3513 }
9e6e96a1
MB		 3514
3515 /* Set revision-specific configuration */
b6b05691 3516 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3a423157
MB		 3517 switch (control->type) {
3518 case WM8994:
3519 switch (wm8994->revision) {
3520 case 2:
3521 case 3:
4537c4e7
MB		 3522 wm8994->hubs.dcs_codes_l = -5;
3523 wm8994->hubs.dcs_codes_r = -5;
3a423157
MB		 3524 wm8994->hubs.hp_startup_mode = 1;
3525 wm8994->hubs.dcs_readback_mode = 1;
f9acf9fe 3526 wm8994->hubs.series_startup = 1;
3a423157
MB		 3527 break;
3528 default:
79ef0abc 3529 wm8994->hubs.dcs_readback_mode = 2;
3a423157
MB		 3530 break;
3531 }
280ec8b7 3532 break;
3a423157
MB		 3533
3534 case WM8958:
8437f700 3535 wm8994->hubs.dcs_readback_mode = 1;
9e6e96a1 3536 break;
3a423157 3537
81204c84
MB		 3538 case WM1811:
3539 wm8994->hubs.dcs_readback_mode = 2;
3540 wm8994->hubs.no_series_update = 1;
3541
3542 switch (wm8994->revision) {
3543 case 0:
3544 case 1:
fc8e6e86
MB		 3545 case 2:
3546 case 3:
6473a148
MB		 3547 wm8994->hubs.dcs_codes_l = -9;
3548 wm8994->hubs.dcs_codes_r = -5;
81204c84
MB		 3549 break;
3550 default:
3551 break;
3552 }
3553
3554 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3555 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
3556 break;
3557
9e6e96a1
MB		 3558 default:
3559 break;
3560 }
9e6e96a1 3561
2a8a856d 3562 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
3b1af3f8 3563 wm8994_fifo_error, "FIFO error", codec);
2a8a856d 3564 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
f0b182b0 3565 wm8994_temp_warn, "Thermal warning", codec);
2a8a856d 3566 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
f0b182b0 3567 wm8994_temp_shut, "Thermal shutdown", codec);
3b1af3f8 3568
2a8a856d 3569 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f
MB		 3570 wm_hubs_dcs_done, "DC servo done",
3571 &wm8994->hubs);
3572 if (ret == 0)
3573 wm8994->hubs.dcs_done_irq = true;
3574
3a423157
MB		 3575 switch (control->type) {
3576 case WM8994:
9b7c525d
MB		 3577 if (wm8994->micdet_irq) {
3578 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3579 wm8994_mic_irq,
3580 IRQF_TRIGGER_RISING,
3581 "Mic1 detect",
3582 wm8994);
3583 if (ret != 0)
3584 dev_warn(codec->dev,
3585 "Failed to request Mic1 detect IRQ: %d\n",
3586 ret);
3587 }
3a423157 3588
2a8a856d 3589 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3590 WM8994_IRQ_MIC1_SHRT,
3591 wm8994_mic_irq, "Mic 1 short",
3592 wm8994);
3593 if (ret != 0)
3594 dev_warn(codec->dev,
3595 "Failed to request Mic1 short IRQ: %d\n",
3596 ret);
3597
2a8a856d 3598 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3599 WM8994_IRQ_MIC2_DET,
3600 wm8994_mic_irq, "Mic 2 detect",
3601 wm8994);
3602 if (ret != 0)
3603 dev_warn(codec->dev,
3604 "Failed to request Mic2 detect IRQ: %d\n",
3605 ret);
3606
2a8a856d 3607 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3608 WM8994_IRQ_MIC2_SHRT,
3609 wm8994_mic_irq, "Mic 2 short",
3610 wm8994);
3611 if (ret != 0)
3612 dev_warn(codec->dev,
3613 "Failed to request Mic2 short IRQ: %d\n",
3614 ret);
3615 break;
821edd2f
MB		 3616
3617 case WM8958:
81204c84 3618 case WM1811:
9b7c525d
MB		 3619 if (wm8994->micdet_irq) {
3620 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3621 wm8958_mic_irq,
3622 IRQF_TRIGGER_RISING,
3623 "Mic detect",
3624 wm8994);
3625 if (ret != 0)
3626 dev_warn(codec->dev,
3627 "Failed to request Mic detect IRQ: %d\n",
3628 ret);
3629 }
3a423157 3630 }
88766984 3631
af6b6fe4
MB		 3632 switch (control->type) {
3633 case WM1811:
3634 if (wm8994->revision > 1) {
3635 ret = wm8994_request_irq(wm8994->wm8994,
3636 WM8994_IRQ_GPIO(6),
3637 wm1811_jackdet_irq, "JACKDET",
3638 wm8994);
3639 if (ret == 0)
3640 wm8994->jackdet = true;
3641 }
3642 break;
3643 default:
3644 break;
3645 }
3646
c7ebf932
MB		 3647 wm8994->fll_locked_irq = true;
3648 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
2a8a856d 3649 ret = wm8994_request_irq(wm8994->wm8994,
c7ebf932
MB		 3650 WM8994_IRQ_FLL1_LOCK + i,
3651 wm8994_fll_locked_irq, "FLL lock",
3652 &wm8994->fll_locked[i]);
3653 if (ret != 0)
3654 wm8994->fll_locked_irq = false;
3655 }
3656
9e6e96a1
MB		 3657 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3658 * configured on init - if a system wants to do this dynamically
3659 * at runtime we can deal with that then.
3660 */
3661 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1);
3662 if (ret < 0) {
3663 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
88766984 3664 goto err_irq;
9e6e96a1
MB		 3665 }
3666 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3667 wm8994->lrclk_shared[0] = 1;
3668 wm8994_dai[0].symmetric_rates = 1;
3669 } else {
3670 wm8994->lrclk_shared[0] = 0;
3671 }
3672
3673 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6);
3674 if (ret < 0) {
3675 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
88766984 3676 goto err_irq;
9e6e96a1
MB		 3677 }
3678 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3679 wm8994->lrclk_shared[1] = 1;
3680 wm8994_dai[1].symmetric_rates = 1;
3681 } else {
3682 wm8994->lrclk_shared[1] = 0;
3683 }
3684
9e6e96a1
MB		 3685 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3686
9e6e96a1 3687 /* Latch volume updates (right only; we always do left then right). */
baa81603
MB		 3688 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME,
3689 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
9e6e96a1
MB		 3690 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3691 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
baa81603
MB		 3692 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME,
3693 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
9e6e96a1
MB		 3694 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3695 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
baa81603
MB		 3696 snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME,
3697 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
9e6e96a1
MB		 3698 snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3699 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
baa81603
MB		 3700 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME,
3701 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
9e6e96a1
MB		 3702 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3703 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
baa81603
MB		 3704 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME,
3705 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
9e6e96a1
MB		 3706 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3707 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
baa81603
MB		 3708 snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME,
3709 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
9e6e96a1
MB		 3710 snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3711 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
baa81603
MB		 3712 snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME,
3713 WM8994_DAC1_VU, WM8994_DAC1_VU);
9e6e96a1
MB		 3714 snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3715 WM8994_DAC1_VU, WM8994_DAC1_VU);
baa81603
MB		 3716 snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME,
3717 WM8994_DAC2_VU, WM8994_DAC2_VU);
9e6e96a1
MB		 3718 snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3719 WM8994_DAC2_VU, WM8994_DAC2_VU);
3720
3721 /* Set the low bit of the 3D stereo depth so TLV matches */
3722 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3723 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3724 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3725 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3726 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3727 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3728 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3729 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3730 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3731
5b739670
MB		 3732 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3733 * use this; it only affects behaviour on idle TDM clock
3734 * cycles. */
3735 switch (control->type) {
3736 case WM8994:
3737 case WM8958:
3738 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3739 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3740 break;
3741 default:
3742 break;
3743 }
d1ce6b20 3744
500fa30e
MB		 3745 /* Put MICBIAS into bypass mode by default on newer devices */
3746 switch (control->type) {
3747 case WM8958:
3748 case WM1811:
3749 snd_soc_update_bits(codec, WM8958_MICBIAS1,
3750 WM8958_MICB1_MODE, WM8958_MICB1_MODE);
3751 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3752 WM8958_MICB2_MODE, WM8958_MICB2_MODE);
3753 break;
3754 default:
3755 break;
3756 }
3757
9e6e96a1
MB		 3758 wm8994_update_class_w(codec);
3759
f0fba2ad 3760 wm8994_handle_pdata(wm8994);
9e6e96a1 3761
f0fba2ad
LG		 3762 wm_hubs_add_analogue_controls(codec);
3763 snd_soc_add_controls(codec, wm8994_snd_controls,
3764 ARRAY_SIZE(wm8994_snd_controls));
ce6120cc 3765 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
f0fba2ad 3766 ARRAY_SIZE(wm8994_dapm_widgets));
c4431df0
MB		 3767
3768 switch (control->type) {
3769 case WM8994:
3770 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3771 ARRAY_SIZE(wm8994_specific_dapm_widgets));
c52fd021 3772 if (wm8994->revision < 4) {
173efa09
DP		 3773 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3774 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
04d28681
DP		 3775 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3776 ARRAY_SIZE(wm8994_adc_revd_widgets));
c52fd021
DP		 3777 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3778 ARRAY_SIZE(wm8994_dac_revd_widgets));
3779 } else {
173efa09
DP		 3780 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3781 ARRAY_SIZE(wm8994_lateclk_widgets));
04d28681
DP		 3782 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3783 ARRAY_SIZE(wm8994_adc_widgets));
c52fd021
DP		 3784 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3785 ARRAY_SIZE(wm8994_dac_widgets));
3786 }
c4431df0
MB		 3787 break;
3788 case WM8958:
3789 snd_soc_add_controls(codec, wm8958_snd_controls,
3790 ARRAY_SIZE(wm8958_snd_controls));
3791 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3792 ARRAY_SIZE(wm8958_dapm_widgets));
780e2806
MB		 3793 if (wm8994->revision < 1) {
3794 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3795 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3796 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3797 ARRAY_SIZE(wm8994_adc_revd_widgets));
3798 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3799 ARRAY_SIZE(wm8994_dac_revd_widgets));
3800 } else {
3801 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3802 ARRAY_SIZE(wm8994_lateclk_widgets));
3803 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3804 ARRAY_SIZE(wm8994_adc_widgets));
3805 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3806 ARRAY_SIZE(wm8994_dac_widgets));
3807 }
c4431df0 3808 break;
81204c84
MB		 3809
3810 case WM1811:
3811 snd_soc_add_controls(codec, wm8958_snd_controls,
3812 ARRAY_SIZE(wm8958_snd_controls));
3813 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3814 ARRAY_SIZE(wm8958_dapm_widgets));
3815 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3816 ARRAY_SIZE(wm8994_lateclk_widgets));
3817 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3818 ARRAY_SIZE(wm8994_adc_widgets));
3819 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3820 ARRAY_SIZE(wm8994_dac_widgets));
3821 break;
c4431df0
MB		 3822 }
3823
3824
f0fba2ad 3825 wm_hubs_add_analogue_routes(codec, 0, 0);
ce6120cc 3826 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
9e6e96a1 3827
c4431df0
MB		 3828 switch (control->type) {
3829 case WM8994:
3830 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3831 ARRAY_SIZE(wm8994_intercon));
6ed8f148 3832
173efa09 3833 if (wm8994->revision < 4) {
6ed8f148
MB		 3834 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3835 ARRAY_SIZE(wm8994_revd_intercon));
173efa09
DP		 3836 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3837 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3838 } else {
3839 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3840 ARRAY_SIZE(wm8994_lateclk_intercon));
3841 }
c4431df0
MB		 3842 break;
3843 case WM8958:
780e2806
MB		 3844 if (wm8994->revision < 1) {
3845 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3846 ARRAY_SIZE(wm8994_revd_intercon));
3847 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3848 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3849 } else {
3850 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3851 ARRAY_SIZE(wm8994_lateclk_intercon));
3852 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3853 ARRAY_SIZE(wm8958_intercon));
3854 }
f701a2e5
MB		 3855
3856 wm8958_dsp2_init(codec);
c4431df0 3857 break;
81204c84
MB		 3858 case WM1811:
3859 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3860 ARRAY_SIZE(wm8994_lateclk_intercon));
3861 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3862 ARRAY_SIZE(wm8958_intercon));
3863 break;
c4431df0
MB		 3864 }
3865
9e6e96a1
MB		 3866 return 0;
3867
88766984 3868err_irq:
af6b6fe4
MB		 3869 if (wm8994->jackdet)
3870 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
2a8a856d
MB		 3871 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
3872 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
3873 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
9b7c525d
MB		 3874 if (wm8994->micdet_irq)
3875 free_irq(wm8994->micdet_irq, wm8994);
c7ebf932 3876 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2a8a856d 3877 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
c7ebf932 3878 &wm8994->fll_locked[i]);
2a8a856d 3879 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f 3880 &wm8994->hubs);
2a8a856d
MB		 3881 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
3882 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
3883 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
9e6e96a1
MB		 3884 return ret;
3885}
3886
f0fba2ad 3887static int wm8994_codec_remove(struct snd_soc_codec *codec)
9e6e96a1 3888{
f0fba2ad 3889 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 3890 struct wm8994 *control = wm8994->wm8994;
c7ebf932 3891 int i;
9e6e96a1
MB		 3892
3893 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
f0fba2ad 3894
39fb51a1
MB		 3895 pm_runtime_disable(codec->dev);
3896
c7ebf932 3897 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2a8a856d 3898 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
c7ebf932
MB		 3899 &wm8994->fll_locked[i]);
3900
2a8a856d 3901 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f 3902 &wm8994->hubs);
2a8a856d
MB		 3903 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
3904 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
3905 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
b30ead5f 3906
af6b6fe4
MB		 3907 if (wm8994->jackdet)
3908 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
3909
3a423157
MB		 3910 switch (control->type) {
3911 case WM8994:
9b7c525d
MB		 3912 if (wm8994->micdet_irq)
3913 free_irq(wm8994->micdet_irq, wm8994);
2a8a856d 3914 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
3a423157 3915 wm8994);
2a8a856d 3916 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
3a423157 3917 wm8994);
2a8a856d 3918 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
3a423157
MB		 3919 wm8994);
3920 break;
821edd2f 3921
81204c84 3922 case WM1811:
821edd2f 3923 case WM8958:
9b7c525d
MB		 3924 if (wm8994->micdet_irq)
3925 free_irq(wm8994->micdet_irq, wm8994);
821edd2f 3926 break;
3a423157 3927 }
fbbf5920
MB		 3928 if (wm8994->mbc)
3929 release_firmware(wm8994->mbc);
09e10d7f
MB		 3930 if (wm8994->mbc_vss)
3931 release_firmware(wm8994->mbc_vss);
31215871
MB		 3932 if (wm8994->enh_eq)
3933 release_firmware(wm8994->enh_eq);
24fb2b11 3934 kfree(wm8994->retune_mobile_texts);
9e6e96a1
MB		 3935
3936 return 0;
3937}
3938
f0fba2ad
LG		 3939static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3940 .probe = wm8994_codec_probe,
3941 .remove = wm8994_codec_remove,
3942 .suspend = wm8994_suspend,
3943 .resume = wm8994_resume,
ca9aef50
MB		 3944 .read = wm8994_read,
3945 .write = wm8994_write,
eba19fdd
MB		 3946 .readable_register = wm8994_readable,
3947 .volatile_register = wm8994_volatile,
f0fba2ad 3948 .set_bias_level = wm8994_set_bias_level,
ca9aef50
MB		 3949
3950 .reg_cache_size = WM8994_CACHE_SIZE,
3951 .reg_cache_default = wm8994_reg_defaults,
3952 .reg_word_size = 2,
2e19b0c8 3953 .compress_type = SND_SOC_RBTREE_COMPRESSION,
f0fba2ad
LG		 3954};
3955
3956static int __devinit wm8994_probe(struct platform_device *pdev)
3957{
3958 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3959 wm8994_dai, ARRAY_SIZE(wm8994_dai));
3960}
3961
3962static int __devexit wm8994_remove(struct platform_device *pdev)
3963{
3964 snd_soc_unregister_codec(&pdev->dev);
3965 return 0;
3966}
3967
9e6e96a1
MB		 3968static struct platform_driver wm8994_codec_driver = {
3969 .driver = {
3970 .name = "wm8994-codec",
3971 .owner = THIS_MODULE,
3972 },
f0fba2ad
LG		 3973 .probe = wm8994_probe,
3974 .remove = __devexit_p(wm8994_remove),
9e6e96a1
MB		 3975};
3976
5bbcc3c0 3977module_platform_driver(wm8994_codec_driver);
9e6e96a1
MB		 3978
3979MODULE_DESCRIPTION("ASoC WM8994 driver");
3980MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3981MODULE_LICENSE("GPL");
3982MODULE_ALIAS("platform:wm8994-codec");
Linux kernel - Deliverables
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