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Merge branch 'for-2.6.37' into for-2.6.38
[deliverable/linux.git] / sound / soc / codecs / wm8994.c
CommitLineData
9e6e96a1
MB		 1/*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
39fb51a1 21#include <linux/pm_runtime.h>
9e6e96a1 22#include <linux/regulator/consumer.h>
5a0e3ad6 23#include <linux/slab.h>
9e6e96a1 24#include <sound/core.h>
821edd2f 25#include <sound/jack.h>
9e6e96a1
MB		 26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
9e6e96a1
MB		 29#include <sound/initval.h>
30#include <sound/tlv.h>
31
32#include <linux/mfd/wm8994/core.h>
33#include <linux/mfd/wm8994/registers.h>
34#include <linux/mfd/wm8994/pdata.h>
35#include <linux/mfd/wm8994/gpio.h>
36
37#include "wm8994.h"
38#include "wm_hubs.h"
39
9e6e96a1
MB		 40struct fll_config {
41 int src;
42 int in;
43 int out;
44};
45
46#define WM8994_NUM_DRC 3
47#define WM8994_NUM_EQ 3
48
49static int wm8994_drc_base[] = {
50 WM8994_AIF1_DRC1_1,
51 WM8994_AIF1_DRC2_1,
52 WM8994_AIF2_DRC_1,
53};
54
55static int wm8994_retune_mobile_base[] = {
56 WM8994_AIF1_DAC1_EQ_GAINS_1,
57 WM8994_AIF1_DAC2_EQ_GAINS_1,
58 WM8994_AIF2_EQ_GAINS_1,
59};
60
88766984
MB		 61struct wm8994_micdet {
62 struct snd_soc_jack *jack;
63 int det;
64 int shrt;
65};
66
9e6e96a1
MB		 67/* codec private data */
68struct wm8994_priv {
69 struct wm_hubs_data hubs;
f0fba2ad
LG		 70 enum snd_soc_control_type control_type;
71 void *control_data;
72 struct snd_soc_codec *codec;
9e6e96a1
MB		 73 int sysclk[2];
74 int sysclk_rate[2];
75 int mclk[2];
76 int aifclk[2];
77 struct fll_config fll[2], fll_suspend[2];
78
79 int dac_rates[2];
80 int lrclk_shared[2];
81
d6addcc9
MB		 82 int mbc_ena[3];
83
9e6e96a1
MB		 84 /* Platform dependant DRC configuration */
85 const char **drc_texts;
86 int drc_cfg[WM8994_NUM_DRC];
87 struct soc_enum drc_enum;
88
89 /* Platform dependant ReTune mobile configuration */
90 int num_retune_mobile_texts;
91 const char **retune_mobile_texts;
92 int retune_mobile_cfg[WM8994_NUM_EQ];
93 struct soc_enum retune_mobile_enum;
94
88766984
MB		 95 struct wm8994_micdet micdet[2];
96
821edd2f
MB		 97 wm8958_micdet_cb jack_cb;
98 void *jack_cb_data;
99 bool jack_is_mic;
100 bool jack_is_video;
101
b6b05691 102 int revision;
9e6e96a1
MB		 103 struct wm8994_pdata *pdata;
104};
105
9e6e96a1
MB		 106static int wm8994_readable(unsigned int reg)
107{
e88ff1e6
MB		 108 switch (reg) {
109 case WM8994_GPIO_1:
110 case WM8994_GPIO_2:
111 case WM8994_GPIO_3:
112 case WM8994_GPIO_4:
113 case WM8994_GPIO_5:
114 case WM8994_GPIO_6:
115 case WM8994_GPIO_7:
116 case WM8994_GPIO_8:
117 case WM8994_GPIO_9:
118 case WM8994_GPIO_10:
119 case WM8994_GPIO_11:
120 case WM8994_INTERRUPT_STATUS_1:
121 case WM8994_INTERRUPT_STATUS_2:
122 case WM8994_INTERRUPT_RAW_STATUS_2:
123 return 1;
124 default:
125 break;
126 }
127
7b306dae 128 if (reg >= WM8994_CACHE_SIZE)
9e6e96a1 129 return 0;
7b306dae 130 return wm8994_access_masks[reg].readable != 0;
9e6e96a1
MB		 131}
132
133static int wm8994_volatile(unsigned int reg)
134{
ca9aef50 135 if (reg >= WM8994_CACHE_SIZE)
9e6e96a1
MB		 136 return 1;
137
138 switch (reg) {
139 case WM8994_SOFTWARE_RESET:
140 case WM8994_CHIP_REVISION:
141 case WM8994_DC_SERVO_1:
142 case WM8994_DC_SERVO_READBACK:
143 case WM8994_RATE_STATUS:
144 case WM8994_LDO_1:
145 case WM8994_LDO_2:
d6addcc9 146 case WM8958_DSP2_EXECCONTROL:
821edd2f 147 case WM8958_MIC_DETECT_3:
9e6e96a1
MB		 148 return 1;
149 default:
150 return 0;
151 }
152}
153
154static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
155 unsigned int value)
156{
ca9aef50 157 int ret;
9e6e96a1
MB		 158
159 BUG_ON(reg > WM8994_MAX_REGISTER);
160
ca9aef50
MB		 161 if (!wm8994_volatile(reg)) {
162 ret = snd_soc_cache_write(codec, reg, value);
163 if (ret != 0)
164 dev_err(codec->dev, "Cache write to %x failed: %d\n",
165 reg, ret);
166 }
9e6e96a1
MB		 167
168 return wm8994_reg_write(codec->control_data, reg, value);
169}
170
171static unsigned int wm8994_read(struct snd_soc_codec *codec,
172 unsigned int reg)
173{
ca9aef50
MB		 174 unsigned int val;
175 int ret;
9e6e96a1
MB		 176
177 BUG_ON(reg > WM8994_MAX_REGISTER);
178
ca9aef50
MB		 179 if (!wm8994_volatile(reg) && wm8994_readable(reg) &&
180 reg < codec->driver->reg_cache_size) {
181 ret = snd_soc_cache_read(codec, reg, &val);
182 if (ret >= 0)
183 return val;
184 else
185 dev_err(codec->dev, "Cache read from %x failed: %d\n",
186 reg, ret);
187 }
188
189 return wm8994_reg_read(codec->control_data, reg);
9e6e96a1
MB		 190}
191
192static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
193{
b2c812e2 194 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 195 int rate;
196 int reg1 = 0;
197 int offset;
198
199 if (aif)
200 offset = 4;
201 else
202 offset = 0;
203
204 switch (wm8994->sysclk[aif]) {
205 case WM8994_SYSCLK_MCLK1:
206 rate = wm8994->mclk[0];
207 break;
208
209 case WM8994_SYSCLK_MCLK2:
210 reg1 |= 0x8;
211 rate = wm8994->mclk[1];
212 break;
213
214 case WM8994_SYSCLK_FLL1:
215 reg1 |= 0x10;
216 rate = wm8994->fll[0].out;
217 break;
218
219 case WM8994_SYSCLK_FLL2:
220 reg1 |= 0x18;
221 rate = wm8994->fll[1].out;
222 break;
223
224 default:
225 return -EINVAL;
226 }
227
228 if (rate >= 13500000) {
229 rate /= 2;
230 reg1 |= WM8994_AIF1CLK_DIV;
231
232 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
233 aif + 1, rate);
234 }
5e5e2bef
MB		 235
236 if (rate && rate < 3000000)
237 dev_warn(codec->dev, "AIF%dCLK is %dHz, should be >=3MHz for optimal performance\n",
238 aif + 1, rate);
239
9e6e96a1
MB		 240 wm8994->aifclk[aif] = rate;
241
242 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
243 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
244 reg1);
245
246 return 0;
247}
248
249static int configure_clock(struct snd_soc_codec *codec)
250{
b2c812e2 251 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 252 int old, new;
253
254 /* Bring up the AIF clocks first */
255 configure_aif_clock(codec, 0);
256 configure_aif_clock(codec, 1);
257
258 /* Then switch CLK_SYS over to the higher of them; a change
259 * can only happen as a result of a clocking change which can
260 * only be made outside of DAPM so we can safely redo the
261 * clocking.
262 */
263
264 /* If they're equal it doesn't matter which is used */
265 if (wm8994->aifclk[0] == wm8994->aifclk[1])
266 return 0;
267
268 if (wm8994->aifclk[0] < wm8994->aifclk[1])
269 new = WM8994_SYSCLK_SRC;
270 else
271 new = 0;
272
273 old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC;
274
275 /* If there's no change then we're done. */
276 if (old == new)
277 return 0;
278
279 snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new);
280
ce6120cc 281 snd_soc_dapm_sync(&codec->dapm);
9e6e96a1
MB		 282
283 return 0;
284}
285
286static int check_clk_sys(struct snd_soc_dapm_widget *source,
287 struct snd_soc_dapm_widget *sink)
288{
289 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
290 const char *clk;
291
292 /* Check what we're currently using for CLK_SYS */
293 if (reg & WM8994_SYSCLK_SRC)
294 clk = "AIF2CLK";
295 else
296 clk = "AIF1CLK";
297
298 return strcmp(source->name, clk) == 0;
299}
300
301static const char *sidetone_hpf_text[] = {
302 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
303};
304
305static const struct soc_enum sidetone_hpf =
306 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
307
308static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
309static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
310static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
311static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
312static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
313
314#define WM8994_DRC_SWITCH(xname, reg, shift) \
315{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
316 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
317 .put = wm8994_put_drc_sw, \
318 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
319
320static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
321 struct snd_ctl_elem_value *ucontrol)
322{
323 struct soc_mixer_control *mc =
324 (struct soc_mixer_control *)kcontrol->private_value;
325 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
326 int mask, ret;
327
328 /* Can't enable both ADC and DAC paths simultaneously */
329 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
330 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
331 WM8994_AIF1ADC1R_DRC_ENA_MASK;
332 else
333 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
334
335 ret = snd_soc_read(codec, mc->reg);
336 if (ret < 0)
337 return ret;
338 if (ret & mask)
339 return -EINVAL;
340
341 return snd_soc_put_volsw(kcontrol, ucontrol);
342}
343
9e6e96a1
MB		 344static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
345{
b2c812e2 346 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 347 struct wm8994_pdata *pdata = wm8994->pdata;
348 int base = wm8994_drc_base[drc];
349 int cfg = wm8994->drc_cfg[drc];
350 int save, i;
351
352 /* Save any enables; the configuration should clear them. */
353 save = snd_soc_read(codec, base);
354 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
355 WM8994_AIF1ADC1R_DRC_ENA;
356
357 for (i = 0; i < WM8994_DRC_REGS; i++)
358 snd_soc_update_bits(codec, base + i, 0xffff,
359 pdata->drc_cfgs[cfg].regs[i]);
360
361 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
362 WM8994_AIF1ADC1L_DRC_ENA |
363 WM8994_AIF1ADC1R_DRC_ENA, save);
364}
365
366/* Icky as hell but saves code duplication */
367static int wm8994_get_drc(const char *name)
368{
369 if (strcmp(name, "AIF1DRC1 Mode") == 0)
370 return 0;
371 if (strcmp(name, "AIF1DRC2 Mode") == 0)
372 return 1;
373 if (strcmp(name, "AIF2DRC Mode") == 0)
374 return 2;
375 return -EINVAL;
376}
377
378static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
379 struct snd_ctl_elem_value *ucontrol)
380{
381 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 382 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 383 struct wm8994_pdata *pdata = wm8994->pdata;
384 int drc = wm8994_get_drc(kcontrol->id.name);
385 int value = ucontrol->value.integer.value[0];
386
387 if (drc < 0)
388 return drc;
389
390 if (value >= pdata->num_drc_cfgs)
391 return -EINVAL;
392
393 wm8994->drc_cfg[drc] = value;
394
395 wm8994_set_drc(codec, drc);
396
397 return 0;
398}
399
400static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
401 struct snd_ctl_elem_value *ucontrol)
402{
403 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 404 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 405 int drc = wm8994_get_drc(kcontrol->id.name);
406
407 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
408
409 return 0;
410}
411
412static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
413{
b2c812e2 414 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 415 struct wm8994_pdata *pdata = wm8994->pdata;
416 int base = wm8994_retune_mobile_base[block];
417 int iface, best, best_val, save, i, cfg;
418
419 if (!pdata || !wm8994->num_retune_mobile_texts)
420 return;
421
422 switch (block) {
423 case 0:
424 case 1:
425 iface = 0;
426 break;
427 case 2:
428 iface = 1;
429 break;
430 default:
431 return;
432 }
433
434 /* Find the version of the currently selected configuration
435 * with the nearest sample rate. */
436 cfg = wm8994->retune_mobile_cfg[block];
437 best = 0;
438 best_val = INT_MAX;
439 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
440 if (strcmp(pdata->retune_mobile_cfgs[i].name,
441 wm8994->retune_mobile_texts[cfg]) == 0 &&
442 abs(pdata->retune_mobile_cfgs[i].rate
443 - wm8994->dac_rates[iface]) < best_val) {
444 best = i;
445 best_val = abs(pdata->retune_mobile_cfgs[i].rate
446 - wm8994->dac_rates[iface]);
447 }
448 }
449
450 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
451 block,
452 pdata->retune_mobile_cfgs[best].name,
453 pdata->retune_mobile_cfgs[best].rate,
454 wm8994->dac_rates[iface]);
455
456 /* The EQ will be disabled while reconfiguring it, remember the
457 * current configuration.
458 */
459 save = snd_soc_read(codec, base);
460 save &= WM8994_AIF1DAC1_EQ_ENA;
461
462 for (i = 0; i < WM8994_EQ_REGS; i++)
463 snd_soc_update_bits(codec, base + i, 0xffff,
464 pdata->retune_mobile_cfgs[best].regs[i]);
465
466 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
467}
468
469/* Icky as hell but saves code duplication */
470static int wm8994_get_retune_mobile_block(const char *name)
471{
472 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
473 return 0;
474 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
475 return 1;
476 if (strcmp(name, "AIF2 EQ Mode") == 0)
477 return 2;
478 return -EINVAL;
479}
480
481static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
482 struct snd_ctl_elem_value *ucontrol)
483{
484 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 485 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 486 struct wm8994_pdata *pdata = wm8994->pdata;
487 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
488 int value = ucontrol->value.integer.value[0];
489
490 if (block < 0)
491 return block;
492
493 if (value >= pdata->num_retune_mobile_cfgs)
494 return -EINVAL;
495
496 wm8994->retune_mobile_cfg[block] = value;
497
498 wm8994_set_retune_mobile(codec, block);
499
500 return 0;
501}
502
503static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
504 struct snd_ctl_elem_value *ucontrol)
505{
506 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 507 struct wm8994_priv *wm8994 =snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 508 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
509
510 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
511
512 return 0;
513}
514
96b101ef 515static const char *aif_chan_src_text[] = {
f554885f
MB		 516 "Left", "Right"
517};
518
96b101ef
MB		 519static const struct soc_enum aif1adcl_src =
520 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
521
522static const struct soc_enum aif1adcr_src =
523 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
524
525static const struct soc_enum aif2adcl_src =
526 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
527
528static const struct soc_enum aif2adcr_src =
529 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
530
f554885f 531static const struct soc_enum aif1dacl_src =
96b101ef 532 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 533
534static const struct soc_enum aif1dacr_src =
96b101ef 535 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f
MB		 536
537static const struct soc_enum aif2dacl_src =
96b101ef 538 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 539
540static const struct soc_enum aif2dacr_src =
96b101ef 541 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f 542
d6addcc9
MB		 543static void wm8958_mbc_apply(struct snd_soc_codec *codec, int mbc, int start)
544{
545 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
546 int pwr_reg = snd_soc_read(codec, WM8994_POWER_MANAGEMENT_5);
547 int ena, reg, aif;
548
549 switch (mbc) {
550 case 0:
551 pwr_reg &= (WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA);
552 aif = 0;
553 break;
554 case 1:
555 pwr_reg &= (WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
556 aif = 0;
557 break;
558 case 2:
559 pwr_reg &= (WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA);
560 aif = 1;
561 break;
562 default:
563 BUG();
564 return;
565 }
566
567 /* We can only enable the MBC if the AIF is enabled and we
568 * want it to be enabled. */
569 ena = pwr_reg && wm8994->mbc_ena[mbc];
570
571 reg = snd_soc_read(codec, WM8958_DSP2_PROGRAM);
572
573 dev_dbg(codec->dev, "MBC %d startup: %d, power: %x, DSP: %x\n",
574 mbc, start, pwr_reg, reg);
575
576 if (start && ena) {
577 /* If the DSP is already running then noop */
578 if (reg & WM8958_DSP2_ENA)
579 return;
580
581 /* Switch the clock over to the appropriate AIF */
582 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
583 WM8958_DSP2CLK_SRC | WM8958_DSP2CLK_ENA,
584 aif << WM8958_DSP2CLK_SRC_SHIFT |
585 WM8958_DSP2CLK_ENA);
586
587 snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
588 WM8958_DSP2_ENA, WM8958_DSP2_ENA);
589
590 /* TODO: Apply any user specified MBC settings */
591
592 /* Run the DSP */
593 snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
594 WM8958_DSP2_RUNR);
595
596 /* And we're off! */
597 snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
598 WM8958_MBC_ENA | WM8958_MBC_SEL_MASK,
599 mbc << WM8958_MBC_SEL_SHIFT |
600 WM8958_MBC_ENA);
601 } else {
602 /* If the DSP is already stopped then noop */
603 if (!(reg & WM8958_DSP2_ENA))
604 return;
605
606 snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
607 WM8958_MBC_ENA, 0);
608 snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
609 WM8958_DSP2_ENA, 0);
610 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
611 WM8958_DSP2CLK_ENA, 0);
612 }
613}
614
615static int wm8958_aif_ev(struct snd_soc_dapm_widget *w,
616 struct snd_kcontrol *kcontrol, int event)
617{
618 struct snd_soc_codec *codec = w->codec;
619 int mbc;
620
621 switch (w->shift) {
622 case 13:
623 case 12:
624 mbc = 2;
625 break;
626 case 11:
627 case 10:
628 mbc = 1;
629 break;
630 case 9:
631 case 8:
632 mbc = 0;
633 break;
634 default:
635 BUG();
636 return -EINVAL;
637 }
638
639 switch (event) {
640 case SND_SOC_DAPM_POST_PMU:
641 wm8958_mbc_apply(codec, mbc, 1);
642 break;
643 case SND_SOC_DAPM_POST_PMD:
644 wm8958_mbc_apply(codec, mbc, 0);
645 break;
646 }
647
648 return 0;
649}
650
651static int wm8958_mbc_info(struct snd_kcontrol *kcontrol,
652 struct snd_ctl_elem_info *uinfo)
653{
654 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
655 uinfo->count = 1;
656 uinfo->value.integer.min = 0;
657 uinfo->value.integer.max = 1;
658 return 0;
659}
660
661static int wm8958_mbc_get(struct snd_kcontrol *kcontrol,
662 struct snd_ctl_elem_value *ucontrol)
663{
664 int mbc = kcontrol->private_value;
665 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
666 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
667
668 ucontrol->value.integer.value[0] = wm8994->mbc_ena[mbc];
669
670 return 0;
671}
672
673static int wm8958_mbc_put(struct snd_kcontrol *kcontrol,
674 struct snd_ctl_elem_value *ucontrol)
675{
676 int mbc = kcontrol->private_value;
677 int i;
678 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
679 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
680
681 if (ucontrol->value.integer.value[0] > 1)
682 return -EINVAL;
683
684 for (i = 0; i < ARRAY_SIZE(wm8994->mbc_ena); i++) {
685 if (mbc != i && wm8994->mbc_ena[i]) {
686 dev_dbg(codec->dev, "MBC %d active already\n", mbc);
687 return -EBUSY;
688 }
689 }
690
691 wm8994->mbc_ena[mbc] = ucontrol->value.integer.value[0];
692
693 wm8958_mbc_apply(codec, mbc, wm8994->mbc_ena[mbc]);
694
695 return 0;
696}
697
698#define WM8958_MBC_SWITCH(xname, xval) {\
699 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
700 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
701 .info = wm8958_mbc_info, \
702 .get = wm8958_mbc_get, .put = wm8958_mbc_put, \
703 .private_value = xval }
704
9e6e96a1
MB		 705static const struct snd_kcontrol_new wm8994_snd_controls[] = {
706SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
707 WM8994_AIF1_ADC1_RIGHT_VOLUME,
708 1, 119, 0, digital_tlv),
709SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
710 WM8994_AIF1_ADC2_RIGHT_VOLUME,
711 1, 119, 0, digital_tlv),
712SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
713 WM8994_AIF2_ADC_RIGHT_VOLUME,
714 1, 119, 0, digital_tlv),
715
96b101ef
MB		 716SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
717SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
718SOC_ENUM("AIF2ADCL Source", aif1adcl_src),
719SOC_ENUM("AIF2ADCR Source", aif1adcr_src),
720
f554885f
MB		 721SOC_ENUM("AIF1DACL Source", aif1dacl_src),
722SOC_ENUM("AIF1DACR Source", aif1dacr_src),
723SOC_ENUM("AIF2DACL Source", aif1dacl_src),
724SOC_ENUM("AIF2DACR Source", aif1dacr_src),
725
9e6e96a1
MB		 726SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
727 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
728SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
729 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
730SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
731 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
732
733SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
734SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
735
736SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
737SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
738SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
739
740WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
741WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
742WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
743
744WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
745WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
746WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
747
748WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
749WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
750WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
751
752SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
753 5, 12, 0, st_tlv),
754SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
755 0, 12, 0, st_tlv),
756SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
757 5, 12, 0, st_tlv),
758SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
759 0, 12, 0, st_tlv),
760SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
761SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
762
763SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
764 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
765SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
766 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
767
768SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
769 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
770SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
771 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
772
773SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
774 6, 1, 1, wm_hubs_spkmix_tlv),
775SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
776 2, 1, 1, wm_hubs_spkmix_tlv),
777
778SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
779 6, 1, 1, wm_hubs_spkmix_tlv),
780SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
781 2, 1, 1, wm_hubs_spkmix_tlv),
782
783SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
784 10, 15, 0, wm8994_3d_tlv),
785SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
786 8, 1, 0),
787SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
788 10, 15, 0, wm8994_3d_tlv),
789SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
790 8, 1, 0),
791SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
792 10, 15, 0, wm8994_3d_tlv),
793SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
794 8, 1, 0),
795};
796
797static const struct snd_kcontrol_new wm8994_eq_controls[] = {
798SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
799 eq_tlv),
800SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
801 eq_tlv),
802SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
803 eq_tlv),
804SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
805 eq_tlv),
806SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
807 eq_tlv),
808
809SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
810 eq_tlv),
811SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
812 eq_tlv),
813SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
814 eq_tlv),
815SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
816 eq_tlv),
817SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
818 eq_tlv),
819
820SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
821 eq_tlv),
822SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
823 eq_tlv),
824SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
825 eq_tlv),
826SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
827 eq_tlv),
828SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
829 eq_tlv),
830};
831
c4431df0
MB		 832static const struct snd_kcontrol_new wm8958_snd_controls[] = {
833SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
d6addcc9
MB		 834WM8958_MBC_SWITCH("AIF1DAC1 MBC Switch", 0),
835WM8958_MBC_SWITCH("AIF1DAC2 MBC Switch", 1),
836WM8958_MBC_SWITCH("AIF2DAC MBC Switch", 2),
c4431df0
MB		 837};
838
9e6e96a1
MB		 839static int clk_sys_event(struct snd_soc_dapm_widget *w,
840 struct snd_kcontrol *kcontrol, int event)
841{
842 struct snd_soc_codec *codec = w->codec;
843
844 switch (event) {
845 case SND_SOC_DAPM_PRE_PMU:
846 return configure_clock(codec);
847
848 case SND_SOC_DAPM_POST_PMD:
849 configure_clock(codec);
850 break;
851 }
852
853 return 0;
854}
855
856static void wm8994_update_class_w(struct snd_soc_codec *codec)
857{
fec6dd83 858 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 859 int enable = 1;
860 int source = 0; /* GCC flow analysis can't track enable */
861 int reg, reg_r;
862
863 /* Only support direct DAC->headphone paths */
864 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
865 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
ee839a21 866 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
9e6e96a1
MB		 867 enable = 0;
868 }
869
870 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
871 if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
ee839a21 872 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
9e6e96a1
MB		 873 enable = 0;
874 }
875
876 /* We also need the same setting for L/R and only one path */
877 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
878 switch (reg) {
879 case WM8994_AIF2DACL_TO_DAC1L:
ee839a21 880 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
9e6e96a1
MB		 881 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
882 break;
883 case WM8994_AIF1DAC2L_TO_DAC1L:
ee839a21 884 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
9e6e96a1
MB		 885 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
886 break;
887 case WM8994_AIF1DAC1L_TO_DAC1L:
ee839a21 888 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
9e6e96a1
MB		 889 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
890 break;
891 default:
ee839a21 892 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
9e6e96a1
MB		 893 enable = 0;
894 break;
895 }
896
897 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
898 if (reg_r != reg) {
ee839a21 899 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
9e6e96a1
MB		 900 enable = 0;
901 }
902
903 if (enable) {
904 dev_dbg(codec->dev, "Class W enabled\n");
905 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
906 WM8994_CP_DYN_PWR |
907 WM8994_CP_DYN_SRC_SEL_MASK,
908 source | WM8994_CP_DYN_PWR);
fec6dd83 909 wm8994->hubs.class_w = true;
9e6e96a1
MB		 910
911 } else {
912 dev_dbg(codec->dev, "Class W disabled\n");
913 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
914 WM8994_CP_DYN_PWR, 0);
fec6dd83 915 wm8994->hubs.class_w = false;
9e6e96a1
MB		 916 }
917}
918
919static const char *hp_mux_text[] = {
920 "Mixer",
921 "DAC",
922};
923
924#define WM8994_HP_ENUM(xname, xenum) \
925{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
926 .info = snd_soc_info_enum_double, \
927 .get = snd_soc_dapm_get_enum_double, \
928 .put = wm8994_put_hp_enum, \
929 .private_value = (unsigned long)&xenum }
930
931static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
932 struct snd_ctl_elem_value *ucontrol)
933{
934 struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
935 struct snd_soc_codec *codec = w->codec;
936 int ret;
937
938 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
939
940 wm8994_update_class_w(codec);
941
942 return ret;
943}
944
945static const struct soc_enum hpl_enum =
946 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
947
948static const struct snd_kcontrol_new hpl_mux =
949 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
950
951static const struct soc_enum hpr_enum =
952 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
953
954static const struct snd_kcontrol_new hpr_mux =
955 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
956
957static const char *adc_mux_text[] = {
958 "ADC",
959 "DMIC",
960};
961
962static const struct soc_enum adc_enum =
963 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
964
965static const struct snd_kcontrol_new adcl_mux =
966 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
967
968static const struct snd_kcontrol_new adcr_mux =
969 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
970
971static const struct snd_kcontrol_new left_speaker_mixer[] = {
972SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
973SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
974SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
975SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
976SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
977};
978
979static const struct snd_kcontrol_new right_speaker_mixer[] = {
980SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
981SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
982SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
983SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
984SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
985};
986
987/* Debugging; dump chip status after DAPM transitions */
988static int post_ev(struct snd_soc_dapm_widget *w,
989 struct snd_kcontrol *kcontrol, int event)
990{
991 struct snd_soc_codec *codec = w->codec;
992 dev_dbg(codec->dev, "SRC status: %x\n",
993 snd_soc_read(codec,
994 WM8994_RATE_STATUS));
995 return 0;
996}
997
998static const struct snd_kcontrol_new aif1adc1l_mix[] = {
999SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1000 1, 1, 0),
1001SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1002 0, 1, 0),
1003};
1004
1005static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1006SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1007 1, 1, 0),
1008SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1009 0, 1, 0),
1010};
1011
a3257ba8
MB		 1012static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1013SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1014 1, 1, 0),
1015SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1016 0, 1, 0),
1017};
1018
1019static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1020SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1021 1, 1, 0),
1022SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1023 0, 1, 0),
1024};
1025
9e6e96a1
MB		 1026static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1027SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1028 5, 1, 0),
1029SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1030 4, 1, 0),
1031SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1032 2, 1, 0),
1033SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1034 1, 1, 0),
1035SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1036 0, 1, 0),
1037};
1038
1039static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1040SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1041 5, 1, 0),
1042SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1043 4, 1, 0),
1044SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1045 2, 1, 0),
1046SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1047 1, 1, 0),
1048SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1049 0, 1, 0),
1050};
1051
1052#define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1053{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1054 .info = snd_soc_info_volsw, \
1055 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1056 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1057
1058static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1059 struct snd_ctl_elem_value *ucontrol)
1060{
1061 struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
1062 struct snd_soc_codec *codec = w->codec;
1063 int ret;
1064
1065 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1066
1067 wm8994_update_class_w(codec);
1068
1069 return ret;
1070}
1071
1072static const struct snd_kcontrol_new dac1l_mix[] = {
1073WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1074 5, 1, 0),
1075WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1076 4, 1, 0),
1077WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1078 2, 1, 0),
1079WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1080 1, 1, 0),
1081WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1082 0, 1, 0),
1083};
1084
1085static const struct snd_kcontrol_new dac1r_mix[] = {
1086WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1087 5, 1, 0),
1088WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1089 4, 1, 0),
1090WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1091 2, 1, 0),
1092WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1093 1, 1, 0),
1094WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1095 0, 1, 0),
1096};
1097
1098static const char *sidetone_text[] = {
1099 "ADC/DMIC1", "DMIC2",
1100};
1101
1102static const struct soc_enum sidetone1_enum =
1103 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1104
1105static const struct snd_kcontrol_new sidetone1_mux =
1106 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1107
1108static const struct soc_enum sidetone2_enum =
1109 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1110
1111static const struct snd_kcontrol_new sidetone2_mux =
1112 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1113
1114static const char *aif1dac_text[] = {
1115 "AIF1DACDAT", "AIF3DACDAT",
1116};
1117
1118static const struct soc_enum aif1dac_enum =
1119 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1120
1121static const struct snd_kcontrol_new aif1dac_mux =
1122 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1123
1124static const char *aif2dac_text[] = {
1125 "AIF2DACDAT", "AIF3DACDAT",
1126};
1127
1128static const struct soc_enum aif2dac_enum =
1129 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1130
1131static const struct snd_kcontrol_new aif2dac_mux =
1132 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1133
1134static const char *aif2adc_text[] = {
1135 "AIF2ADCDAT", "AIF3DACDAT",
1136};
1137
1138static const struct soc_enum aif2adc_enum =
1139 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1140
1141static const struct snd_kcontrol_new aif2adc_mux =
1142 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1143
1144static const char *aif3adc_text[] = {
c4431df0 1145 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
9e6e96a1
MB		 1146};
1147
c4431df0 1148static const struct soc_enum wm8994_aif3adc_enum =
9e6e96a1
MB		 1149 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1150
c4431df0
MB		 1151static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1152 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1153
1154static const struct soc_enum wm8958_aif3adc_enum =
1155 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1156
1157static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1158 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1159
1160static const char *mono_pcm_out_text[] = {
1161 "None", "AIF2ADCL", "AIF2ADCR",
1162};
1163
1164static const struct soc_enum mono_pcm_out_enum =
1165 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1166
1167static const struct snd_kcontrol_new mono_pcm_out_mux =
1168 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1169
1170static const char *aif2dac_src_text[] = {
1171 "AIF2", "AIF3",
1172};
1173
1174/* Note that these two control shouldn't be simultaneously switched to AIF3 */
1175static const struct soc_enum aif2dacl_src_enum =
1176 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1177
1178static const struct snd_kcontrol_new aif2dacl_src_mux =
1179 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1180
1181static const struct soc_enum aif2dacr_src_enum =
1182 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1183
1184static const struct snd_kcontrol_new aif2dacr_src_mux =
1185 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
9e6e96a1
MB		 1186
1187static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1188SND_SOC_DAPM_INPUT("DMIC1DAT"),
1189SND_SOC_DAPM_INPUT("DMIC2DAT"),
66b47fdb 1190SND_SOC_DAPM_INPUT("Clock"),
9e6e96a1
MB		 1191
1192SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1193 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1194
1195SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1196SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1197SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1198
1199SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
1200SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
1201
1202SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture",
1203 0, WM8994_POWER_MANAGEMENT_4, 9, 0),
1204SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture",
1205 0, WM8994_POWER_MANAGEMENT_4, 8, 0),
d6addcc9
MB		 1206SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1207 WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
1208 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1209SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1210 WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
1211 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
9e6e96a1
MB		 1212
1213SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture",
1214 0, WM8994_POWER_MANAGEMENT_4, 11, 0),
1215SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture",
1216 0, WM8994_POWER_MANAGEMENT_4, 10, 0),
d6addcc9
MB		 1217SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1218 WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
1219 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1220SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1221 WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
1222 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
9e6e96a1
MB		 1223
1224SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1225 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1226SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1227 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1228
a3257ba8
MB		 1229SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1230 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1231SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1232 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1233
9e6e96a1
MB		 1234SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1235 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1236SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1237 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1238
1239SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1240SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1241
1242SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1243 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1244SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1245 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1246
1247SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1248 WM8994_POWER_MANAGEMENT_4, 13, 0),
1249SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1250 WM8994_POWER_MANAGEMENT_4, 12, 0),
d6addcc9
MB		 1251SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1252 WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1253 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1254SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1255 WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1256 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
9e6e96a1
MB		 1257
1258SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1259SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1260SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1261
1262SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1263SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1264SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
9e6e96a1
MB		 1265
1266SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1267SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1268
1269SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1270
1271SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1272SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1273SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1274SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1275
1276/* Power is done with the muxes since the ADC power also controls the
1277 * downsampling chain, the chip will automatically manage the analogue
1278 * specific portions.
1279 */
1280SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1281SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1282
1283SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1284SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1285
1286SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1287SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1288SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1289SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1290
1291SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1292SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1293
1294SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1295 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1296SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1297 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1298
1299SND_SOC_DAPM_POST("Debug log", post_ev),
1300};
1301
c4431df0
MB		 1302static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1303SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1304};
9e6e96a1 1305
c4431df0
MB		 1306static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1307SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1308SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1309SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1310SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1311};
1312
1313static const struct snd_soc_dapm_route intercon[] = {
9e6e96a1
MB		 1314 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1315 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1316
1317 { "DSP1CLK", NULL, "CLK_SYS" },
1318 { "DSP2CLK", NULL, "CLK_SYS" },
1319 { "DSPINTCLK", NULL, "CLK_SYS" },
1320
1321 { "AIF1ADC1L", NULL, "AIF1CLK" },
1322 { "AIF1ADC1L", NULL, "DSP1CLK" },
1323 { "AIF1ADC1R", NULL, "AIF1CLK" },
1324 { "AIF1ADC1R", NULL, "DSP1CLK" },
1325 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1326
1327 { "AIF1DAC1L", NULL, "AIF1CLK" },
1328 { "AIF1DAC1L", NULL, "DSP1CLK" },
1329 { "AIF1DAC1R", NULL, "AIF1CLK" },
1330 { "AIF1DAC1R", NULL, "DSP1CLK" },
1331 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1332
1333 { "AIF1ADC2L", NULL, "AIF1CLK" },
1334 { "AIF1ADC2L", NULL, "DSP1CLK" },
1335 { "AIF1ADC2R", NULL, "AIF1CLK" },
1336 { "AIF1ADC2R", NULL, "DSP1CLK" },
1337 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1338
1339 { "AIF1DAC2L", NULL, "AIF1CLK" },
1340 { "AIF1DAC2L", NULL, "DSP1CLK" },
1341 { "AIF1DAC2R", NULL, "AIF1CLK" },
1342 { "AIF1DAC2R", NULL, "DSP1CLK" },
1343 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1344
1345 { "AIF2ADCL", NULL, "AIF2CLK" },
1346 { "AIF2ADCL", NULL, "DSP2CLK" },
1347 { "AIF2ADCR", NULL, "AIF2CLK" },
1348 { "AIF2ADCR", NULL, "DSP2CLK" },
1349 { "AIF2ADCR", NULL, "DSPINTCLK" },
1350
1351 { "AIF2DACL", NULL, "AIF2CLK" },
1352 { "AIF2DACL", NULL, "DSP2CLK" },
1353 { "AIF2DACR", NULL, "AIF2CLK" },
1354 { "AIF2DACR", NULL, "DSP2CLK" },
1355 { "AIF2DACR", NULL, "DSPINTCLK" },
1356
1357 { "DMIC1L", NULL, "DMIC1DAT" },
1358 { "DMIC1L", NULL, "CLK_SYS" },
1359 { "DMIC1R", NULL, "DMIC1DAT" },
1360 { "DMIC1R", NULL, "CLK_SYS" },
1361 { "DMIC2L", NULL, "DMIC2DAT" },
1362 { "DMIC2L", NULL, "CLK_SYS" },
1363 { "DMIC2R", NULL, "DMIC2DAT" },
1364 { "DMIC2R", NULL, "CLK_SYS" },
1365
1366 { "ADCL", NULL, "AIF1CLK" },
1367 { "ADCL", NULL, "DSP1CLK" },
1368 { "ADCL", NULL, "DSPINTCLK" },
1369
1370 { "ADCR", NULL, "AIF1CLK" },
1371 { "ADCR", NULL, "DSP1CLK" },
1372 { "ADCR", NULL, "DSPINTCLK" },
1373
1374 { "ADCL Mux", "ADC", "ADCL" },
1375 { "ADCL Mux", "DMIC", "DMIC1L" },
1376 { "ADCR Mux", "ADC", "ADCR" },
1377 { "ADCR Mux", "DMIC", "DMIC1R" },
1378
1379 { "DAC1L", NULL, "AIF1CLK" },
1380 { "DAC1L", NULL, "DSP1CLK" },
1381 { "DAC1L", NULL, "DSPINTCLK" },
1382
1383 { "DAC1R", NULL, "AIF1CLK" },
1384 { "DAC1R", NULL, "DSP1CLK" },
1385 { "DAC1R", NULL, "DSPINTCLK" },
1386
1387 { "DAC2L", NULL, "AIF2CLK" },
1388 { "DAC2L", NULL, "DSP2CLK" },
1389 { "DAC2L", NULL, "DSPINTCLK" },
1390
1391 { "DAC2R", NULL, "AIF2DACR" },
1392 { "DAC2R", NULL, "AIF2CLK" },
1393 { "DAC2R", NULL, "DSP2CLK" },
1394 { "DAC2R", NULL, "DSPINTCLK" },
1395
1396 { "TOCLK", NULL, "CLK_SYS" },
1397
1398 /* AIF1 outputs */
1399 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1400 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1401 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1402
1403 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1404 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1405 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1406
a3257ba8
MB		 1407 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1408 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1409 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1410
1411 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1412 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1413 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1414
9e6e96a1
MB		 1415 /* Pin level routing for AIF3 */
1416 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1417 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1418 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1419 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1420
9e6e96a1
MB		 1421 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1422 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1423 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1424 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1425 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1426 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1427 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1428
1429 /* DAC1 inputs */
1430 { "DAC1L", NULL, "DAC1L Mixer" },
1431 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1432 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1433 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1434 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1435 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1436
1437 { "DAC1R", NULL, "DAC1R Mixer" },
1438 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1439 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1440 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1441 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1442 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1443
1444 /* DAC2/AIF2 outputs */
1445 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1446 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1447 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1448 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1449 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1450 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1451 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1452
1453 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1454 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1455 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1456 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1457 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1458 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1459 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1460
1461 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1462
1463 /* AIF3 output */
1464 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1465 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1466 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1467 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1468 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1469 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1470 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1471 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1472
1473 /* Sidetone */
1474 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1475 { "Left Sidetone", "DMIC2", "DMIC2L" },
1476 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1477 { "Right Sidetone", "DMIC2", "DMIC2R" },
1478
1479 /* Output stages */
1480 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1481 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1482
1483 { "SPKL", "DAC1 Switch", "DAC1L" },
1484 { "SPKL", "DAC2 Switch", "DAC2L" },
1485
1486 { "SPKR", "DAC1 Switch", "DAC1R" },
1487 { "SPKR", "DAC2 Switch", "DAC2R" },
1488
1489 { "Left Headphone Mux", "DAC", "DAC1L" },
1490 { "Right Headphone Mux", "DAC", "DAC1R" },
1491};
1492
c4431df0
MB		 1493static const struct snd_soc_dapm_route wm8994_intercon[] = {
1494 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1495 { "AIF2DACR", NULL, "AIF2DAC Mux" },
1496};
1497
1498static const struct snd_soc_dapm_route wm8958_intercon[] = {
1499 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1500 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1501
1502 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1503 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1504 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1505 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1506
1507 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1508 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1509
1510 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1511};
1512
9e6e96a1
MB		 1513/* The size in bits of the FLL divide multiplied by 10
1514 * to allow rounding later */
1515#define FIXED_FLL_SIZE ((1 << 16) * 10)
1516
1517struct fll_div {
1518 u16 outdiv;
1519 u16 n;
1520 u16 k;
1521 u16 clk_ref_div;
1522 u16 fll_fratio;
1523};
1524
1525static int wm8994_get_fll_config(struct fll_div *fll,
1526 int freq_in, int freq_out)
1527{
1528 u64 Kpart;
1529 unsigned int K, Ndiv, Nmod;
1530
1531 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1532
1533 /* Scale the input frequency down to <= 13.5MHz */
1534 fll->clk_ref_div = 0;
1535 while (freq_in > 13500000) {
1536 fll->clk_ref_div++;
1537 freq_in /= 2;
1538
1539 if (fll->clk_ref_div > 3)
1540 return -EINVAL;
1541 }
1542 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1543
1544 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1545 fll->outdiv = 3;
1546 while (freq_out * (fll->outdiv + 1) < 90000000) {
1547 fll->outdiv++;
1548 if (fll->outdiv > 63)
1549 return -EINVAL;
1550 }
1551 freq_out *= fll->outdiv + 1;
1552 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1553
1554 if (freq_in > 1000000) {
1555 fll->fll_fratio = 0;
7d48a6ac
MB		 1556 } else if (freq_in > 256000) {
1557 fll->fll_fratio = 1;
1558 freq_in *= 2;
1559 } else if (freq_in > 128000) {
1560 fll->fll_fratio = 2;
1561 freq_in *= 4;
1562 } else if (freq_in > 64000) {
9e6e96a1
MB		 1563 fll->fll_fratio = 3;
1564 freq_in *= 8;
7d48a6ac
MB		 1565 } else {
1566 fll->fll_fratio = 4;
1567 freq_in *= 16;
9e6e96a1
MB		 1568 }
1569 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1570
1571 /* Now, calculate N.K */
1572 Ndiv = freq_out / freq_in;
1573
1574 fll->n = Ndiv;
1575 Nmod = freq_out % freq_in;
1576 pr_debug("Nmod=%d\n", Nmod);
1577
1578 /* Calculate fractional part - scale up so we can round. */
1579 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1580
1581 do_div(Kpart, freq_in);
1582
1583 K = Kpart & 0xFFFFFFFF;
1584
1585 if ((K % 10) >= 5)
1586 K += 5;
1587
1588 /* Move down to proper range now rounding is done */
1589 fll->k = K / 10;
1590
1591 pr_debug("N=%x K=%x\n", fll->n, fll->k);
1592
1593 return 0;
1594}
1595
f0fba2ad 1596static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
9e6e96a1
MB		 1597 unsigned int freq_in, unsigned int freq_out)
1598{
b2c812e2 1599 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 1600 int reg_offset, ret;
1601 struct fll_div fll;
1602 u16 reg, aif1, aif2;
1603
1604 aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1605 & WM8994_AIF1CLK_ENA;
1606
1607 aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1608 & WM8994_AIF2CLK_ENA;
1609
1610 switch (id) {
1611 case WM8994_FLL1:
1612 reg_offset = 0;
1613 id = 0;
1614 break;
1615 case WM8994_FLL2:
1616 reg_offset = 0x20;
1617 id = 1;
1618 break;
1619 default:
1620 return -EINVAL;
1621 }
1622
136ff2a2 1623 switch (src) {
7add84aa
MB		 1624 case 0:
1625 /* Allow no source specification when stopping */
1626 if (freq_out)
1627 return -EINVAL;
1628 break;
136ff2a2
MB		 1629 case WM8994_FLL_SRC_MCLK1:
1630 case WM8994_FLL_SRC_MCLK2:
1631 case WM8994_FLL_SRC_LRCLK:
1632 case WM8994_FLL_SRC_BCLK:
1633 break;
1634 default:
1635 return -EINVAL;
1636 }
1637
9e6e96a1
MB		 1638 /* Are we changing anything? */
1639 if (wm8994->fll[id].src == src &&
1640 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1641 return 0;
1642
1643 /* If we're stopping the FLL redo the old config - no
1644 * registers will actually be written but we avoid GCC flow
1645 * analysis bugs spewing warnings.
1646 */
1647 if (freq_out)
1648 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1649 else
1650 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1651 wm8994->fll[id].out);
1652 if (ret < 0)
1653 return ret;
1654
1655 /* Gate the AIF clocks while we reclock */
1656 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1657 WM8994_AIF1CLK_ENA, 0);
1658 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1659 WM8994_AIF2CLK_ENA, 0);
1660
1661 /* We always need to disable the FLL while reconfiguring */
1662 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1663 WM8994_FLL1_ENA, 0);
1664
1665 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1666 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1667 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1668 WM8994_FLL1_OUTDIV_MASK |
1669 WM8994_FLL1_FRATIO_MASK, reg);
1670
1671 snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1672
1673 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1674 WM8994_FLL1_N_MASK,
1675 fll.n << WM8994_FLL1_N_SHIFT);
1676
1677 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
136ff2a2
MB		 1678 WM8994_FLL1_REFCLK_DIV_MASK |
1679 WM8994_FLL1_REFCLK_SRC_MASK,
1680 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1681 (src - 1));
9e6e96a1
MB		 1682
1683 /* Enable (with fractional mode if required) */
1684 if (freq_out) {
1685 if (fll.k)
1686 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1687 else
1688 reg = WM8994_FLL1_ENA;
1689 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1690 WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1691 reg);
1692 }
1693
1694 wm8994->fll[id].in = freq_in;
1695 wm8994->fll[id].out = freq_out;
136ff2a2 1696 wm8994->fll[id].src = src;
9e6e96a1
MB		 1697
1698 /* Enable any gated AIF clocks */
1699 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1700 WM8994_AIF1CLK_ENA, aif1);
1701 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1702 WM8994_AIF2CLK_ENA, aif2);
1703
1704 configure_clock(codec);
1705
1706 return 0;
1707}
1708
f0fba2ad 1709
66b47fdb
MB		 1710static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1711
f0fba2ad
LG		 1712static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
1713 unsigned int freq_in, unsigned int freq_out)
1714{
1715 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
1716}
1717
9e6e96a1
MB		 1718static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
1719 int clk_id, unsigned int freq, int dir)
1720{
1721 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1722 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
66b47fdb 1723 int i;
9e6e96a1
MB		 1724
1725 switch (dai->id) {
1726 case 1:
1727 case 2:
1728 break;
1729
1730 default:
1731 /* AIF3 shares clocking with AIF1/2 */
1732 return -EINVAL;
1733 }
1734
1735 switch (clk_id) {
1736 case WM8994_SYSCLK_MCLK1:
1737 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
1738 wm8994->mclk[0] = freq;
1739 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
1740 dai->id, freq);
1741 break;
1742
1743 case WM8994_SYSCLK_MCLK2:
1744 /* TODO: Set GPIO AF */
1745 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
1746 wm8994->mclk[1] = freq;
1747 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
1748 dai->id, freq);
1749 break;
1750
1751 case WM8994_SYSCLK_FLL1:
1752 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
1753 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
1754 break;
1755
1756 case WM8994_SYSCLK_FLL2:
1757 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
1758 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
1759 break;
1760
66b47fdb
MB		 1761 case WM8994_SYSCLK_OPCLK:
1762 /* Special case - a division (times 10) is given and
1763 * no effect on main clocking.
1764 */
1765 if (freq) {
1766 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
1767 if (opclk_divs[i] == freq)
1768 break;
1769 if (i == ARRAY_SIZE(opclk_divs))
1770 return -EINVAL;
1771 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
1772 WM8994_OPCLK_DIV_MASK, i);
1773 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1774 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
1775 } else {
1776 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1777 WM8994_OPCLK_ENA, 0);
1778 }
1779
9e6e96a1
MB		 1780 default:
1781 return -EINVAL;
1782 }
1783
1784 configure_clock(codec);
1785
1786 return 0;
1787}
1788
1789static int wm8994_set_bias_level(struct snd_soc_codec *codec,
1790 enum snd_soc_bias_level level)
1791{
3a423157 1792 struct wm8994 *control = codec->control_data;
b6b05691
MB		 1793 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1794
9e6e96a1
MB		 1795 switch (level) {
1796 case SND_SOC_BIAS_ON:
1797 break;
1798
1799 case SND_SOC_BIAS_PREPARE:
1800 /* VMID=2x40k */
1801 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1802 WM8994_VMID_SEL_MASK, 0x2);
1803 break;
1804
1805 case SND_SOC_BIAS_STANDBY:
ce6120cc 1806 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
39fb51a1
MB		 1807 pm_runtime_get_sync(codec->dev);
1808
0c17b393
MB		 1809 /* Tweak DC servo and DSP configuration for
1810 * improved performance. */
3a423157 1811 if (control->type == WM8994 && wm8994->revision < 4) {
b6b05691
MB		 1812 /* Tweak DC servo and DSP configuration for
1813 * improved performance. */
1814 snd_soc_write(codec, 0x102, 0x3);
1815 snd_soc_write(codec, 0x56, 0x3);
1816 snd_soc_write(codec, 0x817, 0);
1817 snd_soc_write(codec, 0x102, 0);
1818 }
9e6e96a1
MB		 1819
1820 /* Discharge LINEOUT1 & 2 */
1821 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
1822 WM8994_LINEOUT1_DISCH |
1823 WM8994_LINEOUT2_DISCH,
1824 WM8994_LINEOUT1_DISCH |
1825 WM8994_LINEOUT2_DISCH);
1826
1827 /* Startup bias, VMID ramp & buffer */
1828 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1829 WM8994_STARTUP_BIAS_ENA |
1830 WM8994_VMID_BUF_ENA |
1831 WM8994_VMID_RAMP_MASK,
1832 WM8994_STARTUP_BIAS_ENA |
1833 WM8994_VMID_BUF_ENA |
1834 (0x11 << WM8994_VMID_RAMP_SHIFT));
1835
1836 /* Main bias enable, VMID=2x40k */
1837 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1838 WM8994_BIAS_ENA |
1839 WM8994_VMID_SEL_MASK,
1840 WM8994_BIAS_ENA | 0x2);
1841
1842 msleep(20);
1843 }
1844
1845 /* VMID=2x500k */
1846 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1847 WM8994_VMID_SEL_MASK, 0x4);
1848
1849 break;
1850
1851 case SND_SOC_BIAS_OFF:
ce6120cc 1852 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
d522ffbf
MB		 1853 /* Switch over to startup biases */
1854 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1855 WM8994_BIAS_SRC |
1856 WM8994_STARTUP_BIAS_ENA |
1857 WM8994_VMID_BUF_ENA |
1858 WM8994_VMID_RAMP_MASK,
1859 WM8994_BIAS_SRC |
1860 WM8994_STARTUP_BIAS_ENA |
1861 WM8994_VMID_BUF_ENA |
1862 (1 << WM8994_VMID_RAMP_SHIFT));
9e6e96a1 1863
d522ffbf
MB		 1864 /* Disable main biases */
1865 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1866 WM8994_BIAS_ENA |
1867 WM8994_VMID_SEL_MASK, 0);
9e6e96a1 1868
d522ffbf
MB		 1869 /* Discharge line */
1870 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
1871 WM8994_LINEOUT1_DISCH |
1872 WM8994_LINEOUT2_DISCH,
1873 WM8994_LINEOUT1_DISCH |
1874 WM8994_LINEOUT2_DISCH);
9e6e96a1 1875
d522ffbf 1876 msleep(5);
9e6e96a1 1877
d522ffbf
MB		 1878 /* Switch off startup biases */
1879 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1880 WM8994_BIAS_SRC |
1881 WM8994_STARTUP_BIAS_ENA |
1882 WM8994_VMID_BUF_ENA |
1883 WM8994_VMID_RAMP_MASK, 0);
39fb51a1
MB		 1884
1885 pm_runtime_put(codec->dev);
d522ffbf 1886 }
9e6e96a1
MB		 1887 break;
1888 }
ce6120cc 1889 codec->dapm.bias_level = level;
9e6e96a1
MB		 1890 return 0;
1891}
1892
1893static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1894{
1895 struct snd_soc_codec *codec = dai->codec;
c4431df0 1896 struct wm8994 *control = codec->control_data;
9e6e96a1
MB		 1897 int ms_reg;
1898 int aif1_reg;
1899 int ms = 0;
1900 int aif1 = 0;
1901
1902 switch (dai->id) {
1903 case 1:
1904 ms_reg = WM8994_AIF1_MASTER_SLAVE;
1905 aif1_reg = WM8994_AIF1_CONTROL_1;
1906 break;
1907 case 2:
1908 ms_reg = WM8994_AIF2_MASTER_SLAVE;
1909 aif1_reg = WM8994_AIF2_CONTROL_1;
1910 break;
1911 default:
1912 return -EINVAL;
1913 }
1914
1915 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1916 case SND_SOC_DAIFMT_CBS_CFS:
1917 break;
1918 case SND_SOC_DAIFMT_CBM_CFM:
1919 ms = WM8994_AIF1_MSTR;
1920 break;
1921 default:
1922 return -EINVAL;
1923 }
1924
1925 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1926 case SND_SOC_DAIFMT_DSP_B:
1927 aif1 |= WM8994_AIF1_LRCLK_INV;
1928 case SND_SOC_DAIFMT_DSP_A:
1929 aif1 |= 0x18;
1930 break;
1931 case SND_SOC_DAIFMT_I2S:
1932 aif1 |= 0x10;
1933 break;
1934 case SND_SOC_DAIFMT_RIGHT_J:
1935 break;
1936 case SND_SOC_DAIFMT_LEFT_J:
1937 aif1 |= 0x8;
1938 break;
1939 default:
1940 return -EINVAL;
1941 }
1942
1943 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1944 case SND_SOC_DAIFMT_DSP_A:
1945 case SND_SOC_DAIFMT_DSP_B:
1946 /* frame inversion not valid for DSP modes */
1947 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1948 case SND_SOC_DAIFMT_NB_NF:
1949 break;
1950 case SND_SOC_DAIFMT_IB_NF:
1951 aif1 |= WM8994_AIF1_BCLK_INV;
1952 break;
1953 default:
1954 return -EINVAL;
1955 }
1956 break;
1957
1958 case SND_SOC_DAIFMT_I2S:
1959 case SND_SOC_DAIFMT_RIGHT_J:
1960 case SND_SOC_DAIFMT_LEFT_J:
1961 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1962 case SND_SOC_DAIFMT_NB_NF:
1963 break;
1964 case SND_SOC_DAIFMT_IB_IF:
1965 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
1966 break;
1967 case SND_SOC_DAIFMT_IB_NF:
1968 aif1 |= WM8994_AIF1_BCLK_INV;
1969 break;
1970 case SND_SOC_DAIFMT_NB_IF:
1971 aif1 |= WM8994_AIF1_LRCLK_INV;
1972 break;
1973 default:
1974 return -EINVAL;
1975 }
1976 break;
1977 default:
1978 return -EINVAL;
1979 }
1980
c4431df0
MB		 1981 /* The AIF2 format configuration needs to be mirrored to AIF3
1982 * on WM8958 if it's in use so just do it all the time. */
1983 if (control->type == WM8958 && dai->id == 2)
1984 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
1985 WM8994_AIF1_LRCLK_INV |
1986 WM8958_AIF3_FMT_MASK, aif1);
1987
9e6e96a1
MB		 1988 snd_soc_update_bits(codec, aif1_reg,
1989 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
1990 WM8994_AIF1_FMT_MASK,
1991 aif1);
1992 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
1993 ms);
1994
1995 return 0;
1996}
1997
1998static struct {
1999 int val, rate;
2000} srs[] = {
2001 { 0, 8000 },
2002 { 1, 11025 },
2003 { 2, 12000 },
2004 { 3, 16000 },
2005 { 4, 22050 },
2006 { 5, 24000 },
2007 { 6, 32000 },
2008 { 7, 44100 },
2009 { 8, 48000 },
2010 { 9, 88200 },
2011 { 10, 96000 },
2012};
2013
2014static int fs_ratios[] = {
2015 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2016};
2017
2018static int bclk_divs[] = {
2019 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2020 640, 880, 960, 1280, 1760, 1920
2021};
2022
2023static int wm8994_hw_params(struct snd_pcm_substream *substream,
2024 struct snd_pcm_hw_params *params,
2025 struct snd_soc_dai *dai)
2026{
2027 struct snd_soc_codec *codec = dai->codec;
c4431df0 2028 struct wm8994 *control = codec->control_data;
b2c812e2 2029 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 2030 int aif1_reg;
2031 int bclk_reg;
2032 int lrclk_reg;
2033 int rate_reg;
2034 int aif1 = 0;
2035 int bclk = 0;
2036 int lrclk = 0;
2037 int rate_val = 0;
2038 int id = dai->id - 1;
2039
2040 int i, cur_val, best_val, bclk_rate, best;
2041
2042 switch (dai->id) {
2043 case 1:
2044 aif1_reg = WM8994_AIF1_CONTROL_1;
2045 bclk_reg = WM8994_AIF1_BCLK;
2046 rate_reg = WM8994_AIF1_RATE;
2047 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2048 wm8994->lrclk_shared[0]) {
9e6e96a1 2049 lrclk_reg = WM8994_AIF1DAC_LRCLK;
7d83d213 2050 } else {
9e6e96a1 2051 lrclk_reg = WM8994_AIF1ADC_LRCLK;
7d83d213
MB		 2052 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2053 }
9e6e96a1
MB		 2054 break;
2055 case 2:
2056 aif1_reg = WM8994_AIF2_CONTROL_1;
2057 bclk_reg = WM8994_AIF2_BCLK;
2058 rate_reg = WM8994_AIF2_RATE;
2059 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2060 wm8994->lrclk_shared[1]) {
9e6e96a1 2061 lrclk_reg = WM8994_AIF2DAC_LRCLK;
7d83d213 2062 } else {
9e6e96a1 2063 lrclk_reg = WM8994_AIF2ADC_LRCLK;
7d83d213
MB		 2064 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2065 }
9e6e96a1 2066 break;
c4431df0
MB		 2067 case 3:
2068 switch (control->type) {
2069 case WM8958:
2070 aif1_reg = WM8958_AIF3_CONTROL_1;
2071 break;
2072 default:
2073 return 0;
2074 }
9e6e96a1
MB		 2075 default:
2076 return -EINVAL;
2077 }
2078
2079 bclk_rate = params_rate(params) * 2;
2080 switch (params_format(params)) {
2081 case SNDRV_PCM_FORMAT_S16_LE:
2082 bclk_rate *= 16;
2083 break;
2084 case SNDRV_PCM_FORMAT_S20_3LE:
2085 bclk_rate *= 20;
2086 aif1 |= 0x20;
2087 break;
2088 case SNDRV_PCM_FORMAT_S24_LE:
2089 bclk_rate *= 24;
2090 aif1 |= 0x40;
2091 break;
2092 case SNDRV_PCM_FORMAT_S32_LE:
2093 bclk_rate *= 32;
2094 aif1 |= 0x60;
2095 break;
2096 default:
2097 return -EINVAL;
2098 }
2099
2100 /* Try to find an appropriate sample rate; look for an exact match. */
2101 for (i = 0; i < ARRAY_SIZE(srs); i++)
2102 if (srs[i].rate == params_rate(params))
2103 break;
2104 if (i == ARRAY_SIZE(srs))
2105 return -EINVAL;
2106 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2107
2108 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2109 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2110 dai->id, wm8994->aifclk[id], bclk_rate);
2111
2112 if (wm8994->aifclk[id] == 0) {
2113 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2114 return -EINVAL;
2115 }
2116
2117 /* AIFCLK/fs ratio; look for a close match in either direction */
2118 best = 0;
2119 best_val = abs((fs_ratios[0] * params_rate(params))
2120 - wm8994->aifclk[id]);
2121 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2122 cur_val = abs((fs_ratios[i] * params_rate(params))
2123 - wm8994->aifclk[id]);
2124 if (cur_val >= best_val)
2125 continue;
2126 best = i;
2127 best_val = cur_val;
2128 }
2129 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2130 dai->id, fs_ratios[best]);
2131 rate_val |= best;
2132
2133 /* We may not get quite the right frequency if using
2134 * approximate clocks so look for the closest match that is
2135 * higher than the target (we need to ensure that there enough
2136 * BCLKs to clock out the samples).
2137 */
2138 best = 0;
2139 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
07cd8ada 2140 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
9e6e96a1
MB		 2141 if (cur_val < 0) /* BCLK table is sorted */
2142 break;
2143 best = i;
2144 }
07cd8ada 2145 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
9e6e96a1
MB		 2146 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2147 bclk_divs[best], bclk_rate);
2148 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2149
2150 lrclk = bclk_rate / params_rate(params);
2151 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2152 lrclk, bclk_rate / lrclk);
2153
2154 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2155 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2156 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2157 lrclk);
2158 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2159 WM8994_AIF1CLK_RATE_MASK, rate_val);
2160
2161 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2162 switch (dai->id) {
2163 case 1:
2164 wm8994->dac_rates[0] = params_rate(params);
2165 wm8994_set_retune_mobile(codec, 0);
2166 wm8994_set_retune_mobile(codec, 1);
2167 break;
2168 case 2:
2169 wm8994->dac_rates[1] = params_rate(params);
2170 wm8994_set_retune_mobile(codec, 2);
2171 break;
2172 }
2173 }
2174
2175 return 0;
2176}
2177
c4431df0
MB		 2178static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2179 struct snd_pcm_hw_params *params,
2180 struct snd_soc_dai *dai)
2181{
2182 struct snd_soc_codec *codec = dai->codec;
2183 struct wm8994 *control = codec->control_data;
2184 int aif1_reg;
2185 int aif1 = 0;
2186
2187 switch (dai->id) {
2188 case 3:
2189 switch (control->type) {
2190 case WM8958:
2191 aif1_reg = WM8958_AIF3_CONTROL_1;
2192 break;
2193 default:
2194 return 0;
2195 }
2196 default:
2197 return 0;
2198 }
2199
2200 switch (params_format(params)) {
2201 case SNDRV_PCM_FORMAT_S16_LE:
2202 break;
2203 case SNDRV_PCM_FORMAT_S20_3LE:
2204 aif1 |= 0x20;
2205 break;
2206 case SNDRV_PCM_FORMAT_S24_LE:
2207 aif1 |= 0x40;
2208 break;
2209 case SNDRV_PCM_FORMAT_S32_LE:
2210 aif1 |= 0x60;
2211 break;
2212 default:
2213 return -EINVAL;
2214 }
2215
2216 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2217}
2218
9e6e96a1
MB		 2219static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2220{
2221 struct snd_soc_codec *codec = codec_dai->codec;
2222 int mute_reg;
2223 int reg;
2224
2225 switch (codec_dai->id) {
2226 case 1:
2227 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2228 break;
2229 case 2:
2230 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2231 break;
2232 default:
2233 return -EINVAL;
2234 }
2235
2236 if (mute)
2237 reg = WM8994_AIF1DAC1_MUTE;
2238 else
2239 reg = 0;
2240
2241 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2242
2243 return 0;
2244}
2245
778a76e2
MB		 2246static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2247{
2248 struct snd_soc_codec *codec = codec_dai->codec;
2249 int reg, val, mask;
2250
2251 switch (codec_dai->id) {
2252 case 1:
2253 reg = WM8994_AIF1_MASTER_SLAVE;
2254 mask = WM8994_AIF1_TRI;
2255 break;
2256 case 2:
2257 reg = WM8994_AIF2_MASTER_SLAVE;
2258 mask = WM8994_AIF2_TRI;
2259 break;
2260 case 3:
2261 reg = WM8994_POWER_MANAGEMENT_6;
2262 mask = WM8994_AIF3_TRI;
2263 break;
2264 default:
2265 return -EINVAL;
2266 }
2267
2268 if (tristate)
2269 val = mask;
2270 else
2271 val = 0;
2272
2273 return snd_soc_update_bits(codec, reg, mask, reg);
2274}
2275
9e6e96a1
MB		 2276#define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2277
2278#define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3079aed5 2279 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
9e6e96a1
MB		 2280
2281static struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2282 .set_sysclk = wm8994_set_dai_sysclk,
2283 .set_fmt = wm8994_set_dai_fmt,
2284 .hw_params = wm8994_hw_params,
2285 .digital_mute = wm8994_aif_mute,
2286 .set_pll = wm8994_set_fll,
778a76e2 2287 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2288};
2289
2290static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2291 .set_sysclk = wm8994_set_dai_sysclk,
2292 .set_fmt = wm8994_set_dai_fmt,
2293 .hw_params = wm8994_hw_params,
2294 .digital_mute = wm8994_aif_mute,
2295 .set_pll = wm8994_set_fll,
778a76e2
MB		 2296 .set_tristate = wm8994_set_tristate,
2297};
2298
2299static struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
c4431df0 2300 .hw_params = wm8994_aif3_hw_params,
778a76e2 2301 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2302};
2303
f0fba2ad 2304static struct snd_soc_dai_driver wm8994_dai[] = {
9e6e96a1 2305 {
f0fba2ad 2306 .name = "wm8994-aif1",
8c7f78b3 2307 .id = 1,
9e6e96a1
MB		 2308 .playback = {
2309 .stream_name = "AIF1 Playback",
2310 .channels_min = 2,
2311 .channels_max = 2,
2312 .rates = WM8994_RATES,
2313 .formats = WM8994_FORMATS,
2314 },
2315 .capture = {
2316 .stream_name = "AIF1 Capture",
2317 .channels_min = 2,
2318 .channels_max = 2,
2319 .rates = WM8994_RATES,
2320 .formats = WM8994_FORMATS,
2321 },
2322 .ops = &wm8994_aif1_dai_ops,
2323 },
2324 {
f0fba2ad 2325 .name = "wm8994-aif2",
8c7f78b3 2326 .id = 2,
9e6e96a1
MB		 2327 .playback = {
2328 .stream_name = "AIF2 Playback",
2329 .channels_min = 2,
2330 .channels_max = 2,
2331 .rates = WM8994_RATES,
2332 .formats = WM8994_FORMATS,
2333 },
2334 .capture = {
2335 .stream_name = "AIF2 Capture",
2336 .channels_min = 2,
2337 .channels_max = 2,
2338 .rates = WM8994_RATES,
2339 .formats = WM8994_FORMATS,
2340 },
2341 .ops = &wm8994_aif2_dai_ops,
2342 },
2343 {
f0fba2ad 2344 .name = "wm8994-aif3",
8c7f78b3 2345 .id = 3,
9e6e96a1
MB		 2346 .playback = {
2347 .stream_name = "AIF3 Playback",
2348 .channels_min = 2,
2349 .channels_max = 2,
2350 .rates = WM8994_RATES,
2351 .formats = WM8994_FORMATS,
2352 },
a8462bde 2353 .capture = {
9e6e96a1
MB		 2354 .stream_name = "AIF3 Capture",
2355 .channels_min = 2,
2356 .channels_max = 2,
2357 .rates = WM8994_RATES,
2358 .formats = WM8994_FORMATS,
2359 },
778a76e2 2360 .ops = &wm8994_aif3_dai_ops,
9e6e96a1
MB		 2361 }
2362};
9e6e96a1
MB		 2363
2364#ifdef CONFIG_PM
f0fba2ad 2365static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state)
9e6e96a1 2366{
b2c812e2 2367 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 2368 int i, ret;
2369
2370 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2371 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2372 sizeof(struct fll_config));
f0fba2ad 2373 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
9e6e96a1
MB		 2374 if (ret < 0)
2375 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2376 i + 1, ret);
2377 }
2378
2379 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2380
2381 return 0;
2382}
2383
f0fba2ad 2384static int wm8994_resume(struct snd_soc_codec *codec)
9e6e96a1 2385{
b2c812e2 2386 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 2387 int i, ret;
2388
2389 /* Restore the registers */
ca9aef50
MB		 2390 ret = snd_soc_cache_sync(codec);
2391 if (ret != 0)
2392 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
9e6e96a1
MB		 2393
2394 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2395
2396 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
6a2f1ee1
MB		 2397 if (!wm8994->fll_suspend[i].out)
2398 continue;
2399
f0fba2ad 2400 ret = _wm8994_set_fll(codec, i + 1,
9e6e96a1
MB		 2401 wm8994->fll_suspend[i].src,
2402 wm8994->fll_suspend[i].in,
2403 wm8994->fll_suspend[i].out);
2404 if (ret < 0)
2405 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2406 i + 1, ret);
2407 }
2408
2409 return 0;
2410}
2411#else
2412#define wm8994_suspend NULL
2413#define wm8994_resume NULL
2414#endif
2415
2416static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2417{
f0fba2ad 2418 struct snd_soc_codec *codec = wm8994->codec;
9e6e96a1
MB		 2419 struct wm8994_pdata *pdata = wm8994->pdata;
2420 struct snd_kcontrol_new controls[] = {
2421 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2422 wm8994->retune_mobile_enum,
2423 wm8994_get_retune_mobile_enum,
2424 wm8994_put_retune_mobile_enum),
2425 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2426 wm8994->retune_mobile_enum,
2427 wm8994_get_retune_mobile_enum,
2428 wm8994_put_retune_mobile_enum),
2429 SOC_ENUM_EXT("AIF2 EQ Mode",
2430 wm8994->retune_mobile_enum,
2431 wm8994_get_retune_mobile_enum,
2432 wm8994_put_retune_mobile_enum),
2433 };
2434 int ret, i, j;
2435 const char **t;
2436
2437 /* We need an array of texts for the enum API but the number
2438 * of texts is likely to be less than the number of
2439 * configurations due to the sample rate dependency of the
2440 * configurations. */
2441 wm8994->num_retune_mobile_texts = 0;
2442 wm8994->retune_mobile_texts = NULL;
2443 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2444 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2445 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2446 wm8994->retune_mobile_texts[j]) == 0)
2447 break;
2448 }
2449
2450 if (j != wm8994->num_retune_mobile_texts)
2451 continue;
2452
2453 /* Expand the array... */
2454 t = krealloc(wm8994->retune_mobile_texts,
2455 sizeof(char *) *
2456 (wm8994->num_retune_mobile_texts + 1),
2457 GFP_KERNEL);
2458 if (t == NULL)
2459 continue;
2460
2461 /* ...store the new entry... */
2462 t[wm8994->num_retune_mobile_texts] =
2463 pdata->retune_mobile_cfgs[i].name;
2464
2465 /* ...and remember the new version. */
2466 wm8994->num_retune_mobile_texts++;
2467 wm8994->retune_mobile_texts = t;
2468 }
2469
2470 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2471 wm8994->num_retune_mobile_texts);
2472
2473 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2474 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2475
f0fba2ad 2476 ret = snd_soc_add_controls(wm8994->codec, controls,
9e6e96a1
MB		 2477 ARRAY_SIZE(controls));
2478 if (ret != 0)
f0fba2ad 2479 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2480 "Failed to add ReTune Mobile controls: %d\n", ret);
2481}
2482
2483static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2484{
f0fba2ad 2485 struct snd_soc_codec *codec = wm8994->codec;
9e6e96a1
MB		 2486 struct wm8994_pdata *pdata = wm8994->pdata;
2487 int ret, i;
2488
2489 if (!pdata)
2490 return;
2491
2492 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2493 pdata->lineout2_diff,
2494 pdata->lineout1fb,
2495 pdata->lineout2fb,
2496 pdata->jd_scthr,
2497 pdata->jd_thr,
2498 pdata->micbias1_lvl,
2499 pdata->micbias2_lvl);
2500
2501 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2502
2503 if (pdata->num_drc_cfgs) {
2504 struct snd_kcontrol_new controls[] = {
2505 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2506 wm8994_get_drc_enum, wm8994_put_drc_enum),
2507 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2508 wm8994_get_drc_enum, wm8994_put_drc_enum),
2509 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2510 wm8994_get_drc_enum, wm8994_put_drc_enum),
2511 };
2512
2513 /* We need an array of texts for the enum API */
2514 wm8994->drc_texts = kmalloc(sizeof(char *)
2515 * pdata->num_drc_cfgs, GFP_KERNEL);
2516 if (!wm8994->drc_texts) {
f0fba2ad 2517 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2518 "Failed to allocate %d DRC config texts\n",
2519 pdata->num_drc_cfgs);
2520 return;
2521 }
2522
2523 for (i = 0; i < pdata->num_drc_cfgs; i++)
2524 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2525
2526 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2527 wm8994->drc_enum.texts = wm8994->drc_texts;
2528
f0fba2ad 2529 ret = snd_soc_add_controls(wm8994->codec, controls,
9e6e96a1
MB		 2530 ARRAY_SIZE(controls));
2531 if (ret != 0)
f0fba2ad 2532 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2533 "Failed to add DRC mode controls: %d\n", ret);
2534
2535 for (i = 0; i < WM8994_NUM_DRC; i++)
2536 wm8994_set_drc(codec, i);
2537 }
2538
2539 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2540 pdata->num_retune_mobile_cfgs);
2541
2542 if (pdata->num_retune_mobile_cfgs)
2543 wm8994_handle_retune_mobile_pdata(wm8994);
2544 else
f0fba2ad 2545 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
9e6e96a1
MB		 2546 ARRAY_SIZE(wm8994_eq_controls));
2547}
2548
88766984
MB		 2549/**
2550 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2551 *
2552 * @codec: WM8994 codec
2553 * @jack: jack to report detection events on
2554 * @micbias: microphone bias to detect on
2555 * @det: value to report for presence detection
2556 * @shrt: value to report for short detection
2557 *
2558 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
2559 * being used to bring out signals to the processor then only platform
5ab230a7 2560 * data configuration is needed for WM8994 and processor GPIOs should
88766984
MB		 2561 * be configured using snd_soc_jack_add_gpios() instead.
2562 *
2563 * Configuration of detection levels is available via the micbias1_lvl
2564 * and micbias2_lvl platform data members.
2565 */
2566int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2567 int micbias, int det, int shrt)
2568{
b2c812e2 2569 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
88766984 2570 struct wm8994_micdet *micdet;
3a423157 2571 struct wm8994 *control = codec->control_data;
88766984
MB		 2572 int reg;
2573
3a423157
MB		 2574 if (control->type != WM8994)
2575 return -EINVAL;
2576
88766984
MB		 2577 switch (micbias) {
2578 case 1:
2579 micdet = &wm8994->micdet[0];
2580 break;
2581 case 2:
2582 micdet = &wm8994->micdet[1];
2583 break;
2584 default:
2585 return -EINVAL;
2586 }
2587
2588 dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
2589 micbias, det, shrt);
2590
2591 /* Store the configuration */
2592 micdet->jack = jack;
2593 micdet->det = det;
2594 micdet->shrt = shrt;
2595
2596 /* If either of the jacks is set up then enable detection */
2597 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2598 reg = WM8994_MICD_ENA;
2599 else
2600 reg = 0;
2601
2602 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
2603
2604 return 0;
2605}
2606EXPORT_SYMBOL_GPL(wm8994_mic_detect);
2607
2608static irqreturn_t wm8994_mic_irq(int irq, void *data)
2609{
2610 struct wm8994_priv *priv = data;
f0fba2ad 2611 struct snd_soc_codec *codec = priv->codec;
88766984
MB		 2612 int reg;
2613 int report;
2614
2615 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
2616 if (reg < 0) {
2617 dev_err(codec->dev, "Failed to read microphone status: %d\n",
2618 reg);
2619 return IRQ_HANDLED;
2620 }
2621
2622 dev_dbg(codec->dev, "Microphone status: %x\n", reg);
2623
2624 report = 0;
2625 if (reg & WM8994_MIC1_DET_STS)
2626 report |= priv->micdet[0].det;
2627 if (reg & WM8994_MIC1_SHRT_STS)
2628 report |= priv->micdet[0].shrt;
2629 snd_soc_jack_report(priv->micdet[0].jack, report,
2630 priv->micdet[0].det | priv->micdet[0].shrt);
2631
2632 report = 0;
2633 if (reg & WM8994_MIC2_DET_STS)
2634 report |= priv->micdet[1].det;
2635 if (reg & WM8994_MIC2_SHRT_STS)
2636 report |= priv->micdet[1].shrt;
2637 snd_soc_jack_report(priv->micdet[1].jack, report,
2638 priv->micdet[1].det | priv->micdet[1].shrt);
2639
2640 return IRQ_HANDLED;
2641}
2642
821edd2f
MB		 2643/* Default microphone detection handler for WM8958 - the user can
2644 * override this if they wish.
2645 */
2646static void wm8958_default_micdet(u16 status, void *data)
2647{
2648 struct snd_soc_codec *codec = data;
2649 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2650 int report = 0;
2651
2652 /* If nothing present then clear our statuses */
2653 if (!(status & WM8958_MICD_STS)) {
2654 wm8994->jack_is_video = false;
2655 wm8994->jack_is_mic = false;
2656 goto done;
2657 }
2658
2659 /* Assume anything over 475 ohms is a microphone and remember
2660 * that we've seen one (since buttons override it) */
2661 if (status & 0x600)
2662 wm8994->jack_is_mic = true;
2663 if (wm8994->jack_is_mic)
2664 report |= SND_JACK_MICROPHONE;
2665
2666 /* Video has an impedence of approximately 75 ohms; assume
2667 * this isn't used as a button and remember it since buttons
2668 * override it. */
2669 if (status & 0x40)
2670 wm8994->jack_is_video = true;
2671 if (wm8994->jack_is_video)
2672 report |= SND_JACK_VIDEOOUT;
2673
2674 /* Everything else is buttons; just assign slots */
2675 if (status & 0x4)
2676 report |= SND_JACK_BTN_0;
2677 if (status & 0x8)
2678 report |= SND_JACK_BTN_1;
2679 if (status & 0x10)
2680 report |= SND_JACK_BTN_2;
2681 if (status & 0x20)
2682 report |= SND_JACK_BTN_3;
2683 if (status & 0x80)
2684 report |= SND_JACK_BTN_4;
2685 if (status & 0x100)
2686 report |= SND_JACK_BTN_5;
2687
2688done:
2689 snd_soc_jack_report(wm8994->micdet[0].jack,
2690 SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2 |
2691 SND_JACK_BTN_3 | SND_JACK_BTN_4 | SND_JACK_BTN_5 |
2692 SND_JACK_MICROPHONE | SND_JACK_VIDEOOUT,
2693 report);
2694}
2695
2696/**
2697 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
2698 *
2699 * @codec: WM8958 codec
2700 * @jack: jack to report detection events on
2701 *
2702 * Enable microphone detection functionality for the WM8958. By
2703 * default simple detection which supports the detection of up to 6
2704 * buttons plus video and microphone functionality is supported.
2705 *
2706 * The WM8958 has an advanced jack detection facility which is able to
2707 * support complex accessory detection, especially when used in
2708 * conjunction with external circuitry. In order to provide maximum
2709 * flexiblity a callback is provided which allows a completely custom
2710 * detection algorithm.
2711 */
2712int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2713 wm8958_micdet_cb cb, void *cb_data)
2714{
2715 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2716 struct wm8994 *control = codec->control_data;
2717
2718 if (control->type != WM8958)
2719 return -EINVAL;
2720
2721 if (jack) {
2722 if (!cb) {
2723 dev_dbg(codec->dev, "Using default micdet callback\n");
2724 cb = wm8958_default_micdet;
2725 cb_data = codec;
2726 }
2727
2728 wm8994->micdet[0].jack = jack;
2729 wm8994->jack_cb = cb;
2730 wm8994->jack_cb_data = cb_data;
2731
2732 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2733 WM8958_MICD_ENA, WM8958_MICD_ENA);
2734 } else {
2735 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2736 WM8958_MICD_ENA, 0);
2737 }
2738
2739 return 0;
2740}
2741EXPORT_SYMBOL_GPL(wm8958_mic_detect);
2742
2743static irqreturn_t wm8958_mic_irq(int irq, void *data)
2744{
2745 struct wm8994_priv *wm8994 = data;
2746 struct snd_soc_codec *codec = wm8994->codec;
2747 int reg;
2748
2749 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
2750 if (reg < 0) {
2751 dev_err(codec->dev, "Failed to read mic detect status: %d\n",
2752 reg);
2753 return IRQ_NONE;
2754 }
2755
2756 if (!(reg & WM8958_MICD_VALID)) {
2757 dev_dbg(codec->dev, "Mic detect data not valid\n");
2758 goto out;
2759 }
2760
2761 if (wm8994->jack_cb)
2762 wm8994->jack_cb(reg, wm8994->jack_cb_data);
2763 else
2764 dev_warn(codec->dev, "Accessory detection with no callback\n");
2765
2766out:
2767 return IRQ_HANDLED;
2768}
2769
f0fba2ad 2770static int wm8994_codec_probe(struct snd_soc_codec *codec)
9e6e96a1 2771{
3a423157 2772 struct wm8994 *control;
9e6e96a1 2773 struct wm8994_priv *wm8994;
ce6120cc 2774 struct snd_soc_dapm_context *dapm = &codec->dapm;
ec62dbd7 2775 int ret, i;
9e6e96a1 2776
f0fba2ad 2777 codec->control_data = dev_get_drvdata(codec->dev->parent);
3a423157 2778 control = codec->control_data;
9e6e96a1
MB		 2779
2780 wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
f0fba2ad 2781 if (wm8994 == NULL)
9e6e96a1 2782 return -ENOMEM;
b2c812e2 2783 snd_soc_codec_set_drvdata(codec, wm8994);
f0fba2ad
LG		 2784
2785 wm8994->pdata = dev_get_platdata(codec->dev->parent);
2786 wm8994->codec = codec;
9e6e96a1 2787
39fb51a1
MB		 2788 pm_runtime_enable(codec->dev);
2789 pm_runtime_resume(codec->dev);
2790
ca9aef50
MB		 2791 /* Read our current status back from the chip - we don't want to
2792 * reset as this may interfere with the GPIO or LDO operation. */
2793 for (i = 0; i < WM8994_CACHE_SIZE; i++) {
2794 if (!wm8994_readable(i) || wm8994_volatile(i))
2795 continue;
9e6e96a1 2796
ca9aef50
MB		 2797 ret = wm8994_reg_read(codec->control_data, i);
2798 if (ret <= 0)
2799 continue;
2800
2801 ret = snd_soc_cache_write(codec, i, ret);
2802 if (ret != 0) {
2803 dev_err(codec->dev,
2804 "Failed to initialise cache for 0x%x: %d\n",
2805 i, ret);
2806 goto err;
2807 }
2808 }
9e6e96a1
MB		 2809
2810 /* Set revision-specific configuration */
b6b05691 2811 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3a423157
MB		 2812 switch (control->type) {
2813 case WM8994:
2814 switch (wm8994->revision) {
2815 case 2:
2816 case 3:
2817 wm8994->hubs.dcs_codes = -5;
2818 wm8994->hubs.hp_startup_mode = 1;
2819 wm8994->hubs.dcs_readback_mode = 1;
2820 break;
2821 default:
2822 wm8994->hubs.dcs_readback_mode = 1;
2823 break;
2824 }
2825
2826 case WM8958:
8437f700 2827 wm8994->hubs.dcs_readback_mode = 1;
9e6e96a1 2828 break;
3a423157 2829
9e6e96a1
MB		 2830 default:
2831 break;
2832 }
9e6e96a1 2833
3a423157
MB		 2834 switch (control->type) {
2835 case WM8994:
2836 ret = wm8994_request_irq(codec->control_data,
2837 WM8994_IRQ_MIC1_DET,
2838 wm8994_mic_irq, "Mic 1 detect",
2839 wm8994);
2840 if (ret != 0)
2841 dev_warn(codec->dev,
2842 "Failed to request Mic1 detect IRQ: %d\n",
2843 ret);
2844
2845 ret = wm8994_request_irq(codec->control_data,
2846 WM8994_IRQ_MIC1_SHRT,
2847 wm8994_mic_irq, "Mic 1 short",
2848 wm8994);
2849 if (ret != 0)
2850 dev_warn(codec->dev,
2851 "Failed to request Mic1 short IRQ: %d\n",
2852 ret);
2853
2854 ret = wm8994_request_irq(codec->control_data,
2855 WM8994_IRQ_MIC2_DET,
2856 wm8994_mic_irq, "Mic 2 detect",
2857 wm8994);
2858 if (ret != 0)
2859 dev_warn(codec->dev,
2860 "Failed to request Mic2 detect IRQ: %d\n",
2861 ret);
2862
2863 ret = wm8994_request_irq(codec->control_data,
2864 WM8994_IRQ_MIC2_SHRT,
2865 wm8994_mic_irq, "Mic 2 short",
2866 wm8994);
2867 if (ret != 0)
2868 dev_warn(codec->dev,
2869 "Failed to request Mic2 short IRQ: %d\n",
2870 ret);
2871 break;
821edd2f
MB		 2872
2873 case WM8958:
2874 ret = wm8994_request_irq(codec->control_data,
2875 WM8994_IRQ_MIC1_DET,
2876 wm8958_mic_irq, "Mic detect",
2877 wm8994);
2878 if (ret != 0)
2879 dev_warn(codec->dev,
2880 "Failed to request Mic detect IRQ: %d\n",
2881 ret);
2882 break;
3a423157 2883 }
88766984 2884
9e6e96a1
MB		 2885 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
2886 * configured on init - if a system wants to do this dynamically
2887 * at runtime we can deal with that then.
2888 */
2889 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1);
2890 if (ret < 0) {
2891 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
88766984 2892 goto err_irq;
9e6e96a1
MB		 2893 }
2894 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
2895 wm8994->lrclk_shared[0] = 1;
2896 wm8994_dai[0].symmetric_rates = 1;
2897 } else {
2898 wm8994->lrclk_shared[0] = 0;
2899 }
2900
2901 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6);
2902 if (ret < 0) {
2903 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
88766984 2904 goto err_irq;
9e6e96a1
MB		 2905 }
2906 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
2907 wm8994->lrclk_shared[1] = 1;
2908 wm8994_dai[1].symmetric_rates = 1;
2909 } else {
2910 wm8994->lrclk_shared[1] = 0;
2911 }
2912
9e6e96a1
MB		 2913 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2914
9e6e96a1
MB		 2915 /* Latch volume updates (right only; we always do left then right). */
2916 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
2917 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
2918 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
2919 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
2920 snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
2921 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
2922 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
2923 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
2924 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
2925 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
2926 snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
2927 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
2928 snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
2929 WM8994_DAC1_VU, WM8994_DAC1_VU);
2930 snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
2931 WM8994_DAC2_VU, WM8994_DAC2_VU);
2932
2933 /* Set the low bit of the 3D stereo depth so TLV matches */
2934 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
2935 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
2936 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
2937 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
2938 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
2939 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
2940 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
2941 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
2942 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
2943
d1ce6b20
MB		 2944 /* Unconditionally enable AIF1 ADC TDM mode; it only affects
2945 * behaviour on idle TDM clock cycles. */
2946 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
2947 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
2948
9e6e96a1
MB		 2949 wm8994_update_class_w(codec);
2950
f0fba2ad 2951 wm8994_handle_pdata(wm8994);
9e6e96a1 2952
f0fba2ad
LG		 2953 wm_hubs_add_analogue_controls(codec);
2954 snd_soc_add_controls(codec, wm8994_snd_controls,
2955 ARRAY_SIZE(wm8994_snd_controls));
ce6120cc 2956 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
f0fba2ad 2957 ARRAY_SIZE(wm8994_dapm_widgets));
c4431df0
MB		 2958
2959 switch (control->type) {
2960 case WM8994:
2961 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
2962 ARRAY_SIZE(wm8994_specific_dapm_widgets));
2963 break;
2964 case WM8958:
2965 snd_soc_add_controls(codec, wm8958_snd_controls,
2966 ARRAY_SIZE(wm8958_snd_controls));
2967 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
2968 ARRAY_SIZE(wm8958_dapm_widgets));
2969 break;
2970 }
2971
2972
f0fba2ad 2973 wm_hubs_add_analogue_routes(codec, 0, 0);
ce6120cc 2974 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
9e6e96a1 2975
c4431df0
MB		 2976 switch (control->type) {
2977 case WM8994:
2978 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
2979 ARRAY_SIZE(wm8994_intercon));
2980 break;
2981 case WM8958:
2982 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
2983 ARRAY_SIZE(wm8958_intercon));
2984 break;
2985 }
2986
9e6e96a1
MB		 2987 return 0;
2988
88766984
MB		 2989err_irq:
2990 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
2991 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
2992 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
2993 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, wm8994);
9e6e96a1
MB		 2994err:
2995 kfree(wm8994);
2996 return ret;
2997}
2998
f0fba2ad 2999static int wm8994_codec_remove(struct snd_soc_codec *codec)
9e6e96a1 3000{
f0fba2ad 3001 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3a423157 3002 struct wm8994 *control = codec->control_data;
9e6e96a1
MB		 3003
3004 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
f0fba2ad 3005
39fb51a1
MB		 3006 pm_runtime_disable(codec->dev);
3007
3a423157
MB		 3008 switch (control->type) {
3009 case WM8994:
3010 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT,
3011 wm8994);
3012 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET,
3013 wm8994);
3014 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT,
3015 wm8994);
3016 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3017 wm8994);
3018 break;
821edd2f
MB		 3019
3020 case WM8958:
3021 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3022 wm8994);
3023 break;
3a423157 3024 }
24fb2b11
AL		 3025 kfree(wm8994->retune_mobile_texts);
3026 kfree(wm8994->drc_texts);
9e6e96a1 3027 kfree(wm8994);
9e6e96a1
MB		 3028
3029 return 0;
3030}
3031
f0fba2ad
LG		 3032static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3033 .probe = wm8994_codec_probe,
3034 .remove = wm8994_codec_remove,
3035 .suspend = wm8994_suspend,
3036 .resume = wm8994_resume,
ca9aef50
MB		 3037 .read = wm8994_read,
3038 .write = wm8994_write,
eba19fdd
MB		 3039 .readable_register = wm8994_readable,
3040 .volatile_register = wm8994_volatile,
f0fba2ad 3041 .set_bias_level = wm8994_set_bias_level,
ca9aef50
MB		 3042
3043 .reg_cache_size = WM8994_CACHE_SIZE,
3044 .reg_cache_default = wm8994_reg_defaults,
3045 .reg_word_size = 2,
2e19b0c8 3046 .compress_type = SND_SOC_RBTREE_COMPRESSION,
f0fba2ad
LG		 3047};
3048
3049static int __devinit wm8994_probe(struct platform_device *pdev)
3050{
3051 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3052 wm8994_dai, ARRAY_SIZE(wm8994_dai));
3053}
3054
3055static int __devexit wm8994_remove(struct platform_device *pdev)
3056{
3057 snd_soc_unregister_codec(&pdev->dev);
3058 return 0;
3059}
3060
9e6e96a1
MB		 3061static struct platform_driver wm8994_codec_driver = {
3062 .driver = {
3063 .name = "wm8994-codec",
3064 .owner = THIS_MODULE,
3065 },
f0fba2ad
LG		 3066 .probe = wm8994_probe,
3067 .remove = __devexit_p(wm8994_remove),
9e6e96a1
MB		 3068};
3069
3070static __init int wm8994_init(void)
3071{
3072 return platform_driver_register(&wm8994_codec_driver);
3073}
3074module_init(wm8994_init);
3075
3076static __exit void wm8994_exit(void)
3077{
3078 platform_driver_unregister(&wm8994_codec_driver);
3079}
3080module_exit(wm8994_exit);
3081
3082
3083MODULE_DESCRIPTION("ASoC WM8994 driver");
3084MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3085MODULE_LICENSE("GPL");
3086MODULE_ALIAS("platform:wm8994-codec");
Linux kernel - Deliverables
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