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1 | /* |
2 | * wm9081.c -- WM9081 ALSA SoC Audio driver | |
3 | * | |
4 | * Author: Mark Brown | |
5 | * | |
6 | * Copyright 2009 Wolfson Microelectronics plc | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | */ | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/moduleparam.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/delay.h> | |
3ee845ac | 18 | #include <linux/device.h> |
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19 | #include <linux/pm.h> |
20 | #include <linux/i2c.h> | |
21 | #include <linux/platform_device.h> | |
5a0e3ad6 | 22 | #include <linux/slab.h> |
86ed3669 MB |
23 | #include <sound/core.h> |
24 | #include <sound/pcm.h> | |
25 | #include <sound/pcm_params.h> | |
26 | #include <sound/soc.h> | |
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27 | #include <sound/initval.h> |
28 | #include <sound/tlv.h> | |
29 | ||
30 | #include <sound/wm9081.h> | |
31 | #include "wm9081.h" | |
32 | ||
33 | static u16 wm9081_reg_defaults[] = { | |
34 | 0x0000, /* R0 - Software Reset */ | |
35 | 0x0000, /* R1 */ | |
36 | 0x00B9, /* R2 - Analogue Lineout */ | |
37 | 0x00B9, /* R3 - Analogue Speaker PGA */ | |
38 | 0x0001, /* R4 - VMID Control */ | |
39 | 0x0068, /* R5 - Bias Control 1 */ | |
40 | 0x0000, /* R6 */ | |
41 | 0x0000, /* R7 - Analogue Mixer */ | |
42 | 0x0000, /* R8 - Anti Pop Control */ | |
43 | 0x01DB, /* R9 - Analogue Speaker 1 */ | |
44 | 0x0018, /* R10 - Analogue Speaker 2 */ | |
45 | 0x0180, /* R11 - Power Management */ | |
46 | 0x0000, /* R12 - Clock Control 1 */ | |
47 | 0x0038, /* R13 - Clock Control 2 */ | |
48 | 0x4000, /* R14 - Clock Control 3 */ | |
49 | 0x0000, /* R15 */ | |
50 | 0x0000, /* R16 - FLL Control 1 */ | |
51 | 0x0200, /* R17 - FLL Control 2 */ | |
52 | 0x0000, /* R18 - FLL Control 3 */ | |
53 | 0x0204, /* R19 - FLL Control 4 */ | |
54 | 0x0000, /* R20 - FLL Control 5 */ | |
55 | 0x0000, /* R21 */ | |
56 | 0x0000, /* R22 - Audio Interface 1 */ | |
57 | 0x0002, /* R23 - Audio Interface 2 */ | |
58 | 0x0008, /* R24 - Audio Interface 3 */ | |
59 | 0x0022, /* R25 - Audio Interface 4 */ | |
60 | 0x0000, /* R26 - Interrupt Status */ | |
61 | 0x0006, /* R27 - Interrupt Status Mask */ | |
62 | 0x0000, /* R28 - Interrupt Polarity */ | |
63 | 0x0000, /* R29 - Interrupt Control */ | |
64 | 0x00C0, /* R30 - DAC Digital 1 */ | |
65 | 0x0008, /* R31 - DAC Digital 2 */ | |
66 | 0x09AF, /* R32 - DRC 1 */ | |
67 | 0x4201, /* R33 - DRC 2 */ | |
68 | 0x0000, /* R34 - DRC 3 */ | |
69 | 0x0000, /* R35 - DRC 4 */ | |
70 | 0x0000, /* R36 */ | |
71 | 0x0000, /* R37 */ | |
72 | 0x0000, /* R38 - Write Sequencer 1 */ | |
73 | 0x0000, /* R39 - Write Sequencer 2 */ | |
74 | 0x0002, /* R40 - MW Slave 1 */ | |
75 | 0x0000, /* R41 */ | |
76 | 0x0000, /* R42 - EQ 1 */ | |
77 | 0x0000, /* R43 - EQ 2 */ | |
78 | 0x0FCA, /* R44 - EQ 3 */ | |
79 | 0x0400, /* R45 - EQ 4 */ | |
80 | 0x00B8, /* R46 - EQ 5 */ | |
81 | 0x1EB5, /* R47 - EQ 6 */ | |
82 | 0xF145, /* R48 - EQ 7 */ | |
83 | 0x0B75, /* R49 - EQ 8 */ | |
84 | 0x01C5, /* R50 - EQ 9 */ | |
85 | 0x169E, /* R51 - EQ 10 */ | |
86 | 0xF829, /* R52 - EQ 11 */ | |
87 | 0x07AD, /* R53 - EQ 12 */ | |
88 | 0x1103, /* R54 - EQ 13 */ | |
89 | 0x1C58, /* R55 - EQ 14 */ | |
90 | 0xF373, /* R56 - EQ 15 */ | |
91 | 0x0A54, /* R57 - EQ 16 */ | |
92 | 0x0558, /* R58 - EQ 17 */ | |
93 | 0x0564, /* R59 - EQ 18 */ | |
94 | 0x0559, /* R60 - EQ 19 */ | |
95 | 0x4000, /* R61 - EQ 20 */ | |
96 | }; | |
97 | ||
98 | static struct { | |
99 | int ratio; | |
100 | int clk_sys_rate; | |
101 | } clk_sys_rates[] = { | |
102 | { 64, 0 }, | |
103 | { 128, 1 }, | |
104 | { 192, 2 }, | |
105 | { 256, 3 }, | |
106 | { 384, 4 }, | |
107 | { 512, 5 }, | |
108 | { 768, 6 }, | |
109 | { 1024, 7 }, | |
110 | { 1408, 8 }, | |
111 | { 1536, 9 }, | |
112 | }; | |
113 | ||
114 | static struct { | |
115 | int rate; | |
116 | int sample_rate; | |
117 | } sample_rates[] = { | |
118 | { 8000, 0 }, | |
119 | { 11025, 1 }, | |
120 | { 12000, 2 }, | |
121 | { 16000, 3 }, | |
122 | { 22050, 4 }, | |
123 | { 24000, 5 }, | |
124 | { 32000, 6 }, | |
125 | { 44100, 7 }, | |
126 | { 48000, 8 }, | |
127 | { 88200, 9 }, | |
128 | { 96000, 10 }, | |
129 | }; | |
130 | ||
131 | static struct { | |
132 | int div; /* *10 due to .5s */ | |
133 | int bclk_div; | |
134 | } bclk_divs[] = { | |
135 | { 10, 0 }, | |
136 | { 15, 1 }, | |
137 | { 20, 2 }, | |
138 | { 30, 3 }, | |
139 | { 40, 4 }, | |
140 | { 50, 5 }, | |
141 | { 55, 6 }, | |
142 | { 60, 7 }, | |
143 | { 80, 8 }, | |
144 | { 100, 9 }, | |
145 | { 110, 10 }, | |
146 | { 120, 11 }, | |
147 | { 160, 12 }, | |
148 | { 200, 13 }, | |
149 | { 220, 14 }, | |
150 | { 240, 15 }, | |
151 | { 250, 16 }, | |
152 | { 300, 17 }, | |
153 | { 320, 18 }, | |
154 | { 440, 19 }, | |
155 | { 480, 20 }, | |
156 | }; | |
157 | ||
158 | struct wm9081_priv { | |
f0fba2ad | 159 | enum snd_soc_control_type control_type; |
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160 | int sysclk_source; |
161 | int mclk_rate; | |
162 | int sysclk_rate; | |
163 | int fs; | |
164 | int bclk; | |
165 | int master; | |
166 | int fll_fref; | |
167 | int fll_fout; | |
e0026bea | 168 | int tdm_width; |
4a5f7bda | 169 | struct wm9081_pdata pdata; |
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170 | }; |
171 | ||
d4754ec9 | 172 | static int wm9081_volatile_register(struct snd_soc_codec *codec, unsigned int reg) |
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173 | { |
174 | switch (reg) { | |
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175 | case WM9081_SOFTWARE_RESET: |
176 | return 1; | |
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177 | default: |
178 | return 0; | |
179 | } | |
180 | } | |
181 | ||
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182 | static int wm9081_reset(struct snd_soc_codec *codec) |
183 | { | |
8d50e447 | 184 | return snd_soc_write(codec, WM9081_SOFTWARE_RESET, 0); |
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185 | } |
186 | ||
187 | static const DECLARE_TLV_DB_SCALE(drc_in_tlv, -4500, 75, 0); | |
188 | static const DECLARE_TLV_DB_SCALE(drc_out_tlv, -2250, 75, 0); | |
189 | static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0); | |
190 | static unsigned int drc_max_tlv[] = { | |
191 | TLV_DB_RANGE_HEAD(4), | |
192 | 0, 0, TLV_DB_SCALE_ITEM(1200, 0, 0), | |
193 | 1, 1, TLV_DB_SCALE_ITEM(1800, 0, 0), | |
194 | 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), | |
195 | 3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0), | |
196 | }; | |
197 | static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0); | |
198 | static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -300, 50, 0); | |
199 | ||
200 | static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); | |
201 | ||
202 | static const DECLARE_TLV_DB_SCALE(in_tlv, -600, 600, 0); | |
203 | static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1); | |
204 | static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0); | |
205 | ||
206 | static const char *drc_high_text[] = { | |
207 | "1", | |
208 | "1/2", | |
209 | "1/4", | |
210 | "1/8", | |
211 | "1/16", | |
212 | "0", | |
213 | }; | |
214 | ||
215 | static const struct soc_enum drc_high = | |
216 | SOC_ENUM_SINGLE(WM9081_DRC_3, 3, 6, drc_high_text); | |
217 | ||
218 | static const char *drc_low_text[] = { | |
219 | "1", | |
220 | "1/2", | |
221 | "1/4", | |
222 | "1/8", | |
223 | "0", | |
224 | }; | |
225 | ||
226 | static const struct soc_enum drc_low = | |
227 | SOC_ENUM_SINGLE(WM9081_DRC_3, 0, 5, drc_low_text); | |
228 | ||
229 | static const char *drc_atk_text[] = { | |
230 | "181us", | |
231 | "181us", | |
232 | "363us", | |
233 | "726us", | |
234 | "1.45ms", | |
235 | "2.9ms", | |
236 | "5.8ms", | |
237 | "11.6ms", | |
238 | "23.2ms", | |
239 | "46.4ms", | |
240 | "92.8ms", | |
241 | "185.6ms", | |
242 | }; | |
243 | ||
244 | static const struct soc_enum drc_atk = | |
245 | SOC_ENUM_SINGLE(WM9081_DRC_2, 12, 12, drc_atk_text); | |
246 | ||
247 | static const char *drc_dcy_text[] = { | |
248 | "186ms", | |
249 | "372ms", | |
250 | "743ms", | |
251 | "1.49s", | |
252 | "2.97s", | |
253 | "5.94s", | |
254 | "11.89s", | |
255 | "23.78s", | |
256 | "47.56s", | |
257 | }; | |
258 | ||
259 | static const struct soc_enum drc_dcy = | |
260 | SOC_ENUM_SINGLE(WM9081_DRC_2, 8, 9, drc_dcy_text); | |
261 | ||
262 | static const char *drc_qr_dcy_text[] = { | |
263 | "0.725ms", | |
264 | "1.45ms", | |
265 | "5.8ms", | |
266 | }; | |
267 | ||
268 | static const struct soc_enum drc_qr_dcy = | |
269 | SOC_ENUM_SINGLE(WM9081_DRC_2, 4, 3, drc_qr_dcy_text); | |
270 | ||
271 | static const char *dac_deemph_text[] = { | |
272 | "None", | |
273 | "32kHz", | |
274 | "44.1kHz", | |
275 | "48kHz", | |
276 | }; | |
277 | ||
278 | static const struct soc_enum dac_deemph = | |
279 | SOC_ENUM_SINGLE(WM9081_DAC_DIGITAL_2, 1, 4, dac_deemph_text); | |
280 | ||
281 | static const char *speaker_mode_text[] = { | |
282 | "Class D", | |
283 | "Class AB", | |
284 | }; | |
285 | ||
286 | static const struct soc_enum speaker_mode = | |
287 | SOC_ENUM_SINGLE(WM9081_ANALOGUE_SPEAKER_2, 6, 2, speaker_mode_text); | |
288 | ||
289 | static int speaker_mode_get(struct snd_kcontrol *kcontrol, | |
290 | struct snd_ctl_elem_value *ucontrol) | |
291 | { | |
292 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
293 | unsigned int reg; | |
294 | ||
8d50e447 | 295 | reg = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2); |
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296 | if (reg & WM9081_SPK_MODE) |
297 | ucontrol->value.integer.value[0] = 1; | |
298 | else | |
299 | ucontrol->value.integer.value[0] = 0; | |
300 | ||
301 | return 0; | |
302 | } | |
303 | ||
304 | /* | |
305 | * Stop any attempts to change speaker mode while the speaker is enabled. | |
306 | * | |
25985edc | 307 | * We also have some special anti-pop controls dependent on speaker |
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308 | * mode which must be changed along with the mode. |
309 | */ | |
310 | static int speaker_mode_put(struct snd_kcontrol *kcontrol, | |
311 | struct snd_ctl_elem_value *ucontrol) | |
312 | { | |
313 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
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314 | unsigned int reg_pwr = snd_soc_read(codec, WM9081_POWER_MANAGEMENT); |
315 | unsigned int reg2 = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2); | |
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316 | |
317 | /* Are we changing anything? */ | |
318 | if (ucontrol->value.integer.value[0] == | |
319 | ((reg2 & WM9081_SPK_MODE) != 0)) | |
320 | return 0; | |
321 | ||
322 | /* Don't try to change modes while enabled */ | |
323 | if (reg_pwr & WM9081_SPK_ENA) | |
324 | return -EINVAL; | |
325 | ||
326 | if (ucontrol->value.integer.value[0]) { | |
327 | /* Class AB */ | |
328 | reg2 &= ~(WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL); | |
329 | reg2 |= WM9081_SPK_MODE; | |
330 | } else { | |
331 | /* Class D */ | |
332 | reg2 |= WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL; | |
333 | reg2 &= ~WM9081_SPK_MODE; | |
334 | } | |
335 | ||
8d50e447 | 336 | snd_soc_write(codec, WM9081_ANALOGUE_SPEAKER_2, reg2); |
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337 | |
338 | return 0; | |
339 | } | |
340 | ||
341 | static const struct snd_kcontrol_new wm9081_snd_controls[] = { | |
342 | SOC_SINGLE_TLV("IN1 Volume", WM9081_ANALOGUE_MIXER, 1, 1, 1, in_tlv), | |
343 | SOC_SINGLE_TLV("IN2 Volume", WM9081_ANALOGUE_MIXER, 3, 1, 1, in_tlv), | |
344 | ||
345 | SOC_SINGLE_TLV("Playback Volume", WM9081_DAC_DIGITAL_1, 1, 96, 0, dac_tlv), | |
346 | ||
347 | SOC_SINGLE("LINEOUT Switch", WM9081_ANALOGUE_LINEOUT, 7, 1, 1), | |
348 | SOC_SINGLE("LINEOUT ZC Switch", WM9081_ANALOGUE_LINEOUT, 6, 1, 0), | |
349 | SOC_SINGLE_TLV("LINEOUT Volume", WM9081_ANALOGUE_LINEOUT, 0, 63, 0, out_tlv), | |
350 | ||
351 | SOC_SINGLE("DRC Switch", WM9081_DRC_1, 15, 1, 0), | |
352 | SOC_ENUM("DRC High Slope", drc_high), | |
353 | SOC_ENUM("DRC Low Slope", drc_low), | |
354 | SOC_SINGLE_TLV("DRC Input Volume", WM9081_DRC_4, 5, 60, 1, drc_in_tlv), | |
355 | SOC_SINGLE_TLV("DRC Output Volume", WM9081_DRC_4, 0, 30, 1, drc_out_tlv), | |
356 | SOC_SINGLE_TLV("DRC Minimum Volume", WM9081_DRC_2, 2, 3, 1, drc_min_tlv), | |
357 | SOC_SINGLE_TLV("DRC Maximum Volume", WM9081_DRC_2, 0, 3, 0, drc_max_tlv), | |
358 | SOC_ENUM("DRC Attack", drc_atk), | |
359 | SOC_ENUM("DRC Decay", drc_dcy), | |
360 | SOC_SINGLE("DRC Quick Release Switch", WM9081_DRC_1, 2, 1, 0), | |
361 | SOC_SINGLE_TLV("DRC Quick Release Volume", WM9081_DRC_2, 6, 3, 0, drc_qr_tlv), | |
362 | SOC_ENUM("DRC Quick Release Decay", drc_qr_dcy), | |
363 | SOC_SINGLE_TLV("DRC Startup Volume", WM9081_DRC_1, 6, 18, 0, drc_startup_tlv), | |
364 | ||
365 | SOC_SINGLE("EQ Switch", WM9081_EQ_1, 0, 1, 0), | |
366 | ||
367 | SOC_SINGLE("Speaker DC Volume", WM9081_ANALOGUE_SPEAKER_1, 3, 5, 0), | |
368 | SOC_SINGLE("Speaker AC Volume", WM9081_ANALOGUE_SPEAKER_1, 0, 5, 0), | |
369 | SOC_SINGLE("Speaker Switch", WM9081_ANALOGUE_SPEAKER_PGA, 7, 1, 1), | |
370 | SOC_SINGLE("Speaker ZC Switch", WM9081_ANALOGUE_SPEAKER_PGA, 6, 1, 0), | |
371 | SOC_SINGLE_TLV("Speaker Volume", WM9081_ANALOGUE_SPEAKER_PGA, 0, 63, 0, | |
372 | out_tlv), | |
373 | SOC_ENUM("DAC Deemphasis", dac_deemph), | |
374 | SOC_ENUM_EXT("Speaker Mode", speaker_mode, speaker_mode_get, speaker_mode_put), | |
375 | }; | |
376 | ||
377 | static const struct snd_kcontrol_new wm9081_eq_controls[] = { | |
378 | SOC_SINGLE_TLV("EQ1 Volume", WM9081_EQ_1, 11, 24, 0, eq_tlv), | |
379 | SOC_SINGLE_TLV("EQ2 Volume", WM9081_EQ_1, 6, 24, 0, eq_tlv), | |
380 | SOC_SINGLE_TLV("EQ3 Volume", WM9081_EQ_1, 1, 24, 0, eq_tlv), | |
381 | SOC_SINGLE_TLV("EQ4 Volume", WM9081_EQ_2, 11, 24, 0, eq_tlv), | |
382 | SOC_SINGLE_TLV("EQ5 Volume", WM9081_EQ_2, 6, 24, 0, eq_tlv), | |
383 | }; | |
384 | ||
385 | static const struct snd_kcontrol_new mixer[] = { | |
386 | SOC_DAPM_SINGLE("IN1 Switch", WM9081_ANALOGUE_MIXER, 0, 1, 0), | |
387 | SOC_DAPM_SINGLE("IN2 Switch", WM9081_ANALOGUE_MIXER, 2, 1, 0), | |
388 | SOC_DAPM_SINGLE("Playback Switch", WM9081_ANALOGUE_MIXER, 4, 1, 0), | |
389 | }; | |
390 | ||
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391 | struct _fll_div { |
392 | u16 fll_fratio; | |
393 | u16 fll_outdiv; | |
394 | u16 fll_clk_ref_div; | |
395 | u16 n; | |
396 | u16 k; | |
397 | }; | |
398 | ||
399 | /* The size in bits of the FLL divide multiplied by 10 | |
400 | * to allow rounding later */ | |
401 | #define FIXED_FLL_SIZE ((1 << 16) * 10) | |
402 | ||
403 | static struct { | |
404 | unsigned int min; | |
405 | unsigned int max; | |
406 | u16 fll_fratio; | |
407 | int ratio; | |
408 | } fll_fratios[] = { | |
409 | { 0, 64000, 4, 16 }, | |
410 | { 64000, 128000, 3, 8 }, | |
411 | { 128000, 256000, 2, 4 }, | |
412 | { 256000, 1000000, 1, 2 }, | |
413 | { 1000000, 13500000, 0, 1 }, | |
414 | }; | |
415 | ||
416 | static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, | |
417 | unsigned int Fout) | |
418 | { | |
419 | u64 Kpart; | |
420 | unsigned int K, Ndiv, Nmod, target; | |
421 | unsigned int div; | |
422 | int i; | |
423 | ||
424 | /* Fref must be <=13.5MHz */ | |
425 | div = 1; | |
426 | while ((Fref / div) > 13500000) { | |
427 | div *= 2; | |
428 | ||
429 | if (div > 8) { | |
430 | pr_err("Can't scale %dMHz input down to <=13.5MHz\n", | |
431 | Fref); | |
432 | return -EINVAL; | |
433 | } | |
434 | } | |
435 | fll_div->fll_clk_ref_div = div / 2; | |
436 | ||
437 | pr_debug("Fref=%u Fout=%u\n", Fref, Fout); | |
438 | ||
439 | /* Apply the division for our remaining calculations */ | |
440 | Fref /= div; | |
441 | ||
442 | /* Fvco should be 90-100MHz; don't check the upper bound */ | |
443 | div = 0; | |
444 | target = Fout * 2; | |
445 | while (target < 90000000) { | |
446 | div++; | |
447 | target *= 2; | |
448 | if (div > 7) { | |
449 | pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n", | |
450 | Fout); | |
451 | return -EINVAL; | |
452 | } | |
453 | } | |
454 | fll_div->fll_outdiv = div; | |
455 | ||
456 | pr_debug("Fvco=%dHz\n", target); | |
457 | ||
25985edc | 458 | /* Find an appropriate FLL_FRATIO and factor it out of the target */ |
86ed3669 MB |
459 | for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { |
460 | if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) { | |
461 | fll_div->fll_fratio = fll_fratios[i].fll_fratio; | |
462 | target /= fll_fratios[i].ratio; | |
463 | break; | |
464 | } | |
465 | } | |
466 | if (i == ARRAY_SIZE(fll_fratios)) { | |
467 | pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref); | |
468 | return -EINVAL; | |
469 | } | |
470 | ||
471 | /* Now, calculate N.K */ | |
472 | Ndiv = target / Fref; | |
473 | ||
474 | fll_div->n = Ndiv; | |
475 | Nmod = target % Fref; | |
476 | pr_debug("Nmod=%d\n", Nmod); | |
477 | ||
478 | /* Calculate fractional part - scale up so we can round. */ | |
479 | Kpart = FIXED_FLL_SIZE * (long long)Nmod; | |
480 | ||
481 | do_div(Kpart, Fref); | |
482 | ||
483 | K = Kpart & 0xFFFFFFFF; | |
484 | ||
485 | if ((K % 10) >= 5) | |
486 | K += 5; | |
487 | ||
488 | /* Move down to proper range now rounding is done */ | |
489 | fll_div->k = K / 10; | |
490 | ||
491 | pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n", | |
492 | fll_div->n, fll_div->k, | |
493 | fll_div->fll_fratio, fll_div->fll_outdiv, | |
494 | fll_div->fll_clk_ref_div); | |
495 | ||
496 | return 0; | |
497 | } | |
498 | ||
499 | static int wm9081_set_fll(struct snd_soc_codec *codec, int fll_id, | |
500 | unsigned int Fref, unsigned int Fout) | |
501 | { | |
b2c812e2 | 502 | struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec); |
86ed3669 MB |
503 | u16 reg1, reg4, reg5; |
504 | struct _fll_div fll_div; | |
505 | int ret; | |
506 | int clk_sys_reg; | |
507 | ||
508 | /* Any change? */ | |
509 | if (Fref == wm9081->fll_fref && Fout == wm9081->fll_fout) | |
510 | return 0; | |
511 | ||
512 | /* Disable the FLL */ | |
513 | if (Fout == 0) { | |
514 | dev_dbg(codec->dev, "FLL disabled\n"); | |
515 | wm9081->fll_fref = 0; | |
516 | wm9081->fll_fout = 0; | |
517 | ||
518 | return 0; | |
519 | } | |
520 | ||
521 | ret = fll_factors(&fll_div, Fref, Fout); | |
522 | if (ret != 0) | |
523 | return ret; | |
524 | ||
8d50e447 | 525 | reg5 = snd_soc_read(codec, WM9081_FLL_CONTROL_5); |
86ed3669 MB |
526 | reg5 &= ~WM9081_FLL_CLK_SRC_MASK; |
527 | ||
528 | switch (fll_id) { | |
529 | case WM9081_SYSCLK_FLL_MCLK: | |
530 | reg5 |= 0x1; | |
531 | break; | |
532 | ||
533 | default: | |
534 | dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id); | |
535 | return -EINVAL; | |
536 | } | |
537 | ||
538 | /* Disable CLK_SYS while we reconfigure */ | |
8d50e447 | 539 | clk_sys_reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_3); |
86ed3669 | 540 | if (clk_sys_reg & WM9081_CLK_SYS_ENA) |
8d50e447 | 541 | snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, |
86ed3669 MB |
542 | clk_sys_reg & ~WM9081_CLK_SYS_ENA); |
543 | ||
544 | /* Any FLL configuration change requires that the FLL be | |
545 | * disabled first. */ | |
8d50e447 | 546 | reg1 = snd_soc_read(codec, WM9081_FLL_CONTROL_1); |
86ed3669 | 547 | reg1 &= ~WM9081_FLL_ENA; |
8d50e447 | 548 | snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1); |
86ed3669 MB |
549 | |
550 | /* Apply the configuration */ | |
551 | if (fll_div.k) | |
552 | reg1 |= WM9081_FLL_FRAC_MASK; | |
553 | else | |
554 | reg1 &= ~WM9081_FLL_FRAC_MASK; | |
8d50e447 | 555 | snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1); |
86ed3669 | 556 | |
8d50e447 | 557 | snd_soc_write(codec, WM9081_FLL_CONTROL_2, |
86ed3669 MB |
558 | (fll_div.fll_outdiv << WM9081_FLL_OUTDIV_SHIFT) | |
559 | (fll_div.fll_fratio << WM9081_FLL_FRATIO_SHIFT)); | |
8d50e447 | 560 | snd_soc_write(codec, WM9081_FLL_CONTROL_3, fll_div.k); |
86ed3669 | 561 | |
8d50e447 | 562 | reg4 = snd_soc_read(codec, WM9081_FLL_CONTROL_4); |
86ed3669 MB |
563 | reg4 &= ~WM9081_FLL_N_MASK; |
564 | reg4 |= fll_div.n << WM9081_FLL_N_SHIFT; | |
8d50e447 | 565 | snd_soc_write(codec, WM9081_FLL_CONTROL_4, reg4); |
86ed3669 MB |
566 | |
567 | reg5 &= ~WM9081_FLL_CLK_REF_DIV_MASK; | |
568 | reg5 |= fll_div.fll_clk_ref_div << WM9081_FLL_CLK_REF_DIV_SHIFT; | |
8d50e447 | 569 | snd_soc_write(codec, WM9081_FLL_CONTROL_5, reg5); |
86ed3669 | 570 | |
249c5156 MB |
571 | /* Set gain to the recommended value */ |
572 | snd_soc_update_bits(codec, WM9081_FLL_CONTROL_4, | |
573 | WM9081_FLL_GAIN_MASK, 0); | |
574 | ||
86ed3669 | 575 | /* Enable the FLL */ |
8d50e447 | 576 | snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1 | WM9081_FLL_ENA); |
86ed3669 MB |
577 | |
578 | /* Then bring CLK_SYS up again if it was disabled */ | |
579 | if (clk_sys_reg & WM9081_CLK_SYS_ENA) | |
8d50e447 | 580 | snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, clk_sys_reg); |
86ed3669 MB |
581 | |
582 | dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout); | |
583 | ||
584 | wm9081->fll_fref = Fref; | |
585 | wm9081->fll_fout = Fout; | |
586 | ||
587 | return 0; | |
588 | } | |
589 | ||
590 | static int configure_clock(struct snd_soc_codec *codec) | |
591 | { | |
b2c812e2 | 592 | struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec); |
86ed3669 MB |
593 | int new_sysclk, i, target; |
594 | unsigned int reg; | |
595 | int ret = 0; | |
596 | int mclkdiv = 0; | |
597 | int fll = 0; | |
598 | ||
599 | switch (wm9081->sysclk_source) { | |
600 | case WM9081_SYSCLK_MCLK: | |
601 | if (wm9081->mclk_rate > 12225000) { | |
602 | mclkdiv = 1; | |
603 | wm9081->sysclk_rate = wm9081->mclk_rate / 2; | |
604 | } else { | |
605 | wm9081->sysclk_rate = wm9081->mclk_rate; | |
606 | } | |
607 | wm9081_set_fll(codec, WM9081_SYSCLK_FLL_MCLK, 0, 0); | |
608 | break; | |
609 | ||
610 | case WM9081_SYSCLK_FLL_MCLK: | |
611 | /* If we have a sample rate calculate a CLK_SYS that | |
612 | * gives us a suitable DAC configuration, plus BCLK. | |
613 | * Ideally we would check to see if we can clock | |
614 | * directly from MCLK and only use the FLL if this is | |
615 | * not the case, though care must be taken with free | |
616 | * running mode. | |
617 | */ | |
618 | if (wm9081->master && wm9081->bclk) { | |
619 | /* Make sure we can generate CLK_SYS and BCLK | |
620 | * and that we've got 3MHz for optimal | |
621 | * performance. */ | |
622 | for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) { | |
623 | target = wm9081->fs * clk_sys_rates[i].ratio; | |
0154724d | 624 | new_sysclk = target; |
86ed3669 MB |
625 | if (target >= wm9081->bclk && |
626 | target > 3000000) | |
0154724d | 627 | break; |
86ed3669 | 628 | } |
4b75e947 MB |
629 | |
630 | if (i == ARRAY_SIZE(clk_sys_rates)) | |
631 | return -EINVAL; | |
632 | ||
86ed3669 MB |
633 | } else if (wm9081->fs) { |
634 | for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) { | |
635 | new_sysclk = clk_sys_rates[i].ratio | |
636 | * wm9081->fs; | |
637 | if (new_sysclk > 3000000) | |
638 | break; | |
639 | } | |
4b75e947 MB |
640 | |
641 | if (i == ARRAY_SIZE(clk_sys_rates)) | |
642 | return -EINVAL; | |
643 | ||
86ed3669 MB |
644 | } else { |
645 | new_sysclk = 12288000; | |
646 | } | |
647 | ||
648 | ret = wm9081_set_fll(codec, WM9081_SYSCLK_FLL_MCLK, | |
649 | wm9081->mclk_rate, new_sysclk); | |
650 | if (ret == 0) { | |
651 | wm9081->sysclk_rate = new_sysclk; | |
652 | ||
653 | /* Switch SYSCLK over to FLL */ | |
654 | fll = 1; | |
655 | } else { | |
656 | wm9081->sysclk_rate = wm9081->mclk_rate; | |
657 | } | |
658 | break; | |
659 | ||
660 | default: | |
661 | return -EINVAL; | |
662 | } | |
663 | ||
8d50e447 | 664 | reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_1); |
86ed3669 MB |
665 | if (mclkdiv) |
666 | reg |= WM9081_MCLKDIV2; | |
667 | else | |
668 | reg &= ~WM9081_MCLKDIV2; | |
8d50e447 | 669 | snd_soc_write(codec, WM9081_CLOCK_CONTROL_1, reg); |
86ed3669 | 670 | |
8d50e447 | 671 | reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_3); |
86ed3669 MB |
672 | if (fll) |
673 | reg |= WM9081_CLK_SRC_SEL; | |
674 | else | |
675 | reg &= ~WM9081_CLK_SRC_SEL; | |
8d50e447 | 676 | snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, reg); |
86ed3669 MB |
677 | |
678 | dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm9081->sysclk_rate); | |
679 | ||
680 | return ret; | |
681 | } | |
682 | ||
683 | static int clk_sys_event(struct snd_soc_dapm_widget *w, | |
684 | struct snd_kcontrol *kcontrol, int event) | |
685 | { | |
686 | struct snd_soc_codec *codec = w->codec; | |
b2c812e2 | 687 | struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec); |
86ed3669 MB |
688 | |
689 | /* This should be done on init() for bypass paths */ | |
690 | switch (wm9081->sysclk_source) { | |
691 | case WM9081_SYSCLK_MCLK: | |
692 | dev_dbg(codec->dev, "Using %dHz MCLK\n", wm9081->mclk_rate); | |
693 | break; | |
694 | case WM9081_SYSCLK_FLL_MCLK: | |
695 | dev_dbg(codec->dev, "Using %dHz MCLK with FLL\n", | |
696 | wm9081->mclk_rate); | |
697 | break; | |
698 | default: | |
699 | dev_err(codec->dev, "System clock not configured\n"); | |
700 | return -EINVAL; | |
701 | } | |
702 | ||
703 | switch (event) { | |
704 | case SND_SOC_DAPM_PRE_PMU: | |
705 | configure_clock(codec); | |
706 | break; | |
707 | ||
708 | case SND_SOC_DAPM_POST_PMD: | |
709 | /* Disable the FLL if it's running */ | |
710 | wm9081_set_fll(codec, 0, 0, 0); | |
711 | break; | |
712 | } | |
713 | ||
714 | return 0; | |
715 | } | |
716 | ||
717 | static const struct snd_soc_dapm_widget wm9081_dapm_widgets[] = { | |
718 | SND_SOC_DAPM_INPUT("IN1"), | |
719 | SND_SOC_DAPM_INPUT("IN2"), | |
720 | ||
721 | SND_SOC_DAPM_DAC("DAC", "HiFi Playback", WM9081_POWER_MANAGEMENT, 0, 0), | |
722 | ||
723 | SND_SOC_DAPM_MIXER_NAMED_CTL("Mixer", SND_SOC_NOPM, 0, 0, | |
724 | mixer, ARRAY_SIZE(mixer)), | |
725 | ||
726 | SND_SOC_DAPM_PGA("LINEOUT PGA", WM9081_POWER_MANAGEMENT, 4, 0, NULL, 0), | |
727 | ||
378a90f4 | 728 | SND_SOC_DAPM_PGA("Speaker PGA", WM9081_POWER_MANAGEMENT, 2, 0, NULL, 0), |
4e8e78e3 | 729 | SND_SOC_DAPM_OUT_DRV("Speaker", WM9081_POWER_MANAGEMENT, 1, 0, NULL, 0), |
86ed3669 MB |
730 | |
731 | SND_SOC_DAPM_OUTPUT("LINEOUT"), | |
732 | SND_SOC_DAPM_OUTPUT("SPKN"), | |
733 | SND_SOC_DAPM_OUTPUT("SPKP"), | |
734 | ||
735 | SND_SOC_DAPM_SUPPLY("CLK_SYS", WM9081_CLOCK_CONTROL_3, 0, 0, clk_sys_event, | |
736 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), | |
737 | SND_SOC_DAPM_SUPPLY("CLK_DSP", WM9081_CLOCK_CONTROL_3, 1, 0, NULL, 0), | |
738 | SND_SOC_DAPM_SUPPLY("TOCLK", WM9081_CLOCK_CONTROL_3, 2, 0, NULL, 0), | |
739 | }; | |
740 | ||
741 | ||
149c7b44 | 742 | static const struct snd_soc_dapm_route wm9081_audio_paths[] = { |
86ed3669 MB |
743 | { "DAC", NULL, "CLK_SYS" }, |
744 | { "DAC", NULL, "CLK_DSP" }, | |
745 | ||
746 | { "Mixer", "IN1 Switch", "IN1" }, | |
747 | { "Mixer", "IN2 Switch", "IN2" }, | |
748 | { "Mixer", "Playback Switch", "DAC" }, | |
749 | ||
750 | { "LINEOUT PGA", NULL, "Mixer" }, | |
751 | { "LINEOUT PGA", NULL, "TOCLK" }, | |
752 | { "LINEOUT PGA", NULL, "CLK_SYS" }, | |
753 | ||
754 | { "LINEOUT", NULL, "LINEOUT PGA" }, | |
755 | ||
756 | { "Speaker PGA", NULL, "Mixer" }, | |
757 | { "Speaker PGA", NULL, "TOCLK" }, | |
758 | { "Speaker PGA", NULL, "CLK_SYS" }, | |
759 | ||
378a90f4 MB |
760 | { "Speaker", NULL, "Speaker PGA" }, |
761 | ||
762 | { "SPKN", NULL, "Speaker" }, | |
763 | { "SPKP", NULL, "Speaker" }, | |
86ed3669 MB |
764 | }; |
765 | ||
766 | static int wm9081_set_bias_level(struct snd_soc_codec *codec, | |
767 | enum snd_soc_bias_level level) | |
768 | { | |
769 | u16 reg; | |
770 | ||
771 | switch (level) { | |
772 | case SND_SOC_BIAS_ON: | |
773 | break; | |
774 | ||
775 | case SND_SOC_BIAS_PREPARE: | |
776 | /* VMID=2*40k */ | |
8d50e447 | 777 | reg = snd_soc_read(codec, WM9081_VMID_CONTROL); |
86ed3669 MB |
778 | reg &= ~WM9081_VMID_SEL_MASK; |
779 | reg |= 0x2; | |
8d50e447 | 780 | snd_soc_write(codec, WM9081_VMID_CONTROL, reg); |
86ed3669 MB |
781 | |
782 | /* Normal bias current */ | |
8d50e447 | 783 | reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1); |
86ed3669 | 784 | reg &= ~WM9081_STBY_BIAS_ENA; |
8d50e447 | 785 | snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg); |
86ed3669 MB |
786 | break; |
787 | ||
788 | case SND_SOC_BIAS_STANDBY: | |
789 | /* Initial cold start */ | |
ce6120cc | 790 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { |
86ed3669 | 791 | /* Disable LINEOUT discharge */ |
8d50e447 | 792 | reg = snd_soc_read(codec, WM9081_ANTI_POP_CONTROL); |
86ed3669 | 793 | reg &= ~WM9081_LINEOUT_DISCH; |
8d50e447 | 794 | snd_soc_write(codec, WM9081_ANTI_POP_CONTROL, reg); |
86ed3669 MB |
795 | |
796 | /* Select startup bias source */ | |
8d50e447 | 797 | reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1); |
86ed3669 | 798 | reg |= WM9081_BIAS_SRC | WM9081_BIAS_ENA; |
8d50e447 | 799 | snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg); |
86ed3669 MB |
800 | |
801 | /* VMID 2*4k; Soft VMID ramp enable */ | |
8d50e447 | 802 | reg = snd_soc_read(codec, WM9081_VMID_CONTROL); |
86ed3669 | 803 | reg |= WM9081_VMID_RAMP | 0x6; |
8d50e447 | 804 | snd_soc_write(codec, WM9081_VMID_CONTROL, reg); |
86ed3669 MB |
805 | |
806 | mdelay(100); | |
807 | ||
808 | /* Normal bias enable & soft start off */ | |
809 | reg |= WM9081_BIAS_ENA; | |
810 | reg &= ~WM9081_VMID_RAMP; | |
8d50e447 | 811 | snd_soc_write(codec, WM9081_VMID_CONTROL, reg); |
86ed3669 MB |
812 | |
813 | /* Standard bias source */ | |
8d50e447 | 814 | reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1); |
86ed3669 | 815 | reg &= ~WM9081_BIAS_SRC; |
8d50e447 | 816 | snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg); |
86ed3669 MB |
817 | } |
818 | ||
819 | /* VMID 2*240k */ | |
8d50e447 | 820 | reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1); |
86ed3669 MB |
821 | reg &= ~WM9081_VMID_SEL_MASK; |
822 | reg |= 0x40; | |
8d50e447 | 823 | snd_soc_write(codec, WM9081_VMID_CONTROL, reg); |
86ed3669 MB |
824 | |
825 | /* Standby bias current on */ | |
8d50e447 | 826 | reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1); |
86ed3669 | 827 | reg |= WM9081_STBY_BIAS_ENA; |
8d50e447 | 828 | snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg); |
86ed3669 MB |
829 | break; |
830 | ||
831 | case SND_SOC_BIAS_OFF: | |
832 | /* Startup bias source */ | |
8d50e447 | 833 | reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1); |
86ed3669 | 834 | reg |= WM9081_BIAS_SRC; |
8d50e447 | 835 | snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg); |
86ed3669 MB |
836 | |
837 | /* Disable VMID and biases with soft ramping */ | |
8d50e447 | 838 | reg = snd_soc_read(codec, WM9081_VMID_CONTROL); |
86ed3669 MB |
839 | reg &= ~(WM9081_VMID_SEL_MASK | WM9081_BIAS_ENA); |
840 | reg |= WM9081_VMID_RAMP; | |
8d50e447 | 841 | snd_soc_write(codec, WM9081_VMID_CONTROL, reg); |
86ed3669 MB |
842 | |
843 | /* Actively discharge LINEOUT */ | |
8d50e447 | 844 | reg = snd_soc_read(codec, WM9081_ANTI_POP_CONTROL); |
86ed3669 | 845 | reg |= WM9081_LINEOUT_DISCH; |
8d50e447 | 846 | snd_soc_write(codec, WM9081_ANTI_POP_CONTROL, reg); |
86ed3669 MB |
847 | break; |
848 | } | |
849 | ||
ce6120cc | 850 | codec->dapm.bias_level = level; |
86ed3669 MB |
851 | |
852 | return 0; | |
853 | } | |
854 | ||
855 | static int wm9081_set_dai_fmt(struct snd_soc_dai *dai, | |
856 | unsigned int fmt) | |
857 | { | |
858 | struct snd_soc_codec *codec = dai->codec; | |
b2c812e2 | 859 | struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec); |
8d50e447 | 860 | unsigned int aif2 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_2); |
86ed3669 MB |
861 | |
862 | aif2 &= ~(WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV | | |
863 | WM9081_BCLK_DIR | WM9081_LRCLK_DIR | WM9081_AIF_FMT_MASK); | |
864 | ||
865 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
866 | case SND_SOC_DAIFMT_CBS_CFS: | |
867 | wm9081->master = 0; | |
868 | break; | |
869 | case SND_SOC_DAIFMT_CBS_CFM: | |
870 | aif2 |= WM9081_LRCLK_DIR; | |
871 | wm9081->master = 1; | |
872 | break; | |
873 | case SND_SOC_DAIFMT_CBM_CFS: | |
874 | aif2 |= WM9081_BCLK_DIR; | |
875 | wm9081->master = 1; | |
876 | break; | |
877 | case SND_SOC_DAIFMT_CBM_CFM: | |
878 | aif2 |= WM9081_LRCLK_DIR | WM9081_BCLK_DIR; | |
879 | wm9081->master = 1; | |
880 | break; | |
881 | default: | |
882 | return -EINVAL; | |
883 | } | |
884 | ||
885 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
886 | case SND_SOC_DAIFMT_DSP_B: | |
887 | aif2 |= WM9081_AIF_LRCLK_INV; | |
888 | case SND_SOC_DAIFMT_DSP_A: | |
889 | aif2 |= 0x3; | |
890 | break; | |
891 | case SND_SOC_DAIFMT_I2S: | |
892 | aif2 |= 0x2; | |
893 | break; | |
894 | case SND_SOC_DAIFMT_RIGHT_J: | |
895 | break; | |
896 | case SND_SOC_DAIFMT_LEFT_J: | |
897 | aif2 |= 0x1; | |
898 | break; | |
899 | default: | |
900 | return -EINVAL; | |
901 | } | |
902 | ||
903 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
904 | case SND_SOC_DAIFMT_DSP_A: | |
905 | case SND_SOC_DAIFMT_DSP_B: | |
906 | /* frame inversion not valid for DSP modes */ | |
907 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
908 | case SND_SOC_DAIFMT_NB_NF: | |
909 | break; | |
910 | case SND_SOC_DAIFMT_IB_NF: | |
911 | aif2 |= WM9081_AIF_BCLK_INV; | |
912 | break; | |
913 | default: | |
914 | return -EINVAL; | |
915 | } | |
916 | break; | |
917 | ||
918 | case SND_SOC_DAIFMT_I2S: | |
919 | case SND_SOC_DAIFMT_RIGHT_J: | |
920 | case SND_SOC_DAIFMT_LEFT_J: | |
921 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
922 | case SND_SOC_DAIFMT_NB_NF: | |
923 | break; | |
924 | case SND_SOC_DAIFMT_IB_IF: | |
925 | aif2 |= WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV; | |
926 | break; | |
927 | case SND_SOC_DAIFMT_IB_NF: | |
928 | aif2 |= WM9081_AIF_BCLK_INV; | |
929 | break; | |
930 | case SND_SOC_DAIFMT_NB_IF: | |
931 | aif2 |= WM9081_AIF_LRCLK_INV; | |
932 | break; | |
933 | default: | |
934 | return -EINVAL; | |
935 | } | |
936 | break; | |
937 | default: | |
938 | return -EINVAL; | |
939 | } | |
940 | ||
8d50e447 | 941 | snd_soc_write(codec, WM9081_AUDIO_INTERFACE_2, aif2); |
86ed3669 MB |
942 | |
943 | return 0; | |
944 | } | |
945 | ||
946 | static int wm9081_hw_params(struct snd_pcm_substream *substream, | |
947 | struct snd_pcm_hw_params *params, | |
948 | struct snd_soc_dai *dai) | |
949 | { | |
950 | struct snd_soc_codec *codec = dai->codec; | |
b2c812e2 | 951 | struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec); |
86ed3669 MB |
952 | int ret, i, best, best_val, cur_val; |
953 | unsigned int clk_ctrl2, aif1, aif2, aif3, aif4; | |
954 | ||
8d50e447 | 955 | clk_ctrl2 = snd_soc_read(codec, WM9081_CLOCK_CONTROL_2); |
86ed3669 MB |
956 | clk_ctrl2 &= ~(WM9081_CLK_SYS_RATE_MASK | WM9081_SAMPLE_RATE_MASK); |
957 | ||
8d50e447 | 958 | aif1 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_1); |
86ed3669 | 959 | |
8d50e447 | 960 | aif2 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_2); |
86ed3669 MB |
961 | aif2 &= ~WM9081_AIF_WL_MASK; |
962 | ||
8d50e447 | 963 | aif3 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_3); |
86ed3669 MB |
964 | aif3 &= ~WM9081_BCLK_DIV_MASK; |
965 | ||
8d50e447 | 966 | aif4 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_4); |
86ed3669 MB |
967 | aif4 &= ~WM9081_LRCLK_RATE_MASK; |
968 | ||
86ed3669 | 969 | wm9081->fs = params_rate(params); |
86ed3669 | 970 | |
e0026bea MB |
971 | if (wm9081->tdm_width) { |
972 | /* If TDM is set up then that fixes our BCLK. */ | |
86ed3669 MB |
973 | int slots = ((aif1 & WM9081_AIFDAC_TDM_MODE_MASK) >> |
974 | WM9081_AIFDAC_TDM_MODE_SHIFT) + 1; | |
e0026bea MB |
975 | |
976 | wm9081->bclk = wm9081->fs * wm9081->tdm_width * slots; | |
977 | } else { | |
978 | /* Otherwise work out a BCLK from the sample size */ | |
979 | wm9081->bclk = 2 * wm9081->fs; | |
980 | ||
981 | switch (params_format(params)) { | |
982 | case SNDRV_PCM_FORMAT_S16_LE: | |
983 | wm9081->bclk *= 16; | |
984 | break; | |
985 | case SNDRV_PCM_FORMAT_S20_3LE: | |
986 | wm9081->bclk *= 20; | |
987 | aif2 |= 0x4; | |
988 | break; | |
989 | case SNDRV_PCM_FORMAT_S24_LE: | |
990 | wm9081->bclk *= 24; | |
991 | aif2 |= 0x8; | |
992 | break; | |
993 | case SNDRV_PCM_FORMAT_S32_LE: | |
994 | wm9081->bclk *= 32; | |
995 | aif2 |= 0xc; | |
996 | break; | |
997 | default: | |
998 | return -EINVAL; | |
999 | } | |
86ed3669 MB |
1000 | } |
1001 | ||
1002 | dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm9081->bclk); | |
1003 | ||
1004 | ret = configure_clock(codec); | |
1005 | if (ret != 0) | |
1006 | return ret; | |
1007 | ||
1008 | /* Select nearest CLK_SYS_RATE */ | |
1009 | best = 0; | |
1010 | best_val = abs((wm9081->sysclk_rate / clk_sys_rates[0].ratio) | |
1011 | - wm9081->fs); | |
1012 | for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) { | |
1013 | cur_val = abs((wm9081->sysclk_rate / | |
a419aef8 | 1014 | clk_sys_rates[i].ratio) - wm9081->fs); |
86ed3669 MB |
1015 | if (cur_val < best_val) { |
1016 | best = i; | |
1017 | best_val = cur_val; | |
1018 | } | |
1019 | } | |
1020 | dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n", | |
1021 | clk_sys_rates[best].ratio); | |
1022 | clk_ctrl2 |= (clk_sys_rates[best].clk_sys_rate | |
1023 | << WM9081_CLK_SYS_RATE_SHIFT); | |
1024 | ||
1025 | /* SAMPLE_RATE */ | |
1026 | best = 0; | |
1027 | best_val = abs(wm9081->fs - sample_rates[0].rate); | |
1028 | for (i = 1; i < ARRAY_SIZE(sample_rates); i++) { | |
1029 | /* Closest match */ | |
1030 | cur_val = abs(wm9081->fs - sample_rates[i].rate); | |
1031 | if (cur_val < best_val) { | |
1032 | best = i; | |
1033 | best_val = cur_val; | |
1034 | } | |
1035 | } | |
1036 | dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n", | |
1037 | sample_rates[best].rate); | |
0154724d MB |
1038 | clk_ctrl2 |= (sample_rates[best].sample_rate |
1039 | << WM9081_SAMPLE_RATE_SHIFT); | |
86ed3669 MB |
1040 | |
1041 | /* BCLK_DIV */ | |
1042 | best = 0; | |
1043 | best_val = INT_MAX; | |
1044 | for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { | |
1045 | cur_val = ((wm9081->sysclk_rate * 10) / bclk_divs[i].div) | |
1046 | - wm9081->bclk; | |
1047 | if (cur_val < 0) /* Table is sorted */ | |
1048 | break; | |
1049 | if (cur_val < best_val) { | |
1050 | best = i; | |
1051 | best_val = cur_val; | |
1052 | } | |
1053 | } | |
1054 | wm9081->bclk = (wm9081->sysclk_rate * 10) / bclk_divs[best].div; | |
1055 | dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n", | |
1056 | bclk_divs[best].div, wm9081->bclk); | |
1057 | aif3 |= bclk_divs[best].bclk_div; | |
1058 | ||
1059 | /* LRCLK is a simple fraction of BCLK */ | |
1060 | dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm9081->bclk / wm9081->fs); | |
1061 | aif4 |= wm9081->bclk / wm9081->fs; | |
1062 | ||
1063 | /* Apply a ReTune Mobile configuration if it's in use */ | |
4a5f7bda MB |
1064 | if (wm9081->pdata.num_retune_configs) { |
1065 | struct wm9081_pdata *pdata = &wm9081->pdata; | |
86ed3669 MB |
1066 | struct wm9081_retune_mobile_setting *s; |
1067 | int eq1; | |
1068 | ||
1069 | best = 0; | |
4a5f7bda MB |
1070 | best_val = abs(pdata->retune_configs[0].rate - wm9081->fs); |
1071 | for (i = 0; i < pdata->num_retune_configs; i++) { | |
1072 | cur_val = abs(pdata->retune_configs[i].rate - | |
1073 | wm9081->fs); | |
86ed3669 MB |
1074 | if (cur_val < best_val) { |
1075 | best_val = cur_val; | |
1076 | best = i; | |
1077 | } | |
1078 | } | |
4a5f7bda | 1079 | s = &pdata->retune_configs[best]; |
86ed3669 MB |
1080 | |
1081 | dev_dbg(codec->dev, "ReTune Mobile %s tuned for %dHz\n", | |
1082 | s->name, s->rate); | |
1083 | ||
1084 | /* If the EQ is enabled then disable it while we write out */ | |
8d50e447 | 1085 | eq1 = snd_soc_read(codec, WM9081_EQ_1) & WM9081_EQ_ENA; |
86ed3669 | 1086 | if (eq1 & WM9081_EQ_ENA) |
8d50e447 | 1087 | snd_soc_write(codec, WM9081_EQ_1, 0); |
86ed3669 MB |
1088 | |
1089 | /* Write out the other values */ | |
1090 | for (i = 1; i < ARRAY_SIZE(s->config); i++) | |
8d50e447 | 1091 | snd_soc_write(codec, WM9081_EQ_1 + i, s->config[i]); |
86ed3669 MB |
1092 | |
1093 | eq1 |= (s->config[0] & ~WM9081_EQ_ENA); | |
8d50e447 | 1094 | snd_soc_write(codec, WM9081_EQ_1, eq1); |
86ed3669 MB |
1095 | } |
1096 | ||
8d50e447 MB |
1097 | snd_soc_write(codec, WM9081_CLOCK_CONTROL_2, clk_ctrl2); |
1098 | snd_soc_write(codec, WM9081_AUDIO_INTERFACE_2, aif2); | |
1099 | snd_soc_write(codec, WM9081_AUDIO_INTERFACE_3, aif3); | |
1100 | snd_soc_write(codec, WM9081_AUDIO_INTERFACE_4, aif4); | |
86ed3669 MB |
1101 | |
1102 | return 0; | |
1103 | } | |
1104 | ||
1105 | static int wm9081_digital_mute(struct snd_soc_dai *codec_dai, int mute) | |
1106 | { | |
1107 | struct snd_soc_codec *codec = codec_dai->codec; | |
1108 | unsigned int reg; | |
1109 | ||
8d50e447 | 1110 | reg = snd_soc_read(codec, WM9081_DAC_DIGITAL_2); |
86ed3669 MB |
1111 | |
1112 | if (mute) | |
1113 | reg |= WM9081_DAC_MUTE; | |
1114 | else | |
1115 | reg &= ~WM9081_DAC_MUTE; | |
1116 | ||
8d50e447 | 1117 | snd_soc_write(codec, WM9081_DAC_DIGITAL_2, reg); |
86ed3669 MB |
1118 | |
1119 | return 0; | |
1120 | } | |
1121 | ||
da1c6ea6 MB |
1122 | static int wm9081_set_sysclk(struct snd_soc_codec *codec, int clk_id, |
1123 | int source, unsigned int freq, int dir) | |
86ed3669 | 1124 | { |
b2c812e2 | 1125 | struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec); |
86ed3669 MB |
1126 | |
1127 | switch (clk_id) { | |
1128 | case WM9081_SYSCLK_MCLK: | |
1129 | case WM9081_SYSCLK_FLL_MCLK: | |
1130 | wm9081->sysclk_source = clk_id; | |
1131 | wm9081->mclk_rate = freq; | |
1132 | break; | |
1133 | ||
1134 | default: | |
1135 | return -EINVAL; | |
1136 | } | |
1137 | ||
1138 | return 0; | |
1139 | } | |
1140 | ||
1141 | static int wm9081_set_tdm_slot(struct snd_soc_dai *dai, | |
a5479e38 | 1142 | unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) |
86ed3669 MB |
1143 | { |
1144 | struct snd_soc_codec *codec = dai->codec; | |
b2c812e2 | 1145 | struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec); |
8d50e447 | 1146 | unsigned int aif1 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_1); |
86ed3669 MB |
1147 | |
1148 | aif1 &= ~(WM9081_AIFDAC_TDM_SLOT_MASK | WM9081_AIFDAC_TDM_MODE_MASK); | |
1149 | ||
e0026bea | 1150 | if (slots < 0 || slots > 4) |
86ed3669 MB |
1151 | return -EINVAL; |
1152 | ||
e0026bea MB |
1153 | wm9081->tdm_width = slot_width; |
1154 | ||
1155 | if (slots == 0) | |
1156 | slots = 1; | |
1157 | ||
86ed3669 MB |
1158 | aif1 |= (slots - 1) << WM9081_AIFDAC_TDM_MODE_SHIFT; |
1159 | ||
a5479e38 | 1160 | switch (rx_mask) { |
86ed3669 MB |
1161 | case 1: |
1162 | break; | |
1163 | case 2: | |
1164 | aif1 |= 0x10; | |
1165 | break; | |
1166 | case 4: | |
1167 | aif1 |= 0x20; | |
1168 | break; | |
1169 | case 8: | |
1170 | aif1 |= 0x30; | |
1171 | break; | |
1172 | default: | |
1173 | return -EINVAL; | |
1174 | } | |
1175 | ||
8d50e447 | 1176 | snd_soc_write(codec, WM9081_AUDIO_INTERFACE_1, aif1); |
86ed3669 MB |
1177 | |
1178 | return 0; | |
1179 | } | |
1180 | ||
1181 | #define WM9081_RATES SNDRV_PCM_RATE_8000_96000 | |
1182 | ||
1183 | #define WM9081_FORMATS \ | |
1184 | (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ | |
1185 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) | |
1186 | ||
1187 | static struct snd_soc_dai_ops wm9081_dai_ops = { | |
1188 | .hw_params = wm9081_hw_params, | |
86ed3669 MB |
1189 | .set_fmt = wm9081_set_dai_fmt, |
1190 | .digital_mute = wm9081_digital_mute, | |
1191 | .set_tdm_slot = wm9081_set_tdm_slot, | |
1192 | }; | |
1193 | ||
1194 | /* We report two channels because the CODEC processes a stereo signal, even | |
1195 | * though it is only capable of handling a mono output. | |
1196 | */ | |
f0fba2ad LG |
1197 | static struct snd_soc_dai_driver wm9081_dai = { |
1198 | .name = "wm9081-hifi", | |
86ed3669 MB |
1199 | .playback = { |
1200 | .stream_name = "HiFi Playback", | |
1201 | .channels_min = 1, | |
1202 | .channels_max = 2, | |
1203 | .rates = WM9081_RATES, | |
1204 | .formats = WM9081_FORMATS, | |
1205 | }, | |
1206 | .ops = &wm9081_dai_ops, | |
1207 | }; | |
86ed3669 | 1208 | |
f0fba2ad | 1209 | static int wm9081_probe(struct snd_soc_codec *codec) |
86ed3669 | 1210 | { |
f0fba2ad LG |
1211 | struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec); |
1212 | int ret; | |
1213 | u16 reg; | |
86ed3669 | 1214 | |
f0fba2ad LG |
1215 | ret = snd_soc_codec_set_cache_io(codec, 8, 16, wm9081->control_type); |
1216 | if (ret != 0) { | |
1217 | dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); | |
1218 | return ret; | |
86ed3669 MB |
1219 | } |
1220 | ||
f0fba2ad LG |
1221 | reg = snd_soc_read(codec, WM9081_SOFTWARE_RESET); |
1222 | if (reg != 0x9081) { | |
1223 | dev_err(codec->dev, "Device is not a WM9081: ID=0x%x\n", reg); | |
1224 | ret = -EINVAL; | |
1225 | return ret; | |
1226 | } | |
86ed3669 | 1227 | |
f0fba2ad | 1228 | ret = wm9081_reset(codec); |
86ed3669 | 1229 | if (ret < 0) { |
f0fba2ad LG |
1230 | dev_err(codec->dev, "Failed to issue reset\n"); |
1231 | return ret; | |
86ed3669 MB |
1232 | } |
1233 | ||
4a5f7bda MB |
1234 | reg = 0; |
1235 | if (wm9081->pdata.irq_high) | |
1236 | reg |= WM9081_IRQ_POL; | |
1237 | if (!wm9081->pdata.irq_cmos) | |
1238 | reg |= WM9081_IRQ_OP_CTRL; | |
1239 | snd_soc_update_bits(codec, WM9081_INTERRUPT_CONTROL, | |
1240 | WM9081_IRQ_POL | WM9081_IRQ_OP_CTRL, reg); | |
1241 | ||
f0fba2ad LG |
1242 | wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY); |
1243 | ||
1244 | /* Enable zero cross by default */ | |
1245 | reg = snd_soc_read(codec, WM9081_ANALOGUE_LINEOUT); | |
1246 | snd_soc_write(codec, WM9081_ANALOGUE_LINEOUT, reg | WM9081_LINEOUTZC); | |
1247 | reg = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_PGA); | |
1248 | snd_soc_write(codec, WM9081_ANALOGUE_SPEAKER_PGA, | |
1249 | reg | WM9081_SPKPGAZC); | |
1250 | ||
4a5f7bda | 1251 | if (!wm9081->pdata.num_retune_configs) { |
86ed3669 MB |
1252 | dev_dbg(codec->dev, |
1253 | "No ReTune Mobile data, using normal EQ\n"); | |
1254 | snd_soc_add_controls(codec, wm9081_eq_controls, | |
1255 | ARRAY_SIZE(wm9081_eq_controls)); | |
1256 | } | |
1257 | ||
86ed3669 | 1258 | return ret; |
86ed3669 MB |
1259 | } |
1260 | ||
f0fba2ad | 1261 | static int wm9081_remove(struct snd_soc_codec *codec) |
86ed3669 | 1262 | { |
f0fba2ad | 1263 | wm9081_set_bias_level(codec, SND_SOC_BIAS_OFF); |
86ed3669 MB |
1264 | return 0; |
1265 | } | |
1266 | ||
1267 | #ifdef CONFIG_PM | |
f0fba2ad | 1268 | static int wm9081_suspend(struct snd_soc_codec *codec, pm_message_t state) |
86ed3669 | 1269 | { |
86ed3669 MB |
1270 | wm9081_set_bias_level(codec, SND_SOC_BIAS_OFF); |
1271 | ||
1272 | return 0; | |
1273 | } | |
1274 | ||
f0fba2ad | 1275 | static int wm9081_resume(struct snd_soc_codec *codec) |
86ed3669 | 1276 | { |
86ed3669 MB |
1277 | u16 *reg_cache = codec->reg_cache; |
1278 | int i; | |
1279 | ||
f0fba2ad | 1280 | for (i = 0; i < codec->driver->reg_cache_size; i++) { |
86ed3669 MB |
1281 | if (i == WM9081_SOFTWARE_RESET) |
1282 | continue; | |
1283 | ||
8d50e447 | 1284 | snd_soc_write(codec, i, reg_cache[i]); |
86ed3669 MB |
1285 | } |
1286 | ||
1287 | wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
1288 | ||
1289 | return 0; | |
1290 | } | |
1291 | #else | |
1292 | #define wm9081_suspend NULL | |
1293 | #define wm9081_resume NULL | |
1294 | #endif | |
1295 | ||
f0fba2ad | 1296 | static struct snd_soc_codec_driver soc_codec_dev_wm9081 = { |
86ed3669 MB |
1297 | .probe = wm9081_probe, |
1298 | .remove = wm9081_remove, | |
1299 | .suspend = wm9081_suspend, | |
1300 | .resume = wm9081_resume, | |
63d24b79 MB |
1301 | |
1302 | .set_sysclk = wm9081_set_sysclk, | |
f0fba2ad | 1303 | .set_bias_level = wm9081_set_bias_level, |
63d24b79 | 1304 | |
e5eec34c | 1305 | .reg_cache_size = ARRAY_SIZE(wm9081_reg_defaults), |
f0fba2ad LG |
1306 | .reg_word_size = sizeof(u16), |
1307 | .reg_cache_default = wm9081_reg_defaults, | |
1308 | .volatile_register = wm9081_volatile_register, | |
63d24b79 | 1309 | |
680fa1f8 MB |
1310 | .controls = wm9081_snd_controls, |
1311 | .num_controls = ARRAY_SIZE(wm9081_snd_controls), | |
149c7b44 MB |
1312 | .dapm_widgets = wm9081_dapm_widgets, |
1313 | .num_dapm_widgets = ARRAY_SIZE(wm9081_dapm_widgets), | |
1314 | .dapm_routes = wm9081_audio_paths, | |
1315 | .num_dapm_routes = ARRAY_SIZE(wm9081_audio_paths), | |
86ed3669 | 1316 | }; |
86ed3669 | 1317 | |
f0fba2ad | 1318 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) |
86ed3669 MB |
1319 | static __devinit int wm9081_i2c_probe(struct i2c_client *i2c, |
1320 | const struct i2c_device_id *id) | |
1321 | { | |
1322 | struct wm9081_priv *wm9081; | |
f0fba2ad | 1323 | int ret; |
86ed3669 MB |
1324 | |
1325 | wm9081 = kzalloc(sizeof(struct wm9081_priv), GFP_KERNEL); | |
1326 | if (wm9081 == NULL) | |
1327 | return -ENOMEM; | |
1328 | ||
86ed3669 | 1329 | i2c_set_clientdata(i2c, wm9081); |
7f984b55 | 1330 | wm9081->control_type = SND_SOC_I2C; |
86ed3669 | 1331 | |
3ee845ac | 1332 | if (dev_get_platdata(&i2c->dev)) |
4a5f7bda MB |
1333 | memcpy(&wm9081->pdata, dev_get_platdata(&i2c->dev), |
1334 | sizeof(wm9081->pdata)); | |
3ee845ac | 1335 | |
f0fba2ad LG |
1336 | ret = snd_soc_register_codec(&i2c->dev, |
1337 | &soc_codec_dev_wm9081, &wm9081_dai, 1); | |
1338 | if (ret < 0) | |
1339 | kfree(wm9081); | |
1340 | return ret; | |
86ed3669 MB |
1341 | } |
1342 | ||
1343 | static __devexit int wm9081_i2c_remove(struct i2c_client *client) | |
1344 | { | |
f0fba2ad LG |
1345 | snd_soc_unregister_codec(&client->dev); |
1346 | kfree(i2c_get_clientdata(client)); | |
86ed3669 MB |
1347 | return 0; |
1348 | } | |
1349 | ||
1350 | static const struct i2c_device_id wm9081_i2c_id[] = { | |
1351 | { "wm9081", 0 }, | |
1352 | { } | |
1353 | }; | |
1354 | MODULE_DEVICE_TABLE(i2c, wm9081_i2c_id); | |
1355 | ||
1356 | static struct i2c_driver wm9081_i2c_driver = { | |
1357 | .driver = { | |
2031c064 | 1358 | .name = "wm9081", |
86ed3669 MB |
1359 | .owner = THIS_MODULE, |
1360 | }, | |
1361 | .probe = wm9081_i2c_probe, | |
1362 | .remove = __devexit_p(wm9081_i2c_remove), | |
1363 | .id_table = wm9081_i2c_id, | |
1364 | }; | |
f0fba2ad | 1365 | #endif |
86ed3669 MB |
1366 | |
1367 | static int __init wm9081_modinit(void) | |
1368 | { | |
f0fba2ad LG |
1369 | int ret = 0; |
1370 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) | |
86ed3669 MB |
1371 | ret = i2c_add_driver(&wm9081_i2c_driver); |
1372 | if (ret != 0) { | |
1373 | printk(KERN_ERR "Failed to register WM9081 I2C driver: %d\n", | |
1374 | ret); | |
1375 | } | |
f0fba2ad | 1376 | #endif |
86ed3669 MB |
1377 | return ret; |
1378 | } | |
1379 | module_init(wm9081_modinit); | |
1380 | ||
1381 | static void __exit wm9081_exit(void) | |
1382 | { | |
f0fba2ad | 1383 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) |
86ed3669 | 1384 | i2c_del_driver(&wm9081_i2c_driver); |
f0fba2ad | 1385 | #endif |
86ed3669 MB |
1386 | } |
1387 | module_exit(wm9081_exit); | |
1388 | ||
1389 | ||
1390 | MODULE_DESCRIPTION("ASoC WM9081 driver"); | |
1391 | MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); | |
1392 | MODULE_LICENSE("GPL"); |