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ASoC: ad1980 - set reg_cache_default to ad1980_reg
[deliverable/linux.git] / sound / soc / codecs / wm9081.c
CommitLineData
86ed3669
MB		 1/*
2 * wm9081.c -- WM9081 ALSA SoC Audio driver
3 *
4 * Author: Mark Brown
5 *
6 * Copyright 2009 Wolfson Microelectronics plc
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
5a0e3ad6 21#include <linux/slab.h>
86ed3669
MB		 22#include <sound/core.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h>
28#include <sound/tlv.h>
29
30#include <sound/wm9081.h>
31#include "wm9081.h"
32
33static u16 wm9081_reg_defaults[] = {
34 0x0000, /* R0 - Software Reset */
35 0x0000, /* R1 */
36 0x00B9, /* R2 - Analogue Lineout */
37 0x00B9, /* R3 - Analogue Speaker PGA */
38 0x0001, /* R4 - VMID Control */
39 0x0068, /* R5 - Bias Control 1 */
40 0x0000, /* R6 */
41 0x0000, /* R7 - Analogue Mixer */
42 0x0000, /* R8 - Anti Pop Control */
43 0x01DB, /* R9 - Analogue Speaker 1 */
44 0x0018, /* R10 - Analogue Speaker 2 */
45 0x0180, /* R11 - Power Management */
46 0x0000, /* R12 - Clock Control 1 */
47 0x0038, /* R13 - Clock Control 2 */
48 0x4000, /* R14 - Clock Control 3 */
49 0x0000, /* R15 */
50 0x0000, /* R16 - FLL Control 1 */
51 0x0200, /* R17 - FLL Control 2 */
52 0x0000, /* R18 - FLL Control 3 */
53 0x0204, /* R19 - FLL Control 4 */
54 0x0000, /* R20 - FLL Control 5 */
55 0x0000, /* R21 */
56 0x0000, /* R22 - Audio Interface 1 */
57 0x0002, /* R23 - Audio Interface 2 */
58 0x0008, /* R24 - Audio Interface 3 */
59 0x0022, /* R25 - Audio Interface 4 */
60 0x0000, /* R26 - Interrupt Status */
61 0x0006, /* R27 - Interrupt Status Mask */
62 0x0000, /* R28 - Interrupt Polarity */
63 0x0000, /* R29 - Interrupt Control */
64 0x00C0, /* R30 - DAC Digital 1 */
65 0x0008, /* R31 - DAC Digital 2 */
66 0x09AF, /* R32 - DRC 1 */
67 0x4201, /* R33 - DRC 2 */
68 0x0000, /* R34 - DRC 3 */
69 0x0000, /* R35 - DRC 4 */
70 0x0000, /* R36 */
71 0x0000, /* R37 */
72 0x0000, /* R38 - Write Sequencer 1 */
73 0x0000, /* R39 - Write Sequencer 2 */
74 0x0002, /* R40 - MW Slave 1 */
75 0x0000, /* R41 */
76 0x0000, /* R42 - EQ 1 */
77 0x0000, /* R43 - EQ 2 */
78 0x0FCA, /* R44 - EQ 3 */
79 0x0400, /* R45 - EQ 4 */
80 0x00B8, /* R46 - EQ 5 */
81 0x1EB5, /* R47 - EQ 6 */
82 0xF145, /* R48 - EQ 7 */
83 0x0B75, /* R49 - EQ 8 */
84 0x01C5, /* R50 - EQ 9 */
85 0x169E, /* R51 - EQ 10 */
86 0xF829, /* R52 - EQ 11 */
87 0x07AD, /* R53 - EQ 12 */
88 0x1103, /* R54 - EQ 13 */
89 0x1C58, /* R55 - EQ 14 */
90 0xF373, /* R56 - EQ 15 */
91 0x0A54, /* R57 - EQ 16 */
92 0x0558, /* R58 - EQ 17 */
93 0x0564, /* R59 - EQ 18 */
94 0x0559, /* R60 - EQ 19 */
95 0x4000, /* R61 - EQ 20 */
96};
97
98static struct {
99 int ratio;
100 int clk_sys_rate;
101} clk_sys_rates[] = {
102 { 64, 0 },
103 { 128, 1 },
104 { 192, 2 },
105 { 256, 3 },
106 { 384, 4 },
107 { 512, 5 },
108 { 768, 6 },
109 { 1024, 7 },
110 { 1408, 8 },
111 { 1536, 9 },
112};
113
114static struct {
115 int rate;
116 int sample_rate;
117} sample_rates[] = {
118 { 8000, 0 },
119 { 11025, 1 },
120 { 12000, 2 },
121 { 16000, 3 },
122 { 22050, 4 },
123 { 24000, 5 },
124 { 32000, 6 },
125 { 44100, 7 },
126 { 48000, 8 },
127 { 88200, 9 },
128 { 96000, 10 },
129};
130
131static struct {
132 int div; /* *10 due to .5s */
133 int bclk_div;
134} bclk_divs[] = {
135 { 10, 0 },
136 { 15, 1 },
137 { 20, 2 },
138 { 30, 3 },
139 { 40, 4 },
140 { 50, 5 },
141 { 55, 6 },
142 { 60, 7 },
143 { 80, 8 },
144 { 100, 9 },
145 { 110, 10 },
146 { 120, 11 },
147 { 160, 12 },
148 { 200, 13 },
149 { 220, 14 },
150 { 240, 15 },
151 { 250, 16 },
152 { 300, 17 },
153 { 320, 18 },
154 { 440, 19 },
155 { 480, 20 },
156};
157
158struct wm9081_priv {
f0fba2ad
LG		 159 enum snd_soc_control_type control_type;
160 void *control_data;
86ed3669
MB		 161 u16 reg_cache[WM9081_MAX_REGISTER + 1];
162 int sysclk_source;
163 int mclk_rate;
164 int sysclk_rate;
165 int fs;
166 int bclk;
167 int master;
168 int fll_fref;
169 int fll_fout;
e0026bea 170 int tdm_width;
86ed3669
MB		 171 struct wm9081_retune_mobile_config *retune;
172};
173
8d50e447 174static int wm9081_volatile_register(unsigned int reg)
86ed3669
MB		 175{
176 switch (reg) {
8d50e447
MB		 177 case WM9081_SOFTWARE_RESET:
178 return 1;
86ed3669
MB		 179 default:
180 return 0;
181 }
182}
183
86ed3669
MB		 184static int wm9081_reset(struct snd_soc_codec *codec)
185{
8d50e447 186 return snd_soc_write(codec, WM9081_SOFTWARE_RESET, 0);
86ed3669
MB		 187}
188
189static const DECLARE_TLV_DB_SCALE(drc_in_tlv, -4500, 75, 0);
190static const DECLARE_TLV_DB_SCALE(drc_out_tlv, -2250, 75, 0);
191static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0);
192static unsigned int drc_max_tlv[] = {
193 TLV_DB_RANGE_HEAD(4),
194 0, 0, TLV_DB_SCALE_ITEM(1200, 0, 0),
195 1, 1, TLV_DB_SCALE_ITEM(1800, 0, 0),
196 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
197 3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0),
198};
199static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0);
200static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -300, 50, 0);
201
202static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
203
204static const DECLARE_TLV_DB_SCALE(in_tlv, -600, 600, 0);
205static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
206static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
207
208static const char *drc_high_text[] = {
209 "1",
210 "1/2",
211 "1/4",
212 "1/8",
213 "1/16",
214 "0",
215};
216
217static const struct soc_enum drc_high =
218 SOC_ENUM_SINGLE(WM9081_DRC_3, 3, 6, drc_high_text);
219
220static const char *drc_low_text[] = {
221 "1",
222 "1/2",
223 "1/4",
224 "1/8",
225 "0",
226};
227
228static const struct soc_enum drc_low =
229 SOC_ENUM_SINGLE(WM9081_DRC_3, 0, 5, drc_low_text);
230
231static const char *drc_atk_text[] = {
232 "181us",
233 "181us",
234 "363us",
235 "726us",
236 "1.45ms",
237 "2.9ms",
238 "5.8ms",
239 "11.6ms",
240 "23.2ms",
241 "46.4ms",
242 "92.8ms",
243 "185.6ms",
244};
245
246static const struct soc_enum drc_atk =
247 SOC_ENUM_SINGLE(WM9081_DRC_2, 12, 12, drc_atk_text);
248
249static const char *drc_dcy_text[] = {
250 "186ms",
251 "372ms",
252 "743ms",
253 "1.49s",
254 "2.97s",
255 "5.94s",
256 "11.89s",
257 "23.78s",
258 "47.56s",
259};
260
261static const struct soc_enum drc_dcy =
262 SOC_ENUM_SINGLE(WM9081_DRC_2, 8, 9, drc_dcy_text);
263
264static const char *drc_qr_dcy_text[] = {
265 "0.725ms",
266 "1.45ms",
267 "5.8ms",
268};
269
270static const struct soc_enum drc_qr_dcy =
271 SOC_ENUM_SINGLE(WM9081_DRC_2, 4, 3, drc_qr_dcy_text);
272
273static const char *dac_deemph_text[] = {
274 "None",
275 "32kHz",
276 "44.1kHz",
277 "48kHz",
278};
279
280static const struct soc_enum dac_deemph =
281 SOC_ENUM_SINGLE(WM9081_DAC_DIGITAL_2, 1, 4, dac_deemph_text);
282
283static const char *speaker_mode_text[] = {
284 "Class D",
285 "Class AB",
286};
287
288static const struct soc_enum speaker_mode =
289 SOC_ENUM_SINGLE(WM9081_ANALOGUE_SPEAKER_2, 6, 2, speaker_mode_text);
290
291static int speaker_mode_get(struct snd_kcontrol *kcontrol,
292 struct snd_ctl_elem_value *ucontrol)
293{
294 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
295 unsigned int reg;
296
8d50e447 297 reg = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2);
86ed3669
MB		 298 if (reg & WM9081_SPK_MODE)
299 ucontrol->value.integer.value[0] = 1;
300 else
301 ucontrol->value.integer.value[0] = 0;
302
303 return 0;
304}
305
306/*
307 * Stop any attempts to change speaker mode while the speaker is enabled.
308 *
309 * We also have some special anti-pop controls dependant on speaker
310 * mode which must be changed along with the mode.
311 */
312static int speaker_mode_put(struct snd_kcontrol *kcontrol,
313 struct snd_ctl_elem_value *ucontrol)
314{
315 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
8d50e447
MB		 316 unsigned int reg_pwr = snd_soc_read(codec, WM9081_POWER_MANAGEMENT);
317 unsigned int reg2 = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2);
86ed3669
MB		 318
319 /* Are we changing anything? */
320 if (ucontrol->value.integer.value[0] ==
321 ((reg2 & WM9081_SPK_MODE) != 0))
322 return 0;
323
324 /* Don't try to change modes while enabled */
325 if (reg_pwr & WM9081_SPK_ENA)
326 return -EINVAL;
327
328 if (ucontrol->value.integer.value[0]) {
329 /* Class AB */
330 reg2 &= ~(WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL);
331 reg2 |= WM9081_SPK_MODE;
332 } else {
333 /* Class D */
334 reg2 |= WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL;
335 reg2 &= ~WM9081_SPK_MODE;
336 }
337
8d50e447 338 snd_soc_write(codec, WM9081_ANALOGUE_SPEAKER_2, reg2);
86ed3669
MB		 339
340 return 0;
341}
342
343static const struct snd_kcontrol_new wm9081_snd_controls[] = {
344SOC_SINGLE_TLV("IN1 Volume", WM9081_ANALOGUE_MIXER, 1, 1, 1, in_tlv),
345SOC_SINGLE_TLV("IN2 Volume", WM9081_ANALOGUE_MIXER, 3, 1, 1, in_tlv),
346
347SOC_SINGLE_TLV("Playback Volume", WM9081_DAC_DIGITAL_1, 1, 96, 0, dac_tlv),
348
349SOC_SINGLE("LINEOUT Switch", WM9081_ANALOGUE_LINEOUT, 7, 1, 1),
350SOC_SINGLE("LINEOUT ZC Switch", WM9081_ANALOGUE_LINEOUT, 6, 1, 0),
351SOC_SINGLE_TLV("LINEOUT Volume", WM9081_ANALOGUE_LINEOUT, 0, 63, 0, out_tlv),
352
353SOC_SINGLE("DRC Switch", WM9081_DRC_1, 15, 1, 0),
354SOC_ENUM("DRC High Slope", drc_high),
355SOC_ENUM("DRC Low Slope", drc_low),
356SOC_SINGLE_TLV("DRC Input Volume", WM9081_DRC_4, 5, 60, 1, drc_in_tlv),
357SOC_SINGLE_TLV("DRC Output Volume", WM9081_DRC_4, 0, 30, 1, drc_out_tlv),
358SOC_SINGLE_TLV("DRC Minimum Volume", WM9081_DRC_2, 2, 3, 1, drc_min_tlv),
359SOC_SINGLE_TLV("DRC Maximum Volume", WM9081_DRC_2, 0, 3, 0, drc_max_tlv),
360SOC_ENUM("DRC Attack", drc_atk),
361SOC_ENUM("DRC Decay", drc_dcy),
362SOC_SINGLE("DRC Quick Release Switch", WM9081_DRC_1, 2, 1, 0),
363SOC_SINGLE_TLV("DRC Quick Release Volume", WM9081_DRC_2, 6, 3, 0, drc_qr_tlv),
364SOC_ENUM("DRC Quick Release Decay", drc_qr_dcy),
365SOC_SINGLE_TLV("DRC Startup Volume", WM9081_DRC_1, 6, 18, 0, drc_startup_tlv),
366
367SOC_SINGLE("EQ Switch", WM9081_EQ_1, 0, 1, 0),
368
369SOC_SINGLE("Speaker DC Volume", WM9081_ANALOGUE_SPEAKER_1, 3, 5, 0),
370SOC_SINGLE("Speaker AC Volume", WM9081_ANALOGUE_SPEAKER_1, 0, 5, 0),
371SOC_SINGLE("Speaker Switch", WM9081_ANALOGUE_SPEAKER_PGA, 7, 1, 1),
372SOC_SINGLE("Speaker ZC Switch", WM9081_ANALOGUE_SPEAKER_PGA, 6, 1, 0),
373SOC_SINGLE_TLV("Speaker Volume", WM9081_ANALOGUE_SPEAKER_PGA, 0, 63, 0,
374 out_tlv),
375SOC_ENUM("DAC Deemphasis", dac_deemph),
376SOC_ENUM_EXT("Speaker Mode", speaker_mode, speaker_mode_get, speaker_mode_put),
377};
378
379static const struct snd_kcontrol_new wm9081_eq_controls[] = {
380SOC_SINGLE_TLV("EQ1 Volume", WM9081_EQ_1, 11, 24, 0, eq_tlv),
381SOC_SINGLE_TLV("EQ2 Volume", WM9081_EQ_1, 6, 24, 0, eq_tlv),
382SOC_SINGLE_TLV("EQ3 Volume", WM9081_EQ_1, 1, 24, 0, eq_tlv),
383SOC_SINGLE_TLV("EQ4 Volume", WM9081_EQ_2, 11, 24, 0, eq_tlv),
384SOC_SINGLE_TLV("EQ5 Volume", WM9081_EQ_2, 6, 24, 0, eq_tlv),
385};
386
387static const struct snd_kcontrol_new mixer[] = {
388SOC_DAPM_SINGLE("IN1 Switch", WM9081_ANALOGUE_MIXER, 0, 1, 0),
389SOC_DAPM_SINGLE("IN2 Switch", WM9081_ANALOGUE_MIXER, 2, 1, 0),
390SOC_DAPM_SINGLE("Playback Switch", WM9081_ANALOGUE_MIXER, 4, 1, 0),
391};
392
393static int speaker_event(struct snd_soc_dapm_widget *w,
394 struct snd_kcontrol *kcontrol, int event)
395{
396 struct snd_soc_codec *codec = w->codec;
8d50e447 397 unsigned int reg = snd_soc_read(codec, WM9081_POWER_MANAGEMENT);
86ed3669
MB		 398
399 switch (event) {
400 case SND_SOC_DAPM_POST_PMU:
401 reg |= WM9081_SPK_ENA;
402 break;
403
404 case SND_SOC_DAPM_PRE_PMD:
405 reg &= ~WM9081_SPK_ENA;
406 break;
407 }
408
8d50e447 409 snd_soc_write(codec, WM9081_POWER_MANAGEMENT, reg);
86ed3669
MB		 410
411 return 0;
412}
413
414struct _fll_div {
415 u16 fll_fratio;
416 u16 fll_outdiv;
417 u16 fll_clk_ref_div;
418 u16 n;
419 u16 k;
420};
421
422/* The size in bits of the FLL divide multiplied by 10
423 * to allow rounding later */
424#define FIXED_FLL_SIZE ((1 << 16) * 10)
425
426static struct {
427 unsigned int min;
428 unsigned int max;
429 u16 fll_fratio;
430 int ratio;
431} fll_fratios[] = {
432 { 0, 64000, 4, 16 },
433 { 64000, 128000, 3, 8 },
434 { 128000, 256000, 2, 4 },
435 { 256000, 1000000, 1, 2 },
436 { 1000000, 13500000, 0, 1 },
437};
438
439static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
440 unsigned int Fout)
441{
442 u64 Kpart;
443 unsigned int K, Ndiv, Nmod, target;
444 unsigned int div;
445 int i;
446
447 /* Fref must be <=13.5MHz */
448 div = 1;
449 while ((Fref / div) > 13500000) {
450 div *= 2;
451
452 if (div > 8) {
453 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
454 Fref);
455 return -EINVAL;
456 }
457 }
458 fll_div->fll_clk_ref_div = div / 2;
459
460 pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
461
462 /* Apply the division for our remaining calculations */
463 Fref /= div;
464
465 /* Fvco should be 90-100MHz; don't check the upper bound */
466 div = 0;
467 target = Fout * 2;
468 while (target < 90000000) {
469 div++;
470 target *= 2;
471 if (div > 7) {
472 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
473 Fout);
474 return -EINVAL;
475 }
476 }
477 fll_div->fll_outdiv = div;
478
479 pr_debug("Fvco=%dHz\n", target);
480
481 /* Find an appropraite FLL_FRATIO and factor it out of the target */
482 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
483 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
484 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
485 target /= fll_fratios[i].ratio;
486 break;
487 }
488 }
489 if (i == ARRAY_SIZE(fll_fratios)) {
490 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
491 return -EINVAL;
492 }
493
494 /* Now, calculate N.K */
495 Ndiv = target / Fref;
496
497 fll_div->n = Ndiv;
498 Nmod = target % Fref;
499 pr_debug("Nmod=%d\n", Nmod);
500
501 /* Calculate fractional part - scale up so we can round. */
502 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
503
504 do_div(Kpart, Fref);
505
506 K = Kpart & 0xFFFFFFFF;
507
508 if ((K % 10) >= 5)
509 K += 5;
510
511 /* Move down to proper range now rounding is done */
512 fll_div->k = K / 10;
513
514 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
515 fll_div->n, fll_div->k,
516 fll_div->fll_fratio, fll_div->fll_outdiv,
517 fll_div->fll_clk_ref_div);
518
519 return 0;
520}
521
522static int wm9081_set_fll(struct snd_soc_codec *codec, int fll_id,
523 unsigned int Fref, unsigned int Fout)
524{
b2c812e2 525 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
86ed3669
MB		 526 u16 reg1, reg4, reg5;
527 struct _fll_div fll_div;
528 int ret;
529 int clk_sys_reg;
530
531 /* Any change? */
532 if (Fref == wm9081->fll_fref && Fout == wm9081->fll_fout)
533 return 0;
534
535 /* Disable the FLL */
536 if (Fout == 0) {
537 dev_dbg(codec->dev, "FLL disabled\n");
538 wm9081->fll_fref = 0;
539 wm9081->fll_fout = 0;
540
541 return 0;
542 }
543
544 ret = fll_factors(&fll_div, Fref, Fout);
545 if (ret != 0)
546 return ret;
547
8d50e447 548 reg5 = snd_soc_read(codec, WM9081_FLL_CONTROL_5);
86ed3669
MB		 549 reg5 &= ~WM9081_FLL_CLK_SRC_MASK;
550
551 switch (fll_id) {
552 case WM9081_SYSCLK_FLL_MCLK:
553 reg5 |= 0x1;
554 break;
555
556 default:
557 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
558 return -EINVAL;
559 }
560
561 /* Disable CLK_SYS while we reconfigure */
8d50e447 562 clk_sys_reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_3);
86ed3669 563 if (clk_sys_reg & WM9081_CLK_SYS_ENA)
8d50e447 564 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3,
86ed3669
MB		 565 clk_sys_reg & ~WM9081_CLK_SYS_ENA);
566
567 /* Any FLL configuration change requires that the FLL be
568 * disabled first. */
8d50e447 569 reg1 = snd_soc_read(codec, WM9081_FLL_CONTROL_1);
86ed3669 570 reg1 &= ~WM9081_FLL_ENA;
8d50e447 571 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1);
86ed3669
MB		 572
573 /* Apply the configuration */
574 if (fll_div.k)
575 reg1 |= WM9081_FLL_FRAC_MASK;
576 else
577 reg1 &= ~WM9081_FLL_FRAC_MASK;
8d50e447 578 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1);
86ed3669 579
8d50e447 580 snd_soc_write(codec, WM9081_FLL_CONTROL_2,
86ed3669
MB		 581 (fll_div.fll_outdiv << WM9081_FLL_OUTDIV_SHIFT) |
582 (fll_div.fll_fratio << WM9081_FLL_FRATIO_SHIFT));
8d50e447 583 snd_soc_write(codec, WM9081_FLL_CONTROL_3, fll_div.k);
86ed3669 584
8d50e447 585 reg4 = snd_soc_read(codec, WM9081_FLL_CONTROL_4);
86ed3669
MB		 586 reg4 &= ~WM9081_FLL_N_MASK;
587 reg4 |= fll_div.n << WM9081_FLL_N_SHIFT;
8d50e447 588 snd_soc_write(codec, WM9081_FLL_CONTROL_4, reg4);
86ed3669
MB		 589
590 reg5 &= ~WM9081_FLL_CLK_REF_DIV_MASK;
591 reg5 |= fll_div.fll_clk_ref_div << WM9081_FLL_CLK_REF_DIV_SHIFT;
8d50e447 592 snd_soc_write(codec, WM9081_FLL_CONTROL_5, reg5);
86ed3669
MB		 593
594 /* Enable the FLL */
8d50e447 595 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1 | WM9081_FLL_ENA);
86ed3669
MB		 596
597 /* Then bring CLK_SYS up again if it was disabled */
598 if (clk_sys_reg & WM9081_CLK_SYS_ENA)
8d50e447 599 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, clk_sys_reg);
86ed3669
MB		 600
601 dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
602
603 wm9081->fll_fref = Fref;
604 wm9081->fll_fout = Fout;
605
606 return 0;
607}
608
609static int configure_clock(struct snd_soc_codec *codec)
610{
b2c812e2 611 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
86ed3669
MB		 612 int new_sysclk, i, target;
613 unsigned int reg;
614 int ret = 0;
615 int mclkdiv = 0;
616 int fll = 0;
617
618 switch (wm9081->sysclk_source) {
619 case WM9081_SYSCLK_MCLK:
620 if (wm9081->mclk_rate > 12225000) {
621 mclkdiv = 1;
622 wm9081->sysclk_rate = wm9081->mclk_rate / 2;
623 } else {
624 wm9081->sysclk_rate = wm9081->mclk_rate;
625 }
626 wm9081_set_fll(codec, WM9081_SYSCLK_FLL_MCLK, 0, 0);
627 break;
628
629 case WM9081_SYSCLK_FLL_MCLK:
630 /* If we have a sample rate calculate a CLK_SYS that
631 * gives us a suitable DAC configuration, plus BCLK.
632 * Ideally we would check to see if we can clock
633 * directly from MCLK and only use the FLL if this is
634 * not the case, though care must be taken with free
635 * running mode.
636 */
637 if (wm9081->master && wm9081->bclk) {
638 /* Make sure we can generate CLK_SYS and BCLK
639 * and that we've got 3MHz for optimal
640 * performance. */
641 for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
642 target = wm9081->fs * clk_sys_rates[i].ratio;
0154724d 643 new_sysclk = target;
86ed3669
MB		 644 if (target >= wm9081->bclk &&
645 target > 3000000)
0154724d 646 break;
86ed3669 647 }
4b75e947
MB		 648
649 if (i == ARRAY_SIZE(clk_sys_rates))
650 return -EINVAL;
651
86ed3669
MB		 652 } else if (wm9081->fs) {
653 for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
654 new_sysclk = clk_sys_rates[i].ratio
655 * wm9081->fs;
656 if (new_sysclk > 3000000)
657 break;
658 }
4b75e947
MB		 659
660 if (i == ARRAY_SIZE(clk_sys_rates))
661 return -EINVAL;
662
86ed3669
MB		 663 } else {
664 new_sysclk = 12288000;
665 }
666
667 ret = wm9081_set_fll(codec, WM9081_SYSCLK_FLL_MCLK,
668 wm9081->mclk_rate, new_sysclk);
669 if (ret == 0) {
670 wm9081->sysclk_rate = new_sysclk;
671
672 /* Switch SYSCLK over to FLL */
673 fll = 1;
674 } else {
675 wm9081->sysclk_rate = wm9081->mclk_rate;
676 }
677 break;
678
679 default:
680 return -EINVAL;
681 }
682
8d50e447 683 reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_1);
86ed3669
MB		 684 if (mclkdiv)
685 reg |= WM9081_MCLKDIV2;
686 else
687 reg &= ~WM9081_MCLKDIV2;
8d50e447 688 snd_soc_write(codec, WM9081_CLOCK_CONTROL_1, reg);
86ed3669 689
8d50e447 690 reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_3);
86ed3669
MB		 691 if (fll)
692 reg |= WM9081_CLK_SRC_SEL;
693 else
694 reg &= ~WM9081_CLK_SRC_SEL;
8d50e447 695 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, reg);
86ed3669
MB		 696
697 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm9081->sysclk_rate);
698
699 return ret;
700}
701
702static int clk_sys_event(struct snd_soc_dapm_widget *w,
703 struct snd_kcontrol *kcontrol, int event)
704{
705 struct snd_soc_codec *codec = w->codec;
b2c812e2 706 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
86ed3669
MB		 707
708 /* This should be done on init() for bypass paths */
709 switch (wm9081->sysclk_source) {
710 case WM9081_SYSCLK_MCLK:
711 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm9081->mclk_rate);
712 break;
713 case WM9081_SYSCLK_FLL_MCLK:
714 dev_dbg(codec->dev, "Using %dHz MCLK with FLL\n",
715 wm9081->mclk_rate);
716 break;
717 default:
718 dev_err(codec->dev, "System clock not configured\n");
719 return -EINVAL;
720 }
721
722 switch (event) {
723 case SND_SOC_DAPM_PRE_PMU:
724 configure_clock(codec);
725 break;
726
727 case SND_SOC_DAPM_POST_PMD:
728 /* Disable the FLL if it's running */
729 wm9081_set_fll(codec, 0, 0, 0);
730 break;
731 }
732
733 return 0;
734}
735
736static const struct snd_soc_dapm_widget wm9081_dapm_widgets[] = {
737SND_SOC_DAPM_INPUT("IN1"),
738SND_SOC_DAPM_INPUT("IN2"),
739
740SND_SOC_DAPM_DAC("DAC", "HiFi Playback", WM9081_POWER_MANAGEMENT, 0, 0),
741
742SND_SOC_DAPM_MIXER_NAMED_CTL("Mixer", SND_SOC_NOPM, 0, 0,
743 mixer, ARRAY_SIZE(mixer)),
744
745SND_SOC_DAPM_PGA("LINEOUT PGA", WM9081_POWER_MANAGEMENT, 4, 0, NULL, 0),
746
747SND_SOC_DAPM_PGA_E("Speaker PGA", WM9081_POWER_MANAGEMENT, 2, 0, NULL, 0,
748 speaker_event,
749 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
750
751SND_SOC_DAPM_OUTPUT("LINEOUT"),
752SND_SOC_DAPM_OUTPUT("SPKN"),
753SND_SOC_DAPM_OUTPUT("SPKP"),
754
755SND_SOC_DAPM_SUPPLY("CLK_SYS", WM9081_CLOCK_CONTROL_3, 0, 0, clk_sys_event,
756 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
757SND_SOC_DAPM_SUPPLY("CLK_DSP", WM9081_CLOCK_CONTROL_3, 1, 0, NULL, 0),
758SND_SOC_DAPM_SUPPLY("TOCLK", WM9081_CLOCK_CONTROL_3, 2, 0, NULL, 0),
759};
760
761
762static const struct snd_soc_dapm_route audio_paths[] = {
763 { "DAC", NULL, "CLK_SYS" },
764 { "DAC", NULL, "CLK_DSP" },
765
766 { "Mixer", "IN1 Switch", "IN1" },
767 { "Mixer", "IN2 Switch", "IN2" },
768 { "Mixer", "Playback Switch", "DAC" },
769
770 { "LINEOUT PGA", NULL, "Mixer" },
771 { "LINEOUT PGA", NULL, "TOCLK" },
772 { "LINEOUT PGA", NULL, "CLK_SYS" },
773
774 { "LINEOUT", NULL, "LINEOUT PGA" },
775
776 { "Speaker PGA", NULL, "Mixer" },
777 { "Speaker PGA", NULL, "TOCLK" },
778 { "Speaker PGA", NULL, "CLK_SYS" },
779
780 { "SPKN", NULL, "Speaker PGA" },
781 { "SPKP", NULL, "Speaker PGA" },
782};
783
784static int wm9081_set_bias_level(struct snd_soc_codec *codec,
785 enum snd_soc_bias_level level)
786{
787 u16 reg;
788
789 switch (level) {
790 case SND_SOC_BIAS_ON:
791 break;
792
793 case SND_SOC_BIAS_PREPARE:
794 /* VMID=2*40k */
8d50e447 795 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
86ed3669
MB		 796 reg &= ~WM9081_VMID_SEL_MASK;
797 reg |= 0x2;
8d50e447 798 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
86ed3669
MB		 799
800 /* Normal bias current */
8d50e447 801 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
86ed3669 802 reg &= ~WM9081_STBY_BIAS_ENA;
8d50e447 803 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
86ed3669
MB		 804 break;
805
806 case SND_SOC_BIAS_STANDBY:
807 /* Initial cold start */
808 if (codec->bias_level == SND_SOC_BIAS_OFF) {
809 /* Disable LINEOUT discharge */
8d50e447 810 reg = snd_soc_read(codec, WM9081_ANTI_POP_CONTROL);
86ed3669 811 reg &= ~WM9081_LINEOUT_DISCH;
8d50e447 812 snd_soc_write(codec, WM9081_ANTI_POP_CONTROL, reg);
86ed3669
MB		 813
814 /* Select startup bias source */
8d50e447 815 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
86ed3669 816 reg |= WM9081_BIAS_SRC | WM9081_BIAS_ENA;
8d50e447 817 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
86ed3669
MB		 818
819 /* VMID 2*4k; Soft VMID ramp enable */
8d50e447 820 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
86ed3669 821 reg |= WM9081_VMID_RAMP | 0x6;
8d50e447 822 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
86ed3669
MB		 823
824 mdelay(100);
825
826 /* Normal bias enable & soft start off */
827 reg |= WM9081_BIAS_ENA;
828 reg &= ~WM9081_VMID_RAMP;
8d50e447 829 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
86ed3669
MB		 830
831 /* Standard bias source */
8d50e447 832 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
86ed3669 833 reg &= ~WM9081_BIAS_SRC;
8d50e447 834 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
86ed3669
MB		 835 }
836
837 /* VMID 2*240k */
8d50e447 838 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
86ed3669
MB		 839 reg &= ~WM9081_VMID_SEL_MASK;
840 reg |= 0x40;
8d50e447 841 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
86ed3669
MB		 842
843 /* Standby bias current on */
8d50e447 844 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
86ed3669 845 reg |= WM9081_STBY_BIAS_ENA;
8d50e447 846 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
86ed3669
MB		 847 break;
848
849 case SND_SOC_BIAS_OFF:
850 /* Startup bias source */
8d50e447 851 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
86ed3669 852 reg |= WM9081_BIAS_SRC;
8d50e447 853 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
86ed3669
MB		 854
855 /* Disable VMID and biases with soft ramping */
8d50e447 856 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
86ed3669
MB		 857 reg &= ~(WM9081_VMID_SEL_MASK | WM9081_BIAS_ENA);
858 reg |= WM9081_VMID_RAMP;
8d50e447 859 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
86ed3669
MB		 860
861 /* Actively discharge LINEOUT */
8d50e447 862 reg = snd_soc_read(codec, WM9081_ANTI_POP_CONTROL);
86ed3669 863 reg |= WM9081_LINEOUT_DISCH;
8d50e447 864 snd_soc_write(codec, WM9081_ANTI_POP_CONTROL, reg);
86ed3669
MB		 865 break;
866 }
867
868 codec->bias_level = level;
869
870 return 0;
871}
872
873static int wm9081_set_dai_fmt(struct snd_soc_dai *dai,
874 unsigned int fmt)
875{
876 struct snd_soc_codec *codec = dai->codec;
b2c812e2 877 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
8d50e447 878 unsigned int aif2 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_2);
86ed3669
MB		 879
880 aif2 &= ~(WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV |
881 WM9081_BCLK_DIR | WM9081_LRCLK_DIR | WM9081_AIF_FMT_MASK);
882
883 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
884 case SND_SOC_DAIFMT_CBS_CFS:
885 wm9081->master = 0;
886 break;
887 case SND_SOC_DAIFMT_CBS_CFM:
888 aif2 |= WM9081_LRCLK_DIR;
889 wm9081->master = 1;
890 break;
891 case SND_SOC_DAIFMT_CBM_CFS:
892 aif2 |= WM9081_BCLK_DIR;
893 wm9081->master = 1;
894 break;
895 case SND_SOC_DAIFMT_CBM_CFM:
896 aif2 |= WM9081_LRCLK_DIR | WM9081_BCLK_DIR;
897 wm9081->master = 1;
898 break;
899 default:
900 return -EINVAL;
901 }
902
903 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
904 case SND_SOC_DAIFMT_DSP_B:
905 aif2 |= WM9081_AIF_LRCLK_INV;
906 case SND_SOC_DAIFMT_DSP_A:
907 aif2 |= 0x3;
908 break;
909 case SND_SOC_DAIFMT_I2S:
910 aif2 |= 0x2;
911 break;
912 case SND_SOC_DAIFMT_RIGHT_J:
913 break;
914 case SND_SOC_DAIFMT_LEFT_J:
915 aif2 |= 0x1;
916 break;
917 default:
918 return -EINVAL;
919 }
920
921 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
922 case SND_SOC_DAIFMT_DSP_A:
923 case SND_SOC_DAIFMT_DSP_B:
924 /* frame inversion not valid for DSP modes */
925 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
926 case SND_SOC_DAIFMT_NB_NF:
927 break;
928 case SND_SOC_DAIFMT_IB_NF:
929 aif2 |= WM9081_AIF_BCLK_INV;
930 break;
931 default:
932 return -EINVAL;
933 }
934 break;
935
936 case SND_SOC_DAIFMT_I2S:
937 case SND_SOC_DAIFMT_RIGHT_J:
938 case SND_SOC_DAIFMT_LEFT_J:
939 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
940 case SND_SOC_DAIFMT_NB_NF:
941 break;
942 case SND_SOC_DAIFMT_IB_IF:
943 aif2 |= WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV;
944 break;
945 case SND_SOC_DAIFMT_IB_NF:
946 aif2 |= WM9081_AIF_BCLK_INV;
947 break;
948 case SND_SOC_DAIFMT_NB_IF:
949 aif2 |= WM9081_AIF_LRCLK_INV;
950 break;
951 default:
952 return -EINVAL;
953 }
954 break;
955 default:
956 return -EINVAL;
957 }
958
8d50e447 959 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
86ed3669
MB		 960
961 return 0;
962}
963
964static int wm9081_hw_params(struct snd_pcm_substream *substream,
965 struct snd_pcm_hw_params *params,
966 struct snd_soc_dai *dai)
967{
968 struct snd_soc_codec *codec = dai->codec;
b2c812e2 969 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
86ed3669
MB		 970 int ret, i, best, best_val, cur_val;
971 unsigned int clk_ctrl2, aif1, aif2, aif3, aif4;
972
8d50e447 973 clk_ctrl2 = snd_soc_read(codec, WM9081_CLOCK_CONTROL_2);
86ed3669
MB		 974 clk_ctrl2 &= ~(WM9081_CLK_SYS_RATE_MASK | WM9081_SAMPLE_RATE_MASK);
975
8d50e447 976 aif1 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_1);
86ed3669 977
8d50e447 978 aif2 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_2);
86ed3669
MB		 979 aif2 &= ~WM9081_AIF_WL_MASK;
980
8d50e447 981 aif3 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_3);
86ed3669
MB		 982 aif3 &= ~WM9081_BCLK_DIV_MASK;
983
8d50e447 984 aif4 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_4);
86ed3669
MB		 985 aif4 &= ~WM9081_LRCLK_RATE_MASK;
986
86ed3669 987 wm9081->fs = params_rate(params);
86ed3669 988
e0026bea
MB		 989 if (wm9081->tdm_width) {
990 /* If TDM is set up then that fixes our BCLK. */
86ed3669
MB		 991 int slots = ((aif1 & WM9081_AIFDAC_TDM_MODE_MASK) >>
992 WM9081_AIFDAC_TDM_MODE_SHIFT) + 1;
e0026bea
MB		 993
994 wm9081->bclk = wm9081->fs * wm9081->tdm_width * slots;
995 } else {
996 /* Otherwise work out a BCLK from the sample size */
997 wm9081->bclk = 2 * wm9081->fs;
998
999 switch (params_format(params)) {
1000 case SNDRV_PCM_FORMAT_S16_LE:
1001 wm9081->bclk *= 16;
1002 break;
1003 case SNDRV_PCM_FORMAT_S20_3LE:
1004 wm9081->bclk *= 20;
1005 aif2 |= 0x4;
1006 break;
1007 case SNDRV_PCM_FORMAT_S24_LE:
1008 wm9081->bclk *= 24;
1009 aif2 |= 0x8;
1010 break;
1011 case SNDRV_PCM_FORMAT_S32_LE:
1012 wm9081->bclk *= 32;
1013 aif2 |= 0xc;
1014 break;
1015 default:
1016 return -EINVAL;
1017 }
86ed3669
MB		 1018 }
1019
1020 dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm9081->bclk);
1021
1022 ret = configure_clock(codec);
1023 if (ret != 0)
1024 return ret;
1025
1026 /* Select nearest CLK_SYS_RATE */
1027 best = 0;
1028 best_val = abs((wm9081->sysclk_rate / clk_sys_rates[0].ratio)
1029 - wm9081->fs);
1030 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1031 cur_val = abs((wm9081->sysclk_rate /
a419aef8 1032 clk_sys_rates[i].ratio) - wm9081->fs);
86ed3669
MB		 1033 if (cur_val < best_val) {
1034 best = i;
1035 best_val = cur_val;
1036 }
1037 }
1038 dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
1039 clk_sys_rates[best].ratio);
1040 clk_ctrl2 |= (clk_sys_rates[best].clk_sys_rate
1041 << WM9081_CLK_SYS_RATE_SHIFT);
1042
1043 /* SAMPLE_RATE */
1044 best = 0;
1045 best_val = abs(wm9081->fs - sample_rates[0].rate);
1046 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1047 /* Closest match */
1048 cur_val = abs(wm9081->fs - sample_rates[i].rate);
1049 if (cur_val < best_val) {
1050 best = i;
1051 best_val = cur_val;
1052 }
1053 }
1054 dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
1055 sample_rates[best].rate);
0154724d
MB		 1056 clk_ctrl2 |= (sample_rates[best].sample_rate
1057 << WM9081_SAMPLE_RATE_SHIFT);
86ed3669
MB		 1058
1059 /* BCLK_DIV */
1060 best = 0;
1061 best_val = INT_MAX;
1062 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1063 cur_val = ((wm9081->sysclk_rate * 10) / bclk_divs[i].div)
1064 - wm9081->bclk;
1065 if (cur_val < 0) /* Table is sorted */
1066 break;
1067 if (cur_val < best_val) {
1068 best = i;
1069 best_val = cur_val;
1070 }
1071 }
1072 wm9081->bclk = (wm9081->sysclk_rate * 10) / bclk_divs[best].div;
1073 dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1074 bclk_divs[best].div, wm9081->bclk);
1075 aif3 |= bclk_divs[best].bclk_div;
1076
1077 /* LRCLK is a simple fraction of BCLK */
1078 dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm9081->bclk / wm9081->fs);
1079 aif4 |= wm9081->bclk / wm9081->fs;
1080
1081 /* Apply a ReTune Mobile configuration if it's in use */
1082 if (wm9081->retune) {
1083 struct wm9081_retune_mobile_config *retune = wm9081->retune;
1084 struct wm9081_retune_mobile_setting *s;
1085 int eq1;
1086
1087 best = 0;
1088 best_val = abs(retune->configs[0].rate - wm9081->fs);
1089 for (i = 0; i < retune->num_configs; i++) {
1090 cur_val = abs(retune->configs[i].rate - wm9081->fs);
1091 if (cur_val < best_val) {
1092 best_val = cur_val;
1093 best = i;
1094 }
1095 }
1096 s = &retune->configs[best];
1097
1098 dev_dbg(codec->dev, "ReTune Mobile %s tuned for %dHz\n",
1099 s->name, s->rate);
1100
1101 /* If the EQ is enabled then disable it while we write out */
8d50e447 1102 eq1 = snd_soc_read(codec, WM9081_EQ_1) & WM9081_EQ_ENA;
86ed3669 1103 if (eq1 & WM9081_EQ_ENA)
8d50e447 1104 snd_soc_write(codec, WM9081_EQ_1, 0);
86ed3669
MB		 1105
1106 /* Write out the other values */
1107 for (i = 1; i < ARRAY_SIZE(s->config); i++)
8d50e447 1108 snd_soc_write(codec, WM9081_EQ_1 + i, s->config[i]);
86ed3669
MB		 1109
1110 eq1 |= (s->config[0] & ~WM9081_EQ_ENA);
8d50e447 1111 snd_soc_write(codec, WM9081_EQ_1, eq1);
86ed3669
MB		 1112 }
1113
8d50e447
MB		 1114 snd_soc_write(codec, WM9081_CLOCK_CONTROL_2, clk_ctrl2);
1115 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
1116 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_3, aif3);
1117 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_4, aif4);
86ed3669
MB		 1118
1119 return 0;
1120}
1121
1122static int wm9081_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1123{
1124 struct snd_soc_codec *codec = codec_dai->codec;
1125 unsigned int reg;
1126
8d50e447 1127 reg = snd_soc_read(codec, WM9081_DAC_DIGITAL_2);
86ed3669
MB		 1128
1129 if (mute)
1130 reg |= WM9081_DAC_MUTE;
1131 else
1132 reg &= ~WM9081_DAC_MUTE;
1133
8d50e447 1134 snd_soc_write(codec, WM9081_DAC_DIGITAL_2, reg);
86ed3669
MB		 1135
1136 return 0;
1137}
1138
1139static int wm9081_set_sysclk(struct snd_soc_dai *codec_dai,
1140 int clk_id, unsigned int freq, int dir)
1141{
1142 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1143 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
86ed3669
MB		 1144
1145 switch (clk_id) {
1146 case WM9081_SYSCLK_MCLK:
1147 case WM9081_SYSCLK_FLL_MCLK:
1148 wm9081->sysclk_source = clk_id;
1149 wm9081->mclk_rate = freq;
1150 break;
1151
1152 default:
1153 return -EINVAL;
1154 }
1155
1156 return 0;
1157}
1158
1159static int wm9081_set_tdm_slot(struct snd_soc_dai *dai,
a5479e38 1160 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
86ed3669
MB		 1161{
1162 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1163 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
8d50e447 1164 unsigned int aif1 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_1);
86ed3669
MB		 1165
1166 aif1 &= ~(WM9081_AIFDAC_TDM_SLOT_MASK | WM9081_AIFDAC_TDM_MODE_MASK);
1167
e0026bea 1168 if (slots < 0 || slots > 4)
86ed3669
MB		 1169 return -EINVAL;
1170
e0026bea
MB		 1171 wm9081->tdm_width = slot_width;
1172
1173 if (slots == 0)
1174 slots = 1;
1175
86ed3669
MB		 1176 aif1 |= (slots - 1) << WM9081_AIFDAC_TDM_MODE_SHIFT;
1177
a5479e38 1178 switch (rx_mask) {
86ed3669
MB		 1179 case 1:
1180 break;
1181 case 2:
1182 aif1 |= 0x10;
1183 break;
1184 case 4:
1185 aif1 |= 0x20;
1186 break;
1187 case 8:
1188 aif1 |= 0x30;
1189 break;
1190 default:
1191 return -EINVAL;
1192 }
1193
8d50e447 1194 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_1, aif1);
86ed3669
MB		 1195
1196 return 0;
1197}
1198
1199#define WM9081_RATES SNDRV_PCM_RATE_8000_96000
1200
1201#define WM9081_FORMATS \
1202 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1203 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1204
1205static struct snd_soc_dai_ops wm9081_dai_ops = {
1206 .hw_params = wm9081_hw_params,
1207 .set_sysclk = wm9081_set_sysclk,
1208 .set_fmt = wm9081_set_dai_fmt,
1209 .digital_mute = wm9081_digital_mute,
1210 .set_tdm_slot = wm9081_set_tdm_slot,
1211};
1212
1213/* We report two channels because the CODEC processes a stereo signal, even
1214 * though it is only capable of handling a mono output.
1215 */
f0fba2ad
LG		 1216static struct snd_soc_dai_driver wm9081_dai = {
1217 .name = "wm9081-hifi",
86ed3669
MB		 1218 .playback = {
1219 .stream_name = "HiFi Playback",
1220 .channels_min = 1,
1221 .channels_max = 2,
1222 .rates = WM9081_RATES,
1223 .formats = WM9081_FORMATS,
1224 },
1225 .ops = &wm9081_dai_ops,
1226};
86ed3669 1227
f0fba2ad 1228static int wm9081_probe(struct snd_soc_codec *codec)
86ed3669 1229{
f0fba2ad
LG		 1230 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
1231 int ret;
1232 u16 reg;
86ed3669 1233
f0fba2ad
LG		 1234 codec->control_data = wm9081->control_data;
1235 ret = snd_soc_codec_set_cache_io(codec, 8, 16, wm9081->control_type);
1236 if (ret != 0) {
1237 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1238 return ret;
86ed3669
MB		 1239 }
1240
f0fba2ad
LG		 1241 reg = snd_soc_read(codec, WM9081_SOFTWARE_RESET);
1242 if (reg != 0x9081) {
1243 dev_err(codec->dev, "Device is not a WM9081: ID=0x%x\n", reg);
1244 ret = -EINVAL;
1245 return ret;
1246 }
86ed3669 1247
f0fba2ad 1248 ret = wm9081_reset(codec);
86ed3669 1249 if (ret < 0) {
f0fba2ad
LG		 1250 dev_err(codec->dev, "Failed to issue reset\n");
1251 return ret;
86ed3669
MB		 1252 }
1253
f0fba2ad
LG		 1254 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1255
1256 /* Enable zero cross by default */
1257 reg = snd_soc_read(codec, WM9081_ANALOGUE_LINEOUT);
1258 snd_soc_write(codec, WM9081_ANALOGUE_LINEOUT, reg | WM9081_LINEOUTZC);
1259 reg = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_PGA);
1260 snd_soc_write(codec, WM9081_ANALOGUE_SPEAKER_PGA,
1261 reg | WM9081_SPKPGAZC);
1262
86ed3669
MB		 1263 snd_soc_add_controls(codec, wm9081_snd_controls,
1264 ARRAY_SIZE(wm9081_snd_controls));
1265 if (!wm9081->retune) {
1266 dev_dbg(codec->dev,
1267 "No ReTune Mobile data, using normal EQ\n");
1268 snd_soc_add_controls(codec, wm9081_eq_controls,
1269 ARRAY_SIZE(wm9081_eq_controls));
1270 }
1271
1272 snd_soc_dapm_new_controls(codec, wm9081_dapm_widgets,
1273 ARRAY_SIZE(wm9081_dapm_widgets));
1274 snd_soc_dapm_add_routes(codec, audio_paths, ARRAY_SIZE(audio_paths));
86ed3669 1275
86ed3669 1276 return ret;
86ed3669
MB		 1277}
1278
f0fba2ad 1279static int wm9081_remove(struct snd_soc_codec *codec)
86ed3669 1280{
f0fba2ad 1281 wm9081_set_bias_level(codec, SND_SOC_BIAS_OFF);
86ed3669
MB		 1282 return 0;
1283}
1284
1285#ifdef CONFIG_PM
f0fba2ad 1286static int wm9081_suspend(struct snd_soc_codec *codec, pm_message_t state)
86ed3669 1287{
86ed3669
MB		 1288 wm9081_set_bias_level(codec, SND_SOC_BIAS_OFF);
1289
1290 return 0;
1291}
1292
f0fba2ad 1293static int wm9081_resume(struct snd_soc_codec *codec)
86ed3669 1294{
86ed3669
MB		 1295 u16 *reg_cache = codec->reg_cache;
1296 int i;
1297
f0fba2ad 1298 for (i = 0; i < codec->driver->reg_cache_size; i++) {
86ed3669
MB		 1299 if (i == WM9081_SOFTWARE_RESET)
1300 continue;
1301
8d50e447 1302 snd_soc_write(codec, i, reg_cache[i]);
86ed3669
MB		 1303 }
1304
1305 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1306
1307 return 0;
1308}
1309#else
1310#define wm9081_suspend NULL
1311#define wm9081_resume NULL
1312#endif
1313
f0fba2ad 1314static struct snd_soc_codec_driver soc_codec_dev_wm9081 = {
86ed3669
MB		 1315 .probe = wm9081_probe,
1316 .remove = wm9081_remove,
1317 .suspend = wm9081_suspend,
1318 .resume = wm9081_resume,
f0fba2ad
LG		 1319 .set_bias_level = wm9081_set_bias_level,
1320 .reg_cache_size = sizeof(wm9081_reg_defaults),
1321 .reg_word_size = sizeof(u16),
1322 .reg_cache_default = wm9081_reg_defaults,
1323 .volatile_register = wm9081_volatile_register,
86ed3669 1324};
86ed3669 1325
f0fba2ad 1326#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
86ed3669
MB		 1327static __devinit int wm9081_i2c_probe(struct i2c_client *i2c,
1328 const struct i2c_device_id *id)
1329{
1330 struct wm9081_priv *wm9081;
f0fba2ad 1331 int ret;
86ed3669
MB		 1332
1333 wm9081 = kzalloc(sizeof(struct wm9081_priv), GFP_KERNEL);
1334 if (wm9081 == NULL)
1335 return -ENOMEM;
1336
86ed3669 1337 i2c_set_clientdata(i2c, wm9081);
f0fba2ad 1338 wm9081->control_data = i2c;
86ed3669 1339
f0fba2ad
LG		 1340 ret = snd_soc_register_codec(&i2c->dev,
1341 &soc_codec_dev_wm9081, &wm9081_dai, 1);
1342 if (ret < 0)
1343 kfree(wm9081);
1344 return ret;
86ed3669
MB		 1345}
1346
1347static __devexit int wm9081_i2c_remove(struct i2c_client *client)
1348{
f0fba2ad
LG		 1349 snd_soc_unregister_codec(&client->dev);
1350 kfree(i2c_get_clientdata(client));
86ed3669
MB		 1351 return 0;
1352}
1353
1354static const struct i2c_device_id wm9081_i2c_id[] = {
1355 { "wm9081", 0 },
1356 { }
1357};
1358MODULE_DEVICE_TABLE(i2c, wm9081_i2c_id);
1359
1360static struct i2c_driver wm9081_i2c_driver = {
1361 .driver = {
f0fba2ad 1362 .name = "wm9081-codec",
86ed3669
MB		 1363 .owner = THIS_MODULE,
1364 },
1365 .probe = wm9081_i2c_probe,
1366 .remove = __devexit_p(wm9081_i2c_remove),
1367 .id_table = wm9081_i2c_id,
1368};
f0fba2ad 1369#endif
86ed3669
MB		 1370
1371static int __init wm9081_modinit(void)
1372{
f0fba2ad
LG		 1373 int ret = 0;
1374#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
86ed3669
MB		 1375 ret = i2c_add_driver(&wm9081_i2c_driver);
1376 if (ret != 0) {
1377 printk(KERN_ERR "Failed to register WM9081 I2C driver: %d\n",
1378 ret);
1379 }
f0fba2ad 1380#endif
86ed3669
MB		 1381 return ret;
1382}
1383module_init(wm9081_modinit);
1384
1385static void __exit wm9081_exit(void)
1386{
f0fba2ad 1387#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
86ed3669 1388 i2c_del_driver(&wm9081_i2c_driver);
f0fba2ad 1389#endif
86ed3669
MB		 1390}
1391module_exit(wm9081_exit);
1392
1393
1394MODULE_DESCRIPTION("ASoC WM9081 driver");
1395MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1396MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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