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ASoC: wm5110: Provide basic hookup for voice control
[deliverable/linux.git] / sound / soc / codecs / wm_adsp.c
CommitLineData
2159ad93
MB		 1/*
2 * wm_adsp.c -- Wolfson ADSP support
3 *
4 * Copyright 2012 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/firmware.h>
cf17c83c 18#include <linux/list.h>
2159ad93
MB		 19#include <linux/pm.h>
20#include <linux/pm_runtime.h>
21#include <linux/regmap.h>
973838a0 22#include <linux/regulator/consumer.h>
2159ad93 23#include <linux/slab.h>
cdcd7f72 24#include <linux/vmalloc.h>
6ab2b7b4 25#include <linux/workqueue.h>
f9f55e31 26#include <linux/debugfs.h>
2159ad93
MB		 27#include <sound/core.h>
28#include <sound/pcm.h>
29#include <sound/pcm_params.h>
30#include <sound/soc.h>
31#include <sound/jack.h>
32#include <sound/initval.h>
33#include <sound/tlv.h>
34
35#include <linux/mfd/arizona/registers.h>
36
dc91428a 37#include "arizona.h"
2159ad93
MB		 38#include "wm_adsp.h"
39
40#define adsp_crit(_dsp, fmt, ...) \
41 dev_crit(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
42#define adsp_err(_dsp, fmt, ...) \
43 dev_err(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
44#define adsp_warn(_dsp, fmt, ...) \
45 dev_warn(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
46#define adsp_info(_dsp, fmt, ...) \
47 dev_info(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
48#define adsp_dbg(_dsp, fmt, ...) \
49 dev_dbg(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
50
51#define ADSP1_CONTROL_1 0x00
52#define ADSP1_CONTROL_2 0x02
53#define ADSP1_CONTROL_3 0x03
54#define ADSP1_CONTROL_4 0x04
55#define ADSP1_CONTROL_5 0x06
56#define ADSP1_CONTROL_6 0x07
57#define ADSP1_CONTROL_7 0x08
58#define ADSP1_CONTROL_8 0x09
59#define ADSP1_CONTROL_9 0x0A
60#define ADSP1_CONTROL_10 0x0B
61#define ADSP1_CONTROL_11 0x0C
62#define ADSP1_CONTROL_12 0x0D
63#define ADSP1_CONTROL_13 0x0F
64#define ADSP1_CONTROL_14 0x10
65#define ADSP1_CONTROL_15 0x11
66#define ADSP1_CONTROL_16 0x12
67#define ADSP1_CONTROL_17 0x13
68#define ADSP1_CONTROL_18 0x14
69#define ADSP1_CONTROL_19 0x16
70#define ADSP1_CONTROL_20 0x17
71#define ADSP1_CONTROL_21 0x18
72#define ADSP1_CONTROL_22 0x1A
73#define ADSP1_CONTROL_23 0x1B
74#define ADSP1_CONTROL_24 0x1C
75#define ADSP1_CONTROL_25 0x1E
76#define ADSP1_CONTROL_26 0x20
77#define ADSP1_CONTROL_27 0x21
78#define ADSP1_CONTROL_28 0x22
79#define ADSP1_CONTROL_29 0x23
80#define ADSP1_CONTROL_30 0x24
81#define ADSP1_CONTROL_31 0x26
82
83/*
84 * ADSP1 Control 19
85 */
86#define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
87#define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
88#define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
89
90
91/*
92 * ADSP1 Control 30
93 */
94#define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
95#define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
96#define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
97#define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
98#define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
99#define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
100#define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
101#define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
102#define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
103#define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
104#define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
105#define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
106#define ADSP1_START 0x0001 /* DSP1_START */
107#define ADSP1_START_MASK 0x0001 /* DSP1_START */
108#define ADSP1_START_SHIFT 0 /* DSP1_START */
109#define ADSP1_START_WIDTH 1 /* DSP1_START */
110
94e205bf
CR		 111/*
112 * ADSP1 Control 31
113 */
114#define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
115#define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
116#define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
117
2d30b575
MB		 118#define ADSP2_CONTROL 0x0
119#define ADSP2_CLOCKING 0x1
120#define ADSP2_STATUS1 0x4
121#define ADSP2_WDMA_CONFIG_1 0x30
122#define ADSP2_WDMA_CONFIG_2 0x31
123#define ADSP2_RDMA_CONFIG_1 0x34
2159ad93 124
10337b07
RF		 125#define ADSP2_SCRATCH0 0x40
126#define ADSP2_SCRATCH1 0x41
127#define ADSP2_SCRATCH2 0x42
128#define ADSP2_SCRATCH3 0x43
129
2159ad93
MB		 130/*
131 * ADSP2 Control
132 */
133
134#define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */
135#define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */
136#define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */
137#define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */
138#define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
139#define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
140#define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
141#define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
142#define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
143#define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
144#define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
145#define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
146#define ADSP2_START 0x0001 /* DSP1_START */
147#define ADSP2_START_MASK 0x0001 /* DSP1_START */
148#define ADSP2_START_SHIFT 0 /* DSP1_START */
149#define ADSP2_START_WIDTH 1 /* DSP1_START */
150
973838a0
MB		 151/*
152 * ADSP2 clocking
153 */
154#define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
155#define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
156#define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
157
2159ad93
MB		 158/*
159 * ADSP2 Status 1
160 */
161#define ADSP2_RAM_RDY 0x0001
162#define ADSP2_RAM_RDY_MASK 0x0001
163#define ADSP2_RAM_RDY_SHIFT 0
164#define ADSP2_RAM_RDY_WIDTH 1
165
cf17c83c
MB		 166struct wm_adsp_buf {
167 struct list_head list;
168 void *buf;
169};
170
171static struct wm_adsp_buf *wm_adsp_buf_alloc(const void *src, size_t len,
172 struct list_head *list)
173{
174 struct wm_adsp_buf *buf = kzalloc(sizeof(*buf), GFP_KERNEL);
175
176 if (buf == NULL)
177 return NULL;
178
cdcd7f72 179 buf->buf = vmalloc(len);
cf17c83c 180 if (!buf->buf) {
cdcd7f72 181 vfree(buf);
cf17c83c
MB		 182 return NULL;
183 }
cdcd7f72 184 memcpy(buf->buf, src, len);
cf17c83c
MB		 185
186 if (list)
187 list_add_tail(&buf->list, list);
188
189 return buf;
190}
191
192static void wm_adsp_buf_free(struct list_head *list)
193{
194 while (!list_empty(list)) {
195 struct wm_adsp_buf *buf = list_first_entry(list,
196 struct wm_adsp_buf,
197 list);
198 list_del(&buf->list);
cdcd7f72 199 vfree(buf->buf);
cf17c83c
MB		 200 kfree(buf);
201 }
202}
203
04d1300f
CK		 204#define WM_ADSP_FW_MBC_VSS 0
205#define WM_ADSP_FW_HIFI 1
206#define WM_ADSP_FW_TX 2
207#define WM_ADSP_FW_TX_SPK 3
208#define WM_ADSP_FW_RX 4
209#define WM_ADSP_FW_RX_ANC 5
210#define WM_ADSP_FW_CTRL 6
211#define WM_ADSP_FW_ASR 7
212#define WM_ADSP_FW_TRACE 8
213#define WM_ADSP_FW_SPK_PROT 9
214#define WM_ADSP_FW_MISC 10
215
216#define WM_ADSP_NUM_FW 11
dd84f925 217
1023dbd9 218static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = {
04d1300f
CK		 219 [WM_ADSP_FW_MBC_VSS] = "MBC/VSS",
220 [WM_ADSP_FW_HIFI] = "MasterHiFi",
221 [WM_ADSP_FW_TX] = "Tx",
222 [WM_ADSP_FW_TX_SPK] = "Tx Speaker",
223 [WM_ADSP_FW_RX] = "Rx",
224 [WM_ADSP_FW_RX_ANC] = "Rx ANC",
225 [WM_ADSP_FW_CTRL] = "Voice Ctrl",
226 [WM_ADSP_FW_ASR] = "ASR Assist",
227 [WM_ADSP_FW_TRACE] = "Dbg Trace",
228 [WM_ADSP_FW_SPK_PROT] = "Protection",
229 [WM_ADSP_FW_MISC] = "Misc",
1023dbd9
MB		 230};
231
232static struct {
233 const char *file;
234} wm_adsp_fw[WM_ADSP_NUM_FW] = {
04d1300f
CK		 235 [WM_ADSP_FW_MBC_VSS] = { .file = "mbc-vss" },
236 [WM_ADSP_FW_HIFI] = { .file = "hifi" },
237 [WM_ADSP_FW_TX] = { .file = "tx" },
238 [WM_ADSP_FW_TX_SPK] = { .file = "tx-spk" },
239 [WM_ADSP_FW_RX] = { .file = "rx" },
240 [WM_ADSP_FW_RX_ANC] = { .file = "rx-anc" },
241 [WM_ADSP_FW_CTRL] = { .file = "ctrl" },
242 [WM_ADSP_FW_ASR] = { .file = "asr" },
243 [WM_ADSP_FW_TRACE] = { .file = "trace" },
244 [WM_ADSP_FW_SPK_PROT] = { .file = "spk-prot" },
245 [WM_ADSP_FW_MISC] = { .file = "misc" },
1023dbd9
MB		 246};
247
6ab2b7b4
DP		 248struct wm_coeff_ctl_ops {
249 int (*xget)(struct snd_kcontrol *kcontrol,
250 struct snd_ctl_elem_value *ucontrol);
251 int (*xput)(struct snd_kcontrol *kcontrol,
252 struct snd_ctl_elem_value *ucontrol);
253 int (*xinfo)(struct snd_kcontrol *kcontrol,
254 struct snd_ctl_elem_info *uinfo);
255};
256
6ab2b7b4
DP		 257struct wm_coeff_ctl {
258 const char *name;
2323736d 259 const char *fw_name;
3809f001 260 struct wm_adsp_alg_region alg_region;
6ab2b7b4 261 struct wm_coeff_ctl_ops ops;
3809f001 262 struct wm_adsp *dsp;
6ab2b7b4
DP		 263 unsigned int enabled:1;
264 struct list_head list;
265 void *cache;
2323736d 266 unsigned int offset;
6ab2b7b4 267 size_t len;
0c2e3f34 268 unsigned int set:1;
6ab2b7b4 269 struct snd_kcontrol *kcontrol;
26c22a19 270 unsigned int flags;
6ab2b7b4
DP		 271};
272
f9f55e31
RF		 273#ifdef CONFIG_DEBUG_FS
274static void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp, const char *s)
275{
276 char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
277
f9f55e31
RF		 278 kfree(dsp->wmfw_file_name);
279 dsp->wmfw_file_name = tmp;
f9f55e31
RF		 280}
281
282static void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp, const char *s)
283{
284 char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
285
f9f55e31
RF		 286 kfree(dsp->bin_file_name);
287 dsp->bin_file_name = tmp;
f9f55e31
RF		 288}
289
290static void wm_adsp_debugfs_clear(struct wm_adsp *dsp)
291{
f9f55e31
RF		 292 kfree(dsp->wmfw_file_name);
293 kfree(dsp->bin_file_name);
294 dsp->wmfw_file_name = NULL;
295 dsp->bin_file_name = NULL;
f9f55e31
RF		 296}
297
298static ssize_t wm_adsp_debugfs_wmfw_read(struct file *file,
299 char __user *user_buf,
300 size_t count, loff_t *ppos)
301{
302 struct wm_adsp *dsp = file->private_data;
303 ssize_t ret;
304
078e7183 305 mutex_lock(&dsp->pwr_lock);
f9f55e31
RF		 306
307 if (!dsp->wmfw_file_name || !dsp->running)
308 ret = 0;
309 else
310 ret = simple_read_from_buffer(user_buf, count, ppos,
311 dsp->wmfw_file_name,
312 strlen(dsp->wmfw_file_name));
313
078e7183 314 mutex_unlock(&dsp->pwr_lock);
f9f55e31
RF		 315 return ret;
316}
317
318static ssize_t wm_adsp_debugfs_bin_read(struct file *file,
319 char __user *user_buf,
320 size_t count, loff_t *ppos)
321{
322 struct wm_adsp *dsp = file->private_data;
323 ssize_t ret;
324
078e7183 325 mutex_lock(&dsp->pwr_lock);
f9f55e31
RF		 326
327 if (!dsp->bin_file_name || !dsp->running)
328 ret = 0;
329 else
330 ret = simple_read_from_buffer(user_buf, count, ppos,
331 dsp->bin_file_name,
332 strlen(dsp->bin_file_name));
333
078e7183 334 mutex_unlock(&dsp->pwr_lock);
f9f55e31
RF		 335 return ret;
336}
337
338static const struct {
339 const char *name;
340 const struct file_operations fops;
341} wm_adsp_debugfs_fops[] = {
342 {
343 .name = "wmfw_file_name",
344 .fops = {
345 .open = simple_open,
346 .read = wm_adsp_debugfs_wmfw_read,
347 },
348 },
349 {
350 .name = "bin_file_name",
351 .fops = {
352 .open = simple_open,
353 .read = wm_adsp_debugfs_bin_read,
354 },
355 },
356};
357
358static void wm_adsp2_init_debugfs(struct wm_adsp *dsp,
359 struct snd_soc_codec *codec)
360{
361 struct dentry *root = NULL;
362 char *root_name;
363 int i;
364
365 if (!codec->component.debugfs_root) {
366 adsp_err(dsp, "No codec debugfs root\n");
367 goto err;
368 }
369
370 root_name = kmalloc(PAGE_SIZE, GFP_KERNEL);
371 if (!root_name)
372 goto err;
373
374 snprintf(root_name, PAGE_SIZE, "dsp%d", dsp->num);
375 root = debugfs_create_dir(root_name, codec->component.debugfs_root);
376 kfree(root_name);
377
378 if (!root)
379 goto err;
380
381 if (!debugfs_create_bool("running", S_IRUGO, root, &dsp->running))
382 goto err;
383
384 if (!debugfs_create_x32("fw_id", S_IRUGO, root, &dsp->fw_id))
385 goto err;
386
387 if (!debugfs_create_x32("fw_version", S_IRUGO, root,
388 &dsp->fw_id_version))
389 goto err;
390
391 for (i = 0; i < ARRAY_SIZE(wm_adsp_debugfs_fops); ++i) {
392 if (!debugfs_create_file(wm_adsp_debugfs_fops[i].name,
393 S_IRUGO, root, dsp,
394 &wm_adsp_debugfs_fops[i].fops))
395 goto err;
396 }
397
398 dsp->debugfs_root = root;
399 return;
400
401err:
402 debugfs_remove_recursive(root);
403 adsp_err(dsp, "Failed to create debugfs\n");
404}
405
406static void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp)
407{
408 wm_adsp_debugfs_clear(dsp);
409 debugfs_remove_recursive(dsp->debugfs_root);
410}
411#else
412static inline void wm_adsp2_init_debugfs(struct wm_adsp *dsp,
413 struct snd_soc_codec *codec)
414{
415}
416
417static inline void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp)
418{
419}
420
421static inline void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp,
422 const char *s)
423{
424}
425
426static inline void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp,
427 const char *s)
428{
429}
430
431static inline void wm_adsp_debugfs_clear(struct wm_adsp *dsp)
432{
433}
434#endif
435
1023dbd9
MB		 436static int wm_adsp_fw_get(struct snd_kcontrol *kcontrol,
437 struct snd_ctl_elem_value *ucontrol)
438{
ea53bf77 439 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1023dbd9 440 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
3809f001 441 struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec);
1023dbd9 442
3809f001 443 ucontrol->value.integer.value[0] = dsp[e->shift_l].fw;
1023dbd9
MB		 444
445 return 0;
446}
447
448static int wm_adsp_fw_put(struct snd_kcontrol *kcontrol,
449 struct snd_ctl_elem_value *ucontrol)
450{
ea53bf77 451 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1023dbd9 452 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
3809f001 453 struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec);
d27c5e15 454 int ret = 0;
1023dbd9 455
3809f001 456 if (ucontrol->value.integer.value[0] == dsp[e->shift_l].fw)
1023dbd9
MB		 457 return 0;
458
459 if (ucontrol->value.integer.value[0] >= WM_ADSP_NUM_FW)
460 return -EINVAL;
461
d27c5e15
CK		 462 mutex_lock(&dsp[e->shift_l].pwr_lock);
463
3809f001 464 if (dsp[e->shift_l].running)
d27c5e15
CK		 465 ret = -EBUSY;
466 else
467 dsp[e->shift_l].fw = ucontrol->value.integer.value[0];
1023dbd9 468
d27c5e15 469 mutex_unlock(&dsp[e->shift_l].pwr_lock);
1023dbd9 470
d27c5e15 471 return ret;
1023dbd9
MB		 472}
473
474static const struct soc_enum wm_adsp_fw_enum[] = {
475 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
476 SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
477 SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
478 SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
479};
480
336d0442 481const struct snd_kcontrol_new wm_adsp_fw_controls[] = {
1023dbd9
MB		 482 SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum[0],
483 wm_adsp_fw_get, wm_adsp_fw_put),
484 SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum[1],
485 wm_adsp_fw_get, wm_adsp_fw_put),
486 SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum[2],
487 wm_adsp_fw_get, wm_adsp_fw_put),
336d0442
RF		 488 SOC_ENUM_EXT("DSP4 Firmware", wm_adsp_fw_enum[3],
489 wm_adsp_fw_get, wm_adsp_fw_put),
b6ed61cf 490};
336d0442 491EXPORT_SYMBOL_GPL(wm_adsp_fw_controls);
2159ad93
MB		 492
493static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp,
494 int type)
495{
496 int i;
497
498 for (i = 0; i < dsp->num_mems; i++)
499 if (dsp->mem[i].type == type)
500 return &dsp->mem[i];
501
502 return NULL;
503}
504
3809f001 505static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *mem,
45b9ee72
MB		 506 unsigned int offset)
507{
3809f001 508 if (WARN_ON(!mem))
6c452bda 509 return offset;
3809f001 510 switch (mem->type) {
45b9ee72 511 case WMFW_ADSP1_PM:
3809f001 512 return mem->base + (offset * 3);
45b9ee72 513 case WMFW_ADSP1_DM:
3809f001 514 return mem->base + (offset * 2);
45b9ee72 515 case WMFW_ADSP2_XM:
3809f001 516 return mem->base + (offset * 2);
45b9ee72 517 case WMFW_ADSP2_YM:
3809f001 518 return mem->base + (offset * 2);
45b9ee72 519 case WMFW_ADSP1_ZM:
3809f001 520 return mem->base + (offset * 2);
45b9ee72 521 default:
6c452bda 522 WARN(1, "Unknown memory region type");
45b9ee72
MB		 523 return offset;
524 }
525}
526
10337b07
RF		 527static void wm_adsp2_show_fw_status(struct wm_adsp *dsp)
528{
529 u16 scratch[4];
530 int ret;
531
532 ret = regmap_raw_read(dsp->regmap, dsp->base + ADSP2_SCRATCH0,
533 scratch, sizeof(scratch));
534 if (ret) {
535 adsp_err(dsp, "Failed to read SCRATCH regs: %d\n", ret);
536 return;
537 }
538
539 adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
540 be16_to_cpu(scratch[0]),
541 be16_to_cpu(scratch[1]),
542 be16_to_cpu(scratch[2]),
543 be16_to_cpu(scratch[3]));
544}
545
7585a5b0 546static int wm_coeff_info(struct snd_kcontrol *kctl,
6ab2b7b4
DP		 547 struct snd_ctl_elem_info *uinfo)
548{
7585a5b0 549 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kctl->private_value;
6ab2b7b4
DP		 550
551 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
552 uinfo->count = ctl->len;
553 return 0;
554}
555
c9f8dd71 556static int wm_coeff_write_control(struct wm_coeff_ctl *ctl,
6ab2b7b4
DP		 557 const void *buf, size_t len)
558{
3809f001 559 struct wm_adsp_alg_region *alg_region = &ctl->alg_region;
6ab2b7b4 560 const struct wm_adsp_region *mem;
3809f001 561 struct wm_adsp *dsp = ctl->dsp;
6ab2b7b4
DP		 562 void *scratch;
563 int ret;
564 unsigned int reg;
565
3809f001 566 mem = wm_adsp_find_region(dsp, alg_region->type);
6ab2b7b4 567 if (!mem) {
3809f001
CK		 568 adsp_err(dsp, "No base for region %x\n",
569 alg_region->type);
6ab2b7b4
DP		 570 return -EINVAL;
571 }
572
2323736d 573 reg = ctl->alg_region.base + ctl->offset;
6ab2b7b4
DP		 574 reg = wm_adsp_region_to_reg(mem, reg);
575
576 scratch = kmemdup(buf, ctl->len, GFP_KERNEL | GFP_DMA);
577 if (!scratch)
578 return -ENOMEM;
579
3809f001 580 ret = regmap_raw_write(dsp->regmap, reg, scratch,
6ab2b7b4
DP		 581 ctl->len);
582 if (ret) {
3809f001 583 adsp_err(dsp, "Failed to write %zu bytes to %x: %d\n",
43bc3bf6 584 ctl->len, reg, ret);
6ab2b7b4
DP		 585 kfree(scratch);
586 return ret;
587 }
3809f001 588 adsp_dbg(dsp, "Wrote %zu bytes to %x\n", ctl->len, reg);
6ab2b7b4
DP		 589
590 kfree(scratch);
591
592 return 0;
593}
594
7585a5b0 595static int wm_coeff_put(struct snd_kcontrol *kctl,
6ab2b7b4
DP		 596 struct snd_ctl_elem_value *ucontrol)
597{
7585a5b0 598 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kctl->private_value;
6ab2b7b4 599 char *p = ucontrol->value.bytes.data;
168d10e7
CK		 600 int ret = 0;
601
602 mutex_lock(&ctl->dsp->pwr_lock);
6ab2b7b4
DP		 603
604 memcpy(ctl->cache, p, ctl->len);
605
65d17a9c 606 ctl->set = 1;
168d10e7
CK		 607 if (ctl->enabled)
608 ret = wm_coeff_write_control(ctl, p, ctl->len);
6ab2b7b4 609
168d10e7
CK		 610 mutex_unlock(&ctl->dsp->pwr_lock);
611
612 return ret;
6ab2b7b4
DP		 613}
614
c9f8dd71 615static int wm_coeff_read_control(struct wm_coeff_ctl *ctl,
6ab2b7b4
DP		 616 void *buf, size_t len)
617{
3809f001 618 struct wm_adsp_alg_region *alg_region = &ctl->alg_region;
6ab2b7b4 619 const struct wm_adsp_region *mem;
3809f001 620 struct wm_adsp *dsp = ctl->dsp;
6ab2b7b4
DP		 621 void *scratch;
622 int ret;
623 unsigned int reg;
624
3809f001 625 mem = wm_adsp_find_region(dsp, alg_region->type);
6ab2b7b4 626 if (!mem) {
3809f001
CK		 627 adsp_err(dsp, "No base for region %x\n",
628 alg_region->type);
6ab2b7b4
DP		 629 return -EINVAL;
630 }
631
2323736d 632 reg = ctl->alg_region.base + ctl->offset;
6ab2b7b4
DP		 633 reg = wm_adsp_region_to_reg(mem, reg);
634
635 scratch = kmalloc(ctl->len, GFP_KERNEL | GFP_DMA);
636 if (!scratch)
637 return -ENOMEM;
638
3809f001 639 ret = regmap_raw_read(dsp->regmap, reg, scratch, ctl->len);
6ab2b7b4 640 if (ret) {
3809f001 641 adsp_err(dsp, "Failed to read %zu bytes from %x: %d\n",
43bc3bf6 642 ctl->len, reg, ret);
6ab2b7b4
DP		 643 kfree(scratch);
644 return ret;
645 }
3809f001 646 adsp_dbg(dsp, "Read %zu bytes from %x\n", ctl->len, reg);
6ab2b7b4
DP		 647
648 memcpy(buf, scratch, ctl->len);
649 kfree(scratch);
650
651 return 0;
652}
653
7585a5b0 654static int wm_coeff_get(struct snd_kcontrol *kctl,
6ab2b7b4
DP		 655 struct snd_ctl_elem_value *ucontrol)
656{
7585a5b0 657 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kctl->private_value;
6ab2b7b4 658 char *p = ucontrol->value.bytes.data;
168d10e7
CK		 659 int ret = 0;
660
661 mutex_lock(&ctl->dsp->pwr_lock);
6ab2b7b4 662
26c22a19
CK		 663 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) {
664 if (ctl->enabled)
168d10e7 665 ret = wm_coeff_read_control(ctl, p, ctl->len);
26c22a19 666 else
168d10e7
CK		 667 ret = -EPERM;
668 } else {
bc1765d6
CK		 669 if (!ctl->flags && ctl->enabled)
670 ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len);
671
168d10e7 672 memcpy(p, ctl->cache, ctl->len);
26c22a19
CK		 673 }
674
168d10e7 675 mutex_unlock(&ctl->dsp->pwr_lock);
26c22a19 676
168d10e7 677 return ret;
6ab2b7b4
DP		 678}
679
6ab2b7b4 680struct wmfw_ctl_work {
3809f001 681 struct wm_adsp *dsp;
6ab2b7b4
DP		 682 struct wm_coeff_ctl *ctl;
683 struct work_struct work;
684};
685
3809f001 686static int wmfw_add_ctl(struct wm_adsp *dsp, struct wm_coeff_ctl *ctl)
6ab2b7b4
DP		 687{
688 struct snd_kcontrol_new *kcontrol;
689 int ret;
690
92bb4c32 691 if (!ctl || !ctl->name)
6ab2b7b4
DP		 692 return -EINVAL;
693
694 kcontrol = kzalloc(sizeof(*kcontrol), GFP_KERNEL);
695 if (!kcontrol)
696 return -ENOMEM;
697 kcontrol->iface = SNDRV_CTL_ELEM_IFACE_MIXER;
698
699 kcontrol->name = ctl->name;
700 kcontrol->info = wm_coeff_info;
701 kcontrol->get = wm_coeff_get;
702 kcontrol->put = wm_coeff_put;
703 kcontrol->private_value = (unsigned long)ctl;
704
26c22a19
CK		 705 if (ctl->flags) {
706 if (ctl->flags & WMFW_CTL_FLAG_WRITEABLE)
707 kcontrol->access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
708 if (ctl->flags & WMFW_CTL_FLAG_READABLE)
709 kcontrol->access |= SNDRV_CTL_ELEM_ACCESS_READ;
710 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
711 kcontrol->access |= SNDRV_CTL_ELEM_ACCESS_VOLATILE;
712 }
713
3809f001 714 ret = snd_soc_add_card_controls(dsp->card,
81ad93ec 715 kcontrol, 1);
6ab2b7b4
DP		 716 if (ret < 0)
717 goto err_kcontrol;
718
719 kfree(kcontrol);
720
3809f001 721 ctl->kcontrol = snd_soc_card_get_kcontrol(dsp->card,
81ad93ec
DP		 722 ctl->name);
723
6ab2b7b4
DP		 724 return 0;
725
726err_kcontrol:
727 kfree(kcontrol);
728 return ret;
729}
730
b21acc1c
CK		 731static int wm_coeff_init_control_caches(struct wm_adsp *dsp)
732{
733 struct wm_coeff_ctl *ctl;
734 int ret;
735
736 list_for_each_entry(ctl, &dsp->ctl_list, list) {
737 if (!ctl->enabled || ctl->set)
738 continue;
26c22a19
CK		 739 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
740 continue;
741
b21acc1c
CK		 742 ret = wm_coeff_read_control(ctl,
743 ctl->cache,
744 ctl->len);
745 if (ret < 0)
746 return ret;
747 }
748
749 return 0;
750}
751
752static int wm_coeff_sync_controls(struct wm_adsp *dsp)
753{
754 struct wm_coeff_ctl *ctl;
755 int ret;
756
757 list_for_each_entry(ctl, &dsp->ctl_list, list) {
758 if (!ctl->enabled)
759 continue;
26c22a19 760 if (ctl->set && !(ctl->flags & WMFW_CTL_FLAG_VOLATILE)) {
b21acc1c
CK		 761 ret = wm_coeff_write_control(ctl,
762 ctl->cache,
763 ctl->len);
764 if (ret < 0)
765 return ret;
766 }
767 }
768
769 return 0;
770}
771
772static void wm_adsp_ctl_work(struct work_struct *work)
773{
774 struct wmfw_ctl_work *ctl_work = container_of(work,
775 struct wmfw_ctl_work,
776 work);
777
778 wmfw_add_ctl(ctl_work->dsp, ctl_work->ctl);
779 kfree(ctl_work);
780}
781
782static int wm_adsp_create_control(struct wm_adsp *dsp,
783 const struct wm_adsp_alg_region *alg_region,
2323736d 784 unsigned int offset, unsigned int len,
26c22a19
CK		 785 const char *subname, unsigned int subname_len,
786 unsigned int flags)
b21acc1c
CK		 787{
788 struct wm_coeff_ctl *ctl;
789 struct wmfw_ctl_work *ctl_work;
790 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
791 char *region_name;
792 int ret;
793
26c22a19
CK		 794 if (flags & WMFW_CTL_FLAG_SYS)
795 return 0;
796
b21acc1c
CK		 797 switch (alg_region->type) {
798 case WMFW_ADSP1_PM:
799 region_name = "PM";
800 break;
801 case WMFW_ADSP1_DM:
802 region_name = "DM";
803 break;
804 case WMFW_ADSP2_XM:
805 region_name = "XM";
806 break;
807 case WMFW_ADSP2_YM:
808 region_name = "YM";
809 break;
810 case WMFW_ADSP1_ZM:
811 region_name = "ZM";
812 break;
813 default:
2323736d 814 adsp_err(dsp, "Unknown region type: %d\n", alg_region->type);
b21acc1c
CK		 815 return -EINVAL;
816 }
817
cb5b57a9
CK		 818 switch (dsp->fw_ver) {
819 case 0:
820 case 1:
821 snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "DSP%d %s %x",
822 dsp->num, region_name, alg_region->alg);
823 break;
824 default:
825 ret = snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN,
826 "DSP%d%c %.12s %x", dsp->num, *region_name,
827 wm_adsp_fw_text[dsp->fw], alg_region->alg);
828
829 /* Truncate the subname from the start if it is too long */
830 if (subname) {
831 int avail = SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret - 2;
832 int skip = 0;
833
834 if (subname_len > avail)
835 skip = subname_len - avail;
836
837 snprintf(name + ret,
838 SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret, " %.*s",
839 subname_len - skip, subname + skip);
840 }
841 break;
842 }
b21acc1c 843
7585a5b0 844 list_for_each_entry(ctl, &dsp->ctl_list, list) {
b21acc1c
CK		 845 if (!strcmp(ctl->name, name)) {
846 if (!ctl->enabled)
847 ctl->enabled = 1;
848 return 0;
849 }
850 }
851
852 ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
853 if (!ctl)
854 return -ENOMEM;
2323736d 855 ctl->fw_name = wm_adsp_fw_text[dsp->fw];
b21acc1c
CK		 856 ctl->alg_region = *alg_region;
857 ctl->name = kmemdup(name, strlen(name) + 1, GFP_KERNEL);
858 if (!ctl->name) {
859 ret = -ENOMEM;
860 goto err_ctl;
861 }
862 ctl->enabled = 1;
863 ctl->set = 0;
864 ctl->ops.xget = wm_coeff_get;
865 ctl->ops.xput = wm_coeff_put;
866 ctl->dsp = dsp;
867
26c22a19 868 ctl->flags = flags;
2323736d 869 ctl->offset = offset;
b21acc1c
CK		 870 if (len > 512) {
871 adsp_warn(dsp, "Truncating control %s from %d\n",
872 ctl->name, len);
873 len = 512;
874 }
875 ctl->len = len;
876 ctl->cache = kzalloc(ctl->len, GFP_KERNEL);
877 if (!ctl->cache) {
878 ret = -ENOMEM;
879 goto err_ctl_name;
880 }
881
2323736d
CK		 882 list_add(&ctl->list, &dsp->ctl_list);
883
b21acc1c
CK		 884 ctl_work = kzalloc(sizeof(*ctl_work), GFP_KERNEL);
885 if (!ctl_work) {
886 ret = -ENOMEM;
887 goto err_ctl_cache;
888 }
889
890 ctl_work->dsp = dsp;
891 ctl_work->ctl = ctl;
892 INIT_WORK(&ctl_work->work, wm_adsp_ctl_work);
893 schedule_work(&ctl_work->work);
894
895 return 0;
896
897err_ctl_cache:
898 kfree(ctl->cache);
899err_ctl_name:
900 kfree(ctl->name);
901err_ctl:
902 kfree(ctl);
903
904 return ret;
905}
906
2323736d
CK		 907struct wm_coeff_parsed_alg {
908 int id;
909 const u8 *name;
910 int name_len;
911 int ncoeff;
912};
913
914struct wm_coeff_parsed_coeff {
915 int offset;
916 int mem_type;
917 const u8 *name;
918 int name_len;
919 int ctl_type;
920 int flags;
921 int len;
922};
923
cb5b57a9
CK		 924static int wm_coeff_parse_string(int bytes, const u8 **pos, const u8 **str)
925{
926 int length;
927
928 switch (bytes) {
929 case 1:
930 length = **pos;
931 break;
932 case 2:
8299ee81 933 length = le16_to_cpu(*((__le16 *)*pos));
cb5b57a9
CK		 934 break;
935 default:
936 return 0;
937 }
938
939 if (str)
940 *str = *pos + bytes;
941
942 *pos += ((length + bytes) + 3) & ~0x03;
943
944 return length;
945}
946
947static int wm_coeff_parse_int(int bytes, const u8 **pos)
948{
949 int val = 0;
950
951 switch (bytes) {
952 case 2:
8299ee81 953 val = le16_to_cpu(*((__le16 *)*pos));
cb5b57a9
CK		 954 break;
955 case 4:
8299ee81 956 val = le32_to_cpu(*((__le32 *)*pos));
cb5b57a9
CK		 957 break;
958 default:
959 break;
960 }
961
962 *pos += bytes;
963
964 return val;
965}
966
2323736d
CK		 967static inline void wm_coeff_parse_alg(struct wm_adsp *dsp, const u8 **data,
968 struct wm_coeff_parsed_alg *blk)
969{
970 const struct wmfw_adsp_alg_data *raw;
971
cb5b57a9
CK		 972 switch (dsp->fw_ver) {
973 case 0:
974 case 1:
975 raw = (const struct wmfw_adsp_alg_data *)*data;
976 *data = raw->data;
2323736d 977
cb5b57a9
CK		 978 blk->id = le32_to_cpu(raw->id);
979 blk->name = raw->name;
980 blk->name_len = strlen(raw->name);
981 blk->ncoeff = le32_to_cpu(raw->ncoeff);
982 break;
983 default:
984 blk->id = wm_coeff_parse_int(sizeof(raw->id), data);
985 blk->name_len = wm_coeff_parse_string(sizeof(u8), data,
986 &blk->name);
987 wm_coeff_parse_string(sizeof(u16), data, NULL);
988 blk->ncoeff = wm_coeff_parse_int(sizeof(raw->ncoeff), data);
989 break;
990 }
2323736d
CK		 991
992 adsp_dbg(dsp, "Algorithm ID: %#x\n", blk->id);
993 adsp_dbg(dsp, "Algorithm name: %.*s\n", blk->name_len, blk->name);
994 adsp_dbg(dsp, "# of coefficient descriptors: %#x\n", blk->ncoeff);
995}
996
997static inline void wm_coeff_parse_coeff(struct wm_adsp *dsp, const u8 **data,
998 struct wm_coeff_parsed_coeff *blk)
999{
1000 const struct wmfw_adsp_coeff_data *raw;
cb5b57a9
CK		 1001 const u8 *tmp;
1002 int length;
2323736d 1003
cb5b57a9
CK		 1004 switch (dsp->fw_ver) {
1005 case 0:
1006 case 1:
1007 raw = (const struct wmfw_adsp_coeff_data *)*data;
1008 *data = *data + sizeof(raw->hdr) + le32_to_cpu(raw->hdr.size);
1009
1010 blk->offset = le16_to_cpu(raw->hdr.offset);
1011 blk->mem_type = le16_to_cpu(raw->hdr.type);
1012 blk->name = raw->name;
1013 blk->name_len = strlen(raw->name);
1014 blk->ctl_type = le16_to_cpu(raw->ctl_type);
1015 blk->flags = le16_to_cpu(raw->flags);
1016 blk->len = le32_to_cpu(raw->len);
1017 break;
1018 default:
1019 tmp = *data;
1020 blk->offset = wm_coeff_parse_int(sizeof(raw->hdr.offset), &tmp);
1021 blk->mem_type = wm_coeff_parse_int(sizeof(raw->hdr.type), &tmp);
1022 length = wm_coeff_parse_int(sizeof(raw->hdr.size), &tmp);
1023 blk->name_len = wm_coeff_parse_string(sizeof(u8), &tmp,
1024 &blk->name);
1025 wm_coeff_parse_string(sizeof(u8), &tmp, NULL);
1026 wm_coeff_parse_string(sizeof(u16), &tmp, NULL);
1027 blk->ctl_type = wm_coeff_parse_int(sizeof(raw->ctl_type), &tmp);
1028 blk->flags = wm_coeff_parse_int(sizeof(raw->flags), &tmp);
1029 blk->len = wm_coeff_parse_int(sizeof(raw->len), &tmp);
1030
1031 *data = *data + sizeof(raw->hdr) + length;
1032 break;
1033 }
2323736d
CK		 1034
1035 adsp_dbg(dsp, "\tCoefficient type: %#x\n", blk->mem_type);
1036 adsp_dbg(dsp, "\tCoefficient offset: %#x\n", blk->offset);
1037 adsp_dbg(dsp, "\tCoefficient name: %.*s\n", blk->name_len, blk->name);
1038 adsp_dbg(dsp, "\tCoefficient flags: %#x\n", blk->flags);
1039 adsp_dbg(dsp, "\tALSA control type: %#x\n", blk->ctl_type);
1040 adsp_dbg(dsp, "\tALSA control len: %#x\n", blk->len);
1041}
1042
1043static int wm_adsp_parse_coeff(struct wm_adsp *dsp,
1044 const struct wmfw_region *region)
1045{
1046 struct wm_adsp_alg_region alg_region = {};
1047 struct wm_coeff_parsed_alg alg_blk;
1048 struct wm_coeff_parsed_coeff coeff_blk;
1049 const u8 *data = region->data;
1050 int i, ret;
1051
1052 wm_coeff_parse_alg(dsp, &data, &alg_blk);
1053 for (i = 0; i < alg_blk.ncoeff; i++) {
1054 wm_coeff_parse_coeff(dsp, &data, &coeff_blk);
1055
1056 switch (coeff_blk.ctl_type) {
1057 case SNDRV_CTL_ELEM_TYPE_BYTES:
1058 break;
1059 default:
1060 adsp_err(dsp, "Unknown control type: %d\n",
1061 coeff_blk.ctl_type);
1062 return -EINVAL;
1063 }
1064
1065 alg_region.type = coeff_blk.mem_type;
1066 alg_region.alg = alg_blk.id;
1067
1068 ret = wm_adsp_create_control(dsp, &alg_region,
1069 coeff_blk.offset,
1070 coeff_blk.len,
1071 coeff_blk.name,
26c22a19
CK		 1072 coeff_blk.name_len,
1073 coeff_blk.flags);
2323736d
CK		 1074 if (ret < 0)
1075 adsp_err(dsp, "Failed to create control: %.*s, %d\n",
1076 coeff_blk.name_len, coeff_blk.name, ret);
1077 }
1078
1079 return 0;
1080}
1081
2159ad93
MB		 1082static int wm_adsp_load(struct wm_adsp *dsp)
1083{
cf17c83c 1084 LIST_HEAD(buf_list);
2159ad93
MB		 1085 const struct firmware *firmware;
1086 struct regmap *regmap = dsp->regmap;
1087 unsigned int pos = 0;
1088 const struct wmfw_header *header;
1089 const struct wmfw_adsp1_sizes *adsp1_sizes;
1090 const struct wmfw_adsp2_sizes *adsp2_sizes;
1091 const struct wmfw_footer *footer;
1092 const struct wmfw_region *region;
1093 const struct wm_adsp_region *mem;
1094 const char *region_name;
1095 char *file, *text;
cf17c83c 1096 struct wm_adsp_buf *buf;
2159ad93
MB		 1097 unsigned int reg;
1098 int regions = 0;
1099 int ret, offset, type, sizes;
1100
1101 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
1102 if (file == NULL)
1103 return -ENOMEM;
1104
1023dbd9
MB		 1105 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.wmfw", dsp->part, dsp->num,
1106 wm_adsp_fw[dsp->fw].file);
2159ad93
MB		 1107 file[PAGE_SIZE - 1] = '\0';
1108
1109 ret = request_firmware(&firmware, file, dsp->dev);
1110 if (ret != 0) {
1111 adsp_err(dsp, "Failed to request '%s'\n", file);
1112 goto out;
1113 }
1114 ret = -EINVAL;
1115
1116 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
1117 if (pos >= firmware->size) {
1118 adsp_err(dsp, "%s: file too short, %zu bytes\n",
1119 file, firmware->size);
1120 goto out_fw;
1121 }
1122
7585a5b0 1123 header = (void *)&firmware->data[0];
2159ad93
MB		 1124
1125 if (memcmp(&header->magic[0], "WMFW", 4) != 0) {
1126 adsp_err(dsp, "%s: invalid magic\n", file);
1127 goto out_fw;
1128 }
1129
2323736d
CK		 1130 switch (header->ver) {
1131 case 0:
c61e59fe
CK		 1132 adsp_warn(dsp, "%s: Depreciated file format %d\n",
1133 file, header->ver);
1134 break;
2323736d 1135 case 1:
cb5b57a9 1136 case 2:
2323736d
CK		 1137 break;
1138 default:
2159ad93
MB		 1139 adsp_err(dsp, "%s: unknown file format %d\n",
1140 file, header->ver);
1141 goto out_fw;
1142 }
2323736d 1143
3626992a 1144 adsp_info(dsp, "Firmware version: %d\n", header->ver);
2323736d 1145 dsp->fw_ver = header->ver;
2159ad93
MB		 1146
1147 if (header->core != dsp->type) {
1148 adsp_err(dsp, "%s: invalid core %d != %d\n",
1149 file, header->core, dsp->type);
1150 goto out_fw;
1151 }
1152
1153 switch (dsp->type) {
1154 case WMFW_ADSP1:
1155 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
1156 adsp1_sizes = (void *)&(header[1]);
1157 footer = (void *)&(adsp1_sizes[1]);
1158 sizes = sizeof(*adsp1_sizes);
1159
1160 adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n",
1161 file, le32_to_cpu(adsp1_sizes->dm),
1162 le32_to_cpu(adsp1_sizes->pm),
1163 le32_to_cpu(adsp1_sizes->zm));
1164 break;
1165
1166 case WMFW_ADSP2:
1167 pos = sizeof(*header) + sizeof(*adsp2_sizes) + sizeof(*footer);
1168 adsp2_sizes = (void *)&(header[1]);
1169 footer = (void *)&(adsp2_sizes[1]);
1170 sizes = sizeof(*adsp2_sizes);
1171
1172 adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n",
1173 file, le32_to_cpu(adsp2_sizes->xm),
1174 le32_to_cpu(adsp2_sizes->ym),
1175 le32_to_cpu(adsp2_sizes->pm),
1176 le32_to_cpu(adsp2_sizes->zm));
1177 break;
1178
1179 default:
6c452bda 1180 WARN(1, "Unknown DSP type");
2159ad93
MB		 1181 goto out_fw;
1182 }
1183
1184 if (le32_to_cpu(header->len) != sizeof(*header) +
1185 sizes + sizeof(*footer)) {
1186 adsp_err(dsp, "%s: unexpected header length %d\n",
1187 file, le32_to_cpu(header->len));
1188 goto out_fw;
1189 }
1190
1191 adsp_dbg(dsp, "%s: timestamp %llu\n", file,
1192 le64_to_cpu(footer->timestamp));
1193
1194 while (pos < firmware->size &&
1195 pos - firmware->size > sizeof(*region)) {
1196 region = (void *)&(firmware->data[pos]);
1197 region_name = "Unknown";
1198 reg = 0;
1199 text = NULL;
1200 offset = le32_to_cpu(region->offset) & 0xffffff;
1201 type = be32_to_cpu(region->type) & 0xff;
1202 mem = wm_adsp_find_region(dsp, type);
7585a5b0 1203
2159ad93
MB		 1204 switch (type) {
1205 case WMFW_NAME_TEXT:
1206 region_name = "Firmware name";
1207 text = kzalloc(le32_to_cpu(region->len) + 1,
1208 GFP_KERNEL);
1209 break;
2323736d
CK		 1210 case WMFW_ALGORITHM_DATA:
1211 region_name = "Algorithm";
1212 ret = wm_adsp_parse_coeff(dsp, region);
1213 if (ret != 0)
1214 goto out_fw;
1215 break;
2159ad93
MB		 1216 case WMFW_INFO_TEXT:
1217 region_name = "Information";
1218 text = kzalloc(le32_to_cpu(region->len) + 1,
1219 GFP_KERNEL);
1220 break;
1221 case WMFW_ABSOLUTE:
1222 region_name = "Absolute";
1223 reg = offset;
1224 break;
1225 case WMFW_ADSP1_PM:
2159ad93 1226 region_name = "PM";
45b9ee72 1227 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 1228 break;
1229 case WMFW_ADSP1_DM:
2159ad93 1230 region_name = "DM";
45b9ee72 1231 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 1232 break;
1233 case WMFW_ADSP2_XM:
2159ad93 1234 region_name = "XM";
45b9ee72 1235 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 1236 break;
1237 case WMFW_ADSP2_YM:
2159ad93 1238 region_name = "YM";
45b9ee72 1239 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 1240 break;
1241 case WMFW_ADSP1_ZM:
2159ad93 1242 region_name = "ZM";
45b9ee72 1243 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 1244 break;
1245 default:
1246 adsp_warn(dsp,
1247 "%s.%d: Unknown region type %x at %d(%x)\n",
1248 file, regions, type, pos, pos);
1249 break;
1250 }
1251
1252 adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file,
1253 regions, le32_to_cpu(region->len), offset,
1254 region_name);
1255
1256 if (text) {
1257 memcpy(text, region->data, le32_to_cpu(region->len));
1258 adsp_info(dsp, "%s: %s\n", file, text);
1259 kfree(text);
1260 }
1261
1262 if (reg) {
cdcd7f72
CK		 1263 buf = wm_adsp_buf_alloc(region->data,
1264 le32_to_cpu(region->len),
1265 &buf_list);
1266 if (!buf) {
1267 adsp_err(dsp, "Out of memory\n");
1268 ret = -ENOMEM;
1269 goto out_fw;
1270 }
c1a7898d 1271
cdcd7f72
CK		 1272 ret = regmap_raw_write_async(regmap, reg, buf->buf,
1273 le32_to_cpu(region->len));
1274 if (ret != 0) {
1275 adsp_err(dsp,
1276 "%s.%d: Failed to write %d bytes at %d in %s: %d\n",
1277 file, regions,
1278 le32_to_cpu(region->len), offset,
1279 region_name, ret);
1280 goto out_fw;
2159ad93
MB		 1281 }
1282 }
1283
1284 pos += le32_to_cpu(region->len) + sizeof(*region);
1285 regions++;
1286 }
cf17c83c
MB		 1287
1288 ret = regmap_async_complete(regmap);
1289 if (ret != 0) {
1290 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
1291 goto out_fw;
1292 }
1293
2159ad93
MB		 1294 if (pos > firmware->size)
1295 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
1296 file, regions, pos - firmware->size);
1297
f9f55e31
RF		 1298 wm_adsp_debugfs_save_wmfwname(dsp, file);
1299
2159ad93 1300out_fw:
cf17c83c
MB		 1301 regmap_async_complete(regmap);
1302 wm_adsp_buf_free(&buf_list);
2159ad93
MB		 1303 release_firmware(firmware);
1304out:
1305 kfree(file);
1306
1307 return ret;
1308}
1309
2323736d
CK		 1310static void wm_adsp_ctl_fixup_base(struct wm_adsp *dsp,
1311 const struct wm_adsp_alg_region *alg_region)
1312{
1313 struct wm_coeff_ctl *ctl;
1314
1315 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1316 if (ctl->fw_name == wm_adsp_fw_text[dsp->fw] &&
1317 alg_region->alg == ctl->alg_region.alg &&
1318 alg_region->type == ctl->alg_region.type) {
1319 ctl->alg_region.base = alg_region->base;
1320 }
1321 }
1322}
1323
3809f001 1324static void *wm_adsp_read_algs(struct wm_adsp *dsp, size_t n_algs,
b618a185 1325 unsigned int pos, unsigned int len)
db40517c 1326{
b618a185
CK		 1327 void *alg;
1328 int ret;
db40517c 1329 __be32 val;
db40517c 1330
3809f001 1331 if (n_algs == 0) {
b618a185
CK		 1332 adsp_err(dsp, "No algorithms\n");
1333 return ERR_PTR(-EINVAL);
db40517c
MB		 1334 }
1335
3809f001
CK		 1336 if (n_algs > 1024) {
1337 adsp_err(dsp, "Algorithm count %zx excessive\n", n_algs);
b618a185
CK		 1338 return ERR_PTR(-EINVAL);
1339 }
db40517c 1340
b618a185
CK		 1341 /* Read the terminator first to validate the length */
1342 ret = regmap_raw_read(dsp->regmap, pos + len, &val, sizeof(val));
1343 if (ret != 0) {
1344 adsp_err(dsp, "Failed to read algorithm list end: %d\n",
1345 ret);
1346 return ERR_PTR(ret);
1347 }
db40517c 1348
b618a185
CK		 1349 if (be32_to_cpu(val) != 0xbedead)
1350 adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbeadead\n",
1351 pos + len, be32_to_cpu(val));
d62f4bc6 1352
b618a185
CK		 1353 alg = kzalloc(len * 2, GFP_KERNEL | GFP_DMA);
1354 if (!alg)
1355 return ERR_PTR(-ENOMEM);
db40517c 1356
b618a185
CK		 1357 ret = regmap_raw_read(dsp->regmap, pos, alg, len * 2);
1358 if (ret != 0) {
1359 adsp_err(dsp, "Failed to read algorithm list: %d\n",
1360 ret);
1361 kfree(alg);
1362 return ERR_PTR(ret);
1363 }
ac50009f 1364
b618a185
CK		 1365 return alg;
1366}
ac50009f 1367
d9d20e17
CK		 1368static struct wm_adsp_alg_region *wm_adsp_create_region(struct wm_adsp *dsp,
1369 int type, __be32 id,
1370 __be32 base)
1371{
1372 struct wm_adsp_alg_region *alg_region;
1373
1374 alg_region = kzalloc(sizeof(*alg_region), GFP_KERNEL);
1375 if (!alg_region)
1376 return ERR_PTR(-ENOMEM);
1377
1378 alg_region->type = type;
1379 alg_region->alg = be32_to_cpu(id);
1380 alg_region->base = be32_to_cpu(base);
1381
1382 list_add_tail(&alg_region->list, &dsp->alg_regions);
1383
2323736d
CK		 1384 if (dsp->fw_ver > 0)
1385 wm_adsp_ctl_fixup_base(dsp, alg_region);
1386
d9d20e17
CK		 1387 return alg_region;
1388}
1389
b618a185
CK		 1390static int wm_adsp1_setup_algs(struct wm_adsp *dsp)
1391{
1392 struct wmfw_adsp1_id_hdr adsp1_id;
1393 struct wmfw_adsp1_alg_hdr *adsp1_alg;
3809f001 1394 struct wm_adsp_alg_region *alg_region;
b618a185
CK		 1395 const struct wm_adsp_region *mem;
1396 unsigned int pos, len;
3809f001 1397 size_t n_algs;
b618a185 1398 int i, ret;
db40517c 1399
b618a185
CK		 1400 mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM);
1401 if (WARN_ON(!mem))
1402 return -EINVAL;
1403
1404 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp1_id,
1405 sizeof(adsp1_id));
1406 if (ret != 0) {
1407 adsp_err(dsp, "Failed to read algorithm info: %d\n",
1408 ret);
1409 return ret;
1410 }
db40517c 1411
3809f001 1412 n_algs = be32_to_cpu(adsp1_id.n_algs);
b618a185
CK		 1413 dsp->fw_id = be32_to_cpu(adsp1_id.fw.id);
1414 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
1415 dsp->fw_id,
1416 (be32_to_cpu(adsp1_id.fw.ver) & 0xff0000) >> 16,
1417 (be32_to_cpu(adsp1_id.fw.ver) & 0xff00) >> 8,
1418 be32_to_cpu(adsp1_id.fw.ver) & 0xff,
3809f001 1419 n_algs);
b618a185 1420
d9d20e17
CK		 1421 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
1422 adsp1_id.fw.id, adsp1_id.zm);
1423 if (IS_ERR(alg_region))
1424 return PTR_ERR(alg_region);
d62f4bc6 1425
d9d20e17
CK		 1426 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
1427 adsp1_id.fw.id, adsp1_id.dm);
1428 if (IS_ERR(alg_region))
1429 return PTR_ERR(alg_region);
db40517c 1430
b618a185 1431 pos = sizeof(adsp1_id) / 2;
3809f001 1432 len = (sizeof(*adsp1_alg) * n_algs) / 2;
b618a185 1433
3809f001 1434 adsp1_alg = wm_adsp_read_algs(dsp, n_algs, mem->base + pos, len);
b618a185
CK		 1435 if (IS_ERR(adsp1_alg))
1436 return PTR_ERR(adsp1_alg);
1437
3809f001 1438 for (i = 0; i < n_algs; i++) {
b618a185
CK		 1439 adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n",
1440 i, be32_to_cpu(adsp1_alg[i].alg.id),
1441 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16,
1442 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8,
1443 be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff,
1444 be32_to_cpu(adsp1_alg[i].dm),
1445 be32_to_cpu(adsp1_alg[i].zm));
ac50009f 1446
d9d20e17
CK		 1447 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
1448 adsp1_alg[i].alg.id,
1449 adsp1_alg[i].dm);
1450 if (IS_ERR(alg_region)) {
1451 ret = PTR_ERR(alg_region);
b618a185
CK		 1452 goto out;
1453 }
2323736d
CK		 1454 if (dsp->fw_ver == 0) {
1455 if (i + 1 < n_algs) {
1456 len = be32_to_cpu(adsp1_alg[i + 1].dm);
1457 len -= be32_to_cpu(adsp1_alg[i].dm);
1458 len *= 4;
1459 wm_adsp_create_control(dsp, alg_region, 0,
26c22a19 1460 len, NULL, 0, 0);
2323736d
CK		 1461 } else {
1462 adsp_warn(dsp, "Missing length info for region DM with ID %x\n",
1463 be32_to_cpu(adsp1_alg[i].alg.id));
1464 }
b618a185 1465 }
ac50009f 1466
d9d20e17
CK		 1467 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
1468 adsp1_alg[i].alg.id,
1469 adsp1_alg[i].zm);
1470 if (IS_ERR(alg_region)) {
1471 ret = PTR_ERR(alg_region);
b618a185
CK		 1472 goto out;
1473 }
2323736d
CK		 1474 if (dsp->fw_ver == 0) {
1475 if (i + 1 < n_algs) {
1476 len = be32_to_cpu(adsp1_alg[i + 1].zm);
1477 len -= be32_to_cpu(adsp1_alg[i].zm);
1478 len *= 4;
1479 wm_adsp_create_control(dsp, alg_region, 0,
26c22a19 1480 len, NULL, 0, 0);
2323736d
CK		 1481 } else {
1482 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
1483 be32_to_cpu(adsp1_alg[i].alg.id));
1484 }
b618a185 1485 }
db40517c
MB		 1486 }
1487
b618a185
CK		 1488out:
1489 kfree(adsp1_alg);
1490 return ret;
1491}
db40517c 1492
b618a185
CK		 1493static int wm_adsp2_setup_algs(struct wm_adsp *dsp)
1494{
1495 struct wmfw_adsp2_id_hdr adsp2_id;
1496 struct wmfw_adsp2_alg_hdr *adsp2_alg;
3809f001 1497 struct wm_adsp_alg_region *alg_region;
b618a185
CK		 1498 const struct wm_adsp_region *mem;
1499 unsigned int pos, len;
3809f001 1500 size_t n_algs;
b618a185
CK		 1501 int i, ret;
1502
1503 mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM);
1504 if (WARN_ON(!mem))
d62f4bc6 1505 return -EINVAL;
d62f4bc6 1506
b618a185
CK		 1507 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp2_id,
1508 sizeof(adsp2_id));
db40517c 1509 if (ret != 0) {
b618a185
CK		 1510 adsp_err(dsp, "Failed to read algorithm info: %d\n",
1511 ret);
db40517c
MB		 1512 return ret;
1513 }
1514
3809f001 1515 n_algs = be32_to_cpu(adsp2_id.n_algs);
b618a185 1516 dsp->fw_id = be32_to_cpu(adsp2_id.fw.id);
f9f55e31 1517 dsp->fw_id_version = be32_to_cpu(adsp2_id.fw.ver);
b618a185
CK		 1518 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
1519 dsp->fw_id,
f9f55e31
RF		 1520 (dsp->fw_id_version & 0xff0000) >> 16,
1521 (dsp->fw_id_version & 0xff00) >> 8,
1522 dsp->fw_id_version & 0xff,
3809f001 1523 n_algs);
b618a185 1524
d9d20e17
CK		 1525 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
1526 adsp2_id.fw.id, adsp2_id.xm);
1527 if (IS_ERR(alg_region))
1528 return PTR_ERR(alg_region);
db40517c 1529
d9d20e17
CK		 1530 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
1531 adsp2_id.fw.id, adsp2_id.ym);
1532 if (IS_ERR(alg_region))
1533 return PTR_ERR(alg_region);
db40517c 1534
d9d20e17
CK		 1535 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
1536 adsp2_id.fw.id, adsp2_id.zm);
1537 if (IS_ERR(alg_region))
1538 return PTR_ERR(alg_region);
db40517c 1539
b618a185 1540 pos = sizeof(adsp2_id) / 2;
3809f001 1541 len = (sizeof(*adsp2_alg) * n_algs) / 2;
db40517c 1542
3809f001 1543 adsp2_alg = wm_adsp_read_algs(dsp, n_algs, mem->base + pos, len);
b618a185
CK		 1544 if (IS_ERR(adsp2_alg))
1545 return PTR_ERR(adsp2_alg);
471f4885 1546
3809f001 1547 for (i = 0; i < n_algs; i++) {
b618a185
CK		 1548 adsp_info(dsp,
1549 "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n",
1550 i, be32_to_cpu(adsp2_alg[i].alg.id),
1551 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16,
1552 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8,
1553 be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff,
1554 be32_to_cpu(adsp2_alg[i].xm),
1555 be32_to_cpu(adsp2_alg[i].ym),
1556 be32_to_cpu(adsp2_alg[i].zm));
db40517c 1557
d9d20e17
CK		 1558 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
1559 adsp2_alg[i].alg.id,
1560 adsp2_alg[i].xm);
1561 if (IS_ERR(alg_region)) {
1562 ret = PTR_ERR(alg_region);
b618a185
CK		 1563 goto out;
1564 }
2323736d
CK		 1565 if (dsp->fw_ver == 0) {
1566 if (i + 1 < n_algs) {
1567 len = be32_to_cpu(adsp2_alg[i + 1].xm);
1568 len -= be32_to_cpu(adsp2_alg[i].xm);
1569 len *= 4;
1570 wm_adsp_create_control(dsp, alg_region, 0,
26c22a19 1571 len, NULL, 0, 0);
2323736d
CK		 1572 } else {
1573 adsp_warn(dsp, "Missing length info for region XM with ID %x\n",
1574 be32_to_cpu(adsp2_alg[i].alg.id));
1575 }
b618a185 1576 }
471f4885 1577
d9d20e17
CK		 1578 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
1579 adsp2_alg[i].alg.id,
1580 adsp2_alg[i].ym);
1581 if (IS_ERR(alg_region)) {
1582 ret = PTR_ERR(alg_region);
b618a185
CK		 1583 goto out;
1584 }
2323736d
CK		 1585 if (dsp->fw_ver == 0) {
1586 if (i + 1 < n_algs) {
1587 len = be32_to_cpu(adsp2_alg[i + 1].ym);
1588 len -= be32_to_cpu(adsp2_alg[i].ym);
1589 len *= 4;
1590 wm_adsp_create_control(dsp, alg_region, 0,
26c22a19 1591 len, NULL, 0, 0);
2323736d
CK		 1592 } else {
1593 adsp_warn(dsp, "Missing length info for region YM with ID %x\n",
1594 be32_to_cpu(adsp2_alg[i].alg.id));
1595 }
b618a185 1596 }
471f4885 1597
d9d20e17
CK		 1598 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
1599 adsp2_alg[i].alg.id,
1600 adsp2_alg[i].zm);
1601 if (IS_ERR(alg_region)) {
1602 ret = PTR_ERR(alg_region);
b618a185
CK		 1603 goto out;
1604 }
2323736d
CK		 1605 if (dsp->fw_ver == 0) {
1606 if (i + 1 < n_algs) {
1607 len = be32_to_cpu(adsp2_alg[i + 1].zm);
1608 len -= be32_to_cpu(adsp2_alg[i].zm);
1609 len *= 4;
1610 wm_adsp_create_control(dsp, alg_region, 0,
26c22a19 1611 len, NULL, 0, 0);
2323736d
CK		 1612 } else {
1613 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
1614 be32_to_cpu(adsp2_alg[i].alg.id));
1615 }
db40517c
MB		 1616 }
1617 }
1618
1619out:
b618a185 1620 kfree(adsp2_alg);
db40517c
MB		 1621 return ret;
1622}
1623
2159ad93
MB		 1624static int wm_adsp_load_coeff(struct wm_adsp *dsp)
1625{
cf17c83c 1626 LIST_HEAD(buf_list);
2159ad93
MB		 1627 struct regmap *regmap = dsp->regmap;
1628 struct wmfw_coeff_hdr *hdr;
1629 struct wmfw_coeff_item *blk;
1630 const struct firmware *firmware;
471f4885
MB		 1631 const struct wm_adsp_region *mem;
1632 struct wm_adsp_alg_region *alg_region;
2159ad93
MB		 1633 const char *region_name;
1634 int ret, pos, blocks, type, offset, reg;
1635 char *file;
cf17c83c 1636 struct wm_adsp_buf *buf;
2159ad93
MB		 1637
1638 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
1639 if (file == NULL)
1640 return -ENOMEM;
1641
1023dbd9
MB		 1642 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.bin", dsp->part, dsp->num,
1643 wm_adsp_fw[dsp->fw].file);
2159ad93
MB		 1644 file[PAGE_SIZE - 1] = '\0';
1645
1646 ret = request_firmware(&firmware, file, dsp->dev);
1647 if (ret != 0) {
1648 adsp_warn(dsp, "Failed to request '%s'\n", file);
1649 ret = 0;
1650 goto out;
1651 }
1652 ret = -EINVAL;
1653
1654 if (sizeof(*hdr) >= firmware->size) {
1655 adsp_err(dsp, "%s: file too short, %zu bytes\n",
1656 file, firmware->size);
1657 goto out_fw;
1658 }
1659
7585a5b0 1660 hdr = (void *)&firmware->data[0];
2159ad93
MB		 1661 if (memcmp(hdr->magic, "WMDR", 4) != 0) {
1662 adsp_err(dsp, "%s: invalid magic\n", file);
a4cdbec7 1663 goto out_fw;
2159ad93
MB		 1664 }
1665
c712326d
MB		 1666 switch (be32_to_cpu(hdr->rev) & 0xff) {
1667 case 1:
1668 break;
1669 default:
1670 adsp_err(dsp, "%s: Unsupported coefficient file format %d\n",
1671 file, be32_to_cpu(hdr->rev) & 0xff);
1672 ret = -EINVAL;
1673 goto out_fw;
1674 }
1675
2159ad93
MB		 1676 adsp_dbg(dsp, "%s: v%d.%d.%d\n", file,
1677 (le32_to_cpu(hdr->ver) >> 16) & 0xff,
1678 (le32_to_cpu(hdr->ver) >> 8) & 0xff,
1679 le32_to_cpu(hdr->ver) & 0xff);
1680
1681 pos = le32_to_cpu(hdr->len);
1682
1683 blocks = 0;
1684 while (pos < firmware->size &&
1685 pos - firmware->size > sizeof(*blk)) {
7585a5b0 1686 blk = (void *)(&firmware->data[pos]);
2159ad93 1687
c712326d
MB		 1688 type = le16_to_cpu(blk->type);
1689 offset = le16_to_cpu(blk->offset);
2159ad93
MB		 1690
1691 adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n",
1692 file, blocks, le32_to_cpu(blk->id),
1693 (le32_to_cpu(blk->ver) >> 16) & 0xff,
1694 (le32_to_cpu(blk->ver) >> 8) & 0xff,
1695 le32_to_cpu(blk->ver) & 0xff);
1696 adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n",
1697 file, blocks, le32_to_cpu(blk->len), offset, type);
1698
1699 reg = 0;
1700 region_name = "Unknown";
1701 switch (type) {
c712326d
MB		 1702 case (WMFW_NAME_TEXT << 8):
1703 case (WMFW_INFO_TEXT << 8):
2159ad93 1704 break;
c712326d 1705 case (WMFW_ABSOLUTE << 8):
f395a218
MB		 1706 /*
1707 * Old files may use this for global
1708 * coefficients.
1709 */
1710 if (le32_to_cpu(blk->id) == dsp->fw_id &&
1711 offset == 0) {
1712 region_name = "global coefficients";
1713 mem = wm_adsp_find_region(dsp, type);
1714 if (!mem) {
1715 adsp_err(dsp, "No ZM\n");
1716 break;
1717 }
1718 reg = wm_adsp_region_to_reg(mem, 0);
1719
1720 } else {
1721 region_name = "register";
1722 reg = offset;
1723 }
2159ad93 1724 break;
471f4885
MB		 1725
1726 case WMFW_ADSP1_DM:
1727 case WMFW_ADSP1_ZM:
1728 case WMFW_ADSP2_XM:
1729 case WMFW_ADSP2_YM:
1730 adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n",
1731 file, blocks, le32_to_cpu(blk->len),
1732 type, le32_to_cpu(blk->id));
1733
1734 mem = wm_adsp_find_region(dsp, type);
1735 if (!mem) {
1736 adsp_err(dsp, "No base for region %x\n", type);
1737 break;
1738 }
1739
1740 reg = 0;
1741 list_for_each_entry(alg_region,
1742 &dsp->alg_regions, list) {
1743 if (le32_to_cpu(blk->id) == alg_region->alg &&
1744 type == alg_region->type) {
338c5188 1745 reg = alg_region->base;
471f4885
MB		 1746 reg = wm_adsp_region_to_reg(mem,
1747 reg);
338c5188 1748 reg += offset;
d733dc08 1749 break;
471f4885
MB		 1750 }
1751 }
1752
1753 if (reg == 0)
1754 adsp_err(dsp, "No %x for algorithm %x\n",
1755 type, le32_to_cpu(blk->id));
1756 break;
1757
2159ad93 1758 default:
25c62f7e
MB		 1759 adsp_err(dsp, "%s.%d: Unknown region type %x at %d\n",
1760 file, blocks, type, pos);
2159ad93
MB		 1761 break;
1762 }
1763
1764 if (reg) {
cf17c83c
MB		 1765 buf = wm_adsp_buf_alloc(blk->data,
1766 le32_to_cpu(blk->len),
1767 &buf_list);
a76fefab
MB		 1768 if (!buf) {
1769 adsp_err(dsp, "Out of memory\n");
f4b82812
WY		 1770 ret = -ENOMEM;
1771 goto out_fw;
a76fefab
MB		 1772 }
1773
20da6d5a
MB		 1774 adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n",
1775 file, blocks, le32_to_cpu(blk->len),
1776 reg);
cf17c83c
MB		 1777 ret = regmap_raw_write_async(regmap, reg, buf->buf,
1778 le32_to_cpu(blk->len));
2159ad93
MB		 1779 if (ret != 0) {
1780 adsp_err(dsp,
43bc3bf6
DP		 1781 "%s.%d: Failed to write to %x in %s: %d\n",
1782 file, blocks, reg, region_name, ret);
2159ad93
MB		 1783 }
1784 }
1785
be951017 1786 pos += (le32_to_cpu(blk->len) + sizeof(*blk) + 3) & ~0x03;
2159ad93
MB		 1787 blocks++;
1788 }
1789
cf17c83c
MB		 1790 ret = regmap_async_complete(regmap);
1791 if (ret != 0)
1792 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
1793
2159ad93
MB		 1794 if (pos > firmware->size)
1795 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
1796 file, blocks, pos - firmware->size);
1797
f9f55e31
RF		 1798 wm_adsp_debugfs_save_binname(dsp, file);
1799
2159ad93 1800out_fw:
9da7a5a9 1801 regmap_async_complete(regmap);
2159ad93 1802 release_firmware(firmware);
cf17c83c 1803 wm_adsp_buf_free(&buf_list);
2159ad93
MB		 1804out:
1805 kfree(file);
f4b82812 1806 return ret;
2159ad93
MB		 1807}
1808
3809f001 1809int wm_adsp1_init(struct wm_adsp *dsp)
5e7a7a22 1810{
3809f001 1811 INIT_LIST_HEAD(&dsp->alg_regions);
5e7a7a22 1812
078e7183
CK		 1813 mutex_init(&dsp->pwr_lock);
1814
5e7a7a22
MB		 1815 return 0;
1816}
1817EXPORT_SYMBOL_GPL(wm_adsp1_init);
1818
2159ad93
MB		 1819int wm_adsp1_event(struct snd_soc_dapm_widget *w,
1820 struct snd_kcontrol *kcontrol,
1821 int event)
1822{
72718517 1823 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2159ad93
MB		 1824 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
1825 struct wm_adsp *dsp = &dsps[w->shift];
b0101b4f 1826 struct wm_adsp_alg_region *alg_region;
6ab2b7b4 1827 struct wm_coeff_ctl *ctl;
2159ad93 1828 int ret;
7585a5b0 1829 unsigned int val;
2159ad93 1830
00200107 1831 dsp->card = codec->component.card;
92bb4c32 1832
078e7183
CK		 1833 mutex_lock(&dsp->pwr_lock);
1834
2159ad93
MB		 1835 switch (event) {
1836 case SND_SOC_DAPM_POST_PMU:
1837 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1838 ADSP1_SYS_ENA, ADSP1_SYS_ENA);
1839
94e205bf
CR		 1840 /*
1841 * For simplicity set the DSP clock rate to be the
1842 * SYSCLK rate rather than making it configurable.
1843 */
7585a5b0 1844 if (dsp->sysclk_reg) {
94e205bf
CR		 1845 ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val);
1846 if (ret != 0) {
1847 adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
1848 ret);
078e7183 1849 goto err_mutex;
94e205bf
CR		 1850 }
1851
1852 val = (val & dsp->sysclk_mask)
1853 >> dsp->sysclk_shift;
1854
1855 ret = regmap_update_bits(dsp->regmap,
1856 dsp->base + ADSP1_CONTROL_31,
1857 ADSP1_CLK_SEL_MASK, val);
1858 if (ret != 0) {
1859 adsp_err(dsp, "Failed to set clock rate: %d\n",
1860 ret);
078e7183 1861 goto err_mutex;
94e205bf
CR		 1862 }
1863 }
1864
2159ad93
MB		 1865 ret = wm_adsp_load(dsp);
1866 if (ret != 0)
078e7183 1867 goto err_ena;
2159ad93 1868
b618a185 1869 ret = wm_adsp1_setup_algs(dsp);
db40517c 1870 if (ret != 0)
078e7183 1871 goto err_ena;
db40517c 1872
2159ad93
MB		 1873 ret = wm_adsp_load_coeff(dsp);
1874 if (ret != 0)
078e7183 1875 goto err_ena;
2159ad93 1876
0c2e3f34 1877 /* Initialize caches for enabled and unset controls */
81ad93ec 1878 ret = wm_coeff_init_control_caches(dsp);
6ab2b7b4 1879 if (ret != 0)
078e7183 1880 goto err_ena;
6ab2b7b4 1881
0c2e3f34 1882 /* Sync set controls */
81ad93ec 1883 ret = wm_coeff_sync_controls(dsp);
6ab2b7b4 1884 if (ret != 0)
078e7183 1885 goto err_ena;
6ab2b7b4 1886
2159ad93
MB		 1887 /* Start the core running */
1888 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1889 ADSP1_CORE_ENA | ADSP1_START,
1890 ADSP1_CORE_ENA | ADSP1_START);
1891 break;
1892
1893 case SND_SOC_DAPM_PRE_PMD:
1894 /* Halt the core */
1895 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1896 ADSP1_CORE_ENA | ADSP1_START, 0);
1897
1898 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19,
1899 ADSP1_WDMA_BUFFER_LENGTH_MASK, 0);
1900
1901 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1902 ADSP1_SYS_ENA, 0);
6ab2b7b4 1903
81ad93ec 1904 list_for_each_entry(ctl, &dsp->ctl_list, list)
6ab2b7b4 1905 ctl->enabled = 0;
b0101b4f
DP		 1906
1907 while (!list_empty(&dsp->alg_regions)) {
1908 alg_region = list_first_entry(&dsp->alg_regions,
1909 struct wm_adsp_alg_region,
1910 list);
1911 list_del(&alg_region->list);
1912 kfree(alg_region);
1913 }
2159ad93
MB		 1914 break;
1915
1916 default:
1917 break;
1918 }
1919
078e7183
CK		 1920 mutex_unlock(&dsp->pwr_lock);
1921
2159ad93
MB		 1922 return 0;
1923
078e7183 1924err_ena:
2159ad93
MB		 1925 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1926 ADSP1_SYS_ENA, 0);
078e7183
CK		 1927err_mutex:
1928 mutex_unlock(&dsp->pwr_lock);
1929
2159ad93
MB		 1930 return ret;
1931}
1932EXPORT_SYMBOL_GPL(wm_adsp1_event);
1933
1934static int wm_adsp2_ena(struct wm_adsp *dsp)
1935{
1936 unsigned int val;
1937 int ret, count;
1938
1552c325
MB		 1939 ret = regmap_update_bits_async(dsp->regmap, dsp->base + ADSP2_CONTROL,
1940 ADSP2_SYS_ENA, ADSP2_SYS_ENA);
2159ad93
MB		 1941 if (ret != 0)
1942 return ret;
1943
1944 /* Wait for the RAM to start, should be near instantaneous */
939fd1e8 1945 for (count = 0; count < 10; ++count) {
2159ad93
MB		 1946 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1,
1947 &val);
1948 if (ret != 0)
1949 return ret;
939fd1e8
CK		 1950
1951 if (val & ADSP2_RAM_RDY)
1952 break;
1953
1954 msleep(1);
1955 }
2159ad93
MB		 1956
1957 if (!(val & ADSP2_RAM_RDY)) {
1958 adsp_err(dsp, "Failed to start DSP RAM\n");
1959 return -EBUSY;
1960 }
1961
1962 adsp_dbg(dsp, "RAM ready after %d polls\n", count);
2159ad93
MB		 1963
1964 return 0;
1965}
1966
18b1a902 1967static void wm_adsp2_boot_work(struct work_struct *work)
2159ad93 1968{
d8a64d6a
CK		 1969 struct wm_adsp *dsp = container_of(work,
1970 struct wm_adsp,
1971 boot_work);
2159ad93 1972 int ret;
d8a64d6a 1973 unsigned int val;
2159ad93 1974
078e7183
CK		 1975 mutex_lock(&dsp->pwr_lock);
1976
d8a64d6a
CK		 1977 /*
1978 * For simplicity set the DSP clock rate to be the
1979 * SYSCLK rate rather than making it configurable.
1980 */
1981 ret = regmap_read(dsp->regmap, ARIZONA_SYSTEM_CLOCK_1, &val);
1982 if (ret != 0) {
1983 adsp_err(dsp, "Failed to read SYSCLK state: %d\n", ret);
078e7183 1984 goto err_mutex;
d8a64d6a
CK		 1985 }
1986 val = (val & ARIZONA_SYSCLK_FREQ_MASK)
1987 >> ARIZONA_SYSCLK_FREQ_SHIFT;
92bb4c32 1988
d8a64d6a
CK		 1989 ret = regmap_update_bits_async(dsp->regmap,
1990 dsp->base + ADSP2_CLOCKING,
1991 ADSP2_CLK_SEL_MASK, val);
1992 if (ret != 0) {
1993 adsp_err(dsp, "Failed to set clock rate: %d\n", ret);
078e7183 1994 goto err_mutex;
d8a64d6a 1995 }
dd49e2c8 1996
d8a64d6a
CK		 1997 ret = wm_adsp2_ena(dsp);
1998 if (ret != 0)
078e7183 1999 goto err_mutex;
2159ad93 2000
d8a64d6a
CK		 2001 ret = wm_adsp_load(dsp);
2002 if (ret != 0)
078e7183 2003 goto err_ena;
2159ad93 2004
b618a185 2005 ret = wm_adsp2_setup_algs(dsp);
d8a64d6a 2006 if (ret != 0)
078e7183 2007 goto err_ena;
db40517c 2008
d8a64d6a
CK		 2009 ret = wm_adsp_load_coeff(dsp);
2010 if (ret != 0)
078e7183 2011 goto err_ena;
2159ad93 2012
d8a64d6a
CK		 2013 /* Initialize caches for enabled and unset controls */
2014 ret = wm_coeff_init_control_caches(dsp);
2015 if (ret != 0)
078e7183 2016 goto err_ena;
6ab2b7b4 2017
d8a64d6a
CK		 2018 /* Sync set controls */
2019 ret = wm_coeff_sync_controls(dsp);
2020 if (ret != 0)
078e7183 2021 goto err_ena;
d8a64d6a 2022
d8a64d6a
CK		 2023 dsp->running = true;
2024
078e7183
CK		 2025 mutex_unlock(&dsp->pwr_lock);
2026
d8a64d6a 2027 return;
6ab2b7b4 2028
078e7183 2029err_ena:
d8a64d6a
CK		 2030 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2031 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
078e7183
CK		 2032err_mutex:
2033 mutex_unlock(&dsp->pwr_lock);
d8a64d6a
CK		 2034}
2035
12db5edd
CK		 2036int wm_adsp2_early_event(struct snd_soc_dapm_widget *w,
2037 struct snd_kcontrol *kcontrol, int event)
2038{
72718517 2039 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
12db5edd
CK		 2040 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
2041 struct wm_adsp *dsp = &dsps[w->shift];
2042
00200107 2043 dsp->card = codec->component.card;
12db5edd
CK		 2044
2045 switch (event) {
2046 case SND_SOC_DAPM_PRE_PMU:
2047 queue_work(system_unbound_wq, &dsp->boot_work);
2048 break;
2049 default:
2050 break;
cab27258 2051 }
12db5edd
CK		 2052
2053 return 0;
2054}
2055EXPORT_SYMBOL_GPL(wm_adsp2_early_event);
2056
d8a64d6a
CK		 2057int wm_adsp2_event(struct snd_soc_dapm_widget *w,
2058 struct snd_kcontrol *kcontrol, int event)
2059{
72718517 2060 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
d8a64d6a
CK		 2061 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
2062 struct wm_adsp *dsp = &dsps[w->shift];
2063 struct wm_adsp_alg_region *alg_region;
2064 struct wm_coeff_ctl *ctl;
2065 int ret;
2066
d8a64d6a
CK		 2067 switch (event) {
2068 case SND_SOC_DAPM_POST_PMU:
d8a64d6a
CK		 2069 flush_work(&dsp->boot_work);
2070
2071 if (!dsp->running)
2072 return -EIO;
6ab2b7b4 2073
d8a64d6a
CK		 2074 ret = regmap_update_bits(dsp->regmap,
2075 dsp->base + ADSP2_CONTROL,
00e4c3b6
CK		 2076 ADSP2_CORE_ENA | ADSP2_START,
2077 ADSP2_CORE_ENA | ADSP2_START);
2159ad93
MB		 2078 if (ret != 0)
2079 goto err;
2080 break;
2081
2082 case SND_SOC_DAPM_PRE_PMD:
10337b07
RF		 2083 /* Log firmware state, it can be useful for analysis */
2084 wm_adsp2_show_fw_status(dsp);
2085
078e7183
CK		 2086 mutex_lock(&dsp->pwr_lock);
2087
f9f55e31
RF		 2088 wm_adsp_debugfs_clear(dsp);
2089
2090 dsp->fw_id = 0;
2091 dsp->fw_id_version = 0;
1023dbd9
MB		 2092 dsp->running = false;
2093
2159ad93 2094 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
a7f9be7e
MB		 2095 ADSP2_SYS_ENA | ADSP2_CORE_ENA |
2096 ADSP2_START, 0);
973838a0 2097
2d30b575
MB		 2098 /* Make sure DMAs are quiesced */
2099 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0);
2100 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0);
2101 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0);
2102
81ad93ec 2103 list_for_each_entry(ctl, &dsp->ctl_list, list)
6ab2b7b4 2104 ctl->enabled = 0;
6ab2b7b4 2105
471f4885
MB		 2106 while (!list_empty(&dsp->alg_regions)) {
2107 alg_region = list_first_entry(&dsp->alg_regions,
2108 struct wm_adsp_alg_region,
2109 list);
2110 list_del(&alg_region->list);
2111 kfree(alg_region);
2112 }
ddbc5efe 2113
078e7183
CK		 2114 mutex_unlock(&dsp->pwr_lock);
2115
ddbc5efe 2116 adsp_dbg(dsp, "Shutdown complete\n");
2159ad93
MB		 2117 break;
2118
2119 default:
2120 break;
2121 }
2122
2123 return 0;
2124err:
2125 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
a7f9be7e 2126 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
2159ad93
MB		 2127 return ret;
2128}
2129EXPORT_SYMBOL_GPL(wm_adsp2_event);
973838a0 2130
f5e2ce92
RF		 2131int wm_adsp2_codec_probe(struct wm_adsp *dsp, struct snd_soc_codec *codec)
2132{
f9f55e31
RF		 2133 wm_adsp2_init_debugfs(dsp, codec);
2134
218e5087 2135 return snd_soc_add_codec_controls(codec,
336d0442
RF		 2136 &wm_adsp_fw_controls[dsp->num - 1],
2137 1);
f5e2ce92
RF		 2138}
2139EXPORT_SYMBOL_GPL(wm_adsp2_codec_probe);
2140
2141int wm_adsp2_codec_remove(struct wm_adsp *dsp, struct snd_soc_codec *codec)
2142{
f9f55e31
RF		 2143 wm_adsp2_cleanup_debugfs(dsp);
2144
f5e2ce92
RF		 2145 return 0;
2146}
2147EXPORT_SYMBOL_GPL(wm_adsp2_codec_remove);
2148
81ac58b1 2149int wm_adsp2_init(struct wm_adsp *dsp)
973838a0
MB		 2150{
2151 int ret;
2152
10a2b662
MB		 2153 /*
2154 * Disable the DSP memory by default when in reset for a small
2155 * power saving.
2156 */
3809f001 2157 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
10a2b662
MB		 2158 ADSP2_MEM_ENA, 0);
2159 if (ret != 0) {
3809f001 2160 adsp_err(dsp, "Failed to clear memory retention: %d\n", ret);
10a2b662
MB		 2161 return ret;
2162 }
2163
3809f001
CK		 2164 INIT_LIST_HEAD(&dsp->alg_regions);
2165 INIT_LIST_HEAD(&dsp->ctl_list);
2166 INIT_WORK(&dsp->boot_work, wm_adsp2_boot_work);
6ab2b7b4 2167
078e7183
CK		 2168 mutex_init(&dsp->pwr_lock);
2169
973838a0
MB		 2170 return 0;
2171}
2172EXPORT_SYMBOL_GPL(wm_adsp2_init);
0a37c6ef
PD		 2173
2174MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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