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2159ad93 MB |
1 | /* |
2 | * wm_adsp.c -- Wolfson ADSP support | |
3 | * | |
4 | * Copyright 2012 Wolfson Microelectronics plc | |
5 | * | |
6 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/module.h> | |
14 | #include <linux/moduleparam.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/firmware.h> | |
18 | #include <linux/pm.h> | |
19 | #include <linux/pm_runtime.h> | |
20 | #include <linux/regmap.h> | |
973838a0 | 21 | #include <linux/regulator/consumer.h> |
2159ad93 MB |
22 | #include <linux/slab.h> |
23 | #include <sound/core.h> | |
24 | #include <sound/pcm.h> | |
25 | #include <sound/pcm_params.h> | |
26 | #include <sound/soc.h> | |
27 | #include <sound/jack.h> | |
28 | #include <sound/initval.h> | |
29 | #include <sound/tlv.h> | |
30 | ||
31 | #include <linux/mfd/arizona/registers.h> | |
32 | ||
33 | #include "wm_adsp.h" | |
34 | ||
35 | #define adsp_crit(_dsp, fmt, ...) \ | |
36 | dev_crit(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__) | |
37 | #define adsp_err(_dsp, fmt, ...) \ | |
38 | dev_err(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__) | |
39 | #define adsp_warn(_dsp, fmt, ...) \ | |
40 | dev_warn(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__) | |
41 | #define adsp_info(_dsp, fmt, ...) \ | |
42 | dev_info(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__) | |
43 | #define adsp_dbg(_dsp, fmt, ...) \ | |
44 | dev_dbg(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__) | |
45 | ||
46 | #define ADSP1_CONTROL_1 0x00 | |
47 | #define ADSP1_CONTROL_2 0x02 | |
48 | #define ADSP1_CONTROL_3 0x03 | |
49 | #define ADSP1_CONTROL_4 0x04 | |
50 | #define ADSP1_CONTROL_5 0x06 | |
51 | #define ADSP1_CONTROL_6 0x07 | |
52 | #define ADSP1_CONTROL_7 0x08 | |
53 | #define ADSP1_CONTROL_8 0x09 | |
54 | #define ADSP1_CONTROL_9 0x0A | |
55 | #define ADSP1_CONTROL_10 0x0B | |
56 | #define ADSP1_CONTROL_11 0x0C | |
57 | #define ADSP1_CONTROL_12 0x0D | |
58 | #define ADSP1_CONTROL_13 0x0F | |
59 | #define ADSP1_CONTROL_14 0x10 | |
60 | #define ADSP1_CONTROL_15 0x11 | |
61 | #define ADSP1_CONTROL_16 0x12 | |
62 | #define ADSP1_CONTROL_17 0x13 | |
63 | #define ADSP1_CONTROL_18 0x14 | |
64 | #define ADSP1_CONTROL_19 0x16 | |
65 | #define ADSP1_CONTROL_20 0x17 | |
66 | #define ADSP1_CONTROL_21 0x18 | |
67 | #define ADSP1_CONTROL_22 0x1A | |
68 | #define ADSP1_CONTROL_23 0x1B | |
69 | #define ADSP1_CONTROL_24 0x1C | |
70 | #define ADSP1_CONTROL_25 0x1E | |
71 | #define ADSP1_CONTROL_26 0x20 | |
72 | #define ADSP1_CONTROL_27 0x21 | |
73 | #define ADSP1_CONTROL_28 0x22 | |
74 | #define ADSP1_CONTROL_29 0x23 | |
75 | #define ADSP1_CONTROL_30 0x24 | |
76 | #define ADSP1_CONTROL_31 0x26 | |
77 | ||
78 | /* | |
79 | * ADSP1 Control 19 | |
80 | */ | |
81 | #define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */ | |
82 | #define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */ | |
83 | #define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */ | |
84 | ||
85 | ||
86 | /* | |
87 | * ADSP1 Control 30 | |
88 | */ | |
89 | #define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */ | |
90 | #define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */ | |
91 | #define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */ | |
92 | #define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */ | |
93 | #define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */ | |
94 | #define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */ | |
95 | #define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */ | |
96 | #define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */ | |
97 | #define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */ | |
98 | #define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */ | |
99 | #define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */ | |
100 | #define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */ | |
101 | #define ADSP1_START 0x0001 /* DSP1_START */ | |
102 | #define ADSP1_START_MASK 0x0001 /* DSP1_START */ | |
103 | #define ADSP1_START_SHIFT 0 /* DSP1_START */ | |
104 | #define ADSP1_START_WIDTH 1 /* DSP1_START */ | |
105 | ||
973838a0 MB |
106 | #define ADSP2_CONTROL 0 |
107 | #define ADSP2_CLOCKING 1 | |
108 | #define ADSP2_STATUS1 4 | |
2159ad93 MB |
109 | |
110 | /* | |
111 | * ADSP2 Control | |
112 | */ | |
113 | ||
114 | #define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */ | |
115 | #define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */ | |
116 | #define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */ | |
117 | #define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */ | |
118 | #define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */ | |
119 | #define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */ | |
120 | #define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */ | |
121 | #define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */ | |
122 | #define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */ | |
123 | #define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */ | |
124 | #define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */ | |
125 | #define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */ | |
126 | #define ADSP2_START 0x0001 /* DSP1_START */ | |
127 | #define ADSP2_START_MASK 0x0001 /* DSP1_START */ | |
128 | #define ADSP2_START_SHIFT 0 /* DSP1_START */ | |
129 | #define ADSP2_START_WIDTH 1 /* DSP1_START */ | |
130 | ||
973838a0 MB |
131 | /* |
132 | * ADSP2 clocking | |
133 | */ | |
134 | #define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */ | |
135 | #define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */ | |
136 | #define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */ | |
137 | ||
2159ad93 MB |
138 | /* |
139 | * ADSP2 Status 1 | |
140 | */ | |
141 | #define ADSP2_RAM_RDY 0x0001 | |
142 | #define ADSP2_RAM_RDY_MASK 0x0001 | |
143 | #define ADSP2_RAM_RDY_SHIFT 0 | |
144 | #define ADSP2_RAM_RDY_WIDTH 1 | |
145 | ||
146 | ||
147 | static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp, | |
148 | int type) | |
149 | { | |
150 | int i; | |
151 | ||
152 | for (i = 0; i < dsp->num_mems; i++) | |
153 | if (dsp->mem[i].type == type) | |
154 | return &dsp->mem[i]; | |
155 | ||
156 | return NULL; | |
157 | } | |
158 | ||
159 | static int wm_adsp_load(struct wm_adsp *dsp) | |
160 | { | |
161 | const struct firmware *firmware; | |
162 | struct regmap *regmap = dsp->regmap; | |
163 | unsigned int pos = 0; | |
164 | const struct wmfw_header *header; | |
165 | const struct wmfw_adsp1_sizes *adsp1_sizes; | |
166 | const struct wmfw_adsp2_sizes *adsp2_sizes; | |
167 | const struct wmfw_footer *footer; | |
168 | const struct wmfw_region *region; | |
169 | const struct wm_adsp_region *mem; | |
170 | const char *region_name; | |
171 | char *file, *text; | |
172 | unsigned int reg; | |
173 | int regions = 0; | |
174 | int ret, offset, type, sizes; | |
175 | ||
176 | file = kzalloc(PAGE_SIZE, GFP_KERNEL); | |
177 | if (file == NULL) | |
178 | return -ENOMEM; | |
179 | ||
180 | snprintf(file, PAGE_SIZE, "%s-dsp%d.wmfw", dsp->part, dsp->num); | |
181 | file[PAGE_SIZE - 1] = '\0'; | |
182 | ||
183 | ret = request_firmware(&firmware, file, dsp->dev); | |
184 | if (ret != 0) { | |
185 | adsp_err(dsp, "Failed to request '%s'\n", file); | |
186 | goto out; | |
187 | } | |
188 | ret = -EINVAL; | |
189 | ||
190 | pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer); | |
191 | if (pos >= firmware->size) { | |
192 | adsp_err(dsp, "%s: file too short, %zu bytes\n", | |
193 | file, firmware->size); | |
194 | goto out_fw; | |
195 | } | |
196 | ||
197 | header = (void*)&firmware->data[0]; | |
198 | ||
199 | if (memcmp(&header->magic[0], "WMFW", 4) != 0) { | |
200 | adsp_err(dsp, "%s: invalid magic\n", file); | |
201 | goto out_fw; | |
202 | } | |
203 | ||
204 | if (header->ver != 0) { | |
205 | adsp_err(dsp, "%s: unknown file format %d\n", | |
206 | file, header->ver); | |
207 | goto out_fw; | |
208 | } | |
209 | ||
210 | if (header->core != dsp->type) { | |
211 | adsp_err(dsp, "%s: invalid core %d != %d\n", | |
212 | file, header->core, dsp->type); | |
213 | goto out_fw; | |
214 | } | |
215 | ||
216 | switch (dsp->type) { | |
217 | case WMFW_ADSP1: | |
218 | pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer); | |
219 | adsp1_sizes = (void *)&(header[1]); | |
220 | footer = (void *)&(adsp1_sizes[1]); | |
221 | sizes = sizeof(*adsp1_sizes); | |
222 | ||
223 | adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n", | |
224 | file, le32_to_cpu(adsp1_sizes->dm), | |
225 | le32_to_cpu(adsp1_sizes->pm), | |
226 | le32_to_cpu(adsp1_sizes->zm)); | |
227 | break; | |
228 | ||
229 | case WMFW_ADSP2: | |
230 | pos = sizeof(*header) + sizeof(*adsp2_sizes) + sizeof(*footer); | |
231 | adsp2_sizes = (void *)&(header[1]); | |
232 | footer = (void *)&(adsp2_sizes[1]); | |
233 | sizes = sizeof(*adsp2_sizes); | |
234 | ||
235 | adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n", | |
236 | file, le32_to_cpu(adsp2_sizes->xm), | |
237 | le32_to_cpu(adsp2_sizes->ym), | |
238 | le32_to_cpu(adsp2_sizes->pm), | |
239 | le32_to_cpu(adsp2_sizes->zm)); | |
240 | break; | |
241 | ||
242 | default: | |
243 | BUG_ON(NULL == "Unknown DSP type"); | |
244 | goto out_fw; | |
245 | } | |
246 | ||
247 | if (le32_to_cpu(header->len) != sizeof(*header) + | |
248 | sizes + sizeof(*footer)) { | |
249 | adsp_err(dsp, "%s: unexpected header length %d\n", | |
250 | file, le32_to_cpu(header->len)); | |
251 | goto out_fw; | |
252 | } | |
253 | ||
254 | adsp_dbg(dsp, "%s: timestamp %llu\n", file, | |
255 | le64_to_cpu(footer->timestamp)); | |
256 | ||
257 | while (pos < firmware->size && | |
258 | pos - firmware->size > sizeof(*region)) { | |
259 | region = (void *)&(firmware->data[pos]); | |
260 | region_name = "Unknown"; | |
261 | reg = 0; | |
262 | text = NULL; | |
263 | offset = le32_to_cpu(region->offset) & 0xffffff; | |
264 | type = be32_to_cpu(region->type) & 0xff; | |
265 | mem = wm_adsp_find_region(dsp, type); | |
266 | ||
267 | switch (type) { | |
268 | case WMFW_NAME_TEXT: | |
269 | region_name = "Firmware name"; | |
270 | text = kzalloc(le32_to_cpu(region->len) + 1, | |
271 | GFP_KERNEL); | |
272 | break; | |
273 | case WMFW_INFO_TEXT: | |
274 | region_name = "Information"; | |
275 | text = kzalloc(le32_to_cpu(region->len) + 1, | |
276 | GFP_KERNEL); | |
277 | break; | |
278 | case WMFW_ABSOLUTE: | |
279 | region_name = "Absolute"; | |
280 | reg = offset; | |
281 | break; | |
282 | case WMFW_ADSP1_PM: | |
283 | BUG_ON(!mem); | |
284 | region_name = "PM"; | |
285 | reg = mem->base + (offset * 3); | |
286 | break; | |
287 | case WMFW_ADSP1_DM: | |
288 | BUG_ON(!mem); | |
289 | region_name = "DM"; | |
290 | reg = mem->base + (offset * 2); | |
291 | break; | |
292 | case WMFW_ADSP2_XM: | |
293 | BUG_ON(!mem); | |
294 | region_name = "XM"; | |
295 | reg = mem->base + (offset * 2); | |
296 | break; | |
297 | case WMFW_ADSP2_YM: | |
298 | BUG_ON(!mem); | |
299 | region_name = "YM"; | |
300 | reg = mem->base + (offset * 2); | |
301 | break; | |
302 | case WMFW_ADSP1_ZM: | |
303 | BUG_ON(!mem); | |
304 | region_name = "ZM"; | |
305 | reg = mem->base + (offset * 2); | |
306 | break; | |
307 | default: | |
308 | adsp_warn(dsp, | |
309 | "%s.%d: Unknown region type %x at %d(%x)\n", | |
310 | file, regions, type, pos, pos); | |
311 | break; | |
312 | } | |
313 | ||
314 | adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file, | |
315 | regions, le32_to_cpu(region->len), offset, | |
316 | region_name); | |
317 | ||
318 | if (text) { | |
319 | memcpy(text, region->data, le32_to_cpu(region->len)); | |
320 | adsp_info(dsp, "%s: %s\n", file, text); | |
321 | kfree(text); | |
322 | } | |
323 | ||
324 | if (reg) { | |
325 | ret = regmap_raw_write(regmap, reg, region->data, | |
326 | le32_to_cpu(region->len)); | |
327 | if (ret != 0) { | |
328 | adsp_err(dsp, | |
329 | "%s.%d: Failed to write %d bytes at %d in %s: %d\n", | |
330 | file, regions, | |
331 | le32_to_cpu(region->len), offset, | |
332 | region_name, ret); | |
333 | goto out_fw; | |
334 | } | |
335 | } | |
336 | ||
337 | pos += le32_to_cpu(region->len) + sizeof(*region); | |
338 | regions++; | |
339 | } | |
340 | ||
341 | if (pos > firmware->size) | |
342 | adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n", | |
343 | file, regions, pos - firmware->size); | |
344 | ||
345 | out_fw: | |
346 | release_firmware(firmware); | |
347 | out: | |
348 | kfree(file); | |
349 | ||
350 | return ret; | |
351 | } | |
352 | ||
db40517c MB |
353 | static int wm_adsp_setup_algs(struct wm_adsp *dsp) |
354 | { | |
355 | struct regmap *regmap = dsp->regmap; | |
356 | struct wmfw_adsp1_id_hdr adsp1_id; | |
357 | struct wmfw_adsp2_id_hdr adsp2_id; | |
358 | struct wmfw_adsp1_alg_hdr *adsp1_alg; | |
359 | struct wmfw_adsp2_alg_hdr *adsp2_alg; | |
360 | void *alg; | |
361 | const struct wm_adsp_region *mem; | |
362 | unsigned int pos, term; | |
363 | size_t algs; | |
364 | __be32 val; | |
365 | int i, ret; | |
366 | ||
367 | switch (dsp->type) { | |
368 | case WMFW_ADSP1: | |
369 | mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM); | |
370 | break; | |
371 | case WMFW_ADSP2: | |
372 | mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM); | |
373 | break; | |
374 | default: | |
375 | mem = NULL; | |
376 | break; | |
377 | } | |
378 | ||
379 | if (mem == NULL) { | |
380 | BUG_ON(mem != NULL); | |
381 | return -EINVAL; | |
382 | } | |
383 | ||
384 | switch (dsp->type) { | |
385 | case WMFW_ADSP1: | |
386 | ret = regmap_raw_read(regmap, mem->base, &adsp1_id, | |
387 | sizeof(adsp1_id)); | |
388 | if (ret != 0) { | |
389 | adsp_err(dsp, "Failed to read algorithm info: %d\n", | |
390 | ret); | |
391 | return ret; | |
392 | } | |
393 | ||
394 | algs = be32_to_cpu(adsp1_id.algs); | |
395 | adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n", | |
396 | be32_to_cpu(adsp1_id.fw.id), | |
397 | (be32_to_cpu(adsp1_id.fw.ver) & 0xff0000) >> 16, | |
398 | (be32_to_cpu(adsp1_id.fw.ver) & 0xff00) >> 8, | |
399 | be32_to_cpu(adsp1_id.fw.ver) & 0xff, | |
400 | algs); | |
401 | ||
402 | pos = sizeof(adsp1_id) / 2; | |
403 | term = pos + ((sizeof(*adsp1_alg) * algs) / 2); | |
404 | break; | |
405 | ||
406 | case WMFW_ADSP2: | |
407 | ret = regmap_raw_read(regmap, mem->base, &adsp2_id, | |
408 | sizeof(adsp2_id)); | |
409 | if (ret != 0) { | |
410 | adsp_err(dsp, "Failed to read algorithm info: %d\n", | |
411 | ret); | |
412 | return ret; | |
413 | } | |
414 | ||
415 | algs = be32_to_cpu(adsp2_id.algs); | |
416 | adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n", | |
417 | be32_to_cpu(adsp2_id.fw.id), | |
418 | (be32_to_cpu(adsp2_id.fw.ver) & 0xff0000) >> 16, | |
419 | (be32_to_cpu(adsp2_id.fw.ver) & 0xff00) >> 8, | |
420 | be32_to_cpu(adsp2_id.fw.ver) & 0xff, | |
421 | algs); | |
422 | ||
423 | pos = sizeof(adsp2_id) / 2; | |
424 | term = pos + ((sizeof(*adsp2_alg) * algs) / 2); | |
425 | break; | |
426 | ||
427 | default: | |
428 | BUG_ON(NULL == "Unknown DSP type"); | |
429 | return -EINVAL; | |
430 | } | |
431 | ||
432 | if (algs == 0) { | |
433 | adsp_err(dsp, "No algorithms\n"); | |
434 | return -EINVAL; | |
435 | } | |
436 | ||
437 | /* Read the terminator first to validate the length */ | |
438 | ret = regmap_raw_read(regmap, mem->base + term, &val, sizeof(val)); | |
439 | if (ret != 0) { | |
440 | adsp_err(dsp, "Failed to read algorithm list end: %d\n", | |
441 | ret); | |
442 | return ret; | |
443 | } | |
444 | ||
445 | if (be32_to_cpu(val) != 0xbedead) | |
446 | adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbeadead\n", | |
447 | term, be32_to_cpu(val)); | |
448 | ||
449 | alg = kzalloc((term - pos) * 2, GFP_KERNEL); | |
450 | if (!alg) | |
451 | return -ENOMEM; | |
452 | ||
453 | ret = regmap_raw_read(regmap, mem->base + pos, alg, (term - pos) * 2); | |
454 | if (ret != 0) { | |
455 | adsp_err(dsp, "Failed to read algorithm list: %d\n", | |
456 | ret); | |
457 | goto out; | |
458 | } | |
459 | ||
460 | adsp1_alg = alg; | |
461 | adsp2_alg = alg; | |
462 | ||
463 | for (i = 0; i < algs; i++) { | |
464 | switch (dsp->type) { | |
465 | case WMFW_ADSP1: | |
466 | adsp_info(dsp, "%d: ID %x v%d.%d.%d\n", | |
467 | i, be32_to_cpu(adsp1_alg[i].alg.id), | |
468 | (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16, | |
469 | (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8, | |
470 | be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff); | |
471 | break; | |
472 | ||
473 | case WMFW_ADSP2: | |
474 | adsp_info(dsp, "%d: ID %x v%d.%d.%d\n", | |
475 | i, be32_to_cpu(adsp2_alg[i].alg.id), | |
476 | (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16, | |
477 | (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8, | |
478 | be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff); | |
479 | break; | |
480 | } | |
481 | } | |
482 | ||
483 | out: | |
484 | kfree(alg); | |
485 | return ret; | |
486 | } | |
487 | ||
2159ad93 MB |
488 | static int wm_adsp_load_coeff(struct wm_adsp *dsp) |
489 | { | |
490 | struct regmap *regmap = dsp->regmap; | |
491 | struct wmfw_coeff_hdr *hdr; | |
492 | struct wmfw_coeff_item *blk; | |
493 | const struct firmware *firmware; | |
494 | const char *region_name; | |
495 | int ret, pos, blocks, type, offset, reg; | |
496 | char *file; | |
497 | ||
498 | file = kzalloc(PAGE_SIZE, GFP_KERNEL); | |
499 | if (file == NULL) | |
500 | return -ENOMEM; | |
501 | ||
502 | snprintf(file, PAGE_SIZE, "%s-dsp%d.bin", dsp->part, dsp->num); | |
503 | file[PAGE_SIZE - 1] = '\0'; | |
504 | ||
505 | ret = request_firmware(&firmware, file, dsp->dev); | |
506 | if (ret != 0) { | |
507 | adsp_warn(dsp, "Failed to request '%s'\n", file); | |
508 | ret = 0; | |
509 | goto out; | |
510 | } | |
511 | ret = -EINVAL; | |
512 | ||
513 | if (sizeof(*hdr) >= firmware->size) { | |
514 | adsp_err(dsp, "%s: file too short, %zu bytes\n", | |
515 | file, firmware->size); | |
516 | goto out_fw; | |
517 | } | |
518 | ||
519 | hdr = (void*)&firmware->data[0]; | |
520 | if (memcmp(hdr->magic, "WMDR", 4) != 0) { | |
521 | adsp_err(dsp, "%s: invalid magic\n", file); | |
522 | return -EINVAL; | |
523 | } | |
524 | ||
525 | adsp_dbg(dsp, "%s: v%d.%d.%d\n", file, | |
526 | (le32_to_cpu(hdr->ver) >> 16) & 0xff, | |
527 | (le32_to_cpu(hdr->ver) >> 8) & 0xff, | |
528 | le32_to_cpu(hdr->ver) & 0xff); | |
529 | ||
530 | pos = le32_to_cpu(hdr->len); | |
531 | ||
532 | blocks = 0; | |
533 | while (pos < firmware->size && | |
534 | pos - firmware->size > sizeof(*blk)) { | |
535 | blk = (void*)(&firmware->data[pos]); | |
536 | ||
537 | type = be32_to_cpu(blk->type) & 0xff; | |
538 | offset = le32_to_cpu(blk->offset) & 0xffffff; | |
539 | ||
540 | adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n", | |
541 | file, blocks, le32_to_cpu(blk->id), | |
542 | (le32_to_cpu(blk->ver) >> 16) & 0xff, | |
543 | (le32_to_cpu(blk->ver) >> 8) & 0xff, | |
544 | le32_to_cpu(blk->ver) & 0xff); | |
545 | adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n", | |
546 | file, blocks, le32_to_cpu(blk->len), offset, type); | |
547 | ||
548 | reg = 0; | |
549 | region_name = "Unknown"; | |
550 | switch (type) { | |
551 | case WMFW_NAME_TEXT: | |
552 | case WMFW_INFO_TEXT: | |
553 | break; | |
554 | case WMFW_ABSOLUTE: | |
555 | region_name = "register"; | |
556 | reg = offset; | |
557 | break; | |
558 | default: | |
559 | adsp_err(dsp, "Unknown region type %x\n", type); | |
560 | break; | |
561 | } | |
562 | ||
563 | if (reg) { | |
564 | ret = regmap_raw_write(regmap, reg, blk->data, | |
565 | le32_to_cpu(blk->len)); | |
566 | if (ret != 0) { | |
567 | adsp_err(dsp, | |
568 | "%s.%d: Failed to write to %x in %s\n", | |
569 | file, blocks, reg, region_name); | |
570 | } | |
571 | } | |
572 | ||
573 | pos += le32_to_cpu(blk->len) + sizeof(*blk); | |
574 | blocks++; | |
575 | } | |
576 | ||
577 | if (pos > firmware->size) | |
578 | adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n", | |
579 | file, blocks, pos - firmware->size); | |
580 | ||
581 | out_fw: | |
582 | release_firmware(firmware); | |
583 | out: | |
584 | kfree(file); | |
585 | return 0; | |
586 | } | |
587 | ||
588 | int wm_adsp1_event(struct snd_soc_dapm_widget *w, | |
589 | struct snd_kcontrol *kcontrol, | |
590 | int event) | |
591 | { | |
592 | struct snd_soc_codec *codec = w->codec; | |
593 | struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec); | |
594 | struct wm_adsp *dsp = &dsps[w->shift]; | |
595 | int ret; | |
596 | ||
597 | switch (event) { | |
598 | case SND_SOC_DAPM_POST_PMU: | |
599 | regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, | |
600 | ADSP1_SYS_ENA, ADSP1_SYS_ENA); | |
601 | ||
602 | ret = wm_adsp_load(dsp); | |
603 | if (ret != 0) | |
604 | goto err; | |
605 | ||
db40517c MB |
606 | ret = wm_adsp_setup_algs(dsp); |
607 | if (ret != 0) | |
608 | goto err; | |
609 | ||
2159ad93 MB |
610 | ret = wm_adsp_load_coeff(dsp); |
611 | if (ret != 0) | |
612 | goto err; | |
613 | ||
614 | /* Start the core running */ | |
615 | regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, | |
616 | ADSP1_CORE_ENA | ADSP1_START, | |
617 | ADSP1_CORE_ENA | ADSP1_START); | |
618 | break; | |
619 | ||
620 | case SND_SOC_DAPM_PRE_PMD: | |
621 | /* Halt the core */ | |
622 | regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, | |
623 | ADSP1_CORE_ENA | ADSP1_START, 0); | |
624 | ||
625 | regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19, | |
626 | ADSP1_WDMA_BUFFER_LENGTH_MASK, 0); | |
627 | ||
628 | regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, | |
629 | ADSP1_SYS_ENA, 0); | |
630 | break; | |
631 | ||
632 | default: | |
633 | break; | |
634 | } | |
635 | ||
636 | return 0; | |
637 | ||
638 | err: | |
639 | regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, | |
640 | ADSP1_SYS_ENA, 0); | |
641 | return ret; | |
642 | } | |
643 | EXPORT_SYMBOL_GPL(wm_adsp1_event); | |
644 | ||
645 | static int wm_adsp2_ena(struct wm_adsp *dsp) | |
646 | { | |
647 | unsigned int val; | |
648 | int ret, count; | |
649 | ||
650 | ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, | |
651 | ADSP2_SYS_ENA, ADSP2_SYS_ENA); | |
652 | if (ret != 0) | |
653 | return ret; | |
654 | ||
655 | /* Wait for the RAM to start, should be near instantaneous */ | |
656 | count = 0; | |
657 | do { | |
658 | ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1, | |
659 | &val); | |
660 | if (ret != 0) | |
661 | return ret; | |
662 | } while (!(val & ADSP2_RAM_RDY) && ++count < 10); | |
663 | ||
664 | if (!(val & ADSP2_RAM_RDY)) { | |
665 | adsp_err(dsp, "Failed to start DSP RAM\n"); | |
666 | return -EBUSY; | |
667 | } | |
668 | ||
669 | adsp_dbg(dsp, "RAM ready after %d polls\n", count); | |
670 | adsp_info(dsp, "RAM ready after %d polls\n", count); | |
671 | ||
672 | return 0; | |
673 | } | |
674 | ||
675 | int wm_adsp2_event(struct snd_soc_dapm_widget *w, | |
676 | struct snd_kcontrol *kcontrol, int event) | |
677 | { | |
678 | struct snd_soc_codec *codec = w->codec; | |
679 | struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec); | |
680 | struct wm_adsp *dsp = &dsps[w->shift]; | |
973838a0 | 681 | unsigned int val; |
2159ad93 MB |
682 | int ret; |
683 | ||
684 | switch (event) { | |
685 | case SND_SOC_DAPM_POST_PMU: | |
dd49e2c8 MB |
686 | /* |
687 | * For simplicity set the DSP clock rate to be the | |
688 | * SYSCLK rate rather than making it configurable. | |
689 | */ | |
690 | ret = regmap_read(dsp->regmap, ARIZONA_SYSTEM_CLOCK_1, &val); | |
691 | if (ret != 0) { | |
692 | adsp_err(dsp, "Failed to read SYSCLK state: %d\n", | |
693 | ret); | |
694 | return ret; | |
695 | } | |
696 | val = (val & ARIZONA_SYSCLK_FREQ_MASK) | |
697 | >> ARIZONA_SYSCLK_FREQ_SHIFT; | |
698 | ||
699 | ret = regmap_update_bits(dsp->regmap, | |
700 | dsp->base + ADSP2_CLOCKING, | |
701 | ADSP2_CLK_SEL_MASK, val); | |
702 | if (ret != 0) { | |
703 | adsp_err(dsp, "Failed to set clock rate: %d\n", | |
704 | ret); | |
705 | return ret; | |
706 | } | |
707 | ||
973838a0 MB |
708 | if (dsp->dvfs) { |
709 | ret = regmap_read(dsp->regmap, | |
710 | dsp->base + ADSP2_CLOCKING, &val); | |
711 | if (ret != 0) { | |
712 | dev_err(dsp->dev, | |
713 | "Failed to read clocking: %d\n", ret); | |
714 | return ret; | |
715 | } | |
716 | ||
25c6fdb0 | 717 | if ((val & ADSP2_CLK_SEL_MASK) >= 3) { |
973838a0 MB |
718 | ret = regulator_enable(dsp->dvfs); |
719 | if (ret != 0) { | |
720 | dev_err(dsp->dev, | |
721 | "Failed to enable supply: %d\n", | |
722 | ret); | |
723 | return ret; | |
724 | } | |
725 | ||
726 | ret = regulator_set_voltage(dsp->dvfs, | |
727 | 1800000, | |
728 | 1800000); | |
729 | if (ret != 0) { | |
730 | dev_err(dsp->dev, | |
731 | "Failed to raise supply: %d\n", | |
732 | ret); | |
733 | return ret; | |
734 | } | |
735 | } | |
736 | } | |
737 | ||
2159ad93 MB |
738 | ret = wm_adsp2_ena(dsp); |
739 | if (ret != 0) | |
740 | return ret; | |
741 | ||
742 | ret = wm_adsp_load(dsp); | |
743 | if (ret != 0) | |
744 | goto err; | |
745 | ||
db40517c MB |
746 | ret = wm_adsp_setup_algs(dsp); |
747 | if (ret != 0) | |
748 | goto err; | |
749 | ||
2159ad93 MB |
750 | ret = wm_adsp_load_coeff(dsp); |
751 | if (ret != 0) | |
752 | goto err; | |
753 | ||
754 | ret = regmap_update_bits(dsp->regmap, | |
755 | dsp->base + ADSP2_CONTROL, | |
a7f9be7e MB |
756 | ADSP2_CORE_ENA | ADSP2_START, |
757 | ADSP2_CORE_ENA | ADSP2_START); | |
2159ad93 MB |
758 | if (ret != 0) |
759 | goto err; | |
760 | break; | |
761 | ||
762 | case SND_SOC_DAPM_PRE_PMD: | |
763 | regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, | |
a7f9be7e MB |
764 | ADSP2_SYS_ENA | ADSP2_CORE_ENA | |
765 | ADSP2_START, 0); | |
973838a0 MB |
766 | |
767 | if (dsp->dvfs) { | |
768 | ret = regulator_set_voltage(dsp->dvfs, 1200000, | |
769 | 1800000); | |
770 | if (ret != 0) | |
771 | dev_warn(dsp->dev, | |
772 | "Failed to lower supply: %d\n", | |
773 | ret); | |
774 | ||
775 | ret = regulator_disable(dsp->dvfs); | |
776 | if (ret != 0) | |
777 | dev_err(dsp->dev, | |
778 | "Failed to enable supply: %d\n", | |
779 | ret); | |
780 | } | |
2159ad93 MB |
781 | break; |
782 | ||
783 | default: | |
784 | break; | |
785 | } | |
786 | ||
787 | return 0; | |
788 | err: | |
789 | regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, | |
a7f9be7e | 790 | ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0); |
2159ad93 MB |
791 | return ret; |
792 | } | |
793 | EXPORT_SYMBOL_GPL(wm_adsp2_event); | |
973838a0 MB |
794 | |
795 | int wm_adsp2_init(struct wm_adsp *adsp, bool dvfs) | |
796 | { | |
797 | int ret; | |
798 | ||
10a2b662 MB |
799 | /* |
800 | * Disable the DSP memory by default when in reset for a small | |
801 | * power saving. | |
802 | */ | |
803 | ret = regmap_update_bits(adsp->regmap, adsp->base + ADSP2_CONTROL, | |
804 | ADSP2_MEM_ENA, 0); | |
805 | if (ret != 0) { | |
806 | adsp_err(adsp, "Failed to clear memory retention: %d\n", ret); | |
807 | return ret; | |
808 | } | |
809 | ||
973838a0 MB |
810 | if (dvfs) { |
811 | adsp->dvfs = devm_regulator_get(adsp->dev, "DCVDD"); | |
812 | if (IS_ERR(adsp->dvfs)) { | |
813 | ret = PTR_ERR(adsp->dvfs); | |
814 | dev_err(adsp->dev, "Failed to get DCVDD: %d\n", ret); | |
815 | return ret; | |
816 | } | |
817 | ||
818 | ret = regulator_enable(adsp->dvfs); | |
819 | if (ret != 0) { | |
820 | dev_err(adsp->dev, "Failed to enable DCVDD: %d\n", | |
821 | ret); | |
822 | return ret; | |
823 | } | |
824 | ||
825 | ret = regulator_set_voltage(adsp->dvfs, 1200000, 1800000); | |
826 | if (ret != 0) { | |
827 | dev_err(adsp->dev, "Failed to initialise DVFS: %d\n", | |
828 | ret); | |
829 | return ret; | |
830 | } | |
831 | ||
832 | ret = regulator_disable(adsp->dvfs); | |
833 | if (ret != 0) { | |
834 | dev_err(adsp->dev, "Failed to disable DCVDD: %d\n", | |
835 | ret); | |
836 | return ret; | |
837 | } | |
838 | } | |
839 | ||
840 | return 0; | |
841 | } | |
842 | EXPORT_SYMBOL_GPL(wm_adsp2_init); |