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310355c1 VB |
1 | /* |
2 | * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor | |
3 | * | |
d6b52039 | 4 | * Author: Vladimir Barinov, <vbarinov@embeddedalley.com> |
310355c1 VB |
5 | * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com> |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/init.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/device.h> | |
5a0e3ad6 | 15 | #include <linux/slab.h> |
310355c1 VB |
16 | #include <linux/delay.h> |
17 | #include <linux/io.h> | |
18 | #include <linux/clk.h> | |
896f66b7 | 19 | #include <linux/platform_data/davinci_asp.h> |
310355c1 VB |
20 | |
21 | #include <sound/core.h> | |
22 | #include <sound/pcm.h> | |
23 | #include <sound/pcm_params.h> | |
24 | #include <sound/initval.h> | |
25 | #include <sound/soc.h> | |
257ade78 | 26 | #include <sound/dmaengine_pcm.h> |
310355c1 | 27 | |
257ade78 | 28 | #include "edma-pcm.h" |
a4c8ea2d | 29 | #include "davinci-i2s.h" |
310355c1 | 30 | |
a62114cb DB |
31 | |
32 | /* | |
33 | * NOTE: terminology here is confusing. | |
34 | * | |
35 | * - This driver supports the "Audio Serial Port" (ASP), | |
36 | * found on dm6446, dm355, and other DaVinci chips. | |
37 | * | |
38 | * - But it labels it a "Multi-channel Buffered Serial Port" | |
39 | * (McBSP) as on older chips like the dm642 ... which was | |
40 | * backward-compatible, possibly explaining that confusion. | |
41 | * | |
42 | * - OMAP chips have a controller called McBSP, which is | |
43 | * incompatible with the DaVinci flavor of McBSP. | |
44 | * | |
45 | * - Newer DaVinci chips have a controller called McASP, | |
46 | * incompatible with ASP and with either McBSP. | |
47 | * | |
48 | * In short: this uses ASP to implement I2S, not McBSP. | |
49 | * And it won't be the only DaVinci implemention of I2S. | |
50 | */ | |
310355c1 VB |
51 | #define DAVINCI_MCBSP_DRR_REG 0x00 |
52 | #define DAVINCI_MCBSP_DXR_REG 0x04 | |
53 | #define DAVINCI_MCBSP_SPCR_REG 0x08 | |
54 | #define DAVINCI_MCBSP_RCR_REG 0x0c | |
55 | #define DAVINCI_MCBSP_XCR_REG 0x10 | |
56 | #define DAVINCI_MCBSP_SRGR_REG 0x14 | |
57 | #define DAVINCI_MCBSP_PCR_REG 0x24 | |
58 | ||
59 | #define DAVINCI_MCBSP_SPCR_RRST (1 << 0) | |
60 | #define DAVINCI_MCBSP_SPCR_RINTM(v) ((v) << 4) | |
61 | #define DAVINCI_MCBSP_SPCR_XRST (1 << 16) | |
62 | #define DAVINCI_MCBSP_SPCR_XINTM(v) ((v) << 20) | |
63 | #define DAVINCI_MCBSP_SPCR_GRST (1 << 22) | |
64 | #define DAVINCI_MCBSP_SPCR_FRST (1 << 23) | |
65 | #define DAVINCI_MCBSP_SPCR_FREE (1 << 25) | |
66 | ||
67 | #define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5) | |
68 | #define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8) | |
69 | #define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16) | |
f5cfa954 | 70 | #define DAVINCI_MCBSP_RCR_RFIG (1 << 18) |
310355c1 | 71 | #define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21) |
a4c8ea2d RR |
72 | #define DAVINCI_MCBSP_RCR_RFRLEN2(v) ((v) << 24) |
73 | #define DAVINCI_MCBSP_RCR_RPHASE BIT(31) | |
310355c1 VB |
74 | |
75 | #define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5) | |
76 | #define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8) | |
77 | #define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16) | |
78 | #define DAVINCI_MCBSP_XCR_XFIG (1 << 18) | |
79 | #define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21) | |
a4c8ea2d RR |
80 | #define DAVINCI_MCBSP_XCR_XFRLEN2(v) ((v) << 24) |
81 | #define DAVINCI_MCBSP_XCR_XPHASE BIT(31) | |
310355c1 VB |
82 | |
83 | #define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8) | |
84 | #define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16) | |
85 | #define DAVINCI_MCBSP_SRGR_FSGM (1 << 28) | |
a4c8ea2d | 86 | #define DAVINCI_MCBSP_SRGR_CLKSM BIT(29) |
310355c1 VB |
87 | |
88 | #define DAVINCI_MCBSP_PCR_CLKRP (1 << 0) | |
89 | #define DAVINCI_MCBSP_PCR_CLKXP (1 << 1) | |
90 | #define DAVINCI_MCBSP_PCR_FSRP (1 << 2) | |
91 | #define DAVINCI_MCBSP_PCR_FSXP (1 << 3) | |
b402dff8 | 92 | #define DAVINCI_MCBSP_PCR_SCLKME (1 << 7) |
310355c1 VB |
93 | #define DAVINCI_MCBSP_PCR_CLKRM (1 << 8) |
94 | #define DAVINCI_MCBSP_PCR_CLKXM (1 << 9) | |
95 | #define DAVINCI_MCBSP_PCR_FSRM (1 << 10) | |
96 | #define DAVINCI_MCBSP_PCR_FSXM (1 << 11) | |
97 | ||
310355c1 VB |
98 | enum { |
99 | DAVINCI_MCBSP_WORD_8 = 0, | |
100 | DAVINCI_MCBSP_WORD_12, | |
101 | DAVINCI_MCBSP_WORD_16, | |
102 | DAVINCI_MCBSP_WORD_20, | |
103 | DAVINCI_MCBSP_WORD_24, | |
104 | DAVINCI_MCBSP_WORD_32, | |
105 | }; | |
106 | ||
0d6c9774 TK |
107 | static const unsigned char data_type[SNDRV_PCM_FORMAT_S32_LE + 1] = { |
108 | [SNDRV_PCM_FORMAT_S8] = 1, | |
109 | [SNDRV_PCM_FORMAT_S16_LE] = 2, | |
110 | [SNDRV_PCM_FORMAT_S32_LE] = 4, | |
111 | }; | |
112 | ||
113 | static const unsigned char asp_word_length[SNDRV_PCM_FORMAT_S32_LE + 1] = { | |
114 | [SNDRV_PCM_FORMAT_S8] = DAVINCI_MCBSP_WORD_8, | |
115 | [SNDRV_PCM_FORMAT_S16_LE] = DAVINCI_MCBSP_WORD_16, | |
116 | [SNDRV_PCM_FORMAT_S32_LE] = DAVINCI_MCBSP_WORD_32, | |
117 | }; | |
118 | ||
119 | static const unsigned char double_fmt[SNDRV_PCM_FORMAT_S32_LE + 1] = { | |
120 | [SNDRV_PCM_FORMAT_S8] = SNDRV_PCM_FORMAT_S16_LE, | |
121 | [SNDRV_PCM_FORMAT_S16_LE] = SNDRV_PCM_FORMAT_S32_LE, | |
122 | }; | |
123 | ||
310355c1 | 124 | struct davinci_mcbsp_dev { |
ec637553 | 125 | struct device *dev; |
257ade78 PU |
126 | struct snd_dmaengine_dai_dma_data dma_data[2]; |
127 | int dma_request[2]; | |
310355c1 | 128 | void __iomem *base; |
f5cfa954 TK |
129 | #define MOD_DSP_A 0 |
130 | #define MOD_DSP_B 1 | |
131 | int mode; | |
c392bec7 | 132 | u32 pcr; |
310355c1 | 133 | struct clk *clk; |
0d6c9774 TK |
134 | /* |
135 | * Combining both channels into 1 element will at least double the | |
136 | * amount of time between servicing the dma channel, increase | |
137 | * effiency, and reduce the chance of overrun/underrun. But, | |
138 | * it will result in the left & right channels being swapped. | |
139 | * | |
140 | * If relabeling the left and right channels is not possible, | |
141 | * you may want to let the codec know to swap them back. | |
142 | * | |
143 | * It may allow x10 the amount of time to service dma requests, | |
144 | * if the codec is master and is using an unnecessarily fast bit clock | |
145 | * (ie. tlvaic23b), independent of the sample rate. So, having an | |
146 | * entire frame at once means it can be serviced at the sample rate | |
147 | * instead of the bit clock rate. | |
148 | * | |
149 | * In the now unlikely case that an underrun still | |
150 | * occurs, both the left and right samples will be repeated | |
151 | * so that no pops are heard, and the left and right channels | |
152 | * won't end up being swapped because of the underrun. | |
153 | */ | |
154 | unsigned enable_channel_combine:1; | |
a4c8ea2d RR |
155 | |
156 | unsigned int fmt; | |
157 | int clk_div; | |
ec637553 | 158 | int clk_input_pin; |
d9823ed9 | 159 | bool i2s_accurate_sck; |
310355c1 VB |
160 | }; |
161 | ||
162 | static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev, | |
163 | int reg, u32 val) | |
164 | { | |
165 | __raw_writel(val, dev->base + reg); | |
166 | } | |
167 | ||
168 | static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg) | |
169 | { | |
170 | return __raw_readl(dev->base + reg); | |
171 | } | |
172 | ||
c392bec7 TK |
173 | static void toggle_clock(struct davinci_mcbsp_dev *dev, int playback) |
174 | { | |
175 | u32 m = playback ? DAVINCI_MCBSP_PCR_CLKXP : DAVINCI_MCBSP_PCR_CLKRP; | |
176 | /* The clock needs to toggle to complete reset. | |
177 | * So, fake it by toggling the clk polarity. | |
178 | */ | |
179 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr ^ m); | |
180 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr); | |
181 | } | |
182 | ||
f9af37cc TK |
183 | static void davinci_mcbsp_start(struct davinci_mcbsp_dev *dev, |
184 | struct snd_pcm_substream *substream) | |
310355c1 VB |
185 | { |
186 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 187 | struct snd_soc_platform *platform = rtd->platform; |
c392bec7 | 188 | int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); |
35cf6358 | 189 | u32 spcr; |
c392bec7 | 190 | u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST; |
35cf6358 | 191 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
c392bec7 TK |
192 | if (spcr & mask) { |
193 | /* start off disabled */ | |
194 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, | |
195 | spcr & ~mask); | |
196 | toggle_clock(dev, playback); | |
197 | } | |
1bef4499 TK |
198 | if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM | |
199 | DAVINCI_MCBSP_PCR_CLKXM | DAVINCI_MCBSP_PCR_CLKRM)) { | |
200 | /* Start the sample generator */ | |
201 | spcr |= DAVINCI_MCBSP_SPCR_GRST; | |
202 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); | |
203 | } | |
fb0ef645 | 204 | |
1bef4499 | 205 | if (playback) { |
fb0ef645 NM |
206 | /* Stop the DMA to avoid data loss */ |
207 | /* while the transmitter is out of reset to handle XSYNCERR */ | |
f0fba2ad LG |
208 | if (platform->driver->ops->trigger) { |
209 | int ret = platform->driver->ops->trigger(substream, | |
fb0ef645 NM |
210 | SNDRV_PCM_TRIGGER_STOP); |
211 | if (ret < 0) | |
212 | printk(KERN_DEBUG "Playback DMA stop failed\n"); | |
213 | } | |
214 | ||
215 | /* Enable the transmitter */ | |
35cf6358 TK |
216 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
217 | spcr |= DAVINCI_MCBSP_SPCR_XRST; | |
218 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); | |
fb0ef645 NM |
219 | |
220 | /* wait for any unexpected frame sync error to occur */ | |
221 | udelay(100); | |
222 | ||
223 | /* Disable the transmitter to clear any outstanding XSYNCERR */ | |
35cf6358 TK |
224 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
225 | spcr &= ~DAVINCI_MCBSP_SPCR_XRST; | |
226 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); | |
c392bec7 | 227 | toggle_clock(dev, playback); |
fb0ef645 NM |
228 | |
229 | /* Restart the DMA */ | |
f0fba2ad LG |
230 | if (platform->driver->ops->trigger) { |
231 | int ret = platform->driver->ops->trigger(substream, | |
fb0ef645 NM |
232 | SNDRV_PCM_TRIGGER_START); |
233 | if (ret < 0) | |
234 | printk(KERN_DEBUG "Playback DMA start failed\n"); | |
235 | } | |
fb0ef645 NM |
236 | } |
237 | ||
1bef4499 | 238 | /* Enable transmitter or receiver */ |
35cf6358 | 239 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
1bef4499 TK |
240 | spcr |= mask; |
241 | ||
242 | if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM)) { | |
243 | /* Start frame sync */ | |
244 | spcr |= DAVINCI_MCBSP_SPCR_FRST; | |
245 | } | |
35cf6358 | 246 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); |
310355c1 VB |
247 | } |
248 | ||
f9af37cc | 249 | static void davinci_mcbsp_stop(struct davinci_mcbsp_dev *dev, int playback) |
310355c1 | 250 | { |
35cf6358 | 251 | u32 spcr; |
310355c1 VB |
252 | |
253 | /* Reset transmitter/receiver and sample rate/frame sync generators */ | |
35cf6358 TK |
254 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
255 | spcr &= ~(DAVINCI_MCBSP_SPCR_GRST | DAVINCI_MCBSP_SPCR_FRST); | |
c392bec7 | 256 | spcr &= playback ? ~DAVINCI_MCBSP_SPCR_XRST : ~DAVINCI_MCBSP_SPCR_RRST; |
35cf6358 | 257 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); |
c392bec7 | 258 | toggle_clock(dev, playback); |
310355c1 VB |
259 | } |
260 | ||
21903c1c TK |
261 | #define DEFAULT_BITPERSAMPLE 16 |
262 | ||
9cb132d7 | 263 | static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, |
310355c1 VB |
264 | unsigned int fmt) |
265 | { | |
f0fba2ad | 266 | struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(cpu_dai); |
21903c1c TK |
267 | unsigned int pcr; |
268 | unsigned int srgr; | |
ad51f765 | 269 | bool inv_fs = false; |
a4c8ea2d | 270 | /* Attention srgr is updated by hw_params! */ |
21903c1c TK |
271 | srgr = DAVINCI_MCBSP_SRGR_FSGM | |
272 | DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) | | |
273 | DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1); | |
310355c1 | 274 | |
a4c8ea2d | 275 | dev->fmt = fmt; |
f5cfa954 | 276 | /* set master/slave audio interface */ |
310355c1 VB |
277 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
278 | case SND_SOC_DAIFMT_CBS_CFS: | |
21903c1c TK |
279 | /* cpu is master */ |
280 | pcr = DAVINCI_MCBSP_PCR_FSXM | | |
281 | DAVINCI_MCBSP_PCR_FSRM | | |
282 | DAVINCI_MCBSP_PCR_CLKXM | | |
283 | DAVINCI_MCBSP_PCR_CLKRM; | |
310355c1 | 284 | break; |
b402dff8 | 285 | case SND_SOC_DAIFMT_CBM_CFS: |
ec637553 RR |
286 | pcr = DAVINCI_MCBSP_PCR_FSRM | DAVINCI_MCBSP_PCR_FSXM; |
287 | /* | |
288 | * Selection of the clock input pin that is the | |
289 | * input for the Sample Rate Generator. | |
290 | * McBSP FSR and FSX are driven by the Sample Rate | |
291 | * Generator. | |
292 | */ | |
293 | switch (dev->clk_input_pin) { | |
294 | case MCBSP_CLKS: | |
295 | pcr |= DAVINCI_MCBSP_PCR_CLKXM | | |
296 | DAVINCI_MCBSP_PCR_CLKRM; | |
297 | break; | |
298 | case MCBSP_CLKR: | |
299 | pcr |= DAVINCI_MCBSP_PCR_SCLKME; | |
300 | break; | |
301 | default: | |
302 | dev_err(dev->dev, "bad clk_input_pin\n"); | |
303 | return -EINVAL; | |
304 | } | |
305 | ||
b402dff8 | 306 | break; |
310355c1 | 307 | case SND_SOC_DAIFMT_CBM_CFM: |
21903c1c TK |
308 | /* codec is master */ |
309 | pcr = 0; | |
310355c1 VB |
310 | break; |
311 | default: | |
21903c1c | 312 | printk(KERN_ERR "%s:bad master\n", __func__); |
310355c1 VB |
313 | return -EINVAL; |
314 | } | |
315 | ||
f5cfa954 | 316 | /* interface format */ |
69ab820c | 317 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
69ab820c | 318 | case SND_SOC_DAIFMT_I2S: |
07d8d9dc TK |
319 | /* Davinci doesn't support TRUE I2S, but some codecs will have |
320 | * the left and right channels contiguous. This allows | |
321 | * dsp_a mode to be used with an inverted normal frame clk. | |
322 | * If your codec is master and does not have contiguous | |
323 | * channels, then you will have sound on only one channel. | |
324 | * Try using a different mode, or codec as slave. | |
325 | * | |
326 | * The TLV320AIC33 is an example of a codec where this works. | |
327 | * It has a variable bit clock frequency allowing it to have | |
328 | * valid data on every bit clock. | |
329 | * | |
330 | * The TLV320AIC23 is an example of a codec where this does not | |
331 | * work. It has a fixed bit clock frequency with progressively | |
332 | * more empty bit clock slots between channels as the sample | |
333 | * rate is lowered. | |
334 | */ | |
ad51f765 | 335 | inv_fs = true; |
07d8d9dc | 336 | case SND_SOC_DAIFMT_DSP_A: |
f5cfa954 TK |
337 | dev->mode = MOD_DSP_A; |
338 | break; | |
339 | case SND_SOC_DAIFMT_DSP_B: | |
340 | dev->mode = MOD_DSP_B; | |
69ab820c TK |
341 | break; |
342 | default: | |
343 | printk(KERN_ERR "%s:bad format\n", __func__); | |
344 | return -EINVAL; | |
345 | } | |
346 | ||
310355c1 | 347 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
9e031624 | 348 | case SND_SOC_DAIFMT_NB_NF: |
664b4af8 TK |
349 | /* CLKRP Receive clock polarity, |
350 | * 1 - sampled on rising edge of CLKR | |
351 | * valid on rising edge | |
352 | * CLKXP Transmit clock polarity, | |
353 | * 1 - clocked on falling edge of CLKX | |
354 | * valid on rising edge | |
355 | * FSRP Receive frame sync pol, 0 - active high | |
356 | * FSXP Transmit frame sync pol, 0 - active high | |
357 | */ | |
21903c1c | 358 | pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP); |
310355c1 | 359 | break; |
9e031624 | 360 | case SND_SOC_DAIFMT_IB_IF: |
664b4af8 TK |
361 | /* CLKRP Receive clock polarity, |
362 | * 0 - sampled on falling edge of CLKR | |
363 | * valid on falling edge | |
364 | * CLKXP Transmit clock polarity, | |
365 | * 0 - clocked on rising edge of CLKX | |
366 | * valid on falling edge | |
367 | * FSRP Receive frame sync pol, 1 - active low | |
368 | * FSXP Transmit frame sync pol, 1 - active low | |
369 | */ | |
21903c1c | 370 | pcr |= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP); |
310355c1 | 371 | break; |
9e031624 | 372 | case SND_SOC_DAIFMT_NB_IF: |
664b4af8 TK |
373 | /* CLKRP Receive clock polarity, |
374 | * 1 - sampled on rising edge of CLKR | |
375 | * valid on rising edge | |
376 | * CLKXP Transmit clock polarity, | |
377 | * 1 - clocked on falling edge of CLKX | |
378 | * valid on rising edge | |
379 | * FSRP Receive frame sync pol, 1 - active low | |
380 | * FSXP Transmit frame sync pol, 1 - active low | |
381 | */ | |
21903c1c TK |
382 | pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP | |
383 | DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP); | |
310355c1 | 384 | break; |
9e031624 | 385 | case SND_SOC_DAIFMT_IB_NF: |
664b4af8 TK |
386 | /* CLKRP Receive clock polarity, |
387 | * 0 - sampled on falling edge of CLKR | |
388 | * valid on falling edge | |
389 | * CLKXP Transmit clock polarity, | |
390 | * 0 - clocked on rising edge of CLKX | |
391 | * valid on falling edge | |
392 | * FSRP Receive frame sync pol, 0 - active high | |
393 | * FSXP Transmit frame sync pol, 0 - active high | |
394 | */ | |
310355c1 VB |
395 | break; |
396 | default: | |
397 | return -EINVAL; | |
398 | } | |
ad51f765 JN |
399 | if (inv_fs == true) |
400 | pcr ^= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP); | |
21903c1c | 401 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr); |
c392bec7 | 402 | dev->pcr = pcr; |
21903c1c | 403 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr); |
310355c1 VB |
404 | return 0; |
405 | } | |
406 | ||
a4c8ea2d RR |
407 | static int davinci_i2s_dai_set_clkdiv(struct snd_soc_dai *cpu_dai, |
408 | int div_id, int div) | |
409 | { | |
f0fba2ad | 410 | struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(cpu_dai); |
a4c8ea2d RR |
411 | |
412 | if (div_id != DAVINCI_MCBSP_CLKGDV) | |
413 | return -ENODEV; | |
414 | ||
415 | dev->clk_div = div; | |
416 | return 0; | |
417 | } | |
418 | ||
310355c1 | 419 | static int davinci_i2s_hw_params(struct snd_pcm_substream *substream, |
dee89c4d MB |
420 | struct snd_pcm_hw_params *params, |
421 | struct snd_soc_dai *dai) | |
310355c1 | 422 | { |
f0fba2ad | 423 | struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai); |
310355c1 | 424 | struct snd_interval *i = NULL; |
a4c8ea2d RR |
425 | int mcbsp_word_length, master; |
426 | unsigned int rcr, xcr, srgr, clk_div, freq, framesize; | |
35cf6358 | 427 | u32 spcr; |
0d6c9774 TK |
428 | snd_pcm_format_t fmt; |
429 | unsigned element_cnt = 1; | |
310355c1 VB |
430 | |
431 | /* general line settings */ | |
35cf6358 | 432 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
cb6e2063 | 433 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { |
35cf6358 TK |
434 | spcr |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE; |
435 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); | |
cb6e2063 | 436 | } else { |
35cf6358 TK |
437 | spcr |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE; |
438 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); | |
cb6e2063 | 439 | } |
310355c1 | 440 | |
a4c8ea2d RR |
441 | master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK; |
442 | fmt = params_format(params); | |
443 | mcbsp_word_length = asp_word_length[fmt]; | |
310355c1 | 444 | |
a4c8ea2d RR |
445 | switch (master) { |
446 | case SND_SOC_DAIFMT_CBS_CFS: | |
447 | freq = clk_get_rate(dev->clk); | |
448 | srgr = DAVINCI_MCBSP_SRGR_FSGM | | |
449 | DAVINCI_MCBSP_SRGR_CLKSM; | |
450 | srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length * | |
451 | 8 - 1); | |
d9823ed9 RR |
452 | if (dev->i2s_accurate_sck) { |
453 | clk_div = 256; | |
454 | do { | |
455 | framesize = (freq / (--clk_div)) / | |
456 | params->rate_num * | |
457 | params->rate_den; | |
458 | } while (((framesize < 33) || (framesize > 4095)) && | |
459 | (clk_div)); | |
460 | clk_div--; | |
461 | srgr |= DAVINCI_MCBSP_SRGR_FPER(framesize - 1); | |
462 | } else { | |
463 | /* symmetric waveforms */ | |
464 | clk_div = freq / (mcbsp_word_length * 16) / | |
465 | params->rate_num * params->rate_den; | |
466 | srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length * | |
467 | 16 - 1); | |
468 | } | |
a4c8ea2d RR |
469 | clk_div &= 0xFF; |
470 | srgr |= clk_div; | |
471 | break; | |
472 | case SND_SOC_DAIFMT_CBM_CFS: | |
473 | srgr = DAVINCI_MCBSP_SRGR_FSGM; | |
474 | clk_div = dev->clk_div - 1; | |
475 | srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length * 8 - 1); | |
476 | srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length * 16 - 1); | |
477 | clk_div &= 0xFF; | |
478 | srgr |= clk_div; | |
479 | break; | |
480 | case SND_SOC_DAIFMT_CBM_CFM: | |
481 | /* Clock and frame sync given from external sources */ | |
482 | i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS); | |
483 | srgr = DAVINCI_MCBSP_SRGR_FSGM; | |
484 | srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1); | |
485 | pr_debug("%s - %d FWID set: re-read srgr = %X\n", | |
486 | __func__, __LINE__, snd_interval_value(i) - 1); | |
487 | ||
488 | i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS); | |
489 | srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1); | |
490 | break; | |
491 | default: | |
492 | return -EINVAL; | |
493 | } | |
35cf6358 | 494 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr); |
310355c1 | 495 | |
f5cfa954 TK |
496 | rcr = DAVINCI_MCBSP_RCR_RFIG; |
497 | xcr = DAVINCI_MCBSP_XCR_XFIG; | |
498 | if (dev->mode == MOD_DSP_B) { | |
499 | rcr |= DAVINCI_MCBSP_RCR_RDATDLY(0); | |
500 | xcr |= DAVINCI_MCBSP_XCR_XDATDLY(0); | |
501 | } else { | |
502 | rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1); | |
503 | xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1); | |
504 | } | |
310355c1 | 505 | /* Determine xfer data type */ |
0d6c9774 TK |
506 | fmt = params_format(params); |
507 | if ((fmt > SNDRV_PCM_FORMAT_S32_LE) || !data_type[fmt]) { | |
9b6e12e4 | 508 | printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n"); |
310355c1 VB |
509 | return -EINVAL; |
510 | } | |
511 | ||
0d6c9774 TK |
512 | if (params_channels(params) == 2) { |
513 | element_cnt = 2; | |
514 | if (double_fmt[fmt] && dev->enable_channel_combine) { | |
515 | element_cnt = 1; | |
516 | fmt = double_fmt[fmt]; | |
517 | } | |
a4c8ea2d RR |
518 | switch (master) { |
519 | case SND_SOC_DAIFMT_CBS_CFS: | |
520 | case SND_SOC_DAIFMT_CBS_CFM: | |
521 | rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(0); | |
522 | xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(0); | |
523 | rcr |= DAVINCI_MCBSP_RCR_RPHASE; | |
524 | xcr |= DAVINCI_MCBSP_XCR_XPHASE; | |
525 | break; | |
526 | case SND_SOC_DAIFMT_CBM_CFM: | |
527 | case SND_SOC_DAIFMT_CBM_CFS: | |
528 | rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(element_cnt - 1); | |
529 | xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(element_cnt - 1); | |
530 | break; | |
531 | default: | |
532 | return -EINVAL; | |
533 | } | |
0d6c9774 | 534 | } |
0d6c9774 | 535 | mcbsp_word_length = asp_word_length[fmt]; |
a4c8ea2d RR |
536 | |
537 | switch (master) { | |
538 | case SND_SOC_DAIFMT_CBS_CFS: | |
539 | case SND_SOC_DAIFMT_CBS_CFM: | |
540 | rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(0); | |
541 | xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(0); | |
542 | break; | |
543 | case SND_SOC_DAIFMT_CBM_CFM: | |
544 | case SND_SOC_DAIFMT_CBM_CFS: | |
545 | rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(element_cnt - 1); | |
546 | xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(element_cnt - 1); | |
547 | break; | |
548 | default: | |
549 | return -EINVAL; | |
550 | } | |
310355c1 | 551 | |
f5cfa954 TK |
552 | rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) | |
553 | DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length); | |
554 | xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) | | |
555 | DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length); | |
310355c1 | 556 | |
f5cfa954 TK |
557 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
558 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr); | |
559 | else | |
560 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr); | |
a4c8ea2d RR |
561 | |
562 | pr_debug("%s - %d srgr=%X\n", __func__, __LINE__, srgr); | |
563 | pr_debug("%s - %d xcr=%X\n", __func__, __LINE__, xcr); | |
564 | pr_debug("%s - %d rcr=%X\n", __func__, __LINE__, rcr); | |
310355c1 VB |
565 | return 0; |
566 | } | |
567 | ||
af0adf3e TK |
568 | static int davinci_i2s_prepare(struct snd_pcm_substream *substream, |
569 | struct snd_soc_dai *dai) | |
570 | { | |
f0fba2ad | 571 | struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai); |
af0adf3e TK |
572 | int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); |
573 | davinci_mcbsp_stop(dev, playback); | |
af0adf3e TK |
574 | return 0; |
575 | } | |
576 | ||
dee89c4d MB |
577 | static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd, |
578 | struct snd_soc_dai *dai) | |
310355c1 | 579 | { |
f0fba2ad | 580 | struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai); |
310355c1 | 581 | int ret = 0; |
f9af37cc | 582 | int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); |
310355c1 VB |
583 | |
584 | switch (cmd) { | |
585 | case SNDRV_PCM_TRIGGER_START: | |
586 | case SNDRV_PCM_TRIGGER_RESUME: | |
587 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
f9af37cc | 588 | davinci_mcbsp_start(dev, substream); |
310355c1 VB |
589 | break; |
590 | case SNDRV_PCM_TRIGGER_STOP: | |
591 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
592 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
f9af37cc | 593 | davinci_mcbsp_stop(dev, playback); |
310355c1 VB |
594 | break; |
595 | default: | |
596 | ret = -EINVAL; | |
597 | } | |
310355c1 VB |
598 | return ret; |
599 | } | |
600 | ||
af0adf3e TK |
601 | static void davinci_i2s_shutdown(struct snd_pcm_substream *substream, |
602 | struct snd_soc_dai *dai) | |
603 | { | |
f0fba2ad | 604 | struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai); |
af0adf3e TK |
605 | int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); |
606 | davinci_mcbsp_stop(dev, playback); | |
607 | } | |
608 | ||
5204d496 C |
609 | #define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000 |
610 | ||
85e7652d | 611 | static const struct snd_soc_dai_ops davinci_i2s_dai_ops = { |
3f405b46 MB |
612 | .shutdown = davinci_i2s_shutdown, |
613 | .prepare = davinci_i2s_prepare, | |
5204d496 C |
614 | .trigger = davinci_i2s_trigger, |
615 | .hw_params = davinci_i2s_hw_params, | |
616 | .set_fmt = davinci_i2s_set_dai_fmt, | |
a4c8ea2d | 617 | .set_clkdiv = davinci_i2s_dai_set_clkdiv, |
5204d496 C |
618 | |
619 | }; | |
620 | ||
257ade78 PU |
621 | static int davinci_i2s_dai_probe(struct snd_soc_dai *dai) |
622 | { | |
623 | struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai); | |
624 | ||
625 | dai->playback_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; | |
626 | dai->capture_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_CAPTURE]; | |
627 | ||
628 | return 0; | |
629 | } | |
630 | ||
f0fba2ad | 631 | static struct snd_soc_dai_driver davinci_i2s_dai = { |
257ade78 | 632 | .probe = davinci_i2s_dai_probe, |
5204d496 C |
633 | .playback = { |
634 | .channels_min = 2, | |
635 | .channels_max = 2, | |
636 | .rates = DAVINCI_I2S_RATES, | |
637 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
638 | .capture = { | |
639 | .channels_min = 2, | |
640 | .channels_max = 2, | |
641 | .rates = DAVINCI_I2S_RATES, | |
642 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
643 | .ops = &davinci_i2s_dai_ops, | |
644 | ||
645 | }; | |
5204d496 | 646 | |
bfcb921c KM |
647 | static const struct snd_soc_component_driver davinci_i2s_component = { |
648 | .name = "davinci-i2s", | |
649 | }; | |
650 | ||
5204d496 | 651 | static int davinci_i2s_probe(struct platform_device *pdev) |
310355c1 | 652 | { |
310355c1 | 653 | struct davinci_mcbsp_dev *dev; |
508a43fd AL |
654 | struct resource *mem, *res; |
655 | void __iomem *io_base; | |
257ade78 | 656 | int *dma; |
310355c1 VB |
657 | int ret; |
658 | ||
659 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
508a43fd AL |
660 | io_base = devm_ioremap_resource(&pdev->dev, mem); |
661 | if (IS_ERR(io_base)) | |
662 | return PTR_ERR(io_base); | |
310355c1 | 663 | |
cd0ff7ef JL |
664 | dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcbsp_dev), |
665 | GFP_KERNEL); | |
666 | if (!dev) | |
667 | return -ENOMEM; | |
48519f0a | 668 | |
3e46a447 | 669 | dev->clk = clk_get(&pdev->dev, NULL); |
cd0ff7ef JL |
670 | if (IS_ERR(dev->clk)) |
671 | return -ENODEV; | |
310355c1 VB |
672 | clk_enable(dev->clk); |
673 | ||
508a43fd | 674 | dev->base = io_base; |
310355c1 | 675 | |
257ade78 | 676 | dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr = |
4f82f028 | 677 | (dma_addr_t)(mem->start + DAVINCI_MCBSP_DXR_REG); |
310355c1 | 678 | |
257ade78 | 679 | dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr = |
4f82f028 | 680 | (dma_addr_t)(mem->start + DAVINCI_MCBSP_DRR_REG); |
310355c1 | 681 | |
5204d496 C |
682 | /* first TX, then RX */ |
683 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); | |
684 | if (!res) { | |
685 | dev_err(&pdev->dev, "no DMA resource\n"); | |
efd13be0 | 686 | ret = -ENXIO; |
cd0ff7ef | 687 | goto err_release_clk; |
5204d496 | 688 | } |
257ade78 PU |
689 | dma = &dev->dma_request[SNDRV_PCM_STREAM_PLAYBACK]; |
690 | *dma = res->start; | |
691 | dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data = dma; | |
5204d496 C |
692 | |
693 | res = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
694 | if (!res) { | |
695 | dev_err(&pdev->dev, "no DMA resource\n"); | |
efd13be0 | 696 | ret = -ENXIO; |
cd0ff7ef | 697 | goto err_release_clk; |
5204d496 | 698 | } |
257ade78 PU |
699 | dma = &dev->dma_request[SNDRV_PCM_STREAM_CAPTURE]; |
700 | *dma = res->start; | |
701 | dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].filter_data = dma; | |
5204d496 | 702 | |
257ade78 | 703 | dev->dev = &pdev->dev; |
f0fba2ad LG |
704 | dev_set_drvdata(&pdev->dev, dev); |
705 | ||
bfcb921c KM |
706 | ret = snd_soc_register_component(&pdev->dev, &davinci_i2s_component, |
707 | &davinci_i2s_dai, 1); | |
5204d496 | 708 | if (ret != 0) |
cd0ff7ef | 709 | goto err_release_clk; |
5204d496 | 710 | |
257ade78 | 711 | ret = edma_pcm_platform_register(&pdev->dev); |
f08095a4 HG |
712 | if (ret) { |
713 | dev_err(&pdev->dev, "register PCM failed: %d\n", ret); | |
bfcb921c | 714 | goto err_unregister_component; |
f08095a4 HG |
715 | } |
716 | ||
310355c1 VB |
717 | return 0; |
718 | ||
bfcb921c KM |
719 | err_unregister_component: |
720 | snd_soc_unregister_component(&pdev->dev); | |
eef6d7b8 VB |
721 | err_release_clk: |
722 | clk_disable(dev->clk); | |
723 | clk_put(dev->clk); | |
310355c1 VB |
724 | return ret; |
725 | } | |
726 | ||
5204d496 | 727 | static int davinci_i2s_remove(struct platform_device *pdev) |
310355c1 | 728 | { |
f0fba2ad | 729 | struct davinci_mcbsp_dev *dev = dev_get_drvdata(&pdev->dev); |
310355c1 | 730 | |
bfcb921c | 731 | snd_soc_unregister_component(&pdev->dev); |
f08095a4 | 732 | |
310355c1 VB |
733 | clk_disable(dev->clk); |
734 | clk_put(dev->clk); | |
735 | dev->clk = NULL; | |
310355c1 | 736 | |
5204d496 C |
737 | return 0; |
738 | } | |
6335d055 | 739 | |
5204d496 C |
740 | static struct platform_driver davinci_mcbsp_driver = { |
741 | .probe = davinci_i2s_probe, | |
742 | .remove = davinci_i2s_remove, | |
743 | .driver = { | |
bedad0ca | 744 | .name = "davinci-mcbsp", |
5204d496 | 745 | }, |
310355c1 | 746 | }; |
310355c1 | 747 | |
f9b8a514 | 748 | module_platform_driver(davinci_mcbsp_driver); |
3f4b783c | 749 | |
310355c1 VB |
750 | MODULE_AUTHOR("Vladimir Barinov"); |
751 | MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface"); | |
752 | MODULE_LICENSE("GPL"); |