[deliverable/linux.git] / sound / soc / ep93xx / ep93xx-ac97.c

/*
 * ASoC driver for Cirrus Logic EP93xx AC97 controller.
 *
 * Copyright (c) 2010 Mika Westerberg
 *
 * Based on s3c-ac97 ASoC driver by Jaswinder Singh.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/delay.h>
#include <linux/io.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#include <sound/core.h>
#include <sound/ac97_codec.h>
#include <sound/soc.h>

#include <mach/dma.h>
#include "ep93xx-pcm.h"

/*
 * Per channel (1-4) registers.
 */
#define AC97CH(n)		(((n) - 1) * 0x20)

#define AC97DR(n)		(AC97CH(n) + 0x0000)

#define AC97RXCR(n)		(AC97CH(n) + 0x0004)
#define AC97RXCR_REN		BIT(0)
#define AC97RXCR_RX3		BIT(3)
#define AC97RXCR_RX4		BIT(4)
#define AC97RXCR_CM		BIT(15)

#define AC97TXCR(n)		(AC97CH(n) + 0x0008)
#define AC97TXCR_TEN		BIT(0)
#define AC97TXCR_TX3		BIT(3)
#define AC97TXCR_TX4		BIT(4)
#define AC97TXCR_CM		BIT(15)

#define AC97SR(n)		(AC97CH(n) + 0x000c)
#define AC97SR_TXFE		BIT(1)
#define AC97SR_TXUE		BIT(6)

#define AC97RISR(n)		(AC97CH(n) + 0x0010)
#define AC97ISR(n)		(AC97CH(n) + 0x0014)
#define AC97IE(n)		(AC97CH(n) + 0x0018)

/*
 * Global AC97 controller registers.
 */
#define AC97S1DATA		0x0080
#define AC97S2DATA		0x0084
#define AC97S12DATA		0x0088

#define AC97RGIS		0x008c
#define AC97GIS			0x0090
#define AC97IM			0x0094
/*
 * Common bits for RGIS, GIS and IM registers.
 */
#define AC97_SLOT2RXVALID	BIT(1)
#define AC97_CODECREADY		BIT(5)
#define AC97_SLOT2TXCOMPLETE	BIT(6)

#define AC97EOI			0x0098
#define AC97EOI_WINT		BIT(0)
#define AC97EOI_CODECREADY	BIT(1)

#define AC97GCR			0x009c
#define AC97GCR_AC97IFE		BIT(0)

#define AC97RESET		0x00a0
#define AC97RESET_TIMEDRESET	BIT(0)

#define AC97SYNC		0x00a4
#define AC97SYNC_TIMEDSYNC	BIT(0)

#define AC97_TIMEOUT		msecs_to_jiffies(5)

/**
 * struct ep93xx_ac97_info - EP93xx AC97 controller info structure
 * @lock: mutex serializing access to the bus (slot 1 & 2 ops)
 * @dev: pointer to the platform device dev structure
 * @mem: physical memory resource for the registers
 * @regs: mapped AC97 controller registers
 * @irq: AC97 interrupt number
 * @done: bus ops wait here for an interrupt
 */
struct ep93xx_ac97_info {
	struct mutex		lock;
	struct device		*dev;
	struct resource		*mem;
	void __iomem		*regs;
	int			irq;
	struct completion	done;
};

/* currently ALSA only supports a single AC97 device */
static struct ep93xx_ac97_info *ep93xx_ac97_info;

static struct ep93xx_pcm_dma_params ep93xx_ac97_pcm_out = {
	.name		= "ac97-pcm-out",
	.dma_port	= EP93XX_DMA_AAC1,
};

static struct ep93xx_pcm_dma_params ep93xx_ac97_pcm_in = {
	.name		= "ac97-pcm-in",
	.dma_port	= EP93XX_DMA_AAC1,
};

static inline unsigned ep93xx_ac97_read_reg(struct ep93xx_ac97_info *info,
					    unsigned reg)
{
	return __raw_readl(info->regs + reg);
}

static inline void ep93xx_ac97_write_reg(struct ep93xx_ac97_info *info,
					 unsigned reg, unsigned val)
{
	__raw_writel(val, info->regs + reg);
}

static unsigned short ep93xx_ac97_read(struct snd_ac97 *ac97,
				       unsigned short reg)
{
	struct ep93xx_ac97_info *info = ep93xx_ac97_info;
	unsigned short val;

	mutex_lock(&info->lock);

	ep93xx_ac97_write_reg(info, AC97S1DATA, reg);
	ep93xx_ac97_write_reg(info, AC97IM, AC97_SLOT2RXVALID);
	if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT)) {
		dev_warn(info->dev, "timeout reading register %x\n", reg);
		mutex_unlock(&info->lock);
		return -ETIMEDOUT;
	}
	val = (unsigned short)ep93xx_ac97_read_reg(info, AC97S2DATA);

	mutex_unlock(&info->lock);
	return val;
}

static void ep93xx_ac97_write(struct snd_ac97 *ac97,
			      unsigned short reg,
			      unsigned short val)
{
	struct ep93xx_ac97_info *info = ep93xx_ac97_info;

	mutex_lock(&info->lock);

	/*
	 * Writes to the codec need to be done so that slot 2 is filled in
	 * before slot 1.
	 */
	ep93xx_ac97_write_reg(info, AC97S2DATA, val);
	ep93xx_ac97_write_reg(info, AC97S1DATA, reg);

	ep93xx_ac97_write_reg(info, AC97IM, AC97_SLOT2TXCOMPLETE);
	if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT))
		dev_warn(info->dev, "timeout writing register %x\n", reg);

	mutex_unlock(&info->lock);
}

static void ep93xx_ac97_warm_reset(struct snd_ac97 *ac97)
{
	struct ep93xx_ac97_info *info = ep93xx_ac97_info;

	mutex_lock(&info->lock);

	/*
	 * We are assuming that before this functions gets called, the codec
	 * BIT_CLK is stopped by forcing the codec into powerdown mode. We can
	 * control the SYNC signal directly via AC97SYNC register. Using
	 * TIMEDSYNC the controller will keep the SYNC high > 1us.
	 */
	ep93xx_ac97_write_reg(info, AC97SYNC, AC97SYNC_TIMEDSYNC);
	ep93xx_ac97_write_reg(info, AC97IM, AC97_CODECREADY);
	if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT))
		dev_warn(info->dev, "codec warm reset timeout\n");

	mutex_unlock(&info->lock);
}

static void ep93xx_ac97_cold_reset(struct snd_ac97 *ac97)
{
	struct ep93xx_ac97_info *info = ep93xx_ac97_info;

	mutex_lock(&info->lock);

	/*
	 * For doing cold reset, we disable the AC97 controller interface, clear
	 * WINT and CODECREADY bits, and finally enable the interface again.
	 */
	ep93xx_ac97_write_reg(info, AC97GCR, 0);
	ep93xx_ac97_write_reg(info, AC97EOI, AC97EOI_CODECREADY | AC97EOI_WINT);
	ep93xx_ac97_write_reg(info, AC97GCR, AC97GCR_AC97IFE);

	/*
	 * Now, assert the reset and wait for the codec to become ready.
	 */
	ep93xx_ac97_write_reg(info, AC97RESET, AC97RESET_TIMEDRESET);
	ep93xx_ac97_write_reg(info, AC97IM, AC97_CODECREADY);
	if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT))
		dev_warn(info->dev, "codec cold reset timeout\n");

	/*
	 * Give the codec some time to come fully out from the reset. This way
	 * we ensure that the subsequent reads/writes will work.
	 */
	usleep_range(15000, 20000);

	mutex_unlock(&info->lock);
}

static irqreturn_t ep93xx_ac97_interrupt(int irq, void *dev_id)
{
	struct ep93xx_ac97_info *info = dev_id;
	unsigned status, mask;

	/*
	 * Just mask out the interrupt and wake up the waiting thread.
	 * Interrupts are cleared via reading/writing to slot 1 & 2 registers by
	 * the waiting thread.
	 */
	status = ep93xx_ac97_read_reg(info, AC97GIS);
	mask = ep93xx_ac97_read_reg(info, AC97IM);
	mask &= ~status;
	ep93xx_ac97_write_reg(info, AC97IM, mask);

	complete(&info->done);
	return IRQ_HANDLED;
}

struct snd_ac97_bus_ops soc_ac97_ops = {
	.read		= ep93xx_ac97_read,
	.write		= ep93xx_ac97_write,
	.reset		= ep93xx_ac97_cold_reset,
	.warm_reset	= ep93xx_ac97_warm_reset,
};
EXPORT_SYMBOL_GPL(soc_ac97_ops);

static int ep93xx_ac97_trigger(struct snd_pcm_substream *substream,
			       int cmd, struct snd_soc_dai *dai)
{
	struct ep93xx_ac97_info *info = snd_soc_dai_get_drvdata(dai);
	unsigned v = 0;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
			/*
			 * Enable compact mode, TX slots 3 & 4, and the TX FIFO
			 * itself.
			 */
			v |= AC97TXCR_CM;
			v |= AC97TXCR_TX3 | AC97TXCR_TX4;
			v |= AC97TXCR_TEN;
			ep93xx_ac97_write_reg(info, AC97TXCR(1), v);
		} else {
			/*
			 * Enable compact mode, RX slots 3 & 4, and the RX FIFO
			 * itself.
			 */
			v |= AC97RXCR_CM;
			v |= AC97RXCR_RX3 | AC97RXCR_RX4;
			v |= AC97RXCR_REN;
			ep93xx_ac97_write_reg(info, AC97RXCR(1), v);
		}
		break;

	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
			/*
			 * As per Cirrus EP93xx errata described below:
			 *
			 * http://www.cirrus.com/en/pubs/errata/ER667E2B.pdf
			 *
			 * we will wait for the TX FIFO to be empty before
			 * clearing the TEN bit.
			 */
			unsigned long timeout = jiffies + AC97_TIMEOUT;

			do {
				v = ep93xx_ac97_read_reg(info, AC97SR(1));
				if (time_after(jiffies, timeout)) {
					dev_warn(info->dev, "TX timeout\n");
					break;
				}
			} while (!(v & (AC97SR_TXFE | AC97SR_TXUE)));

			/* disable the TX FIFO */
			ep93xx_ac97_write_reg(info, AC97TXCR(1), 0);
		} else {
			/* disable the RX FIFO */
			ep93xx_ac97_write_reg(info, AC97RXCR(1), 0);
		}
		break;

	default:
		dev_warn(info->dev, "unknown command %d\n", cmd);
		return -EINVAL;
	}

	return 0;
}

static int ep93xx_ac97_startup(struct snd_pcm_substream *substream,
			       struct snd_soc_dai *dai)
{
	struct ep93xx_pcm_dma_params *dma_data;

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		dma_data = &ep93xx_ac97_pcm_out;
	else
		dma_data = &ep93xx_ac97_pcm_in;

	snd_soc_dai_set_dma_data(dai, substream, dma_data);
	return 0;
}

static struct snd_soc_dai_ops ep93xx_ac97_dai_ops = {
	.startup	= ep93xx_ac97_startup,
	.trigger	= ep93xx_ac97_trigger,
};

struct snd_soc_dai_driver ep93xx_ac97_dai = {
	.name		= "ep93xx-ac97",
	.id		= 0,
	.ac97_control	= 1,
	.playback	= {
		.stream_name	= "AC97 Playback",
		.channels_min	= 2,
		.channels_max	= 2,
		.rates		= SNDRV_PCM_RATE_8000_48000,
		.formats	= SNDRV_PCM_FMTBIT_S16_LE,
	},
	.capture	= {
		.stream_name	= "AC97 Capture",
		.channels_min	= 2,
		.channels_max	= 2,
		.rates		= SNDRV_PCM_RATE_8000_48000,
		.formats	= SNDRV_PCM_FMTBIT_S16_LE,
	},
	.ops			= &ep93xx_ac97_dai_ops,
};

static int __devinit ep93xx_ac97_probe(struct platform_device *pdev)
{
	struct ep93xx_ac97_info *info;
	int ret;

	info = kzalloc(sizeof(struct ep93xx_ac97_info), GFP_KERNEL);
	if (!info)
		return -ENOMEM;

	dev_set_drvdata(&pdev->dev, info);

	mutex_init(&info->lock);
	init_completion(&info->done);
	info->dev = &pdev->dev;

	info->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!info->mem) {
		ret = -ENXIO;
		goto fail_free_info;
	}

	info->irq = platform_get_irq(pdev, 0);
	if (!info->irq) {
		ret = -ENXIO;
		goto fail_free_info;
	}

	if (!request_mem_region(info->mem->start, resource_size(info->mem),
				pdev->name)) {
		ret = -EBUSY;
		goto fail_free_info;
	}

	info->regs = ioremap(info->mem->start, resource_size(info->mem));
	if (!info->regs) {
		ret = -ENOMEM;
		goto fail_release_mem;
	}

	ret = request_irq(info->irq, ep93xx_ac97_interrupt, IRQF_TRIGGER_HIGH,
			  pdev->name, info);
	if (ret)
		goto fail_unmap_mem;

	ep93xx_ac97_info = info;
	platform_set_drvdata(pdev, info);

	ret = snd_soc_register_dai(&pdev->dev, &ep93xx_ac97_dai);
	if (ret)
		goto fail_free_irq;

	return 0;

fail_free_irq:
	platform_set_drvdata(pdev, NULL);
	free_irq(info->irq, info);
fail_unmap_mem:
	iounmap(info->regs);
fail_release_mem:
	release_mem_region(info->mem->start, resource_size(info->mem));
fail_free_info:
	kfree(info);

	return ret;
}

static int __devexit ep93xx_ac97_remove(struct platform_device *pdev)
{
	struct ep93xx_ac97_info	*info = platform_get_drvdata(pdev);

	snd_soc_unregister_dai(&pdev->dev);

	/* disable the AC97 controller */
	ep93xx_ac97_write_reg(info, AC97GCR, 0);

	free_irq(info->irq, info);
	iounmap(info->regs);
	release_mem_region(info->mem->start, resource_size(info->mem));
	platform_set_drvdata(pdev, NULL);
	kfree(info);

	return 0;
}

static struct platform_driver ep93xx_ac97_driver = {
	.probe	= ep93xx_ac97_probe,
	.remove	= __devexit_p(ep93xx_ac97_remove),
	.driver = {
		.name = "ep93xx-ac97",
		.owner = THIS_MODULE,
	},
};

static int __init ep93xx_ac97_init(void)
{
	return platform_driver_register(&ep93xx_ac97_driver);
}
module_init(ep93xx_ac97_init);

static void __exit ep93xx_ac97_exit(void)
{
	platform_driver_unregister(&ep93xx_ac97_driver);
}
module_exit(ep93xx_ac97_exit);

MODULE_DESCRIPTION("EP93xx AC97 ASoC Driver");
MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:ep93xx-ac97");
Commit	Line	Data
aa7e1b84 MW	1	/*
	2	* ASoC driver for Cirrus Logic EP93xx AC97 controller.
	3	*
	4	* Copyright (c) 2010 Mika Westerberg
	5	*
	6	* Based on s3c-ac97 ASoC driver by Jaswinder Singh.
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/delay.h>
	14	#include <linux/io.h>
	15	#include <linux/init.h>
	16	#include <linux/module.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/slab.h>
	19
	20	#include <sound/core.h>
	21	#include <sound/ac97_codec.h>
	22	#include <sound/soc.h>
	23
	24	#include <mach/dma.h>
	25	#include "ep93xx-pcm.h"
	26
	27	/*
	28	* Per channel (1-4) registers.
	29	*/
	30	#define AC97CH(n) (((n) - 1) * 0x20)
	31
	32	#define AC97DR(n) (AC97CH(n) + 0x0000)
	33
	34	#define AC97RXCR(n) (AC97CH(n) + 0x0004)
	35	#define AC97RXCR_REN BIT(0)
	36	#define AC97RXCR_RX3 BIT(3)
	37	#define AC97RXCR_RX4 BIT(4)
	38	#define AC97RXCR_CM BIT(15)
	39
	40	#define AC97TXCR(n) (AC97CH(n) + 0x0008)
	41	#define AC97TXCR_TEN BIT(0)
	42	#define AC97TXCR_TX3 BIT(3)
	43	#define AC97TXCR_TX4 BIT(4)
	44	#define AC97TXCR_CM BIT(15)
	45
	46	#define AC97SR(n) (AC97CH(n) + 0x000c)
	47	#define AC97SR_TXFE BIT(1)
	48	#define AC97SR_TXUE BIT(6)
	49
	50	#define AC97RISR(n) (AC97CH(n) + 0x0010)
	51	#define AC97ISR(n) (AC97CH(n) + 0x0014)
	52	#define AC97IE(n) (AC97CH(n) + 0x0018)
	53
	54	/*
	55	* Global AC97 controller registers.
	56	*/
	57	#define AC97S1DATA 0x0080
	58	#define AC97S2DATA 0x0084
	59	#define AC97S12DATA 0x0088
	60
	61	#define AC97RGIS 0x008c
	62	#define AC97GIS 0x0090
	63	#define AC97IM 0x0094
	64	/*
65	* Common bits for RGIS, GIS and IM registers.
66	*/
67	#define AC97_SLOT2RXVALID BIT(1)
68	#define AC97_CODECREADY BIT(5)
69	#define AC97_SLOT2TXCOMPLETE BIT(6)
70
71	#define AC97EOI 0x0098
72	#define AC97EOI_WINT BIT(0)
73	#define AC97EOI_CODECREADY BIT(1)
74
75	#define AC97GCR 0x009c
76	#define AC97GCR_AC97IFE BIT(0)
77
78	#define AC97RESET 0x00a0
79	#define AC97RESET_TIMEDRESET BIT(0)
80
81	#define AC97SYNC 0x00a4
82	#define AC97SYNC_TIMEDSYNC BIT(0)
83
84	#define AC97_TIMEOUT msecs_to_jiffies(5)
85
86	/**
87	* struct ep93xx_ac97_info - EP93xx AC97 controller info structure
88	* @lock: mutex serializing access to the bus (slot 1 & 2 ops)
89	* @dev: pointer to the platform device dev structure
90	* @mem: physical memory resource for the registers
91	* @regs: mapped AC97 controller registers
92	* @irq: AC97 interrupt number
93	* @done: bus ops wait here for an interrupt
94	*/
95	struct ep93xx_ac97_info {
96	struct mutex lock;
97	struct device *dev;
98	struct resource *mem;
99	void __iomem *regs;
100	int irq;
101	struct completion done;
102	};
103
104	/* currently ALSA only supports a single AC97 device */
105	static struct ep93xx_ac97_info *ep93xx_ac97_info;
106
107	static struct ep93xx_pcm_dma_params ep93xx_ac97_pcm_out = {
108	.name = "ac97-pcm-out",
51e2cc0c	109	.dma_port = EP93XX_DMA_AAC1,
aa7e1b84 MW	110	};
	111
	112	static struct ep93xx_pcm_dma_params ep93xx_ac97_pcm_in = {
	113	.name = "ac97-pcm-in",
51e2cc0c	114	.dma_port = EP93XX_DMA_AAC1,
aa7e1b84 MW	115	};
	116
	117	static inline unsigned ep93xx_ac97_read_reg(struct ep93xx_ac97_info *info,
	118	unsigned reg)
	119	{
	120	return __raw_readl(info->regs + reg);
	121	}
	122
	123	static inline void ep93xx_ac97_write_reg(struct ep93xx_ac97_info *info,
	124	unsigned reg, unsigned val)
	125	{
	126	__raw_writel(val, info->regs + reg);
	127	}
	128
	129	static unsigned short ep93xx_ac97_read(struct snd_ac97 *ac97,
	130	unsigned short reg)
	131	{
	132	struct ep93xx_ac97_info *info = ep93xx_ac97_info;
	133	unsigned short val;
	134
	135	mutex_lock(&info->lock);
	136
	137	ep93xx_ac97_write_reg(info, AC97S1DATA, reg);
	138	ep93xx_ac97_write_reg(info, AC97IM, AC97_SLOT2RXVALID);
	139	if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT)) {
	140	dev_warn(info->dev, "timeout reading register %x\n", reg);
	141	mutex_unlock(&info->lock);
	142	return -ETIMEDOUT;
	143	}
	144	val = (unsigned short)ep93xx_ac97_read_reg(info, AC97S2DATA);
	145
	146	mutex_unlock(&info->lock);
	147	return val;
	148	}
	149
	150	static void ep93xx_ac97_write(struct snd_ac97 *ac97,
	151	unsigned short reg,
	152	unsigned short val)
	153	{
	154	struct ep93xx_ac97_info *info = ep93xx_ac97_info;
	155
	156	mutex_lock(&info->lock);
	157
	158	/*
	159	* Writes to the codec need to be done so that slot 2 is filled in
	160	* before slot 1.
	161	*/
	162	ep93xx_ac97_write_reg(info, AC97S2DATA, val);
	163	ep93xx_ac97_write_reg(info, AC97S1DATA, reg);
	164
	165	ep93xx_ac97_write_reg(info, AC97IM, AC97_SLOT2TXCOMPLETE);
	166	if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT))
	167	dev_warn(info->dev, "timeout writing register %x\n", reg);
	168
	169	mutex_unlock(&info->lock);
	170	}
	171
	172	static void ep93xx_ac97_warm_reset(struct snd_ac97 *ac97)
	173	{
	174	struct ep93xx_ac97_info *info = ep93xx_ac97_info;
	175
	176	mutex_lock(&info->lock);
	177
	178	/*
179	* We are assuming that before this functions gets called, the codec
180	* BIT_CLK is stopped by forcing the codec into powerdown mode. We can
181	* control the SYNC signal directly via AC97SYNC register. Using
182	* TIMEDSYNC the controller will keep the SYNC high > 1us.
183	*/
184	ep93xx_ac97_write_reg(info, AC97SYNC, AC97SYNC_TIMEDSYNC);
185	ep93xx_ac97_write_reg(info, AC97IM, AC97_CODECREADY);
186	if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT))
187	dev_warn(info->dev, "codec warm reset timeout\n");
188
189	mutex_unlock(&info->lock);
190	}
191
192	static void ep93xx_ac97_cold_reset(struct snd_ac97 *ac97)
193	{
194	struct ep93xx_ac97_info *info = ep93xx_ac97_info;
195
196	mutex_lock(&info->lock);
197
198	/*
199	* For doing cold reset, we disable the AC97 controller interface, clear
200	* WINT and CODECREADY bits, and finally enable the interface again.
201	*/
202	ep93xx_ac97_write_reg(info, AC97GCR, 0);
203	ep93xx_ac97_write_reg(info, AC97EOI, AC97EOI_CODECREADY \| AC97EOI_WINT);
204	ep93xx_ac97_write_reg(info, AC97GCR, AC97GCR_AC97IFE);
205
206	/*
207	* Now, assert the reset and wait for the codec to become ready.
208	*/
209	ep93xx_ac97_write_reg(info, AC97RESET, AC97RESET_TIMEDRESET);
210	ep93xx_ac97_write_reg(info, AC97IM, AC97_CODECREADY);
211	if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT))
212	dev_warn(info->dev, "codec cold reset timeout\n");
213
214	/*
215	* Give the codec some time to come fully out from the reset. This way
216	* we ensure that the subsequent reads/writes will work.
217	*/
218	usleep_range(15000, 20000);
219
220	mutex_unlock(&info->lock);
221	}
222
223	static irqreturn_t ep93xx_ac97_interrupt(int irq, void *dev_id)
224	{
225	struct ep93xx_ac97_info *info = dev_id;
226	unsigned status, mask;
227
228	/*
229	* Just mask out the interrupt and wake up the waiting thread.
230	* Interrupts are cleared via reading/writing to slot 1 & 2 registers by
231	* the waiting thread.
232	*/
233	status = ep93xx_ac97_read_reg(info, AC97GIS);
234	mask = ep93xx_ac97_read_reg(info, AC97IM);
235	mask &= ~status;
236	ep93xx_ac97_write_reg(info, AC97IM, mask);
237
238	complete(&info->done);
239	return IRQ_HANDLED;
240	}
241
242	struct snd_ac97_bus_ops soc_ac97_ops = {
243	.read = ep93xx_ac97_read,
244	.write = ep93xx_ac97_write,
245	.reset = ep93xx_ac97_cold_reset,
246	.warm_reset = ep93xx_ac97_warm_reset,
247	};
248	EXPORT_SYMBOL_GPL(soc_ac97_ops);
249
250	static int ep93xx_ac97_trigger(struct snd_pcm_substream *substream,
251	int cmd, struct snd_soc_dai *dai)
252	{
253	struct ep93xx_ac97_info *info = snd_soc_dai_get_drvdata(dai);
254	unsigned v = 0;
255
aa7e1b84 MW	256	switch (cmd) {
	257	case SNDRV_PCM_TRIGGER_START:
	258	case SNDRV_PCM_TRIGGER_RESUME:
	259	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	260	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
	261	/*
	262	* Enable compact mode, TX slots 3 & 4, and the TX FIFO
	263	* itself.
	264	*/
	265	v \|= AC97TXCR_CM;
	266	v \|= AC97TXCR_TX3 \| AC97TXCR_TX4;
	267	v \|= AC97TXCR_TEN;
	268	ep93xx_ac97_write_reg(info, AC97TXCR(1), v);
	269	} else {
	270	/*
	271	* Enable compact mode, RX slots 3 & 4, and the RX FIFO
	272	* itself.
	273	*/
	274	v \|= AC97RXCR_CM;
	275	v \|= AC97RXCR_RX3 \| AC97RXCR_RX4;
	276	v \|= AC97RXCR_REN;
	277	ep93xx_ac97_write_reg(info, AC97RXCR(1), v);
	278	}
	279	break;
	280
	281	case SNDRV_PCM_TRIGGER_STOP:
	282	case SNDRV_PCM_TRIGGER_SUSPEND:
	283	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	284	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
	285	/*
	286	* As per Cirrus EP93xx errata described below:
	287	*
	288	* http://www.cirrus.com/en/pubs/errata/ER667E2B.pdf
	289	*
	290	* we will wait for the TX FIFO to be empty before
	291	* clearing the TEN bit.
	292	*/
	293	unsigned long timeout = jiffies + AC97_TIMEOUT;
	294
	295	do {
	296	v = ep93xx_ac97_read_reg(info, AC97SR(1));
	297	if (time_after(jiffies, timeout)) {
	298	dev_warn(info->dev, "TX timeout\n");
	299	break;
	300	}
	301	} while (!(v & (AC97SR_TXFE \| AC97SR_TXUE)));
	302
	303	/* disable the TX FIFO */
	304	ep93xx_ac97_write_reg(info, AC97TXCR(1), 0);
	305	} else {
	306	/* disable the RX FIFO */
	307	ep93xx_ac97_write_reg(info, AC97RXCR(1), 0);
	308	}
	309	break;
	310
	311	default:
	312	dev_warn(info->dev, "unknown command %d\n", cmd);
	313	return -EINVAL;
	314	}
	315
	316	return 0;
	317	}
	318
	319	static int ep93xx_ac97_startup(struct snd_pcm_substream *substream,
320	struct snd_soc_dai *dai)
321	{
322	struct ep93xx_pcm_dma_params *dma_data;
323
324	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
325	dma_data = &ep93xx_ac97_pcm_out;
326	else
327	dma_data = &ep93xx_ac97_pcm_in;
328
329	snd_soc_dai_set_dma_data(dai, substream, dma_data);
330	return 0;
331	}
332
333	static struct snd_soc_dai_ops ep93xx_ac97_dai_ops = {
334	.startup = ep93xx_ac97_startup,
335	.trigger = ep93xx_ac97_trigger,
336	};
337
338	struct snd_soc_dai_driver ep93xx_ac97_dai = {
339	.name = "ep93xx-ac97",
340	.id = 0,
341	.ac97_control = 1,
342	.playback = {
343	.stream_name = "AC97 Playback",
344	.channels_min = 2,
345	.channels_max = 2,
346	.rates = SNDRV_PCM_RATE_8000_48000,
347	.formats = SNDRV_PCM_FMTBIT_S16_LE,
348	},
349	.capture = {
350	.stream_name = "AC97 Capture",
351	.channels_min = 2,
352	.channels_max = 2,
353	.rates = SNDRV_PCM_RATE_8000_48000,
354	.formats = SNDRV_PCM_FMTBIT_S16_LE,
355	},
356	.ops = &ep93xx_ac97_dai_ops,
357	};
358
359	static int __devinit ep93xx_ac97_probe(struct platform_device *pdev)
360	{
361	struct ep93xx_ac97_info *info;
362	int ret;
363
364	info = kzalloc(sizeof(struct ep93xx_ac97_info), GFP_KERNEL);
365	if (!info)
366	return -ENOMEM;
367
368	dev_set_drvdata(&pdev->dev, info);
369
370	mutex_init(&info->lock);
371	init_completion(&info->done);
372	info->dev = &pdev->dev;
373
374	info->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
375	if (!info->mem) {
376	ret = -ENXIO;
377	goto fail_free_info;
378	}
379
380	info->irq = platform_get_irq(pdev, 0);
381	if (!info->irq) {
382	ret = -ENXIO;
383	goto fail_free_info;
384	}
385
386	if (!request_mem_region(info->mem->start, resource_size(info->mem),
387	pdev->name)) {
388	ret = -EBUSY;
389	goto fail_free_info;
390	}
391
392	info->regs = ioremap(info->mem->start, resource_size(info->mem));
393	if (!info->regs) {
394	ret = -ENOMEM;
395	goto fail_release_mem;
396	}
397
398	ret = request_irq(info->irq, ep93xx_ac97_interrupt, IRQF_TRIGGER_HIGH,
399	pdev->name, info);
400	if (ret)
401	goto fail_unmap_mem;
402
403	ep93xx_ac97_info = info;
404	platform_set_drvdata(pdev, info);
405
406	ret = snd_soc_register_dai(&pdev->dev, &ep93xx_ac97_dai);
407	if (ret)
408	goto fail_free_irq;
409
410	return 0;
411
412	fail_free_irq:
413	platform_set_drvdata(pdev, NULL);
414	free_irq(info->irq, info);
415	fail_unmap_mem:
416	iounmap(info->regs);
417	fail_release_mem:
418	release_mem_region(info->mem->start, resource_size(info->mem));
419	fail_free_info:
420	kfree(info);
421
422	return ret;
423	}
424
425	static int __devexit ep93xx_ac97_remove(struct platform_device *pdev)
426	{
427	struct ep93xx_ac97_info *info = platform_get_drvdata(pdev);
428
429	snd_soc_unregister_dai(&pdev->dev);
430
431	/* disable the AC97 controller */
432	ep93xx_ac97_write_reg(info, AC97GCR, 0);
433
434	free_irq(info->irq, info);
435	iounmap(info->regs);
436	release_mem_region(info->mem->start, resource_size(info->mem));
437	platform_set_drvdata(pdev, NULL);
438	kfree(info);
439
440	return 0;
441	}
442
443	static struct platform_driver ep93xx_ac97_driver = {
444	.probe = ep93xx_ac97_probe,
445	.remove = __devexit_p(ep93xx_ac97_remove),
446	.driver = {
447	.name = "ep93xx-ac97",
448	.owner = THIS_MODULE,
449	},
450	};
451
452	static int __init ep93xx_ac97_init(void)
453	{
454	return platform_driver_register(&ep93xx_ac97_driver);
455	}
456	module_init(ep93xx_ac97_init);
457
458	static void __exit ep93xx_ac97_exit(void)
459	{
460	platform_driver_unregister(&ep93xx_ac97_driver);
461	}
462	module_exit(ep93xx_ac97_exit);
463
464	MODULE_DESCRIPTION("EP93xx AC97 ASoC Driver");
465	MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>");
466	MODULE_LICENSE("GPL");
467	MODULE_ALIAS("platform:ep93xx-ac97");