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1 | /* |
2 | * Freescale ASRC ALSA SoC Digital Audio Interface (DAI) driver | |
3 | * | |
4 | * Copyright (C) 2014 Freescale Semiconductor, Inc. | |
5 | * | |
6 | * Author: Nicolin Chen <nicoleotsuka@gmail.com> | |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public License | |
9 | * version 2. This program is licensed "as is" without any warranty of any | |
10 | * kind, whether express or implied. | |
11 | */ | |
12 | ||
13 | #include <linux/clk.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/dma-mapping.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/of_platform.h> | |
18 | #include <linux/platform_data/dma-imx.h> | |
19 | #include <linux/pm_runtime.h> | |
20 | #include <sound/dmaengine_pcm.h> | |
21 | #include <sound/pcm_params.h> | |
22 | ||
23 | #include "fsl_asrc.h" | |
24 | ||
25 | #define IDEAL_RATIO_DECIMAL_DEPTH 26 | |
26 | ||
27 | #define pair_err(fmt, ...) \ | |
28 | dev_err(&asrc_priv->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__) | |
29 | ||
30 | #define pair_dbg(fmt, ...) \ | |
31 | dev_dbg(&asrc_priv->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__) | |
32 | ||
33 | /* Sample rates are aligned with that defined in pcm.h file */ | |
34 | static const u8 process_option[][8][2] = { | |
35 | /* 32kHz 44.1kHz 48kHz 64kHz 88.2kHz 96kHz 176kHz 192kHz */ | |
36 | {{0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 5512Hz */ | |
37 | {{0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 8kHz */ | |
38 | {{0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 11025Hz */ | |
39 | {{0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 16kHz */ | |
40 | {{0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 22050Hz */ | |
41 | {{0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0},}, /* 32kHz */ | |
42 | {{0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0},}, /* 44.1kHz */ | |
43 | {{0, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0},}, /* 48kHz */ | |
44 | {{1, 2}, {0, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0},}, /* 64kHz */ | |
45 | {{1, 2}, {1, 2}, {1, 2}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1},}, /* 88.2kHz */ | |
46 | {{1, 2}, {1, 2}, {1, 2}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1},}, /* 96kHz */ | |
47 | {{2, 2}, {2, 2}, {2, 2}, {2, 1}, {2, 1}, {2, 1}, {2, 1}, {2, 1},}, /* 176kHz */ | |
48 | {{2, 2}, {2, 2}, {2, 2}, {2, 1}, {2, 1}, {2, 1}, {2, 1}, {2, 1},}, /* 192kHz */ | |
49 | }; | |
50 | ||
51 | /* Corresponding to process_option */ | |
52 | static int supported_input_rate[] = { | |
53 | 5512, 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 88200, | |
54 | 96000, 176400, 192000, | |
55 | }; | |
56 | ||
57 | static int supported_asrc_rate[] = { | |
58 | 32000, 44100, 48000, 64000, 88200, 96000, 176400, 192000, | |
59 | }; | |
60 | ||
61 | /** | |
62 | * The following tables map the relationship between asrc_inclk/asrc_outclk in | |
63 | * fsl_asrc.h and the registers of ASRCSR | |
64 | */ | |
65 | static unsigned char input_clk_map_imx35[] = { | |
66 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, | |
67 | }; | |
68 | ||
69 | static unsigned char output_clk_map_imx35[] = { | |
70 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, | |
71 | }; | |
72 | ||
73 | /* i.MX53 uses the same map for input and output */ | |
74 | static unsigned char input_clk_map_imx53[] = { | |
75 | /* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */ | |
76 | 0x0, 0x1, 0x2, 0x7, 0x4, 0x5, 0x6, 0x3, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xe, 0xd, | |
77 | }; | |
78 | ||
79 | static unsigned char output_clk_map_imx53[] = { | |
80 | /* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */ | |
81 | 0x8, 0x9, 0xa, 0x7, 0xc, 0x5, 0x6, 0xb, 0x0, 0x1, 0x2, 0x3, 0x4, 0xf, 0xe, 0xd, | |
82 | }; | |
83 | ||
84 | static unsigned char *clk_map[2]; | |
85 | ||
86 | /** | |
87 | * Request ASRC pair | |
88 | * | |
89 | * It assigns pair by the order of A->C->B because allocation of pair B, | |
90 | * within range [ANCA, ANCA+ANCB-1], depends on the channels of pair A | |
91 | * while pair A and pair C are comparatively independent. | |
92 | */ | |
93 | static int fsl_asrc_request_pair(int channels, struct fsl_asrc_pair *pair) | |
94 | { | |
95 | enum asrc_pair_index index = ASRC_INVALID_PAIR; | |
96 | struct fsl_asrc *asrc_priv = pair->asrc_priv; | |
97 | struct device *dev = &asrc_priv->pdev->dev; | |
98 | unsigned long lock_flags; | |
99 | int i, ret = 0; | |
100 | ||
101 | spin_lock_irqsave(&asrc_priv->lock, lock_flags); | |
102 | ||
103 | for (i = ASRC_PAIR_A; i < ASRC_PAIR_MAX_NUM; i++) { | |
104 | if (asrc_priv->pair[i] != NULL) | |
105 | continue; | |
106 | ||
107 | index = i; | |
108 | ||
109 | if (i != ASRC_PAIR_B) | |
110 | break; | |
111 | } | |
112 | ||
113 | if (index == ASRC_INVALID_PAIR) { | |
114 | dev_err(dev, "all pairs are busy now\n"); | |
115 | ret = -EBUSY; | |
116 | } else if (asrc_priv->channel_avail < channels) { | |
117 | dev_err(dev, "can't afford required channels: %d\n", channels); | |
118 | ret = -EINVAL; | |
119 | } else { | |
120 | asrc_priv->channel_avail -= channels; | |
121 | asrc_priv->pair[index] = pair; | |
122 | pair->channels = channels; | |
123 | pair->index = index; | |
124 | } | |
125 | ||
126 | spin_unlock_irqrestore(&asrc_priv->lock, lock_flags); | |
127 | ||
128 | return ret; | |
129 | } | |
130 | ||
131 | /** | |
132 | * Release ASRC pair | |
133 | * | |
134 | * It clears the resource from asrc_priv and releases the occupied channels. | |
135 | */ | |
136 | static void fsl_asrc_release_pair(struct fsl_asrc_pair *pair) | |
137 | { | |
138 | struct fsl_asrc *asrc_priv = pair->asrc_priv; | |
139 | enum asrc_pair_index index = pair->index; | |
140 | unsigned long lock_flags; | |
141 | ||
142 | /* Make sure the pair is disabled */ | |
143 | regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, | |
144 | ASRCTR_ASRCEi_MASK(index), 0); | |
145 | ||
146 | spin_lock_irqsave(&asrc_priv->lock, lock_flags); | |
147 | ||
148 | asrc_priv->channel_avail += pair->channels; | |
149 | asrc_priv->pair[index] = NULL; | |
150 | pair->error = 0; | |
151 | ||
152 | spin_unlock_irqrestore(&asrc_priv->lock, lock_flags); | |
153 | } | |
154 | ||
155 | /** | |
156 | * Configure input and output thresholds | |
157 | */ | |
158 | static void fsl_asrc_set_watermarks(struct fsl_asrc_pair *pair, u32 in, u32 out) | |
159 | { | |
160 | struct fsl_asrc *asrc_priv = pair->asrc_priv; | |
161 | enum asrc_pair_index index = pair->index; | |
162 | ||
163 | regmap_update_bits(asrc_priv->regmap, REG_ASRMCR(index), | |
164 | ASRMCRi_EXTTHRSHi_MASK | | |
165 | ASRMCRi_INFIFO_THRESHOLD_MASK | | |
166 | ASRMCRi_OUTFIFO_THRESHOLD_MASK, | |
167 | ASRMCRi_EXTTHRSHi | | |
168 | ASRMCRi_INFIFO_THRESHOLD(in) | | |
169 | ASRMCRi_OUTFIFO_THRESHOLD(out)); | |
170 | } | |
171 | ||
172 | /** | |
173 | * Calculate the total divisor between asrck clock rate and sample rate | |
174 | * | |
175 | * It follows the formula clk_rate = samplerate * (2 ^ prescaler) * divider | |
176 | */ | |
177 | static u32 fsl_asrc_cal_asrck_divisor(struct fsl_asrc_pair *pair, u32 div) | |
178 | { | |
179 | u32 ps; | |
180 | ||
181 | /* Calculate the divisors: prescaler [2^0, 2^7], divder [1, 8] */ | |
182 | for (ps = 0; div > 8; ps++) | |
183 | div >>= 1; | |
184 | ||
185 | return ((div - 1) << ASRCDRi_AxCPi_WIDTH) | ps; | |
186 | } | |
187 | ||
188 | /** | |
189 | * Calculate and set the ratio for Ideal Ratio mode only | |
190 | * | |
191 | * The ratio is a 32-bit fixed point value with 26 fractional bits. | |
192 | */ | |
193 | static int fsl_asrc_set_ideal_ratio(struct fsl_asrc_pair *pair, | |
194 | int inrate, int outrate) | |
195 | { | |
196 | struct fsl_asrc *asrc_priv = pair->asrc_priv; | |
197 | enum asrc_pair_index index = pair->index; | |
198 | unsigned long ratio; | |
199 | int i; | |
200 | ||
201 | if (!outrate) { | |
202 | pair_err("output rate should not be zero\n"); | |
203 | return -EINVAL; | |
204 | } | |
205 | ||
206 | /* Calculate the intergal part of the ratio */ | |
207 | ratio = (inrate / outrate) << IDEAL_RATIO_DECIMAL_DEPTH; | |
208 | ||
209 | /* ... and then the 26 depth decimal part */ | |
210 | inrate %= outrate; | |
211 | ||
212 | for (i = 1; i <= IDEAL_RATIO_DECIMAL_DEPTH; i++) { | |
213 | inrate <<= 1; | |
214 | ||
215 | if (inrate < outrate) | |
216 | continue; | |
217 | ||
218 | ratio |= 1 << (IDEAL_RATIO_DECIMAL_DEPTH - i); | |
219 | inrate -= outrate; | |
220 | ||
221 | if (!inrate) | |
222 | break; | |
223 | } | |
224 | ||
225 | regmap_write(asrc_priv->regmap, REG_ASRIDRL(index), ratio); | |
226 | regmap_write(asrc_priv->regmap, REG_ASRIDRH(index), ratio >> 24); | |
227 | ||
228 | return 0; | |
229 | } | |
230 | ||
231 | /** | |
232 | * Configure the assigned ASRC pair | |
233 | * | |
234 | * It configures those ASRC registers according to a configuration instance | |
235 | * of struct asrc_config which includes in/output sample rate, width, channel | |
236 | * and clock settings. | |
237 | */ | |
238 | static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair) | |
239 | { | |
240 | struct asrc_config *config = pair->config; | |
241 | struct fsl_asrc *asrc_priv = pair->asrc_priv; | |
242 | enum asrc_pair_index index = pair->index; | |
243 | u32 inrate = config->input_sample_rate, indiv; | |
244 | u32 outrate = config->output_sample_rate, outdiv; | |
245 | bool ideal = config->inclk == INCLK_NONE; | |
246 | u32 clk_index[2], div[2]; | |
247 | int in, out, channels; | |
248 | struct clk *clk; | |
249 | ||
250 | if (!config) { | |
251 | pair_err("invalid pair config\n"); | |
252 | return -EINVAL; | |
253 | } | |
254 | ||
255 | /* Validate channels */ | |
256 | if (config->channel_num < 1 || config->channel_num > 10) { | |
257 | pair_err("does not support %d channels\n", config->channel_num); | |
258 | return -EINVAL; | |
259 | } | |
260 | ||
261 | /* Validate output width */ | |
262 | if (config->output_word_width == ASRC_WIDTH_8_BIT) { | |
263 | pair_err("does not support 8bit width output\n"); | |
264 | return -EINVAL; | |
265 | } | |
266 | ||
267 | /* Validate input and output sample rates */ | |
268 | for (in = 0; in < ARRAY_SIZE(supported_input_rate); in++) | |
269 | if (inrate == supported_input_rate[in]) | |
270 | break; | |
271 | ||
272 | if (in == ARRAY_SIZE(supported_input_rate)) { | |
273 | pair_err("unsupported input sample rate: %dHz\n", inrate); | |
274 | return -EINVAL; | |
275 | } | |
276 | ||
277 | for (out = 0; out < ARRAY_SIZE(supported_asrc_rate); out++) | |
278 | if (outrate == supported_asrc_rate[out]) | |
279 | break; | |
280 | ||
281 | if (out == ARRAY_SIZE(supported_asrc_rate)) { | |
282 | pair_err("unsupported output sample rate: %dHz\n", outrate); | |
283 | return -EINVAL; | |
284 | } | |
285 | ||
286 | /* Validate input and output clock sources */ | |
287 | clk_index[IN] = clk_map[IN][config->inclk]; | |
288 | clk_index[OUT] = clk_map[OUT][config->outclk]; | |
289 | ||
290 | /* We only have output clock for ideal ratio mode */ | |
291 | clk = asrc_priv->asrck_clk[clk_index[ideal ? OUT : IN]]; | |
292 | ||
293 | div[IN] = clk_get_rate(clk) / inrate; | |
294 | if (div[IN] == 0) { | |
295 | pair_err("failed to support input sample rate %dHz by asrck_%x\n", | |
296 | inrate, clk_index[ideal ? OUT : IN]); | |
297 | return -EINVAL; | |
298 | } | |
299 | ||
300 | clk = asrc_priv->asrck_clk[clk_index[OUT]]; | |
301 | ||
302 | /* Use fixed output rate for Ideal Ratio mode (INCLK_NONE) */ | |
303 | if (ideal) | |
304 | div[OUT] = clk_get_rate(clk) / IDEAL_RATIO_RATE; | |
305 | else | |
306 | div[OUT] = clk_get_rate(clk) / outrate; | |
307 | ||
308 | if (div[OUT] == 0) { | |
309 | pair_err("failed to support output sample rate %dHz by asrck_%x\n", | |
310 | outrate, clk_index[OUT]); | |
311 | return -EINVAL; | |
312 | } | |
313 | ||
314 | /* Set the channel number */ | |
315 | channels = config->channel_num; | |
316 | ||
317 | if (asrc_priv->channel_bits < 4) | |
318 | channels /= 2; | |
319 | ||
320 | /* Update channels for current pair */ | |
321 | regmap_update_bits(asrc_priv->regmap, REG_ASRCNCR, | |
322 | ASRCNCR_ANCi_MASK(index, asrc_priv->channel_bits), | |
323 | ASRCNCR_ANCi(index, channels, asrc_priv->channel_bits)); | |
324 | ||
325 | /* Default setting: Automatic selection for processing mode */ | |
326 | regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, | |
327 | ASRCTR_ATSi_MASK(index), ASRCTR_ATS(index)); | |
328 | regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, | |
329 | ASRCTR_USRi_MASK(index), 0); | |
330 | ||
331 | /* Set the input and output clock sources */ | |
332 | regmap_update_bits(asrc_priv->regmap, REG_ASRCSR, | |
333 | ASRCSR_AICSi_MASK(index) | ASRCSR_AOCSi_MASK(index), | |
334 | ASRCSR_AICS(index, clk_index[IN]) | | |
335 | ASRCSR_AOCS(index, clk_index[OUT])); | |
336 | ||
337 | /* Calculate the input clock divisors */ | |
338 | indiv = fsl_asrc_cal_asrck_divisor(pair, div[IN]); | |
339 | outdiv = fsl_asrc_cal_asrck_divisor(pair, div[OUT]); | |
340 | ||
341 | /* Suppose indiv and outdiv includes prescaler, so add its MASK too */ | |
342 | regmap_update_bits(asrc_priv->regmap, REG_ASRCDR(index), | |
343 | ASRCDRi_AOCPi_MASK(index) | ASRCDRi_AICPi_MASK(index) | | |
344 | ASRCDRi_AOCDi_MASK(index) | ASRCDRi_AICDi_MASK(index), | |
345 | ASRCDRi_AOCP(index, outdiv) | ASRCDRi_AICP(index, indiv)); | |
346 | ||
347 | /* Implement word_width configurations */ | |
348 | regmap_update_bits(asrc_priv->regmap, REG_ASRMCR1(index), | |
349 | ASRMCR1i_OW16_MASK | ASRMCR1i_IWD_MASK, | |
350 | ASRMCR1i_OW16(config->output_word_width) | | |
351 | ASRMCR1i_IWD(config->input_word_width)); | |
352 | ||
353 | /* Enable BUFFER STALL */ | |
354 | regmap_update_bits(asrc_priv->regmap, REG_ASRMCR(index), | |
355 | ASRMCRi_BUFSTALLi_MASK, ASRMCRi_BUFSTALLi); | |
356 | ||
357 | /* Set default thresholds for input and output FIFO */ | |
358 | fsl_asrc_set_watermarks(pair, ASRC_INPUTFIFO_THRESHOLD, | |
359 | ASRC_INPUTFIFO_THRESHOLD); | |
360 | ||
361 | /* Configure the followings only for Ideal Ratio mode */ | |
362 | if (!ideal) | |
363 | return 0; | |
364 | ||
365 | /* Clear ASTSx bit to use Ideal Ratio mode */ | |
366 | regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, | |
367 | ASRCTR_ATSi_MASK(index), 0); | |
368 | ||
369 | /* Enable Ideal Ratio mode */ | |
370 | regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, | |
371 | ASRCTR_IDRi_MASK(index) | ASRCTR_USRi_MASK(index), | |
372 | ASRCTR_IDR(index) | ASRCTR_USR(index)); | |
373 | ||
374 | /* Apply configurations for pre- and post-processing */ | |
375 | regmap_update_bits(asrc_priv->regmap, REG_ASRCFG, | |
376 | ASRCFG_PREMODi_MASK(index) | ASRCFG_POSTMODi_MASK(index), | |
377 | ASRCFG_PREMOD(index, process_option[in][out][0]) | | |
378 | ASRCFG_POSTMOD(index, process_option[in][out][1])); | |
379 | ||
380 | return fsl_asrc_set_ideal_ratio(pair, inrate, outrate); | |
381 | } | |
382 | ||
383 | /** | |
384 | * Start the assigned ASRC pair | |
385 | * | |
386 | * It enables the assigned pair and makes it stopped at the stall level. | |
387 | */ | |
388 | static void fsl_asrc_start_pair(struct fsl_asrc_pair *pair) | |
389 | { | |
390 | struct fsl_asrc *asrc_priv = pair->asrc_priv; | |
391 | enum asrc_pair_index index = pair->index; | |
392 | int reg, retry = 10, i; | |
393 | ||
394 | /* Enable the current pair */ | |
395 | regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, | |
396 | ASRCTR_ASRCEi_MASK(index), ASRCTR_ASRCE(index)); | |
397 | ||
398 | /* Wait for status of initialization */ | |
399 | do { | |
400 | udelay(5); | |
401 | regmap_read(asrc_priv->regmap, REG_ASRCFG, ®); | |
402 | reg &= ASRCFG_INIRQi_MASK(index); | |
403 | } while (!reg && --retry); | |
404 | ||
405 | /* Make the input fifo to ASRC STALL level */ | |
406 | regmap_read(asrc_priv->regmap, REG_ASRCNCR, ®); | |
407 | for (i = 0; i < pair->channels * 4; i++) | |
408 | regmap_write(asrc_priv->regmap, REG_ASRDI(index), 0); | |
409 | ||
410 | /* Enable overload interrupt */ | |
411 | regmap_write(asrc_priv->regmap, REG_ASRIER, ASRIER_AOLIE); | |
412 | } | |
413 | ||
414 | /** | |
415 | * Stop the assigned ASRC pair | |
416 | */ | |
417 | static void fsl_asrc_stop_pair(struct fsl_asrc_pair *pair) | |
418 | { | |
419 | struct fsl_asrc *asrc_priv = pair->asrc_priv; | |
420 | enum asrc_pair_index index = pair->index; | |
421 | ||
422 | /* Stop the current pair */ | |
423 | regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, | |
424 | ASRCTR_ASRCEi_MASK(index), 0); | |
425 | } | |
426 | ||
427 | /** | |
428 | * Get DMA channel according to the pair and direction. | |
429 | */ | |
430 | struct dma_chan *fsl_asrc_get_dma_channel(struct fsl_asrc_pair *pair, bool dir) | |
431 | { | |
432 | struct fsl_asrc *asrc_priv = pair->asrc_priv; | |
433 | enum asrc_pair_index index = pair->index; | |
434 | char name[4]; | |
435 | ||
436 | sprintf(name, "%cx%c", dir == IN ? 'r' : 't', index + 'a'); | |
437 | ||
438 | return dma_request_slave_channel(&asrc_priv->pdev->dev, name); | |
439 | } | |
440 | EXPORT_SYMBOL_GPL(fsl_asrc_get_dma_channel); | |
441 | ||
442 | static int fsl_asrc_dai_hw_params(struct snd_pcm_substream *substream, | |
443 | struct snd_pcm_hw_params *params, | |
444 | struct snd_soc_dai *dai) | |
445 | { | |
446 | struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai); | |
447 | int width = snd_pcm_format_width(params_format(params)); | |
448 | struct snd_pcm_runtime *runtime = substream->runtime; | |
449 | struct fsl_asrc_pair *pair = runtime->private_data; | |
450 | unsigned int channels = params_channels(params); | |
451 | unsigned int rate = params_rate(params); | |
452 | struct asrc_config config; | |
453 | int word_width, ret; | |
454 | ||
455 | ret = fsl_asrc_request_pair(channels, pair); | |
456 | if (ret) { | |
457 | dev_err(dai->dev, "fail to request asrc pair\n"); | |
458 | return ret; | |
459 | } | |
460 | ||
461 | pair->config = &config; | |
462 | ||
463 | if (width == 16) | |
464 | width = ASRC_WIDTH_16_BIT; | |
465 | else | |
466 | width = ASRC_WIDTH_24_BIT; | |
467 | ||
468 | if (asrc_priv->asrc_width == 16) | |
469 | word_width = ASRC_WIDTH_16_BIT; | |
470 | else | |
471 | word_width = ASRC_WIDTH_24_BIT; | |
472 | ||
473 | config.pair = pair->index; | |
474 | config.channel_num = channels; | |
475 | config.inclk = INCLK_NONE; | |
476 | config.outclk = OUTCLK_ASRCK1_CLK; | |
477 | ||
478 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
479 | config.input_word_width = width; | |
480 | config.output_word_width = word_width; | |
481 | config.input_sample_rate = rate; | |
482 | config.output_sample_rate = asrc_priv->asrc_rate; | |
483 | } else { | |
484 | config.input_word_width = word_width; | |
485 | config.output_word_width = width; | |
486 | config.input_sample_rate = asrc_priv->asrc_rate; | |
487 | config.output_sample_rate = rate; | |
488 | } | |
489 | ||
490 | ret = fsl_asrc_config_pair(pair); | |
491 | if (ret) { | |
492 | dev_err(dai->dev, "fail to config asrc pair\n"); | |
493 | return ret; | |
494 | } | |
495 | ||
496 | return 0; | |
497 | } | |
498 | ||
499 | static int fsl_asrc_dai_hw_free(struct snd_pcm_substream *substream, | |
500 | struct snd_soc_dai *dai) | |
501 | { | |
502 | struct snd_pcm_runtime *runtime = substream->runtime; | |
503 | struct fsl_asrc_pair *pair = runtime->private_data; | |
504 | ||
505 | if (pair) | |
506 | fsl_asrc_release_pair(pair); | |
507 | ||
508 | return 0; | |
509 | } | |
510 | ||
511 | static int fsl_asrc_dai_trigger(struct snd_pcm_substream *substream, int cmd, | |
512 | struct snd_soc_dai *dai) | |
513 | { | |
514 | struct snd_pcm_runtime *runtime = substream->runtime; | |
515 | struct fsl_asrc_pair *pair = runtime->private_data; | |
516 | ||
517 | switch (cmd) { | |
518 | case SNDRV_PCM_TRIGGER_START: | |
519 | case SNDRV_PCM_TRIGGER_RESUME: | |
520 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
521 | fsl_asrc_start_pair(pair); | |
522 | break; | |
523 | case SNDRV_PCM_TRIGGER_STOP: | |
524 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
525 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
526 | fsl_asrc_stop_pair(pair); | |
527 | break; | |
528 | default: | |
529 | return -EINVAL; | |
530 | } | |
531 | ||
532 | return 0; | |
533 | } | |
534 | ||
535 | static struct snd_soc_dai_ops fsl_asrc_dai_ops = { | |
536 | .hw_params = fsl_asrc_dai_hw_params, | |
537 | .hw_free = fsl_asrc_dai_hw_free, | |
538 | .trigger = fsl_asrc_dai_trigger, | |
539 | }; | |
540 | ||
541 | static int fsl_asrc_dai_probe(struct snd_soc_dai *dai) | |
542 | { | |
543 | struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai); | |
544 | ||
545 | snd_soc_dai_init_dma_data(dai, &asrc_priv->dma_params_tx, | |
546 | &asrc_priv->dma_params_rx); | |
547 | ||
548 | return 0; | |
549 | } | |
550 | ||
551 | #define FSL_ASRC_RATES SNDRV_PCM_RATE_8000_192000 | |
552 | #define FSL_ASRC_FORMATS (SNDRV_PCM_FMTBIT_S24_LE | \ | |
553 | SNDRV_PCM_FMTBIT_S16_LE | \ | |
d526416c | 554 | SNDRV_PCM_FMTBIT_S20_3LE) |
3117bb31 NC |
555 | |
556 | static struct snd_soc_dai_driver fsl_asrc_dai = { | |
557 | .probe = fsl_asrc_dai_probe, | |
558 | .playback = { | |
559 | .stream_name = "ASRC-Playback", | |
560 | .channels_min = 1, | |
561 | .channels_max = 10, | |
562 | .rates = FSL_ASRC_RATES, | |
563 | .formats = FSL_ASRC_FORMATS, | |
564 | }, | |
565 | .capture = { | |
566 | .stream_name = "ASRC-Capture", | |
567 | .channels_min = 1, | |
568 | .channels_max = 10, | |
569 | .rates = FSL_ASRC_RATES, | |
570 | .formats = FSL_ASRC_FORMATS, | |
571 | }, | |
572 | .ops = &fsl_asrc_dai_ops, | |
573 | }; | |
574 | ||
575 | static const struct snd_soc_component_driver fsl_asrc_component = { | |
576 | .name = "fsl-asrc-dai", | |
577 | }; | |
578 | ||
579 | static bool fsl_asrc_readable_reg(struct device *dev, unsigned int reg) | |
580 | { | |
581 | switch (reg) { | |
582 | case REG_ASRCTR: | |
583 | case REG_ASRIER: | |
584 | case REG_ASRCNCR: | |
585 | case REG_ASRCFG: | |
586 | case REG_ASRCSR: | |
587 | case REG_ASRCDR1: | |
588 | case REG_ASRCDR2: | |
589 | case REG_ASRSTR: | |
590 | case REG_ASRPM1: | |
591 | case REG_ASRPM2: | |
592 | case REG_ASRPM3: | |
593 | case REG_ASRPM4: | |
594 | case REG_ASRPM5: | |
595 | case REG_ASRTFR1: | |
596 | case REG_ASRCCR: | |
597 | case REG_ASRDOA: | |
598 | case REG_ASRDOB: | |
599 | case REG_ASRDOC: | |
600 | case REG_ASRIDRHA: | |
601 | case REG_ASRIDRLA: | |
602 | case REG_ASRIDRHB: | |
603 | case REG_ASRIDRLB: | |
604 | case REG_ASRIDRHC: | |
605 | case REG_ASRIDRLC: | |
606 | case REG_ASR76K: | |
607 | case REG_ASR56K: | |
608 | case REG_ASRMCRA: | |
609 | case REG_ASRFSTA: | |
610 | case REG_ASRMCRB: | |
611 | case REG_ASRFSTB: | |
612 | case REG_ASRMCRC: | |
613 | case REG_ASRFSTC: | |
614 | case REG_ASRMCR1A: | |
615 | case REG_ASRMCR1B: | |
616 | case REG_ASRMCR1C: | |
617 | return true; | |
618 | default: | |
619 | return false; | |
620 | } | |
621 | } | |
622 | ||
623 | static bool fsl_asrc_volatile_reg(struct device *dev, unsigned int reg) | |
624 | { | |
625 | switch (reg) { | |
626 | case REG_ASRSTR: | |
627 | case REG_ASRDIA: | |
628 | case REG_ASRDIB: | |
629 | case REG_ASRDIC: | |
630 | case REG_ASRDOA: | |
631 | case REG_ASRDOB: | |
632 | case REG_ASRDOC: | |
633 | case REG_ASRFSTA: | |
634 | case REG_ASRFSTB: | |
635 | case REG_ASRFSTC: | |
636 | case REG_ASRCFG: | |
637 | return true; | |
638 | default: | |
639 | return false; | |
640 | } | |
641 | } | |
642 | ||
643 | static bool fsl_asrc_writeable_reg(struct device *dev, unsigned int reg) | |
644 | { | |
645 | switch (reg) { | |
646 | case REG_ASRCTR: | |
647 | case REG_ASRIER: | |
648 | case REG_ASRCNCR: | |
649 | case REG_ASRCFG: | |
650 | case REG_ASRCSR: | |
651 | case REG_ASRCDR1: | |
652 | case REG_ASRCDR2: | |
653 | case REG_ASRSTR: | |
654 | case REG_ASRPM1: | |
655 | case REG_ASRPM2: | |
656 | case REG_ASRPM3: | |
657 | case REG_ASRPM4: | |
658 | case REG_ASRPM5: | |
659 | case REG_ASRTFR1: | |
660 | case REG_ASRCCR: | |
661 | case REG_ASRDIA: | |
662 | case REG_ASRDIB: | |
663 | case REG_ASRDIC: | |
664 | case REG_ASRIDRHA: | |
665 | case REG_ASRIDRLA: | |
666 | case REG_ASRIDRHB: | |
667 | case REG_ASRIDRLB: | |
668 | case REG_ASRIDRHC: | |
669 | case REG_ASRIDRLC: | |
670 | case REG_ASR76K: | |
671 | case REG_ASR56K: | |
672 | case REG_ASRMCRA: | |
673 | case REG_ASRMCRB: | |
674 | case REG_ASRMCRC: | |
675 | case REG_ASRMCR1A: | |
676 | case REG_ASRMCR1B: | |
677 | case REG_ASRMCR1C: | |
678 | return true; | |
679 | default: | |
680 | return false; | |
681 | } | |
682 | } | |
683 | ||
684 | static struct regmap_config fsl_asrc_regmap_config = { | |
685 | .reg_bits = 32, | |
686 | .reg_stride = 4, | |
687 | .val_bits = 32, | |
688 | ||
689 | .max_register = REG_ASRMCR1C, | |
690 | .readable_reg = fsl_asrc_readable_reg, | |
691 | .volatile_reg = fsl_asrc_volatile_reg, | |
692 | .writeable_reg = fsl_asrc_writeable_reg, | |
693 | .cache_type = REGCACHE_RBTREE, | |
694 | }; | |
695 | ||
696 | /** | |
697 | * Initialize ASRC registers with a default configurations | |
698 | */ | |
699 | static int fsl_asrc_init(struct fsl_asrc *asrc_priv) | |
700 | { | |
701 | /* Halt ASRC internal FP when input FIFO needs data for pair A, B, C */ | |
702 | regmap_write(asrc_priv->regmap, REG_ASRCTR, ASRCTR_ASRCEN); | |
703 | ||
704 | /* Disable interrupt by default */ | |
705 | regmap_write(asrc_priv->regmap, REG_ASRIER, 0x0); | |
706 | ||
707 | /* Apply recommended settings for parameters from Reference Manual */ | |
708 | regmap_write(asrc_priv->regmap, REG_ASRPM1, 0x7fffff); | |
709 | regmap_write(asrc_priv->regmap, REG_ASRPM2, 0x255555); | |
710 | regmap_write(asrc_priv->regmap, REG_ASRPM3, 0xff7280); | |
711 | regmap_write(asrc_priv->regmap, REG_ASRPM4, 0xff7280); | |
712 | regmap_write(asrc_priv->regmap, REG_ASRPM5, 0xff7280); | |
713 | ||
714 | /* Base address for task queue FIFO. Set to 0x7C */ | |
715 | regmap_update_bits(asrc_priv->regmap, REG_ASRTFR1, | |
716 | ASRTFR1_TF_BASE_MASK, ASRTFR1_TF_BASE(0xfc)); | |
717 | ||
718 | /* Set the processing clock for 76KHz to 133M */ | |
719 | regmap_write(asrc_priv->regmap, REG_ASR76K, 0x06D6); | |
720 | ||
721 | /* Set the processing clock for 56KHz to 133M */ | |
722 | return regmap_write(asrc_priv->regmap, REG_ASR56K, 0x0947); | |
723 | } | |
724 | ||
725 | /** | |
726 | * Interrupt handler for ASRC | |
727 | */ | |
728 | static irqreturn_t fsl_asrc_isr(int irq, void *dev_id) | |
729 | { | |
730 | struct fsl_asrc *asrc_priv = (struct fsl_asrc *)dev_id; | |
731 | struct device *dev = &asrc_priv->pdev->dev; | |
732 | enum asrc_pair_index index; | |
733 | u32 status; | |
734 | ||
735 | regmap_read(asrc_priv->regmap, REG_ASRSTR, &status); | |
736 | ||
737 | /* Clean overload error */ | |
738 | regmap_write(asrc_priv->regmap, REG_ASRSTR, ASRSTR_AOLE); | |
739 | ||
740 | /* | |
741 | * We here use dev_dbg() for all exceptions because ASRC itself does | |
742 | * not care if FIFO overflowed or underrun while a warning in the | |
743 | * interrupt would result a ridged conversion. | |
744 | */ | |
745 | for (index = ASRC_PAIR_A; index < ASRC_PAIR_MAX_NUM; index++) { | |
746 | if (!asrc_priv->pair[index]) | |
747 | continue; | |
748 | ||
749 | if (status & ASRSTR_ATQOL) { | |
750 | asrc_priv->pair[index]->error |= ASRC_TASK_Q_OVERLOAD; | |
751 | dev_dbg(dev, "ASRC Task Queue FIFO overload\n"); | |
752 | } | |
753 | ||
754 | if (status & ASRSTR_AOOL(index)) { | |
755 | asrc_priv->pair[index]->error |= ASRC_OUTPUT_TASK_OVERLOAD; | |
756 | pair_dbg("Output Task Overload\n"); | |
757 | } | |
758 | ||
759 | if (status & ASRSTR_AIOL(index)) { | |
760 | asrc_priv->pair[index]->error |= ASRC_INPUT_TASK_OVERLOAD; | |
761 | pair_dbg("Input Task Overload\n"); | |
762 | } | |
763 | ||
764 | if (status & ASRSTR_AODO(index)) { | |
765 | asrc_priv->pair[index]->error |= ASRC_OUTPUT_BUFFER_OVERFLOW; | |
766 | pair_dbg("Output Data Buffer has overflowed\n"); | |
767 | } | |
768 | ||
769 | if (status & ASRSTR_AIDU(index)) { | |
770 | asrc_priv->pair[index]->error |= ASRC_INPUT_BUFFER_UNDERRUN; | |
771 | pair_dbg("Input Data Buffer has underflowed\n"); | |
772 | } | |
773 | } | |
774 | ||
775 | return IRQ_HANDLED; | |
776 | } | |
777 | ||
778 | static int fsl_asrc_probe(struct platform_device *pdev) | |
779 | { | |
780 | struct device_node *np = pdev->dev.of_node; | |
781 | struct fsl_asrc *asrc_priv; | |
782 | struct resource *res; | |
783 | void __iomem *regs; | |
784 | int irq, ret, i; | |
785 | char tmp[16]; | |
786 | ||
787 | asrc_priv = devm_kzalloc(&pdev->dev, sizeof(*asrc_priv), GFP_KERNEL); | |
788 | if (!asrc_priv) | |
789 | return -ENOMEM; | |
790 | ||
791 | asrc_priv->pdev = pdev; | |
792 | strcpy(asrc_priv->name, np->name); | |
793 | ||
794 | /* Get the addresses and IRQ */ | |
795 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
796 | regs = devm_ioremap_resource(&pdev->dev, res); | |
797 | if (IS_ERR(regs)) | |
798 | return PTR_ERR(regs); | |
799 | ||
800 | asrc_priv->paddr = res->start; | |
801 | ||
802 | /* Register regmap and let it prepare core clock */ | |
803 | if (of_property_read_bool(np, "big-endian")) | |
804 | fsl_asrc_regmap_config.val_format_endian = REGMAP_ENDIAN_BIG; | |
805 | ||
806 | asrc_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "mem", regs, | |
807 | &fsl_asrc_regmap_config); | |
808 | if (IS_ERR(asrc_priv->regmap)) { | |
809 | dev_err(&pdev->dev, "failed to init regmap\n"); | |
810 | return PTR_ERR(asrc_priv->regmap); | |
811 | } | |
812 | ||
813 | irq = platform_get_irq(pdev, 0); | |
814 | if (irq < 0) { | |
815 | dev_err(&pdev->dev, "no irq for node %s\n", np->full_name); | |
816 | return irq; | |
817 | } | |
818 | ||
819 | ret = devm_request_irq(&pdev->dev, irq, fsl_asrc_isr, 0, | |
820 | asrc_priv->name, asrc_priv); | |
821 | if (ret) { | |
822 | dev_err(&pdev->dev, "failed to claim irq %u: %d\n", irq, ret); | |
823 | return ret; | |
824 | } | |
825 | ||
826 | asrc_priv->mem_clk = devm_clk_get(&pdev->dev, "mem"); | |
827 | if (IS_ERR(asrc_priv->mem_clk)) { | |
828 | dev_err(&pdev->dev, "failed to get mem clock\n"); | |
829 | return PTR_ERR(asrc_priv->ipg_clk); | |
830 | } | |
831 | ||
832 | asrc_priv->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); | |
833 | if (IS_ERR(asrc_priv->ipg_clk)) { | |
834 | dev_err(&pdev->dev, "failed to get ipg clock\n"); | |
835 | return PTR_ERR(asrc_priv->ipg_clk); | |
836 | } | |
837 | ||
838 | for (i = 0; i < ASRC_CLK_MAX_NUM; i++) { | |
839 | sprintf(tmp, "asrck_%x", i); | |
840 | asrc_priv->asrck_clk[i] = devm_clk_get(&pdev->dev, tmp); | |
841 | if (IS_ERR(asrc_priv->asrck_clk[i])) { | |
842 | dev_err(&pdev->dev, "failed to get %s clock\n", tmp); | |
843 | return PTR_ERR(asrc_priv->asrck_clk[i]); | |
844 | } | |
845 | } | |
846 | ||
847 | if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx35-asrc")) { | |
848 | asrc_priv->channel_bits = 3; | |
849 | clk_map[IN] = input_clk_map_imx35; | |
850 | clk_map[OUT] = output_clk_map_imx35; | |
851 | } else { | |
852 | asrc_priv->channel_bits = 4; | |
853 | clk_map[IN] = input_clk_map_imx53; | |
854 | clk_map[OUT] = output_clk_map_imx53; | |
855 | } | |
856 | ||
857 | ret = fsl_asrc_init(asrc_priv); | |
858 | if (ret) { | |
859 | dev_err(&pdev->dev, "failed to init asrc %d\n", ret); | |
860 | return -EINVAL; | |
861 | } | |
862 | ||
863 | asrc_priv->channel_avail = 10; | |
864 | ||
865 | ret = of_property_read_u32(np, "fsl,asrc-rate", | |
866 | &asrc_priv->asrc_rate); | |
867 | if (ret) { | |
868 | dev_err(&pdev->dev, "failed to get output rate\n"); | |
869 | return -EINVAL; | |
870 | } | |
871 | ||
872 | ret = of_property_read_u32(np, "fsl,asrc-width", | |
873 | &asrc_priv->asrc_width); | |
874 | if (ret) { | |
875 | dev_err(&pdev->dev, "failed to get output width\n"); | |
876 | return -EINVAL; | |
877 | } | |
878 | ||
879 | if (asrc_priv->asrc_width != 16 && asrc_priv->asrc_width != 24) { | |
880 | dev_warn(&pdev->dev, "unsupported width, switching to 24bit\n"); | |
881 | asrc_priv->asrc_width = 24; | |
882 | } | |
883 | ||
884 | platform_set_drvdata(pdev, asrc_priv); | |
885 | pm_runtime_enable(&pdev->dev); | |
886 | spin_lock_init(&asrc_priv->lock); | |
887 | ||
888 | ret = devm_snd_soc_register_component(&pdev->dev, &fsl_asrc_component, | |
889 | &fsl_asrc_dai, 1); | |
890 | if (ret) { | |
891 | dev_err(&pdev->dev, "failed to register ASoC DAI\n"); | |
892 | return ret; | |
893 | } | |
894 | ||
895 | ret = devm_snd_soc_register_platform(&pdev->dev, &fsl_asrc_platform); | |
896 | if (ret) { | |
897 | dev_err(&pdev->dev, "failed to register ASoC platform\n"); | |
898 | return ret; | |
899 | } | |
900 | ||
901 | dev_info(&pdev->dev, "driver registered\n"); | |
902 | ||
903 | return 0; | |
904 | } | |
905 | ||
d3dacda9 | 906 | #ifdef CONFIG_PM_RUNTIME |
3117bb31 NC |
907 | static int fsl_asrc_runtime_resume(struct device *dev) |
908 | { | |
909 | struct fsl_asrc *asrc_priv = dev_get_drvdata(dev); | |
910 | int i; | |
911 | ||
912 | clk_prepare_enable(asrc_priv->mem_clk); | |
913 | clk_prepare_enable(asrc_priv->ipg_clk); | |
914 | for (i = 0; i < ASRC_CLK_MAX_NUM; i++) | |
915 | clk_prepare_enable(asrc_priv->asrck_clk[i]); | |
916 | ||
917 | return 0; | |
918 | } | |
919 | ||
920 | static int fsl_asrc_runtime_suspend(struct device *dev) | |
921 | { | |
922 | struct fsl_asrc *asrc_priv = dev_get_drvdata(dev); | |
923 | int i; | |
924 | ||
925 | for (i = 0; i < ASRC_CLK_MAX_NUM; i++) | |
926 | clk_disable_unprepare(asrc_priv->asrck_clk[i]); | |
927 | clk_disable_unprepare(asrc_priv->ipg_clk); | |
928 | clk_disable_unprepare(asrc_priv->mem_clk); | |
929 | ||
930 | return 0; | |
931 | } | |
932 | #endif /* CONFIG_PM_RUNTIME */ | |
933 | ||
d3dacda9 | 934 | #ifdef CONFIG_PM_SLEEP |
3117bb31 NC |
935 | static int fsl_asrc_suspend(struct device *dev) |
936 | { | |
937 | struct fsl_asrc *asrc_priv = dev_get_drvdata(dev); | |
938 | ||
939 | regcache_cache_only(asrc_priv->regmap, true); | |
940 | regcache_mark_dirty(asrc_priv->regmap); | |
941 | ||
942 | return 0; | |
943 | } | |
944 | ||
945 | static int fsl_asrc_resume(struct device *dev) | |
946 | { | |
947 | struct fsl_asrc *asrc_priv = dev_get_drvdata(dev); | |
948 | u32 asrctr; | |
949 | ||
950 | /* Stop all pairs provisionally */ | |
951 | regmap_read(asrc_priv->regmap, REG_ASRCTR, &asrctr); | |
952 | regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, | |
953 | ASRCTR_ASRCEi_ALL_MASK, 0); | |
954 | ||
955 | /* Restore all registers */ | |
956 | regcache_cache_only(asrc_priv->regmap, false); | |
957 | regcache_sync(asrc_priv->regmap); | |
958 | ||
959 | /* Restart enabled pairs */ | |
960 | regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, | |
961 | ASRCTR_ASRCEi_ALL_MASK, asrctr); | |
962 | ||
963 | return 0; | |
964 | } | |
965 | #endif /* CONFIG_PM_SLEEP */ | |
966 | ||
967 | static const struct dev_pm_ops fsl_asrc_pm = { | |
968 | SET_RUNTIME_PM_OPS(fsl_asrc_runtime_suspend, fsl_asrc_runtime_resume, NULL) | |
969 | SET_SYSTEM_SLEEP_PM_OPS(fsl_asrc_suspend, fsl_asrc_resume) | |
970 | }; | |
971 | ||
972 | static const struct of_device_id fsl_asrc_ids[] = { | |
973 | { .compatible = "fsl,imx35-asrc", }, | |
974 | { .compatible = "fsl,imx53-asrc", }, | |
975 | {} | |
976 | }; | |
977 | MODULE_DEVICE_TABLE(of, fsl_asrc_ids); | |
978 | ||
979 | static struct platform_driver fsl_asrc_driver = { | |
980 | .probe = fsl_asrc_probe, | |
981 | .driver = { | |
982 | .name = "fsl-asrc", | |
983 | .of_match_table = fsl_asrc_ids, | |
984 | .pm = &fsl_asrc_pm, | |
985 | }, | |
986 | }; | |
987 | module_platform_driver(fsl_asrc_driver); | |
988 | ||
989 | MODULE_DESCRIPTION("Freescale ASRC ASoC driver"); | |
990 | MODULE_AUTHOR("Nicolin Chen <nicoleotsuka@gmail.com>"); | |
991 | MODULE_ALIAS("platform:fsl-asrc"); | |
992 | MODULE_LICENSE("GPL v2"); |