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ASoC: Intel: Skylake: Add i915 enabling in skl probe
[deliverable/linux.git] / sound / soc / intel / skylake / skl-pcm.c
CommitLineData
a40e693c
JK		 1/*
2 * skl-pcm.c -ASoC HDA Platform driver file implementing PCM functionality
3 *
4 * Copyright (C) 2014-2015 Intel Corp
5 * Author: Jeeja KP <jeeja.kp@intel.com>
6 *
7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
19 *
20 */
21
22#include <linux/pci.h>
23#include <linux/pm_runtime.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
26#include "skl.h"
b663a8c5 27#include "skl-topology.h"
721c3e36
D		 28#include "skl-sst-dsp.h"
29#include "skl-sst-ipc.h"
a40e693c
JK		 30
31#define HDA_MONO 1
32#define HDA_STEREO 2
8f35bf3f 33#define HDA_QUAD 4
a40e693c
JK		 34
35static struct snd_pcm_hardware azx_pcm_hw = {
36 .info = (SNDRV_PCM_INFO_MMAP |
37 SNDRV_PCM_INFO_INTERLEAVED |
38 SNDRV_PCM_INFO_BLOCK_TRANSFER |
39 SNDRV_PCM_INFO_MMAP_VALID |
40 SNDRV_PCM_INFO_PAUSE |
3637976b 41 SNDRV_PCM_INFO_RESUME |
a40e693c
JK		 42 SNDRV_PCM_INFO_SYNC_START |
43 SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
44 SNDRV_PCM_INFO_HAS_LINK_ATIME |
45 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
06b23d93
JK		 46 .formats = SNDRV_PCM_FMTBIT_S16_LE |
47 SNDRV_PCM_FMTBIT_S32_LE |
48 SNDRV_PCM_FMTBIT_S24_LE,
49 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
50 SNDRV_PCM_RATE_8000,
51 .rate_min = 8000,
a40e693c 52 .rate_max = 48000,
8f35bf3f
JK		 53 .channels_min = 1,
54 .channels_max = HDA_QUAD,
a40e693c
JK		 55 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
56 .period_bytes_min = 128,
57 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
58 .periods_min = 2,
59 .periods_max = AZX_MAX_FRAG,
60 .fifo_size = 0,
61};
62
63static inline
64struct hdac_ext_stream *get_hdac_ext_stream(struct snd_pcm_substream *substream)
65{
66 return substream->runtime->private_data;
67}
68
69static struct hdac_ext_bus *get_bus_ctx(struct snd_pcm_substream *substream)
70{
71 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
72 struct hdac_stream *hstream = hdac_stream(stream);
73 struct hdac_bus *bus = hstream->bus;
74
75 return hbus_to_ebus(bus);
76}
77
78static int skl_substream_alloc_pages(struct hdac_ext_bus *ebus,
79 struct snd_pcm_substream *substream,
80 size_t size)
81{
82 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
83
84 hdac_stream(stream)->bufsize = 0;
85 hdac_stream(stream)->period_bytes = 0;
86 hdac_stream(stream)->format_val = 0;
87
88 return snd_pcm_lib_malloc_pages(substream, size);
89}
90
91static int skl_substream_free_pages(struct hdac_bus *bus,
92 struct snd_pcm_substream *substream)
93{
94 return snd_pcm_lib_free_pages(substream);
95}
96
97static void skl_set_pcm_constrains(struct hdac_ext_bus *ebus,
98 struct snd_pcm_runtime *runtime)
99{
100 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
101
102 /* avoid wrap-around with wall-clock */
103 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
104 20, 178000000);
105}
106
05057001
JK		 107static enum hdac_ext_stream_type skl_get_host_stream_type(struct hdac_ext_bus *ebus)
108{
109 if (ebus->ppcap)
110 return HDAC_EXT_STREAM_TYPE_HOST;
111 else
112 return HDAC_EXT_STREAM_TYPE_COUPLED;
113}
114
4557c305
JK		 115/*
116 * check if the stream opened is marked as ignore_suspend by machine, if so
117 * then enable suspend_active refcount
118 *
119 * The count supend_active does not need lock as it is used in open/close
120 * and suspend context
121 */
122static void skl_set_suspend_active(struct snd_pcm_substream *substream,
123 struct snd_soc_dai *dai, bool enable)
124{
125 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
126 struct snd_soc_dapm_widget *w;
127 struct skl *skl = ebus_to_skl(ebus);
128
129 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
130 w = dai->playback_widget;
131 else
132 w = dai->capture_widget;
133
134 if (w->ignore_suspend && enable)
135 skl->supend_active++;
136 else if (w->ignore_suspend && !enable)
137 skl->supend_active--;
138}
139
a40e693c
JK		 140static int skl_pcm_open(struct snd_pcm_substream *substream,
141 struct snd_soc_dai *dai)
142{
143 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
144 struct hdac_ext_stream *stream;
145 struct snd_pcm_runtime *runtime = substream->runtime;
146 struct skl_dma_params *dma_params;
a40e693c
JK		 147
148 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
a40e693c
JK		 149
150 stream = snd_hdac_ext_stream_assign(ebus, substream,
05057001 151 skl_get_host_stream_type(ebus));
a40e693c
JK		 152 if (stream == NULL)
153 return -EBUSY;
154
155 skl_set_pcm_constrains(ebus, runtime);
156
157 /*
158 * disable WALLCLOCK timestamps for capture streams
159 * until we figure out how to handle digital inputs
160 */
161 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
162 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
163 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
164 }
165
166 runtime->private_data = stream;
167
168 dma_params = kzalloc(sizeof(*dma_params), GFP_KERNEL);
169 if (!dma_params)
170 return -ENOMEM;
171
172 dma_params->stream_tag = hdac_stream(stream)->stream_tag;
173 snd_soc_dai_set_dma_data(dai, substream, dma_params);
174
175 dev_dbg(dai->dev, "stream tag set in dma params=%d\n",
176 dma_params->stream_tag);
4557c305 177 skl_set_suspend_active(substream, dai, true);
a40e693c
JK		 178 snd_pcm_set_sync(substream);
179
180 return 0;
181}
182
183static int skl_get_format(struct snd_pcm_substream *substream,
184 struct snd_soc_dai *dai)
185{
186 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
187 struct skl_dma_params *dma_params;
05057001 188 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
a40e693c 189 int format_val = 0;
a40e693c 190
05057001
JK		 191 if (ebus->ppcap) {
192 struct snd_pcm_runtime *runtime = substream->runtime;
193
194 format_val = snd_hdac_calc_stream_format(runtime->rate,
195 runtime->channels,
196 runtime->format,
197 32, 0);
198 } else {
199 struct snd_soc_dai *codec_dai = rtd->codec_dai;
200
201 dma_params = snd_soc_dai_get_dma_data(codec_dai, substream);
202 if (dma_params)
203 format_val = dma_params->format;
204 }
a40e693c
JK		 205
206 return format_val;
207}
208
c115fa5e
D		 209static int skl_be_prepare(struct snd_pcm_substream *substream,
210 struct snd_soc_dai *dai)
211{
212 struct skl *skl = get_skl_ctx(dai->dev);
213 struct skl_sst *ctx = skl->skl_sst;
214 struct skl_module_cfg *mconfig;
215
216 if ((dai->playback_active > 1) || (dai->capture_active > 1))
217 return 0;
218
219 mconfig = skl_tplg_be_get_cpr_module(dai, substream->stream);
220 if (mconfig == NULL)
221 return -EINVAL;
222
223 return skl_dsp_set_dma_control(ctx, mconfig);
224}
225
a40e693c
JK		 226static int skl_pcm_prepare(struct snd_pcm_substream *substream,
227 struct snd_soc_dai *dai)
228{
229 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
230 unsigned int format_val;
231 int err;
232
233 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
a40e693c
JK		 234
235 format_val = skl_get_format(substream, dai);
236 dev_dbg(dai->dev, "stream_tag=%d formatvalue=%d\n",
237 hdac_stream(stream)->stream_tag, format_val);
238 snd_hdac_stream_reset(hdac_stream(stream));
239
240 err = snd_hdac_stream_set_params(hdac_stream(stream), format_val);
241 if (err < 0)
242 return err;
243
244 err = snd_hdac_stream_setup(hdac_stream(stream));
245 if (err < 0)
246 return err;
247
248 hdac_stream(stream)->prepared = 1;
249
250 return err;
251}
252
253static int skl_pcm_hw_params(struct snd_pcm_substream *substream,
254 struct snd_pcm_hw_params *params,
255 struct snd_soc_dai *dai)
256{
257 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
05057001 258 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
a40e693c 259 struct snd_pcm_runtime *runtime = substream->runtime;
b663a8c5
JK		 260 struct skl_pipe_params p_params = {0};
261 struct skl_module_cfg *m_cfg;
05057001 262 int ret, dma_id;
a40e693c
JK		 263
264 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
265 ret = skl_substream_alloc_pages(ebus, substream,
266 params_buffer_bytes(params));
267 if (ret < 0)
268 return ret;
269
270 dev_dbg(dai->dev, "format_val, rate=%d, ch=%d, format=%d\n",
271 runtime->rate, runtime->channels, runtime->format);
272
05057001
JK		 273 dma_id = hdac_stream(stream)->stream_tag - 1;
274 dev_dbg(dai->dev, "dma_id=%d\n", dma_id);
275
b663a8c5
JK		 276 p_params.s_fmt = snd_pcm_format_width(params_format(params));
277 p_params.ch = params_channels(params);
278 p_params.s_freq = params_rate(params);
279 p_params.host_dma_id = dma_id;
280 p_params.stream = substream->stream;
281
282 m_cfg = skl_tplg_fe_get_cpr_module(dai, p_params.stream);
283 if (m_cfg)
284 skl_tplg_update_pipe_params(dai->dev, m_cfg, &p_params);
285
a40e693c
JK		 286 return 0;
287}
288
289static void skl_pcm_close(struct snd_pcm_substream *substream,
290 struct snd_soc_dai *dai)
291{
292 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
05057001 293 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
a40e693c 294 struct skl_dma_params *dma_params = NULL;
721c3e36 295 struct skl *skl = ebus_to_skl(ebus);
a40e693c
JK		 296
297 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
05057001
JK		 298
299 snd_hdac_ext_stream_release(stream, skl_get_host_stream_type(ebus));
a40e693c
JK		 300
301 dma_params = snd_soc_dai_get_dma_data(dai, substream);
302 /*
303 * now we should set this to NULL as we are freeing by the
304 * dma_params
305 */
306 snd_soc_dai_set_dma_data(dai, substream, NULL);
4557c305 307 skl_set_suspend_active(substream, dai, false);
a40e693c 308
721c3e36
D		 309 /*
310 * check if close is for "Reference Pin" and set back the
311 * CGCTL.MISCBDCGE if disabled by driver
312 */
313 if (!strncmp(dai->name, "Reference Pin", 13) &&
314 skl->skl_sst->miscbdcg_disabled) {
315 skl->skl_sst->enable_miscbdcge(dai->dev, true);
316 skl->skl_sst->miscbdcg_disabled = false;
317 }
318
a40e693c
JK		 319 kfree(dma_params);
320}
321
322static int skl_pcm_hw_free(struct snd_pcm_substream *substream,
323 struct snd_soc_dai *dai)
324{
325 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
326 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
327
328 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
329
330 snd_hdac_stream_cleanup(hdac_stream(stream));
331 hdac_stream(stream)->prepared = 0;
332
333 return skl_substream_free_pages(ebus_to_hbus(ebus), substream);
334}
335
b663a8c5
JK		 336static int skl_be_hw_params(struct snd_pcm_substream *substream,
337 struct snd_pcm_hw_params *params,
338 struct snd_soc_dai *dai)
339{
340 struct skl_pipe_params p_params = {0};
341
342 p_params.s_fmt = snd_pcm_format_width(params_format(params));
343 p_params.ch = params_channels(params);
344 p_params.s_freq = params_rate(params);
345 p_params.stream = substream->stream;
b663a8c5 346
4bd073f9 347 return skl_tplg_be_update_params(dai, &p_params);
b663a8c5
JK		 348}
349
d1730c3d
JK		 350static int skl_decoupled_trigger(struct snd_pcm_substream *substream,
351 int cmd)
352{
353 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
354 struct hdac_bus *bus = ebus_to_hbus(ebus);
355 struct hdac_ext_stream *stream;
356 int start;
357 unsigned long cookie;
358 struct hdac_stream *hstr;
359
360 stream = get_hdac_ext_stream(substream);
361 hstr = hdac_stream(stream);
362
363 if (!hstr->prepared)
364 return -EPIPE;
365
366 switch (cmd) {
367 case SNDRV_PCM_TRIGGER_START:
368 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
369 case SNDRV_PCM_TRIGGER_RESUME:
370 start = 1;
371 break;
372
373 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
374 case SNDRV_PCM_TRIGGER_SUSPEND:
375 case SNDRV_PCM_TRIGGER_STOP:
376 start = 0;
377 break;
378
379 default:
380 return -EINVAL;
381 }
382
383 spin_lock_irqsave(&bus->reg_lock, cookie);
384
385 if (start) {
386 snd_hdac_stream_start(hdac_stream(stream), true);
387 snd_hdac_stream_timecounter_init(hstr, 0);
388 } else {
389 snd_hdac_stream_stop(hdac_stream(stream));
390 }
391
392 spin_unlock_irqrestore(&bus->reg_lock, cookie);
393
394 return 0;
395}
396
b663a8c5
JK		 397static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
398 struct snd_soc_dai *dai)
399{
400 struct skl *skl = get_skl_ctx(dai->dev);
401 struct skl_sst *ctx = skl->skl_sst;
402 struct skl_module_cfg *mconfig;
7e3a17d3
JK		 403 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
404 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
d1730c3d 405 int ret;
b663a8c5
JK		 406
407 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
408 if (!mconfig)
409 return -EIO;
410
411 switch (cmd) {
7e3a17d3
JK		 412 case SNDRV_PCM_TRIGGER_RESUME:
413 skl_pcm_prepare(substream, dai);
748a1d5a
JK		 414 /*
415 * enable DMA Resume enable bit for the stream, set the dpib
416 * & lpib position to resune before starting the DMA
417 */
418 snd_hdac_ext_stream_drsm_enable(ebus, true,
419 hdac_stream(stream)->index);
420 snd_hdac_ext_stream_set_dpibr(ebus, stream, stream->dpib);
421 snd_hdac_ext_stream_set_lpib(stream, stream->lpib);
422
d1730c3d 423 case SNDRV_PCM_TRIGGER_START:
b663a8c5 424 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
d1730c3d
JK		 425 /*
426 * Start HOST DMA and Start FE Pipe.This is to make sure that
427 * there are no underrun/overrun in the case when the FE
428 * pipeline is started but there is a delay in starting the
429 * DMA channel on the host.
430 */
7e3a17d3 431 snd_hdac_ext_stream_decouple(ebus, stream, true);
d1730c3d
JK		 432 ret = skl_decoupled_trigger(substream, cmd);
433 if (ret < 0)
434 return ret;
b663a8c5 435 return skl_run_pipe(ctx, mconfig->pipe);
d1730c3d 436 break;
b663a8c5
JK		 437
438 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
439 case SNDRV_PCM_TRIGGER_SUSPEND:
d1730c3d
JK		 440 case SNDRV_PCM_TRIGGER_STOP:
441 /*
442 * Stop FE Pipe first and stop DMA. This is to make sure that
443 * there are no underrun/overrun in the case if there is a delay
444 * between the two operations.
445 */
446 ret = skl_stop_pipe(ctx, mconfig->pipe);
447 if (ret < 0)
448 return ret;
449
450 ret = skl_decoupled_trigger(substream, cmd);
748a1d5a
JK		 451 if (cmd == SNDRV_PCM_TRIGGER_SUSPEND) {
452 /* save the dpib and lpib positions */
453 stream->dpib = readl(ebus->bus.remap_addr +
454 AZX_REG_VS_SDXDPIB_XBASE +
455 (AZX_REG_VS_SDXDPIB_XINTERVAL *
456 hdac_stream(stream)->index));
457
458 stream->lpib = snd_hdac_stream_get_pos_lpib(
459 hdac_stream(stream));
7e3a17d3 460 snd_hdac_ext_stream_decouple(ebus, stream, false);
748a1d5a 461 }
d1730c3d 462 break;
b663a8c5
JK		 463
464 default:
d1730c3d 465 return -EINVAL;
b663a8c5 466 }
d1730c3d
JK		 467
468 return 0;
b663a8c5
JK		 469}
470
05057001
JK		 471static int skl_link_hw_params(struct snd_pcm_substream *substream,
472 struct snd_pcm_hw_params *params,
473 struct snd_soc_dai *dai)
474{
475 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
476 struct hdac_ext_stream *link_dev;
477 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
aceb5d20 478 struct hdac_ext_dma_params *dma_params;
05057001 479 struct snd_soc_dai *codec_dai = rtd->codec_dai;
b663a8c5 480 struct skl_pipe_params p_params = {0};
05057001 481
05057001
JK		 482 link_dev = snd_hdac_ext_stream_assign(ebus, substream,
483 HDAC_EXT_STREAM_TYPE_LINK);
484 if (!link_dev)
485 return -EBUSY;
486
487 snd_soc_dai_set_dma_data(dai, substream, (void *)link_dev);
488
489 /* set the stream tag in the codec dai dma params */
aceb5d20 490 dma_params = snd_soc_dai_get_dma_data(codec_dai, substream);
05057001
JK		 491 if (dma_params)
492 dma_params->stream_tag = hdac_stream(link_dev)->stream_tag;
b663a8c5
JK		 493
494 p_params.s_fmt = snd_pcm_format_width(params_format(params));
495 p_params.ch = params_channels(params);
496 p_params.s_freq = params_rate(params);
497 p_params.stream = substream->stream;
498 p_params.link_dma_id = hdac_stream(link_dev)->stream_tag - 1;
499
4bd073f9 500 return skl_tplg_be_update_params(dai, &p_params);
05057001
JK		 501}
502
503static int skl_link_pcm_prepare(struct snd_pcm_substream *substream,
504 struct snd_soc_dai *dai)
505{
506 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
507 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
508 struct hdac_ext_stream *link_dev =
509 snd_soc_dai_get_dma_data(dai, substream);
510 unsigned int format_val = 0;
511 struct skl_dma_params *dma_params;
512 struct snd_soc_dai *codec_dai = rtd->codec_dai;
05057001
JK		 513 struct hdac_ext_link *link;
514
05057001
JK		 515 dma_params = (struct skl_dma_params *)
516 snd_soc_dai_get_dma_data(codec_dai, substream);
517 if (dma_params)
518 format_val = dma_params->format;
519 dev_dbg(dai->dev, "stream_tag=%d formatvalue=%d codec_dai_name=%s\n",
520 hdac_stream(link_dev)->stream_tag, format_val, codec_dai->name);
521
05057001
JK		 522 link = snd_hdac_ext_bus_get_link(ebus, rtd->codec->component.name);
523 if (!link)
524 return -EINVAL;
525
920982c9
JK		 526 snd_hdac_ext_bus_link_power_up(link);
527 snd_hdac_ext_link_stream_reset(link_dev);
528
529 snd_hdac_ext_link_stream_setup(link_dev, format_val);
530
05057001
JK		 531 snd_hdac_ext_link_set_stream_id(link, hdac_stream(link_dev)->stream_tag);
532 link_dev->link_prepared = 1;
533
534 return 0;
535}
536
537static int skl_link_pcm_trigger(struct snd_pcm_substream *substream,
538 int cmd, struct snd_soc_dai *dai)
539{
540 struct hdac_ext_stream *link_dev =
541 snd_soc_dai_get_dma_data(dai, substream);
920982c9
JK		 542 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
543 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
05057001
JK		 544
545 dev_dbg(dai->dev, "In %s cmd=%d\n", __func__, cmd);
546 switch (cmd) {
920982c9
JK		 547 case SNDRV_PCM_TRIGGER_RESUME:
548 skl_link_pcm_prepare(substream, dai);
05057001
JK		 549 case SNDRV_PCM_TRIGGER_START:
550 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
920982c9 551 snd_hdac_ext_stream_decouple(ebus, stream, true);
05057001
JK		 552 snd_hdac_ext_link_stream_start(link_dev);
553 break;
554
555 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
556 case SNDRV_PCM_TRIGGER_SUSPEND:
557 case SNDRV_PCM_TRIGGER_STOP:
558 snd_hdac_ext_link_stream_clear(link_dev);
920982c9
JK		 559 if (cmd == SNDRV_PCM_TRIGGER_SUSPEND)
560 snd_hdac_ext_stream_decouple(ebus, stream, false);
05057001
JK		 561 break;
562
563 default:
564 return -EINVAL;
565 }
566 return 0;
567}
568
569static int skl_link_hw_free(struct snd_pcm_substream *substream,
570 struct snd_soc_dai *dai)
571{
572 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
573 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
574 struct hdac_ext_stream *link_dev =
575 snd_soc_dai_get_dma_data(dai, substream);
576 struct hdac_ext_link *link;
577
578 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
579
580 link_dev->link_prepared = 0;
581
582 link = snd_hdac_ext_bus_get_link(ebus, rtd->codec->component.name);
583 if (!link)
584 return -EINVAL;
585
586 snd_hdac_ext_link_clear_stream_id(link, hdac_stream(link_dev)->stream_tag);
587 snd_hdac_ext_stream_release(link_dev, HDAC_EXT_STREAM_TYPE_LINK);
588 return 0;
589}
590
a40e693c
JK		 591static struct snd_soc_dai_ops skl_pcm_dai_ops = {
592 .startup = skl_pcm_open,
593 .shutdown = skl_pcm_close,
594 .prepare = skl_pcm_prepare,
595 .hw_params = skl_pcm_hw_params,
596 .hw_free = skl_pcm_hw_free,
b663a8c5 597 .trigger = skl_pcm_trigger,
a40e693c
JK		 598};
599
05057001 600static struct snd_soc_dai_ops skl_dmic_dai_ops = {
b663a8c5 601 .hw_params = skl_be_hw_params,
b663a8c5
JK		 602};
603
604static struct snd_soc_dai_ops skl_be_ssp_dai_ops = {
b663a8c5 605 .hw_params = skl_be_hw_params,
c115fa5e 606 .prepare = skl_be_prepare,
05057001
JK		 607};
608
609static struct snd_soc_dai_ops skl_link_dai_ops = {
05057001
JK		 610 .prepare = skl_link_pcm_prepare,
611 .hw_params = skl_link_hw_params,
612 .hw_free = skl_link_hw_free,
613 .trigger = skl_link_pcm_trigger,
05057001
JK		 614};
615
a40e693c
JK		 616static struct snd_soc_dai_driver skl_platform_dai[] = {
617{
618 .name = "System Pin",
619 .ops = &skl_pcm_dai_ops,
620 .playback = {
621 .stream_name = "System Playback",
622 .channels_min = HDA_MONO,
623 .channels_max = HDA_STEREO,
624 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_8000,
625 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
626 },
627 .capture = {
628 .stream_name = "System Capture",
629 .channels_min = HDA_MONO,
630 .channels_max = HDA_STEREO,
631 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
632 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
633 },
634},
05057001
JK		 635{
636 .name = "Reference Pin",
637 .ops = &skl_pcm_dai_ops,
638 .capture = {
639 .stream_name = "Reference Capture",
640 .channels_min = HDA_MONO,
8f35bf3f 641 .channels_max = HDA_QUAD,
05057001
JK		 642 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
643 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
644 },
645},
a40e693c
JK		 646{
647 .name = "Deepbuffer Pin",
648 .ops = &skl_pcm_dai_ops,
649 .playback = {
650 .stream_name = "Deepbuffer Playback",
651 .channels_min = HDA_STEREO,
652 .channels_max = HDA_STEREO,
653 .rates = SNDRV_PCM_RATE_48000,
654 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
655 },
656},
657{
658 .name = "LowLatency Pin",
659 .ops = &skl_pcm_dai_ops,
660 .playback = {
661 .stream_name = "Low Latency Playback",
662 .channels_min = HDA_STEREO,
663 .channels_max = HDA_STEREO,
664 .rates = SNDRV_PCM_RATE_48000,
665 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
666 },
667},
8f35bf3f
JK		 668{
669 .name = "DMIC Pin",
670 .ops = &skl_pcm_dai_ops,
671 .capture = {
672 .stream_name = "DMIC Capture",
673 .channels_min = HDA_MONO,
674 .channels_max = HDA_QUAD,
675 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
676 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
677 },
678},
679
05057001 680/* BE CPU Dais */
b663a8c5
JK		 681{
682 .name = "SSP0 Pin",
683 .ops = &skl_be_ssp_dai_ops,
684 .playback = {
685 .stream_name = "ssp0 Tx",
686 .channels_min = HDA_STEREO,
687 .channels_max = HDA_STEREO,
688 .rates = SNDRV_PCM_RATE_48000,
689 .formats = SNDRV_PCM_FMTBIT_S16_LE,
690 },
691 .capture = {
692 .stream_name = "ssp0 Rx",
693 .channels_min = HDA_STEREO,
694 .channels_max = HDA_STEREO,
695 .rates = SNDRV_PCM_RATE_48000,
696 .formats = SNDRV_PCM_FMTBIT_S16_LE,
697 },
698},
c80fd4da
JK		 699{
700 .name = "SSP1 Pin",
701 .ops = &skl_be_ssp_dai_ops,
702 .playback = {
703 .stream_name = "ssp1 Tx",
704 .channels_min = HDA_STEREO,
705 .channels_max = HDA_STEREO,
706 .rates = SNDRV_PCM_RATE_48000,
707 .formats = SNDRV_PCM_FMTBIT_S16_LE,
708 },
709 .capture = {
710 .stream_name = "ssp1 Rx",
711 .channels_min = HDA_STEREO,
712 .channels_max = HDA_STEREO,
713 .rates = SNDRV_PCM_RATE_48000,
714 .formats = SNDRV_PCM_FMTBIT_S16_LE,
715 },
716},
05057001
JK		 717{
718 .name = "iDisp Pin",
719 .ops = &skl_link_dai_ops,
720 .playback = {
721 .stream_name = "iDisp Tx",
722 .channels_min = HDA_STEREO,
723 .channels_max = HDA_STEREO,
724 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_48000,
725 .formats = SNDRV_PCM_FMTBIT_S16_LE,
726 },
727},
728{
729 .name = "DMIC01 Pin",
730 .ops = &skl_dmic_dai_ops,
731 .capture = {
732 .stream_name = "DMIC01 Rx",
8f35bf3f
JK		 733 .channels_min = HDA_MONO,
734 .channels_max = HDA_QUAD,
05057001
JK		 735 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
736 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
737 },
738},
05057001
JK		 739{
740 .name = "HD-Codec Pin",
741 .ops = &skl_link_dai_ops,
742 .playback = {
743 .stream_name = "HD-Codec Tx",
744 .channels_min = HDA_STEREO,
745 .channels_max = HDA_STEREO,
746 .rates = SNDRV_PCM_RATE_48000,
747 .formats = SNDRV_PCM_FMTBIT_S16_LE,
748 },
749 .capture = {
750 .stream_name = "HD-Codec Rx",
751 .channels_min = HDA_STEREO,
752 .channels_max = HDA_STEREO,
753 .rates = SNDRV_PCM_RATE_48000,
754 .formats = SNDRV_PCM_FMTBIT_S16_LE,
755 },
756},
a40e693c
JK		 757};
758
759static int skl_platform_open(struct snd_pcm_substream *substream)
760{
761 struct snd_pcm_runtime *runtime;
762 struct snd_soc_pcm_runtime *rtd = substream->private_data;
763 struct snd_soc_dai_link *dai_link = rtd->dai_link;
764
765 dev_dbg(rtd->cpu_dai->dev, "In %s:%s\n", __func__,
766 dai_link->cpu_dai_name);
767
768 runtime = substream->runtime;
769 snd_soc_set_runtime_hwparams(substream, &azx_pcm_hw);
770
771 return 0;
772}
773
b663a8c5 774static int skl_coupled_trigger(struct snd_pcm_substream *substream,
a40e693c
JK		 775 int cmd)
776{
777 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
778 struct hdac_bus *bus = ebus_to_hbus(ebus);
779 struct hdac_ext_stream *stream;
780 struct snd_pcm_substream *s;
781 bool start;
782 int sbits = 0;
783 unsigned long cookie;
784 struct hdac_stream *hstr;
785
786 stream = get_hdac_ext_stream(substream);
787 hstr = hdac_stream(stream);
788
789 dev_dbg(bus->dev, "In %s cmd=%d\n", __func__, cmd);
790
791 if (!hstr->prepared)
792 return -EPIPE;
793
794 switch (cmd) {
795 case SNDRV_PCM_TRIGGER_START:
796 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
797 case SNDRV_PCM_TRIGGER_RESUME:
798 start = true;
799 break;
800
801 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
802 case SNDRV_PCM_TRIGGER_SUSPEND:
803 case SNDRV_PCM_TRIGGER_STOP:
804 start = false;
805 break;
806
807 default:
808 return -EINVAL;
809 }
810
811 snd_pcm_group_for_each_entry(s, substream) {
812 if (s->pcm->card != substream->pcm->card)
813 continue;
814 stream = get_hdac_ext_stream(s);
815 sbits |= 1 << hdac_stream(stream)->index;
816 snd_pcm_trigger_done(s, substream);
817 }
818
819 spin_lock_irqsave(&bus->reg_lock, cookie);
820
821 /* first, set SYNC bits of corresponding streams */
822 snd_hdac_stream_sync_trigger(hstr, true, sbits, AZX_REG_SSYNC);
823
824 snd_pcm_group_for_each_entry(s, substream) {
825 if (s->pcm->card != substream->pcm->card)
826 continue;
827 stream = get_hdac_ext_stream(s);
828 if (start)
829 snd_hdac_stream_start(hdac_stream(stream), true);
830 else
831 snd_hdac_stream_stop(hdac_stream(stream));
832 }
833 spin_unlock_irqrestore(&bus->reg_lock, cookie);
834
835 snd_hdac_stream_sync(hstr, start, sbits);
836
837 spin_lock_irqsave(&bus->reg_lock, cookie);
838
839 /* reset SYNC bits */
840 snd_hdac_stream_sync_trigger(hstr, false, sbits, AZX_REG_SSYNC);
841 if (start)
842 snd_hdac_stream_timecounter_init(hstr, sbits);
843 spin_unlock_irqrestore(&bus->reg_lock, cookie);
844
845 return 0;
846}
847
05057001
JK		 848static int skl_platform_pcm_trigger(struct snd_pcm_substream *substream,
849 int cmd)
850{
851 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
852
d1730c3d 853 if (!ebus->ppcap)
b663a8c5 854 return skl_coupled_trigger(substream, cmd);
d1730c3d
JK		 855
856 return 0;
05057001
JK		 857}
858
a40e693c
JK		 859/* calculate runtime delay from LPIB */
860static int skl_get_delay_from_lpib(struct hdac_ext_bus *ebus,
861 struct hdac_ext_stream *sstream,
862 unsigned int pos)
863{
864 struct hdac_bus *bus = ebus_to_hbus(ebus);
865 struct hdac_stream *hstream = hdac_stream(sstream);
866 struct snd_pcm_substream *substream = hstream->substream;
867 int stream = substream->stream;
868 unsigned int lpib_pos = snd_hdac_stream_get_pos_lpib(hstream);
869 int delay;
870
871 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
872 delay = pos - lpib_pos;
873 else
874 delay = lpib_pos - pos;
875
876 if (delay < 0) {
877 if (delay >= hstream->delay_negative_threshold)
878 delay = 0;
879 else
880 delay += hstream->bufsize;
881 }
33420d66
VK		 882
883 if (hstream->bufsize == delay)
884 delay = 0;
a40e693c
JK		 885
886 if (delay >= hstream->period_bytes) {
887 dev_info(bus->dev,
888 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
889 delay, hstream->period_bytes);
890 delay = 0;
891 }
892
893 return bytes_to_frames(substream->runtime, delay);
894}
895
896static unsigned int skl_get_position(struct hdac_ext_stream *hstream,
897 int codec_delay)
898{
899 struct hdac_stream *hstr = hdac_stream(hstream);
900 struct snd_pcm_substream *substream = hstr->substream;
c7b2a444 901 struct hdac_ext_bus *ebus;
a40e693c
JK		 902 unsigned int pos;
903 int delay;
904
905 /* use the position buffer as default */
906 pos = snd_hdac_stream_get_pos_posbuf(hdac_stream(hstream));
907
908 if (pos >= hdac_stream(hstream)->bufsize)
909 pos = 0;
910
911 if (substream->runtime) {
c7b2a444 912 ebus = get_bus_ctx(substream);
a40e693c
JK		 913 delay = skl_get_delay_from_lpib(ebus, hstream, pos)
914 + codec_delay;
915 substream->runtime->delay += delay;
916 }
917
918 return pos;
919}
920
921static snd_pcm_uframes_t skl_platform_pcm_pointer
922 (struct snd_pcm_substream *substream)
923{
924 struct hdac_ext_stream *hstream = get_hdac_ext_stream(substream);
925
926 return bytes_to_frames(substream->runtime,
927 skl_get_position(hstream, 0));
928}
929
930static u64 skl_adjust_codec_delay(struct snd_pcm_substream *substream,
931 u64 nsec)
932{
933 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
934 struct snd_soc_dai *codec_dai = rtd->codec_dai;
935 u64 codec_frames, codec_nsecs;
936
937 if (!codec_dai->driver->ops->delay)
938 return nsec;
939
940 codec_frames = codec_dai->driver->ops->delay(substream, codec_dai);
941 codec_nsecs = div_u64(codec_frames * 1000000000LL,
942 substream->runtime->rate);
943
944 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
945 return nsec + codec_nsecs;
946
947 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
948}
949
950static int skl_get_time_info(struct snd_pcm_substream *substream,
951 struct timespec *system_ts, struct timespec *audio_ts,
952 struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
953 struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
954{
955 struct hdac_ext_stream *sstream = get_hdac_ext_stream(substream);
956 struct hdac_stream *hstr = hdac_stream(sstream);
957 u64 nsec;
958
959 if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
960 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
961
962 snd_pcm_gettime(substream->runtime, system_ts);
963
964 nsec = timecounter_read(&hstr->tc);
965 nsec = div_u64(nsec, 3); /* can be optimized */
966 if (audio_tstamp_config->report_delay)
967 nsec = skl_adjust_codec_delay(substream, nsec);
968
969 *audio_ts = ns_to_timespec(nsec);
970
971 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
972 audio_tstamp_report->accuracy_report = 1; /* rest of struct is valid */
973 audio_tstamp_report->accuracy = 42; /* 24MHzWallClk == 42ns resolution */
974
975 } else {
976 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
977 }
978
979 return 0;
980}
981
982static struct snd_pcm_ops skl_platform_ops = {
983 .open = skl_platform_open,
984 .ioctl = snd_pcm_lib_ioctl,
985 .trigger = skl_platform_pcm_trigger,
986 .pointer = skl_platform_pcm_pointer,
987 .get_time_info = skl_get_time_info,
988 .mmap = snd_pcm_lib_default_mmap,
989 .page = snd_pcm_sgbuf_ops_page,
990};
991
992static void skl_pcm_free(struct snd_pcm *pcm)
993{
994 snd_pcm_lib_preallocate_free_for_all(pcm);
995}
996
997#define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
998
999static int skl_pcm_new(struct snd_soc_pcm_runtime *rtd)
1000{
1001 struct snd_soc_dai *dai = rtd->cpu_dai;
1002 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
1003 struct snd_pcm *pcm = rtd->pcm;
1004 unsigned int size;
1005 int retval = 0;
1006 struct skl *skl = ebus_to_skl(ebus);
1007
1008 if (dai->driver->playback.channels_min ||
1009 dai->driver->capture.channels_min) {
1010 /* buffer pre-allocation */
1011 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
1012 if (size > MAX_PREALLOC_SIZE)
1013 size = MAX_PREALLOC_SIZE;
1014 retval = snd_pcm_lib_preallocate_pages_for_all(pcm,
1015 SNDRV_DMA_TYPE_DEV_SG,
1016 snd_dma_pci_data(skl->pci),
1017 size, MAX_PREALLOC_SIZE);
1018 if (retval) {
1019 dev_err(dai->dev, "dma buffer allocationf fail\n");
1020 return retval;
1021 }
1022 }
1023
1024 return retval;
1025}
1026
b663a8c5
JK		 1027static int skl_platform_soc_probe(struct snd_soc_platform *platform)
1028{
1029 struct hdac_ext_bus *ebus = dev_get_drvdata(platform->dev);
1030
1031 if (ebus->ppcap)
1032 return skl_tplg_init(platform, ebus);
1033
1034 return 0;
1035}
a40e693c 1036static struct snd_soc_platform_driver skl_platform_drv = {
b663a8c5 1037 .probe = skl_platform_soc_probe,
a40e693c
JK		 1038 .ops = &skl_platform_ops,
1039 .pcm_new = skl_pcm_new,
1040 .pcm_free = skl_pcm_free,
1041};
1042
1043static const struct snd_soc_component_driver skl_component = {
1044 .name = "pcm",
1045};
1046
1047int skl_platform_register(struct device *dev)
1048{
1049 int ret;
b663a8c5
JK		 1050 struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
1051 struct skl *skl = ebus_to_skl(ebus);
1052
1053 INIT_LIST_HEAD(&skl->ppl_list);
a40e693c
JK		 1054
1055 ret = snd_soc_register_platform(dev, &skl_platform_drv);
1056 if (ret) {
1057 dev_err(dev, "soc platform registration failed %d\n", ret);
1058 return ret;
1059 }
1060 ret = snd_soc_register_component(dev, &skl_component,
1061 skl_platform_dai,
1062 ARRAY_SIZE(skl_platform_dai));
1063 if (ret) {
1064 dev_err(dev, "soc component registration failed %d\n", ret);
1065 snd_soc_unregister_platform(dev);
1066 }
1067
1068 return ret;
1069
1070}
1071
1072int skl_platform_unregister(struct device *dev)
1073{
1074 snd_soc_unregister_component(dev);
1075 snd_soc_unregister_platform(dev);
1076 return 0;
1077}
Linux kernel - Deliverables
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