projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ASoC: Intel: Skylake: Fix a comment style
[deliverable/linux.git] / sound / soc / intel / skylake / skl-sst-ipc.c
CommitLineData
b81fd263
SP		 1/*
2 * skl-sst-ipc.c - Intel skl IPC Support
3 *
4 * Copyright (C) 2014-15, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as version 2, as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 */
15#include <linux/device.h>
16
17#include "../common/sst-dsp.h"
18#include "../common/sst-dsp-priv.h"
721c3e36 19#include "skl.h"
b81fd263
SP		 20#include "skl-sst-dsp.h"
21#include "skl-sst-ipc.h"
721c3e36 22#include "sound/hdaudio_ext.h"
b81fd263
SP		 23
24
25#define IPC_IXC_STATUS_BITS 24
26
27/* Global Message - Generic */
28#define IPC_GLB_TYPE_SHIFT 24
29#define IPC_GLB_TYPE_MASK (0xf << IPC_GLB_TYPE_SHIFT)
30#define IPC_GLB_TYPE(x) ((x) << IPC_GLB_TYPE_SHIFT)
31
32/* Global Message - Reply */
33#define IPC_GLB_REPLY_STATUS_SHIFT 24
34#define IPC_GLB_REPLY_STATUS_MASK ((0x1 << IPC_GLB_REPLY_STATUS_SHIFT) - 1)
35#define IPC_GLB_REPLY_STATUS(x) ((x) << IPC_GLB_REPLY_STATUS_SHIFT)
36
37#define IPC_TIMEOUT_MSECS 3000
38
39#define IPC_EMPTY_LIST_SIZE 8
40
41#define IPC_MSG_TARGET_SHIFT 30
42#define IPC_MSG_TARGET_MASK 0x1
43#define IPC_MSG_TARGET(x) (((x) & IPC_MSG_TARGET_MASK) \
44 << IPC_MSG_TARGET_SHIFT)
45
46#define IPC_MSG_DIR_SHIFT 29
47#define IPC_MSG_DIR_MASK 0x1
48#define IPC_MSG_DIR(x) (((x) & IPC_MSG_DIR_MASK) \
49 << IPC_MSG_DIR_SHIFT)
50/* Global Notification Message */
51#define IPC_GLB_NOTIFY_TYPE_SHIFT 16
52#define IPC_GLB_NOTIFY_TYPE_MASK 0xFF
53#define IPC_GLB_NOTIFY_TYPE(x) (((x) >> IPC_GLB_NOTIFY_TYPE_SHIFT) \
54 & IPC_GLB_NOTIFY_TYPE_MASK)
55
56#define IPC_GLB_NOTIFY_MSG_TYPE_SHIFT 24
57#define IPC_GLB_NOTIFY_MSG_TYPE_MASK 0x1F
58#define IPC_GLB_NOTIFY_MSG_TYPE(x) (((x) >> IPC_GLB_NOTIFY_MSG_TYPE_SHIFT) \
59 & IPC_GLB_NOTIFY_MSG_TYPE_MASK)
60
61#define IPC_GLB_NOTIFY_RSP_SHIFT 29
62#define IPC_GLB_NOTIFY_RSP_MASK 0x1
63#define IPC_GLB_NOTIFY_RSP_TYPE(x) (((x) >> IPC_GLB_NOTIFY_RSP_SHIFT) \
64 & IPC_GLB_NOTIFY_RSP_MASK)
65
66/* Pipeline operations */
67
68/* Create pipeline message */
69#define IPC_PPL_MEM_SIZE_SHIFT 0
70#define IPC_PPL_MEM_SIZE_MASK 0x7FF
71#define IPC_PPL_MEM_SIZE(x) (((x) & IPC_PPL_MEM_SIZE_MASK) \
72 << IPC_PPL_MEM_SIZE_SHIFT)
73
74#define IPC_PPL_TYPE_SHIFT 11
75#define IPC_PPL_TYPE_MASK 0x1F
76#define IPC_PPL_TYPE(x) (((x) & IPC_PPL_TYPE_MASK) \
77 << IPC_PPL_TYPE_SHIFT)
78
79#define IPC_INSTANCE_ID_SHIFT 16
80#define IPC_INSTANCE_ID_MASK 0xFF
81#define IPC_INSTANCE_ID(x) (((x) & IPC_INSTANCE_ID_MASK) \
82 << IPC_INSTANCE_ID_SHIFT)
83
84/* Set pipeline state message */
85#define IPC_PPL_STATE_SHIFT 0
86#define IPC_PPL_STATE_MASK 0x1F
87#define IPC_PPL_STATE(x) (((x) & IPC_PPL_STATE_MASK) \
88 << IPC_PPL_STATE_SHIFT)
89
90/* Module operations primary register */
91#define IPC_MOD_ID_SHIFT 0
92#define IPC_MOD_ID_MASK 0xFFFF
93#define IPC_MOD_ID(x) (((x) & IPC_MOD_ID_MASK) \
94 << IPC_MOD_ID_SHIFT)
95
96#define IPC_MOD_INSTANCE_ID_SHIFT 16
97#define IPC_MOD_INSTANCE_ID_MASK 0xFF
98#define IPC_MOD_INSTANCE_ID(x) (((x) & IPC_MOD_INSTANCE_ID_MASK) \
99 << IPC_MOD_INSTANCE_ID_SHIFT)
100
101/* Init instance message extension register */
102#define IPC_PARAM_BLOCK_SIZE_SHIFT 0
103#define IPC_PARAM_BLOCK_SIZE_MASK 0xFFFF
104#define IPC_PARAM_BLOCK_SIZE(x) (((x) & IPC_PARAM_BLOCK_SIZE_MASK) \
105 << IPC_PARAM_BLOCK_SIZE_SHIFT)
106
107#define IPC_PPL_INSTANCE_ID_SHIFT 16
108#define IPC_PPL_INSTANCE_ID_MASK 0xFF
109#define IPC_PPL_INSTANCE_ID(x) (((x) & IPC_PPL_INSTANCE_ID_MASK) \
110 << IPC_PPL_INSTANCE_ID_SHIFT)
111
112#define IPC_CORE_ID_SHIFT 24
113#define IPC_CORE_ID_MASK 0x1F
114#define IPC_CORE_ID(x) (((x) & IPC_CORE_ID_MASK) \
115 << IPC_CORE_ID_SHIFT)
116
117/* Bind/Unbind message extension register */
118#define IPC_DST_MOD_ID_SHIFT 0
119#define IPC_DST_MOD_ID(x) (((x) & IPC_MOD_ID_MASK) \
120 << IPC_DST_MOD_ID_SHIFT)
121
122#define IPC_DST_MOD_INSTANCE_ID_SHIFT 16
123#define IPC_DST_MOD_INSTANCE_ID(x) (((x) & IPC_MOD_INSTANCE_ID_MASK) \
124 << IPC_DST_MOD_INSTANCE_ID_SHIFT)
125
126#define IPC_DST_QUEUE_SHIFT 24
127#define IPC_DST_QUEUE_MASK 0x7
128#define IPC_DST_QUEUE(x) (((x) & IPC_DST_QUEUE_MASK) \
129 << IPC_DST_QUEUE_SHIFT)
130
131#define IPC_SRC_QUEUE_SHIFT 27
132#define IPC_SRC_QUEUE_MASK 0x7
133#define IPC_SRC_QUEUE(x) (((x) & IPC_SRC_QUEUE_MASK) \
134 << IPC_SRC_QUEUE_SHIFT)
6c5768b3
D		 135/* Load Module count */
136#define IPC_LOAD_MODULE_SHIFT 0
137#define IPC_LOAD_MODULE_MASK 0xFF
138#define IPC_LOAD_MODULE_CNT(x) (((x) & IPC_LOAD_MODULE_MASK) \
139 << IPC_LOAD_MODULE_SHIFT)
b81fd263
SP		 140
141/* Save pipeline messgae extension register */
142#define IPC_DMA_ID_SHIFT 0
143#define IPC_DMA_ID_MASK 0x1F
144#define IPC_DMA_ID(x) (((x) & IPC_DMA_ID_MASK) \
145 << IPC_DMA_ID_SHIFT)
146/* Large Config message extension register */
147#define IPC_DATA_OFFSET_SZ_SHIFT 0
148#define IPC_DATA_OFFSET_SZ_MASK 0xFFFFF
149#define IPC_DATA_OFFSET_SZ(x) (((x) & IPC_DATA_OFFSET_SZ_MASK) \
150 << IPC_DATA_OFFSET_SZ_SHIFT)
151#define IPC_DATA_OFFSET_SZ_CLEAR ~(IPC_DATA_OFFSET_SZ_MASK \
152 << IPC_DATA_OFFSET_SZ_SHIFT)
153
154#define IPC_LARGE_PARAM_ID_SHIFT 20
155#define IPC_LARGE_PARAM_ID_MASK 0xFF
156#define IPC_LARGE_PARAM_ID(x) (((x) & IPC_LARGE_PARAM_ID_MASK) \
157 << IPC_LARGE_PARAM_ID_SHIFT)
158
159#define IPC_FINAL_BLOCK_SHIFT 28
160#define IPC_FINAL_BLOCK_MASK 0x1
161#define IPC_FINAL_BLOCK(x) (((x) & IPC_FINAL_BLOCK_MASK) \
162 << IPC_FINAL_BLOCK_SHIFT)
163
164#define IPC_INITIAL_BLOCK_SHIFT 29
165#define IPC_INITIAL_BLOCK_MASK 0x1
166#define IPC_INITIAL_BLOCK(x) (((x) & IPC_INITIAL_BLOCK_MASK) \
167 << IPC_INITIAL_BLOCK_SHIFT)
168#define IPC_INITIAL_BLOCK_CLEAR ~(IPC_INITIAL_BLOCK_MASK \
169 << IPC_INITIAL_BLOCK_SHIFT)
170
171enum skl_ipc_msg_target {
172 IPC_FW_GEN_MSG = 0,
173 IPC_MOD_MSG = 1
174};
175
176enum skl_ipc_msg_direction {
177 IPC_MSG_REQUEST = 0,
178 IPC_MSG_REPLY = 1
179};
180
181/* Global Message Types */
182enum skl_ipc_glb_type {
183 IPC_GLB_GET_FW_VERSION = 0, /* Retrieves firmware version */
184 IPC_GLB_LOAD_MULTIPLE_MODS = 15,
185 IPC_GLB_UNLOAD_MULTIPLE_MODS = 16,
186 IPC_GLB_CREATE_PPL = 17,
187 IPC_GLB_DELETE_PPL = 18,
188 IPC_GLB_SET_PPL_STATE = 19,
189 IPC_GLB_GET_PPL_STATE = 20,
190 IPC_GLB_GET_PPL_CONTEXT_SIZE = 21,
191 IPC_GLB_SAVE_PPL = 22,
192 IPC_GLB_RESTORE_PPL = 23,
20fb2fbd 193 IPC_GLB_LOAD_LIBRARY = 24,
b81fd263
SP		 194 IPC_GLB_NOTIFY = 26,
195 IPC_GLB_MAX_IPC_MSG_NUMBER = 31 /* Maximum message number */
196};
197
198enum skl_ipc_glb_reply {
199 IPC_GLB_REPLY_SUCCESS = 0,
200
201 IPC_GLB_REPLY_UNKNOWN_MSG_TYPE = 1,
202 IPC_GLB_REPLY_ERROR_INVALID_PARAM = 2,
203
204 IPC_GLB_REPLY_BUSY = 3,
205 IPC_GLB_REPLY_PENDING = 4,
206 IPC_GLB_REPLY_FAILURE = 5,
207 IPC_GLB_REPLY_INVALID_REQUEST = 6,
208
209 IPC_GLB_REPLY_OUT_OF_MEMORY = 7,
210 IPC_GLB_REPLY_OUT_OF_MIPS = 8,
211
212 IPC_GLB_REPLY_INVALID_RESOURCE_ID = 9,
213 IPC_GLB_REPLY_INVALID_RESOURCE_STATE = 10,
214
215 IPC_GLB_REPLY_MOD_MGMT_ERROR = 100,
216 IPC_GLB_REPLY_MOD_LOAD_CL_FAILED = 101,
217 IPC_GLB_REPLY_MOD_LOAD_INVALID_HASH = 102,
218
219 IPC_GLB_REPLY_MOD_UNLOAD_INST_EXIST = 103,
220 IPC_GLB_REPLY_MOD_NOT_INITIALIZED = 104,
221
222 IPC_GLB_REPLY_INVALID_CONFIG_PARAM_ID = 120,
223 IPC_GLB_REPLY_INVALID_CONFIG_DATA_LEN = 121,
224 IPC_GLB_REPLY_GATEWAY_NOT_INITIALIZED = 140,
225 IPC_GLB_REPLY_GATEWAY_NOT_EXIST = 141,
226
227 IPC_GLB_REPLY_PPL_NOT_INITIALIZED = 160,
228 IPC_GLB_REPLY_PPL_NOT_EXIST = 161,
229 IPC_GLB_REPLY_PPL_SAVE_FAILED = 162,
230 IPC_GLB_REPLY_PPL_RESTORE_FAILED = 163,
231
232 IPC_MAX_STATUS = ((1<<IPC_IXC_STATUS_BITS)-1)
233};
234
235enum skl_ipc_notification_type {
236 IPC_GLB_NOTIFY_GLITCH = 0,
237 IPC_GLB_NOTIFY_OVERRUN = 1,
238 IPC_GLB_NOTIFY_UNDERRUN = 2,
239 IPC_GLB_NOTIFY_END_STREAM = 3,
240 IPC_GLB_NOTIFY_PHRASE_DETECTED = 4,
241 IPC_GLB_NOTIFY_RESOURCE_EVENT = 5,
242 IPC_GLB_NOTIFY_LOG_BUFFER_STATUS = 6,
243 IPC_GLB_NOTIFY_TIMESTAMP_CAPTURED = 7,
244 IPC_GLB_NOTIFY_FW_READY = 8
245};
246
247/* Module Message Types */
248enum skl_ipc_module_msg {
249 IPC_MOD_INIT_INSTANCE = 0,
250 IPC_MOD_CONFIG_GET = 1,
251 IPC_MOD_CONFIG_SET = 2,
252 IPC_MOD_LARGE_CONFIG_GET = 3,
253 IPC_MOD_LARGE_CONFIG_SET = 4,
254 IPC_MOD_BIND = 5,
255 IPC_MOD_UNBIND = 6,
256 IPC_MOD_SET_DX = 7
257};
258
259static void skl_ipc_tx_data_copy(struct ipc_message *msg, char *tx_data,
260 size_t tx_size)
261{
262 if (tx_size)
263 memcpy(msg->tx_data, tx_data, tx_size);
264}
265
266static bool skl_ipc_is_dsp_busy(struct sst_dsp *dsp)
267{
268 u32 hipci;
269
270 hipci = sst_dsp_shim_read_unlocked(dsp, SKL_ADSP_REG_HIPCI);
271 return (hipci & SKL_ADSP_REG_HIPCI_BUSY);
272}
273
274/* Lock to be held by caller */
275static void skl_ipc_tx_msg(struct sst_generic_ipc *ipc, struct ipc_message *msg)
276{
277 struct skl_ipc_header *header = (struct skl_ipc_header *)(&msg->header);
278
279 if (msg->tx_size)
280 sst_dsp_outbox_write(ipc->dsp, msg->tx_data, msg->tx_size);
281 sst_dsp_shim_write_unlocked(ipc->dsp, SKL_ADSP_REG_HIPCIE,
282 header->extension);
283 sst_dsp_shim_write_unlocked(ipc->dsp, SKL_ADSP_REG_HIPCI,
284 header->primary | SKL_ADSP_REG_HIPCI_BUSY);
285}
286
287static struct ipc_message *skl_ipc_reply_get_msg(struct sst_generic_ipc *ipc,
288 u64 ipc_header)
289{
290 struct ipc_message *msg = NULL;
291 struct skl_ipc_header *header = (struct skl_ipc_header *)(&ipc_header);
292
293 if (list_empty(&ipc->rx_list)) {
294 dev_err(ipc->dev, "ipc: rx list is empty but received 0x%x\n",
295 header->primary);
296 goto out;
297 }
298
299 msg = list_first_entry(&ipc->rx_list, struct ipc_message, list);
300
301out:
302 return msg;
303
304}
305
306static int skl_ipc_process_notification(struct sst_generic_ipc *ipc,
307 struct skl_ipc_header header)
308{
309 struct skl_sst *skl = container_of(ipc, struct skl_sst, ipc);
310
311 if (IPC_GLB_NOTIFY_MSG_TYPE(header.primary)) {
312 switch (IPC_GLB_NOTIFY_TYPE(header.primary)) {
313
314 case IPC_GLB_NOTIFY_UNDERRUN:
315 dev_err(ipc->dev, "FW Underrun %x\n", header.primary);
316 break;
317
318 case IPC_GLB_NOTIFY_RESOURCE_EVENT:
319 dev_err(ipc->dev, "MCPS Budget Violation: %x\n",
320 header.primary);
321 break;
322
323 case IPC_GLB_NOTIFY_FW_READY:
324 skl->boot_complete = true;
325 wake_up(&skl->boot_wait);
326 break;
327
721c3e36
D		 328 case IPC_GLB_NOTIFY_PHRASE_DETECTED:
329 dev_dbg(ipc->dev, "***** Phrase Detected **********\n");
330
331 /*
332 * Per HW recomendation, After phrase detection,
333 * clear the CGCTL.MISCBDCGE.
334 *
335 * This will be set back on stream closure
336 */
337 skl->enable_miscbdcge(ipc->dev, false);
338 skl->miscbdcg_disabled = true;
339 break;
340
b81fd263
SP		 341 default:
342 dev_err(ipc->dev, "ipc: Unhandled error msg=%x",
343 header.primary);
344 break;
345 }
346 }
347
348 return 0;
349}
350
351static void skl_ipc_process_reply(struct sst_generic_ipc *ipc,
352 struct skl_ipc_header header)
353{
354 struct ipc_message *msg;
355 u32 reply = header.primary & IPC_GLB_REPLY_STATUS_MASK;
356 u64 *ipc_header = (u64 *)(&header);
357
358 msg = skl_ipc_reply_get_msg(ipc, *ipc_header);
359 if (msg == NULL) {
360 dev_dbg(ipc->dev, "ipc: rx list is empty\n");
361 return;
362 }
363
364 /* first process the header */
365 switch (reply) {
366 case IPC_GLB_REPLY_SUCCESS:
91c18325 367 dev_dbg(ipc->dev, "ipc FW reply %x: success\n", header.primary);
cce1c7f3
MJ		 368 /* copy the rx data from the mailbox */
369 sst_dsp_inbox_read(ipc->dsp, msg->rx_data, msg->rx_size);
b81fd263
SP		 370 break;
371
372 case IPC_GLB_REPLY_OUT_OF_MEMORY:
373 dev_err(ipc->dev, "ipc fw reply: %x: no memory\n", header.primary);
374 msg->errno = -ENOMEM;
375 break;
376
377 case IPC_GLB_REPLY_BUSY:
378 dev_err(ipc->dev, "ipc fw reply: %x: Busy\n", header.primary);
379 msg->errno = -EBUSY;
380 break;
381
382 default:
383 dev_err(ipc->dev, "Unknown ipc reply: 0x%x", reply);
384 msg->errno = -EINVAL;
385 break;
386 }
387
28f3b6f1
OA		 388 if (reply != IPC_GLB_REPLY_SUCCESS) {
389 dev_err(ipc->dev, "ipc FW reply: reply=%d", reply);
390 dev_err(ipc->dev, "FW Error Code: %u\n",
391 ipc->dsp->fw_ops.get_fw_errcode(ipc->dsp));
392 }
393
b81fd263
SP		 394 list_del(&msg->list);
395 sst_ipc_tx_msg_reply_complete(ipc, msg);
396}
397
398irqreturn_t skl_dsp_irq_thread_handler(int irq, void *context)
399{
400 struct sst_dsp *dsp = context;
401 struct skl_sst *skl = sst_dsp_get_thread_context(dsp);
402 struct sst_generic_ipc *ipc = &skl->ipc;
403 struct skl_ipc_header header = {0};
404 u32 hipcie, hipct, hipcte;
405 int ipc_irq = 0;
406
6cb00333
SP		 407 if (dsp->intr_status & SKL_ADSPIS_CL_DMA)
408 skl_cldma_process_intr(dsp);
409
b81fd263
SP		 410 /* Here we handle IPC interrupts only */
411 if (!(dsp->intr_status & SKL_ADSPIS_IPC))
412 return IRQ_NONE;
413
414 hipcie = sst_dsp_shim_read_unlocked(dsp, SKL_ADSP_REG_HIPCIE);
415 hipct = sst_dsp_shim_read_unlocked(dsp, SKL_ADSP_REG_HIPCT);
416
417 /* reply message from DSP */
418 if (hipcie & SKL_ADSP_REG_HIPCIE_DONE) {
419 sst_dsp_shim_update_bits(dsp, SKL_ADSP_REG_HIPCCTL,
420 SKL_ADSP_REG_HIPCCTL_DONE, 0);
421
422 /* clear DONE bit - tell DSP we have completed the operation */
423 sst_dsp_shim_update_bits_forced(dsp, SKL_ADSP_REG_HIPCIE,
424 SKL_ADSP_REG_HIPCIE_DONE, SKL_ADSP_REG_HIPCIE_DONE);
425
426 ipc_irq = 1;
427
428 /* unmask Done interrupt */
429 sst_dsp_shim_update_bits(dsp, SKL_ADSP_REG_HIPCCTL,
430 SKL_ADSP_REG_HIPCCTL_DONE, SKL_ADSP_REG_HIPCCTL_DONE);
431 }
432
433 /* New message from DSP */
434 if (hipct & SKL_ADSP_REG_HIPCT_BUSY) {
435 hipcte = sst_dsp_shim_read_unlocked(dsp, SKL_ADSP_REG_HIPCTE);
436 header.primary = hipct;
437 header.extension = hipcte;
438 dev_dbg(dsp->dev, "IPC irq: Firmware respond primary:%x",
439 header.primary);
440 dev_dbg(dsp->dev, "IPC irq: Firmware respond extension:%x",
441 header.extension);
442
443 if (IPC_GLB_NOTIFY_RSP_TYPE(header.primary)) {
444 /* Handle Immediate reply from DSP Core */
445 skl_ipc_process_reply(ipc, header);
446 } else {
447 dev_dbg(dsp->dev, "IPC irq: Notification from firmware\n");
448 skl_ipc_process_notification(ipc, header);
449 }
450 /* clear busy interrupt */
451 sst_dsp_shim_update_bits_forced(dsp, SKL_ADSP_REG_HIPCT,
452 SKL_ADSP_REG_HIPCT_BUSY, SKL_ADSP_REG_HIPCT_BUSY);
453 ipc_irq = 1;
454 }
455
456 if (ipc_irq == 0)
457 return IRQ_NONE;
458
459 skl_ipc_int_enable(dsp);
460
461 /* continue to send any remaining messages... */
462 queue_kthread_work(&ipc->kworker, &ipc->kwork);
463
464 return IRQ_HANDLED;
465}
466
467void skl_ipc_int_enable(struct sst_dsp *ctx)
468{
469 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_ADSPIC,
470 SKL_ADSPIC_IPC, SKL_ADSPIC_IPC);
471}
472
473void skl_ipc_int_disable(struct sst_dsp *ctx)
474{
475 sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_ADSPIC,
476 SKL_ADSPIC_IPC, 0);
477}
478
479void skl_ipc_op_int_enable(struct sst_dsp *ctx)
480{
481 /* enable IPC DONE interrupt */
482 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_HIPCCTL,
483 SKL_ADSP_REG_HIPCCTL_DONE, SKL_ADSP_REG_HIPCCTL_DONE);
484
485 /* Enable IPC BUSY interrupt */
486 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_HIPCCTL,
487 SKL_ADSP_REG_HIPCCTL_BUSY, SKL_ADSP_REG_HIPCCTL_BUSY);
488}
489
84c9e283
JK		 490void skl_ipc_op_int_disable(struct sst_dsp *ctx)
491{
492 /* disable IPC DONE interrupt */
493 sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_HIPCCTL,
494 SKL_ADSP_REG_HIPCCTL_DONE, 0);
495
496 /* Disable IPC BUSY interrupt */
497 sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_HIPCCTL,
498 SKL_ADSP_REG_HIPCCTL_BUSY, 0);
499
500}
501
b81fd263
SP		 502bool skl_ipc_int_status(struct sst_dsp *ctx)
503{
504 return sst_dsp_shim_read_unlocked(ctx,
505 SKL_ADSP_REG_ADSPIS) & SKL_ADSPIS_IPC;
506}
507
508int skl_ipc_init(struct device *dev, struct skl_sst *skl)
509{
510 struct sst_generic_ipc *ipc;
511 int err;
512
513 ipc = &skl->ipc;
514 ipc->dsp = skl->dsp;
515 ipc->dev = dev;
516
517 ipc->tx_data_max_size = SKL_ADSP_W1_SZ;
518 ipc->rx_data_max_size = SKL_ADSP_W0_UP_SZ;
519
520 err = sst_ipc_init(ipc);
521 if (err)
522 return err;
523
524 ipc->ops.tx_msg = skl_ipc_tx_msg;
525 ipc->ops.tx_data_copy = skl_ipc_tx_data_copy;
526 ipc->ops.is_dsp_busy = skl_ipc_is_dsp_busy;
527
528 return 0;
529}
530
531void skl_ipc_free(struct sst_generic_ipc *ipc)
532{
533 /* Disable IPC DONE interrupt */
534 sst_dsp_shim_update_bits(ipc->dsp, SKL_ADSP_REG_HIPCCTL,
535 SKL_ADSP_REG_HIPCCTL_DONE, 0);
536
537 /* Disable IPC BUSY interrupt */
538 sst_dsp_shim_update_bits(ipc->dsp, SKL_ADSP_REG_HIPCCTL,
539 SKL_ADSP_REG_HIPCCTL_BUSY, 0);
a750ba5f
SP		 540
541 sst_ipc_fini(ipc);
b81fd263
SP		 542}
543
544int skl_ipc_create_pipeline(struct sst_generic_ipc *ipc,
545 u16 ppl_mem_size, u8 ppl_type, u8 instance_id)
546{
547 struct skl_ipc_header header = {0};
548 u64 *ipc_header = (u64 *)(&header);
549 int ret;
550
551 header.primary = IPC_MSG_TARGET(IPC_FW_GEN_MSG);
552 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
553 header.primary |= IPC_GLB_TYPE(IPC_GLB_CREATE_PPL);
554 header.primary |= IPC_INSTANCE_ID(instance_id);
555 header.primary |= IPC_PPL_TYPE(ppl_type);
556 header.primary |= IPC_PPL_MEM_SIZE(ppl_mem_size);
557
558 dev_dbg(ipc->dev, "In %s header=%d\n", __func__, header.primary);
559 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, NULL, 0, NULL, 0);
560 if (ret < 0) {
561 dev_err(ipc->dev, "ipc: create pipeline fail, err: %d\n", ret);
562 return ret;
563 }
564
565 return ret;
566}
567EXPORT_SYMBOL_GPL(skl_ipc_create_pipeline);
568
569int skl_ipc_delete_pipeline(struct sst_generic_ipc *ipc, u8 instance_id)
570{
571 struct skl_ipc_header header = {0};
572 u64 *ipc_header = (u64 *)(&header);
573 int ret;
574
575 header.primary = IPC_MSG_TARGET(IPC_FW_GEN_MSG);
576 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
577 header.primary |= IPC_GLB_TYPE(IPC_GLB_DELETE_PPL);
578 header.primary |= IPC_INSTANCE_ID(instance_id);
579
580 dev_dbg(ipc->dev, "In %s header=%d\n", __func__, header.primary);
581 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, NULL, 0, NULL, 0);
582 if (ret < 0) {
583 dev_err(ipc->dev, "ipc: delete pipeline failed, err %d\n", ret);
584 return ret;
585 }
586
587 return 0;
588}
589EXPORT_SYMBOL_GPL(skl_ipc_delete_pipeline);
590
591int skl_ipc_set_pipeline_state(struct sst_generic_ipc *ipc,
592 u8 instance_id, enum skl_ipc_pipeline_state state)
593{
594 struct skl_ipc_header header = {0};
595 u64 *ipc_header = (u64 *)(&header);
596 int ret;
597
598 header.primary = IPC_MSG_TARGET(IPC_FW_GEN_MSG);
599 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
600 header.primary |= IPC_GLB_TYPE(IPC_GLB_SET_PPL_STATE);
601 header.primary |= IPC_INSTANCE_ID(instance_id);
602 header.primary |= IPC_PPL_STATE(state);
603
604 dev_dbg(ipc->dev, "In %s header=%d\n", __func__, header.primary);
605 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, NULL, 0, NULL, 0);
606 if (ret < 0) {
607 dev_err(ipc->dev, "ipc: set pipeline state failed, err: %d\n", ret);
608 return ret;
609 }
610 return ret;
611}
612EXPORT_SYMBOL_GPL(skl_ipc_set_pipeline_state);
613
614int
615skl_ipc_save_pipeline(struct sst_generic_ipc *ipc, u8 instance_id, int dma_id)
616{
617 struct skl_ipc_header header = {0};
618 u64 *ipc_header = (u64 *)(&header);
619 int ret;
620
621 header.primary = IPC_MSG_TARGET(IPC_FW_GEN_MSG);
622 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
623 header.primary |= IPC_GLB_TYPE(IPC_GLB_SAVE_PPL);
624 header.primary |= IPC_INSTANCE_ID(instance_id);
625
626 header.extension = IPC_DMA_ID(dma_id);
627 dev_dbg(ipc->dev, "In %s header=%d\n", __func__, header.primary);
628 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, NULL, 0, NULL, 0);
629 if (ret < 0) {
630 dev_err(ipc->dev, "ipc: save pipeline failed, err: %d\n", ret);
631 return ret;
632 }
633
634 return ret;
635}
636EXPORT_SYMBOL_GPL(skl_ipc_save_pipeline);
637
638int skl_ipc_restore_pipeline(struct sst_generic_ipc *ipc, u8 instance_id)
639{
640 struct skl_ipc_header header = {0};
641 u64 *ipc_header = (u64 *)(&header);
642 int ret;
643
644 header.primary = IPC_MSG_TARGET(IPC_FW_GEN_MSG);
645 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
646 header.primary |= IPC_GLB_TYPE(IPC_GLB_RESTORE_PPL);
647 header.primary |= IPC_INSTANCE_ID(instance_id);
648
649 dev_dbg(ipc->dev, "In %s header=%d\n", __func__, header.primary);
650 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, NULL, 0, NULL, 0);
651 if (ret < 0) {
652 dev_err(ipc->dev, "ipc: restore pipeline failed, err: %d\n", ret);
653 return ret;
654 }
655
656 return ret;
657}
658EXPORT_SYMBOL_GPL(skl_ipc_restore_pipeline);
659
660int skl_ipc_set_dx(struct sst_generic_ipc *ipc, u8 instance_id,
661 u16 module_id, struct skl_ipc_dxstate_info *dx)
662{
663 struct skl_ipc_header header = {0};
664 u64 *ipc_header = (u64 *)(&header);
665 int ret;
666
667 header.primary = IPC_MSG_TARGET(IPC_MOD_MSG);
668 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
669 header.primary |= IPC_GLB_TYPE(IPC_MOD_SET_DX);
670 header.primary |= IPC_MOD_INSTANCE_ID(instance_id);
671 header.primary |= IPC_MOD_ID(module_id);
672
673 dev_dbg(ipc->dev, "In %s primary =%x ext=%x\n", __func__,
674 header.primary, header.extension);
675 ret = sst_ipc_tx_message_wait(ipc, *ipc_header,
aaec7e9f 676 dx, sizeof(*dx), NULL, 0);
b81fd263
SP		 677 if (ret < 0) {
678 dev_err(ipc->dev, "ipc: set dx failed, err %d\n", ret);
679 return ret;
680 }
681
682 return ret;
683}
684EXPORT_SYMBOL_GPL(skl_ipc_set_dx);
685
686int skl_ipc_init_instance(struct sst_generic_ipc *ipc,
687 struct skl_ipc_init_instance_msg *msg, void *param_data)
688{
689 struct skl_ipc_header header = {0};
690 u64 *ipc_header = (u64 *)(&header);
691 int ret;
692 u32 *buffer = (u32 *)param_data;
693 /* param_block_size must be in dwords */
694 u16 param_block_size = msg->param_data_size / sizeof(u32);
695
96bd6033 696 print_hex_dump_debug("Param data:", DUMP_PREFIX_NONE,
b81fd263
SP		 697 16, 4, buffer, param_block_size, false);
698
699 header.primary = IPC_MSG_TARGET(IPC_MOD_MSG);
700 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
701 header.primary |= IPC_GLB_TYPE(IPC_MOD_INIT_INSTANCE);
702 header.primary |= IPC_MOD_INSTANCE_ID(msg->instance_id);
703 header.primary |= IPC_MOD_ID(msg->module_id);
704
705 header.extension = IPC_CORE_ID(msg->core_id);
706 header.extension |= IPC_PPL_INSTANCE_ID(msg->ppl_instance_id);
707 header.extension |= IPC_PARAM_BLOCK_SIZE(param_block_size);
708
709 dev_dbg(ipc->dev, "In %s primary =%x ext=%x\n", __func__,
710 header.primary, header.extension);
711 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, param_data,
712 msg->param_data_size, NULL, 0);
713
714 if (ret < 0) {
715 dev_err(ipc->dev, "ipc: init instance failed\n");
716 return ret;
717 }
718
719 return ret;
720}
721EXPORT_SYMBOL_GPL(skl_ipc_init_instance);
722
723int skl_ipc_bind_unbind(struct sst_generic_ipc *ipc,
724 struct skl_ipc_bind_unbind_msg *msg)
725{
726 struct skl_ipc_header header = {0};
727 u64 *ipc_header = (u64 *)(&header);
728 u8 bind_unbind = msg->bind ? IPC_MOD_BIND : IPC_MOD_UNBIND;
729 int ret;
730
731 header.primary = IPC_MSG_TARGET(IPC_MOD_MSG);
732 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
733 header.primary |= IPC_GLB_TYPE(bind_unbind);
734 header.primary |= IPC_MOD_INSTANCE_ID(msg->instance_id);
735 header.primary |= IPC_MOD_ID(msg->module_id);
736
737 header.extension = IPC_DST_MOD_ID(msg->dst_module_id);
738 header.extension |= IPC_DST_MOD_INSTANCE_ID(msg->dst_instance_id);
739 header.extension |= IPC_DST_QUEUE(msg->dst_queue);
740 header.extension |= IPC_SRC_QUEUE(msg->src_queue);
741
742 dev_dbg(ipc->dev, "In %s hdr=%x ext=%x\n", __func__, header.primary,
743 header.extension);
744 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, NULL, 0, NULL, 0);
745 if (ret < 0) {
746 dev_err(ipc->dev, "ipc: bind/unbind faileden");
747 return ret;
748 }
749
750 return ret;
751}
752EXPORT_SYMBOL_GPL(skl_ipc_bind_unbind);
753
6c5768b3
D		 754/*
755 * In order to load a module we need to send IPC to initiate that. DMA will
756 * performed to load the module memory. The FW supports multiple module load
757 * at single shot, so we can send IPC with N modules represented by
758 * module_cnt
759 */
760int skl_ipc_load_modules(struct sst_generic_ipc *ipc,
761 u8 module_cnt, void *data)
762{
763 struct skl_ipc_header header = {0};
764 u64 *ipc_header = (u64 *)(&header);
765 int ret;
766
767 header.primary = IPC_MSG_TARGET(IPC_FW_GEN_MSG);
768 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
769 header.primary |= IPC_GLB_TYPE(IPC_GLB_LOAD_MULTIPLE_MODS);
770 header.primary |= IPC_LOAD_MODULE_CNT(module_cnt);
771
772 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, data,
773 (sizeof(u16) * module_cnt), NULL, 0);
774 if (ret < 0)
775 dev_err(ipc->dev, "ipc: load modules failed :%d\n", ret);
776
777 return ret;
778}
779EXPORT_SYMBOL_GPL(skl_ipc_load_modules);
780
781int skl_ipc_unload_modules(struct sst_generic_ipc *ipc, u8 module_cnt,
782 void *data)
783{
784 struct skl_ipc_header header = {0};
785 u64 *ipc_header = (u64 *)(&header);
786 int ret;
787
788 header.primary = IPC_MSG_TARGET(IPC_FW_GEN_MSG);
789 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
790 header.primary |= IPC_GLB_TYPE(IPC_GLB_UNLOAD_MULTIPLE_MODS);
791 header.primary |= IPC_LOAD_MODULE_CNT(module_cnt);
792
793 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, data,
794 (sizeof(u16) * module_cnt), NULL, 0);
795 if (ret < 0)
796 dev_err(ipc->dev, "ipc: unload modules failed :%d\n", ret);
797
798 return ret;
799}
800EXPORT_SYMBOL_GPL(skl_ipc_unload_modules);
801
b81fd263
SP		 802int skl_ipc_set_large_config(struct sst_generic_ipc *ipc,
803 struct skl_ipc_large_config_msg *msg, u32 *param)
804{
805 struct skl_ipc_header header = {0};
806 u64 *ipc_header = (u64 *)(&header);
807 int ret = 0;
808 size_t sz_remaining, tx_size, data_offset;
809
810 header.primary = IPC_MSG_TARGET(IPC_MOD_MSG);
811 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
812 header.primary |= IPC_GLB_TYPE(IPC_MOD_LARGE_CONFIG_SET);
813 header.primary |= IPC_MOD_INSTANCE_ID(msg->instance_id);
814 header.primary |= IPC_MOD_ID(msg->module_id);
815
816 header.extension = IPC_DATA_OFFSET_SZ(msg->param_data_size);
817 header.extension |= IPC_LARGE_PARAM_ID(msg->large_param_id);
818 header.extension |= IPC_FINAL_BLOCK(0);
819 header.extension |= IPC_INITIAL_BLOCK(1);
820
821 sz_remaining = msg->param_data_size;
822 data_offset = 0;
823 while (sz_remaining != 0) {
824 tx_size = sz_remaining > SKL_ADSP_W1_SZ
825 ? SKL_ADSP_W1_SZ : sz_remaining;
826 if (tx_size == sz_remaining)
827 header.extension |= IPC_FINAL_BLOCK(1);
828
829 dev_dbg(ipc->dev, "In %s primary=%#x ext=%#x\n", __func__,
830 header.primary, header.extension);
831 dev_dbg(ipc->dev, "transmitting offset: %#x, size: %#x\n",
832 (unsigned)data_offset, (unsigned)tx_size);
833 ret = sst_ipc_tx_message_wait(ipc, *ipc_header,
834 ((char *)param) + data_offset,
835 tx_size, NULL, 0);
836 if (ret < 0) {
837 dev_err(ipc->dev,
838 "ipc: set large config fail, err: %d\n", ret);
839 return ret;
840 }
841 sz_remaining -= tx_size;
842 data_offset = msg->param_data_size - sz_remaining;
843
844 /* clear the fields */
845 header.extension &= IPC_INITIAL_BLOCK_CLEAR;
846 header.extension &= IPC_DATA_OFFSET_SZ_CLEAR;
847 /* fill the fields */
848 header.extension |= IPC_INITIAL_BLOCK(0);
849 header.extension |= IPC_DATA_OFFSET_SZ(data_offset);
850 }
851
852 return ret;
853}
854EXPORT_SYMBOL_GPL(skl_ipc_set_large_config);
cce1c7f3
MJ		 855
856int skl_ipc_get_large_config(struct sst_generic_ipc *ipc,
857 struct skl_ipc_large_config_msg *msg, u32 *param)
858{
859 struct skl_ipc_header header = {0};
860 u64 *ipc_header = (u64 *)(&header);
861 int ret = 0;
862 size_t sz_remaining, rx_size, data_offset;
863
864 header.primary = IPC_MSG_TARGET(IPC_MOD_MSG);
865 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
866 header.primary |= IPC_GLB_TYPE(IPC_MOD_LARGE_CONFIG_GET);
867 header.primary |= IPC_MOD_INSTANCE_ID(msg->instance_id);
868 header.primary |= IPC_MOD_ID(msg->module_id);
869
870 header.extension = IPC_DATA_OFFSET_SZ(msg->param_data_size);
871 header.extension |= IPC_LARGE_PARAM_ID(msg->large_param_id);
872 header.extension |= IPC_FINAL_BLOCK(1);
873 header.extension |= IPC_INITIAL_BLOCK(1);
874
875 sz_remaining = msg->param_data_size;
876 data_offset = 0;
877
878 while (sz_remaining != 0) {
879 rx_size = sz_remaining > SKL_ADSP_W1_SZ
880 ? SKL_ADSP_W1_SZ : sz_remaining;
881 if (rx_size == sz_remaining)
882 header.extension |= IPC_FINAL_BLOCK(1);
883
884 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, NULL, 0,
885 ((char *)param) + data_offset,
886 msg->param_data_size);
887 if (ret < 0) {
888 dev_err(ipc->dev,
889 "ipc: get large config fail, err: %d\n", ret);
890 return ret;
891 }
892 sz_remaining -= rx_size;
893 data_offset = msg->param_data_size - sz_remaining;
894
895 /* clear the fields */
896 header.extension &= IPC_INITIAL_BLOCK_CLEAR;
897 header.extension &= IPC_DATA_OFFSET_SZ_CLEAR;
898 /* fill the fields */
899 header.extension |= IPC_INITIAL_BLOCK(1);
900 header.extension |= IPC_DATA_OFFSET_SZ(data_offset);
901 }
902
903 return ret;
904}
905EXPORT_SYMBOL_GPL(skl_ipc_get_large_config);
20fb2fbd
RB		 906
907int skl_sst_ipc_load_library(struct sst_generic_ipc *ipc,
908 u8 dma_id, u8 table_id)
909{
910 struct skl_ipc_header header = {0};
911 u64 *ipc_header = (u64 *)(&header);
912 int ret = 0;
913
914 header.primary = IPC_MSG_TARGET(IPC_FW_GEN_MSG);
915 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
916 header.primary |= IPC_GLB_TYPE(IPC_GLB_LOAD_LIBRARY);
917 header.primary |= IPC_MOD_INSTANCE_ID(table_id);
918 header.primary |= IPC_MOD_ID(dma_id);
919
920 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, NULL, 0, NULL, 0);
921
922 if (ret < 0)
923 dev_err(ipc->dev, "ipc: load lib failed\n");
924
925 return ret;
926}
927EXPORT_SYMBOL_GPL(skl_sst_ipc_load_library);
Linux kernel - Deliverables
This page took 0.093771 seconds and 5 git commands to generate.