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23db472b JK |
1 | /* |
2 | * skl-tplg-interface.h - Intel DSP FW private data interface | |
3 | * | |
4 | * Copyright (C) 2015 Intel Corp | |
5 | * Author: Jeeja KP <jeeja.kp@intel.com> | |
6 | * Nilofer, Samreen <samreen.nilofer@intel.com> | |
7 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as version 2, as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | */ | |
18 | ||
19 | #ifndef __HDA_TPLG_INTERFACE_H__ | |
20 | #define __HDA_TPLG_INTERFACE_H__ | |
21 | ||
3af36706 VK |
22 | /* |
23 | * Default types range from 0~12. type can range from 0 to 0xff | |
24 | * SST types start at higher to avoid any overlapping in future | |
25 | */ | |
140adfba | 26 | #define SKL_CONTROL_TYPE_BYTE_TLV 0x100 |
3af36706 VK |
27 | |
28 | #define HDA_SST_CFG_MAX 900 /* size of copier cfg*/ | |
29 | #define MAX_IN_QUEUE 8 | |
30 | #define MAX_OUT_QUEUE 8 | |
31 | ||
65aecfa8 | 32 | #define SKL_UUID_STR_SZ 40 |
3af36706 VK |
33 | /* Event types goes here */ |
34 | /* Reserve event type 0 for no event handlers */ | |
35 | enum skl_event_types { | |
36 | SKL_EVENT_NONE = 0, | |
37 | SKL_MIXER_EVENT, | |
38 | SKL_MUX_EVENT, | |
39 | SKL_VMIXER_EVENT, | |
40 | SKL_PGA_EVENT | |
41 | }; | |
42 | ||
23db472b JK |
43 | /** |
44 | * enum skl_ch_cfg - channel configuration | |
45 | * | |
46 | * @SKL_CH_CFG_MONO: One channel only | |
47 | * @SKL_CH_CFG_STEREO: L & R | |
48 | * @SKL_CH_CFG_2_1: L, R & LFE | |
49 | * @SKL_CH_CFG_3_0: L, C & R | |
50 | * @SKL_CH_CFG_3_1: L, C, R & LFE | |
51 | * @SKL_CH_CFG_QUATRO: L, R, Ls & Rs | |
52 | * @SKL_CH_CFG_4_0: L, C, R & Cs | |
53 | * @SKL_CH_CFG_5_0: L, C, R, Ls & Rs | |
54 | * @SKL_CH_CFG_5_1: L, C, R, Ls, Rs & LFE | |
55 | * @SKL_CH_CFG_DUAL_MONO: One channel replicated in two | |
56 | * @SKL_CH_CFG_I2S_DUAL_STEREO_0: Stereo(L,R) in 4 slots, 1st stream:[ L, R, -, - ] | |
57 | * @SKL_CH_CFG_I2S_DUAL_STEREO_1: Stereo(L,R) in 4 slots, 2nd stream:[ -, -, L, R ] | |
58 | * @SKL_CH_CFG_INVALID: Invalid | |
59 | */ | |
60 | enum skl_ch_cfg { | |
61 | SKL_CH_CFG_MONO = 0, | |
62 | SKL_CH_CFG_STEREO = 1, | |
63 | SKL_CH_CFG_2_1 = 2, | |
64 | SKL_CH_CFG_3_0 = 3, | |
65 | SKL_CH_CFG_3_1 = 4, | |
66 | SKL_CH_CFG_QUATRO = 5, | |
67 | SKL_CH_CFG_4_0 = 6, | |
68 | SKL_CH_CFG_5_0 = 7, | |
69 | SKL_CH_CFG_5_1 = 8, | |
70 | SKL_CH_CFG_DUAL_MONO = 9, | |
71 | SKL_CH_CFG_I2S_DUAL_STEREO_0 = 10, | |
72 | SKL_CH_CFG_I2S_DUAL_STEREO_1 = 11, | |
04afbbbb | 73 | SKL_CH_CFG_4_CHANNEL = 12, |
23db472b JK |
74 | SKL_CH_CFG_INVALID |
75 | }; | |
76 | ||
77 | enum skl_module_type { | |
78 | SKL_MODULE_TYPE_MIXER = 0, | |
79 | SKL_MODULE_TYPE_COPIER, | |
80 | SKL_MODULE_TYPE_UPDWMIX, | |
399b210b | 81 | SKL_MODULE_TYPE_SRCINT, |
fd18110f D |
82 | SKL_MODULE_TYPE_ALGO, |
83 | SKL_MODULE_TYPE_BASE_OUTFMT | |
23db472b JK |
84 | }; |
85 | ||
86 | enum skl_core_affinity { | |
87 | SKL_AFFINITY_CORE_0 = 0, | |
88 | SKL_AFFINITY_CORE_1, | |
89 | SKL_AFFINITY_CORE_MAX | |
90 | }; | |
91 | ||
92 | enum skl_pipe_conn_type { | |
93 | SKL_PIPE_CONN_TYPE_NONE = 0, | |
94 | SKL_PIPE_CONN_TYPE_FE, | |
95 | SKL_PIPE_CONN_TYPE_BE | |
96 | }; | |
97 | ||
98 | enum skl_hw_conn_type { | |
99 | SKL_CONN_NONE = 0, | |
100 | SKL_CONN_SOURCE = 1, | |
101 | SKL_CONN_SINK = 2 | |
102 | }; | |
103 | ||
104 | enum skl_dev_type { | |
105 | SKL_DEVICE_BT = 0x0, | |
106 | SKL_DEVICE_DMIC = 0x1, | |
107 | SKL_DEVICE_I2S = 0x2, | |
108 | SKL_DEVICE_SLIMBUS = 0x3, | |
109 | SKL_DEVICE_HDALINK = 0x4, | |
bfa764ac | 110 | SKL_DEVICE_HDAHOST = 0x5, |
23db472b JK |
111 | SKL_DEVICE_NONE |
112 | }; | |
3af36706 | 113 | |
04afbbbb HS |
114 | /** |
115 | * enum skl_interleaving - interleaving style | |
116 | * | |
117 | * @SKL_INTERLEAVING_PER_CHANNEL: [s1_ch1...s1_chN,...,sM_ch1...sM_chN] | |
118 | * @SKL_INTERLEAVING_PER_SAMPLE: [s1_ch1...sM_ch1,...,s1_chN...sM_chN] | |
119 | */ | |
120 | enum skl_interleaving { | |
121 | SKL_INTERLEAVING_PER_CHANNEL = 0, | |
122 | SKL_INTERLEAVING_PER_SAMPLE = 1, | |
123 | }; | |
124 | ||
125 | enum skl_sample_type { | |
126 | SKL_SAMPLE_TYPE_INT_MSB = 0, | |
127 | SKL_SAMPLE_TYPE_INT_LSB = 1, | |
128 | SKL_SAMPLE_TYPE_INT_SIGNED = 2, | |
129 | SKL_SAMPLE_TYPE_INT_UNSIGNED = 3, | |
130 | SKL_SAMPLE_TYPE_FLOAT = 4 | |
131 | }; | |
132 | ||
4cd9899f HS |
133 | enum module_pin_type { |
134 | /* All pins of the module takes same PCM inputs or outputs | |
135 | * e.g. mixout | |
136 | */ | |
137 | SKL_PIN_TYPE_HOMOGENEOUS, | |
138 | /* All pins of the module takes different PCM inputs or outputs | |
139 | * e.g mux | |
140 | */ | |
141 | SKL_PIN_TYPE_HETEROGENEOUS, | |
142 | }; | |
143 | ||
4ced1827 JK |
144 | enum skl_module_param_type { |
145 | SKL_PARAM_DEFAULT = 0, | |
146 | SKL_PARAM_INIT, | |
cc6a4044 JK |
147 | SKL_PARAM_SET, |
148 | SKL_PARAM_BIND | |
4ced1827 JK |
149 | }; |
150 | ||
3af36706 VK |
151 | struct skl_dfw_module_pin { |
152 | u16 module_id; | |
153 | u16 instance_id; | |
3af36706 VK |
154 | } __packed; |
155 | ||
156 | struct skl_dfw_module_fmt { | |
157 | u32 channels; | |
158 | u32 freq; | |
159 | u32 bit_depth; | |
160 | u32 valid_bit_depth; | |
161 | u32 ch_cfg; | |
4cd9899f HS |
162 | u32 interleaving_style; |
163 | u32 sample_type; | |
164 | u32 ch_map; | |
3af36706 VK |
165 | } __packed; |
166 | ||
167 | struct skl_dfw_module_caps { | |
4ced1827 JK |
168 | u32 set_params:2; |
169 | u32 rsvd:30; | |
04afbbbb | 170 | u32 param_id; |
3af36706 VK |
171 | u32 caps_size; |
172 | u32 caps[HDA_SST_CFG_MAX]; | |
173 | }; | |
174 | ||
175 | struct skl_dfw_pipe { | |
176 | u8 pipe_id; | |
177 | u8 pipe_priority; | |
04afbbbb HS |
178 | u16 conn_type:4; |
179 | u16 rsvd:4; | |
180 | u16 memory_pages:8; | |
3af36706 VK |
181 | } __packed; |
182 | ||
183 | struct skl_dfw_module { | |
09305da9 | 184 | u8 uuid[16]; |
65aecfa8 | 185 | |
3af36706 VK |
186 | u16 module_id; |
187 | u16 instance_id; | |
188 | u32 max_mcps; | |
04afbbbb | 189 | u32 mem_pages; |
3af36706 VK |
190 | u32 obs; |
191 | u32 ibs; | |
3af36706 | 192 | u32 vbus_id; |
04afbbbb HS |
193 | |
194 | u32 max_in_queue:8; | |
195 | u32 max_out_queue:8; | |
196 | u32 time_slot:8; | |
197 | u32 core_id:4; | |
198 | u32 rsvd1:4; | |
199 | ||
200 | u32 module_type:8; | |
201 | u32 conn_type:4; | |
202 | u32 dev_type:4; | |
203 | u32 hw_conn_type:4; | |
204 | u32 rsvd2:12; | |
205 | ||
206 | u32 params_fixup:8; | |
207 | u32 converter:8; | |
208 | u32 input_pin_type:1; | |
209 | u32 output_pin_type:1; | |
210 | u32 is_dynamic_in_pin:1; | |
211 | u32 is_dynamic_out_pin:1; | |
212 | u32 is_loadable:1; | |
213 | u32 rsvd3:11; | |
214 | ||
3af36706 | 215 | struct skl_dfw_pipe pipe; |
4cd9899f HS |
216 | struct skl_dfw_module_fmt in_fmt[MAX_IN_QUEUE]; |
217 | struct skl_dfw_module_fmt out_fmt[MAX_OUT_QUEUE]; | |
6abca1d7 JK |
218 | struct skl_dfw_module_pin in_pin[MAX_IN_QUEUE]; |
219 | struct skl_dfw_module_pin out_pin[MAX_OUT_QUEUE]; | |
3af36706 VK |
220 | struct skl_dfw_module_caps caps; |
221 | } __packed; | |
222 | ||
223 | struct skl_dfw_algo_data { | |
4ced1827 JK |
224 | u32 set_params:2; |
225 | u32 rsvd:30; | |
140adfba | 226 | u32 param_id; |
4ced1827 | 227 | u32 max; |
04afbbbb | 228 | char params[0]; |
3af36706 VK |
229 | } __packed; |
230 | ||
23db472b | 231 | #endif |