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Merge branch 'audit-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/mszeredi/vfs
[deliverable/linux.git] / sound / soc / omap / mcbsp.c
CommitLineData
5e1c5ff4 1/*
71e822e9 2 * sound/soc/omap/mcbsp.c
5e1c5ff4
TL		 3 *
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
6 *
71e822e9
PU		 7 * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
8 * Peter Ujfalusi <peter.ujfalusi@ti.com>
5e1c5ff4
TL		 9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * Multichannel mode not supported.
15 */
16
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/device.h>
bc5d0c89 20#include <linux/platform_device.h>
5e1c5ff4
TL		 21#include <linux/interrupt.h>
22#include <linux/err.h>
f8ce2547 23#include <linux/clk.h>
04fbf6a2 24#include <linux/delay.h>
fb78d808 25#include <linux/io.h>
5a0e3ad6 26#include <linux/slab.h>
5e1c5ff4 27
ce491cf8 28#include <plat/mcbsp.h>
5e1c5ff4 29
219f4316
PU		 30#include "mcbsp.h"
31
b0a330dc 32static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
b4b58f58 33{
cdc71514
JN		 34 void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
35
36 if (mcbsp->pdata->reg_size == 2) {
37 ((u16 *)mcbsp->reg_cache)[reg] = (u16)val;
38 __raw_writew((u16)val, addr);
c8c99699 39 } else {
cdc71514
JN		 40 ((u32 *)mcbsp->reg_cache)[reg] = val;
41 __raw_writel(val, addr);
c8c99699 42 }
b4b58f58
CS		 43}
44
b0a330dc 45static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
b4b58f58 46{
cdc71514
JN		 47 void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
48
49 if (mcbsp->pdata->reg_size == 2) {
50 return !from_cache ? __raw_readw(addr) :
51 ((u16 *)mcbsp->reg_cache)[reg];
c8c99699 52 } else {
cdc71514
JN		 53 return !from_cache ? __raw_readl(addr) :
54 ((u32 *)mcbsp->reg_cache)[reg];
c8c99699 55 }
b4b58f58
CS		 56}
57
b0a330dc 58static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
d912fa92
EN		 59{
60 __raw_writel(val, mcbsp->st_data->io_base_st + reg);
61}
62
b0a330dc 63static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
d912fa92
EN		 64{
65 return __raw_readl(mcbsp->st_data->io_base_st + reg);
66}
d912fa92 67
8ea3200f 68#define MCBSP_READ(mcbsp, reg) \
c8c99699 69 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
8ea3200f
JK		 70#define MCBSP_WRITE(mcbsp, reg, val) \
71 omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
c8c99699
JK		 72#define MCBSP_READ_CACHE(mcbsp, reg) \
73 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
b4b58f58 74
d912fa92
EN		 75#define MCBSP_ST_READ(mcbsp, reg) \
76 omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
77#define MCBSP_ST_WRITE(mcbsp, reg, val) \
78 omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
79
45656b44 80static void omap_mcbsp_dump_reg(struct omap_mcbsp *mcbsp)
5e1c5ff4 81{
b4b58f58
CS		 82 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
83 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n",
8ea3200f 84 MCBSP_READ(mcbsp, DRR2));
b4b58f58 85 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n",
8ea3200f 86 MCBSP_READ(mcbsp, DRR1));
b4b58f58 87 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n",
8ea3200f 88 MCBSP_READ(mcbsp, DXR2));
b4b58f58 89 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n",
8ea3200f 90 MCBSP_READ(mcbsp, DXR1));
b4b58f58 91 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
8ea3200f 92 MCBSP_READ(mcbsp, SPCR2));
b4b58f58 93 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
8ea3200f 94 MCBSP_READ(mcbsp, SPCR1));
b4b58f58 95 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n",
8ea3200f 96 MCBSP_READ(mcbsp, RCR2));
b4b58f58 97 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n",
8ea3200f 98 MCBSP_READ(mcbsp, RCR1));
b4b58f58 99 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n",
8ea3200f 100 MCBSP_READ(mcbsp, XCR2));
b4b58f58 101 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n",
8ea3200f 102 MCBSP_READ(mcbsp, XCR1));
b4b58f58 103 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
8ea3200f 104 MCBSP_READ(mcbsp, SRGR2));
b4b58f58 105 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
8ea3200f 106 MCBSP_READ(mcbsp, SRGR1));
b4b58f58 107 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n",
8ea3200f 108 MCBSP_READ(mcbsp, PCR0));
b4b58f58 109 dev_dbg(mcbsp->dev, "***********************\n");
5e1c5ff4
TL		 110}
111
35d210fa
PU		 112static irqreturn_t omap_mcbsp_irq_handler(int irq, void *dev_id)
113{
114 struct omap_mcbsp *mcbsp = dev_id;
115 u16 irqst;
116
117 irqst = MCBSP_READ(mcbsp, IRQST);
118 dev_dbg(mcbsp->dev, "IRQ callback : 0x%x\n", irqst);
119
120 if (irqst & RSYNCERREN)
121 dev_err(mcbsp->dev, "RX Frame Sync Error!\n");
122 if (irqst & RFSREN)
123 dev_dbg(mcbsp->dev, "RX Frame Sync\n");
124 if (irqst & REOFEN)
125 dev_dbg(mcbsp->dev, "RX End Of Frame\n");
126 if (irqst & RRDYEN)
127 dev_dbg(mcbsp->dev, "RX Buffer Threshold Reached\n");
128 if (irqst & RUNDFLEN)
129 dev_err(mcbsp->dev, "RX Buffer Underflow!\n");
130 if (irqst & ROVFLEN)
131 dev_err(mcbsp->dev, "RX Buffer Overflow!\n");
132
133 if (irqst & XSYNCERREN)
134 dev_err(mcbsp->dev, "TX Frame Sync Error!\n");
135 if (irqst & XFSXEN)
136 dev_dbg(mcbsp->dev, "TX Frame Sync\n");
137 if (irqst & XEOFEN)
138 dev_dbg(mcbsp->dev, "TX End Of Frame\n");
139 if (irqst & XRDYEN)
140 dev_dbg(mcbsp->dev, "TX Buffer threshold Reached\n");
141 if (irqst & XUNDFLEN)
142 dev_err(mcbsp->dev, "TX Buffer Underflow!\n");
143 if (irqst & XOVFLEN)
144 dev_err(mcbsp->dev, "TX Buffer Overflow!\n");
145 if (irqst & XEMPTYEOFEN)
146 dev_dbg(mcbsp->dev, "TX Buffer empty at end of frame\n");
147
148 MCBSP_WRITE(mcbsp, IRQST, irqst);
149
150 return IRQ_HANDLED;
151}
152
0cd61b68 153static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
5e1c5ff4 154{
e8f2af17 155 struct omap_mcbsp *mcbsp_tx = dev_id;
d6d834b0 156 u16 irqst_spcr2;
5e1c5ff4 157
8ea3200f 158 irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
d6d834b0 159 dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
5e1c5ff4 160
d6d834b0
EN		 161 if (irqst_spcr2 & XSYNC_ERR) {
162 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
163 irqst_spcr2);
164 /* Writing zero to XSYNC_ERR clears the IRQ */
0841cb82 165 MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
d6d834b0 166 }
fb78d808 167
5e1c5ff4
TL		 168 return IRQ_HANDLED;
169}
170
0cd61b68 171static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
5e1c5ff4 172{
e8f2af17 173 struct omap_mcbsp *mcbsp_rx = dev_id;
d6d834b0
EN		 174 u16 irqst_spcr1;
175
8ea3200f 176 irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
d6d834b0
EN		 177 dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
178
179 if (irqst_spcr1 & RSYNC_ERR) {
180 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
181 irqst_spcr1);
182 /* Writing zero to RSYNC_ERR clears the IRQ */
0841cb82 183 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
d6d834b0 184 }
fb78d808 185
5e1c5ff4
TL		 186 return IRQ_HANDLED;
187}
188
5e1c5ff4
TL		 189/*
190 * omap_mcbsp_config simply write a config to the
191 * appropriate McBSP.
192 * You either call this function or set the McBSP registers
193 * by yourself before calling omap_mcbsp_start().
194 */
45656b44
PU		 195void omap_mcbsp_config(struct omap_mcbsp *mcbsp,
196 const struct omap_mcbsp_reg_cfg *config)
5e1c5ff4 197{
b4b58f58
CS		 198 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
199 mcbsp->id, mcbsp->phys_base);
5e1c5ff4
TL		 200
201 /* We write the given config */
8ea3200f
JK		 202 MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
203 MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
204 MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
205 MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
206 MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
207 MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
208 MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
209 MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
210 MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
211 MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
212 MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
88408230 213 if (mcbsp->pdata->has_ccr) {
8ea3200f
JK		 214 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
215 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
3127f8f8 216 }
08905d8a
PU		 217 /* Enable wakeup behavior */
218 if (mcbsp->pdata->has_wakeup)
219 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
35d210fa
PU		 220
221 /* Enable TX/RX sync error interrupts by default */
222 if (mcbsp->irq)
223 MCBSP_WRITE(mcbsp, IRQEN, RSYNCERREN | XSYNCERREN);
5e1c5ff4 224}
5e1c5ff4 225
9504ba64
KVA		 226/**
227 * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
228 * @id - mcbsp id
229 * @stream - indicates the direction of data flow (rx or tx)
230 *
231 * Returns the address of mcbsp data transmit register or data receive register
232 * to be used by DMA for transferring/receiving data based on the value of
233 * @stream for the requested mcbsp given by @id
234 */
b8fb4907
PU		 235static int omap_mcbsp_dma_reg_params(struct omap_mcbsp *mcbsp,
236 unsigned int stream)
9504ba64 237{
9504ba64
KVA		 238 int data_reg;
239
cdc71514 240 if (mcbsp->pdata->reg_size == 2) {
9504ba64 241 if (stream)
cdc71514 242 data_reg = OMAP_MCBSP_REG_DRR1;
9504ba64 243 else
cdc71514 244 data_reg = OMAP_MCBSP_REG_DXR1;
9504ba64
KVA		 245 } else {
246 if (stream)
cdc71514 247 data_reg = OMAP_MCBSP_REG_DRR;
9504ba64 248 else
cdc71514 249 data_reg = OMAP_MCBSP_REG_DXR;
9504ba64
KVA		 250 }
251
cdc71514 252 return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step;
9504ba64 253}
9504ba64 254
d912fa92
EN		 255static void omap_st_on(struct omap_mcbsp *mcbsp)
256{
257 unsigned int w;
258
1743d14f
JN		 259 if (mcbsp->pdata->enable_st_clock)
260 mcbsp->pdata->enable_st_clock(mcbsp->id, 1);
d912fa92
EN		 261
262 /* Enable McBSP Sidetone */
263 w = MCBSP_READ(mcbsp, SSELCR);
264 MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
265
d912fa92
EN		 266 /* Enable Sidetone from Sidetone Core */
267 w = MCBSP_ST_READ(mcbsp, SSELCR);
268 MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
269}
270
271static void omap_st_off(struct omap_mcbsp *mcbsp)
272{
273 unsigned int w;
274
275 w = MCBSP_ST_READ(mcbsp, SSELCR);
276 MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
277
d912fa92
EN		 278 w = MCBSP_READ(mcbsp, SSELCR);
279 MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
280
1743d14f
JN		 281 if (mcbsp->pdata->enable_st_clock)
282 mcbsp->pdata->enable_st_clock(mcbsp->id, 0);
d912fa92
EN		 283}
284
285static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
286{
287 u16 val, i;
d912fa92
EN		 288
289 val = MCBSP_ST_READ(mcbsp, SSELCR);
290
291 if (val & ST_COEFFWREN)
292 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
293
294 MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
295
296 for (i = 0; i < 128; i++)
297 MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
298
299 i = 0;
300
301 val = MCBSP_ST_READ(mcbsp, SSELCR);
302 while (!(val & ST_COEFFWRDONE) && (++i < 1000))
303 val = MCBSP_ST_READ(mcbsp, SSELCR);
304
305 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
306
307 if (i == 1000)
308 dev_err(mcbsp->dev, "McBSP FIR load error!\n");
309}
310
311static void omap_st_chgain(struct omap_mcbsp *mcbsp)
312{
313 u16 w;
314 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
d912fa92
EN		 315
316 w = MCBSP_ST_READ(mcbsp, SSELCR);
317
318 MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
319 ST_CH1GAIN(st_data->ch1gain));
320}
321
45656b44 322int omap_st_set_chgain(struct omap_mcbsp *mcbsp, int channel, s16 chgain)
d912fa92 323{
e2002ab3 324 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
d912fa92
EN		 325 int ret = 0;
326
d912fa92
EN		 327 if (!st_data)
328 return -ENOENT;
329
330 spin_lock_irq(&mcbsp->lock);
331 if (channel == 0)
332 st_data->ch0gain = chgain;
333 else if (channel == 1)
334 st_data->ch1gain = chgain;
335 else
336 ret = -EINVAL;
337
338 if (st_data->enabled)
339 omap_st_chgain(mcbsp);
340 spin_unlock_irq(&mcbsp->lock);
341
342 return ret;
343}
d912fa92 344
45656b44 345int omap_st_get_chgain(struct omap_mcbsp *mcbsp, int channel, s16 *chgain)
d912fa92 346{
e2002ab3 347 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
d912fa92
EN		 348 int ret = 0;
349
d912fa92
EN		 350 if (!st_data)
351 return -ENOENT;
352
353 spin_lock_irq(&mcbsp->lock);
354 if (channel == 0)
355 *chgain = st_data->ch0gain;
356 else if (channel == 1)
357 *chgain = st_data->ch1gain;
358 else
359 ret = -EINVAL;
360 spin_unlock_irq(&mcbsp->lock);
361
362 return ret;
363}
d912fa92
EN		 364
365static int omap_st_start(struct omap_mcbsp *mcbsp)
366{
367 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
368
58db1dcd 369 if (st_data->enabled && !st_data->running) {
d912fa92
EN		 370 omap_st_fir_write(mcbsp, st_data->taps);
371 omap_st_chgain(mcbsp);
372
373 if (!mcbsp->free) {
374 omap_st_on(mcbsp);
375 st_data->running = 1;
376 }
377 }
378
379 return 0;
380}
381
45656b44 382int omap_st_enable(struct omap_mcbsp *mcbsp)
d912fa92 383{
e2002ab3 384 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
d912fa92
EN		 385
386 if (!st_data)
387 return -ENODEV;
388
389 spin_lock_irq(&mcbsp->lock);
390 st_data->enabled = 1;
391 omap_st_start(mcbsp);
392 spin_unlock_irq(&mcbsp->lock);
393
394 return 0;
395}
d912fa92
EN		 396
397static int omap_st_stop(struct omap_mcbsp *mcbsp)
398{
399 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
400
58db1dcd 401 if (st_data->running) {
d912fa92
EN		 402 if (!mcbsp->free) {
403 omap_st_off(mcbsp);
404 st_data->running = 0;
405 }
406 }
407
408 return 0;
409}
410
45656b44 411int omap_st_disable(struct omap_mcbsp *mcbsp)
d912fa92 412{
e2002ab3 413 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
d912fa92
EN		 414 int ret = 0;
415
d912fa92
EN		 416 if (!st_data)
417 return -ENODEV;
418
419 spin_lock_irq(&mcbsp->lock);
420 omap_st_stop(mcbsp);
421 st_data->enabled = 0;
422 spin_unlock_irq(&mcbsp->lock);
423
424 return ret;
425}
d912fa92 426
45656b44 427int omap_st_is_enabled(struct omap_mcbsp *mcbsp)
d912fa92 428{
e2002ab3 429 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
d912fa92
EN		 430
431 if (!st_data)
432 return -ENODEV;
433
d912fa92
EN		 434 return st_data->enabled;
435}
d912fa92 436
7aa9ff56 437/*
451fd82d
PU		 438 * omap_mcbsp_set_rx_threshold configures the transmit threshold in words.
439 * The threshold parameter is 1 based, and it is converted (threshold - 1)
440 * for the THRSH2 register.
7aa9ff56 441 */
45656b44 442void omap_mcbsp_set_tx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
7aa9ff56 443{
7bba67ab
JN		 444 if (mcbsp->pdata->buffer_size == 0)
445 return;
7aa9ff56 446
451fd82d
PU		 447 if (threshold && threshold <= mcbsp->max_tx_thres)
448 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
7aa9ff56 449}
7aa9ff56
EV		 450
451/*
451fd82d
PU		 452 * omap_mcbsp_set_rx_threshold configures the receive threshold in words.
453 * The threshold parameter is 1 based, and it is converted (threshold - 1)
454 * for the THRSH1 register.
7aa9ff56 455 */
45656b44 456void omap_mcbsp_set_rx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
7aa9ff56 457{
7bba67ab
JN		 458 if (mcbsp->pdata->buffer_size == 0)
459 return;
7aa9ff56 460
451fd82d
PU		 461 if (threshold && threshold <= mcbsp->max_rx_thres)
462 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
7aa9ff56 463}
a1a56f5f 464
7dc976ed
PU		 465/*
466 * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
467 */
45656b44 468u16 omap_mcbsp_get_tx_delay(struct omap_mcbsp *mcbsp)
7dc976ed 469{
7dc976ed
PU		 470 u16 buffstat;
471
7bba67ab
JN		 472 if (mcbsp->pdata->buffer_size == 0)
473 return 0;
7dc976ed
PU		 474
475 /* Returns the number of free locations in the buffer */
476 buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
477
478 /* Number of slots are different in McBSP ports */
f10b8ad1 479 return mcbsp->pdata->buffer_size - buffstat;
7dc976ed 480}
7dc976ed
PU		 481
482/*
483 * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
484 * to reach the threshold value (when the DMA will be triggered to read it)
485 */
45656b44 486u16 omap_mcbsp_get_rx_delay(struct omap_mcbsp *mcbsp)
7dc976ed 487{
7dc976ed
PU		 488 u16 buffstat, threshold;
489
7bba67ab
JN		 490 if (mcbsp->pdata->buffer_size == 0)
491 return 0;
7dc976ed
PU		 492
493 /* Returns the number of used locations in the buffer */
494 buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
495 /* RX threshold */
496 threshold = MCBSP_READ(mcbsp, THRSH1);
497
498 /* Return the number of location till we reach the threshold limit */
499 if (threshold <= buffstat)
500 return 0;
501 else
502 return threshold - buffstat;
503}
7dc976ed 504
45656b44 505int omap_mcbsp_request(struct omap_mcbsp *mcbsp)
5e1c5ff4 506{
c8c99699 507 void *reg_cache;
5e1c5ff4
TL		 508 int err;
509
ac6747ca 510 reg_cache = kzalloc(mcbsp->reg_cache_size, GFP_KERNEL);
c8c99699
JK		 511 if (!reg_cache) {
512 return -ENOMEM;
513 }
514
b4b58f58
CS		 515 spin_lock(&mcbsp->lock);
516 if (!mcbsp->free) {
517 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
518 mcbsp->id);
c8c99699
JK		 519 err = -EBUSY;
520 goto err_kfree;
5e1c5ff4
TL		 521 }
522
6722a723 523 mcbsp->free = false;
c8c99699 524 mcbsp->reg_cache = reg_cache;
b4b58f58 525 spin_unlock(&mcbsp->lock);
5e1c5ff4 526
b820ce4e 527 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
45656b44 528 mcbsp->pdata->ops->request(mcbsp->id - 1);
b820ce4e 529
5a07055a
JN		 530 /*
531 * Make sure that transmitter, receiver and sample-rate generator are
532 * not running before activating IRQs.
533 */
8ea3200f
JK		 534 MCBSP_WRITE(mcbsp, SPCR1, 0);
535 MCBSP_WRITE(mcbsp, SPCR2, 0);
5a07055a 536
35d210fa
PU		 537 if (mcbsp->irq) {
538 err = request_irq(mcbsp->irq, omap_mcbsp_irq_handler, 0,
539 "McBSP", (void *)mcbsp);
540 if (err != 0) {
541 dev_err(mcbsp->dev, "Unable to request IRQ\n");
542 goto err_clk_disable;
543 }
544 } else {
545 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler, 0,
546 "McBSP TX", (void *)mcbsp);
547 if (err != 0) {
548 dev_err(mcbsp->dev, "Unable to request TX IRQ\n");
549 goto err_clk_disable;
550 }
bafe2721 551
35d210fa
PU		 552 err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler, 0,
553 "McBSP RX", (void *)mcbsp);
120db2cb 554 if (err != 0) {
35d210fa 555 dev_err(mcbsp->dev, "Unable to request RX IRQ\n");
bafe2721 556 goto err_free_irq;
120db2cb 557 }
5e1c5ff4
TL		 558 }
559
5e1c5ff4 560 return 0;
c8c99699 561err_free_irq:
1866b545 562 free_irq(mcbsp->tx_irq, (void *)mcbsp);
c8c99699 563err_clk_disable:
1866b545 564 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
45656b44 565 mcbsp->pdata->ops->free(mcbsp->id - 1);
1866b545 566
1a645884
JN		 567 /* Disable wakeup behavior */
568 if (mcbsp->pdata->has_wakeup)
569 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
1866b545 570
c8c99699 571 spin_lock(&mcbsp->lock);
6722a723 572 mcbsp->free = true;
c8c99699
JK		 573 mcbsp->reg_cache = NULL;
574err_kfree:
575 spin_unlock(&mcbsp->lock);
576 kfree(reg_cache);
1866b545
JK		 577
578 return err;
5e1c5ff4
TL		 579}
580
45656b44 581void omap_mcbsp_free(struct omap_mcbsp *mcbsp)
5e1c5ff4 582{
c8c99699 583 void *reg_cache;
b4b58f58 584
b4b58f58 585 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
45656b44 586 mcbsp->pdata->ops->free(mcbsp->id - 1);
bc5d0c89 587
1a645884
JN		 588 /* Disable wakeup behavior */
589 if (mcbsp->pdata->has_wakeup)
590 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
2122fdc6 591
35d210fa
PU		 592 /* Disable interrupt requests */
593 if (mcbsp->irq)
594 MCBSP_WRITE(mcbsp, IRQEN, 0);
595
596 if (mcbsp->irq) {
597 free_irq(mcbsp->irq, (void *)mcbsp);
598 } else {
bafe2721 599 free_irq(mcbsp->rx_irq, (void *)mcbsp);
35d210fa
PU		 600 free_irq(mcbsp->tx_irq, (void *)mcbsp);
601 }
5e1c5ff4 602
c8c99699 603 reg_cache = mcbsp->reg_cache;
5e1c5ff4 604
e386615c
PU		 605 /*
606 * Select CLKS source from internal source unconditionally before
607 * marking the McBSP port as free.
608 * If the external clock source via MCBSP_CLKS pin has been selected the
609 * system will refuse to enter idle if the CLKS pin source is not reset
610 * back to internal source.
611 */
612 if (!cpu_class_is_omap1())
613 omap2_mcbsp_set_clks_src(mcbsp, MCBSP_CLKS_PRCM_SRC);
614
c8c99699
JK		 615 spin_lock(&mcbsp->lock);
616 if (mcbsp->free)
617 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
618 else
6722a723 619 mcbsp->free = true;
c8c99699 620 mcbsp->reg_cache = NULL;
b4b58f58 621 spin_unlock(&mcbsp->lock);
c8c99699
JK		 622
623 if (reg_cache)
624 kfree(reg_cache);
5e1c5ff4
TL		 625}
626
627/*
c12abc01
JN		 628 * Here we start the McBSP, by enabling transmitter, receiver or both.
629 * If no transmitter or receiver is active prior calling, then sample-rate
630 * generator and frame sync are started.
5e1c5ff4 631 */
45656b44 632void omap_mcbsp_start(struct omap_mcbsp *mcbsp, int tx, int rx)
5e1c5ff4 633{
ce3f054b 634 int enable_srg = 0;
5e1c5ff4
TL		 635 u16 w;
636
f821eece 637 if (mcbsp->st_data)
d912fa92
EN		 638 omap_st_start(mcbsp);
639
ce3f054b
PU		 640 /* Only enable SRG, if McBSP is master */
641 w = MCBSP_READ_CACHE(mcbsp, PCR0);
642 if (w & (FSXM | FSRM | CLKXM | CLKRM))
643 enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
644 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
c12abc01 645
ce3f054b 646 if (enable_srg) {
c12abc01 647 /* Start the sample generator */
96fbd745 648 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 649 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
c12abc01 650 }
5e1c5ff4
TL		 651
652 /* Enable transmitter and receiver */
d09a2afc 653 tx &= 1;
96fbd745 654 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 655 MCBSP_WRITE(mcbsp, SPCR2, w | tx);
5e1c5ff4 656
d09a2afc 657 rx &= 1;
96fbd745 658 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
8ea3200f 659 MCBSP_WRITE(mcbsp, SPCR1, w | rx);
5e1c5ff4 660
44a6311c
EV		 661 /*
662 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
663 * REVISIT: 100us may give enough time for two CLKSRG, however
664 * due to some unknown PM related, clock gating etc. reason it
665 * is now at 500us.
666 */
667 udelay(500);
5e1c5ff4 668
ce3f054b 669 if (enable_srg) {
c12abc01 670 /* Start frame sync */
96fbd745 671 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 672 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
c12abc01 673 }
5e1c5ff4 674
88408230 675 if (mcbsp->pdata->has_ccr) {
d09a2afc 676 /* Release the transmitter and receiver */
96fbd745 677 w = MCBSP_READ_CACHE(mcbsp, XCCR);
d09a2afc 678 w &= ~(tx ? XDISABLE : 0);
8ea3200f 679 MCBSP_WRITE(mcbsp, XCCR, w);
96fbd745 680 w = MCBSP_READ_CACHE(mcbsp, RCCR);
d09a2afc 681 w &= ~(rx ? RDISABLE : 0);
8ea3200f 682 MCBSP_WRITE(mcbsp, RCCR, w);
d09a2afc
JN		 683 }
684
5e1c5ff4 685 /* Dump McBSP Regs */
45656b44 686 omap_mcbsp_dump_reg(mcbsp);
5e1c5ff4
TL		 687}
688
45656b44 689void omap_mcbsp_stop(struct omap_mcbsp *mcbsp, int tx, int rx)
5e1c5ff4 690{
c12abc01 691 int idle;
5e1c5ff4
TL		 692 u16 w;
693
fb78d808 694 /* Reset transmitter */
d09a2afc 695 tx &= 1;
88408230 696 if (mcbsp->pdata->has_ccr) {
96fbd745 697 w = MCBSP_READ_CACHE(mcbsp, XCCR);
d09a2afc 698 w |= (tx ? XDISABLE : 0);
8ea3200f 699 MCBSP_WRITE(mcbsp, XCCR, w);
d09a2afc 700 }
96fbd745 701 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 702 MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
5e1c5ff4
TL		 703
704 /* Reset receiver */
d09a2afc 705 rx &= 1;
88408230 706 if (mcbsp->pdata->has_ccr) {
96fbd745 707 w = MCBSP_READ_CACHE(mcbsp, RCCR);
a93d4ed2 708 w |= (rx ? RDISABLE : 0);
8ea3200f 709 MCBSP_WRITE(mcbsp, RCCR, w);
d09a2afc 710 }
96fbd745 711 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
8ea3200f 712 MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
5e1c5ff4 713
96fbd745
JK		 714 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
715 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
c12abc01
JN		 716
717 if (idle) {
718 /* Reset the sample rate generator */
96fbd745 719 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 720 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
c12abc01 721 }
d912fa92 722
f821eece 723 if (mcbsp->st_data)
d912fa92 724 omap_st_stop(mcbsp);
5e1c5ff4 725}
5e1c5ff4 726
45656b44 727int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id)
69d042d1 728{
09d28d2c
JN		 729 const char *src;
730
09d28d2c
JN		 731 if (fck_src_id == MCBSP_CLKS_PAD_SRC)
732 src = "clks_ext";
733 else if (fck_src_id == MCBSP_CLKS_PRCM_SRC)
734 src = "clks_fclk";
735 else
736 return -EINVAL;
737
738 if (mcbsp->pdata->set_clk_src)
739 return mcbsp->pdata->set_clk_src(mcbsp->dev, mcbsp->fclk, src);
740 else
741 return -EINVAL;
69d042d1
PW		 742}
743
cd1f08c7 744int omap_mcbsp_6pin_src_mux(struct omap_mcbsp *mcbsp, u8 mux)
69d042d1 745{
cd1f08c7 746 const char *signal, *src;
5788c62e 747
d0db84e7 748 if (!mcbsp->pdata->mux_signal)
5788c62e 749 return -EINVAL;
45656b44 750
cd1f08c7
PU		 751 switch (mux) {
752 case CLKR_SRC_CLKR:
753 signal = "clkr";
7bc0c4ba 754 src = "clkr";
cd1f08c7
PU		 755 break;
756 case CLKR_SRC_CLKX:
757 signal = "clkr";
7bc0c4ba 758 src = "clkx";
cd1f08c7
PU		 759 break;
760 case FSR_SRC_FSR:
761 signal = "fsr";
7bc0c4ba 762 src = "fsr";
cd1f08c7
PU		 763 break;
764 case FSR_SRC_FSX:
765 signal = "fsr";
7bc0c4ba 766 src = "fsx";
cd1f08c7
PU		 767 break;
768 default:
769 return -EINVAL;
770 }
7bc0c4ba 771
5788c62e 772 return mcbsp->pdata->mux_signal(mcbsp->dev, signal, src);
69d042d1 773}
69d042d1 774
a1a56f5f
EV		 775#define max_thres(m) (mcbsp->pdata->buffer_size)
776#define valid_threshold(m, val) ((val) <= max_thres(m))
777#define THRESHOLD_PROP_BUILDER(prop) \
778static ssize_t prop##_show(struct device *dev, \
779 struct device_attribute *attr, char *buf) \
780{ \
781 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
782 \
783 return sprintf(buf, "%u\n", mcbsp->prop); \
784} \
785 \
786static ssize_t prop##_store(struct device *dev, \
787 struct device_attribute *attr, \
788 const char *buf, size_t size) \
789{ \
790 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
791 unsigned long val; \
792 int status; \
793 \
794 status = strict_strtoul(buf, 0, &val); \
795 if (status) \
796 return status; \
797 \
798 if (!valid_threshold(mcbsp, val)) \
799 return -EDOM; \
800 \
801 mcbsp->prop = val; \
802 return size; \
803} \
804 \
805static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
806
807THRESHOLD_PROP_BUILDER(max_tx_thres);
808THRESHOLD_PROP_BUILDER(max_rx_thres);
809
9b300509 810static const char *dma_op_modes[] = {
09fa37ac 811 "element", "threshold",
9b300509
JN		 812};
813
98cb20e8
PU		 814static ssize_t dma_op_mode_show(struct device *dev,
815 struct device_attribute *attr, char *buf)
816{
817 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
9b300509
JN		 818 int dma_op_mode, i = 0;
819 ssize_t len = 0;
820 const char * const *s;
98cb20e8 821
98cb20e8 822 dma_op_mode = mcbsp->dma_op_mode;
98cb20e8 823
9b300509
JN		 824 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
825 if (dma_op_mode == i)
826 len += sprintf(buf + len, "[%s] ", *s);
827 else
828 len += sprintf(buf + len, "%s ", *s);
829 }
830 len += sprintf(buf + len, "\n");
831
832 return len;
98cb20e8
PU		 833}
834
835static ssize_t dma_op_mode_store(struct device *dev,
836 struct device_attribute *attr,
837 const char *buf, size_t size)
838{
839 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
9b300509
JN		 840 const char * const *s;
841 int i = 0;
98cb20e8 842
9b300509
JN		 843 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
844 if (sysfs_streq(buf, *s))
845 break;
98cb20e8 846
9b300509
JN		 847 if (i == ARRAY_SIZE(dma_op_modes))
848 return -EINVAL;
98cb20e8 849
9b300509 850 spin_lock_irq(&mcbsp->lock);
98cb20e8
PU		 851 if (!mcbsp->free) {
852 size = -EBUSY;
853 goto unlock;
854 }
9b300509 855 mcbsp->dma_op_mode = i;
98cb20e8
PU		 856
857unlock:
858 spin_unlock_irq(&mcbsp->lock);
859
860 return size;
861}
862
863static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
864
7bba67ab
JN		 865static const struct attribute *additional_attrs[] = {
866 &dev_attr_max_tx_thres.attr,
867 &dev_attr_max_rx_thres.attr,
868 &dev_attr_dma_op_mode.attr,
869 NULL,
870};
871
872static const struct attribute_group additional_attr_group = {
873 .attrs = (struct attribute **)additional_attrs,
874};
875
d912fa92
EN		 876static ssize_t st_taps_show(struct device *dev,
877 struct device_attribute *attr, char *buf)
878{
879 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
880 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
881 ssize_t status = 0;
882 int i;
883
884 spin_lock_irq(&mcbsp->lock);
885 for (i = 0; i < st_data->nr_taps; i++)
886 status += sprintf(&buf[status], (i ? ", %d" : "%d"),
887 st_data->taps[i]);
888 if (i)
889 status += sprintf(&buf[status], "\n");
890 spin_unlock_irq(&mcbsp->lock);
891
892 return status;
893}
894
895static ssize_t st_taps_store(struct device *dev,
896 struct device_attribute *attr,
897 const char *buf, size_t size)
898{
899 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
900 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
901 int val, tmp, status, i = 0;
902
903 spin_lock_irq(&mcbsp->lock);
904 memset(st_data->taps, 0, sizeof(st_data->taps));
905 st_data->nr_taps = 0;
906
907 do {
908 status = sscanf(buf, "%d%n", &val, &tmp);
909 if (status < 0 || status == 0) {
910 size = -EINVAL;
911 goto out;
912 }
913 if (val < -32768 || val > 32767) {
914 size = -EINVAL;
915 goto out;
916 }
917 st_data->taps[i++] = val;
918 buf += tmp;
919 if (*buf != ',')
920 break;
921 buf++;
922 } while (1);
923
924 st_data->nr_taps = i;
925
926out:
927 spin_unlock_irq(&mcbsp->lock);
928
929 return size;
930}
931
932static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
933
d912fa92
EN		 934static const struct attribute *sidetone_attrs[] = {
935 &dev_attr_st_taps.attr,
936 NULL,
937};
938
939static const struct attribute_group sidetone_attr_group = {
940 .attrs = (struct attribute **)sidetone_attrs,
941};
942
f821eece
JN		 943static int __devinit omap_st_add(struct omap_mcbsp *mcbsp,
944 struct resource *res)
d912fa92 945{
d912fa92
EN		 946 struct omap_mcbsp_st_data *st_data;
947 int err;
948
2ee65950
PU		 949 st_data = devm_kzalloc(mcbsp->dev, sizeof(*mcbsp->st_data), GFP_KERNEL);
950 if (!st_data)
951 return -ENOMEM;
d912fa92 952
2ee65950
PU		 953 st_data->io_base_st = devm_ioremap(mcbsp->dev, res->start,
954 resource_size(res));
955 if (!st_data->io_base_st)
956 return -ENOMEM;
d912fa92
EN		 957
958 err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
959 if (err)
2ee65950 960 return err;
d912fa92
EN		 961
962 mcbsp->st_data = st_data;
963 return 0;
a1a56f5f 964}
a1a56f5f 965
5e1c5ff4
TL		 966/*
967 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
968 * 730 has only 2 McBSP, and both of them are MPU peripherals.
969 */
2ee65950 970int __devinit omap_mcbsp_init(struct platform_device *pdev)
bc5d0c89 971{
2ee65950 972 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
3cf32bba 973 struct resource *res;
bc5d0c89 974 int ret = 0;
5e1c5ff4 975
b4b58f58 976 spin_lock_init(&mcbsp->lock);
6722a723 977 mcbsp->free = true;
bc5d0c89 978
3cf32bba
KVA		 979 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
980 if (!res) {
981 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
982 if (!res) {
2ee65950
PU		 983 dev_err(mcbsp->dev, "invalid memory resource\n");
984 return -ENOMEM;
3cf32bba
KVA		 985 }
986 }
2ee65950
PU		 987 if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res),
988 dev_name(&pdev->dev))) {
989 dev_err(mcbsp->dev, "memory region already claimed\n");
990 return -ENODEV;
991 }
992
3cf32bba 993 mcbsp->phys_base = res->start;
ac6747ca 994 mcbsp->reg_cache_size = resource_size(res);
2ee65950
PU		 995 mcbsp->io_base = devm_ioremap(&pdev->dev, res->start,
996 resource_size(res));
997 if (!mcbsp->io_base)
998 return -ENOMEM;
d592dd1a 999
3cf32bba
KVA		 1000 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
1001 if (!res)
1002 mcbsp->phys_dma_base = mcbsp->phys_base;
1003 else
1004 mcbsp->phys_dma_base = res->start;
1005
35d210fa
PU		 1006 /*
1007 * OMAP1, 2 uses two interrupt lines: TX, RX
1008 * OMAP2430, OMAP3 SoC have combined IRQ line as well.
1009 * OMAP4 and newer SoC only have the combined IRQ line.
1010 * Use the combined IRQ if available since it gives better debugging
1011 * possibilities.
1012 */
1013 mcbsp->irq = platform_get_irq_byname(pdev, "common");
1014 if (mcbsp->irq == -ENXIO) {
1015 mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
1016
1017 if (mcbsp->tx_irq == -ENXIO) {
1018 mcbsp->irq = platform_get_irq(pdev, 0);
1019 mcbsp->tx_irq = 0;
1020 } else {
1021 mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
1022 mcbsp->irq = 0;
1023 }
73c9522e 1024 }
cb7e9ded 1025
3cf32bba
KVA		 1026 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1027 if (!res) {
2ee65950
PU		 1028 dev_err(&pdev->dev, "invalid rx DMA channel\n");
1029 return -ENODEV;
3cf32bba 1030 }
b8fb4907
PU		 1031 /* RX DMA request number, and port address configuration */
1032 mcbsp->dma_data[1].name = "Audio Capture";
1033 mcbsp->dma_data[1].dma_req = res->start;
1034 mcbsp->dma_data[1].port_addr = omap_mcbsp_dma_reg_params(mcbsp, 1);
3cf32bba
KVA		 1035
1036 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1037 if (!res) {
2ee65950
PU		 1038 dev_err(&pdev->dev, "invalid tx DMA channel\n");
1039 return -ENODEV;
3cf32bba 1040 }
b8fb4907
PU		 1041 /* TX DMA request number, and port address configuration */
1042 mcbsp->dma_data[0].name = "Audio Playback";
1043 mcbsp->dma_data[0].dma_req = res->start;
1044 mcbsp->dma_data[0].port_addr = omap_mcbsp_dma_reg_params(mcbsp, 0);
bc5d0c89 1045
b820ce4e
RK		 1046 mcbsp->fclk = clk_get(&pdev->dev, "fck");
1047 if (IS_ERR(mcbsp->fclk)) {
1048 ret = PTR_ERR(mcbsp->fclk);
2ee65950
PU		 1049 dev_err(mcbsp->dev, "unable to get fck: %d\n", ret);
1050 return ret;
bc5d0c89
EV		 1051 }
1052
7bba67ab
JN		 1053 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1054 if (mcbsp->pdata->buffer_size) {
1055 /*
1056 * Initially configure the maximum thresholds to a safe value.
1057 * The McBSP FIFO usage with these values should not go under
1058 * 16 locations.
1059 * If the whole FIFO without safety buffer is used, than there
1060 * is a possibility that the DMA will be not able to push the
1061 * new data on time, causing channel shifts in runtime.
1062 */
1063 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
1064 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
1065
1066 ret = sysfs_create_group(&mcbsp->dev->kobj,
1067 &additional_attr_group);
1068 if (ret) {
1069 dev_err(mcbsp->dev,
1070 "Unable to create additional controls\n");
1071 goto err_thres;
1072 }
1073 } else {
1074 mcbsp->max_tx_thres = -EINVAL;
1075 mcbsp->max_rx_thres = -EINVAL;
1076 }
1077
f821eece
JN		 1078 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
1079 if (res) {
1080 ret = omap_st_add(mcbsp, res);
1081 if (ret) {
1082 dev_err(mcbsp->dev,
1083 "Unable to create sidetone controls\n");
1084 goto err_st;
1085 }
1086 }
a1a56f5f 1087
d592dd1a 1088 return 0;
bc5d0c89 1089
f821eece
JN		 1090err_st:
1091 if (mcbsp->pdata->buffer_size)
2ee65950 1092 sysfs_remove_group(&mcbsp->dev->kobj, &additional_attr_group);
7bba67ab
JN		 1093err_thres:
1094 clk_put(mcbsp->fclk);
bc5d0c89
EV		 1095 return ret;
1096}
120db2cb 1097
2ee65950 1098void __devexit omap_mcbsp_sysfs_remove(struct omap_mcbsp *mcbsp)
5e1c5ff4 1099{
2ee65950
PU		 1100 if (mcbsp->pdata->buffer_size)
1101 sysfs_remove_group(&mcbsp->dev->kobj, &additional_attr_group);
5e1c5ff4 1102
2ee65950
PU		 1103 if (mcbsp->st_data)
1104 sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
5e1c5ff4 1105}
Linux kernel - Deliverables
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