projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 61c66c60 | 1 | /* |
| fd88edd2 BD |
2 | * Copyright (c) 2006 Simtec Electronics <linux@simtec.co.uk> |
| 3 | * http://www.simtec.co.uk/products/SWLINUX/ | |
| 4 | * | |
| 5 | * This program is free software; you can redistribute it and/or modify | |
| 6 | * it under the terms of the GNU General Public License version 2 as | |
| 7 | * published by the Free Software Foundation. | |
| 8 | * | |
| 9 | * S3C2440 AC97 Controller | |
| 10 | */ | |
| 11 | ||
| 61c66c60 SK |
12 | #ifndef __SAMSUNG_REGS_AC97_H__ |
| 13 | #define __SAMSUNG_REGS_AC97_H__ | |
| fd88edd2 | 14 | |
| ef085747 GG |
15 | #define S3C_AC97_GLBCTRL (0x00) |
| 16 | ||
| 17 | #define S3C_AC97_GLBCTRL_CODECREADYIE (1<<22) | |
| 18 | #define S3C_AC97_GLBCTRL_PCMOUTURIE (1<<21) | |
| 19 | #define S3C_AC97_GLBCTRL_PCMINORIE (1<<20) | |
| 20 | #define S3C_AC97_GLBCTRL_MICINORIE (1<<19) | |
| 21 | #define S3C_AC97_GLBCTRL_PCMOUTTIE (1<<18) | |
| 22 | #define S3C_AC97_GLBCTRL_PCMINTIE (1<<17) | |
| 23 | #define S3C_AC97_GLBCTRL_MICINTIE (1<<16) | |
| 24 | #define S3C_AC97_GLBCTRL_PCMOUTTM_OFF (0<<12) | |
| 25 | #define S3C_AC97_GLBCTRL_PCMOUTTM_PIO (1<<12) | |
| 26 | #define S3C_AC97_GLBCTRL_PCMOUTTM_DMA (2<<12) | |
| 27 | #define S3C_AC97_GLBCTRL_PCMOUTTM_MASK (3<<12) | |
| 28 | #define S3C_AC97_GLBCTRL_PCMINTM_OFF (0<<10) | |
| 29 | #define S3C_AC97_GLBCTRL_PCMINTM_PIO (1<<10) | |
| 30 | #define S3C_AC97_GLBCTRL_PCMINTM_DMA (2<<10) | |
| 31 | #define S3C_AC97_GLBCTRL_PCMINTM_MASK (3<<10) | |
| 32 | #define S3C_AC97_GLBCTRL_MICINTM_OFF (0<<8) | |
| 33 | #define S3C_AC97_GLBCTRL_MICINTM_PIO (1<<8) | |
| 34 | #define S3C_AC97_GLBCTRL_MICINTM_DMA (2<<8) | |
| 35 | #define S3C_AC97_GLBCTRL_MICINTM_MASK (3<<8) | |
| 36 | #define S3C_AC97_GLBCTRL_TRANSFERDATAENABLE (1<<3) | |
| 37 | #define S3C_AC97_GLBCTRL_ACLINKON (1<<2) | |
| 38 | #define S3C_AC97_GLBCTRL_WARMRESET (1<<1) | |
| 39 | #define S3C_AC97_GLBCTRL_COLDRESET (1<<0) | |
| 40 | ||
| 41 | #define S3C_AC97_GLBSTAT (0x04) | |
| 42 | ||
| 43 | #define S3C_AC97_GLBSTAT_CODECREADY (1<<22) | |
| 44 | #define S3C_AC97_GLBSTAT_PCMOUTUR (1<<21) | |
| 45 | #define S3C_AC97_GLBSTAT_PCMINORI (1<<20) | |
| 46 | #define S3C_AC97_GLBSTAT_MICINORI (1<<19) | |
| 47 | #define S3C_AC97_GLBSTAT_PCMOUTTI (1<<18) | |
| 48 | #define S3C_AC97_GLBSTAT_PCMINTI (1<<17) | |
| 49 | #define S3C_AC97_GLBSTAT_MICINTI (1<<16) | |
| 50 | #define S3C_AC97_GLBSTAT_MAINSTATE_IDLE (0<<0) | |
| 51 | #define S3C_AC97_GLBSTAT_MAINSTATE_INIT (1<<0) | |
| 52 | #define S3C_AC97_GLBSTAT_MAINSTATE_READY (2<<0) | |
| 53 | #define S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE (3<<0) | |
| 54 | #define S3C_AC97_GLBSTAT_MAINSTATE_LP (4<<0) | |
| 55 | #define S3C_AC97_GLBSTAT_MAINSTATE_WARM (5<<0) | |
| 56 | ||
| 57 | #define S3C_AC97_CODEC_CMD (0x08) | |
| 58 | ||
| 59 | #define S3C_AC97_CODEC_CMD_READ (1<<23) | |
| 60 | ||
| 61 | #define S3C_AC97_STAT (0x0c) | |
| 62 | #define S3C_AC97_PCM_ADDR (0x10) | |
| 63 | #define S3C_AC97_PCM_DATA (0x18) | |
| 64 | #define S3C_AC97_MIC_DATA (0x1C) | |
| fd88edd2 | 65 | |
| 61c66c60 | 66 | #endif /* __SAMSUNG_REGS_AC97_H__ */ |