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a4d7d550 KM |
1 | /* |
2 | * Fifo-attached Serial Interface (FSI) support for SH7724 | |
3 | * | |
4 | * Copyright (C) 2009 Renesas Solutions Corp. | |
5 | * Kuninori Morimoto <morimoto.kuninori@renesas.com> | |
6 | * | |
7 | * Based on ssi.c | |
8 | * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
a4d7d550 | 15 | #include <linux/delay.h> |
7da9ced6 | 16 | #include <linux/dma-mapping.h> |
785d1c45 | 17 | #include <linux/pm_runtime.h> |
a4d7d550 | 18 | #include <linux/io.h> |
9e7b6d60 KM |
19 | #include <linux/of.h> |
20 | #include <linux/of_device.h> | |
7da9ced6 KM |
21 | #include <linux/scatterlist.h> |
22 | #include <linux/sh_dma.h> | |
5a0e3ad6 | 23 | #include <linux/slab.h> |
da155d5b | 24 | #include <linux/module.h> |
57451e43 | 25 | #include <linux/workqueue.h> |
a4d7d550 | 26 | #include <sound/soc.h> |
ab6f6d85 | 27 | #include <sound/pcm_params.h> |
a4d7d550 | 28 | #include <sound/sh_fsi.h> |
a4d7d550 | 29 | |
e8c8b631 KM |
30 | /* PortA/PortB register */ |
31 | #define REG_DO_FMT 0x0000 | |
32 | #define REG_DOFF_CTL 0x0004 | |
33 | #define REG_DOFF_ST 0x0008 | |
34 | #define REG_DI_FMT 0x000C | |
35 | #define REG_DIFF_CTL 0x0010 | |
36 | #define REG_DIFF_ST 0x0014 | |
37 | #define REG_CKG1 0x0018 | |
38 | #define REG_CKG2 0x001C | |
39 | #define REG_DIDT 0x0020 | |
40 | #define REG_DODT 0x0024 | |
41 | #define REG_MUTE_ST 0x0028 | |
65ff03f4 | 42 | #define REG_OUT_DMAC 0x002C |
e8c8b631 | 43 | #define REG_OUT_SEL 0x0030 |
65ff03f4 | 44 | #define REG_IN_DMAC 0x0038 |
cc780d38 | 45 | |
43fa95ca KM |
46 | /* master register */ |
47 | #define MST_CLK_RST 0x0210 | |
48 | #define MST_SOFT_RST 0x0214 | |
49 | #define MST_FIFO_SZ 0x0218 | |
50 | ||
51 | /* core register (depend on FSI version) */ | |
3bc28070 KM |
52 | #define A_MST_CTLR 0x0180 |
53 | #define B_MST_CTLR 0x01A0 | |
cc780d38 KM |
54 | #define CPU_INT_ST 0x01F4 |
55 | #define CPU_IEMSK 0x01F8 | |
56 | #define CPU_IMSK 0x01FC | |
a4d7d550 KM |
57 | #define INT_ST 0x0200 |
58 | #define IEMSK 0x0204 | |
59 | #define IMSK 0x0208 | |
a4d7d550 KM |
60 | |
61 | /* DO_FMT */ | |
62 | /* DI_FMT */ | |
7da9ced6 | 63 | #define CR_BWS_MASK (0x3 << 20) /* FSI2 */ |
f7d711e3 KM |
64 | #define CR_BWS_24 (0x0 << 20) /* FSI2 */ |
65 | #define CR_BWS_16 (0x1 << 20) /* FSI2 */ | |
66 | #define CR_BWS_20 (0x2 << 20) /* FSI2 */ | |
67 | ||
68 | #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */ | |
69 | #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */ | |
70 | #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */ | |
71 | ||
a7ffb52b KM |
72 | #define CR_MONO (0x0 << 4) |
73 | #define CR_MONO_D (0x1 << 4) | |
74 | #define CR_PCM (0x2 << 4) | |
75 | #define CR_I2S (0x3 << 4) | |
76 | #define CR_TDM (0x4 << 4) | |
77 | #define CR_TDM_D (0x5 << 4) | |
a4d7d550 | 78 | |
7da9ced6 KM |
79 | /* OUT_DMAC */ |
80 | /* IN_DMAC */ | |
81 | #define VDMD_MASK (0x3 << 4) | |
82 | #define VDMD_FRONT (0x0 << 4) /* Package in front */ | |
83 | #define VDMD_BACK (0x1 << 4) /* Package in back */ | |
84 | #define VDMD_STREAM (0x2 << 4) /* Stream mode(16bit * 2) */ | |
85 | ||
86 | #define DMA_ON (0x1 << 0) | |
87 | ||
a4d7d550 KM |
88 | /* DOFF_CTL */ |
89 | /* DIFF_CTL */ | |
90 | #define IRQ_HALF 0x00100000 | |
91 | #define FIFO_CLR 0x00000001 | |
92 | ||
93 | /* DOFF_ST */ | |
94 | #define ERR_OVER 0x00000010 | |
95 | #define ERR_UNDER 0x00000001 | |
59c3b003 | 96 | #define ST_ERR (ERR_OVER | ERR_UNDER) |
a4d7d550 | 97 | |
ccad7b44 KM |
98 | /* CKG1 */ |
99 | #define ACKMD_MASK 0x00007000 | |
100 | #define BPFMD_MASK 0x00000700 | |
4d805f7b KM |
101 | #define DIMD (1 << 4) |
102 | #define DOMD (1 << 0) | |
ccad7b44 | 103 | |
3bc28070 KM |
104 | /* A/B MST_CTLR */ |
105 | #define BP (1 << 4) /* Fix the signal of Biphase output */ | |
106 | #define SE (1 << 0) /* Fix the master clock */ | |
107 | ||
a4d7d550 | 108 | /* CLK_RST */ |
1f5e2a31 KM |
109 | #define CRB (1 << 4) |
110 | #define CRA (1 << 0) | |
a4d7d550 | 111 | |
cf6edd00 KM |
112 | /* IO SHIFT / MACRO */ |
113 | #define BI_SHIFT 12 | |
114 | #define BO_SHIFT 8 | |
115 | #define AI_SHIFT 4 | |
116 | #define AO_SHIFT 0 | |
117 | #define AB_IO(param, shift) (param << shift) | |
a4d7d550 | 118 | |
feb58cff KM |
119 | /* SOFT_RST */ |
120 | #define PBSR (1 << 12) /* Port B Software Reset */ | |
121 | #define PASR (1 << 8) /* Port A Software Reset */ | |
122 | #define IR (1 << 4) /* Interrupt Reset */ | |
123 | #define FSISR (1 << 0) /* Software Reset */ | |
124 | ||
f7d711e3 KM |
125 | /* OUT_SEL (FSI2) */ |
126 | #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */ | |
127 | /* 1: Biphase and serial */ | |
128 | ||
4a942b45 | 129 | /* FIFO_SZ */ |
cf6edd00 | 130 | #define FIFO_SZ_MASK 0x7 |
4a942b45 | 131 | |
a4d7d550 KM |
132 | #define FSI_RATES SNDRV_PCM_RATE_8000_96000 |
133 | ||
134 | #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE) | |
135 | ||
766812e6 KM |
136 | /* |
137 | * bus options | |
138 | * | |
139 | * 0x000000BA | |
140 | * | |
141 | * A : sample widtht 16bit setting | |
142 | * B : sample widtht 24bit setting | |
143 | */ | |
144 | ||
145 | #define SHIFT_16DATA 0 | |
146 | #define SHIFT_24DATA 4 | |
147 | ||
148 | #define PACKAGE_24BITBUS_BACK 0 | |
149 | #define PACKAGE_24BITBUS_FRONT 1 | |
150 | #define PACKAGE_16BITBUS_STREAM 2 | |
151 | ||
152 | #define BUSOP_SET(s, a) ((a) << SHIFT_ ## s ## DATA) | |
153 | #define BUSOP_GET(s, a) (((a) >> SHIFT_ ## s ## DATA) & 0xF) | |
154 | ||
5bfb9ad0 KM |
155 | /* |
156 | * FSI driver use below type name for variable | |
157 | * | |
5bfb9ad0 | 158 | * xxx_num : number of data |
2e651baf KM |
159 | * xxx_pos : position of data |
160 | * xxx_capa : capacity of data | |
161 | */ | |
162 | ||
163 | /* | |
164 | * period/frame/sample image | |
165 | * | |
166 | * ex) PCM (2ch) | |
167 | * | |
168 | * period pos period pos | |
169 | * [n] [n + 1] | |
170 | * |<-------------------- period--------------------->| | |
171 | * ==|============================================ ... =|== | |
172 | * | | | |
173 | * ||<----- frame ----->|<------ frame ----->| ... | | |
174 | * |+--------------------+--------------------+- ... | | |
175 | * ||[ sample ][ sample ]|[ sample ][ sample ]| ... | | |
176 | * |+--------------------+--------------------+- ... | | |
177 | * ==|============================================ ... =|== | |
178 | */ | |
179 | ||
180 | /* | |
181 | * FSI FIFO image | |
182 | * | |
183 | * | | | |
184 | * | | | |
185 | * | [ sample ] | | |
186 | * | [ sample ] | | |
187 | * | [ sample ] | | |
188 | * | [ sample ] | | |
189 | * --> go to codecs | |
5bfb9ad0 KM |
190 | */ |
191 | ||
ab6f6d85 KM |
192 | /* |
193 | * FSI clock | |
194 | * | |
195 | * FSIxCLK [CPG] (ick) -------> | | |
196 | * |-> FSI_DIV (div)-> FSI2 | |
197 | * FSIxCK [external] (xck) ---> | | |
198 | */ | |
199 | ||
c8fe2574 KM |
200 | /* |
201 | * struct | |
202 | */ | |
a4d7d550 | 203 | |
5e97313a | 204 | struct fsi_stream_handler; |
93193c2b | 205 | struct fsi_stream { |
a4d7d550 | 206 | |
5e97313a KM |
207 | /* |
208 | * these are initialized by fsi_stream_init() | |
209 | */ | |
210 | struct snd_pcm_substream *substream; | |
2e651baf KM |
211 | int fifo_sample_capa; /* sample capacity of FSI FIFO */ |
212 | int buff_sample_capa; /* sample capacity of ALSA buffer */ | |
213 | int buff_sample_pos; /* sample position of ALSA buffer */ | |
214 | int period_samples; /* sample number / 1 period */ | |
215 | int period_pos; /* current period position */ | |
c1e6f10e | 216 | int sample_width; /* sample width */ |
1ec9bc35 KM |
217 | int uerr_num; |
218 | int oerr_num; | |
5e97313a | 219 | |
766812e6 KM |
220 | /* |
221 | * bus options | |
222 | */ | |
223 | u32 bus_option; | |
224 | ||
5e97313a KM |
225 | /* |
226 | * thse are initialized by fsi_handler_init() | |
227 | */ | |
228 | struct fsi_stream_handler *handler; | |
229 | struct fsi_priv *priv; | |
7da9ced6 KM |
230 | |
231 | /* | |
232 | * these are for DMAEngine | |
233 | */ | |
234 | struct dma_chan *chan; | |
235 | struct sh_dmae_slave slave; /* see fsi_handler_init() */ | |
57451e43 | 236 | struct work_struct work; |
7da9ced6 | 237 | dma_addr_t dma; |
53110a25 KM |
238 | int loop_cnt; |
239 | int additional_pos; | |
93193c2b KM |
240 | }; |
241 | ||
ab6f6d85 KM |
242 | struct fsi_clk { |
243 | /* see [FSI clock] */ | |
244 | struct clk *own; | |
245 | struct clk *xck; | |
246 | struct clk *ick; | |
247 | struct clk *div; | |
248 | int (*set_rate)(struct device *dev, | |
6cbdbffb | 249 | struct fsi_priv *fsi); |
ab6f6d85 KM |
250 | |
251 | unsigned long rate; | |
252 | unsigned int count; | |
253 | }; | |
254 | ||
93193c2b KM |
255 | struct fsi_priv { |
256 | void __iomem *base; | |
257 | struct fsi_master *master; | |
258 | ||
259 | struct fsi_stream playback; | |
260 | struct fsi_stream capture; | |
3bc28070 | 261 | |
ab6f6d85 KM |
262 | struct fsi_clk clock; |
263 | ||
9c59dd34 | 264 | u32 fmt; |
9478e0b6 | 265 | |
6a9ebad8 KM |
266 | int chan_num:16; |
267 | int clk_master:1; | |
ab6340c4 | 268 | int clk_cpg:1; |
9478e0b6 | 269 | int spdif:1; |
2522acd2 | 270 | int enable_stream:1; |
3449f5fa KM |
271 | int bit_clk_inv:1; |
272 | int lr_clk_inv:1; | |
a4d7d550 KM |
273 | }; |
274 | ||
5e97313a | 275 | struct fsi_stream_handler { |
83344027 KM |
276 | int (*init)(struct fsi_priv *fsi, struct fsi_stream *io); |
277 | int (*quit)(struct fsi_priv *fsi, struct fsi_stream *io); | |
b1226dc5 | 278 | int (*probe)(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev); |
5e97313a KM |
279 | int (*transfer)(struct fsi_priv *fsi, struct fsi_stream *io); |
280 | int (*remove)(struct fsi_priv *fsi, struct fsi_stream *io); | |
c375b2d7 | 281 | int (*start_stop)(struct fsi_priv *fsi, struct fsi_stream *io, |
180346ed | 282 | int enable); |
5e97313a KM |
283 | }; |
284 | #define fsi_stream_handler_call(io, func, args...) \ | |
285 | (!(io) ? -ENODEV : \ | |
286 | !((io)->handler->func) ? 0 : \ | |
287 | (io)->handler->func(args)) | |
288 | ||
73b92c1f KM |
289 | struct fsi_core { |
290 | int ver; | |
291 | ||
cc780d38 KM |
292 | u32 int_st; |
293 | u32 iemsk; | |
294 | u32 imsk; | |
2b0e7302 KM |
295 | u32 a_mclk; |
296 | u32 b_mclk; | |
cc780d38 KM |
297 | }; |
298 | ||
a4d7d550 KM |
299 | struct fsi_master { |
300 | void __iomem *base; | |
a4d7d550 KM |
301 | struct fsi_priv fsia; |
302 | struct fsi_priv fsib; | |
9e7b6d60 | 303 | const struct fsi_core *core; |
8fc176d5 | 304 | spinlock_t lock; |
a4d7d550 KM |
305 | }; |
306 | ||
7b1b3331 KM |
307 | static int fsi_stream_is_play(struct fsi_priv *fsi, struct fsi_stream *io); |
308 | ||
c8fe2574 KM |
309 | /* |
310 | * basic read write function | |
311 | */ | |
a4d7d550 | 312 | |
ca7aceef | 313 | static void __fsi_reg_write(u32 __iomem *reg, u32 data) |
a4d7d550 KM |
314 | { |
315 | /* valid data area is 24bit */ | |
316 | data &= 0x00ffffff; | |
317 | ||
0f69d978 | 318 | __raw_writel(data, reg); |
a4d7d550 KM |
319 | } |
320 | ||
ca7aceef | 321 | static u32 __fsi_reg_read(u32 __iomem *reg) |
a4d7d550 | 322 | { |
0f69d978 | 323 | return __raw_readl(reg); |
a4d7d550 KM |
324 | } |
325 | ||
ca7aceef | 326 | static void __fsi_reg_mask_set(u32 __iomem *reg, u32 mask, u32 data) |
a4d7d550 KM |
327 | { |
328 | u32 val = __fsi_reg_read(reg); | |
329 | ||
330 | val &= ~mask; | |
331 | val |= data & mask; | |
332 | ||
0f69d978 | 333 | __fsi_reg_write(reg, val); |
a4d7d550 KM |
334 | } |
335 | ||
e8c8b631 | 336 | #define fsi_reg_write(p, r, d)\ |
8918b843 | 337 | __fsi_reg_write((p->base + REG_##r), d) |
a4d7d550 | 338 | |
e8c8b631 | 339 | #define fsi_reg_read(p, r)\ |
8918b843 | 340 | __fsi_reg_read((p->base + REG_##r)) |
a4d7d550 | 341 | |
e8c8b631 | 342 | #define fsi_reg_mask_set(p, r, m, d)\ |
8918b843 | 343 | __fsi_reg_mask_set((p->base + REG_##r), m, d) |
a4d7d550 | 344 | |
43fa95ca KM |
345 | #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r) |
346 | #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r) | |
347 | static u32 _fsi_master_read(struct fsi_master *master, u32 reg) | |
a4d7d550 | 348 | { |
8fc176d5 KM |
349 | u32 ret; |
350 | unsigned long flags; | |
351 | ||
8fc176d5 | 352 | spin_lock_irqsave(&master->lock, flags); |
ca7aceef | 353 | ret = __fsi_reg_read(master->base + reg); |
8fc176d5 KM |
354 | spin_unlock_irqrestore(&master->lock, flags); |
355 | ||
356 | return ret; | |
a4d7d550 KM |
357 | } |
358 | ||
43fa95ca KM |
359 | #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d) |
360 | #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d) | |
361 | static void _fsi_master_mask_set(struct fsi_master *master, | |
71f6e064 | 362 | u32 reg, u32 mask, u32 data) |
a4d7d550 | 363 | { |
8fc176d5 KM |
364 | unsigned long flags; |
365 | ||
8fc176d5 | 366 | spin_lock_irqsave(&master->lock, flags); |
ca7aceef | 367 | __fsi_reg_mask_set(master->base + reg, mask, data); |
8fc176d5 | 368 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
369 | } |
370 | ||
c8fe2574 KM |
371 | /* |
372 | * basic function | |
373 | */ | |
284c6f65 KM |
374 | static int fsi_version(struct fsi_master *master) |
375 | { | |
376 | return master->core->ver; | |
377 | } | |
a4d7d550 | 378 | |
71f6e064 | 379 | static struct fsi_master *fsi_get_master(struct fsi_priv *fsi) |
a4d7d550 | 380 | { |
71f6e064 | 381 | return fsi->master; |
a4d7d550 KM |
382 | } |
383 | ||
6a9ebad8 KM |
384 | static int fsi_is_clk_master(struct fsi_priv *fsi) |
385 | { | |
386 | return fsi->clk_master; | |
387 | } | |
388 | ||
a4d7d550 KM |
389 | static int fsi_is_port_a(struct fsi_priv *fsi) |
390 | { | |
71f6e064 KM |
391 | return fsi->master->base == fsi->base; |
392 | } | |
a4d7d550 | 393 | |
9478e0b6 KM |
394 | static int fsi_is_spdif(struct fsi_priv *fsi) |
395 | { | |
396 | return fsi->spdif; | |
397 | } | |
398 | ||
2522acd2 KM |
399 | static int fsi_is_enable_stream(struct fsi_priv *fsi) |
400 | { | |
401 | return fsi->enable_stream; | |
402 | } | |
403 | ||
a449e467 KM |
404 | static int fsi_is_play(struct snd_pcm_substream *substream) |
405 | { | |
406 | return substream->stream == SNDRV_PCM_STREAM_PLAYBACK; | |
407 | } | |
408 | ||
142e8174 | 409 | static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream) |
71f6e064 KM |
410 | { |
411 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
142e8174 | 412 | |
f0fba2ad | 413 | return rtd->cpu_dai; |
142e8174 KM |
414 | } |
415 | ||
0d032c19 | 416 | static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai) |
142e8174 | 417 | { |
f0fba2ad | 418 | struct fsi_master *master = snd_soc_dai_get_drvdata(dai); |
a4d7d550 | 419 | |
f0fba2ad LG |
420 | if (dai->id == 0) |
421 | return &master->fsia; | |
422 | else | |
423 | return &master->fsib; | |
a4d7d550 KM |
424 | } |
425 | ||
0d032c19 KM |
426 | static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream) |
427 | { | |
428 | return fsi_get_priv_frm_dai(fsi_get_dai(substream)); | |
429 | } | |
430 | ||
938e2a8d | 431 | static u32 fsi_get_port_shift(struct fsi_priv *fsi, struct fsi_stream *io) |
a4d7d550 | 432 | { |
938e2a8d | 433 | int is_play = fsi_stream_is_play(fsi, io); |
a4d7d550 | 434 | int is_porta = fsi_is_port_a(fsi); |
cf6edd00 | 435 | u32 shift; |
a4d7d550 KM |
436 | |
437 | if (is_porta) | |
cf6edd00 | 438 | shift = is_play ? AO_SHIFT : AI_SHIFT; |
a4d7d550 | 439 | else |
cf6edd00 | 440 | shift = is_play ? BO_SHIFT : BI_SHIFT; |
a4d7d550 | 441 | |
cf6edd00 | 442 | return shift; |
a4d7d550 KM |
443 | } |
444 | ||
2e651baf KM |
445 | static int fsi_frame2sample(struct fsi_priv *fsi, int frames) |
446 | { | |
447 | return frames * fsi->chan_num; | |
448 | } | |
449 | ||
450 | static int fsi_sample2frame(struct fsi_priv *fsi, int samples) | |
451 | { | |
452 | return samples / fsi->chan_num; | |
453 | } | |
454 | ||
7b1b3331 KM |
455 | static int fsi_get_current_fifo_samples(struct fsi_priv *fsi, |
456 | struct fsi_stream *io) | |
4e62d84d | 457 | { |
7b1b3331 | 458 | int is_play = fsi_stream_is_play(fsi, io); |
4e62d84d KM |
459 | u32 status; |
460 | int frames; | |
461 | ||
462 | status = is_play ? | |
463 | fsi_reg_read(fsi, DOFF_ST) : | |
464 | fsi_reg_read(fsi, DIFF_ST); | |
465 | ||
466 | frames = 0x1ff & (status >> 8); | |
467 | ||
468 | return fsi_frame2sample(fsi, frames); | |
469 | } | |
470 | ||
471 | static void fsi_count_fifo_err(struct fsi_priv *fsi) | |
472 | { | |
473 | u32 ostatus = fsi_reg_read(fsi, DOFF_ST); | |
474 | u32 istatus = fsi_reg_read(fsi, DIFF_ST); | |
475 | ||
476 | if (ostatus & ERR_OVER) | |
477 | fsi->playback.oerr_num++; | |
478 | ||
479 | if (ostatus & ERR_UNDER) | |
480 | fsi->playback.uerr_num++; | |
481 | ||
482 | if (istatus & ERR_OVER) | |
483 | fsi->capture.oerr_num++; | |
484 | ||
485 | if (istatus & ERR_UNDER) | |
486 | fsi->capture.uerr_num++; | |
487 | ||
488 | fsi_reg_write(fsi, DOFF_ST, 0); | |
489 | fsi_reg_write(fsi, DIFF_ST, 0); | |
490 | } | |
491 | ||
492 | /* | |
493 | * fsi_stream_xx() function | |
494 | */ | |
a449e467 KM |
495 | static inline int fsi_stream_is_play(struct fsi_priv *fsi, |
496 | struct fsi_stream *io) | |
4e62d84d | 497 | { |
a449e467 | 498 | return &fsi->playback == io; |
4e62d84d KM |
499 | } |
500 | ||
501 | static inline struct fsi_stream *fsi_stream_get(struct fsi_priv *fsi, | |
938e2a8d | 502 | struct snd_pcm_substream *substream) |
4e62d84d | 503 | { |
938e2a8d | 504 | return fsi_is_play(substream) ? &fsi->playback : &fsi->capture; |
4e62d84d KM |
505 | } |
506 | ||
cda828ca | 507 | static int fsi_stream_is_working(struct fsi_priv *fsi, |
938e2a8d | 508 | struct fsi_stream *io) |
cda828ca | 509 | { |
cda828ca KM |
510 | struct fsi_master *master = fsi_get_master(fsi); |
511 | unsigned long flags; | |
512 | int ret; | |
513 | ||
514 | spin_lock_irqsave(&master->lock, flags); | |
97df8187 | 515 | ret = !!(io->substream && io->substream->runtime); |
cda828ca KM |
516 | spin_unlock_irqrestore(&master->lock, flags); |
517 | ||
518 | return ret; | |
519 | } | |
520 | ||
5e97313a KM |
521 | static struct fsi_priv *fsi_stream_to_priv(struct fsi_stream *io) |
522 | { | |
523 | return io->priv; | |
524 | } | |
525 | ||
8c415295 | 526 | static void fsi_stream_init(struct fsi_priv *fsi, |
938e2a8d | 527 | struct fsi_stream *io, |
0ffe296a | 528 | struct snd_pcm_substream *substream) |
a4d7d550 | 529 | { |
0ffe296a | 530 | struct snd_pcm_runtime *runtime = substream->runtime; |
2da65892 KM |
531 | struct fsi_master *master = fsi_get_master(fsi); |
532 | unsigned long flags; | |
93193c2b | 533 | |
2da65892 | 534 | spin_lock_irqsave(&master->lock, flags); |
93193c2b | 535 | io->substream = substream; |
2e651baf KM |
536 | io->buff_sample_capa = fsi_frame2sample(fsi, runtime->buffer_size); |
537 | io->buff_sample_pos = 0; | |
538 | io->period_samples = fsi_frame2sample(fsi, runtime->period_size); | |
539 | io->period_pos = 0; | |
c1e6f10e | 540 | io->sample_width = samples_to_bytes(runtime, 1); |
766812e6 | 541 | io->bus_option = 0; |
1ec9bc35 KM |
542 | io->oerr_num = -1; /* ignore 1st err */ |
543 | io->uerr_num = -1; /* ignore 1st err */ | |
83344027 | 544 | fsi_stream_handler_call(io, init, fsi, io); |
2da65892 | 545 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
546 | } |
547 | ||
938e2a8d | 548 | static void fsi_stream_quit(struct fsi_priv *fsi, struct fsi_stream *io) |
a4d7d550 | 549 | { |
1ec9bc35 | 550 | struct snd_soc_dai *dai = fsi_get_dai(io->substream); |
2da65892 KM |
551 | struct fsi_master *master = fsi_get_master(fsi); |
552 | unsigned long flags; | |
1ec9bc35 | 553 | |
2da65892 | 554 | spin_lock_irqsave(&master->lock, flags); |
1ec9bc35 KM |
555 | |
556 | if (io->oerr_num > 0) | |
557 | dev_err(dai->dev, "over_run = %d\n", io->oerr_num); | |
558 | ||
559 | if (io->uerr_num > 0) | |
560 | dev_err(dai->dev, "under_run = %d\n", io->uerr_num); | |
93193c2b | 561 | |
83344027 | 562 | fsi_stream_handler_call(io, quit, fsi, io); |
93193c2b | 563 | io->substream = NULL; |
2e651baf KM |
564 | io->buff_sample_capa = 0; |
565 | io->buff_sample_pos = 0; | |
566 | io->period_samples = 0; | |
567 | io->period_pos = 0; | |
c1e6f10e | 568 | io->sample_width = 0; |
766812e6 | 569 | io->bus_option = 0; |
1ec9bc35 KM |
570 | io->oerr_num = 0; |
571 | io->uerr_num = 0; | |
2da65892 | 572 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
573 | } |
574 | ||
5e97313a KM |
575 | static int fsi_stream_transfer(struct fsi_stream *io) |
576 | { | |
577 | struct fsi_priv *fsi = fsi_stream_to_priv(io); | |
578 | if (!fsi) | |
579 | return -EIO; | |
580 | ||
581 | return fsi_stream_handler_call(io, transfer, fsi, io); | |
582 | } | |
583 | ||
180346ed KM |
584 | #define fsi_stream_start(fsi, io)\ |
585 | fsi_stream_handler_call(io, start_stop, fsi, io, 1) | |
586 | ||
587 | #define fsi_stream_stop(fsi, io)\ | |
588 | fsi_stream_handler_call(io, start_stop, fsi, io, 0) | |
589 | ||
b1226dc5 | 590 | static int fsi_stream_probe(struct fsi_priv *fsi, struct device *dev) |
5e97313a KM |
591 | { |
592 | struct fsi_stream *io; | |
593 | int ret1, ret2; | |
594 | ||
595 | io = &fsi->playback; | |
b1226dc5 | 596 | ret1 = fsi_stream_handler_call(io, probe, fsi, io, dev); |
5e97313a KM |
597 | |
598 | io = &fsi->capture; | |
b1226dc5 | 599 | ret2 = fsi_stream_handler_call(io, probe, fsi, io, dev); |
5e97313a KM |
600 | |
601 | if (ret1 < 0) | |
602 | return ret1; | |
603 | if (ret2 < 0) | |
604 | return ret2; | |
605 | ||
606 | return 0; | |
607 | } | |
608 | ||
609 | static int fsi_stream_remove(struct fsi_priv *fsi) | |
610 | { | |
611 | struct fsi_stream *io; | |
612 | int ret1, ret2; | |
613 | ||
614 | io = &fsi->playback; | |
615 | ret1 = fsi_stream_handler_call(io, remove, fsi, io); | |
616 | ||
617 | io = &fsi->capture; | |
618 | ret2 = fsi_stream_handler_call(io, remove, fsi, io); | |
619 | ||
620 | if (ret1 < 0) | |
621 | return ret1; | |
622 | if (ret2 < 0) | |
623 | return ret2; | |
624 | ||
625 | return 0; | |
626 | } | |
627 | ||
766812e6 KM |
628 | /* |
629 | * format/bus/dma setting | |
630 | */ | |
631 | static void fsi_format_bus_setup(struct fsi_priv *fsi, struct fsi_stream *io, | |
632 | u32 bus, struct device *dev) | |
633 | { | |
634 | struct fsi_master *master = fsi_get_master(fsi); | |
635 | int is_play = fsi_stream_is_play(fsi, io); | |
636 | u32 fmt = fsi->fmt; | |
637 | ||
638 | if (fsi_version(master) >= 2) { | |
639 | u32 dma = 0; | |
640 | ||
641 | /* | |
642 | * FSI2 needs DMA/Bus setting | |
643 | */ | |
644 | switch (bus) { | |
645 | case PACKAGE_24BITBUS_FRONT: | |
646 | fmt |= CR_BWS_24; | |
647 | dma |= VDMD_FRONT; | |
648 | dev_dbg(dev, "24bit bus / package in front\n"); | |
649 | break; | |
650 | case PACKAGE_16BITBUS_STREAM: | |
651 | fmt |= CR_BWS_16; | |
652 | dma |= VDMD_STREAM; | |
653 | dev_dbg(dev, "16bit bus / stream mode\n"); | |
654 | break; | |
655 | case PACKAGE_24BITBUS_BACK: | |
656 | default: | |
657 | fmt |= CR_BWS_24; | |
658 | dma |= VDMD_BACK; | |
659 | dev_dbg(dev, "24bit bus / package in back\n"); | |
660 | break; | |
661 | } | |
662 | ||
663 | if (is_play) | |
664 | fsi_reg_write(fsi, OUT_DMAC, dma); | |
665 | else | |
666 | fsi_reg_write(fsi, IN_DMAC, dma); | |
667 | } | |
668 | ||
669 | if (is_play) | |
670 | fsi_reg_write(fsi, DO_FMT, fmt); | |
671 | else | |
672 | fsi_reg_write(fsi, DI_FMT, fmt); | |
673 | } | |
674 | ||
c8fe2574 KM |
675 | /* |
676 | * irq function | |
677 | */ | |
a4d7d550 | 678 | |
938e2a8d | 679 | static void fsi_irq_enable(struct fsi_priv *fsi, struct fsi_stream *io) |
a4d7d550 | 680 | { |
938e2a8d | 681 | u32 data = AB_IO(1, fsi_get_port_shift(fsi, io)); |
71f6e064 | 682 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 683 | |
43fa95ca KM |
684 | fsi_core_mask_set(master, imsk, data, data); |
685 | fsi_core_mask_set(master, iemsk, data, data); | |
a4d7d550 KM |
686 | } |
687 | ||
938e2a8d | 688 | static void fsi_irq_disable(struct fsi_priv *fsi, struct fsi_stream *io) |
a4d7d550 | 689 | { |
938e2a8d | 690 | u32 data = AB_IO(1, fsi_get_port_shift(fsi, io)); |
71f6e064 | 691 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 692 | |
43fa95ca KM |
693 | fsi_core_mask_set(master, imsk, data, 0); |
694 | fsi_core_mask_set(master, iemsk, data, 0); | |
a4d7d550 KM |
695 | } |
696 | ||
10ea76cc KM |
697 | static u32 fsi_irq_get_status(struct fsi_master *master) |
698 | { | |
43fa95ca | 699 | return fsi_core_read(master, int_st); |
10ea76cc KM |
700 | } |
701 | ||
10ea76cc KM |
702 | static void fsi_irq_clear_status(struct fsi_priv *fsi) |
703 | { | |
704 | u32 data = 0; | |
705 | struct fsi_master *master = fsi_get_master(fsi); | |
706 | ||
938e2a8d KM |
707 | data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->playback)); |
708 | data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->capture)); | |
10ea76cc KM |
709 | |
710 | /* clear interrupt factor */ | |
43fa95ca | 711 | fsi_core_mask_set(master, int_st, data, 0); |
10ea76cc KM |
712 | } |
713 | ||
c8fe2574 KM |
714 | /* |
715 | * SPDIF master clock function | |
716 | * | |
717 | * These functions are used later FSI2 | |
718 | */ | |
3bc28070 KM |
719 | static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable) |
720 | { | |
721 | struct fsi_master *master = fsi_get_master(fsi); | |
2b0e7302 | 722 | u32 mask, val; |
3bc28070 | 723 | |
2b0e7302 KM |
724 | mask = BP | SE; |
725 | val = enable ? mask : 0; | |
726 | ||
727 | fsi_is_port_a(fsi) ? | |
43fa95ca KM |
728 | fsi_core_mask_set(master, a_mclk, mask, val) : |
729 | fsi_core_mask_set(master, b_mclk, mask, val); | |
3bc28070 KM |
730 | } |
731 | ||
c8fe2574 | 732 | /* |
1f5e2a31 | 733 | * clock function |
c8fe2574 | 734 | */ |
ab6f6d85 KM |
735 | static int fsi_clk_init(struct device *dev, |
736 | struct fsi_priv *fsi, | |
737 | int xck, | |
738 | int ick, | |
739 | int div, | |
740 | int (*set_rate)(struct device *dev, | |
6cbdbffb | 741 | struct fsi_priv *fsi)) |
ab6f6d85 KM |
742 | { |
743 | struct fsi_clk *clock = &fsi->clock; | |
744 | int is_porta = fsi_is_port_a(fsi); | |
745 | ||
746 | clock->xck = NULL; | |
747 | clock->ick = NULL; | |
748 | clock->div = NULL; | |
749 | clock->rate = 0; | |
750 | clock->count = 0; | |
751 | clock->set_rate = set_rate; | |
752 | ||
753 | clock->own = devm_clk_get(dev, NULL); | |
754 | if (IS_ERR(clock->own)) | |
755 | return -EINVAL; | |
756 | ||
757 | /* external clock */ | |
758 | if (xck) { | |
759 | clock->xck = devm_clk_get(dev, is_porta ? "xcka" : "xckb"); | |
760 | if (IS_ERR(clock->xck)) { | |
761 | dev_err(dev, "can't get xck clock\n"); | |
762 | return -EINVAL; | |
763 | } | |
764 | if (clock->xck == clock->own) { | |
765 | dev_err(dev, "cpu doesn't support xck clock\n"); | |
766 | return -EINVAL; | |
767 | } | |
768 | } | |
769 | ||
770 | /* FSIACLK/FSIBCLK */ | |
771 | if (ick) { | |
772 | clock->ick = devm_clk_get(dev, is_porta ? "icka" : "ickb"); | |
773 | if (IS_ERR(clock->ick)) { | |
774 | dev_err(dev, "can't get ick clock\n"); | |
775 | return -EINVAL; | |
776 | } | |
777 | if (clock->ick == clock->own) { | |
778 | dev_err(dev, "cpu doesn't support ick clock\n"); | |
779 | return -EINVAL; | |
780 | } | |
781 | } | |
782 | ||
783 | /* FSI-DIV */ | |
784 | if (div) { | |
785 | clock->div = devm_clk_get(dev, is_porta ? "diva" : "divb"); | |
786 | if (IS_ERR(clock->div)) { | |
787 | dev_err(dev, "can't get div clock\n"); | |
788 | return -EINVAL; | |
789 | } | |
790 | if (clock->div == clock->own) { | |
791 | dev_err(dev, "cpu doens't support div clock\n"); | |
792 | return -EINVAL; | |
793 | } | |
794 | } | |
795 | ||
796 | return 0; | |
797 | } | |
798 | ||
799 | #define fsi_clk_invalid(fsi) fsi_clk_valid(fsi, 0) | |
800 | static void fsi_clk_valid(struct fsi_priv *fsi, unsigned long rate) | |
801 | { | |
802 | fsi->clock.rate = rate; | |
803 | } | |
804 | ||
805 | static int fsi_clk_is_valid(struct fsi_priv *fsi) | |
806 | { | |
807 | return fsi->clock.set_rate && | |
808 | fsi->clock.rate; | |
809 | } | |
810 | ||
811 | static int fsi_clk_enable(struct device *dev, | |
6cbdbffb | 812 | struct fsi_priv *fsi) |
ab6f6d85 KM |
813 | { |
814 | struct fsi_clk *clock = &fsi->clock; | |
815 | int ret = -EINVAL; | |
816 | ||
817 | if (!fsi_clk_is_valid(fsi)) | |
818 | return ret; | |
819 | ||
820 | if (0 == clock->count) { | |
6cbdbffb | 821 | ret = clock->set_rate(dev, fsi); |
ab6f6d85 KM |
822 | if (ret < 0) { |
823 | fsi_clk_invalid(fsi); | |
824 | return ret; | |
825 | } | |
826 | ||
827 | if (clock->xck) | |
828 | clk_enable(clock->xck); | |
829 | if (clock->ick) | |
830 | clk_enable(clock->ick); | |
831 | if (clock->div) | |
832 | clk_enable(clock->div); | |
833 | ||
834 | clock->count++; | |
835 | } | |
836 | ||
837 | return ret; | |
838 | } | |
839 | ||
840 | static int fsi_clk_disable(struct device *dev, | |
841 | struct fsi_priv *fsi) | |
842 | { | |
843 | struct fsi_clk *clock = &fsi->clock; | |
844 | ||
845 | if (!fsi_clk_is_valid(fsi)) | |
846 | return -EINVAL; | |
847 | ||
848 | if (1 == clock->count--) { | |
849 | if (clock->xck) | |
850 | clk_disable(clock->xck); | |
851 | if (clock->ick) | |
852 | clk_disable(clock->ick); | |
853 | if (clock->div) | |
854 | clk_disable(clock->div); | |
855 | } | |
856 | ||
857 | return 0; | |
858 | } | |
859 | ||
860 | static int fsi_clk_set_ackbpf(struct device *dev, | |
861 | struct fsi_priv *fsi, | |
862 | int ackmd, int bpfmd) | |
863 | { | |
864 | u32 data = 0; | |
865 | ||
866 | /* check ackmd/bpfmd relationship */ | |
867 | if (bpfmd > ackmd) { | |
868 | dev_err(dev, "unsupported rate (%d/%d)\n", ackmd, bpfmd); | |
869 | return -EINVAL; | |
870 | } | |
871 | ||
872 | /* ACKMD */ | |
873 | switch (ackmd) { | |
874 | case 512: | |
875 | data |= (0x0 << 12); | |
876 | break; | |
877 | case 256: | |
878 | data |= (0x1 << 12); | |
879 | break; | |
880 | case 128: | |
881 | data |= (0x2 << 12); | |
882 | break; | |
883 | case 64: | |
884 | data |= (0x3 << 12); | |
885 | break; | |
886 | case 32: | |
887 | data |= (0x4 << 12); | |
888 | break; | |
889 | default: | |
890 | dev_err(dev, "unsupported ackmd (%d)\n", ackmd); | |
891 | return -EINVAL; | |
892 | } | |
893 | ||
894 | /* BPFMD */ | |
895 | switch (bpfmd) { | |
896 | case 32: | |
897 | data |= (0x0 << 8); | |
898 | break; | |
899 | case 64: | |
900 | data |= (0x1 << 8); | |
901 | break; | |
902 | case 128: | |
903 | data |= (0x2 << 8); | |
904 | break; | |
905 | case 256: | |
906 | data |= (0x3 << 8); | |
907 | break; | |
908 | case 512: | |
909 | data |= (0x4 << 8); | |
910 | break; | |
911 | case 16: | |
912 | data |= (0x7 << 8); | |
913 | break; | |
914 | default: | |
915 | dev_err(dev, "unsupported bpfmd (%d)\n", bpfmd); | |
916 | return -EINVAL; | |
917 | } | |
918 | ||
919 | dev_dbg(dev, "ACKMD/BPFMD = %d/%d\n", ackmd, bpfmd); | |
920 | ||
921 | fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data); | |
922 | udelay(10); | |
923 | ||
924 | return 0; | |
925 | } | |
926 | ||
927 | static int fsi_clk_set_rate_external(struct device *dev, | |
6cbdbffb | 928 | struct fsi_priv *fsi) |
ab6f6d85 KM |
929 | { |
930 | struct clk *xck = fsi->clock.xck; | |
931 | struct clk *ick = fsi->clock.ick; | |
6cbdbffb | 932 | unsigned long rate = fsi->clock.rate; |
ab6f6d85 KM |
933 | unsigned long xrate; |
934 | int ackmd, bpfmd; | |
935 | int ret = 0; | |
936 | ||
937 | /* check clock rate */ | |
938 | xrate = clk_get_rate(xck); | |
939 | if (xrate % rate) { | |
940 | dev_err(dev, "unsupported clock rate\n"); | |
941 | return -EINVAL; | |
942 | } | |
943 | ||
944 | clk_set_parent(ick, xck); | |
945 | clk_set_rate(ick, xrate); | |
946 | ||
947 | bpfmd = fsi->chan_num * 32; | |
948 | ackmd = xrate / rate; | |
949 | ||
950 | dev_dbg(dev, "external/rate = %ld/%ld\n", xrate, rate); | |
951 | ||
952 | ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd); | |
953 | if (ret < 0) | |
954 | dev_err(dev, "%s failed", __func__); | |
955 | ||
956 | return ret; | |
957 | } | |
958 | ||
959 | static int fsi_clk_set_rate_cpg(struct device *dev, | |
6cbdbffb | 960 | struct fsi_priv *fsi) |
ab6f6d85 KM |
961 | { |
962 | struct clk *ick = fsi->clock.ick; | |
963 | struct clk *div = fsi->clock.div; | |
6cbdbffb | 964 | unsigned long rate = fsi->clock.rate; |
ab6f6d85 KM |
965 | unsigned long target = 0; /* 12288000 or 11289600 */ |
966 | unsigned long actual, cout; | |
967 | unsigned long diff, min; | |
968 | unsigned long best_cout, best_act; | |
969 | int adj; | |
970 | int ackmd, bpfmd; | |
971 | int ret = -EINVAL; | |
972 | ||
973 | if (!(12288000 % rate)) | |
974 | target = 12288000; | |
975 | if (!(11289600 % rate)) | |
976 | target = 11289600; | |
977 | if (!target) { | |
978 | dev_err(dev, "unsupported rate\n"); | |
979 | return ret; | |
980 | } | |
981 | ||
982 | bpfmd = fsi->chan_num * 32; | |
983 | ackmd = target / rate; | |
984 | ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd); | |
985 | if (ret < 0) { | |
986 | dev_err(dev, "%s failed", __func__); | |
987 | return ret; | |
988 | } | |
989 | ||
990 | /* | |
991 | * The clock flow is | |
992 | * | |
993 | * [CPG] = cout => [FSI_DIV] = audio => [FSI] => [codec] | |
994 | * | |
995 | * But, it needs to find best match of CPG and FSI_DIV | |
996 | * combination, since it is difficult to generate correct | |
997 | * frequency of audio clock from ick clock only. | |
998 | * Because ick is created from its parent clock. | |
999 | * | |
1000 | * target = rate x [512/256/128/64]fs | |
1001 | * cout = round(target x adjustment) | |
1002 | * actual = cout / adjustment (by FSI-DIV) ~= target | |
1003 | * audio = actual | |
1004 | */ | |
1005 | min = ~0; | |
1006 | best_cout = 0; | |
1007 | best_act = 0; | |
1008 | for (adj = 1; adj < 0xffff; adj++) { | |
1009 | ||
1010 | cout = target * adj; | |
1011 | if (cout > 100000000) /* max clock = 100MHz */ | |
1012 | break; | |
1013 | ||
1014 | /* cout/actual audio clock */ | |
1015 | cout = clk_round_rate(ick, cout); | |
1016 | actual = cout / adj; | |
1017 | ||
1018 | /* find best frequency */ | |
1019 | diff = abs(actual - target); | |
1020 | if (diff < min) { | |
1021 | min = diff; | |
1022 | best_cout = cout; | |
1023 | best_act = actual; | |
1024 | } | |
1025 | } | |
1026 | ||
1027 | ret = clk_set_rate(ick, best_cout); | |
1028 | if (ret < 0) { | |
1029 | dev_err(dev, "ick clock failed\n"); | |
1030 | return -EIO; | |
1031 | } | |
1032 | ||
1033 | ret = clk_set_rate(div, clk_round_rate(div, best_act)); | |
1034 | if (ret < 0) { | |
1035 | dev_err(dev, "div clock failed\n"); | |
1036 | return -EIO; | |
1037 | } | |
1038 | ||
1039 | dev_dbg(dev, "ick/div = %ld/%ld\n", | |
1040 | clk_get_rate(ick), clk_get_rate(div)); | |
1041 | ||
1042 | return ret; | |
1043 | } | |
1044 | ||
1f5e2a31 | 1045 | /* |
1b0ca1a0 | 1046 | * pio data transfer handler |
1f5e2a31 | 1047 | */ |
1b0ca1a0 KM |
1048 | static void fsi_pio_push16(struct fsi_priv *fsi, u8 *_buf, int samples) |
1049 | { | |
1b0ca1a0 KM |
1050 | int i; |
1051 | ||
2522acd2 | 1052 | if (fsi_is_enable_stream(fsi)) { |
766812e6 KM |
1053 | /* |
1054 | * stream mode | |
1055 | * see | |
1056 | * fsi_pio_push_init() | |
1057 | */ | |
1058 | u32 *buf = (u32 *)_buf; | |
1059 | ||
1060 | for (i = 0; i < samples / 2; i++) | |
1061 | fsi_reg_write(fsi, DODT, buf[i]); | |
1062 | } else { | |
1063 | /* normal mode */ | |
1064 | u16 *buf = (u16 *)_buf; | |
1065 | ||
1066 | for (i = 0; i < samples; i++) | |
1067 | fsi_reg_write(fsi, DODT, ((u32)*(buf + i) << 8)); | |
1068 | } | |
1b0ca1a0 KM |
1069 | } |
1070 | ||
1071 | static void fsi_pio_pop16(struct fsi_priv *fsi, u8 *_buf, int samples) | |
1072 | { | |
1073 | u16 *buf = (u16 *)_buf; | |
1074 | int i; | |
1075 | ||
1076 | for (i = 0; i < samples; i++) | |
1077 | *(buf + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8); | |
1078 | } | |
1079 | ||
1080 | static void fsi_pio_push32(struct fsi_priv *fsi, u8 *_buf, int samples) | |
1081 | { | |
1082 | u32 *buf = (u32 *)_buf; | |
1083 | int i; | |
1084 | ||
1085 | for (i = 0; i < samples; i++) | |
1086 | fsi_reg_write(fsi, DODT, *(buf + i)); | |
1087 | } | |
1088 | ||
1089 | static void fsi_pio_pop32(struct fsi_priv *fsi, u8 *_buf, int samples) | |
1090 | { | |
1091 | u32 *buf = (u32 *)_buf; | |
1092 | int i; | |
1093 | ||
1094 | for (i = 0; i < samples; i++) | |
1095 | *(buf + i) = fsi_reg_read(fsi, DIDT); | |
1096 | } | |
1097 | ||
1098 | static u8 *fsi_pio_get_area(struct fsi_priv *fsi, struct fsi_stream *io) | |
1099 | { | |
1100 | struct snd_pcm_runtime *runtime = io->substream->runtime; | |
1101 | ||
1102 | return runtime->dma_area + | |
1103 | samples_to_bytes(runtime, io->buff_sample_pos); | |
1104 | } | |
1105 | ||
1106 | static int fsi_pio_transfer(struct fsi_priv *fsi, struct fsi_stream *io, | |
95b0cf05 KM |
1107 | void (*run16)(struct fsi_priv *fsi, u8 *buf, int samples), |
1108 | void (*run32)(struct fsi_priv *fsi, u8 *buf, int samples), | |
1109 | int samples) | |
a4d7d550 KM |
1110 | { |
1111 | struct snd_pcm_runtime *runtime; | |
376cf38a | 1112 | struct snd_pcm_substream *substream; |
95b0cf05 | 1113 | u8 *buf; |
b9fde18c | 1114 | int over_period; |
a4d7d550 | 1115 | |
97df8187 | 1116 | if (!fsi_stream_is_working(fsi, io)) |
a4d7d550 KM |
1117 | return -EINVAL; |
1118 | ||
1c418d1f | 1119 | over_period = 0; |
93193c2b | 1120 | substream = io->substream; |
1c418d1f | 1121 | runtime = substream->runtime; |
a4d7d550 KM |
1122 | |
1123 | /* FSI FIFO has limit. | |
1124 | * So, this driver can not send periods data at a time | |
1125 | */ | |
2e651baf KM |
1126 | if (io->buff_sample_pos >= |
1127 | io->period_samples * (io->period_pos + 1)) { | |
a4d7d550 | 1128 | |
1c418d1f | 1129 | over_period = 1; |
2e651baf | 1130 | io->period_pos = (io->period_pos + 1) % runtime->periods; |
a4d7d550 | 1131 | |
2e651baf KM |
1132 | if (0 == io->period_pos) |
1133 | io->buff_sample_pos = 0; | |
a4d7d550 KM |
1134 | } |
1135 | ||
95b0cf05 KM |
1136 | buf = fsi_pio_get_area(fsi, io); |
1137 | ||
376cf38a KM |
1138 | switch (io->sample_width) { |
1139 | case 2: | |
95b0cf05 | 1140 | run16(fsi, buf, samples); |
376cf38a KM |
1141 | break; |
1142 | case 4: | |
95b0cf05 | 1143 | run32(fsi, buf, samples); |
376cf38a KM |
1144 | break; |
1145 | default: | |
1146 | return -EINVAL; | |
d8b33534 | 1147 | } |
a4d7d550 | 1148 | |
2e651baf KM |
1149 | /* update buff_sample_pos */ |
1150 | io->buff_sample_pos += samples; | |
a4d7d550 | 1151 | |
1c418d1f | 1152 | if (over_period) |
a4d7d550 KM |
1153 | snd_pcm_period_elapsed(substream); |
1154 | ||
47fc9a0a | 1155 | return 0; |
a4d7d550 KM |
1156 | } |
1157 | ||
5e97313a | 1158 | static int fsi_pio_pop(struct fsi_priv *fsi, struct fsi_stream *io) |
07102f3c | 1159 | { |
376cf38a KM |
1160 | int sample_residues; /* samples in FSI fifo */ |
1161 | int sample_space; /* ALSA free samples space */ | |
1162 | int samples; | |
376cf38a | 1163 | |
7b1b3331 | 1164 | sample_residues = fsi_get_current_fifo_samples(fsi, io); |
376cf38a KM |
1165 | sample_space = io->buff_sample_capa - io->buff_sample_pos; |
1166 | ||
1167 | samples = min(sample_residues, sample_space); | |
1168 | ||
1b0ca1a0 | 1169 | return fsi_pio_transfer(fsi, io, |
d78629e2 KM |
1170 | fsi_pio_pop16, |
1171 | fsi_pio_pop32, | |
376cf38a | 1172 | samples); |
d8b33534 | 1173 | } |
07102f3c | 1174 | |
5e97313a | 1175 | static int fsi_pio_push(struct fsi_priv *fsi, struct fsi_stream *io) |
d8b33534 | 1176 | { |
376cf38a KM |
1177 | int sample_residues; /* ALSA residue samples */ |
1178 | int sample_space; /* FSI fifo free samples space */ | |
1179 | int samples; | |
376cf38a KM |
1180 | |
1181 | sample_residues = io->buff_sample_capa - io->buff_sample_pos; | |
1182 | sample_space = io->fifo_sample_capa - | |
7b1b3331 | 1183 | fsi_get_current_fifo_samples(fsi, io); |
376cf38a KM |
1184 | |
1185 | samples = min(sample_residues, sample_space); | |
1186 | ||
1b0ca1a0 | 1187 | return fsi_pio_transfer(fsi, io, |
d78629e2 KM |
1188 | fsi_pio_push16, |
1189 | fsi_pio_push32, | |
376cf38a | 1190 | samples); |
07102f3c KM |
1191 | } |
1192 | ||
c375b2d7 | 1193 | static int fsi_pio_start_stop(struct fsi_priv *fsi, struct fsi_stream *io, |
180346ed KM |
1194 | int enable) |
1195 | { | |
1196 | struct fsi_master *master = fsi_get_master(fsi); | |
1197 | u32 clk = fsi_is_port_a(fsi) ? CRA : CRB; | |
1198 | ||
1199 | if (enable) | |
1200 | fsi_irq_enable(fsi, io); | |
1201 | else | |
1202 | fsi_irq_disable(fsi, io); | |
1203 | ||
1204 | if (fsi_is_clk_master(fsi)) | |
1205 | fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0); | |
c375b2d7 KM |
1206 | |
1207 | return 0; | |
180346ed KM |
1208 | } |
1209 | ||
766812e6 KM |
1210 | static int fsi_pio_push_init(struct fsi_priv *fsi, struct fsi_stream *io) |
1211 | { | |
766812e6 KM |
1212 | /* |
1213 | * we can use 16bit stream mode | |
1214 | * when "playback" and "16bit data" | |
1215 | * and platform allows "stream mode" | |
1216 | * see | |
1217 | * fsi_pio_push16() | |
1218 | */ | |
2522acd2 | 1219 | if (fsi_is_enable_stream(fsi)) |
766812e6 KM |
1220 | io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | |
1221 | BUSOP_SET(16, PACKAGE_16BITBUS_STREAM); | |
1222 | else | |
1223 | io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | | |
1224 | BUSOP_SET(16, PACKAGE_24BITBUS_BACK); | |
1225 | return 0; | |
1226 | } | |
1227 | ||
1228 | static int fsi_pio_pop_init(struct fsi_priv *fsi, struct fsi_stream *io) | |
1229 | { | |
1230 | /* | |
1231 | * always 24bit bus, package back when "capture" | |
1232 | */ | |
1233 | io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | | |
1234 | BUSOP_SET(16, PACKAGE_24BITBUS_BACK); | |
1235 | return 0; | |
1236 | } | |
1237 | ||
5e97313a | 1238 | static struct fsi_stream_handler fsi_pio_push_handler = { |
766812e6 | 1239 | .init = fsi_pio_push_init, |
5e97313a | 1240 | .transfer = fsi_pio_push, |
180346ed | 1241 | .start_stop = fsi_pio_start_stop, |
5e97313a KM |
1242 | }; |
1243 | ||
1244 | static struct fsi_stream_handler fsi_pio_pop_handler = { | |
766812e6 | 1245 | .init = fsi_pio_pop_init, |
5e97313a | 1246 | .transfer = fsi_pio_pop, |
180346ed | 1247 | .start_stop = fsi_pio_start_stop, |
5e97313a KM |
1248 | }; |
1249 | ||
a4d7d550 KM |
1250 | static irqreturn_t fsi_interrupt(int irq, void *data) |
1251 | { | |
71f6e064 | 1252 | struct fsi_master *master = data; |
10ea76cc | 1253 | u32 int_st = fsi_irq_get_status(master); |
a4d7d550 KM |
1254 | |
1255 | /* clear irq status */ | |
feb58cff KM |
1256 | fsi_master_mask_set(master, SOFT_RST, IR, 0); |
1257 | fsi_master_mask_set(master, SOFT_RST, IR, IR); | |
a4d7d550 | 1258 | |
cf6edd00 | 1259 | if (int_st & AB_IO(1, AO_SHIFT)) |
5e97313a | 1260 | fsi_stream_transfer(&master->fsia.playback); |
cf6edd00 | 1261 | if (int_st & AB_IO(1, BO_SHIFT)) |
5e97313a | 1262 | fsi_stream_transfer(&master->fsib.playback); |
cf6edd00 | 1263 | if (int_st & AB_IO(1, AI_SHIFT)) |
5e97313a | 1264 | fsi_stream_transfer(&master->fsia.capture); |
cf6edd00 | 1265 | if (int_st & AB_IO(1, BI_SHIFT)) |
5e97313a | 1266 | fsi_stream_transfer(&master->fsib.capture); |
1ec9bc35 KM |
1267 | |
1268 | fsi_count_fifo_err(&master->fsia); | |
1269 | fsi_count_fifo_err(&master->fsib); | |
a4d7d550 | 1270 | |
48d78e58 KM |
1271 | fsi_irq_clear_status(&master->fsia); |
1272 | fsi_irq_clear_status(&master->fsib); | |
a4d7d550 KM |
1273 | |
1274 | return IRQ_HANDLED; | |
1275 | } | |
1276 | ||
7da9ced6 KM |
1277 | /* |
1278 | * dma data transfer handler | |
1279 | */ | |
1280 | static int fsi_dma_init(struct fsi_priv *fsi, struct fsi_stream *io) | |
1281 | { | |
1282 | struct snd_pcm_runtime *runtime = io->substream->runtime; | |
1283 | struct snd_soc_dai *dai = fsi_get_dai(io->substream); | |
1284 | enum dma_data_direction dir = fsi_stream_is_play(fsi, io) ? | |
1285 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
1286 | ||
766812e6 KM |
1287 | /* |
1288 | * 24bit data : 24bit bus / package in back | |
1289 | * 16bit data : 16bit bus / stream mode | |
1290 | */ | |
1291 | io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | | |
1292 | BUSOP_SET(16, PACKAGE_16BITBUS_STREAM); | |
1293 | ||
53110a25 KM |
1294 | io->loop_cnt = 2; /* push 1st, 2nd period first, then 3rd, 4th... */ |
1295 | io->additional_pos = 0; | |
7da9ced6 KM |
1296 | io->dma = dma_map_single(dai->dev, runtime->dma_area, |
1297 | snd_pcm_lib_buffer_bytes(io->substream), dir); | |
1298 | return 0; | |
1299 | } | |
1300 | ||
1301 | static int fsi_dma_quit(struct fsi_priv *fsi, struct fsi_stream *io) | |
1302 | { | |
1303 | struct snd_soc_dai *dai = fsi_get_dai(io->substream); | |
1304 | enum dma_data_direction dir = fsi_stream_is_play(fsi, io) ? | |
1305 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
1306 | ||
1307 | dma_unmap_single(dai->dev, io->dma, | |
1308 | snd_pcm_lib_buffer_bytes(io->substream), dir); | |
1309 | return 0; | |
1310 | } | |
1311 | ||
53110a25 | 1312 | static dma_addr_t fsi_dma_get_area(struct fsi_stream *io, int additional) |
4a1b09b7 KM |
1313 | { |
1314 | struct snd_pcm_runtime *runtime = io->substream->runtime; | |
53110a25 | 1315 | int period = io->period_pos + additional; |
4a1b09b7 | 1316 | |
53110a25 KM |
1317 | if (period >= runtime->periods) |
1318 | period = 0; | |
1319 | ||
1320 | return io->dma + samples_to_bytes(runtime, period * io->period_samples); | |
4a1b09b7 KM |
1321 | } |
1322 | ||
7da9ced6 KM |
1323 | static void fsi_dma_complete(void *data) |
1324 | { | |
1325 | struct fsi_stream *io = (struct fsi_stream *)data; | |
1326 | struct fsi_priv *fsi = fsi_stream_to_priv(io); | |
1327 | struct snd_pcm_runtime *runtime = io->substream->runtime; | |
1328 | struct snd_soc_dai *dai = fsi_get_dai(io->substream); | |
1329 | enum dma_data_direction dir = fsi_stream_is_play(fsi, io) ? | |
1330 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
1331 | ||
53110a25 | 1332 | dma_sync_single_for_cpu(dai->dev, fsi_dma_get_area(io, 0), |
7da9ced6 KM |
1333 | samples_to_bytes(runtime, io->period_samples), dir); |
1334 | ||
1335 | io->buff_sample_pos += io->period_samples; | |
1336 | io->period_pos++; | |
1337 | ||
1338 | if (io->period_pos >= runtime->periods) { | |
1339 | io->period_pos = 0; | |
1340 | io->buff_sample_pos = 0; | |
1341 | } | |
1342 | ||
1343 | fsi_count_fifo_err(fsi); | |
1344 | fsi_stream_transfer(io); | |
1345 | ||
1346 | snd_pcm_period_elapsed(io->substream); | |
1347 | } | |
1348 | ||
57451e43 | 1349 | static void fsi_dma_do_work(struct work_struct *work) |
7da9ced6 | 1350 | { |
57451e43 | 1351 | struct fsi_stream *io = container_of(work, struct fsi_stream, work); |
7da9ced6 | 1352 | struct fsi_priv *fsi = fsi_stream_to_priv(io); |
7da9ced6 KM |
1353 | struct snd_soc_dai *dai; |
1354 | struct dma_async_tx_descriptor *desc; | |
7da9ced6 KM |
1355 | struct snd_pcm_runtime *runtime; |
1356 | enum dma_data_direction dir; | |
7da9ced6 | 1357 | int is_play = fsi_stream_is_play(fsi, io); |
53110a25 | 1358 | int len, i; |
7da9ced6 KM |
1359 | dma_addr_t buf; |
1360 | ||
1361 | if (!fsi_stream_is_working(fsi, io)) | |
1362 | return; | |
1363 | ||
1364 | dai = fsi_get_dai(io->substream); | |
7da9ced6 KM |
1365 | runtime = io->substream->runtime; |
1366 | dir = is_play ? DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
1367 | len = samples_to_bytes(runtime, io->period_samples); | |
7da9ced6 | 1368 | |
53110a25 KM |
1369 | for (i = 0; i < io->loop_cnt; i++) { |
1370 | buf = fsi_dma_get_area(io, io->additional_pos); | |
7da9ced6 | 1371 | |
53110a25 | 1372 | dma_sync_single_for_device(dai->dev, buf, len, dir); |
7da9ced6 | 1373 | |
53110a25 KM |
1374 | desc = dmaengine_prep_slave_single(io->chan, buf, len, dir, |
1375 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
1376 | if (!desc) { | |
1377 | dev_err(dai->dev, "dmaengine_prep_slave_sg() fail\n"); | |
1378 | return; | |
1379 | } | |
7da9ced6 | 1380 | |
53110a25 KM |
1381 | desc->callback = fsi_dma_complete; |
1382 | desc->callback_param = io; | |
1383 | ||
1384 | if (dmaengine_submit(desc) < 0) { | |
1385 | dev_err(dai->dev, "tx_submit() fail\n"); | |
1386 | return; | |
1387 | } | |
1388 | ||
1389 | dma_async_issue_pending(io->chan); | |
1390 | ||
1391 | io->additional_pos = 1; | |
7da9ced6 KM |
1392 | } |
1393 | ||
53110a25 | 1394 | io->loop_cnt = 1; |
7da9ced6 KM |
1395 | |
1396 | /* | |
1397 | * FIXME | |
1398 | * | |
1399 | * In DMAEngine case, codec and FSI cannot be started simultaneously | |
57451e43 | 1400 | * since FSI is using the scheduler work queue. |
7da9ced6 KM |
1401 | * Therefore, in capture case, probably FSI FIFO will have got |
1402 | * overflow error in this point. | |
1403 | * in that case, DMA cannot start transfer until error was cleared. | |
1404 | */ | |
1405 | if (!is_play) { | |
1406 | if (ERR_OVER & fsi_reg_read(fsi, DIFF_ST)) { | |
1407 | fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR); | |
1408 | fsi_reg_write(fsi, DIFF_ST, 0); | |
1409 | } | |
1410 | } | |
1411 | } | |
1412 | ||
1413 | static bool fsi_dma_filter(struct dma_chan *chan, void *param) | |
1414 | { | |
1415 | struct sh_dmae_slave *slave = param; | |
1416 | ||
1417 | chan->private = slave; | |
1418 | ||
1419 | return true; | |
1420 | } | |
1421 | ||
1422 | static int fsi_dma_transfer(struct fsi_priv *fsi, struct fsi_stream *io) | |
1423 | { | |
57451e43 | 1424 | schedule_work(&io->work); |
7da9ced6 KM |
1425 | |
1426 | return 0; | |
1427 | } | |
1428 | ||
c375b2d7 | 1429 | static int fsi_dma_push_start_stop(struct fsi_priv *fsi, struct fsi_stream *io, |
7da9ced6 KM |
1430 | int start) |
1431 | { | |
e42bb9bf KM |
1432 | struct fsi_master *master = fsi_get_master(fsi); |
1433 | u32 clk = fsi_is_port_a(fsi) ? CRA : CRB; | |
766812e6 | 1434 | u32 enable = start ? DMA_ON : 0; |
7da9ced6 | 1435 | |
766812e6 | 1436 | fsi_reg_mask_set(fsi, OUT_DMAC, DMA_ON, enable); |
e42bb9bf | 1437 | |
fbe42f66 KM |
1438 | dmaengine_terminate_all(io->chan); |
1439 | ||
e42bb9bf KM |
1440 | if (fsi_is_clk_master(fsi)) |
1441 | fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0); | |
c375b2d7 KM |
1442 | |
1443 | return 0; | |
7da9ced6 KM |
1444 | } |
1445 | ||
b1226dc5 | 1446 | static int fsi_dma_probe(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev) |
7da9ced6 KM |
1447 | { |
1448 | dma_cap_mask_t mask; | |
1449 | ||
1450 | dma_cap_zero(mask); | |
1451 | dma_cap_set(DMA_SLAVE, mask); | |
1452 | ||
1453 | io->chan = dma_request_channel(mask, fsi_dma_filter, &io->slave); | |
b1226dc5 KM |
1454 | if (!io->chan) { |
1455 | ||
1456 | /* switch to PIO handler */ | |
1457 | if (fsi_stream_is_play(fsi, io)) | |
1458 | fsi->playback.handler = &fsi_pio_push_handler; | |
1459 | else | |
1460 | fsi->capture.handler = &fsi_pio_pop_handler; | |
1461 | ||
1462 | dev_info(dev, "switch handler (dma => pio)\n"); | |
1463 | ||
1464 | /* probe again */ | |
1465 | return fsi_stream_probe(fsi, dev); | |
1466 | } | |
7da9ced6 | 1467 | |
57451e43 | 1468 | INIT_WORK(&io->work, fsi_dma_do_work); |
7da9ced6 KM |
1469 | |
1470 | return 0; | |
1471 | } | |
1472 | ||
1473 | static int fsi_dma_remove(struct fsi_priv *fsi, struct fsi_stream *io) | |
1474 | { | |
57451e43 | 1475 | cancel_work_sync(&io->work); |
7da9ced6 KM |
1476 | |
1477 | fsi_stream_stop(fsi, io); | |
1478 | ||
1479 | if (io->chan) | |
1480 | dma_release_channel(io->chan); | |
1481 | ||
1482 | io->chan = NULL; | |
1483 | return 0; | |
1484 | } | |
1485 | ||
1486 | static struct fsi_stream_handler fsi_dma_push_handler = { | |
1487 | .init = fsi_dma_init, | |
1488 | .quit = fsi_dma_quit, | |
1489 | .probe = fsi_dma_probe, | |
1490 | .transfer = fsi_dma_transfer, | |
1491 | .remove = fsi_dma_remove, | |
1492 | .start_stop = fsi_dma_push_start_stop, | |
1493 | }; | |
1494 | ||
c8fe2574 KM |
1495 | /* |
1496 | * dai ops | |
1497 | */ | |
b49e8027 | 1498 | static void fsi_fifo_init(struct fsi_priv *fsi, |
938e2a8d | 1499 | struct fsi_stream *io, |
b49e8027 KM |
1500 | struct device *dev) |
1501 | { | |
1502 | struct fsi_master *master = fsi_get_master(fsi); | |
938e2a8d | 1503 | int is_play = fsi_stream_is_play(fsi, io); |
b49e8027 KM |
1504 | u32 shift, i; |
1505 | int frame_capa; | |
1506 | ||
1507 | /* get on-chip RAM capacity */ | |
1508 | shift = fsi_master_read(master, FIFO_SZ); | |
938e2a8d | 1509 | shift >>= fsi_get_port_shift(fsi, io); |
b49e8027 KM |
1510 | shift &= FIFO_SZ_MASK; |
1511 | frame_capa = 256 << shift; | |
1512 | dev_dbg(dev, "fifo = %d words\n", frame_capa); | |
1513 | ||
1514 | /* | |
1515 | * The maximum number of sample data varies depending | |
1516 | * on the number of channels selected for the format. | |
1517 | * | |
1518 | * FIFOs are used in 4-channel units in 3-channel mode | |
1519 | * and in 8-channel units in 5- to 7-channel mode | |
1520 | * meaning that more FIFOs than the required size of DPRAM | |
1521 | * are used. | |
1522 | * | |
1523 | * ex) if 256 words of DP-RAM is connected | |
1524 | * 1 channel: 256 (256 x 1 = 256) | |
1525 | * 2 channels: 128 (128 x 2 = 256) | |
1526 | * 3 channels: 64 ( 64 x 3 = 192) | |
1527 | * 4 channels: 64 ( 64 x 4 = 256) | |
1528 | * 5 channels: 32 ( 32 x 5 = 160) | |
1529 | * 6 channels: 32 ( 32 x 6 = 192) | |
1530 | * 7 channels: 32 ( 32 x 7 = 224) | |
1531 | * 8 channels: 32 ( 32 x 8 = 256) | |
1532 | */ | |
1533 | for (i = 1; i < fsi->chan_num; i <<= 1) | |
1534 | frame_capa >>= 1; | |
1535 | dev_dbg(dev, "%d channel %d store\n", | |
1536 | fsi->chan_num, frame_capa); | |
1537 | ||
1538 | io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa); | |
1539 | ||
1540 | /* | |
1541 | * set interrupt generation factor | |
1542 | * clear FIFO | |
1543 | */ | |
1544 | if (is_play) { | |
1545 | fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF); | |
1546 | fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR); | |
1547 | } else { | |
1548 | fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF); | |
1549 | fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR); | |
1550 | } | |
1551 | } | |
a4d7d550 | 1552 | |
23ca8533 | 1553 | static int fsi_hw_startup(struct fsi_priv *fsi, |
938e2a8d | 1554 | struct fsi_stream *io, |
23ca8533 | 1555 | struct device *dev) |
a4d7d550 | 1556 | { |
9478e0b6 | 1557 | u32 data = 0; |
a4d7d550 | 1558 | |
9478e0b6 KM |
1559 | /* clock setting */ |
1560 | if (fsi_is_clk_master(fsi)) | |
1561 | data = DIMD | DOMD; | |
1562 | ||
1563 | fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data); | |
a4d7d550 KM |
1564 | |
1565 | /* clock inversion (CKG2) */ | |
1566 | data = 0; | |
3449f5fa KM |
1567 | if (fsi->bit_clk_inv) |
1568 | data |= (1 << 0); | |
1569 | if (fsi->lr_clk_inv) | |
1570 | data |= (1 << 4); | |
1571 | if (fsi_is_clk_master(fsi)) | |
1572 | data <<= 8; | |
a4d7d550 KM |
1573 | fsi_reg_write(fsi, CKG2, data); |
1574 | ||
9478e0b6 KM |
1575 | /* spdif ? */ |
1576 | if (fsi_is_spdif(fsi)) { | |
1577 | fsi_spdif_clk_ctrl(fsi, 1); | |
1578 | fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD); | |
1579 | } | |
1580 | ||
65ff03f4 | 1581 | /* |
766812e6 | 1582 | * get bus settings |
65ff03f4 | 1583 | */ |
766812e6 KM |
1584 | data = 0; |
1585 | switch (io->sample_width) { | |
1586 | case 2: | |
1587 | data = BUSOP_GET(16, io->bus_option); | |
1588 | break; | |
1589 | case 4: | |
1590 | data = BUSOP_GET(24, io->bus_option); | |
1591 | break; | |
65ff03f4 | 1592 | } |
766812e6 | 1593 | fsi_format_bus_setup(fsi, io, data, dev); |
65ff03f4 | 1594 | |
10ea76cc | 1595 | /* irq clear */ |
938e2a8d | 1596 | fsi_irq_disable(fsi, io); |
10ea76cc KM |
1597 | fsi_irq_clear_status(fsi); |
1598 | ||
1599 | /* fifo init */ | |
938e2a8d | 1600 | fsi_fifo_init(fsi, io, dev); |
a4d7d550 | 1601 | |
ddeb2d70 KM |
1602 | /* start master clock */ |
1603 | if (fsi_is_clk_master(fsi)) | |
6cbdbffb | 1604 | return fsi_clk_enable(dev, fsi); |
ddeb2d70 | 1605 | |
a68a3b4e | 1606 | return 0; |
a4d7d550 KM |
1607 | } |
1608 | ||
80b4addc | 1609 | static int fsi_hw_shutdown(struct fsi_priv *fsi, |
23ca8533 KM |
1610 | struct device *dev) |
1611 | { | |
ddeb2d70 | 1612 | /* stop master clock */ |
23ca8533 | 1613 | if (fsi_is_clk_master(fsi)) |
6cbdbffb | 1614 | return fsi_clk_disable(dev, fsi); |
80b4addc KM |
1615 | |
1616 | return 0; | |
23ca8533 KM |
1617 | } |
1618 | ||
1619 | static int fsi_dai_startup(struct snd_pcm_substream *substream, | |
1620 | struct snd_soc_dai *dai) | |
1621 | { | |
1622 | struct fsi_priv *fsi = fsi_get_priv(substream); | |
23ca8533 | 1623 | |
ab6f6d85 | 1624 | fsi_clk_invalid(fsi); |
f33238e9 KM |
1625 | |
1626 | return 0; | |
23ca8533 KM |
1627 | } |
1628 | ||
a4d7d550 KM |
1629 | static void fsi_dai_shutdown(struct snd_pcm_substream *substream, |
1630 | struct snd_soc_dai *dai) | |
1631 | { | |
71f6e064 | 1632 | struct fsi_priv *fsi = fsi_get_priv(substream); |
a4d7d550 | 1633 | |
ab6f6d85 | 1634 | fsi_clk_invalid(fsi); |
a4d7d550 KM |
1635 | } |
1636 | ||
1637 | static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd, | |
1638 | struct snd_soc_dai *dai) | |
1639 | { | |
71f6e064 | 1640 | struct fsi_priv *fsi = fsi_get_priv(substream); |
938e2a8d | 1641 | struct fsi_stream *io = fsi_stream_get(fsi, substream); |
a4d7d550 KM |
1642 | int ret = 0; |
1643 | ||
a4d7d550 KM |
1644 | switch (cmd) { |
1645 | case SNDRV_PCM_TRIGGER_START: | |
938e2a8d | 1646 | fsi_stream_init(fsi, io, substream); |
80b4addc KM |
1647 | if (!ret) |
1648 | ret = fsi_hw_startup(fsi, io, dai->dev); | |
1649 | if (!ret) | |
1650 | ret = fsi_stream_transfer(io); | |
1651 | if (!ret) | |
180346ed | 1652 | fsi_stream_start(fsi, io); |
a4d7d550 KM |
1653 | break; |
1654 | case SNDRV_PCM_TRIGGER_STOP: | |
80b4addc KM |
1655 | if (!ret) |
1656 | ret = fsi_hw_shutdown(fsi, dai->dev); | |
180346ed | 1657 | fsi_stream_stop(fsi, io); |
938e2a8d | 1658 | fsi_stream_quit(fsi, io); |
a4d7d550 KM |
1659 | break; |
1660 | } | |
1661 | ||
1662 | return ret; | |
1663 | } | |
1664 | ||
f17c13ca KM |
1665 | static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt) |
1666 | { | |
f17c13ca KM |
1667 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
1668 | case SND_SOC_DAIFMT_I2S: | |
9c59dd34 | 1669 | fsi->fmt = CR_I2S; |
f17c13ca KM |
1670 | fsi->chan_num = 2; |
1671 | break; | |
1672 | case SND_SOC_DAIFMT_LEFT_J: | |
9c59dd34 | 1673 | fsi->fmt = CR_PCM; |
f17c13ca KM |
1674 | fsi->chan_num = 2; |
1675 | break; | |
1676 | default: | |
1677 | return -EINVAL; | |
1678 | } | |
1679 | ||
f17c13ca KM |
1680 | return 0; |
1681 | } | |
1682 | ||
1683 | static int fsi_set_fmt_spdif(struct fsi_priv *fsi) | |
1684 | { | |
1685 | struct fsi_master *master = fsi_get_master(fsi); | |
f17c13ca | 1686 | |
284c6f65 | 1687 | if (fsi_version(master) < 2) |
f17c13ca KM |
1688 | return -EINVAL; |
1689 | ||
766812e6 | 1690 | fsi->fmt = CR_DTMD_SPDIF_PCM | CR_PCM; |
f17c13ca | 1691 | fsi->chan_num = 2; |
f17c13ca | 1692 | |
f17c13ca KM |
1693 | return 0; |
1694 | } | |
1695 | ||
4d805f7b KM |
1696 | static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) |
1697 | { | |
1698 | struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai); | |
4d805f7b KM |
1699 | int ret; |
1700 | ||
4d805f7b KM |
1701 | /* set master/slave audio interface */ |
1702 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1703 | case SND_SOC_DAIFMT_CBM_CFM: | |
6a9ebad8 | 1704 | fsi->clk_master = 1; |
4d805f7b KM |
1705 | break; |
1706 | case SND_SOC_DAIFMT_CBS_CFS: | |
1707 | break; | |
1708 | default: | |
9478e0b6 | 1709 | return -EINVAL; |
4d805f7b | 1710 | } |
6a9ebad8 | 1711 | |
3449f5fa KM |
1712 | /* set clock inversion */ |
1713 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1714 | case SND_SOC_DAIFMT_NB_IF: | |
1715 | fsi->bit_clk_inv = 0; | |
1716 | fsi->lr_clk_inv = 1; | |
f17c13ca | 1717 | break; |
3449f5fa KM |
1718 | case SND_SOC_DAIFMT_IB_NF: |
1719 | fsi->bit_clk_inv = 1; | |
1720 | fsi->lr_clk_inv = 0; | |
f17c13ca | 1721 | break; |
3449f5fa KM |
1722 | case SND_SOC_DAIFMT_IB_IF: |
1723 | fsi->bit_clk_inv = 1; | |
1724 | fsi->lr_clk_inv = 1; | |
1725 | break; | |
1726 | case SND_SOC_DAIFMT_NB_NF: | |
f17c13ca | 1727 | default: |
3449f5fa KM |
1728 | fsi->bit_clk_inv = 0; |
1729 | fsi->lr_clk_inv = 0; | |
1730 | break; | |
1731 | } | |
1732 | ||
ab6f6d85 | 1733 | if (fsi_is_clk_master(fsi)) { |
ab6340c4 | 1734 | if (fsi->clk_cpg) |
ab6f6d85 KM |
1735 | fsi_clk_init(dai->dev, fsi, 0, 1, 1, |
1736 | fsi_clk_set_rate_cpg); | |
ab6340c4 KM |
1737 | else |
1738 | fsi_clk_init(dai->dev, fsi, 1, 1, 0, | |
1739 | fsi_clk_set_rate_external); | |
f17c13ca | 1740 | } |
4d805f7b | 1741 | |
f17c13ca | 1742 | /* set format */ |
c2052def | 1743 | if (fsi_is_spdif(fsi)) |
f17c13ca | 1744 | ret = fsi_set_fmt_spdif(fsi); |
c2052def KM |
1745 | else |
1746 | ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK); | |
4d805f7b | 1747 | |
4d805f7b KM |
1748 | return ret; |
1749 | } | |
1750 | ||
ccad7b44 KM |
1751 | static int fsi_dai_hw_params(struct snd_pcm_substream *substream, |
1752 | struct snd_pcm_hw_params *params, | |
1753 | struct snd_soc_dai *dai) | |
1754 | { | |
1755 | struct fsi_priv *fsi = fsi_get_priv(substream); | |
ccad7b44 | 1756 | |
6cbdbffb KM |
1757 | if (fsi_is_clk_master(fsi)) |
1758 | fsi_clk_valid(fsi, params_rate(params)); | |
ccad7b44 | 1759 | |
ddeb2d70 | 1760 | return 0; |
ccad7b44 KM |
1761 | } |
1762 | ||
85e7652d | 1763 | static const struct snd_soc_dai_ops fsi_dai_ops = { |
a4d7d550 KM |
1764 | .startup = fsi_dai_startup, |
1765 | .shutdown = fsi_dai_shutdown, | |
1766 | .trigger = fsi_dai_trigger, | |
4d805f7b | 1767 | .set_fmt = fsi_dai_set_fmt, |
ccad7b44 | 1768 | .hw_params = fsi_dai_hw_params, |
a4d7d550 KM |
1769 | }; |
1770 | ||
c8fe2574 KM |
1771 | /* |
1772 | * pcm ops | |
1773 | */ | |
a4d7d550 | 1774 | |
a4d7d550 KM |
1775 | static struct snd_pcm_hardware fsi_pcm_hardware = { |
1776 | .info = SNDRV_PCM_INFO_INTERLEAVED | | |
1777 | SNDRV_PCM_INFO_MMAP | | |
1778 | SNDRV_PCM_INFO_MMAP_VALID | | |
1779 | SNDRV_PCM_INFO_PAUSE, | |
1780 | .formats = FSI_FMTS, | |
1781 | .rates = FSI_RATES, | |
1782 | .rate_min = 8000, | |
1783 | .rate_max = 192000, | |
2a8c8a56 | 1784 | .channels_min = 2, |
a4d7d550 KM |
1785 | .channels_max = 2, |
1786 | .buffer_bytes_max = 64 * 1024, | |
1787 | .period_bytes_min = 32, | |
1788 | .period_bytes_max = 8192, | |
1789 | .periods_min = 1, | |
1790 | .periods_max = 32, | |
1791 | .fifo_size = 256, | |
1792 | }; | |
1793 | ||
1794 | static int fsi_pcm_open(struct snd_pcm_substream *substream) | |
1795 | { | |
1796 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1797 | int ret = 0; | |
1798 | ||
1799 | snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware); | |
1800 | ||
1801 | ret = snd_pcm_hw_constraint_integer(runtime, | |
1802 | SNDRV_PCM_HW_PARAM_PERIODS); | |
1803 | ||
1804 | return ret; | |
1805 | } | |
1806 | ||
1807 | static int fsi_hw_params(struct snd_pcm_substream *substream, | |
1808 | struct snd_pcm_hw_params *hw_params) | |
1809 | { | |
1810 | return snd_pcm_lib_malloc_pages(substream, | |
1811 | params_buffer_bytes(hw_params)); | |
1812 | } | |
1813 | ||
1814 | static int fsi_hw_free(struct snd_pcm_substream *substream) | |
1815 | { | |
1816 | return snd_pcm_lib_free_pages(substream); | |
1817 | } | |
1818 | ||
1819 | static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream) | |
1820 | { | |
71f6e064 | 1821 | struct fsi_priv *fsi = fsi_get_priv(substream); |
938e2a8d | 1822 | struct fsi_stream *io = fsi_stream_get(fsi, substream); |
a4d7d550 | 1823 | |
1987877d | 1824 | return fsi_sample2frame(fsi, io->buff_sample_pos); |
a4d7d550 KM |
1825 | } |
1826 | ||
1827 | static struct snd_pcm_ops fsi_pcm_ops = { | |
1828 | .open = fsi_pcm_open, | |
1829 | .ioctl = snd_pcm_lib_ioctl, | |
1830 | .hw_params = fsi_hw_params, | |
1831 | .hw_free = fsi_hw_free, | |
1832 | .pointer = fsi_pointer, | |
1833 | }; | |
1834 | ||
c8fe2574 KM |
1835 | /* |
1836 | * snd_soc_platform | |
1837 | */ | |
a4d7d550 | 1838 | |
a4d7d550 KM |
1839 | #define PREALLOC_BUFFER (32 * 1024) |
1840 | #define PREALLOC_BUFFER_MAX (32 * 1024) | |
1841 | ||
1842 | static void fsi_pcm_free(struct snd_pcm *pcm) | |
1843 | { | |
1844 | snd_pcm_lib_preallocate_free_for_all(pcm); | |
1845 | } | |
1846 | ||
552d1ef6 | 1847 | static int fsi_pcm_new(struct snd_soc_pcm_runtime *rtd) |
a4d7d550 | 1848 | { |
552d1ef6 LG |
1849 | struct snd_pcm *pcm = rtd->pcm; |
1850 | ||
a4d7d550 KM |
1851 | /* |
1852 | * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel | |
1853 | * in MMAP mode (i.e. aplay -M) | |
1854 | */ | |
1855 | return snd_pcm_lib_preallocate_pages_for_all( | |
1856 | pcm, | |
1857 | SNDRV_DMA_TYPE_CONTINUOUS, | |
1858 | snd_dma_continuous_data(GFP_KERNEL), | |
1859 | PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); | |
1860 | } | |
1861 | ||
c8fe2574 KM |
1862 | /* |
1863 | * alsa struct | |
1864 | */ | |
a4d7d550 | 1865 | |
f0fba2ad | 1866 | static struct snd_soc_dai_driver fsi_soc_dai[] = { |
a4d7d550 | 1867 | { |
f0fba2ad | 1868 | .name = "fsia-dai", |
a4d7d550 KM |
1869 | .playback = { |
1870 | .rates = FSI_RATES, | |
1871 | .formats = FSI_FMTS, | |
2a8c8a56 KM |
1872 | .channels_min = 2, |
1873 | .channels_max = 2, | |
a4d7d550 | 1874 | }, |
07102f3c KM |
1875 | .capture = { |
1876 | .rates = FSI_RATES, | |
1877 | .formats = FSI_FMTS, | |
2a8c8a56 KM |
1878 | .channels_min = 2, |
1879 | .channels_max = 2, | |
07102f3c | 1880 | }, |
a4d7d550 KM |
1881 | .ops = &fsi_dai_ops, |
1882 | }, | |
1883 | { | |
f0fba2ad | 1884 | .name = "fsib-dai", |
a4d7d550 KM |
1885 | .playback = { |
1886 | .rates = FSI_RATES, | |
1887 | .formats = FSI_FMTS, | |
2a8c8a56 KM |
1888 | .channels_min = 2, |
1889 | .channels_max = 2, | |
a4d7d550 | 1890 | }, |
07102f3c KM |
1891 | .capture = { |
1892 | .rates = FSI_RATES, | |
1893 | .formats = FSI_FMTS, | |
2a8c8a56 KM |
1894 | .channels_min = 2, |
1895 | .channels_max = 2, | |
07102f3c | 1896 | }, |
a4d7d550 KM |
1897 | .ops = &fsi_dai_ops, |
1898 | }, | |
1899 | }; | |
a4d7d550 | 1900 | |
f0fba2ad LG |
1901 | static struct snd_soc_platform_driver fsi_soc_platform = { |
1902 | .ops = &fsi_pcm_ops, | |
a4d7d550 KM |
1903 | .pcm_new = fsi_pcm_new, |
1904 | .pcm_free = fsi_pcm_free, | |
1905 | }; | |
a4d7d550 | 1906 | |
da4f2f9e KM |
1907 | static const struct snd_soc_component_driver fsi_soc_component = { |
1908 | .name = "fsi", | |
1909 | }; | |
1910 | ||
c8fe2574 KM |
1911 | /* |
1912 | * platform function | |
1913 | */ | |
9e7b6d60 KM |
1914 | static void fsi_of_parse(char *name, |
1915 | struct device_node *np, | |
1916 | struct sh_fsi_port_info *info, | |
1917 | struct device *dev) | |
1918 | { | |
1919 | int i; | |
1920 | char prop[128]; | |
1921 | unsigned long flags = 0; | |
1922 | struct { | |
1923 | char *name; | |
1924 | unsigned int val; | |
1925 | } of_parse_property[] = { | |
1926 | { "spdif-connection", SH_FSI_FMT_SPDIF }, | |
1927 | { "stream-mode-support", SH_FSI_ENABLE_STREAM_MODE }, | |
1928 | { "use-internal-clock", SH_FSI_CLK_CPG }, | |
1929 | }; | |
1930 | ||
1931 | for (i = 0; i < ARRAY_SIZE(of_parse_property); i++) { | |
1932 | sprintf(prop, "%s,%s", name, of_parse_property[i].name); | |
1933 | if (of_get_property(np, prop, NULL)) | |
1934 | flags |= of_parse_property[i].val; | |
1935 | } | |
1936 | info->flags = flags; | |
1937 | ||
1938 | dev_dbg(dev, "%s flags : %lx\n", name, info->flags); | |
1939 | } | |
1940 | ||
c2052def KM |
1941 | static void fsi_port_info_init(struct fsi_priv *fsi, |
1942 | struct sh_fsi_port_info *info) | |
1943 | { | |
1944 | if (info->flags & SH_FSI_FMT_SPDIF) | |
1945 | fsi->spdif = 1; | |
ab6340c4 KM |
1946 | |
1947 | if (info->flags & SH_FSI_CLK_CPG) | |
1948 | fsi->clk_cpg = 1; | |
2522acd2 KM |
1949 | |
1950 | if (info->flags & SH_FSI_ENABLE_STREAM_MODE) | |
1951 | fsi->enable_stream = 1; | |
c2052def KM |
1952 | } |
1953 | ||
943fdadc KM |
1954 | static void fsi_handler_init(struct fsi_priv *fsi, |
1955 | struct sh_fsi_port_info *info) | |
5e97313a KM |
1956 | { |
1957 | fsi->playback.handler = &fsi_pio_push_handler; /* default PIO */ | |
1958 | fsi->playback.priv = fsi; | |
1959 | fsi->capture.handler = &fsi_pio_pop_handler; /* default PIO */ | |
1960 | fsi->capture.priv = fsi; | |
7da9ced6 | 1961 | |
943fdadc KM |
1962 | if (info->tx_id) { |
1963 | fsi->playback.slave.shdma_slave.slave_id = info->tx_id; | |
b8373147 | 1964 | fsi->playback.handler = &fsi_dma_push_handler; |
7da9ced6 | 1965 | } |
5e97313a | 1966 | } |
a4d7d550 | 1967 | |
9e7b6d60 | 1968 | static struct of_device_id fsi_of_match[]; |
a4d7d550 KM |
1969 | static int fsi_probe(struct platform_device *pdev) |
1970 | { | |
71f6e064 | 1971 | struct fsi_master *master; |
9e7b6d60 | 1972 | struct device_node *np = pdev->dev.of_node; |
fd974e52 | 1973 | struct sh_fsi_platform_info info; |
9e7b6d60 | 1974 | const struct fsi_core *core; |
40f9118b | 1975 | struct fsi_priv *fsi; |
a4d7d550 | 1976 | struct resource *res; |
a4d7d550 KM |
1977 | unsigned int irq; |
1978 | int ret; | |
1979 | ||
fd974e52 | 1980 | memset(&info, 0, sizeof(info)); |
943fdadc | 1981 | |
9e7b6d60 KM |
1982 | core = NULL; |
1983 | if (np) { | |
1984 | const struct of_device_id *of_id; | |
1985 | ||
1986 | of_id = of_match_device(fsi_of_match, &pdev->dev); | |
1987 | if (of_id) { | |
1988 | core = of_id->data; | |
1989 | fsi_of_parse("fsia", np, &info.port_a, &pdev->dev); | |
1990 | fsi_of_parse("fsib", np, &info.port_b, &pdev->dev); | |
1991 | } | |
1992 | } else { | |
1993 | const struct platform_device_id *id_entry = pdev->id_entry; | |
1994 | if (id_entry) | |
1995 | core = (struct fsi_core *)id_entry->driver_data; | |
1996 | ||
1997 | if (pdev->dev.platform_data) | |
1998 | memcpy(&info, pdev->dev.platform_data, sizeof(info)); | |
1999 | } | |
2000 | ||
2001 | if (!core) { | |
cc780d38 KM |
2002 | dev_err(&pdev->dev, "unknown fsi device\n"); |
2003 | return -ENODEV; | |
2004 | } | |
2005 | ||
a4d7d550 KM |
2006 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
2007 | irq = platform_get_irq(pdev, 0); | |
b6aa1793 | 2008 | if (!res || (int)irq <= 0) { |
a4d7d550 | 2009 | dev_err(&pdev->dev, "Not enough FSI platform resources.\n"); |
6ac4262f | 2010 | return -ENODEV; |
a4d7d550 KM |
2011 | } |
2012 | ||
6ac4262f | 2013 | master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL); |
a4d7d550 KM |
2014 | if (!master) { |
2015 | dev_err(&pdev->dev, "Could not allocate master\n"); | |
6ac4262f | 2016 | return -ENOMEM; |
a4d7d550 KM |
2017 | } |
2018 | ||
6ac4262f KM |
2019 | master->base = devm_ioremap_nocache(&pdev->dev, |
2020 | res->start, resource_size(res)); | |
a4d7d550 | 2021 | if (!master->base) { |
a4d7d550 | 2022 | dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n"); |
6ac4262f | 2023 | return -ENXIO; |
a4d7d550 KM |
2024 | } |
2025 | ||
3bc28070 | 2026 | /* master setting */ |
9e7b6d60 | 2027 | master->core = core; |
3bc28070 KM |
2028 | spin_lock_init(&master->lock); |
2029 | ||
2030 | /* FSI A setting */ | |
40f9118b KM |
2031 | fsi = &master->fsia; |
2032 | fsi->base = master->base; | |
2033 | fsi->master = master; | |
fd974e52 KM |
2034 | fsi_port_info_init(fsi, &info.port_a); |
2035 | fsi_handler_init(fsi, &info.port_a); | |
40f9118b | 2036 | ret = fsi_stream_probe(fsi, &pdev->dev); |
5e97313a KM |
2037 | if (ret < 0) { |
2038 | dev_err(&pdev->dev, "FSIA stream probe failed\n"); | |
6ac4262f | 2039 | return ret; |
5e97313a | 2040 | } |
3bc28070 KM |
2041 | |
2042 | /* FSI B setting */ | |
40f9118b KM |
2043 | fsi = &master->fsib; |
2044 | fsi->base = master->base + 0x40; | |
2045 | fsi->master = master; | |
fd974e52 KM |
2046 | fsi_port_info_init(fsi, &info.port_b); |
2047 | fsi_handler_init(fsi, &info.port_b); | |
40f9118b | 2048 | ret = fsi_stream_probe(fsi, &pdev->dev); |
5e97313a KM |
2049 | if (ret < 0) { |
2050 | dev_err(&pdev->dev, "FSIB stream probe failed\n"); | |
2051 | goto exit_fsia; | |
2052 | } | |
a4d7d550 | 2053 | |
785d1c45 | 2054 | pm_runtime_enable(&pdev->dev); |
f0fba2ad | 2055 | dev_set_drvdata(&pdev->dev, master); |
a4d7d550 | 2056 | |
1ddd8286 | 2057 | ret = devm_request_irq(&pdev->dev, irq, &fsi_interrupt, 0, |
9e7b6d60 | 2058 | dev_name(&pdev->dev), master); |
a4d7d550 KM |
2059 | if (ret) { |
2060 | dev_err(&pdev->dev, "irq request err\n"); | |
5e97313a | 2061 | goto exit_fsib; |
a4d7d550 KM |
2062 | } |
2063 | ||
f0fba2ad | 2064 | ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform); |
a4d7d550 KM |
2065 | if (ret < 0) { |
2066 | dev_err(&pdev->dev, "cannot snd soc register\n"); | |
1ddd8286 | 2067 | goto exit_fsib; |
a4d7d550 KM |
2068 | } |
2069 | ||
da4f2f9e KM |
2070 | ret = snd_soc_register_component(&pdev->dev, &fsi_soc_component, |
2071 | fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai)); | |
0b5ec87d | 2072 | if (ret < 0) { |
da4f2f9e | 2073 | dev_err(&pdev->dev, "cannot snd component register\n"); |
0b5ec87d KM |
2074 | goto exit_snd_soc; |
2075 | } | |
a4d7d550 | 2076 | |
0b5ec87d KM |
2077 | return ret; |
2078 | ||
2079 | exit_snd_soc: | |
2080 | snd_soc_unregister_platform(&pdev->dev); | |
5e97313a | 2081 | exit_fsib: |
c35e005f | 2082 | pm_runtime_disable(&pdev->dev); |
5e97313a KM |
2083 | fsi_stream_remove(&master->fsib); |
2084 | exit_fsia: | |
2085 | fsi_stream_remove(&master->fsia); | |
6ac4262f | 2086 | |
a4d7d550 KM |
2087 | return ret; |
2088 | } | |
2089 | ||
2090 | static int fsi_remove(struct platform_device *pdev) | |
2091 | { | |
71f6e064 KM |
2092 | struct fsi_master *master; |
2093 | ||
f0fba2ad | 2094 | master = dev_get_drvdata(&pdev->dev); |
71f6e064 | 2095 | |
785d1c45 | 2096 | pm_runtime_disable(&pdev->dev); |
a4d7d550 | 2097 | |
da4f2f9e | 2098 | snd_soc_unregister_component(&pdev->dev); |
d985f27e | 2099 | snd_soc_unregister_platform(&pdev->dev); |
a4d7d550 | 2100 | |
5e97313a KM |
2101 | fsi_stream_remove(&master->fsia); |
2102 | fsi_stream_remove(&master->fsib); | |
2103 | ||
a4d7d550 KM |
2104 | return 0; |
2105 | } | |
2106 | ||
106c79ec | 2107 | static void __fsi_suspend(struct fsi_priv *fsi, |
938e2a8d | 2108 | struct fsi_stream *io, |
4f56cde1 | 2109 | struct device *dev) |
106c79ec | 2110 | { |
938e2a8d | 2111 | if (!fsi_stream_is_working(fsi, io)) |
cda828ca | 2112 | return; |
106c79ec | 2113 | |
180346ed | 2114 | fsi_stream_stop(fsi, io); |
41bba151 | 2115 | fsi_hw_shutdown(fsi, dev); |
106c79ec KM |
2116 | } |
2117 | ||
2118 | static void __fsi_resume(struct fsi_priv *fsi, | |
938e2a8d | 2119 | struct fsi_stream *io, |
4f56cde1 | 2120 | struct device *dev) |
106c79ec | 2121 | { |
938e2a8d | 2122 | if (!fsi_stream_is_working(fsi, io)) |
cda828ca | 2123 | return; |
106c79ec | 2124 | |
938e2a8d | 2125 | fsi_hw_startup(fsi, io, dev); |
180346ed | 2126 | fsi_stream_start(fsi, io); |
106c79ec KM |
2127 | } |
2128 | ||
2129 | static int fsi_suspend(struct device *dev) | |
2130 | { | |
2131 | struct fsi_master *master = dev_get_drvdata(dev); | |
cda828ca KM |
2132 | struct fsi_priv *fsia = &master->fsia; |
2133 | struct fsi_priv *fsib = &master->fsib; | |
106c79ec | 2134 | |
938e2a8d KM |
2135 | __fsi_suspend(fsia, &fsia->playback, dev); |
2136 | __fsi_suspend(fsia, &fsia->capture, dev); | |
106c79ec | 2137 | |
938e2a8d KM |
2138 | __fsi_suspend(fsib, &fsib->playback, dev); |
2139 | __fsi_suspend(fsib, &fsib->capture, dev); | |
106c79ec KM |
2140 | |
2141 | return 0; | |
2142 | } | |
2143 | ||
2144 | static int fsi_resume(struct device *dev) | |
2145 | { | |
2146 | struct fsi_master *master = dev_get_drvdata(dev); | |
cda828ca KM |
2147 | struct fsi_priv *fsia = &master->fsia; |
2148 | struct fsi_priv *fsib = &master->fsib; | |
106c79ec | 2149 | |
938e2a8d KM |
2150 | __fsi_resume(fsia, &fsia->playback, dev); |
2151 | __fsi_resume(fsia, &fsia->capture, dev); | |
106c79ec | 2152 | |
938e2a8d KM |
2153 | __fsi_resume(fsib, &fsib->playback, dev); |
2154 | __fsi_resume(fsib, &fsib->capture, dev); | |
106c79ec KM |
2155 | |
2156 | return 0; | |
2157 | } | |
2158 | ||
785d1c45 | 2159 | static struct dev_pm_ops fsi_pm_ops = { |
106c79ec KM |
2160 | .suspend = fsi_suspend, |
2161 | .resume = fsi_resume, | |
785d1c45 KM |
2162 | }; |
2163 | ||
73b92c1f KM |
2164 | static struct fsi_core fsi1_core = { |
2165 | .ver = 1, | |
2166 | ||
2167 | /* Interrupt */ | |
cc780d38 KM |
2168 | .int_st = INT_ST, |
2169 | .iemsk = IEMSK, | |
2170 | .imsk = IMSK, | |
2171 | }; | |
2172 | ||
73b92c1f KM |
2173 | static struct fsi_core fsi2_core = { |
2174 | .ver = 2, | |
2175 | ||
2176 | /* Interrupt */ | |
cc780d38 KM |
2177 | .int_st = CPU_INT_ST, |
2178 | .iemsk = CPU_IEMSK, | |
2179 | .imsk = CPU_IMSK, | |
2b0e7302 KM |
2180 | .a_mclk = A_MST_CTLR, |
2181 | .b_mclk = B_MST_CTLR, | |
cc780d38 KM |
2182 | }; |
2183 | ||
e43fc6af | 2184 | static struct of_device_id fsi_of_match[] = { |
9e7b6d60 KM |
2185 | { .compatible = "renesas,sh_fsi", .data = &fsi1_core}, |
2186 | { .compatible = "renesas,sh_fsi2", .data = &fsi2_core}, | |
2187 | {}, | |
2188 | }; | |
2189 | MODULE_DEVICE_TABLE(of, fsi_of_match); | |
2190 | ||
cc780d38 | 2191 | static struct platform_device_id fsi_id_table[] = { |
73b92c1f KM |
2192 | { "sh_fsi", (kernel_ulong_t)&fsi1_core }, |
2193 | { "sh_fsi2", (kernel_ulong_t)&fsi2_core }, | |
05c69450 | 2194 | {}, |
cc780d38 | 2195 | }; |
d85a6d7b | 2196 | MODULE_DEVICE_TABLE(platform, fsi_id_table); |
cc780d38 | 2197 | |
a4d7d550 KM |
2198 | static struct platform_driver fsi_driver = { |
2199 | .driver = { | |
f0fba2ad | 2200 | .name = "fsi-pcm-audio", |
785d1c45 | 2201 | .pm = &fsi_pm_ops, |
9e7b6d60 | 2202 | .of_match_table = fsi_of_match, |
a4d7d550 KM |
2203 | }, |
2204 | .probe = fsi_probe, | |
2205 | .remove = fsi_remove, | |
cc780d38 | 2206 | .id_table = fsi_id_table, |
a4d7d550 KM |
2207 | }; |
2208 | ||
cb5e8738 | 2209 | module_platform_driver(fsi_driver); |
a4d7d550 KM |
2210 | |
2211 | MODULE_LICENSE("GPL"); | |
2212 | MODULE_DESCRIPTION("SuperH onchip FSI audio driver"); | |
2213 | MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>"); | |
b3c27b51 | 2214 | MODULE_ALIAS("platform:fsi-pcm-audio"); |