Commit | Line | Data |
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a4d7d550 KM |
1 | /* |
2 | * Fifo-attached Serial Interface (FSI) support for SH7724 | |
3 | * | |
4 | * Copyright (C) 2009 Renesas Solutions Corp. | |
5 | * Kuninori Morimoto <morimoto.kuninori@renesas.com> | |
6 | * | |
7 | * Based on ssi.c | |
8 | * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
a4d7d550 | 15 | #include <linux/delay.h> |
785d1c45 | 16 | #include <linux/pm_runtime.h> |
a4d7d550 | 17 | #include <linux/io.h> |
5a0e3ad6 | 18 | #include <linux/slab.h> |
a4d7d550 | 19 | #include <sound/soc.h> |
a4d7d550 | 20 | #include <sound/sh_fsi.h> |
a4d7d550 | 21 | |
e8c8b631 KM |
22 | /* PortA/PortB register */ |
23 | #define REG_DO_FMT 0x0000 | |
24 | #define REG_DOFF_CTL 0x0004 | |
25 | #define REG_DOFF_ST 0x0008 | |
26 | #define REG_DI_FMT 0x000C | |
27 | #define REG_DIFF_CTL 0x0010 | |
28 | #define REG_DIFF_ST 0x0014 | |
29 | #define REG_CKG1 0x0018 | |
30 | #define REG_CKG2 0x001C | |
31 | #define REG_DIDT 0x0020 | |
32 | #define REG_DODT 0x0024 | |
33 | #define REG_MUTE_ST 0x0028 | |
34 | #define REG_OUT_SEL 0x0030 | |
cc780d38 | 35 | |
43fa95ca KM |
36 | /* master register */ |
37 | #define MST_CLK_RST 0x0210 | |
38 | #define MST_SOFT_RST 0x0214 | |
39 | #define MST_FIFO_SZ 0x0218 | |
40 | ||
41 | /* core register (depend on FSI version) */ | |
3bc28070 KM |
42 | #define A_MST_CTLR 0x0180 |
43 | #define B_MST_CTLR 0x01A0 | |
cc780d38 KM |
44 | #define CPU_INT_ST 0x01F4 |
45 | #define CPU_IEMSK 0x01F8 | |
46 | #define CPU_IMSK 0x01FC | |
a4d7d550 KM |
47 | #define INT_ST 0x0200 |
48 | #define IEMSK 0x0204 | |
49 | #define IMSK 0x0208 | |
a4d7d550 KM |
50 | |
51 | /* DO_FMT */ | |
52 | /* DI_FMT */ | |
f7d711e3 KM |
53 | #define CR_BWS_24 (0x0 << 20) /* FSI2 */ |
54 | #define CR_BWS_16 (0x1 << 20) /* FSI2 */ | |
55 | #define CR_BWS_20 (0x2 << 20) /* FSI2 */ | |
56 | ||
57 | #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */ | |
58 | #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */ | |
59 | #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */ | |
60 | ||
a7ffb52b KM |
61 | #define CR_MONO (0x0 << 4) |
62 | #define CR_MONO_D (0x1 << 4) | |
63 | #define CR_PCM (0x2 << 4) | |
64 | #define CR_I2S (0x3 << 4) | |
65 | #define CR_TDM (0x4 << 4) | |
66 | #define CR_TDM_D (0x5 << 4) | |
a4d7d550 KM |
67 | |
68 | /* DOFF_CTL */ | |
69 | /* DIFF_CTL */ | |
70 | #define IRQ_HALF 0x00100000 | |
71 | #define FIFO_CLR 0x00000001 | |
72 | ||
73 | /* DOFF_ST */ | |
74 | #define ERR_OVER 0x00000010 | |
75 | #define ERR_UNDER 0x00000001 | |
59c3b003 | 76 | #define ST_ERR (ERR_OVER | ERR_UNDER) |
a4d7d550 | 77 | |
ccad7b44 KM |
78 | /* CKG1 */ |
79 | #define ACKMD_MASK 0x00007000 | |
80 | #define BPFMD_MASK 0x00000700 | |
81 | ||
3bc28070 KM |
82 | /* A/B MST_CTLR */ |
83 | #define BP (1 << 4) /* Fix the signal of Biphase output */ | |
84 | #define SE (1 << 0) /* Fix the master clock */ | |
85 | ||
a4d7d550 KM |
86 | /* CLK_RST */ |
87 | #define B_CLK 0x00000010 | |
88 | #define A_CLK 0x00000001 | |
89 | ||
cf6edd00 KM |
90 | /* IO SHIFT / MACRO */ |
91 | #define BI_SHIFT 12 | |
92 | #define BO_SHIFT 8 | |
93 | #define AI_SHIFT 4 | |
94 | #define AO_SHIFT 0 | |
95 | #define AB_IO(param, shift) (param << shift) | |
a4d7d550 | 96 | |
feb58cff KM |
97 | /* SOFT_RST */ |
98 | #define PBSR (1 << 12) /* Port B Software Reset */ | |
99 | #define PASR (1 << 8) /* Port A Software Reset */ | |
100 | #define IR (1 << 4) /* Interrupt Reset */ | |
101 | #define FSISR (1 << 0) /* Software Reset */ | |
102 | ||
f7d711e3 KM |
103 | /* OUT_SEL (FSI2) */ |
104 | #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */ | |
105 | /* 1: Biphase and serial */ | |
106 | ||
4a942b45 | 107 | /* FIFO_SZ */ |
cf6edd00 | 108 | #define FIFO_SZ_MASK 0x7 |
4a942b45 | 109 | |
a4d7d550 KM |
110 | #define FSI_RATES SNDRV_PCM_RATE_8000_96000 |
111 | ||
112 | #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE) | |
113 | ||
5bfb9ad0 KM |
114 | /* |
115 | * FSI driver use below type name for variable | |
116 | * | |
117 | * xxx_len : data length | |
118 | * xxx_width : data width | |
119 | * xxx_offset : data offset | |
120 | * xxx_num : number of data | |
121 | */ | |
122 | ||
c8fe2574 KM |
123 | /* |
124 | * struct | |
125 | */ | |
a4d7d550 | 126 | |
93193c2b | 127 | struct fsi_stream { |
a4d7d550 KM |
128 | struct snd_pcm_substream *substream; |
129 | ||
5bfb9ad0 KM |
130 | int fifo_max_num; |
131 | int chan_num; | |
a4d7d550 | 132 | |
5bfb9ad0 KM |
133 | int buff_offset; |
134 | int buff_len; | |
a4d7d550 | 135 | int period_len; |
5bfb9ad0 | 136 | int period_num; |
1ec9bc35 KM |
137 | |
138 | int uerr_num; | |
139 | int oerr_num; | |
93193c2b KM |
140 | }; |
141 | ||
142 | struct fsi_priv { | |
143 | void __iomem *base; | |
144 | struct fsi_master *master; | |
145 | ||
146 | struct fsi_stream playback; | |
147 | struct fsi_stream capture; | |
3bc28070 | 148 | |
d4bc99b9 | 149 | long rate; |
a4d7d550 KM |
150 | }; |
151 | ||
73b92c1f KM |
152 | struct fsi_core { |
153 | int ver; | |
154 | ||
cc780d38 KM |
155 | u32 int_st; |
156 | u32 iemsk; | |
157 | u32 imsk; | |
2b0e7302 KM |
158 | u32 a_mclk; |
159 | u32 b_mclk; | |
cc780d38 KM |
160 | }; |
161 | ||
a4d7d550 KM |
162 | struct fsi_master { |
163 | void __iomem *base; | |
164 | int irq; | |
a4d7d550 KM |
165 | struct fsi_priv fsia; |
166 | struct fsi_priv fsib; | |
73b92c1f | 167 | struct fsi_core *core; |
a4d7d550 | 168 | struct sh_fsi_platform_info *info; |
8fc176d5 | 169 | spinlock_t lock; |
a4d7d550 KM |
170 | }; |
171 | ||
c8fe2574 KM |
172 | /* |
173 | * basic read write function | |
174 | */ | |
a4d7d550 | 175 | |
0f69d978 | 176 | static void __fsi_reg_write(u32 reg, u32 data) |
a4d7d550 KM |
177 | { |
178 | /* valid data area is 24bit */ | |
179 | data &= 0x00ffffff; | |
180 | ||
0f69d978 | 181 | __raw_writel(data, reg); |
a4d7d550 KM |
182 | } |
183 | ||
184 | static u32 __fsi_reg_read(u32 reg) | |
185 | { | |
0f69d978 | 186 | return __raw_readl(reg); |
a4d7d550 KM |
187 | } |
188 | ||
0f69d978 | 189 | static void __fsi_reg_mask_set(u32 reg, u32 mask, u32 data) |
a4d7d550 KM |
190 | { |
191 | u32 val = __fsi_reg_read(reg); | |
192 | ||
193 | val &= ~mask; | |
194 | val |= data & mask; | |
195 | ||
0f69d978 | 196 | __fsi_reg_write(reg, val); |
a4d7d550 KM |
197 | } |
198 | ||
e8c8b631 KM |
199 | #define fsi_reg_write(p, r, d)\ |
200 | __fsi_reg_write((u32)(p->base + REG_##r), d) | |
a4d7d550 | 201 | |
e8c8b631 KM |
202 | #define fsi_reg_read(p, r)\ |
203 | __fsi_reg_read((u32)(p->base + REG_##r)) | |
a4d7d550 | 204 | |
e8c8b631 KM |
205 | #define fsi_reg_mask_set(p, r, m, d)\ |
206 | __fsi_reg_mask_set((u32)(p->base + REG_##r), m, d) | |
a4d7d550 | 207 | |
43fa95ca KM |
208 | #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r) |
209 | #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r) | |
210 | static u32 _fsi_master_read(struct fsi_master *master, u32 reg) | |
a4d7d550 | 211 | { |
8fc176d5 KM |
212 | u32 ret; |
213 | unsigned long flags; | |
214 | ||
8fc176d5 KM |
215 | spin_lock_irqsave(&master->lock, flags); |
216 | ret = __fsi_reg_read((u32)(master->base + reg)); | |
217 | spin_unlock_irqrestore(&master->lock, flags); | |
218 | ||
219 | return ret; | |
a4d7d550 KM |
220 | } |
221 | ||
43fa95ca KM |
222 | #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d) |
223 | #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d) | |
224 | static void _fsi_master_mask_set(struct fsi_master *master, | |
71f6e064 | 225 | u32 reg, u32 mask, u32 data) |
a4d7d550 | 226 | { |
8fc176d5 KM |
227 | unsigned long flags; |
228 | ||
8fc176d5 | 229 | spin_lock_irqsave(&master->lock, flags); |
0f69d978 | 230 | __fsi_reg_mask_set((u32)(master->base + reg), mask, data); |
8fc176d5 | 231 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
232 | } |
233 | ||
c8fe2574 KM |
234 | /* |
235 | * basic function | |
236 | */ | |
a4d7d550 | 237 | |
71f6e064 | 238 | static struct fsi_master *fsi_get_master(struct fsi_priv *fsi) |
a4d7d550 | 239 | { |
71f6e064 | 240 | return fsi->master; |
a4d7d550 KM |
241 | } |
242 | ||
243 | static int fsi_is_port_a(struct fsi_priv *fsi) | |
244 | { | |
71f6e064 KM |
245 | return fsi->master->base == fsi->base; |
246 | } | |
a4d7d550 | 247 | |
142e8174 | 248 | static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream) |
71f6e064 KM |
249 | { |
250 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
142e8174 | 251 | |
f0fba2ad | 252 | return rtd->cpu_dai; |
142e8174 KM |
253 | } |
254 | ||
0d032c19 | 255 | static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai) |
142e8174 | 256 | { |
f0fba2ad | 257 | struct fsi_master *master = snd_soc_dai_get_drvdata(dai); |
a4d7d550 | 258 | |
f0fba2ad LG |
259 | if (dai->id == 0) |
260 | return &master->fsia; | |
261 | else | |
262 | return &master->fsib; | |
a4d7d550 KM |
263 | } |
264 | ||
0d032c19 KM |
265 | static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream) |
266 | { | |
267 | return fsi_get_priv_frm_dai(fsi_get_dai(substream)); | |
268 | } | |
269 | ||
a4d7d550 KM |
270 | static u32 fsi_get_info_flags(struct fsi_priv *fsi) |
271 | { | |
272 | int is_porta = fsi_is_port_a(fsi); | |
71f6e064 | 273 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 KM |
274 | |
275 | return is_porta ? master->info->porta_flags : | |
276 | master->info->portb_flags; | |
277 | } | |
278 | ||
93193c2b KM |
279 | static inline int fsi_stream_is_play(int stream) |
280 | { | |
281 | return stream == SNDRV_PCM_STREAM_PLAYBACK; | |
282 | } | |
283 | ||
00545785 KM |
284 | static inline int fsi_is_play(struct snd_pcm_substream *substream) |
285 | { | |
93193c2b KM |
286 | return fsi_stream_is_play(substream->stream); |
287 | } | |
288 | ||
289 | static inline struct fsi_stream *fsi_get_stream(struct fsi_priv *fsi, | |
290 | int is_play) | |
291 | { | |
292 | return is_play ? &fsi->playback : &fsi->capture; | |
00545785 KM |
293 | } |
294 | ||
a4d7d550 KM |
295 | static int fsi_is_master_mode(struct fsi_priv *fsi, int is_play) |
296 | { | |
297 | u32 mode; | |
298 | u32 flags = fsi_get_info_flags(fsi); | |
299 | ||
300 | mode = is_play ? SH_FSI_OUT_SLAVE_MODE : SH_FSI_IN_SLAVE_MODE; | |
301 | ||
302 | /* return | |
303 | * 1 : master mode | |
304 | * 0 : slave mode | |
305 | */ | |
306 | ||
307 | return (mode & flags) != mode; | |
308 | } | |
309 | ||
cf6edd00 | 310 | static u32 fsi_get_port_shift(struct fsi_priv *fsi, int is_play) |
a4d7d550 KM |
311 | { |
312 | int is_porta = fsi_is_port_a(fsi); | |
cf6edd00 | 313 | u32 shift; |
a4d7d550 KM |
314 | |
315 | if (is_porta) | |
cf6edd00 | 316 | shift = is_play ? AO_SHIFT : AI_SHIFT; |
a4d7d550 | 317 | else |
cf6edd00 | 318 | shift = is_play ? BO_SHIFT : BI_SHIFT; |
a4d7d550 | 319 | |
cf6edd00 | 320 | return shift; |
a4d7d550 KM |
321 | } |
322 | ||
323 | static void fsi_stream_push(struct fsi_priv *fsi, | |
93193c2b | 324 | int is_play, |
a4d7d550 KM |
325 | struct snd_pcm_substream *substream, |
326 | u32 buffer_len, | |
327 | u32 period_len) | |
328 | { | |
93193c2b KM |
329 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); |
330 | ||
331 | io->substream = substream; | |
332 | io->buff_len = buffer_len; | |
333 | io->buff_offset = 0; | |
334 | io->period_len = period_len; | |
335 | io->period_num = 0; | |
1ec9bc35 KM |
336 | io->oerr_num = -1; /* ignore 1st err */ |
337 | io->uerr_num = -1; /* ignore 1st err */ | |
a4d7d550 KM |
338 | } |
339 | ||
93193c2b | 340 | static void fsi_stream_pop(struct fsi_priv *fsi, int is_play) |
a4d7d550 | 341 | { |
93193c2b | 342 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); |
1ec9bc35 KM |
343 | struct snd_soc_dai *dai = fsi_get_dai(io->substream); |
344 | ||
345 | ||
346 | if (io->oerr_num > 0) | |
347 | dev_err(dai->dev, "over_run = %d\n", io->oerr_num); | |
348 | ||
349 | if (io->uerr_num > 0) | |
350 | dev_err(dai->dev, "under_run = %d\n", io->uerr_num); | |
93193c2b KM |
351 | |
352 | io->substream = NULL; | |
353 | io->buff_len = 0; | |
354 | io->buff_offset = 0; | |
355 | io->period_len = 0; | |
356 | io->period_num = 0; | |
1ec9bc35 KM |
357 | io->oerr_num = 0; |
358 | io->uerr_num = 0; | |
a4d7d550 KM |
359 | } |
360 | ||
5bfb9ad0 | 361 | static int fsi_get_fifo_data_num(struct fsi_priv *fsi, int is_play) |
a4d7d550 KM |
362 | { |
363 | u32 status; | |
93193c2b | 364 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); |
5bfb9ad0 | 365 | int data_num; |
a4d7d550 | 366 | |
e8c8b631 KM |
367 | status = is_play ? |
368 | fsi_reg_read(fsi, DOFF_ST) : | |
369 | fsi_reg_read(fsi, DIFF_ST); | |
370 | ||
5bfb9ad0 | 371 | data_num = 0x1ff & (status >> 8); |
93193c2b | 372 | data_num *= io->chan_num; |
5bfb9ad0 KM |
373 | |
374 | return data_num; | |
375 | } | |
a4d7d550 | 376 | |
5bfb9ad0 KM |
377 | static int fsi_len2num(int len, int width) |
378 | { | |
379 | return len / width; | |
380 | } | |
381 | ||
382 | #define fsi_num2offset(a, b) fsi_num2len(a, b) | |
383 | static int fsi_num2len(int num, int width) | |
384 | { | |
385 | return num * width; | |
a4d7d550 KM |
386 | } |
387 | ||
93193c2b | 388 | static int fsi_get_frame_width(struct fsi_priv *fsi, int is_play) |
cca1b235 | 389 | { |
93193c2b KM |
390 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); |
391 | struct snd_pcm_substream *substream = io->substream; | |
cca1b235 KM |
392 | struct snd_pcm_runtime *runtime = substream->runtime; |
393 | ||
93193c2b | 394 | return frames_to_bytes(runtime, 1) / io->chan_num; |
cca1b235 KM |
395 | } |
396 | ||
1ec9bc35 KM |
397 | static void fsi_count_fifo_err(struct fsi_priv *fsi) |
398 | { | |
399 | u32 ostatus = fsi_reg_read(fsi, DOFF_ST); | |
400 | u32 istatus = fsi_reg_read(fsi, DIFF_ST); | |
401 | ||
402 | if (ostatus & ERR_OVER) | |
403 | fsi->playback.oerr_num++; | |
404 | ||
405 | if (ostatus & ERR_UNDER) | |
406 | fsi->playback.uerr_num++; | |
407 | ||
408 | if (istatus & ERR_OVER) | |
409 | fsi->capture.oerr_num++; | |
410 | ||
411 | if (istatus & ERR_UNDER) | |
412 | fsi->capture.uerr_num++; | |
413 | ||
414 | fsi_reg_write(fsi, DOFF_ST, 0); | |
415 | fsi_reg_write(fsi, DIFF_ST, 0); | |
416 | } | |
417 | ||
b9fde18c KM |
418 | /* |
419 | * dma function | |
420 | */ | |
421 | ||
93193c2b | 422 | static u8 *fsi_dma_get_area(struct fsi_priv *fsi, int stream) |
c79eab3e | 423 | { |
93193c2b KM |
424 | int is_play = fsi_stream_is_play(stream); |
425 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); | |
426 | ||
427 | return io->substream->runtime->dma_area + io->buff_offset; | |
c79eab3e KM |
428 | } |
429 | ||
5bfb9ad0 | 430 | static void fsi_dma_soft_push16(struct fsi_priv *fsi, int num) |
b9fde18c KM |
431 | { |
432 | u16 *start; | |
433 | int i; | |
434 | ||
93193c2b | 435 | start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK); |
b9fde18c | 436 | |
5bfb9ad0 | 437 | for (i = 0; i < num; i++) |
b9fde18c KM |
438 | fsi_reg_write(fsi, DODT, ((u32)*(start + i) << 8)); |
439 | } | |
440 | ||
5bfb9ad0 | 441 | static void fsi_dma_soft_pop16(struct fsi_priv *fsi, int num) |
b9fde18c KM |
442 | { |
443 | u16 *start; | |
444 | int i; | |
445 | ||
93193c2b KM |
446 | start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE); |
447 | ||
b9fde18c | 448 | |
5bfb9ad0 | 449 | for (i = 0; i < num; i++) |
b9fde18c KM |
450 | *(start + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8); |
451 | } | |
452 | ||
5bfb9ad0 | 453 | static void fsi_dma_soft_push32(struct fsi_priv *fsi, int num) |
b9fde18c KM |
454 | { |
455 | u32 *start; | |
456 | int i; | |
457 | ||
93193c2b KM |
458 | start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK); |
459 | ||
b9fde18c | 460 | |
5bfb9ad0 | 461 | for (i = 0; i < num; i++) |
b9fde18c KM |
462 | fsi_reg_write(fsi, DODT, *(start + i)); |
463 | } | |
464 | ||
5bfb9ad0 | 465 | static void fsi_dma_soft_pop32(struct fsi_priv *fsi, int num) |
b9fde18c KM |
466 | { |
467 | u32 *start; | |
468 | int i; | |
469 | ||
93193c2b | 470 | start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE); |
b9fde18c | 471 | |
5bfb9ad0 | 472 | for (i = 0; i < num; i++) |
b9fde18c KM |
473 | *(start + i) = fsi_reg_read(fsi, DIDT); |
474 | } | |
475 | ||
c8fe2574 KM |
476 | /* |
477 | * irq function | |
478 | */ | |
a4d7d550 | 479 | |
a4d7d550 KM |
480 | static void fsi_irq_enable(struct fsi_priv *fsi, int is_play) |
481 | { | |
cf6edd00 | 482 | u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play)); |
71f6e064 | 483 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 484 | |
43fa95ca KM |
485 | fsi_core_mask_set(master, imsk, data, data); |
486 | fsi_core_mask_set(master, iemsk, data, data); | |
a4d7d550 KM |
487 | } |
488 | ||
489 | static void fsi_irq_disable(struct fsi_priv *fsi, int is_play) | |
490 | { | |
cf6edd00 | 491 | u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play)); |
71f6e064 | 492 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 493 | |
43fa95ca KM |
494 | fsi_core_mask_set(master, imsk, data, 0); |
495 | fsi_core_mask_set(master, iemsk, data, 0); | |
a4d7d550 KM |
496 | } |
497 | ||
10ea76cc KM |
498 | static u32 fsi_irq_get_status(struct fsi_master *master) |
499 | { | |
43fa95ca | 500 | return fsi_core_read(master, int_st); |
10ea76cc KM |
501 | } |
502 | ||
10ea76cc KM |
503 | static void fsi_irq_clear_status(struct fsi_priv *fsi) |
504 | { | |
505 | u32 data = 0; | |
506 | struct fsi_master *master = fsi_get_master(fsi); | |
507 | ||
cf6edd00 KM |
508 | data |= AB_IO(1, fsi_get_port_shift(fsi, 0)); |
509 | data |= AB_IO(1, fsi_get_port_shift(fsi, 1)); | |
10ea76cc KM |
510 | |
511 | /* clear interrupt factor */ | |
43fa95ca | 512 | fsi_core_mask_set(master, int_st, data, 0); |
10ea76cc KM |
513 | } |
514 | ||
c8fe2574 KM |
515 | /* |
516 | * SPDIF master clock function | |
517 | * | |
518 | * These functions are used later FSI2 | |
519 | */ | |
3bc28070 KM |
520 | static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable) |
521 | { | |
522 | struct fsi_master *master = fsi_get_master(fsi); | |
2b0e7302 | 523 | u32 mask, val; |
3bc28070 KM |
524 | |
525 | if (master->core->ver < 2) { | |
526 | pr_err("fsi: register access err (%s)\n", __func__); | |
527 | return; | |
528 | } | |
529 | ||
2b0e7302 KM |
530 | mask = BP | SE; |
531 | val = enable ? mask : 0; | |
532 | ||
533 | fsi_is_port_a(fsi) ? | |
43fa95ca KM |
534 | fsi_core_mask_set(master, a_mclk, mask, val) : |
535 | fsi_core_mask_set(master, b_mclk, mask, val); | |
3bc28070 KM |
536 | } |
537 | ||
c8fe2574 KM |
538 | /* |
539 | * ctrl function | |
540 | */ | |
10ea76cc | 541 | |
a4d7d550 KM |
542 | static void fsi_clk_ctrl(struct fsi_priv *fsi, int enable) |
543 | { | |
544 | u32 val = fsi_is_port_a(fsi) ? (1 << 0) : (1 << 4); | |
71f6e064 | 545 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 KM |
546 | |
547 | if (enable) | |
71f6e064 | 548 | fsi_master_mask_set(master, CLK_RST, val, val); |
a4d7d550 | 549 | else |
71f6e064 | 550 | fsi_master_mask_set(master, CLK_RST, val, 0); |
a4d7d550 KM |
551 | } |
552 | ||
4a942b45 KM |
553 | static void fsi_fifo_init(struct fsi_priv *fsi, |
554 | int is_play, | |
555 | struct snd_soc_dai *dai) | |
a4d7d550 | 556 | { |
4a942b45 | 557 | struct fsi_master *master = fsi_get_master(fsi); |
93193c2b | 558 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); |
e8c8b631 | 559 | u32 shift, i; |
a4d7d550 | 560 | |
4a942b45 KM |
561 | /* get on-chip RAM capacity */ |
562 | shift = fsi_master_read(master, FIFO_SZ); | |
cf6edd00 KM |
563 | shift >>= fsi_get_port_shift(fsi, is_play); |
564 | shift &= FIFO_SZ_MASK; | |
93193c2b KM |
565 | io->fifo_max_num = 256 << shift; |
566 | dev_dbg(dai->dev, "fifo = %d words\n", io->fifo_max_num); | |
a4d7d550 | 567 | |
4a942b45 KM |
568 | /* |
569 | * The maximum number of sample data varies depending | |
570 | * on the number of channels selected for the format. | |
571 | * | |
572 | * FIFOs are used in 4-channel units in 3-channel mode | |
573 | * and in 8-channel units in 5- to 7-channel mode | |
574 | * meaning that more FIFOs than the required size of DPRAM | |
575 | * are used. | |
576 | * | |
577 | * ex) if 256 words of DP-RAM is connected | |
578 | * 1 channel: 256 (256 x 1 = 256) | |
579 | * 2 channels: 128 (128 x 2 = 256) | |
580 | * 3 channels: 64 ( 64 x 3 = 192) | |
581 | * 4 channels: 64 ( 64 x 4 = 256) | |
582 | * 5 channels: 32 ( 32 x 5 = 160) | |
583 | * 6 channels: 32 ( 32 x 6 = 192) | |
584 | * 7 channels: 32 ( 32 x 7 = 224) | |
585 | * 8 channels: 32 ( 32 x 8 = 256) | |
586 | */ | |
93193c2b KM |
587 | for (i = 1; i < io->chan_num; i <<= 1) |
588 | io->fifo_max_num >>= 1; | |
5bfb9ad0 | 589 | dev_dbg(dai->dev, "%d channel %d store\n", |
93193c2b | 590 | io->chan_num, io->fifo_max_num); |
a4d7d550 | 591 | |
e8c8b631 KM |
592 | /* |
593 | * set interrupt generation factor | |
594 | * clear FIFO | |
595 | */ | |
596 | if (is_play) { | |
597 | fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF); | |
598 | fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR); | |
599 | } else { | |
600 | fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF); | |
601 | fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR); | |
602 | } | |
a4d7d550 KM |
603 | } |
604 | ||
71f6e064 | 605 | static void fsi_soft_all_reset(struct fsi_master *master) |
a4d7d550 | 606 | { |
a4d7d550 | 607 | /* port AB reset */ |
feb58cff | 608 | fsi_master_mask_set(master, SOFT_RST, PASR | PBSR, 0); |
a4d7d550 KM |
609 | mdelay(10); |
610 | ||
611 | /* soft reset */ | |
feb58cff KM |
612 | fsi_master_mask_set(master, SOFT_RST, FSISR, 0); |
613 | fsi_master_mask_set(master, SOFT_RST, FSISR, FSISR); | |
a4d7d550 KM |
614 | mdelay(10); |
615 | } | |
616 | ||
1ec9bc35 | 617 | static int fsi_fifo_data_ctrl(struct fsi_priv *fsi, int stream) |
a4d7d550 KM |
618 | { |
619 | struct snd_pcm_runtime *runtime; | |
620 | struct snd_pcm_substream *substream = NULL; | |
93193c2b KM |
621 | int is_play = fsi_stream_is_play(stream); |
622 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); | |
d8b33534 KM |
623 | int data_residue_num; |
624 | int data_num; | |
625 | int data_num_max; | |
5bfb9ad0 | 626 | int ch_width; |
b9fde18c | 627 | int over_period; |
d8b33534 | 628 | void (*fn)(struct fsi_priv *fsi, int size); |
a4d7d550 KM |
629 | |
630 | if (!fsi || | |
93193c2b KM |
631 | !io->substream || |
632 | !io->substream->runtime) | |
a4d7d550 KM |
633 | return -EINVAL; |
634 | ||
1c418d1f | 635 | over_period = 0; |
93193c2b | 636 | substream = io->substream; |
1c418d1f | 637 | runtime = substream->runtime; |
a4d7d550 KM |
638 | |
639 | /* FSI FIFO has limit. | |
640 | * So, this driver can not send periods data at a time | |
641 | */ | |
93193c2b KM |
642 | if (io->buff_offset >= |
643 | fsi_num2offset(io->period_num + 1, io->period_len)) { | |
a4d7d550 | 644 | |
1c418d1f | 645 | over_period = 1; |
93193c2b | 646 | io->period_num = (io->period_num + 1) % runtime->periods; |
a4d7d550 | 647 | |
93193c2b KM |
648 | if (0 == io->period_num) |
649 | io->buff_offset = 0; | |
a4d7d550 KM |
650 | } |
651 | ||
652 | /* get 1 channel data width */ | |
93193c2b | 653 | ch_width = fsi_get_frame_width(fsi, is_play); |
a4d7d550 | 654 | |
d8b33534 | 655 | /* get residue data number of alsa */ |
93193c2b | 656 | data_residue_num = fsi_len2num(io->buff_len - io->buff_offset, |
d8b33534 KM |
657 | ch_width); |
658 | ||
659 | if (is_play) { | |
660 | /* | |
661 | * for play-back | |
662 | * | |
663 | * data_num_max : number of FSI fifo free space | |
664 | * data_num : number of ALSA residue data | |
665 | */ | |
93193c2b | 666 | data_num_max = io->fifo_max_num * io->chan_num; |
d8b33534 KM |
667 | data_num_max -= fsi_get_fifo_data_num(fsi, is_play); |
668 | ||
669 | data_num = data_residue_num; | |
670 | ||
671 | switch (ch_width) { | |
672 | case 2: | |
673 | fn = fsi_dma_soft_push16; | |
674 | break; | |
675 | case 4: | |
676 | fn = fsi_dma_soft_push32; | |
677 | break; | |
678 | default: | |
679 | return -EINVAL; | |
680 | } | |
681 | } else { | |
682 | /* | |
683 | * for capture | |
684 | * | |
685 | * data_num_max : number of ALSA free space | |
686 | * data_num : number of data in FSI fifo | |
687 | */ | |
688 | data_num_max = data_residue_num; | |
689 | data_num = fsi_get_fifo_data_num(fsi, is_play); | |
690 | ||
691 | switch (ch_width) { | |
692 | case 2: | |
693 | fn = fsi_dma_soft_pop16; | |
694 | break; | |
695 | case 4: | |
696 | fn = fsi_dma_soft_pop32; | |
697 | break; | |
698 | default: | |
699 | return -EINVAL; | |
700 | } | |
701 | } | |
a4d7d550 | 702 | |
d8b33534 | 703 | data_num = min(data_num, data_num_max); |
a4d7d550 | 704 | |
d8b33534 | 705 | fn(fsi, data_num); |
a4d7d550 | 706 | |
d8b33534 | 707 | /* update buff_offset */ |
93193c2b | 708 | io->buff_offset += fsi_num2offset(data_num, ch_width); |
a4d7d550 | 709 | |
1c418d1f | 710 | if (over_period) |
a4d7d550 KM |
711 | snd_pcm_period_elapsed(substream); |
712 | ||
47fc9a0a | 713 | return 0; |
a4d7d550 KM |
714 | } |
715 | ||
1ec9bc35 | 716 | static int fsi_data_pop(struct fsi_priv *fsi) |
07102f3c | 717 | { |
1ec9bc35 | 718 | return fsi_fifo_data_ctrl(fsi, SNDRV_PCM_STREAM_CAPTURE); |
d8b33534 | 719 | } |
07102f3c | 720 | |
1ec9bc35 | 721 | static int fsi_data_push(struct fsi_priv *fsi) |
d8b33534 | 722 | { |
1ec9bc35 | 723 | return fsi_fifo_data_ctrl(fsi, SNDRV_PCM_STREAM_PLAYBACK); |
07102f3c KM |
724 | } |
725 | ||
a4d7d550 KM |
726 | static irqreturn_t fsi_interrupt(int irq, void *data) |
727 | { | |
71f6e064 | 728 | struct fsi_master *master = data; |
10ea76cc | 729 | u32 int_st = fsi_irq_get_status(master); |
a4d7d550 KM |
730 | |
731 | /* clear irq status */ | |
feb58cff KM |
732 | fsi_master_mask_set(master, SOFT_RST, IR, 0); |
733 | fsi_master_mask_set(master, SOFT_RST, IR, IR); | |
a4d7d550 | 734 | |
cf6edd00 | 735 | if (int_st & AB_IO(1, AO_SHIFT)) |
1ec9bc35 | 736 | fsi_data_push(&master->fsia); |
cf6edd00 | 737 | if (int_st & AB_IO(1, BO_SHIFT)) |
1ec9bc35 | 738 | fsi_data_push(&master->fsib); |
cf6edd00 | 739 | if (int_st & AB_IO(1, AI_SHIFT)) |
1ec9bc35 | 740 | fsi_data_pop(&master->fsia); |
cf6edd00 | 741 | if (int_st & AB_IO(1, BI_SHIFT)) |
1ec9bc35 KM |
742 | fsi_data_pop(&master->fsib); |
743 | ||
744 | fsi_count_fifo_err(&master->fsia); | |
745 | fsi_count_fifo_err(&master->fsib); | |
a4d7d550 | 746 | |
48d78e58 KM |
747 | fsi_irq_clear_status(&master->fsia); |
748 | fsi_irq_clear_status(&master->fsib); | |
a4d7d550 KM |
749 | |
750 | return IRQ_HANDLED; | |
751 | } | |
752 | ||
c8fe2574 KM |
753 | /* |
754 | * dai ops | |
755 | */ | |
a4d7d550 | 756 | |
a4d7d550 KM |
757 | static int fsi_dai_startup(struct snd_pcm_substream *substream, |
758 | struct snd_soc_dai *dai) | |
759 | { | |
71f6e064 | 760 | struct fsi_priv *fsi = fsi_get_priv(substream); |
3bc28070 | 761 | struct fsi_master *master = fsi_get_master(fsi); |
93193c2b KM |
762 | struct fsi_stream *io; |
763 | u32 flags = fsi_get_info_flags(fsi); | |
a4d7d550 | 764 | u32 fmt; |
a4d7d550 | 765 | u32 data; |
00545785 | 766 | int is_play = fsi_is_play(substream); |
a4d7d550 | 767 | int is_master; |
a4d7d550 | 768 | |
93193c2b KM |
769 | io = fsi_get_stream(fsi, is_play); |
770 | ||
785d1c45 | 771 | pm_runtime_get_sync(dai->dev); |
a4d7d550 KM |
772 | |
773 | /* CKG1 */ | |
774 | data = is_play ? (1 << 0) : (1 << 4); | |
775 | is_master = fsi_is_master_mode(fsi, is_play); | |
776 | if (is_master) | |
777 | fsi_reg_mask_set(fsi, CKG1, data, data); | |
778 | else | |
779 | fsi_reg_mask_set(fsi, CKG1, data, 0); | |
780 | ||
781 | /* clock inversion (CKG2) */ | |
782 | data = 0; | |
b427b44c KM |
783 | if (SH_FSI_LRM_INV & flags) |
784 | data |= 1 << 12; | |
785 | if (SH_FSI_BRM_INV & flags) | |
786 | data |= 1 << 8; | |
787 | if (SH_FSI_LRS_INV & flags) | |
788 | data |= 1 << 4; | |
789 | if (SH_FSI_BRS_INV & flags) | |
790 | data |= 1 << 0; | |
791 | ||
a4d7d550 KM |
792 | fsi_reg_write(fsi, CKG2, data); |
793 | ||
794 | /* do fmt, di fmt */ | |
795 | data = 0; | |
a4d7d550 KM |
796 | fmt = is_play ? SH_FSI_GET_OFMT(flags) : SH_FSI_GET_IFMT(flags); |
797 | switch (fmt) { | |
798 | case SH_FSI_FMT_MONO: | |
a7ffb52b | 799 | data = CR_MONO; |
93193c2b | 800 | io->chan_num = 1; |
a4d7d550 KM |
801 | break; |
802 | case SH_FSI_FMT_MONO_DELAY: | |
a7ffb52b | 803 | data = CR_MONO_D; |
93193c2b | 804 | io->chan_num = 1; |
a4d7d550 KM |
805 | break; |
806 | case SH_FSI_FMT_PCM: | |
a7ffb52b | 807 | data = CR_PCM; |
93193c2b | 808 | io->chan_num = 2; |
a4d7d550 KM |
809 | break; |
810 | case SH_FSI_FMT_I2S: | |
a7ffb52b | 811 | data = CR_I2S; |
93193c2b | 812 | io->chan_num = 2; |
a4d7d550 KM |
813 | break; |
814 | case SH_FSI_FMT_TDM: | |
93193c2b | 815 | io->chan_num = is_play ? |
a4d7d550 | 816 | SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags); |
93193c2b | 817 | data = CR_TDM | (io->chan_num - 1); |
a4d7d550 KM |
818 | break; |
819 | case SH_FSI_FMT_TDM_DELAY: | |
93193c2b | 820 | io->chan_num = is_play ? |
a4d7d550 | 821 | SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags); |
93193c2b | 822 | data = CR_TDM_D | (io->chan_num - 1); |
a4d7d550 | 823 | break; |
3bc28070 KM |
824 | case SH_FSI_FMT_SPDIF: |
825 | if (master->core->ver < 2) { | |
826 | dev_err(dai->dev, "This FSI can not use SPDIF\n"); | |
827 | return -EINVAL; | |
828 | } | |
f7d711e3 | 829 | data = CR_BWS_16 | CR_DTMD_SPDIF_PCM | CR_PCM; |
93193c2b | 830 | io->chan_num = 2; |
3bc28070 | 831 | fsi_spdif_clk_ctrl(fsi, 1); |
f7d711e3 | 832 | fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD); |
3bc28070 | 833 | break; |
a4d7d550 KM |
834 | default: |
835 | dev_err(dai->dev, "unknown format.\n"); | |
836 | return -EINVAL; | |
837 | } | |
e8c8b631 KM |
838 | is_play ? |
839 | fsi_reg_write(fsi, DO_FMT, data) : | |
840 | fsi_reg_write(fsi, DI_FMT, data); | |
a4d7d550 | 841 | |
10ea76cc KM |
842 | /* irq clear */ |
843 | fsi_irq_disable(fsi, is_play); | |
844 | fsi_irq_clear_status(fsi); | |
845 | ||
846 | /* fifo init */ | |
4a942b45 | 847 | fsi_fifo_init(fsi, is_play, dai); |
a4d7d550 | 848 | |
a68a3b4e | 849 | return 0; |
a4d7d550 KM |
850 | } |
851 | ||
852 | static void fsi_dai_shutdown(struct snd_pcm_substream *substream, | |
853 | struct snd_soc_dai *dai) | |
854 | { | |
71f6e064 | 855 | struct fsi_priv *fsi = fsi_get_priv(substream); |
00545785 | 856 | int is_play = fsi_is_play(substream); |
d4bc99b9 KM |
857 | struct fsi_master *master = fsi_get_master(fsi); |
858 | int (*set_rate)(struct device *dev, int is_porta, int rate, int enable); | |
a4d7d550 KM |
859 | |
860 | fsi_irq_disable(fsi, is_play); | |
861 | fsi_clk_ctrl(fsi, 0); | |
862 | ||
d4bc99b9 KM |
863 | set_rate = master->info->set_rate; |
864 | if (set_rate && fsi->rate) | |
865 | set_rate(dai->dev, fsi_is_port_a(fsi), fsi->rate, 0); | |
866 | fsi->rate = 0; | |
867 | ||
785d1c45 | 868 | pm_runtime_put_sync(dai->dev); |
a4d7d550 KM |
869 | } |
870 | ||
871 | static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd, | |
872 | struct snd_soc_dai *dai) | |
873 | { | |
71f6e064 | 874 | struct fsi_priv *fsi = fsi_get_priv(substream); |
a4d7d550 | 875 | struct snd_pcm_runtime *runtime = substream->runtime; |
00545785 | 876 | int is_play = fsi_is_play(substream); |
a4d7d550 KM |
877 | int ret = 0; |
878 | ||
a4d7d550 KM |
879 | switch (cmd) { |
880 | case SNDRV_PCM_TRIGGER_START: | |
93193c2b | 881 | fsi_stream_push(fsi, is_play, substream, |
a4d7d550 KM |
882 | frames_to_bytes(runtime, runtime->buffer_size), |
883 | frames_to_bytes(runtime, runtime->period_size)); | |
1ec9bc35 | 884 | ret = is_play ? fsi_data_push(fsi) : fsi_data_pop(fsi); |
9e261bbc | 885 | fsi_irq_enable(fsi, is_play); |
a4d7d550 KM |
886 | break; |
887 | case SNDRV_PCM_TRIGGER_STOP: | |
888 | fsi_irq_disable(fsi, is_play); | |
93193c2b | 889 | fsi_stream_pop(fsi, is_play); |
a4d7d550 KM |
890 | break; |
891 | } | |
892 | ||
893 | return ret; | |
894 | } | |
895 | ||
ccad7b44 KM |
896 | static int fsi_dai_hw_params(struct snd_pcm_substream *substream, |
897 | struct snd_pcm_hw_params *params, | |
898 | struct snd_soc_dai *dai) | |
899 | { | |
900 | struct fsi_priv *fsi = fsi_get_priv(substream); | |
901 | struct fsi_master *master = fsi_get_master(fsi); | |
d4bc99b9 | 902 | int (*set_rate)(struct device *dev, int is_porta, int rate, int enable); |
ccad7b44 | 903 | int fsi_ver = master->core->ver; |
d4bc99b9 | 904 | long rate = params_rate(params); |
ccad7b44 KM |
905 | int ret; |
906 | ||
d4bc99b9 | 907 | set_rate = master->info->set_rate; |
ccad7b44 | 908 | if (!set_rate) |
ccad7b44 KM |
909 | return 0; |
910 | ||
d4bc99b9 KM |
911 | ret = set_rate(dai->dev, fsi_is_port_a(fsi), rate, 1); |
912 | if (ret < 0) /* error */ | |
913 | return ret; | |
ccad7b44 | 914 | |
d4bc99b9 | 915 | fsi->rate = rate; |
ccad7b44 KM |
916 | if (ret > 0) { |
917 | u32 data = 0; | |
918 | ||
919 | switch (ret & SH_FSI_ACKMD_MASK) { | |
920 | default: | |
921 | /* FALL THROUGH */ | |
922 | case SH_FSI_ACKMD_512: | |
923 | data |= (0x0 << 12); | |
924 | break; | |
925 | case SH_FSI_ACKMD_256: | |
926 | data |= (0x1 << 12); | |
927 | break; | |
928 | case SH_FSI_ACKMD_128: | |
929 | data |= (0x2 << 12); | |
930 | break; | |
931 | case SH_FSI_ACKMD_64: | |
932 | data |= (0x3 << 12); | |
933 | break; | |
934 | case SH_FSI_ACKMD_32: | |
935 | if (fsi_ver < 2) | |
936 | dev_err(dai->dev, "unsupported ACKMD\n"); | |
937 | else | |
938 | data |= (0x4 << 12); | |
939 | break; | |
940 | } | |
941 | ||
942 | switch (ret & SH_FSI_BPFMD_MASK) { | |
943 | default: | |
944 | /* FALL THROUGH */ | |
945 | case SH_FSI_BPFMD_32: | |
946 | data |= (0x0 << 8); | |
947 | break; | |
948 | case SH_FSI_BPFMD_64: | |
949 | data |= (0x1 << 8); | |
950 | break; | |
951 | case SH_FSI_BPFMD_128: | |
952 | data |= (0x2 << 8); | |
953 | break; | |
954 | case SH_FSI_BPFMD_256: | |
955 | data |= (0x3 << 8); | |
956 | break; | |
957 | case SH_FSI_BPFMD_512: | |
958 | data |= (0x4 << 8); | |
959 | break; | |
960 | case SH_FSI_BPFMD_16: | |
961 | if (fsi_ver < 2) | |
962 | dev_err(dai->dev, "unsupported ACKMD\n"); | |
963 | else | |
964 | data |= (0x7 << 8); | |
965 | break; | |
966 | } | |
967 | ||
968 | fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data); | |
969 | udelay(10); | |
970 | fsi_clk_ctrl(fsi, 1); | |
971 | ret = 0; | |
972 | } | |
ccad7b44 KM |
973 | |
974 | return ret; | |
975 | ||
976 | } | |
977 | ||
a4d7d550 KM |
978 | static struct snd_soc_dai_ops fsi_dai_ops = { |
979 | .startup = fsi_dai_startup, | |
980 | .shutdown = fsi_dai_shutdown, | |
981 | .trigger = fsi_dai_trigger, | |
ccad7b44 | 982 | .hw_params = fsi_dai_hw_params, |
a4d7d550 KM |
983 | }; |
984 | ||
c8fe2574 KM |
985 | /* |
986 | * pcm ops | |
987 | */ | |
a4d7d550 | 988 | |
a4d7d550 KM |
989 | static struct snd_pcm_hardware fsi_pcm_hardware = { |
990 | .info = SNDRV_PCM_INFO_INTERLEAVED | | |
991 | SNDRV_PCM_INFO_MMAP | | |
992 | SNDRV_PCM_INFO_MMAP_VALID | | |
993 | SNDRV_PCM_INFO_PAUSE, | |
994 | .formats = FSI_FMTS, | |
995 | .rates = FSI_RATES, | |
996 | .rate_min = 8000, | |
997 | .rate_max = 192000, | |
998 | .channels_min = 1, | |
999 | .channels_max = 2, | |
1000 | .buffer_bytes_max = 64 * 1024, | |
1001 | .period_bytes_min = 32, | |
1002 | .period_bytes_max = 8192, | |
1003 | .periods_min = 1, | |
1004 | .periods_max = 32, | |
1005 | .fifo_size = 256, | |
1006 | }; | |
1007 | ||
1008 | static int fsi_pcm_open(struct snd_pcm_substream *substream) | |
1009 | { | |
1010 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1011 | int ret = 0; | |
1012 | ||
1013 | snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware); | |
1014 | ||
1015 | ret = snd_pcm_hw_constraint_integer(runtime, | |
1016 | SNDRV_PCM_HW_PARAM_PERIODS); | |
1017 | ||
1018 | return ret; | |
1019 | } | |
1020 | ||
1021 | static int fsi_hw_params(struct snd_pcm_substream *substream, | |
1022 | struct snd_pcm_hw_params *hw_params) | |
1023 | { | |
1024 | return snd_pcm_lib_malloc_pages(substream, | |
1025 | params_buffer_bytes(hw_params)); | |
1026 | } | |
1027 | ||
1028 | static int fsi_hw_free(struct snd_pcm_substream *substream) | |
1029 | { | |
1030 | return snd_pcm_lib_free_pages(substream); | |
1031 | } | |
1032 | ||
1033 | static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream) | |
1034 | { | |
1035 | struct snd_pcm_runtime *runtime = substream->runtime; | |
71f6e064 | 1036 | struct fsi_priv *fsi = fsi_get_priv(substream); |
93193c2b | 1037 | struct fsi_stream *io = fsi_get_stream(fsi, fsi_is_play(substream)); |
a4d7d550 KM |
1038 | long location; |
1039 | ||
93193c2b | 1040 | location = (io->buff_offset - 1); |
a4d7d550 KM |
1041 | if (location < 0) |
1042 | location = 0; | |
1043 | ||
1044 | return bytes_to_frames(runtime, location); | |
1045 | } | |
1046 | ||
1047 | static struct snd_pcm_ops fsi_pcm_ops = { | |
1048 | .open = fsi_pcm_open, | |
1049 | .ioctl = snd_pcm_lib_ioctl, | |
1050 | .hw_params = fsi_hw_params, | |
1051 | .hw_free = fsi_hw_free, | |
1052 | .pointer = fsi_pointer, | |
1053 | }; | |
1054 | ||
c8fe2574 KM |
1055 | /* |
1056 | * snd_soc_platform | |
1057 | */ | |
a4d7d550 | 1058 | |
a4d7d550 KM |
1059 | #define PREALLOC_BUFFER (32 * 1024) |
1060 | #define PREALLOC_BUFFER_MAX (32 * 1024) | |
1061 | ||
1062 | static void fsi_pcm_free(struct snd_pcm *pcm) | |
1063 | { | |
1064 | snd_pcm_lib_preallocate_free_for_all(pcm); | |
1065 | } | |
1066 | ||
1067 | static int fsi_pcm_new(struct snd_card *card, | |
1068 | struct snd_soc_dai *dai, | |
1069 | struct snd_pcm *pcm) | |
1070 | { | |
1071 | /* | |
1072 | * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel | |
1073 | * in MMAP mode (i.e. aplay -M) | |
1074 | */ | |
1075 | return snd_pcm_lib_preallocate_pages_for_all( | |
1076 | pcm, | |
1077 | SNDRV_DMA_TYPE_CONTINUOUS, | |
1078 | snd_dma_continuous_data(GFP_KERNEL), | |
1079 | PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); | |
1080 | } | |
1081 | ||
c8fe2574 KM |
1082 | /* |
1083 | * alsa struct | |
1084 | */ | |
a4d7d550 | 1085 | |
f0fba2ad | 1086 | static struct snd_soc_dai_driver fsi_soc_dai[] = { |
a4d7d550 | 1087 | { |
f0fba2ad | 1088 | .name = "fsia-dai", |
a4d7d550 KM |
1089 | .playback = { |
1090 | .rates = FSI_RATES, | |
1091 | .formats = FSI_FMTS, | |
1092 | .channels_min = 1, | |
1093 | .channels_max = 8, | |
1094 | }, | |
07102f3c KM |
1095 | .capture = { |
1096 | .rates = FSI_RATES, | |
1097 | .formats = FSI_FMTS, | |
1098 | .channels_min = 1, | |
1099 | .channels_max = 8, | |
1100 | }, | |
a4d7d550 KM |
1101 | .ops = &fsi_dai_ops, |
1102 | }, | |
1103 | { | |
f0fba2ad | 1104 | .name = "fsib-dai", |
a4d7d550 KM |
1105 | .playback = { |
1106 | .rates = FSI_RATES, | |
1107 | .formats = FSI_FMTS, | |
1108 | .channels_min = 1, | |
1109 | .channels_max = 8, | |
1110 | }, | |
07102f3c KM |
1111 | .capture = { |
1112 | .rates = FSI_RATES, | |
1113 | .formats = FSI_FMTS, | |
1114 | .channels_min = 1, | |
1115 | .channels_max = 8, | |
1116 | }, | |
a4d7d550 KM |
1117 | .ops = &fsi_dai_ops, |
1118 | }, | |
1119 | }; | |
a4d7d550 | 1120 | |
f0fba2ad LG |
1121 | static struct snd_soc_platform_driver fsi_soc_platform = { |
1122 | .ops = &fsi_pcm_ops, | |
a4d7d550 KM |
1123 | .pcm_new = fsi_pcm_new, |
1124 | .pcm_free = fsi_pcm_free, | |
1125 | }; | |
a4d7d550 | 1126 | |
c8fe2574 KM |
1127 | /* |
1128 | * platform function | |
1129 | */ | |
a4d7d550 | 1130 | |
a4d7d550 KM |
1131 | static int fsi_probe(struct platform_device *pdev) |
1132 | { | |
71f6e064 | 1133 | struct fsi_master *master; |
cc780d38 | 1134 | const struct platform_device_id *id_entry; |
a4d7d550 | 1135 | struct resource *res; |
a4d7d550 KM |
1136 | unsigned int irq; |
1137 | int ret; | |
1138 | ||
cc780d38 KM |
1139 | id_entry = pdev->id_entry; |
1140 | if (!id_entry) { | |
1141 | dev_err(&pdev->dev, "unknown fsi device\n"); | |
1142 | return -ENODEV; | |
1143 | } | |
1144 | ||
a4d7d550 KM |
1145 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1146 | irq = platform_get_irq(pdev, 0); | |
b6aa1793 | 1147 | if (!res || (int)irq <= 0) { |
a4d7d550 KM |
1148 | dev_err(&pdev->dev, "Not enough FSI platform resources.\n"); |
1149 | ret = -ENODEV; | |
1150 | goto exit; | |
1151 | } | |
1152 | ||
1153 | master = kzalloc(sizeof(*master), GFP_KERNEL); | |
1154 | if (!master) { | |
1155 | dev_err(&pdev->dev, "Could not allocate master\n"); | |
1156 | ret = -ENOMEM; | |
1157 | goto exit; | |
1158 | } | |
1159 | ||
1160 | master->base = ioremap_nocache(res->start, resource_size(res)); | |
1161 | if (!master->base) { | |
1162 | ret = -ENXIO; | |
1163 | dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n"); | |
1164 | goto exit_kfree; | |
1165 | } | |
1166 | ||
3bc28070 | 1167 | /* master setting */ |
a4d7d550 KM |
1168 | master->irq = irq; |
1169 | master->info = pdev->dev.platform_data; | |
3bc28070 KM |
1170 | master->core = (struct fsi_core *)id_entry->driver_data; |
1171 | spin_lock_init(&master->lock); | |
1172 | ||
1173 | /* FSI A setting */ | |
a4d7d550 | 1174 | master->fsia.base = master->base; |
71f6e064 | 1175 | master->fsia.master = master; |
3bc28070 KM |
1176 | |
1177 | /* FSI B setting */ | |
a4d7d550 | 1178 | master->fsib.base = master->base + 0x40; |
71f6e064 | 1179 | master->fsib.master = master; |
a4d7d550 | 1180 | |
785d1c45 KM |
1181 | pm_runtime_enable(&pdev->dev); |
1182 | pm_runtime_resume(&pdev->dev); | |
f0fba2ad | 1183 | dev_set_drvdata(&pdev->dev, master); |
a4d7d550 | 1184 | |
71f6e064 | 1185 | fsi_soft_all_reset(master); |
a4d7d550 | 1186 | |
cc780d38 KM |
1187 | ret = request_irq(irq, &fsi_interrupt, IRQF_DISABLED, |
1188 | id_entry->name, master); | |
a4d7d550 KM |
1189 | if (ret) { |
1190 | dev_err(&pdev->dev, "irq request err\n"); | |
9ddc9aa9 | 1191 | goto exit_iounmap; |
a4d7d550 KM |
1192 | } |
1193 | ||
f0fba2ad | 1194 | ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform); |
a4d7d550 KM |
1195 | if (ret < 0) { |
1196 | dev_err(&pdev->dev, "cannot snd soc register\n"); | |
1197 | goto exit_free_irq; | |
1198 | } | |
1199 | ||
f0fba2ad | 1200 | return snd_soc_register_dais(&pdev->dev, fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai)); |
a4d7d550 KM |
1201 | |
1202 | exit_free_irq: | |
1203 | free_irq(irq, master); | |
a4d7d550 KM |
1204 | exit_iounmap: |
1205 | iounmap(master->base); | |
785d1c45 | 1206 | pm_runtime_disable(&pdev->dev); |
a4d7d550 KM |
1207 | exit_kfree: |
1208 | kfree(master); | |
1209 | master = NULL; | |
1210 | exit: | |
1211 | return ret; | |
1212 | } | |
1213 | ||
1214 | static int fsi_remove(struct platform_device *pdev) | |
1215 | { | |
71f6e064 KM |
1216 | struct fsi_master *master; |
1217 | ||
f0fba2ad | 1218 | master = dev_get_drvdata(&pdev->dev); |
71f6e064 | 1219 | |
f0fba2ad LG |
1220 | snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(fsi_soc_dai)); |
1221 | snd_soc_unregister_platform(&pdev->dev); | |
a4d7d550 | 1222 | |
785d1c45 | 1223 | pm_runtime_disable(&pdev->dev); |
a4d7d550 | 1224 | |
a4d7d550 KM |
1225 | free_irq(master->irq, master); |
1226 | ||
1227 | iounmap(master->base); | |
1228 | kfree(master); | |
71f6e064 | 1229 | |
a4d7d550 KM |
1230 | return 0; |
1231 | } | |
1232 | ||
785d1c45 KM |
1233 | static int fsi_runtime_nop(struct device *dev) |
1234 | { | |
1235 | /* Runtime PM callback shared between ->runtime_suspend() | |
1236 | * and ->runtime_resume(). Simply returns success. | |
1237 | * | |
1238 | * This driver re-initializes all registers after | |
1239 | * pm_runtime_get_sync() anyway so there is no need | |
1240 | * to save and restore registers here. | |
1241 | */ | |
1242 | return 0; | |
1243 | } | |
1244 | ||
1245 | static struct dev_pm_ops fsi_pm_ops = { | |
1246 | .runtime_suspend = fsi_runtime_nop, | |
1247 | .runtime_resume = fsi_runtime_nop, | |
1248 | }; | |
1249 | ||
73b92c1f KM |
1250 | static struct fsi_core fsi1_core = { |
1251 | .ver = 1, | |
1252 | ||
1253 | /* Interrupt */ | |
cc780d38 KM |
1254 | .int_st = INT_ST, |
1255 | .iemsk = IEMSK, | |
1256 | .imsk = IMSK, | |
1257 | }; | |
1258 | ||
73b92c1f KM |
1259 | static struct fsi_core fsi2_core = { |
1260 | .ver = 2, | |
1261 | ||
1262 | /* Interrupt */ | |
cc780d38 KM |
1263 | .int_st = CPU_INT_ST, |
1264 | .iemsk = CPU_IEMSK, | |
1265 | .imsk = CPU_IMSK, | |
2b0e7302 KM |
1266 | .a_mclk = A_MST_CTLR, |
1267 | .b_mclk = B_MST_CTLR, | |
cc780d38 KM |
1268 | }; |
1269 | ||
1270 | static struct platform_device_id fsi_id_table[] = { | |
73b92c1f KM |
1271 | { "sh_fsi", (kernel_ulong_t)&fsi1_core }, |
1272 | { "sh_fsi2", (kernel_ulong_t)&fsi2_core }, | |
05c69450 | 1273 | {}, |
cc780d38 | 1274 | }; |
d85a6d7b | 1275 | MODULE_DEVICE_TABLE(platform, fsi_id_table); |
cc780d38 | 1276 | |
a4d7d550 KM |
1277 | static struct platform_driver fsi_driver = { |
1278 | .driver = { | |
f0fba2ad | 1279 | .name = "fsi-pcm-audio", |
785d1c45 | 1280 | .pm = &fsi_pm_ops, |
a4d7d550 KM |
1281 | }, |
1282 | .probe = fsi_probe, | |
1283 | .remove = fsi_remove, | |
cc780d38 | 1284 | .id_table = fsi_id_table, |
a4d7d550 KM |
1285 | }; |
1286 | ||
1287 | static int __init fsi_mobile_init(void) | |
1288 | { | |
1289 | return platform_driver_register(&fsi_driver); | |
1290 | } | |
1291 | ||
1292 | static void __exit fsi_mobile_exit(void) | |
1293 | { | |
1294 | platform_driver_unregister(&fsi_driver); | |
1295 | } | |
d85a6d7b | 1296 | |
a4d7d550 KM |
1297 | module_init(fsi_mobile_init); |
1298 | module_exit(fsi_mobile_exit); | |
1299 | ||
1300 | MODULE_LICENSE("GPL"); | |
1301 | MODULE_DESCRIPTION("SuperH onchip FSI audio driver"); | |
1302 | MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>"); |