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a4d7d550 KM |
1 | /* |
2 | * Fifo-attached Serial Interface (FSI) support for SH7724 | |
3 | * | |
4 | * Copyright (C) 2009 Renesas Solutions Corp. | |
5 | * Kuninori Morimoto <morimoto.kuninori@renesas.com> | |
6 | * | |
7 | * Based on ssi.c | |
8 | * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include <linux/init.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/list.h> | |
785d1c45 | 20 | #include <linux/pm_runtime.h> |
a4d7d550 KM |
21 | #include <linux/io.h> |
22 | #include <sound/core.h> | |
23 | #include <sound/pcm.h> | |
24 | #include <sound/initval.h> | |
25 | #include <sound/soc.h> | |
26 | #include <sound/pcm_params.h> | |
27 | #include <sound/sh_fsi.h> | |
28 | #include <asm/atomic.h> | |
a4d7d550 KM |
29 | |
30 | #define DO_FMT 0x0000 | |
31 | #define DOFF_CTL 0x0004 | |
32 | #define DOFF_ST 0x0008 | |
33 | #define DI_FMT 0x000C | |
34 | #define DIFF_CTL 0x0010 | |
35 | #define DIFF_ST 0x0014 | |
36 | #define CKG1 0x0018 | |
37 | #define CKG2 0x001C | |
38 | #define DIDT 0x0020 | |
39 | #define DODT 0x0024 | |
40 | #define MUTE_ST 0x0028 | |
41 | #define REG_END MUTE_ST | |
42 | ||
43 | #define INT_ST 0x0200 | |
44 | #define IEMSK 0x0204 | |
45 | #define IMSK 0x0208 | |
46 | #define MUTE 0x020C | |
47 | #define CLK_RST 0x0210 | |
48 | #define SOFT_RST 0x0214 | |
49 | #define MREG_START INT_ST | |
50 | #define MREG_END SOFT_RST | |
51 | ||
52 | /* DO_FMT */ | |
53 | /* DI_FMT */ | |
54 | #define CR_FMT(param) ((param) << 4) | |
55 | # define CR_MONO 0x0 | |
56 | # define CR_MONO_D 0x1 | |
57 | # define CR_PCM 0x2 | |
58 | # define CR_I2S 0x3 | |
59 | # define CR_TDM 0x4 | |
60 | # define CR_TDM_D 0x5 | |
61 | ||
62 | /* DOFF_CTL */ | |
63 | /* DIFF_CTL */ | |
64 | #define IRQ_HALF 0x00100000 | |
65 | #define FIFO_CLR 0x00000001 | |
66 | ||
67 | /* DOFF_ST */ | |
68 | #define ERR_OVER 0x00000010 | |
69 | #define ERR_UNDER 0x00000001 | |
70 | ||
71 | /* CLK_RST */ | |
72 | #define B_CLK 0x00000010 | |
73 | #define A_CLK 0x00000001 | |
74 | ||
75 | /* INT_ST */ | |
76 | #define INT_B_IN (1 << 12) | |
77 | #define INT_B_OUT (1 << 8) | |
78 | #define INT_A_IN (1 << 4) | |
79 | #define INT_A_OUT (1 << 0) | |
80 | ||
81 | #define FSI_RATES SNDRV_PCM_RATE_8000_96000 | |
82 | ||
83 | #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE) | |
84 | ||
85 | /************************************************************************ | |
86 | ||
87 | ||
88 | struct | |
89 | ||
90 | ||
91 | ************************************************************************/ | |
92 | struct fsi_priv { | |
93 | void __iomem *base; | |
94 | struct snd_pcm_substream *substream; | |
71f6e064 | 95 | struct fsi_master *master; |
a4d7d550 KM |
96 | |
97 | int fifo_max; | |
98 | int chan; | |
a4d7d550 KM |
99 | |
100 | int byte_offset; | |
101 | int period_len; | |
102 | int buffer_len; | |
103 | int periods; | |
104 | }; | |
105 | ||
106 | struct fsi_master { | |
107 | void __iomem *base; | |
108 | int irq; | |
a4d7d550 KM |
109 | struct fsi_priv fsia; |
110 | struct fsi_priv fsib; | |
111 | struct sh_fsi_platform_info *info; | |
112 | }; | |
113 | ||
a4d7d550 KM |
114 | /************************************************************************ |
115 | ||
116 | ||
117 | basic read write function | |
118 | ||
119 | ||
120 | ************************************************************************/ | |
121 | static int __fsi_reg_write(u32 reg, u32 data) | |
122 | { | |
123 | /* valid data area is 24bit */ | |
124 | data &= 0x00ffffff; | |
125 | ||
126 | return ctrl_outl(data, reg); | |
127 | } | |
128 | ||
129 | static u32 __fsi_reg_read(u32 reg) | |
130 | { | |
131 | return ctrl_inl(reg); | |
132 | } | |
133 | ||
134 | static int __fsi_reg_mask_set(u32 reg, u32 mask, u32 data) | |
135 | { | |
136 | u32 val = __fsi_reg_read(reg); | |
137 | ||
138 | val &= ~mask; | |
139 | val |= data & mask; | |
140 | ||
141 | return __fsi_reg_write(reg, val); | |
142 | } | |
143 | ||
144 | static int fsi_reg_write(struct fsi_priv *fsi, u32 reg, u32 data) | |
145 | { | |
146 | if (reg > REG_END) | |
147 | return -1; | |
148 | ||
149 | return __fsi_reg_write((u32)(fsi->base + reg), data); | |
150 | } | |
151 | ||
152 | static u32 fsi_reg_read(struct fsi_priv *fsi, u32 reg) | |
153 | { | |
154 | if (reg > REG_END) | |
155 | return 0; | |
156 | ||
157 | return __fsi_reg_read((u32)(fsi->base + reg)); | |
158 | } | |
159 | ||
160 | static int fsi_reg_mask_set(struct fsi_priv *fsi, u32 reg, u32 mask, u32 data) | |
161 | { | |
162 | if (reg > REG_END) | |
163 | return -1; | |
164 | ||
165 | return __fsi_reg_mask_set((u32)(fsi->base + reg), mask, data); | |
166 | } | |
167 | ||
71f6e064 | 168 | static int fsi_master_write(struct fsi_master *master, u32 reg, u32 data) |
a4d7d550 KM |
169 | { |
170 | if ((reg < MREG_START) || | |
171 | (reg > MREG_END)) | |
172 | return -1; | |
173 | ||
174 | return __fsi_reg_write((u32)(master->base + reg), data); | |
175 | } | |
176 | ||
71f6e064 | 177 | static u32 fsi_master_read(struct fsi_master *master, u32 reg) |
a4d7d550 KM |
178 | { |
179 | if ((reg < MREG_START) || | |
180 | (reg > MREG_END)) | |
181 | return 0; | |
182 | ||
183 | return __fsi_reg_read((u32)(master->base + reg)); | |
184 | } | |
185 | ||
71f6e064 KM |
186 | static int fsi_master_mask_set(struct fsi_master *master, |
187 | u32 reg, u32 mask, u32 data) | |
a4d7d550 KM |
188 | { |
189 | if ((reg < MREG_START) || | |
190 | (reg > MREG_END)) | |
191 | return -1; | |
192 | ||
193 | return __fsi_reg_mask_set((u32)(master->base + reg), mask, data); | |
194 | } | |
195 | ||
196 | /************************************************************************ | |
197 | ||
198 | ||
199 | basic function | |
200 | ||
201 | ||
202 | ************************************************************************/ | |
71f6e064 | 203 | static struct fsi_master *fsi_get_master(struct fsi_priv *fsi) |
a4d7d550 | 204 | { |
71f6e064 | 205 | return fsi->master; |
a4d7d550 KM |
206 | } |
207 | ||
208 | static int fsi_is_port_a(struct fsi_priv *fsi) | |
209 | { | |
71f6e064 KM |
210 | return fsi->master->base == fsi->base; |
211 | } | |
a4d7d550 | 212 | |
71f6e064 KM |
213 | static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream) |
214 | { | |
215 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
216 | struct snd_soc_dai_link *machine = rtd->dai; | |
217 | struct snd_soc_dai *dai = machine->cpu_dai; | |
a4d7d550 | 218 | |
71f6e064 | 219 | return dai->private_data; |
a4d7d550 KM |
220 | } |
221 | ||
222 | static u32 fsi_get_info_flags(struct fsi_priv *fsi) | |
223 | { | |
224 | int is_porta = fsi_is_port_a(fsi); | |
71f6e064 | 225 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 KM |
226 | |
227 | return is_porta ? master->info->porta_flags : | |
228 | master->info->portb_flags; | |
229 | } | |
230 | ||
231 | static int fsi_is_master_mode(struct fsi_priv *fsi, int is_play) | |
232 | { | |
233 | u32 mode; | |
234 | u32 flags = fsi_get_info_flags(fsi); | |
235 | ||
236 | mode = is_play ? SH_FSI_OUT_SLAVE_MODE : SH_FSI_IN_SLAVE_MODE; | |
237 | ||
238 | /* return | |
239 | * 1 : master mode | |
240 | * 0 : slave mode | |
241 | */ | |
242 | ||
243 | return (mode & flags) != mode; | |
244 | } | |
245 | ||
246 | static u32 fsi_port_ab_io_bit(struct fsi_priv *fsi, int is_play) | |
247 | { | |
248 | int is_porta = fsi_is_port_a(fsi); | |
249 | u32 data; | |
250 | ||
251 | if (is_porta) | |
252 | data = is_play ? (1 << 0) : (1 << 4); | |
253 | else | |
254 | data = is_play ? (1 << 8) : (1 << 12); | |
255 | ||
256 | return data; | |
257 | } | |
258 | ||
259 | static void fsi_stream_push(struct fsi_priv *fsi, | |
260 | struct snd_pcm_substream *substream, | |
261 | u32 buffer_len, | |
262 | u32 period_len) | |
263 | { | |
264 | fsi->substream = substream; | |
265 | fsi->buffer_len = buffer_len; | |
266 | fsi->period_len = period_len; | |
267 | fsi->byte_offset = 0; | |
268 | fsi->periods = 0; | |
269 | } | |
270 | ||
271 | static void fsi_stream_pop(struct fsi_priv *fsi) | |
272 | { | |
273 | fsi->substream = NULL; | |
274 | fsi->buffer_len = 0; | |
275 | fsi->period_len = 0; | |
276 | fsi->byte_offset = 0; | |
277 | fsi->periods = 0; | |
278 | } | |
279 | ||
280 | static int fsi_get_fifo_residue(struct fsi_priv *fsi, int is_play) | |
281 | { | |
282 | u32 status; | |
283 | u32 reg = is_play ? DOFF_ST : DIFF_ST; | |
284 | int residue; | |
285 | ||
286 | status = fsi_reg_read(fsi, reg); | |
287 | residue = 0x1ff & (status >> 8); | |
288 | residue *= fsi->chan; | |
289 | ||
290 | return residue; | |
291 | } | |
292 | ||
a4d7d550 KM |
293 | /************************************************************************ |
294 | ||
295 | ||
296 | ctrl function | |
297 | ||
298 | ||
299 | ************************************************************************/ | |
300 | static void fsi_irq_enable(struct fsi_priv *fsi, int is_play) | |
301 | { | |
302 | u32 data = fsi_port_ab_io_bit(fsi, is_play); | |
71f6e064 | 303 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 304 | |
71f6e064 KM |
305 | fsi_master_mask_set(master, IMSK, data, data); |
306 | fsi_master_mask_set(master, IEMSK, data, data); | |
a4d7d550 KM |
307 | } |
308 | ||
309 | static void fsi_irq_disable(struct fsi_priv *fsi, int is_play) | |
310 | { | |
311 | u32 data = fsi_port_ab_io_bit(fsi, is_play); | |
71f6e064 | 312 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 313 | |
71f6e064 KM |
314 | fsi_master_mask_set(master, IMSK, data, 0); |
315 | fsi_master_mask_set(master, IEMSK, data, 0); | |
a4d7d550 KM |
316 | } |
317 | ||
318 | static void fsi_clk_ctrl(struct fsi_priv *fsi, int enable) | |
319 | { | |
320 | u32 val = fsi_is_port_a(fsi) ? (1 << 0) : (1 << 4); | |
71f6e064 | 321 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 KM |
322 | |
323 | if (enable) | |
71f6e064 | 324 | fsi_master_mask_set(master, CLK_RST, val, val); |
a4d7d550 | 325 | else |
71f6e064 | 326 | fsi_master_mask_set(master, CLK_RST, val, 0); |
a4d7d550 KM |
327 | } |
328 | ||
329 | static void fsi_irq_init(struct fsi_priv *fsi, int is_play) | |
330 | { | |
331 | u32 data; | |
332 | u32 ctrl; | |
333 | ||
334 | data = fsi_port_ab_io_bit(fsi, is_play); | |
335 | ctrl = is_play ? DOFF_CTL : DIFF_CTL; | |
336 | ||
337 | /* set IMSK */ | |
338 | fsi_irq_disable(fsi, is_play); | |
339 | ||
340 | /* set interrupt generation factor */ | |
341 | fsi_reg_write(fsi, ctrl, IRQ_HALF); | |
342 | ||
343 | /* clear FIFO */ | |
344 | fsi_reg_mask_set(fsi, ctrl, FIFO_CLR, FIFO_CLR); | |
345 | ||
346 | /* clear interrupt factor */ | |
71f6e064 | 347 | fsi_master_mask_set(fsi_get_master(fsi), INT_ST, data, 0); |
a4d7d550 KM |
348 | } |
349 | ||
71f6e064 | 350 | static void fsi_soft_all_reset(struct fsi_master *master) |
a4d7d550 | 351 | { |
71f6e064 | 352 | u32 status = fsi_master_read(master, SOFT_RST); |
a4d7d550 KM |
353 | |
354 | /* port AB reset */ | |
355 | status &= 0x000000ff; | |
71f6e064 | 356 | fsi_master_write(master, SOFT_RST, status); |
a4d7d550 KM |
357 | mdelay(10); |
358 | ||
359 | /* soft reset */ | |
360 | status &= 0x000000f0; | |
71f6e064 | 361 | fsi_master_write(master, SOFT_RST, status); |
a4d7d550 | 362 | status |= 0x00000001; |
71f6e064 | 363 | fsi_master_write(master, SOFT_RST, status); |
a4d7d550 KM |
364 | mdelay(10); |
365 | } | |
366 | ||
a4d7d550 KM |
367 | /* playback interrupt */ |
368 | static int fsi_data_push(struct fsi_priv *fsi) | |
369 | { | |
370 | struct snd_pcm_runtime *runtime; | |
371 | struct snd_pcm_substream *substream = NULL; | |
372 | int send; | |
373 | int fifo_free; | |
374 | int width; | |
9ddc9aa9 | 375 | u8 *start; |
1c418d1f | 376 | int i, over_period; |
a4d7d550 KM |
377 | |
378 | if (!fsi || | |
379 | !fsi->substream || | |
380 | !fsi->substream->runtime) | |
381 | return -EINVAL; | |
382 | ||
1c418d1f KM |
383 | over_period = 0; |
384 | substream = fsi->substream; | |
385 | runtime = substream->runtime; | |
a4d7d550 KM |
386 | |
387 | /* FSI FIFO has limit. | |
388 | * So, this driver can not send periods data at a time | |
389 | */ | |
390 | if (fsi->byte_offset >= | |
391 | fsi->period_len * (fsi->periods + 1)) { | |
392 | ||
1c418d1f | 393 | over_period = 1; |
a4d7d550 KM |
394 | fsi->periods = (fsi->periods + 1) % runtime->periods; |
395 | ||
396 | if (0 == fsi->periods) | |
397 | fsi->byte_offset = 0; | |
398 | } | |
399 | ||
400 | /* get 1 channel data width */ | |
401 | width = frames_to_bytes(runtime, 1) / fsi->chan; | |
402 | ||
403 | /* get send size for alsa */ | |
404 | send = (fsi->buffer_len - fsi->byte_offset) / width; | |
405 | ||
406 | /* get FIFO free size */ | |
407 | fifo_free = (fsi->fifo_max * fsi->chan) - fsi_get_fifo_residue(fsi, 1); | |
408 | ||
409 | /* size check */ | |
410 | if (fifo_free < send) | |
411 | send = fifo_free; | |
412 | ||
9ddc9aa9 KM |
413 | start = runtime->dma_area; |
414 | start += fsi->byte_offset; | |
415 | ||
416 | switch (width) { | |
417 | case 2: | |
418 | for (i = 0; i < send; i++) | |
419 | fsi_reg_write(fsi, DODT, | |
420 | ((u32)*((u16 *)start + i) << 8)); | |
421 | break; | |
422 | case 4: | |
423 | for (i = 0; i < send; i++) | |
424 | fsi_reg_write(fsi, DODT, *((u32 *)start + i)); | |
425 | break; | |
426 | default: | |
a4d7d550 | 427 | return -EINVAL; |
9ddc9aa9 | 428 | } |
a4d7d550 KM |
429 | |
430 | fsi->byte_offset += send * width; | |
431 | ||
432 | fsi_irq_enable(fsi, 1); | |
433 | ||
1c418d1f | 434 | if (over_period) |
a4d7d550 KM |
435 | snd_pcm_period_elapsed(substream); |
436 | ||
437 | return 0; | |
438 | } | |
439 | ||
07102f3c KM |
440 | static int fsi_data_pop(struct fsi_priv *fsi) |
441 | { | |
442 | struct snd_pcm_runtime *runtime; | |
443 | struct snd_pcm_substream *substream = NULL; | |
444 | int free; | |
445 | int fifo_fill; | |
446 | int width; | |
447 | u8 *start; | |
1c418d1f | 448 | int i, over_period; |
07102f3c KM |
449 | |
450 | if (!fsi || | |
451 | !fsi->substream || | |
452 | !fsi->substream->runtime) | |
453 | return -EINVAL; | |
454 | ||
1c418d1f KM |
455 | over_period = 0; |
456 | substream = fsi->substream; | |
457 | runtime = substream->runtime; | |
07102f3c KM |
458 | |
459 | /* FSI FIFO has limit. | |
460 | * So, this driver can not send periods data at a time | |
461 | */ | |
462 | if (fsi->byte_offset >= | |
463 | fsi->period_len * (fsi->periods + 1)) { | |
464 | ||
1c418d1f | 465 | over_period = 1; |
07102f3c KM |
466 | fsi->periods = (fsi->periods + 1) % runtime->periods; |
467 | ||
468 | if (0 == fsi->periods) | |
469 | fsi->byte_offset = 0; | |
470 | } | |
471 | ||
472 | /* get 1 channel data width */ | |
473 | width = frames_to_bytes(runtime, 1) / fsi->chan; | |
474 | ||
475 | /* get free space for alsa */ | |
476 | free = (fsi->buffer_len - fsi->byte_offset) / width; | |
477 | ||
478 | /* get recv size */ | |
479 | fifo_fill = fsi_get_fifo_residue(fsi, 0); | |
480 | ||
481 | if (free < fifo_fill) | |
482 | fifo_fill = free; | |
483 | ||
484 | start = runtime->dma_area; | |
485 | start += fsi->byte_offset; | |
486 | ||
487 | switch (width) { | |
488 | case 2: | |
489 | for (i = 0; i < fifo_fill; i++) | |
490 | *((u16 *)start + i) = | |
491 | (u16)(fsi_reg_read(fsi, DIDT) >> 8); | |
492 | break; | |
493 | case 4: | |
494 | for (i = 0; i < fifo_fill; i++) | |
495 | *((u32 *)start + i) = fsi_reg_read(fsi, DIDT); | |
496 | break; | |
497 | default: | |
498 | return -EINVAL; | |
499 | } | |
500 | ||
501 | fsi->byte_offset += fifo_fill * width; | |
502 | ||
503 | fsi_irq_enable(fsi, 0); | |
504 | ||
1c418d1f | 505 | if (over_period) |
07102f3c KM |
506 | snd_pcm_period_elapsed(substream); |
507 | ||
508 | return 0; | |
509 | } | |
510 | ||
a4d7d550 KM |
511 | static irqreturn_t fsi_interrupt(int irq, void *data) |
512 | { | |
71f6e064 KM |
513 | struct fsi_master *master = data; |
514 | u32 status = fsi_master_read(master, SOFT_RST) & ~0x00000010; | |
515 | u32 int_st = fsi_master_read(master, INT_ST); | |
a4d7d550 KM |
516 | |
517 | /* clear irq status */ | |
71f6e064 KM |
518 | fsi_master_write(master, SOFT_RST, status); |
519 | fsi_master_write(master, SOFT_RST, status | 0x00000010); | |
a4d7d550 KM |
520 | |
521 | if (int_st & INT_A_OUT) | |
522 | fsi_data_push(&master->fsia); | |
523 | if (int_st & INT_B_OUT) | |
524 | fsi_data_push(&master->fsib); | |
07102f3c KM |
525 | if (int_st & INT_A_IN) |
526 | fsi_data_pop(&master->fsia); | |
527 | if (int_st & INT_B_IN) | |
528 | fsi_data_pop(&master->fsib); | |
a4d7d550 | 529 | |
71f6e064 | 530 | fsi_master_write(master, INT_ST, 0x0000000); |
a4d7d550 KM |
531 | |
532 | return IRQ_HANDLED; | |
533 | } | |
534 | ||
535 | /************************************************************************ | |
536 | ||
537 | ||
538 | dai ops | |
539 | ||
540 | ||
541 | ************************************************************************/ | |
542 | static int fsi_dai_startup(struct snd_pcm_substream *substream, | |
543 | struct snd_soc_dai *dai) | |
544 | { | |
71f6e064 | 545 | struct fsi_priv *fsi = fsi_get_priv(substream); |
a4d7d550 KM |
546 | const char *msg; |
547 | u32 flags = fsi_get_info_flags(fsi); | |
548 | u32 fmt; | |
549 | u32 reg; | |
550 | u32 data; | |
551 | int is_play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); | |
552 | int is_master; | |
553 | int ret = 0; | |
554 | ||
785d1c45 | 555 | pm_runtime_get_sync(dai->dev); |
a4d7d550 KM |
556 | |
557 | /* CKG1 */ | |
558 | data = is_play ? (1 << 0) : (1 << 4); | |
559 | is_master = fsi_is_master_mode(fsi, is_play); | |
560 | if (is_master) | |
561 | fsi_reg_mask_set(fsi, CKG1, data, data); | |
562 | else | |
563 | fsi_reg_mask_set(fsi, CKG1, data, 0); | |
564 | ||
565 | /* clock inversion (CKG2) */ | |
566 | data = 0; | |
567 | switch (SH_FSI_INVERSION_MASK & flags) { | |
568 | case SH_FSI_LRM_INV: | |
569 | data = 1 << 12; | |
570 | break; | |
571 | case SH_FSI_BRM_INV: | |
572 | data = 1 << 8; | |
573 | break; | |
574 | case SH_FSI_LRS_INV: | |
575 | data = 1 << 4; | |
576 | break; | |
577 | case SH_FSI_BRS_INV: | |
578 | data = 1 << 0; | |
579 | break; | |
580 | } | |
581 | fsi_reg_write(fsi, CKG2, data); | |
582 | ||
583 | /* do fmt, di fmt */ | |
584 | data = 0; | |
585 | reg = is_play ? DO_FMT : DI_FMT; | |
586 | fmt = is_play ? SH_FSI_GET_OFMT(flags) : SH_FSI_GET_IFMT(flags); | |
587 | switch (fmt) { | |
588 | case SH_FSI_FMT_MONO: | |
589 | msg = "MONO"; | |
590 | data = CR_FMT(CR_MONO); | |
591 | fsi->chan = 1; | |
592 | break; | |
593 | case SH_FSI_FMT_MONO_DELAY: | |
594 | msg = "MONO Delay"; | |
595 | data = CR_FMT(CR_MONO_D); | |
596 | fsi->chan = 1; | |
597 | break; | |
598 | case SH_FSI_FMT_PCM: | |
599 | msg = "PCM"; | |
600 | data = CR_FMT(CR_PCM); | |
601 | fsi->chan = 2; | |
602 | break; | |
603 | case SH_FSI_FMT_I2S: | |
604 | msg = "I2S"; | |
605 | data = CR_FMT(CR_I2S); | |
606 | fsi->chan = 2; | |
607 | break; | |
608 | case SH_FSI_FMT_TDM: | |
609 | msg = "TDM"; | |
610 | data = CR_FMT(CR_TDM) | (fsi->chan - 1); | |
611 | fsi->chan = is_play ? | |
612 | SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags); | |
613 | break; | |
614 | case SH_FSI_FMT_TDM_DELAY: | |
615 | msg = "TDM Delay"; | |
616 | data = CR_FMT(CR_TDM_D) | (fsi->chan - 1); | |
617 | fsi->chan = is_play ? | |
618 | SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags); | |
619 | break; | |
620 | default: | |
621 | dev_err(dai->dev, "unknown format.\n"); | |
622 | return -EINVAL; | |
623 | } | |
624 | ||
625 | switch (fsi->chan) { | |
626 | case 1: | |
627 | fsi->fifo_max = 256; | |
628 | break; | |
629 | case 2: | |
630 | fsi->fifo_max = 128; | |
631 | break; | |
632 | case 3: | |
633 | case 4: | |
634 | fsi->fifo_max = 64; | |
635 | break; | |
636 | case 5: | |
637 | case 6: | |
638 | case 7: | |
639 | case 8: | |
640 | fsi->fifo_max = 32; | |
641 | break; | |
642 | default: | |
643 | dev_err(dai->dev, "channel size error.\n"); | |
644 | return -EINVAL; | |
645 | } | |
646 | ||
647 | fsi_reg_write(fsi, reg, data); | |
a4d7d550 KM |
648 | |
649 | /* | |
650 | * clear clk reset if master mode | |
651 | */ | |
652 | if (is_master) | |
653 | fsi_clk_ctrl(fsi, 1); | |
654 | ||
655 | /* irq setting */ | |
656 | fsi_irq_init(fsi, is_play); | |
657 | ||
658 | return ret; | |
659 | } | |
660 | ||
661 | static void fsi_dai_shutdown(struct snd_pcm_substream *substream, | |
662 | struct snd_soc_dai *dai) | |
663 | { | |
71f6e064 | 664 | struct fsi_priv *fsi = fsi_get_priv(substream); |
a4d7d550 KM |
665 | int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
666 | ||
667 | fsi_irq_disable(fsi, is_play); | |
668 | fsi_clk_ctrl(fsi, 0); | |
669 | ||
785d1c45 | 670 | pm_runtime_put_sync(dai->dev); |
a4d7d550 KM |
671 | } |
672 | ||
673 | static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd, | |
674 | struct snd_soc_dai *dai) | |
675 | { | |
71f6e064 | 676 | struct fsi_priv *fsi = fsi_get_priv(substream); |
a4d7d550 KM |
677 | struct snd_pcm_runtime *runtime = substream->runtime; |
678 | int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; | |
679 | int ret = 0; | |
680 | ||
a4d7d550 KM |
681 | switch (cmd) { |
682 | case SNDRV_PCM_TRIGGER_START: | |
683 | fsi_stream_push(fsi, substream, | |
684 | frames_to_bytes(runtime, runtime->buffer_size), | |
685 | frames_to_bytes(runtime, runtime->period_size)); | |
07102f3c | 686 | ret = is_play ? fsi_data_push(fsi) : fsi_data_pop(fsi); |
a4d7d550 KM |
687 | break; |
688 | case SNDRV_PCM_TRIGGER_STOP: | |
689 | fsi_irq_disable(fsi, is_play); | |
690 | fsi_stream_pop(fsi); | |
691 | break; | |
692 | } | |
693 | ||
694 | return ret; | |
695 | } | |
696 | ||
697 | static struct snd_soc_dai_ops fsi_dai_ops = { | |
698 | .startup = fsi_dai_startup, | |
699 | .shutdown = fsi_dai_shutdown, | |
700 | .trigger = fsi_dai_trigger, | |
701 | }; | |
702 | ||
703 | /************************************************************************ | |
704 | ||
705 | ||
706 | pcm ops | |
707 | ||
708 | ||
709 | ************************************************************************/ | |
710 | static struct snd_pcm_hardware fsi_pcm_hardware = { | |
711 | .info = SNDRV_PCM_INFO_INTERLEAVED | | |
712 | SNDRV_PCM_INFO_MMAP | | |
713 | SNDRV_PCM_INFO_MMAP_VALID | | |
714 | SNDRV_PCM_INFO_PAUSE, | |
715 | .formats = FSI_FMTS, | |
716 | .rates = FSI_RATES, | |
717 | .rate_min = 8000, | |
718 | .rate_max = 192000, | |
719 | .channels_min = 1, | |
720 | .channels_max = 2, | |
721 | .buffer_bytes_max = 64 * 1024, | |
722 | .period_bytes_min = 32, | |
723 | .period_bytes_max = 8192, | |
724 | .periods_min = 1, | |
725 | .periods_max = 32, | |
726 | .fifo_size = 256, | |
727 | }; | |
728 | ||
729 | static int fsi_pcm_open(struct snd_pcm_substream *substream) | |
730 | { | |
731 | struct snd_pcm_runtime *runtime = substream->runtime; | |
732 | int ret = 0; | |
733 | ||
734 | snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware); | |
735 | ||
736 | ret = snd_pcm_hw_constraint_integer(runtime, | |
737 | SNDRV_PCM_HW_PARAM_PERIODS); | |
738 | ||
739 | return ret; | |
740 | } | |
741 | ||
742 | static int fsi_hw_params(struct snd_pcm_substream *substream, | |
743 | struct snd_pcm_hw_params *hw_params) | |
744 | { | |
745 | return snd_pcm_lib_malloc_pages(substream, | |
746 | params_buffer_bytes(hw_params)); | |
747 | } | |
748 | ||
749 | static int fsi_hw_free(struct snd_pcm_substream *substream) | |
750 | { | |
751 | return snd_pcm_lib_free_pages(substream); | |
752 | } | |
753 | ||
754 | static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream) | |
755 | { | |
756 | struct snd_pcm_runtime *runtime = substream->runtime; | |
71f6e064 | 757 | struct fsi_priv *fsi = fsi_get_priv(substream); |
a4d7d550 KM |
758 | long location; |
759 | ||
9ddc9aa9 | 760 | location = (fsi->byte_offset - 1); |
a4d7d550 KM |
761 | if (location < 0) |
762 | location = 0; | |
763 | ||
764 | return bytes_to_frames(runtime, location); | |
765 | } | |
766 | ||
767 | static struct snd_pcm_ops fsi_pcm_ops = { | |
768 | .open = fsi_pcm_open, | |
769 | .ioctl = snd_pcm_lib_ioctl, | |
770 | .hw_params = fsi_hw_params, | |
771 | .hw_free = fsi_hw_free, | |
772 | .pointer = fsi_pointer, | |
773 | }; | |
774 | ||
775 | /************************************************************************ | |
776 | ||
777 | ||
778 | snd_soc_platform | |
779 | ||
780 | ||
781 | ************************************************************************/ | |
782 | #define PREALLOC_BUFFER (32 * 1024) | |
783 | #define PREALLOC_BUFFER_MAX (32 * 1024) | |
784 | ||
785 | static void fsi_pcm_free(struct snd_pcm *pcm) | |
786 | { | |
787 | snd_pcm_lib_preallocate_free_for_all(pcm); | |
788 | } | |
789 | ||
790 | static int fsi_pcm_new(struct snd_card *card, | |
791 | struct snd_soc_dai *dai, | |
792 | struct snd_pcm *pcm) | |
793 | { | |
794 | /* | |
795 | * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel | |
796 | * in MMAP mode (i.e. aplay -M) | |
797 | */ | |
798 | return snd_pcm_lib_preallocate_pages_for_all( | |
799 | pcm, | |
800 | SNDRV_DMA_TYPE_CONTINUOUS, | |
801 | snd_dma_continuous_data(GFP_KERNEL), | |
802 | PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); | |
803 | } | |
804 | ||
805 | /************************************************************************ | |
806 | ||
807 | ||
808 | alsa struct | |
809 | ||
810 | ||
811 | ************************************************************************/ | |
812 | struct snd_soc_dai fsi_soc_dai[] = { | |
813 | { | |
814 | .name = "FSIA", | |
815 | .id = 0, | |
816 | .playback = { | |
817 | .rates = FSI_RATES, | |
818 | .formats = FSI_FMTS, | |
819 | .channels_min = 1, | |
820 | .channels_max = 8, | |
821 | }, | |
07102f3c KM |
822 | .capture = { |
823 | .rates = FSI_RATES, | |
824 | .formats = FSI_FMTS, | |
825 | .channels_min = 1, | |
826 | .channels_max = 8, | |
827 | }, | |
a4d7d550 KM |
828 | .ops = &fsi_dai_ops, |
829 | }, | |
830 | { | |
831 | .name = "FSIB", | |
832 | .id = 1, | |
833 | .playback = { | |
834 | .rates = FSI_RATES, | |
835 | .formats = FSI_FMTS, | |
836 | .channels_min = 1, | |
837 | .channels_max = 8, | |
838 | }, | |
07102f3c KM |
839 | .capture = { |
840 | .rates = FSI_RATES, | |
841 | .formats = FSI_FMTS, | |
842 | .channels_min = 1, | |
843 | .channels_max = 8, | |
844 | }, | |
a4d7d550 KM |
845 | .ops = &fsi_dai_ops, |
846 | }, | |
847 | }; | |
848 | EXPORT_SYMBOL_GPL(fsi_soc_dai); | |
849 | ||
850 | struct snd_soc_platform fsi_soc_platform = { | |
851 | .name = "fsi-pcm", | |
852 | .pcm_ops = &fsi_pcm_ops, | |
853 | .pcm_new = fsi_pcm_new, | |
854 | .pcm_free = fsi_pcm_free, | |
855 | }; | |
856 | EXPORT_SYMBOL_GPL(fsi_soc_platform); | |
857 | ||
858 | /************************************************************************ | |
859 | ||
860 | ||
861 | platform function | |
862 | ||
863 | ||
864 | ************************************************************************/ | |
865 | static int fsi_probe(struct platform_device *pdev) | |
866 | { | |
71f6e064 | 867 | struct fsi_master *master; |
a4d7d550 | 868 | struct resource *res; |
a4d7d550 KM |
869 | unsigned int irq; |
870 | int ret; | |
871 | ||
71f6e064 KM |
872 | if (0 != pdev->id) { |
873 | dev_err(&pdev->dev, "current fsi support id 0 only now\n"); | |
874 | return -ENODEV; | |
875 | } | |
876 | ||
a4d7d550 KM |
877 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
878 | irq = platform_get_irq(pdev, 0); | |
879 | if (!res || !irq) { | |
880 | dev_err(&pdev->dev, "Not enough FSI platform resources.\n"); | |
881 | ret = -ENODEV; | |
882 | goto exit; | |
883 | } | |
884 | ||
885 | master = kzalloc(sizeof(*master), GFP_KERNEL); | |
886 | if (!master) { | |
887 | dev_err(&pdev->dev, "Could not allocate master\n"); | |
888 | ret = -ENOMEM; | |
889 | goto exit; | |
890 | } | |
891 | ||
892 | master->base = ioremap_nocache(res->start, resource_size(res)); | |
893 | if (!master->base) { | |
894 | ret = -ENXIO; | |
895 | dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n"); | |
896 | goto exit_kfree; | |
897 | } | |
898 | ||
899 | master->irq = irq; | |
900 | master->info = pdev->dev.platform_data; | |
901 | master->fsia.base = master->base; | |
71f6e064 | 902 | master->fsia.master = master; |
a4d7d550 | 903 | master->fsib.base = master->base + 0x40; |
71f6e064 | 904 | master->fsib.master = master; |
a4d7d550 | 905 | |
785d1c45 KM |
906 | pm_runtime_enable(&pdev->dev); |
907 | pm_runtime_resume(&pdev->dev); | |
a4d7d550 KM |
908 | |
909 | fsi_soc_dai[0].dev = &pdev->dev; | |
71f6e064 | 910 | fsi_soc_dai[0].private_data = &master->fsia; |
a4d7d550 | 911 | fsi_soc_dai[1].dev = &pdev->dev; |
71f6e064 | 912 | fsi_soc_dai[1].private_data = &master->fsib; |
a4d7d550 | 913 | |
71f6e064 | 914 | fsi_soft_all_reset(master); |
a4d7d550 KM |
915 | |
916 | ret = request_irq(irq, &fsi_interrupt, IRQF_DISABLED, "fsi", master); | |
917 | if (ret) { | |
918 | dev_err(&pdev->dev, "irq request err\n"); | |
9ddc9aa9 | 919 | goto exit_iounmap; |
a4d7d550 KM |
920 | } |
921 | ||
922 | ret = snd_soc_register_platform(&fsi_soc_platform); | |
923 | if (ret < 0) { | |
924 | dev_err(&pdev->dev, "cannot snd soc register\n"); | |
925 | goto exit_free_irq; | |
926 | } | |
927 | ||
928 | return snd_soc_register_dais(fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai)); | |
929 | ||
930 | exit_free_irq: | |
931 | free_irq(irq, master); | |
a4d7d550 KM |
932 | exit_iounmap: |
933 | iounmap(master->base); | |
785d1c45 | 934 | pm_runtime_disable(&pdev->dev); |
a4d7d550 KM |
935 | exit_kfree: |
936 | kfree(master); | |
937 | master = NULL; | |
938 | exit: | |
939 | return ret; | |
940 | } | |
941 | ||
942 | static int fsi_remove(struct platform_device *pdev) | |
943 | { | |
71f6e064 KM |
944 | struct fsi_master *master; |
945 | ||
946 | master = fsi_get_master(fsi_soc_dai[0].private_data); | |
947 | ||
a4d7d550 KM |
948 | snd_soc_unregister_dais(fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai)); |
949 | snd_soc_unregister_platform(&fsi_soc_platform); | |
950 | ||
785d1c45 | 951 | pm_runtime_disable(&pdev->dev); |
a4d7d550 | 952 | |
a4d7d550 KM |
953 | free_irq(master->irq, master); |
954 | ||
955 | iounmap(master->base); | |
956 | kfree(master); | |
71f6e064 KM |
957 | |
958 | fsi_soc_dai[0].dev = NULL; | |
959 | fsi_soc_dai[0].private_data = NULL; | |
960 | fsi_soc_dai[1].dev = NULL; | |
961 | fsi_soc_dai[1].private_data = NULL; | |
962 | ||
a4d7d550 KM |
963 | return 0; |
964 | } | |
965 | ||
785d1c45 KM |
966 | static int fsi_runtime_nop(struct device *dev) |
967 | { | |
968 | /* Runtime PM callback shared between ->runtime_suspend() | |
969 | * and ->runtime_resume(). Simply returns success. | |
970 | * | |
971 | * This driver re-initializes all registers after | |
972 | * pm_runtime_get_sync() anyway so there is no need | |
973 | * to save and restore registers here. | |
974 | */ | |
975 | return 0; | |
976 | } | |
977 | ||
978 | static struct dev_pm_ops fsi_pm_ops = { | |
979 | .runtime_suspend = fsi_runtime_nop, | |
980 | .runtime_resume = fsi_runtime_nop, | |
981 | }; | |
982 | ||
a4d7d550 KM |
983 | static struct platform_driver fsi_driver = { |
984 | .driver = { | |
985 | .name = "sh_fsi", | |
785d1c45 | 986 | .pm = &fsi_pm_ops, |
a4d7d550 KM |
987 | }, |
988 | .probe = fsi_probe, | |
989 | .remove = fsi_remove, | |
990 | }; | |
991 | ||
992 | static int __init fsi_mobile_init(void) | |
993 | { | |
994 | return platform_driver_register(&fsi_driver); | |
995 | } | |
996 | ||
997 | static void __exit fsi_mobile_exit(void) | |
998 | { | |
999 | platform_driver_unregister(&fsi_driver); | |
1000 | } | |
1001 | module_init(fsi_mobile_init); | |
1002 | module_exit(fsi_mobile_exit); | |
1003 | ||
1004 | MODULE_LICENSE("GPL"); | |
1005 | MODULE_DESCRIPTION("SuperH onchip FSI audio driver"); | |
1006 | MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>"); |