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a4d7d550 KM |
1 | /* |
2 | * Fifo-attached Serial Interface (FSI) support for SH7724 | |
3 | * | |
4 | * Copyright (C) 2009 Renesas Solutions Corp. | |
5 | * Kuninori Morimoto <morimoto.kuninori@renesas.com> | |
6 | * | |
7 | * Based on ssi.c | |
8 | * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
a4d7d550 | 15 | #include <linux/delay.h> |
7da9ced6 | 16 | #include <linux/dma-mapping.h> |
785d1c45 | 17 | #include <linux/pm_runtime.h> |
a4d7d550 | 18 | #include <linux/io.h> |
7da9ced6 KM |
19 | #include <linux/scatterlist.h> |
20 | #include <linux/sh_dma.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
da155d5b | 22 | #include <linux/module.h> |
a4d7d550 | 23 | #include <sound/soc.h> |
a4d7d550 | 24 | #include <sound/sh_fsi.h> |
a4d7d550 | 25 | |
e8c8b631 KM |
26 | /* PortA/PortB register */ |
27 | #define REG_DO_FMT 0x0000 | |
28 | #define REG_DOFF_CTL 0x0004 | |
29 | #define REG_DOFF_ST 0x0008 | |
30 | #define REG_DI_FMT 0x000C | |
31 | #define REG_DIFF_CTL 0x0010 | |
32 | #define REG_DIFF_ST 0x0014 | |
33 | #define REG_CKG1 0x0018 | |
34 | #define REG_CKG2 0x001C | |
35 | #define REG_DIDT 0x0020 | |
36 | #define REG_DODT 0x0024 | |
37 | #define REG_MUTE_ST 0x0028 | |
65ff03f4 | 38 | #define REG_OUT_DMAC 0x002C |
e8c8b631 | 39 | #define REG_OUT_SEL 0x0030 |
65ff03f4 | 40 | #define REG_IN_DMAC 0x0038 |
cc780d38 | 41 | |
43fa95ca KM |
42 | /* master register */ |
43 | #define MST_CLK_RST 0x0210 | |
44 | #define MST_SOFT_RST 0x0214 | |
45 | #define MST_FIFO_SZ 0x0218 | |
46 | ||
47 | /* core register (depend on FSI version) */ | |
3bc28070 KM |
48 | #define A_MST_CTLR 0x0180 |
49 | #define B_MST_CTLR 0x01A0 | |
cc780d38 KM |
50 | #define CPU_INT_ST 0x01F4 |
51 | #define CPU_IEMSK 0x01F8 | |
52 | #define CPU_IMSK 0x01FC | |
a4d7d550 KM |
53 | #define INT_ST 0x0200 |
54 | #define IEMSK 0x0204 | |
55 | #define IMSK 0x0208 | |
a4d7d550 KM |
56 | |
57 | /* DO_FMT */ | |
58 | /* DI_FMT */ | |
7da9ced6 | 59 | #define CR_BWS_MASK (0x3 << 20) /* FSI2 */ |
f7d711e3 KM |
60 | #define CR_BWS_24 (0x0 << 20) /* FSI2 */ |
61 | #define CR_BWS_16 (0x1 << 20) /* FSI2 */ | |
62 | #define CR_BWS_20 (0x2 << 20) /* FSI2 */ | |
63 | ||
64 | #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */ | |
65 | #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */ | |
66 | #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */ | |
67 | ||
a7ffb52b KM |
68 | #define CR_MONO (0x0 << 4) |
69 | #define CR_MONO_D (0x1 << 4) | |
70 | #define CR_PCM (0x2 << 4) | |
71 | #define CR_I2S (0x3 << 4) | |
72 | #define CR_TDM (0x4 << 4) | |
73 | #define CR_TDM_D (0x5 << 4) | |
a4d7d550 | 74 | |
7da9ced6 KM |
75 | /* OUT_DMAC */ |
76 | /* IN_DMAC */ | |
77 | #define VDMD_MASK (0x3 << 4) | |
78 | #define VDMD_FRONT (0x0 << 4) /* Package in front */ | |
79 | #define VDMD_BACK (0x1 << 4) /* Package in back */ | |
80 | #define VDMD_STREAM (0x2 << 4) /* Stream mode(16bit * 2) */ | |
81 | ||
82 | #define DMA_ON (0x1 << 0) | |
83 | ||
a4d7d550 KM |
84 | /* DOFF_CTL */ |
85 | /* DIFF_CTL */ | |
86 | #define IRQ_HALF 0x00100000 | |
87 | #define FIFO_CLR 0x00000001 | |
88 | ||
89 | /* DOFF_ST */ | |
90 | #define ERR_OVER 0x00000010 | |
91 | #define ERR_UNDER 0x00000001 | |
59c3b003 | 92 | #define ST_ERR (ERR_OVER | ERR_UNDER) |
a4d7d550 | 93 | |
ccad7b44 KM |
94 | /* CKG1 */ |
95 | #define ACKMD_MASK 0x00007000 | |
96 | #define BPFMD_MASK 0x00000700 | |
4d805f7b KM |
97 | #define DIMD (1 << 4) |
98 | #define DOMD (1 << 0) | |
ccad7b44 | 99 | |
3bc28070 KM |
100 | /* A/B MST_CTLR */ |
101 | #define BP (1 << 4) /* Fix the signal of Biphase output */ | |
102 | #define SE (1 << 0) /* Fix the master clock */ | |
103 | ||
a4d7d550 | 104 | /* CLK_RST */ |
1f5e2a31 KM |
105 | #define CRB (1 << 4) |
106 | #define CRA (1 << 0) | |
a4d7d550 | 107 | |
cf6edd00 KM |
108 | /* IO SHIFT / MACRO */ |
109 | #define BI_SHIFT 12 | |
110 | #define BO_SHIFT 8 | |
111 | #define AI_SHIFT 4 | |
112 | #define AO_SHIFT 0 | |
113 | #define AB_IO(param, shift) (param << shift) | |
a4d7d550 | 114 | |
feb58cff KM |
115 | /* SOFT_RST */ |
116 | #define PBSR (1 << 12) /* Port B Software Reset */ | |
117 | #define PASR (1 << 8) /* Port A Software Reset */ | |
118 | #define IR (1 << 4) /* Interrupt Reset */ | |
119 | #define FSISR (1 << 0) /* Software Reset */ | |
120 | ||
f7d711e3 KM |
121 | /* OUT_SEL (FSI2) */ |
122 | #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */ | |
123 | /* 1: Biphase and serial */ | |
124 | ||
4a942b45 | 125 | /* FIFO_SZ */ |
cf6edd00 | 126 | #define FIFO_SZ_MASK 0x7 |
4a942b45 | 127 | |
a4d7d550 KM |
128 | #define FSI_RATES SNDRV_PCM_RATE_8000_96000 |
129 | ||
130 | #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE) | |
131 | ||
fec691e7 | 132 | typedef int (*set_rate_func)(struct device *dev, int rate, int enable); |
d7c5762b | 133 | |
766812e6 KM |
134 | /* |
135 | * bus options | |
136 | * | |
137 | * 0x000000BA | |
138 | * | |
139 | * A : sample widtht 16bit setting | |
140 | * B : sample widtht 24bit setting | |
141 | */ | |
142 | ||
143 | #define SHIFT_16DATA 0 | |
144 | #define SHIFT_24DATA 4 | |
145 | ||
146 | #define PACKAGE_24BITBUS_BACK 0 | |
147 | #define PACKAGE_24BITBUS_FRONT 1 | |
148 | #define PACKAGE_16BITBUS_STREAM 2 | |
149 | ||
150 | #define BUSOP_SET(s, a) ((a) << SHIFT_ ## s ## DATA) | |
151 | #define BUSOP_GET(s, a) (((a) >> SHIFT_ ## s ## DATA) & 0xF) | |
152 | ||
5bfb9ad0 KM |
153 | /* |
154 | * FSI driver use below type name for variable | |
155 | * | |
5bfb9ad0 | 156 | * xxx_num : number of data |
2e651baf KM |
157 | * xxx_pos : position of data |
158 | * xxx_capa : capacity of data | |
159 | */ | |
160 | ||
161 | /* | |
162 | * period/frame/sample image | |
163 | * | |
164 | * ex) PCM (2ch) | |
165 | * | |
166 | * period pos period pos | |
167 | * [n] [n + 1] | |
168 | * |<-------------------- period--------------------->| | |
169 | * ==|============================================ ... =|== | |
170 | * | | | |
171 | * ||<----- frame ----->|<------ frame ----->| ... | | |
172 | * |+--------------------+--------------------+- ... | | |
173 | * ||[ sample ][ sample ]|[ sample ][ sample ]| ... | | |
174 | * |+--------------------+--------------------+- ... | | |
175 | * ==|============================================ ... =|== | |
176 | */ | |
177 | ||
178 | /* | |
179 | * FSI FIFO image | |
180 | * | |
181 | * | | | |
182 | * | | | |
183 | * | [ sample ] | | |
184 | * | [ sample ] | | |
185 | * | [ sample ] | | |
186 | * | [ sample ] | | |
187 | * --> go to codecs | |
5bfb9ad0 KM |
188 | */ |
189 | ||
c8fe2574 KM |
190 | /* |
191 | * struct | |
192 | */ | |
a4d7d550 | 193 | |
5e97313a | 194 | struct fsi_stream_handler; |
93193c2b | 195 | struct fsi_stream { |
a4d7d550 | 196 | |
5e97313a KM |
197 | /* |
198 | * these are initialized by fsi_stream_init() | |
199 | */ | |
200 | struct snd_pcm_substream *substream; | |
2e651baf KM |
201 | int fifo_sample_capa; /* sample capacity of FSI FIFO */ |
202 | int buff_sample_capa; /* sample capacity of ALSA buffer */ | |
203 | int buff_sample_pos; /* sample position of ALSA buffer */ | |
204 | int period_samples; /* sample number / 1 period */ | |
205 | int period_pos; /* current period position */ | |
c1e6f10e | 206 | int sample_width; /* sample width */ |
1ec9bc35 KM |
207 | int uerr_num; |
208 | int oerr_num; | |
5e97313a | 209 | |
766812e6 KM |
210 | /* |
211 | * bus options | |
212 | */ | |
213 | u32 bus_option; | |
214 | ||
5e97313a KM |
215 | /* |
216 | * thse are initialized by fsi_handler_init() | |
217 | */ | |
218 | struct fsi_stream_handler *handler; | |
219 | struct fsi_priv *priv; | |
7da9ced6 KM |
220 | |
221 | /* | |
222 | * these are for DMAEngine | |
223 | */ | |
224 | struct dma_chan *chan; | |
225 | struct sh_dmae_slave slave; /* see fsi_handler_init() */ | |
226 | struct tasklet_struct tasklet; | |
227 | dma_addr_t dma; | |
93193c2b KM |
228 | }; |
229 | ||
230 | struct fsi_priv { | |
231 | void __iomem *base; | |
232 | struct fsi_master *master; | |
fec691e7 | 233 | struct sh_fsi_port_info *info; |
93193c2b KM |
234 | |
235 | struct fsi_stream playback; | |
236 | struct fsi_stream capture; | |
3bc28070 | 237 | |
9c59dd34 | 238 | u32 fmt; |
9478e0b6 | 239 | |
6a9ebad8 KM |
240 | int chan_num:16; |
241 | int clk_master:1; | |
9478e0b6 | 242 | int spdif:1; |
6a9ebad8 | 243 | |
d4bc99b9 | 244 | long rate; |
a4d7d550 KM |
245 | }; |
246 | ||
5e97313a | 247 | struct fsi_stream_handler { |
83344027 KM |
248 | int (*init)(struct fsi_priv *fsi, struct fsi_stream *io); |
249 | int (*quit)(struct fsi_priv *fsi, struct fsi_stream *io); | |
b1226dc5 | 250 | int (*probe)(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev); |
5e97313a KM |
251 | int (*transfer)(struct fsi_priv *fsi, struct fsi_stream *io); |
252 | int (*remove)(struct fsi_priv *fsi, struct fsi_stream *io); | |
180346ed KM |
253 | void (*start_stop)(struct fsi_priv *fsi, struct fsi_stream *io, |
254 | int enable); | |
5e97313a KM |
255 | }; |
256 | #define fsi_stream_handler_call(io, func, args...) \ | |
257 | (!(io) ? -ENODEV : \ | |
258 | !((io)->handler->func) ? 0 : \ | |
259 | (io)->handler->func(args)) | |
260 | ||
73b92c1f KM |
261 | struct fsi_core { |
262 | int ver; | |
263 | ||
cc780d38 KM |
264 | u32 int_st; |
265 | u32 iemsk; | |
266 | u32 imsk; | |
2b0e7302 KM |
267 | u32 a_mclk; |
268 | u32 b_mclk; | |
cc780d38 KM |
269 | }; |
270 | ||
a4d7d550 KM |
271 | struct fsi_master { |
272 | void __iomem *base; | |
273 | int irq; | |
a4d7d550 KM |
274 | struct fsi_priv fsia; |
275 | struct fsi_priv fsib; | |
73b92c1f | 276 | struct fsi_core *core; |
8fc176d5 | 277 | spinlock_t lock; |
a4d7d550 KM |
278 | }; |
279 | ||
7b1b3331 KM |
280 | static int fsi_stream_is_play(struct fsi_priv *fsi, struct fsi_stream *io); |
281 | ||
c8fe2574 KM |
282 | /* |
283 | * basic read write function | |
284 | */ | |
a4d7d550 | 285 | |
ca7aceef | 286 | static void __fsi_reg_write(u32 __iomem *reg, u32 data) |
a4d7d550 KM |
287 | { |
288 | /* valid data area is 24bit */ | |
289 | data &= 0x00ffffff; | |
290 | ||
0f69d978 | 291 | __raw_writel(data, reg); |
a4d7d550 KM |
292 | } |
293 | ||
ca7aceef | 294 | static u32 __fsi_reg_read(u32 __iomem *reg) |
a4d7d550 | 295 | { |
0f69d978 | 296 | return __raw_readl(reg); |
a4d7d550 KM |
297 | } |
298 | ||
ca7aceef | 299 | static void __fsi_reg_mask_set(u32 __iomem *reg, u32 mask, u32 data) |
a4d7d550 KM |
300 | { |
301 | u32 val = __fsi_reg_read(reg); | |
302 | ||
303 | val &= ~mask; | |
304 | val |= data & mask; | |
305 | ||
0f69d978 | 306 | __fsi_reg_write(reg, val); |
a4d7d550 KM |
307 | } |
308 | ||
e8c8b631 | 309 | #define fsi_reg_write(p, r, d)\ |
8918b843 | 310 | __fsi_reg_write((p->base + REG_##r), d) |
a4d7d550 | 311 | |
e8c8b631 | 312 | #define fsi_reg_read(p, r)\ |
8918b843 | 313 | __fsi_reg_read((p->base + REG_##r)) |
a4d7d550 | 314 | |
e8c8b631 | 315 | #define fsi_reg_mask_set(p, r, m, d)\ |
8918b843 | 316 | __fsi_reg_mask_set((p->base + REG_##r), m, d) |
a4d7d550 | 317 | |
43fa95ca KM |
318 | #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r) |
319 | #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r) | |
320 | static u32 _fsi_master_read(struct fsi_master *master, u32 reg) | |
a4d7d550 | 321 | { |
8fc176d5 KM |
322 | u32 ret; |
323 | unsigned long flags; | |
324 | ||
8fc176d5 | 325 | spin_lock_irqsave(&master->lock, flags); |
ca7aceef | 326 | ret = __fsi_reg_read(master->base + reg); |
8fc176d5 KM |
327 | spin_unlock_irqrestore(&master->lock, flags); |
328 | ||
329 | return ret; | |
a4d7d550 KM |
330 | } |
331 | ||
43fa95ca KM |
332 | #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d) |
333 | #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d) | |
334 | static void _fsi_master_mask_set(struct fsi_master *master, | |
71f6e064 | 335 | u32 reg, u32 mask, u32 data) |
a4d7d550 | 336 | { |
8fc176d5 KM |
337 | unsigned long flags; |
338 | ||
8fc176d5 | 339 | spin_lock_irqsave(&master->lock, flags); |
ca7aceef | 340 | __fsi_reg_mask_set(master->base + reg, mask, data); |
8fc176d5 | 341 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
342 | } |
343 | ||
c8fe2574 KM |
344 | /* |
345 | * basic function | |
346 | */ | |
284c6f65 KM |
347 | static int fsi_version(struct fsi_master *master) |
348 | { | |
349 | return master->core->ver; | |
350 | } | |
a4d7d550 | 351 | |
71f6e064 | 352 | static struct fsi_master *fsi_get_master(struct fsi_priv *fsi) |
a4d7d550 | 353 | { |
71f6e064 | 354 | return fsi->master; |
a4d7d550 KM |
355 | } |
356 | ||
6a9ebad8 KM |
357 | static int fsi_is_clk_master(struct fsi_priv *fsi) |
358 | { | |
359 | return fsi->clk_master; | |
360 | } | |
361 | ||
a4d7d550 KM |
362 | static int fsi_is_port_a(struct fsi_priv *fsi) |
363 | { | |
71f6e064 KM |
364 | return fsi->master->base == fsi->base; |
365 | } | |
a4d7d550 | 366 | |
9478e0b6 KM |
367 | static int fsi_is_spdif(struct fsi_priv *fsi) |
368 | { | |
369 | return fsi->spdif; | |
370 | } | |
371 | ||
a449e467 KM |
372 | static int fsi_is_play(struct snd_pcm_substream *substream) |
373 | { | |
374 | return substream->stream == SNDRV_PCM_STREAM_PLAYBACK; | |
375 | } | |
376 | ||
142e8174 | 377 | static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream) |
71f6e064 KM |
378 | { |
379 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
142e8174 | 380 | |
f0fba2ad | 381 | return rtd->cpu_dai; |
142e8174 KM |
382 | } |
383 | ||
0d032c19 | 384 | static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai) |
142e8174 | 385 | { |
f0fba2ad | 386 | struct fsi_master *master = snd_soc_dai_get_drvdata(dai); |
a4d7d550 | 387 | |
f0fba2ad LG |
388 | if (dai->id == 0) |
389 | return &master->fsia; | |
390 | else | |
391 | return &master->fsib; | |
a4d7d550 KM |
392 | } |
393 | ||
0d032c19 KM |
394 | static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream) |
395 | { | |
396 | return fsi_get_priv_frm_dai(fsi_get_dai(substream)); | |
397 | } | |
398 | ||
fec691e7 | 399 | static set_rate_func fsi_get_info_set_rate(struct fsi_priv *fsi) |
d7c5762b | 400 | { |
fec691e7 | 401 | if (!fsi->info) |
d7c5762b KM |
402 | return NULL; |
403 | ||
fec691e7 | 404 | return fsi->info->set_rate; |
d7c5762b KM |
405 | } |
406 | ||
a4d7d550 KM |
407 | static u32 fsi_get_info_flags(struct fsi_priv *fsi) |
408 | { | |
fec691e7 | 409 | if (!fsi->info) |
d7c5762b KM |
410 | return 0; |
411 | ||
fec691e7 | 412 | return fsi->info->flags; |
a4d7d550 KM |
413 | } |
414 | ||
938e2a8d | 415 | static u32 fsi_get_port_shift(struct fsi_priv *fsi, struct fsi_stream *io) |
a4d7d550 | 416 | { |
938e2a8d | 417 | int is_play = fsi_stream_is_play(fsi, io); |
a4d7d550 | 418 | int is_porta = fsi_is_port_a(fsi); |
cf6edd00 | 419 | u32 shift; |
a4d7d550 KM |
420 | |
421 | if (is_porta) | |
cf6edd00 | 422 | shift = is_play ? AO_SHIFT : AI_SHIFT; |
a4d7d550 | 423 | else |
cf6edd00 | 424 | shift = is_play ? BO_SHIFT : BI_SHIFT; |
a4d7d550 | 425 | |
cf6edd00 | 426 | return shift; |
a4d7d550 KM |
427 | } |
428 | ||
2e651baf KM |
429 | static int fsi_frame2sample(struct fsi_priv *fsi, int frames) |
430 | { | |
431 | return frames * fsi->chan_num; | |
432 | } | |
433 | ||
434 | static int fsi_sample2frame(struct fsi_priv *fsi, int samples) | |
435 | { | |
436 | return samples / fsi->chan_num; | |
437 | } | |
438 | ||
7b1b3331 KM |
439 | static int fsi_get_current_fifo_samples(struct fsi_priv *fsi, |
440 | struct fsi_stream *io) | |
4e62d84d | 441 | { |
7b1b3331 | 442 | int is_play = fsi_stream_is_play(fsi, io); |
4e62d84d KM |
443 | u32 status; |
444 | int frames; | |
445 | ||
446 | status = is_play ? | |
447 | fsi_reg_read(fsi, DOFF_ST) : | |
448 | fsi_reg_read(fsi, DIFF_ST); | |
449 | ||
450 | frames = 0x1ff & (status >> 8); | |
451 | ||
452 | return fsi_frame2sample(fsi, frames); | |
453 | } | |
454 | ||
455 | static void fsi_count_fifo_err(struct fsi_priv *fsi) | |
456 | { | |
457 | u32 ostatus = fsi_reg_read(fsi, DOFF_ST); | |
458 | u32 istatus = fsi_reg_read(fsi, DIFF_ST); | |
459 | ||
460 | if (ostatus & ERR_OVER) | |
461 | fsi->playback.oerr_num++; | |
462 | ||
463 | if (ostatus & ERR_UNDER) | |
464 | fsi->playback.uerr_num++; | |
465 | ||
466 | if (istatus & ERR_OVER) | |
467 | fsi->capture.oerr_num++; | |
468 | ||
469 | if (istatus & ERR_UNDER) | |
470 | fsi->capture.uerr_num++; | |
471 | ||
472 | fsi_reg_write(fsi, DOFF_ST, 0); | |
473 | fsi_reg_write(fsi, DIFF_ST, 0); | |
474 | } | |
475 | ||
476 | /* | |
477 | * fsi_stream_xx() function | |
478 | */ | |
a449e467 KM |
479 | static inline int fsi_stream_is_play(struct fsi_priv *fsi, |
480 | struct fsi_stream *io) | |
4e62d84d | 481 | { |
a449e467 | 482 | return &fsi->playback == io; |
4e62d84d KM |
483 | } |
484 | ||
485 | static inline struct fsi_stream *fsi_stream_get(struct fsi_priv *fsi, | |
938e2a8d | 486 | struct snd_pcm_substream *substream) |
4e62d84d | 487 | { |
938e2a8d | 488 | return fsi_is_play(substream) ? &fsi->playback : &fsi->capture; |
4e62d84d KM |
489 | } |
490 | ||
cda828ca | 491 | static int fsi_stream_is_working(struct fsi_priv *fsi, |
938e2a8d | 492 | struct fsi_stream *io) |
cda828ca | 493 | { |
cda828ca KM |
494 | struct fsi_master *master = fsi_get_master(fsi); |
495 | unsigned long flags; | |
496 | int ret; | |
497 | ||
498 | spin_lock_irqsave(&master->lock, flags); | |
97df8187 | 499 | ret = !!(io->substream && io->substream->runtime); |
cda828ca KM |
500 | spin_unlock_irqrestore(&master->lock, flags); |
501 | ||
502 | return ret; | |
503 | } | |
504 | ||
5e97313a KM |
505 | static struct fsi_priv *fsi_stream_to_priv(struct fsi_stream *io) |
506 | { | |
507 | return io->priv; | |
508 | } | |
509 | ||
8c415295 | 510 | static void fsi_stream_init(struct fsi_priv *fsi, |
938e2a8d | 511 | struct fsi_stream *io, |
0ffe296a | 512 | struct snd_pcm_substream *substream) |
a4d7d550 | 513 | { |
0ffe296a | 514 | struct snd_pcm_runtime *runtime = substream->runtime; |
2da65892 KM |
515 | struct fsi_master *master = fsi_get_master(fsi); |
516 | unsigned long flags; | |
93193c2b | 517 | |
2da65892 | 518 | spin_lock_irqsave(&master->lock, flags); |
93193c2b | 519 | io->substream = substream; |
2e651baf KM |
520 | io->buff_sample_capa = fsi_frame2sample(fsi, runtime->buffer_size); |
521 | io->buff_sample_pos = 0; | |
522 | io->period_samples = fsi_frame2sample(fsi, runtime->period_size); | |
523 | io->period_pos = 0; | |
c1e6f10e | 524 | io->sample_width = samples_to_bytes(runtime, 1); |
766812e6 | 525 | io->bus_option = 0; |
1ec9bc35 KM |
526 | io->oerr_num = -1; /* ignore 1st err */ |
527 | io->uerr_num = -1; /* ignore 1st err */ | |
83344027 | 528 | fsi_stream_handler_call(io, init, fsi, io); |
2da65892 | 529 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
530 | } |
531 | ||
938e2a8d | 532 | static void fsi_stream_quit(struct fsi_priv *fsi, struct fsi_stream *io) |
a4d7d550 | 533 | { |
1ec9bc35 | 534 | struct snd_soc_dai *dai = fsi_get_dai(io->substream); |
2da65892 KM |
535 | struct fsi_master *master = fsi_get_master(fsi); |
536 | unsigned long flags; | |
1ec9bc35 | 537 | |
2da65892 | 538 | spin_lock_irqsave(&master->lock, flags); |
1ec9bc35 KM |
539 | |
540 | if (io->oerr_num > 0) | |
541 | dev_err(dai->dev, "over_run = %d\n", io->oerr_num); | |
542 | ||
543 | if (io->uerr_num > 0) | |
544 | dev_err(dai->dev, "under_run = %d\n", io->uerr_num); | |
93193c2b | 545 | |
83344027 | 546 | fsi_stream_handler_call(io, quit, fsi, io); |
93193c2b | 547 | io->substream = NULL; |
2e651baf KM |
548 | io->buff_sample_capa = 0; |
549 | io->buff_sample_pos = 0; | |
550 | io->period_samples = 0; | |
551 | io->period_pos = 0; | |
c1e6f10e | 552 | io->sample_width = 0; |
766812e6 | 553 | io->bus_option = 0; |
1ec9bc35 KM |
554 | io->oerr_num = 0; |
555 | io->uerr_num = 0; | |
2da65892 | 556 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
557 | } |
558 | ||
5e97313a KM |
559 | static int fsi_stream_transfer(struct fsi_stream *io) |
560 | { | |
561 | struct fsi_priv *fsi = fsi_stream_to_priv(io); | |
562 | if (!fsi) | |
563 | return -EIO; | |
564 | ||
565 | return fsi_stream_handler_call(io, transfer, fsi, io); | |
566 | } | |
567 | ||
180346ed KM |
568 | #define fsi_stream_start(fsi, io)\ |
569 | fsi_stream_handler_call(io, start_stop, fsi, io, 1) | |
570 | ||
571 | #define fsi_stream_stop(fsi, io)\ | |
572 | fsi_stream_handler_call(io, start_stop, fsi, io, 0) | |
573 | ||
b1226dc5 | 574 | static int fsi_stream_probe(struct fsi_priv *fsi, struct device *dev) |
5e97313a KM |
575 | { |
576 | struct fsi_stream *io; | |
577 | int ret1, ret2; | |
578 | ||
579 | io = &fsi->playback; | |
b1226dc5 | 580 | ret1 = fsi_stream_handler_call(io, probe, fsi, io, dev); |
5e97313a KM |
581 | |
582 | io = &fsi->capture; | |
b1226dc5 | 583 | ret2 = fsi_stream_handler_call(io, probe, fsi, io, dev); |
5e97313a KM |
584 | |
585 | if (ret1 < 0) | |
586 | return ret1; | |
587 | if (ret2 < 0) | |
588 | return ret2; | |
589 | ||
590 | return 0; | |
591 | } | |
592 | ||
593 | static int fsi_stream_remove(struct fsi_priv *fsi) | |
594 | { | |
595 | struct fsi_stream *io; | |
596 | int ret1, ret2; | |
597 | ||
598 | io = &fsi->playback; | |
599 | ret1 = fsi_stream_handler_call(io, remove, fsi, io); | |
600 | ||
601 | io = &fsi->capture; | |
602 | ret2 = fsi_stream_handler_call(io, remove, fsi, io); | |
603 | ||
604 | if (ret1 < 0) | |
605 | return ret1; | |
606 | if (ret2 < 0) | |
607 | return ret2; | |
608 | ||
609 | return 0; | |
610 | } | |
611 | ||
766812e6 KM |
612 | /* |
613 | * format/bus/dma setting | |
614 | */ | |
615 | static void fsi_format_bus_setup(struct fsi_priv *fsi, struct fsi_stream *io, | |
616 | u32 bus, struct device *dev) | |
617 | { | |
618 | struct fsi_master *master = fsi_get_master(fsi); | |
619 | int is_play = fsi_stream_is_play(fsi, io); | |
620 | u32 fmt = fsi->fmt; | |
621 | ||
622 | if (fsi_version(master) >= 2) { | |
623 | u32 dma = 0; | |
624 | ||
625 | /* | |
626 | * FSI2 needs DMA/Bus setting | |
627 | */ | |
628 | switch (bus) { | |
629 | case PACKAGE_24BITBUS_FRONT: | |
630 | fmt |= CR_BWS_24; | |
631 | dma |= VDMD_FRONT; | |
632 | dev_dbg(dev, "24bit bus / package in front\n"); | |
633 | break; | |
634 | case PACKAGE_16BITBUS_STREAM: | |
635 | fmt |= CR_BWS_16; | |
636 | dma |= VDMD_STREAM; | |
637 | dev_dbg(dev, "16bit bus / stream mode\n"); | |
638 | break; | |
639 | case PACKAGE_24BITBUS_BACK: | |
640 | default: | |
641 | fmt |= CR_BWS_24; | |
642 | dma |= VDMD_BACK; | |
643 | dev_dbg(dev, "24bit bus / package in back\n"); | |
644 | break; | |
645 | } | |
646 | ||
647 | if (is_play) | |
648 | fsi_reg_write(fsi, OUT_DMAC, dma); | |
649 | else | |
650 | fsi_reg_write(fsi, IN_DMAC, dma); | |
651 | } | |
652 | ||
653 | if (is_play) | |
654 | fsi_reg_write(fsi, DO_FMT, fmt); | |
655 | else | |
656 | fsi_reg_write(fsi, DI_FMT, fmt); | |
657 | } | |
658 | ||
c8fe2574 KM |
659 | /* |
660 | * irq function | |
661 | */ | |
a4d7d550 | 662 | |
938e2a8d | 663 | static void fsi_irq_enable(struct fsi_priv *fsi, struct fsi_stream *io) |
a4d7d550 | 664 | { |
938e2a8d | 665 | u32 data = AB_IO(1, fsi_get_port_shift(fsi, io)); |
71f6e064 | 666 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 667 | |
43fa95ca KM |
668 | fsi_core_mask_set(master, imsk, data, data); |
669 | fsi_core_mask_set(master, iemsk, data, data); | |
a4d7d550 KM |
670 | } |
671 | ||
938e2a8d | 672 | static void fsi_irq_disable(struct fsi_priv *fsi, struct fsi_stream *io) |
a4d7d550 | 673 | { |
938e2a8d | 674 | u32 data = AB_IO(1, fsi_get_port_shift(fsi, io)); |
71f6e064 | 675 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 676 | |
43fa95ca KM |
677 | fsi_core_mask_set(master, imsk, data, 0); |
678 | fsi_core_mask_set(master, iemsk, data, 0); | |
a4d7d550 KM |
679 | } |
680 | ||
10ea76cc KM |
681 | static u32 fsi_irq_get_status(struct fsi_master *master) |
682 | { | |
43fa95ca | 683 | return fsi_core_read(master, int_st); |
10ea76cc KM |
684 | } |
685 | ||
10ea76cc KM |
686 | static void fsi_irq_clear_status(struct fsi_priv *fsi) |
687 | { | |
688 | u32 data = 0; | |
689 | struct fsi_master *master = fsi_get_master(fsi); | |
690 | ||
938e2a8d KM |
691 | data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->playback)); |
692 | data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->capture)); | |
10ea76cc KM |
693 | |
694 | /* clear interrupt factor */ | |
43fa95ca | 695 | fsi_core_mask_set(master, int_st, data, 0); |
10ea76cc KM |
696 | } |
697 | ||
c8fe2574 KM |
698 | /* |
699 | * SPDIF master clock function | |
700 | * | |
701 | * These functions are used later FSI2 | |
702 | */ | |
3bc28070 KM |
703 | static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable) |
704 | { | |
705 | struct fsi_master *master = fsi_get_master(fsi); | |
2b0e7302 | 706 | u32 mask, val; |
3bc28070 | 707 | |
2b0e7302 KM |
708 | mask = BP | SE; |
709 | val = enable ? mask : 0; | |
710 | ||
711 | fsi_is_port_a(fsi) ? | |
43fa95ca KM |
712 | fsi_core_mask_set(master, a_mclk, mask, val) : |
713 | fsi_core_mask_set(master, b_mclk, mask, val); | |
3bc28070 KM |
714 | } |
715 | ||
c8fe2574 | 716 | /* |
1f5e2a31 | 717 | * clock function |
c8fe2574 | 718 | */ |
4f56cde1 KM |
719 | static int fsi_set_master_clk(struct device *dev, struct fsi_priv *fsi, |
720 | long rate, int enable) | |
721 | { | |
fec691e7 | 722 | set_rate_func set_rate = fsi_get_info_set_rate(fsi); |
4f56cde1 KM |
723 | int ret; |
724 | ||
fec691e7 KM |
725 | if (!set_rate) |
726 | return 0; | |
727 | ||
728 | ret = set_rate(dev, rate, enable); | |
4f56cde1 KM |
729 | if (ret < 0) /* error */ |
730 | return ret; | |
731 | ||
732 | if (!enable) | |
733 | return 0; | |
734 | ||
735 | if (ret > 0) { | |
736 | u32 data = 0; | |
737 | ||
738 | switch (ret & SH_FSI_ACKMD_MASK) { | |
739 | default: | |
740 | /* FALL THROUGH */ | |
741 | case SH_FSI_ACKMD_512: | |
742 | data |= (0x0 << 12); | |
743 | break; | |
744 | case SH_FSI_ACKMD_256: | |
745 | data |= (0x1 << 12); | |
746 | break; | |
747 | case SH_FSI_ACKMD_128: | |
748 | data |= (0x2 << 12); | |
749 | break; | |
750 | case SH_FSI_ACKMD_64: | |
751 | data |= (0x3 << 12); | |
752 | break; | |
753 | case SH_FSI_ACKMD_32: | |
284c6f65 | 754 | data |= (0x4 << 12); |
4f56cde1 KM |
755 | break; |
756 | } | |
757 | ||
758 | switch (ret & SH_FSI_BPFMD_MASK) { | |
759 | default: | |
760 | /* FALL THROUGH */ | |
761 | case SH_FSI_BPFMD_32: | |
762 | data |= (0x0 << 8); | |
763 | break; | |
764 | case SH_FSI_BPFMD_64: | |
765 | data |= (0x1 << 8); | |
766 | break; | |
767 | case SH_FSI_BPFMD_128: | |
768 | data |= (0x2 << 8); | |
769 | break; | |
770 | case SH_FSI_BPFMD_256: | |
771 | data |= (0x3 << 8); | |
772 | break; | |
773 | case SH_FSI_BPFMD_512: | |
774 | data |= (0x4 << 8); | |
775 | break; | |
776 | case SH_FSI_BPFMD_16: | |
284c6f65 | 777 | data |= (0x7 << 8); |
4f56cde1 KM |
778 | break; |
779 | } | |
780 | ||
781 | fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data); | |
782 | udelay(10); | |
783 | ret = 0; | |
784 | } | |
785 | ||
786 | return ret; | |
4f56cde1 KM |
787 | } |
788 | ||
1f5e2a31 | 789 | /* |
1b0ca1a0 | 790 | * pio data transfer handler |
1f5e2a31 | 791 | */ |
1b0ca1a0 KM |
792 | static void fsi_pio_push16(struct fsi_priv *fsi, u8 *_buf, int samples) |
793 | { | |
766812e6 | 794 | u32 enable_stream = fsi_get_info_flags(fsi) & SH_FSI_ENABLE_STREAM_MODE; |
1b0ca1a0 KM |
795 | int i; |
796 | ||
766812e6 KM |
797 | if (enable_stream) { |
798 | /* | |
799 | * stream mode | |
800 | * see | |
801 | * fsi_pio_push_init() | |
802 | */ | |
803 | u32 *buf = (u32 *)_buf; | |
804 | ||
805 | for (i = 0; i < samples / 2; i++) | |
806 | fsi_reg_write(fsi, DODT, buf[i]); | |
807 | } else { | |
808 | /* normal mode */ | |
809 | u16 *buf = (u16 *)_buf; | |
810 | ||
811 | for (i = 0; i < samples; i++) | |
812 | fsi_reg_write(fsi, DODT, ((u32)*(buf + i) << 8)); | |
813 | } | |
1b0ca1a0 KM |
814 | } |
815 | ||
816 | static void fsi_pio_pop16(struct fsi_priv *fsi, u8 *_buf, int samples) | |
817 | { | |
818 | u16 *buf = (u16 *)_buf; | |
819 | int i; | |
820 | ||
821 | for (i = 0; i < samples; i++) | |
822 | *(buf + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8); | |
823 | } | |
824 | ||
825 | static void fsi_pio_push32(struct fsi_priv *fsi, u8 *_buf, int samples) | |
826 | { | |
827 | u32 *buf = (u32 *)_buf; | |
828 | int i; | |
829 | ||
830 | for (i = 0; i < samples; i++) | |
831 | fsi_reg_write(fsi, DODT, *(buf + i)); | |
832 | } | |
833 | ||
834 | static void fsi_pio_pop32(struct fsi_priv *fsi, u8 *_buf, int samples) | |
835 | { | |
836 | u32 *buf = (u32 *)_buf; | |
837 | int i; | |
838 | ||
839 | for (i = 0; i < samples; i++) | |
840 | *(buf + i) = fsi_reg_read(fsi, DIDT); | |
841 | } | |
842 | ||
843 | static u8 *fsi_pio_get_area(struct fsi_priv *fsi, struct fsi_stream *io) | |
844 | { | |
845 | struct snd_pcm_runtime *runtime = io->substream->runtime; | |
846 | ||
847 | return runtime->dma_area + | |
848 | samples_to_bytes(runtime, io->buff_sample_pos); | |
849 | } | |
850 | ||
851 | static int fsi_pio_transfer(struct fsi_priv *fsi, struct fsi_stream *io, | |
95b0cf05 KM |
852 | void (*run16)(struct fsi_priv *fsi, u8 *buf, int samples), |
853 | void (*run32)(struct fsi_priv *fsi, u8 *buf, int samples), | |
854 | int samples) | |
a4d7d550 KM |
855 | { |
856 | struct snd_pcm_runtime *runtime; | |
376cf38a | 857 | struct snd_pcm_substream *substream; |
95b0cf05 | 858 | u8 *buf; |
b9fde18c | 859 | int over_period; |
a4d7d550 | 860 | |
97df8187 | 861 | if (!fsi_stream_is_working(fsi, io)) |
a4d7d550 KM |
862 | return -EINVAL; |
863 | ||
1c418d1f | 864 | over_period = 0; |
93193c2b | 865 | substream = io->substream; |
1c418d1f | 866 | runtime = substream->runtime; |
a4d7d550 KM |
867 | |
868 | /* FSI FIFO has limit. | |
869 | * So, this driver can not send periods data at a time | |
870 | */ | |
2e651baf KM |
871 | if (io->buff_sample_pos >= |
872 | io->period_samples * (io->period_pos + 1)) { | |
a4d7d550 | 873 | |
1c418d1f | 874 | over_period = 1; |
2e651baf | 875 | io->period_pos = (io->period_pos + 1) % runtime->periods; |
a4d7d550 | 876 | |
2e651baf KM |
877 | if (0 == io->period_pos) |
878 | io->buff_sample_pos = 0; | |
a4d7d550 KM |
879 | } |
880 | ||
95b0cf05 KM |
881 | buf = fsi_pio_get_area(fsi, io); |
882 | ||
376cf38a KM |
883 | switch (io->sample_width) { |
884 | case 2: | |
95b0cf05 | 885 | run16(fsi, buf, samples); |
376cf38a KM |
886 | break; |
887 | case 4: | |
95b0cf05 | 888 | run32(fsi, buf, samples); |
376cf38a KM |
889 | break; |
890 | default: | |
891 | return -EINVAL; | |
d8b33534 | 892 | } |
a4d7d550 | 893 | |
2e651baf KM |
894 | /* update buff_sample_pos */ |
895 | io->buff_sample_pos += samples; | |
a4d7d550 | 896 | |
1c418d1f | 897 | if (over_period) |
a4d7d550 KM |
898 | snd_pcm_period_elapsed(substream); |
899 | ||
47fc9a0a | 900 | return 0; |
a4d7d550 KM |
901 | } |
902 | ||
5e97313a | 903 | static int fsi_pio_pop(struct fsi_priv *fsi, struct fsi_stream *io) |
07102f3c | 904 | { |
376cf38a KM |
905 | int sample_residues; /* samples in FSI fifo */ |
906 | int sample_space; /* ALSA free samples space */ | |
907 | int samples; | |
376cf38a | 908 | |
7b1b3331 | 909 | sample_residues = fsi_get_current_fifo_samples(fsi, io); |
376cf38a KM |
910 | sample_space = io->buff_sample_capa - io->buff_sample_pos; |
911 | ||
912 | samples = min(sample_residues, sample_space); | |
913 | ||
1b0ca1a0 | 914 | return fsi_pio_transfer(fsi, io, |
d78629e2 KM |
915 | fsi_pio_pop16, |
916 | fsi_pio_pop32, | |
376cf38a | 917 | samples); |
d8b33534 | 918 | } |
07102f3c | 919 | |
5e97313a | 920 | static int fsi_pio_push(struct fsi_priv *fsi, struct fsi_stream *io) |
d8b33534 | 921 | { |
376cf38a KM |
922 | int sample_residues; /* ALSA residue samples */ |
923 | int sample_space; /* FSI fifo free samples space */ | |
924 | int samples; | |
376cf38a KM |
925 | |
926 | sample_residues = io->buff_sample_capa - io->buff_sample_pos; | |
927 | sample_space = io->fifo_sample_capa - | |
7b1b3331 | 928 | fsi_get_current_fifo_samples(fsi, io); |
376cf38a KM |
929 | |
930 | samples = min(sample_residues, sample_space); | |
931 | ||
1b0ca1a0 | 932 | return fsi_pio_transfer(fsi, io, |
d78629e2 KM |
933 | fsi_pio_push16, |
934 | fsi_pio_push32, | |
376cf38a | 935 | samples); |
07102f3c KM |
936 | } |
937 | ||
180346ed KM |
938 | static void fsi_pio_start_stop(struct fsi_priv *fsi, struct fsi_stream *io, |
939 | int enable) | |
940 | { | |
941 | struct fsi_master *master = fsi_get_master(fsi); | |
942 | u32 clk = fsi_is_port_a(fsi) ? CRA : CRB; | |
943 | ||
944 | if (enable) | |
945 | fsi_irq_enable(fsi, io); | |
946 | else | |
947 | fsi_irq_disable(fsi, io); | |
948 | ||
949 | if (fsi_is_clk_master(fsi)) | |
950 | fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0); | |
951 | } | |
952 | ||
766812e6 KM |
953 | static int fsi_pio_push_init(struct fsi_priv *fsi, struct fsi_stream *io) |
954 | { | |
955 | u32 enable_stream = fsi_get_info_flags(fsi) & SH_FSI_ENABLE_STREAM_MODE; | |
956 | ||
957 | /* | |
958 | * we can use 16bit stream mode | |
959 | * when "playback" and "16bit data" | |
960 | * and platform allows "stream mode" | |
961 | * see | |
962 | * fsi_pio_push16() | |
963 | */ | |
964 | if (enable_stream) | |
965 | io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | | |
966 | BUSOP_SET(16, PACKAGE_16BITBUS_STREAM); | |
967 | else | |
968 | io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | | |
969 | BUSOP_SET(16, PACKAGE_24BITBUS_BACK); | |
970 | return 0; | |
971 | } | |
972 | ||
973 | static int fsi_pio_pop_init(struct fsi_priv *fsi, struct fsi_stream *io) | |
974 | { | |
975 | /* | |
976 | * always 24bit bus, package back when "capture" | |
977 | */ | |
978 | io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | | |
979 | BUSOP_SET(16, PACKAGE_24BITBUS_BACK); | |
980 | return 0; | |
981 | } | |
982 | ||
5e97313a | 983 | static struct fsi_stream_handler fsi_pio_push_handler = { |
766812e6 | 984 | .init = fsi_pio_push_init, |
5e97313a | 985 | .transfer = fsi_pio_push, |
180346ed | 986 | .start_stop = fsi_pio_start_stop, |
5e97313a KM |
987 | }; |
988 | ||
989 | static struct fsi_stream_handler fsi_pio_pop_handler = { | |
766812e6 | 990 | .init = fsi_pio_pop_init, |
5e97313a | 991 | .transfer = fsi_pio_pop, |
180346ed | 992 | .start_stop = fsi_pio_start_stop, |
5e97313a KM |
993 | }; |
994 | ||
a4d7d550 KM |
995 | static irqreturn_t fsi_interrupt(int irq, void *data) |
996 | { | |
71f6e064 | 997 | struct fsi_master *master = data; |
10ea76cc | 998 | u32 int_st = fsi_irq_get_status(master); |
a4d7d550 KM |
999 | |
1000 | /* clear irq status */ | |
feb58cff KM |
1001 | fsi_master_mask_set(master, SOFT_RST, IR, 0); |
1002 | fsi_master_mask_set(master, SOFT_RST, IR, IR); | |
a4d7d550 | 1003 | |
cf6edd00 | 1004 | if (int_st & AB_IO(1, AO_SHIFT)) |
5e97313a | 1005 | fsi_stream_transfer(&master->fsia.playback); |
cf6edd00 | 1006 | if (int_st & AB_IO(1, BO_SHIFT)) |
5e97313a | 1007 | fsi_stream_transfer(&master->fsib.playback); |
cf6edd00 | 1008 | if (int_st & AB_IO(1, AI_SHIFT)) |
5e97313a | 1009 | fsi_stream_transfer(&master->fsia.capture); |
cf6edd00 | 1010 | if (int_st & AB_IO(1, BI_SHIFT)) |
5e97313a | 1011 | fsi_stream_transfer(&master->fsib.capture); |
1ec9bc35 KM |
1012 | |
1013 | fsi_count_fifo_err(&master->fsia); | |
1014 | fsi_count_fifo_err(&master->fsib); | |
a4d7d550 | 1015 | |
48d78e58 KM |
1016 | fsi_irq_clear_status(&master->fsia); |
1017 | fsi_irq_clear_status(&master->fsib); | |
a4d7d550 KM |
1018 | |
1019 | return IRQ_HANDLED; | |
1020 | } | |
1021 | ||
7da9ced6 KM |
1022 | /* |
1023 | * dma data transfer handler | |
1024 | */ | |
1025 | static int fsi_dma_init(struct fsi_priv *fsi, struct fsi_stream *io) | |
1026 | { | |
1027 | struct snd_pcm_runtime *runtime = io->substream->runtime; | |
1028 | struct snd_soc_dai *dai = fsi_get_dai(io->substream); | |
1029 | enum dma_data_direction dir = fsi_stream_is_play(fsi, io) ? | |
1030 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
1031 | ||
766812e6 KM |
1032 | /* |
1033 | * 24bit data : 24bit bus / package in back | |
1034 | * 16bit data : 16bit bus / stream mode | |
1035 | */ | |
1036 | io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | | |
1037 | BUSOP_SET(16, PACKAGE_16BITBUS_STREAM); | |
1038 | ||
7da9ced6 KM |
1039 | io->dma = dma_map_single(dai->dev, runtime->dma_area, |
1040 | snd_pcm_lib_buffer_bytes(io->substream), dir); | |
1041 | return 0; | |
1042 | } | |
1043 | ||
1044 | static int fsi_dma_quit(struct fsi_priv *fsi, struct fsi_stream *io) | |
1045 | { | |
1046 | struct snd_soc_dai *dai = fsi_get_dai(io->substream); | |
1047 | enum dma_data_direction dir = fsi_stream_is_play(fsi, io) ? | |
1048 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
1049 | ||
1050 | dma_unmap_single(dai->dev, io->dma, | |
1051 | snd_pcm_lib_buffer_bytes(io->substream), dir); | |
1052 | return 0; | |
1053 | } | |
1054 | ||
4a1b09b7 KM |
1055 | static dma_addr_t fsi_dma_get_area(struct fsi_stream *io) |
1056 | { | |
1057 | struct snd_pcm_runtime *runtime = io->substream->runtime; | |
1058 | ||
1059 | return io->dma + samples_to_bytes(runtime, io->buff_sample_pos); | |
1060 | } | |
1061 | ||
7da9ced6 KM |
1062 | static void fsi_dma_complete(void *data) |
1063 | { | |
1064 | struct fsi_stream *io = (struct fsi_stream *)data; | |
1065 | struct fsi_priv *fsi = fsi_stream_to_priv(io); | |
1066 | struct snd_pcm_runtime *runtime = io->substream->runtime; | |
1067 | struct snd_soc_dai *dai = fsi_get_dai(io->substream); | |
1068 | enum dma_data_direction dir = fsi_stream_is_play(fsi, io) ? | |
1069 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
1070 | ||
4a1b09b7 | 1071 | dma_sync_single_for_cpu(dai->dev, fsi_dma_get_area(io), |
7da9ced6 KM |
1072 | samples_to_bytes(runtime, io->period_samples), dir); |
1073 | ||
1074 | io->buff_sample_pos += io->period_samples; | |
1075 | io->period_pos++; | |
1076 | ||
1077 | if (io->period_pos >= runtime->periods) { | |
1078 | io->period_pos = 0; | |
1079 | io->buff_sample_pos = 0; | |
1080 | } | |
1081 | ||
1082 | fsi_count_fifo_err(fsi); | |
1083 | fsi_stream_transfer(io); | |
1084 | ||
1085 | snd_pcm_period_elapsed(io->substream); | |
1086 | } | |
1087 | ||
7da9ced6 KM |
1088 | static void fsi_dma_do_tasklet(unsigned long data) |
1089 | { | |
1090 | struct fsi_stream *io = (struct fsi_stream *)data; | |
1091 | struct fsi_priv *fsi = fsi_stream_to_priv(io); | |
7da9ced6 KM |
1092 | struct snd_soc_dai *dai; |
1093 | struct dma_async_tx_descriptor *desc; | |
7da9ced6 KM |
1094 | struct snd_pcm_runtime *runtime; |
1095 | enum dma_data_direction dir; | |
7da9ced6 KM |
1096 | int is_play = fsi_stream_is_play(fsi, io); |
1097 | int len; | |
1098 | dma_addr_t buf; | |
1099 | ||
1100 | if (!fsi_stream_is_working(fsi, io)) | |
1101 | return; | |
1102 | ||
1103 | dai = fsi_get_dai(io->substream); | |
7da9ced6 KM |
1104 | runtime = io->substream->runtime; |
1105 | dir = is_play ? DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
1106 | len = samples_to_bytes(runtime, io->period_samples); | |
1107 | buf = fsi_dma_get_area(io); | |
1108 | ||
4a1b09b7 | 1109 | dma_sync_single_for_device(dai->dev, buf, len, dir); |
7da9ced6 | 1110 | |
5514efdf KM |
1111 | desc = dmaengine_prep_slave_single(io->chan, buf, len, dir, |
1112 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
7da9ced6 | 1113 | if (!desc) { |
cdf27f37 | 1114 | dev_err(dai->dev, "dmaengine_prep_slave_sg() fail\n"); |
7da9ced6 KM |
1115 | return; |
1116 | } | |
1117 | ||
1118 | desc->callback = fsi_dma_complete; | |
1119 | desc->callback_param = io; | |
1120 | ||
5514efdf | 1121 | if (dmaengine_submit(desc) < 0) { |
7da9ced6 KM |
1122 | dev_err(dai->dev, "tx_submit() fail\n"); |
1123 | return; | |
1124 | } | |
1125 | ||
5514efdf | 1126 | dma_async_issue_pending(io->chan); |
7da9ced6 KM |
1127 | |
1128 | /* | |
1129 | * FIXME | |
1130 | * | |
1131 | * In DMAEngine case, codec and FSI cannot be started simultaneously | |
1132 | * since FSI is using tasklet. | |
1133 | * Therefore, in capture case, probably FSI FIFO will have got | |
1134 | * overflow error in this point. | |
1135 | * in that case, DMA cannot start transfer until error was cleared. | |
1136 | */ | |
1137 | if (!is_play) { | |
1138 | if (ERR_OVER & fsi_reg_read(fsi, DIFF_ST)) { | |
1139 | fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR); | |
1140 | fsi_reg_write(fsi, DIFF_ST, 0); | |
1141 | } | |
1142 | } | |
1143 | } | |
1144 | ||
1145 | static bool fsi_dma_filter(struct dma_chan *chan, void *param) | |
1146 | { | |
1147 | struct sh_dmae_slave *slave = param; | |
1148 | ||
1149 | chan->private = slave; | |
1150 | ||
1151 | return true; | |
1152 | } | |
1153 | ||
1154 | static int fsi_dma_transfer(struct fsi_priv *fsi, struct fsi_stream *io) | |
1155 | { | |
1156 | tasklet_schedule(&io->tasklet); | |
1157 | ||
1158 | return 0; | |
1159 | } | |
1160 | ||
1161 | static void fsi_dma_push_start_stop(struct fsi_priv *fsi, struct fsi_stream *io, | |
1162 | int start) | |
1163 | { | |
e42bb9bf KM |
1164 | struct fsi_master *master = fsi_get_master(fsi); |
1165 | u32 clk = fsi_is_port_a(fsi) ? CRA : CRB; | |
766812e6 | 1166 | u32 enable = start ? DMA_ON : 0; |
7da9ced6 | 1167 | |
766812e6 | 1168 | fsi_reg_mask_set(fsi, OUT_DMAC, DMA_ON, enable); |
e42bb9bf | 1169 | |
fbe42f66 KM |
1170 | dmaengine_terminate_all(io->chan); |
1171 | ||
e42bb9bf KM |
1172 | if (fsi_is_clk_master(fsi)) |
1173 | fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0); | |
7da9ced6 KM |
1174 | } |
1175 | ||
b1226dc5 | 1176 | static int fsi_dma_probe(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev) |
7da9ced6 KM |
1177 | { |
1178 | dma_cap_mask_t mask; | |
1179 | ||
1180 | dma_cap_zero(mask); | |
1181 | dma_cap_set(DMA_SLAVE, mask); | |
1182 | ||
1183 | io->chan = dma_request_channel(mask, fsi_dma_filter, &io->slave); | |
b1226dc5 KM |
1184 | if (!io->chan) { |
1185 | ||
1186 | /* switch to PIO handler */ | |
1187 | if (fsi_stream_is_play(fsi, io)) | |
1188 | fsi->playback.handler = &fsi_pio_push_handler; | |
1189 | else | |
1190 | fsi->capture.handler = &fsi_pio_pop_handler; | |
1191 | ||
1192 | dev_info(dev, "switch handler (dma => pio)\n"); | |
1193 | ||
1194 | /* probe again */ | |
1195 | return fsi_stream_probe(fsi, dev); | |
1196 | } | |
7da9ced6 KM |
1197 | |
1198 | tasklet_init(&io->tasklet, fsi_dma_do_tasklet, (unsigned long)io); | |
1199 | ||
1200 | return 0; | |
1201 | } | |
1202 | ||
1203 | static int fsi_dma_remove(struct fsi_priv *fsi, struct fsi_stream *io) | |
1204 | { | |
1205 | tasklet_kill(&io->tasklet); | |
1206 | ||
1207 | fsi_stream_stop(fsi, io); | |
1208 | ||
1209 | if (io->chan) | |
1210 | dma_release_channel(io->chan); | |
1211 | ||
1212 | io->chan = NULL; | |
1213 | return 0; | |
1214 | } | |
1215 | ||
1216 | static struct fsi_stream_handler fsi_dma_push_handler = { | |
1217 | .init = fsi_dma_init, | |
1218 | .quit = fsi_dma_quit, | |
1219 | .probe = fsi_dma_probe, | |
1220 | .transfer = fsi_dma_transfer, | |
1221 | .remove = fsi_dma_remove, | |
1222 | .start_stop = fsi_dma_push_start_stop, | |
1223 | }; | |
1224 | ||
c8fe2574 KM |
1225 | /* |
1226 | * dai ops | |
1227 | */ | |
b49e8027 | 1228 | static void fsi_fifo_init(struct fsi_priv *fsi, |
938e2a8d | 1229 | struct fsi_stream *io, |
b49e8027 KM |
1230 | struct device *dev) |
1231 | { | |
1232 | struct fsi_master *master = fsi_get_master(fsi); | |
938e2a8d | 1233 | int is_play = fsi_stream_is_play(fsi, io); |
b49e8027 KM |
1234 | u32 shift, i; |
1235 | int frame_capa; | |
1236 | ||
1237 | /* get on-chip RAM capacity */ | |
1238 | shift = fsi_master_read(master, FIFO_SZ); | |
938e2a8d | 1239 | shift >>= fsi_get_port_shift(fsi, io); |
b49e8027 KM |
1240 | shift &= FIFO_SZ_MASK; |
1241 | frame_capa = 256 << shift; | |
1242 | dev_dbg(dev, "fifo = %d words\n", frame_capa); | |
1243 | ||
1244 | /* | |
1245 | * The maximum number of sample data varies depending | |
1246 | * on the number of channels selected for the format. | |
1247 | * | |
1248 | * FIFOs are used in 4-channel units in 3-channel mode | |
1249 | * and in 8-channel units in 5- to 7-channel mode | |
1250 | * meaning that more FIFOs than the required size of DPRAM | |
1251 | * are used. | |
1252 | * | |
1253 | * ex) if 256 words of DP-RAM is connected | |
1254 | * 1 channel: 256 (256 x 1 = 256) | |
1255 | * 2 channels: 128 (128 x 2 = 256) | |
1256 | * 3 channels: 64 ( 64 x 3 = 192) | |
1257 | * 4 channels: 64 ( 64 x 4 = 256) | |
1258 | * 5 channels: 32 ( 32 x 5 = 160) | |
1259 | * 6 channels: 32 ( 32 x 6 = 192) | |
1260 | * 7 channels: 32 ( 32 x 7 = 224) | |
1261 | * 8 channels: 32 ( 32 x 8 = 256) | |
1262 | */ | |
1263 | for (i = 1; i < fsi->chan_num; i <<= 1) | |
1264 | frame_capa >>= 1; | |
1265 | dev_dbg(dev, "%d channel %d store\n", | |
1266 | fsi->chan_num, frame_capa); | |
1267 | ||
1268 | io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa); | |
1269 | ||
1270 | /* | |
1271 | * set interrupt generation factor | |
1272 | * clear FIFO | |
1273 | */ | |
1274 | if (is_play) { | |
1275 | fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF); | |
1276 | fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR); | |
1277 | } else { | |
1278 | fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF); | |
1279 | fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR); | |
1280 | } | |
1281 | } | |
a4d7d550 | 1282 | |
23ca8533 | 1283 | static int fsi_hw_startup(struct fsi_priv *fsi, |
938e2a8d | 1284 | struct fsi_stream *io, |
23ca8533 | 1285 | struct device *dev) |
a4d7d550 | 1286 | { |
93193c2b | 1287 | u32 flags = fsi_get_info_flags(fsi); |
9478e0b6 | 1288 | u32 data = 0; |
a4d7d550 | 1289 | |
9478e0b6 KM |
1290 | /* clock setting */ |
1291 | if (fsi_is_clk_master(fsi)) | |
1292 | data = DIMD | DOMD; | |
1293 | ||
1294 | fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data); | |
a4d7d550 KM |
1295 | |
1296 | /* clock inversion (CKG2) */ | |
1297 | data = 0; | |
b427b44c KM |
1298 | if (SH_FSI_LRM_INV & flags) |
1299 | data |= 1 << 12; | |
1300 | if (SH_FSI_BRM_INV & flags) | |
1301 | data |= 1 << 8; | |
1302 | if (SH_FSI_LRS_INV & flags) | |
1303 | data |= 1 << 4; | |
1304 | if (SH_FSI_BRS_INV & flags) | |
1305 | data |= 1 << 0; | |
1306 | ||
a4d7d550 KM |
1307 | fsi_reg_write(fsi, CKG2, data); |
1308 | ||
9478e0b6 KM |
1309 | /* spdif ? */ |
1310 | if (fsi_is_spdif(fsi)) { | |
1311 | fsi_spdif_clk_ctrl(fsi, 1); | |
1312 | fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD); | |
1313 | } | |
1314 | ||
65ff03f4 | 1315 | /* |
766812e6 | 1316 | * get bus settings |
65ff03f4 | 1317 | */ |
766812e6 KM |
1318 | data = 0; |
1319 | switch (io->sample_width) { | |
1320 | case 2: | |
1321 | data = BUSOP_GET(16, io->bus_option); | |
1322 | break; | |
1323 | case 4: | |
1324 | data = BUSOP_GET(24, io->bus_option); | |
1325 | break; | |
65ff03f4 | 1326 | } |
766812e6 | 1327 | fsi_format_bus_setup(fsi, io, data, dev); |
65ff03f4 | 1328 | |
10ea76cc | 1329 | /* irq clear */ |
938e2a8d | 1330 | fsi_irq_disable(fsi, io); |
10ea76cc KM |
1331 | fsi_irq_clear_status(fsi); |
1332 | ||
1333 | /* fifo init */ | |
938e2a8d | 1334 | fsi_fifo_init(fsi, io, dev); |
a4d7d550 | 1335 | |
a68a3b4e | 1336 | return 0; |
a4d7d550 KM |
1337 | } |
1338 | ||
23ca8533 | 1339 | static void fsi_hw_shutdown(struct fsi_priv *fsi, |
23ca8533 KM |
1340 | struct device *dev) |
1341 | { | |
1342 | if (fsi_is_clk_master(fsi)) | |
1343 | fsi_set_master_clk(dev, fsi, fsi->rate, 0); | |
23ca8533 KM |
1344 | } |
1345 | ||
1346 | static int fsi_dai_startup(struct snd_pcm_substream *substream, | |
1347 | struct snd_soc_dai *dai) | |
1348 | { | |
1349 | struct fsi_priv *fsi = fsi_get_priv(substream); | |
23ca8533 | 1350 | |
f33238e9 KM |
1351 | fsi->rate = 0; |
1352 | ||
1353 | return 0; | |
23ca8533 KM |
1354 | } |
1355 | ||
a4d7d550 KM |
1356 | static void fsi_dai_shutdown(struct snd_pcm_substream *substream, |
1357 | struct snd_soc_dai *dai) | |
1358 | { | |
71f6e064 | 1359 | struct fsi_priv *fsi = fsi_get_priv(substream); |
a4d7d550 | 1360 | |
d4bc99b9 | 1361 | fsi->rate = 0; |
a4d7d550 KM |
1362 | } |
1363 | ||
1364 | static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd, | |
1365 | struct snd_soc_dai *dai) | |
1366 | { | |
71f6e064 | 1367 | struct fsi_priv *fsi = fsi_get_priv(substream); |
938e2a8d | 1368 | struct fsi_stream *io = fsi_stream_get(fsi, substream); |
a4d7d550 KM |
1369 | int ret = 0; |
1370 | ||
a4d7d550 KM |
1371 | switch (cmd) { |
1372 | case SNDRV_PCM_TRIGGER_START: | |
938e2a8d | 1373 | fsi_stream_init(fsi, io, substream); |
f33238e9 | 1374 | fsi_hw_startup(fsi, io, dai->dev); |
5e97313a KM |
1375 | ret = fsi_stream_transfer(io); |
1376 | if (0 == ret) | |
180346ed | 1377 | fsi_stream_start(fsi, io); |
a4d7d550 KM |
1378 | break; |
1379 | case SNDRV_PCM_TRIGGER_STOP: | |
f33238e9 | 1380 | fsi_hw_shutdown(fsi, dai->dev); |
180346ed | 1381 | fsi_stream_stop(fsi, io); |
938e2a8d | 1382 | fsi_stream_quit(fsi, io); |
a4d7d550 KM |
1383 | break; |
1384 | } | |
1385 | ||
1386 | return ret; | |
1387 | } | |
1388 | ||
f17c13ca KM |
1389 | static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt) |
1390 | { | |
f17c13ca KM |
1391 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
1392 | case SND_SOC_DAIFMT_I2S: | |
9c59dd34 | 1393 | fsi->fmt = CR_I2S; |
f17c13ca KM |
1394 | fsi->chan_num = 2; |
1395 | break; | |
1396 | case SND_SOC_DAIFMT_LEFT_J: | |
9c59dd34 | 1397 | fsi->fmt = CR_PCM; |
f17c13ca KM |
1398 | fsi->chan_num = 2; |
1399 | break; | |
1400 | default: | |
1401 | return -EINVAL; | |
1402 | } | |
1403 | ||
f17c13ca KM |
1404 | return 0; |
1405 | } | |
1406 | ||
1407 | static int fsi_set_fmt_spdif(struct fsi_priv *fsi) | |
1408 | { | |
1409 | struct fsi_master *master = fsi_get_master(fsi); | |
f17c13ca | 1410 | |
284c6f65 | 1411 | if (fsi_version(master) < 2) |
f17c13ca KM |
1412 | return -EINVAL; |
1413 | ||
766812e6 | 1414 | fsi->fmt = CR_DTMD_SPDIF_PCM | CR_PCM; |
f17c13ca | 1415 | fsi->chan_num = 2; |
9478e0b6 | 1416 | fsi->spdif = 1; |
f17c13ca | 1417 | |
f17c13ca KM |
1418 | return 0; |
1419 | } | |
1420 | ||
4d805f7b KM |
1421 | static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) |
1422 | { | |
1423 | struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai); | |
fec691e7 | 1424 | set_rate_func set_rate = fsi_get_info_set_rate(fsi); |
f17c13ca | 1425 | u32 flags = fsi_get_info_flags(fsi); |
4d805f7b KM |
1426 | int ret; |
1427 | ||
4d805f7b KM |
1428 | /* set master/slave audio interface */ |
1429 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1430 | case SND_SOC_DAIFMT_CBM_CFM: | |
6a9ebad8 | 1431 | fsi->clk_master = 1; |
4d805f7b KM |
1432 | break; |
1433 | case SND_SOC_DAIFMT_CBS_CFS: | |
1434 | break; | |
1435 | default: | |
9478e0b6 | 1436 | return -EINVAL; |
4d805f7b | 1437 | } |
6a9ebad8 KM |
1438 | |
1439 | if (fsi_is_clk_master(fsi) && !set_rate) { | |
1440 | dev_err(dai->dev, "platform doesn't have set_rate\n"); | |
9478e0b6 | 1441 | return -EINVAL; |
6a9ebad8 KM |
1442 | } |
1443 | ||
f17c13ca KM |
1444 | /* set format */ |
1445 | switch (flags & SH_FSI_FMT_MASK) { | |
1446 | case SH_FSI_FMT_DAI: | |
1447 | ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK); | |
1448 | break; | |
1449 | case SH_FSI_FMT_SPDIF: | |
1450 | ret = fsi_set_fmt_spdif(fsi); | |
1451 | break; | |
1452 | default: | |
1453 | ret = -EINVAL; | |
1454 | } | |
4d805f7b | 1455 | |
4d805f7b KM |
1456 | return ret; |
1457 | } | |
1458 | ||
ccad7b44 KM |
1459 | static int fsi_dai_hw_params(struct snd_pcm_substream *substream, |
1460 | struct snd_pcm_hw_params *params, | |
1461 | struct snd_soc_dai *dai) | |
1462 | { | |
1463 | struct fsi_priv *fsi = fsi_get_priv(substream); | |
d4bc99b9 | 1464 | long rate = params_rate(params); |
ccad7b44 KM |
1465 | int ret; |
1466 | ||
6a9ebad8 | 1467 | if (!fsi_is_clk_master(fsi)) |
ccad7b44 KM |
1468 | return 0; |
1469 | ||
4f56cde1 KM |
1470 | ret = fsi_set_master_clk(dai->dev, fsi, rate, 1); |
1471 | if (ret < 0) | |
d4bc99b9 | 1472 | return ret; |
ccad7b44 | 1473 | |
d4bc99b9 | 1474 | fsi->rate = rate; |
ccad7b44 KM |
1475 | |
1476 | return ret; | |
ccad7b44 KM |
1477 | } |
1478 | ||
85e7652d | 1479 | static const struct snd_soc_dai_ops fsi_dai_ops = { |
a4d7d550 KM |
1480 | .startup = fsi_dai_startup, |
1481 | .shutdown = fsi_dai_shutdown, | |
1482 | .trigger = fsi_dai_trigger, | |
4d805f7b | 1483 | .set_fmt = fsi_dai_set_fmt, |
ccad7b44 | 1484 | .hw_params = fsi_dai_hw_params, |
a4d7d550 KM |
1485 | }; |
1486 | ||
c8fe2574 KM |
1487 | /* |
1488 | * pcm ops | |
1489 | */ | |
a4d7d550 | 1490 | |
a4d7d550 KM |
1491 | static struct snd_pcm_hardware fsi_pcm_hardware = { |
1492 | .info = SNDRV_PCM_INFO_INTERLEAVED | | |
1493 | SNDRV_PCM_INFO_MMAP | | |
1494 | SNDRV_PCM_INFO_MMAP_VALID | | |
1495 | SNDRV_PCM_INFO_PAUSE, | |
1496 | .formats = FSI_FMTS, | |
1497 | .rates = FSI_RATES, | |
1498 | .rate_min = 8000, | |
1499 | .rate_max = 192000, | |
1500 | .channels_min = 1, | |
1501 | .channels_max = 2, | |
1502 | .buffer_bytes_max = 64 * 1024, | |
1503 | .period_bytes_min = 32, | |
1504 | .period_bytes_max = 8192, | |
1505 | .periods_min = 1, | |
1506 | .periods_max = 32, | |
1507 | .fifo_size = 256, | |
1508 | }; | |
1509 | ||
1510 | static int fsi_pcm_open(struct snd_pcm_substream *substream) | |
1511 | { | |
1512 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1513 | int ret = 0; | |
1514 | ||
1515 | snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware); | |
1516 | ||
1517 | ret = snd_pcm_hw_constraint_integer(runtime, | |
1518 | SNDRV_PCM_HW_PARAM_PERIODS); | |
1519 | ||
1520 | return ret; | |
1521 | } | |
1522 | ||
1523 | static int fsi_hw_params(struct snd_pcm_substream *substream, | |
1524 | struct snd_pcm_hw_params *hw_params) | |
1525 | { | |
1526 | return snd_pcm_lib_malloc_pages(substream, | |
1527 | params_buffer_bytes(hw_params)); | |
1528 | } | |
1529 | ||
1530 | static int fsi_hw_free(struct snd_pcm_substream *substream) | |
1531 | { | |
1532 | return snd_pcm_lib_free_pages(substream); | |
1533 | } | |
1534 | ||
1535 | static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream) | |
1536 | { | |
71f6e064 | 1537 | struct fsi_priv *fsi = fsi_get_priv(substream); |
938e2a8d | 1538 | struct fsi_stream *io = fsi_stream_get(fsi, substream); |
a4d7d550 | 1539 | |
1987877d | 1540 | return fsi_sample2frame(fsi, io->buff_sample_pos); |
a4d7d550 KM |
1541 | } |
1542 | ||
1543 | static struct snd_pcm_ops fsi_pcm_ops = { | |
1544 | .open = fsi_pcm_open, | |
1545 | .ioctl = snd_pcm_lib_ioctl, | |
1546 | .hw_params = fsi_hw_params, | |
1547 | .hw_free = fsi_hw_free, | |
1548 | .pointer = fsi_pointer, | |
1549 | }; | |
1550 | ||
c8fe2574 KM |
1551 | /* |
1552 | * snd_soc_platform | |
1553 | */ | |
a4d7d550 | 1554 | |
a4d7d550 KM |
1555 | #define PREALLOC_BUFFER (32 * 1024) |
1556 | #define PREALLOC_BUFFER_MAX (32 * 1024) | |
1557 | ||
1558 | static void fsi_pcm_free(struct snd_pcm *pcm) | |
1559 | { | |
1560 | snd_pcm_lib_preallocate_free_for_all(pcm); | |
1561 | } | |
1562 | ||
552d1ef6 | 1563 | static int fsi_pcm_new(struct snd_soc_pcm_runtime *rtd) |
a4d7d550 | 1564 | { |
552d1ef6 LG |
1565 | struct snd_pcm *pcm = rtd->pcm; |
1566 | ||
a4d7d550 KM |
1567 | /* |
1568 | * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel | |
1569 | * in MMAP mode (i.e. aplay -M) | |
1570 | */ | |
1571 | return snd_pcm_lib_preallocate_pages_for_all( | |
1572 | pcm, | |
1573 | SNDRV_DMA_TYPE_CONTINUOUS, | |
1574 | snd_dma_continuous_data(GFP_KERNEL), | |
1575 | PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); | |
1576 | } | |
1577 | ||
c8fe2574 KM |
1578 | /* |
1579 | * alsa struct | |
1580 | */ | |
a4d7d550 | 1581 | |
f0fba2ad | 1582 | static struct snd_soc_dai_driver fsi_soc_dai[] = { |
a4d7d550 | 1583 | { |
f0fba2ad | 1584 | .name = "fsia-dai", |
a4d7d550 KM |
1585 | .playback = { |
1586 | .rates = FSI_RATES, | |
1587 | .formats = FSI_FMTS, | |
1588 | .channels_min = 1, | |
1589 | .channels_max = 8, | |
1590 | }, | |
07102f3c KM |
1591 | .capture = { |
1592 | .rates = FSI_RATES, | |
1593 | .formats = FSI_FMTS, | |
1594 | .channels_min = 1, | |
1595 | .channels_max = 8, | |
1596 | }, | |
a4d7d550 KM |
1597 | .ops = &fsi_dai_ops, |
1598 | }, | |
1599 | { | |
f0fba2ad | 1600 | .name = "fsib-dai", |
a4d7d550 KM |
1601 | .playback = { |
1602 | .rates = FSI_RATES, | |
1603 | .formats = FSI_FMTS, | |
1604 | .channels_min = 1, | |
1605 | .channels_max = 8, | |
1606 | }, | |
07102f3c KM |
1607 | .capture = { |
1608 | .rates = FSI_RATES, | |
1609 | .formats = FSI_FMTS, | |
1610 | .channels_min = 1, | |
1611 | .channels_max = 8, | |
1612 | }, | |
a4d7d550 KM |
1613 | .ops = &fsi_dai_ops, |
1614 | }, | |
1615 | }; | |
a4d7d550 | 1616 | |
f0fba2ad LG |
1617 | static struct snd_soc_platform_driver fsi_soc_platform = { |
1618 | .ops = &fsi_pcm_ops, | |
a4d7d550 KM |
1619 | .pcm_new = fsi_pcm_new, |
1620 | .pcm_free = fsi_pcm_free, | |
1621 | }; | |
a4d7d550 | 1622 | |
c8fe2574 KM |
1623 | /* |
1624 | * platform function | |
1625 | */ | |
5e97313a KM |
1626 | static void fsi_handler_init(struct fsi_priv *fsi) |
1627 | { | |
1628 | fsi->playback.handler = &fsi_pio_push_handler; /* default PIO */ | |
1629 | fsi->playback.priv = fsi; | |
1630 | fsi->capture.handler = &fsi_pio_pop_handler; /* default PIO */ | |
1631 | fsi->capture.priv = fsi; | |
7da9ced6 KM |
1632 | |
1633 | if (fsi->info->tx_id) { | |
b8373147 GL |
1634 | fsi->playback.slave.shdma_slave.slave_id = fsi->info->tx_id; |
1635 | fsi->playback.handler = &fsi_dma_push_handler; | |
7da9ced6 | 1636 | } |
5e97313a | 1637 | } |
a4d7d550 | 1638 | |
a4d7d550 KM |
1639 | static int fsi_probe(struct platform_device *pdev) |
1640 | { | |
71f6e064 | 1641 | struct fsi_master *master; |
cc780d38 | 1642 | const struct platform_device_id *id_entry; |
fec691e7 | 1643 | struct sh_fsi_platform_info *info = pdev->dev.platform_data; |
a4d7d550 | 1644 | struct resource *res; |
a4d7d550 KM |
1645 | unsigned int irq; |
1646 | int ret; | |
1647 | ||
cc780d38 KM |
1648 | id_entry = pdev->id_entry; |
1649 | if (!id_entry) { | |
1650 | dev_err(&pdev->dev, "unknown fsi device\n"); | |
1651 | return -ENODEV; | |
1652 | } | |
1653 | ||
a4d7d550 KM |
1654 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1655 | irq = platform_get_irq(pdev, 0); | |
b6aa1793 | 1656 | if (!res || (int)irq <= 0) { |
a4d7d550 KM |
1657 | dev_err(&pdev->dev, "Not enough FSI platform resources.\n"); |
1658 | ret = -ENODEV; | |
1659 | goto exit; | |
1660 | } | |
1661 | ||
1662 | master = kzalloc(sizeof(*master), GFP_KERNEL); | |
1663 | if (!master) { | |
1664 | dev_err(&pdev->dev, "Could not allocate master\n"); | |
1665 | ret = -ENOMEM; | |
1666 | goto exit; | |
1667 | } | |
1668 | ||
1669 | master->base = ioremap_nocache(res->start, resource_size(res)); | |
1670 | if (!master->base) { | |
1671 | ret = -ENXIO; | |
1672 | dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n"); | |
1673 | goto exit_kfree; | |
1674 | } | |
1675 | ||
3bc28070 | 1676 | /* master setting */ |
a4d7d550 | 1677 | master->irq = irq; |
3bc28070 KM |
1678 | master->core = (struct fsi_core *)id_entry->driver_data; |
1679 | spin_lock_init(&master->lock); | |
1680 | ||
1681 | /* FSI A setting */ | |
a4d7d550 | 1682 | master->fsia.base = master->base; |
71f6e064 | 1683 | master->fsia.master = master; |
fec691e7 | 1684 | master->fsia.info = &info->port_a; |
5e97313a | 1685 | fsi_handler_init(&master->fsia); |
b1226dc5 | 1686 | ret = fsi_stream_probe(&master->fsia, &pdev->dev); |
5e97313a KM |
1687 | if (ret < 0) { |
1688 | dev_err(&pdev->dev, "FSIA stream probe failed\n"); | |
1689 | goto exit_iounmap; | |
1690 | } | |
3bc28070 KM |
1691 | |
1692 | /* FSI B setting */ | |
a4d7d550 | 1693 | master->fsib.base = master->base + 0x40; |
71f6e064 | 1694 | master->fsib.master = master; |
fec691e7 | 1695 | master->fsib.info = &info->port_b; |
5e97313a | 1696 | fsi_handler_init(&master->fsib); |
b1226dc5 | 1697 | ret = fsi_stream_probe(&master->fsib, &pdev->dev); |
5e97313a KM |
1698 | if (ret < 0) { |
1699 | dev_err(&pdev->dev, "FSIB stream probe failed\n"); | |
1700 | goto exit_fsia; | |
1701 | } | |
a4d7d550 | 1702 | |
785d1c45 | 1703 | pm_runtime_enable(&pdev->dev); |
f0fba2ad | 1704 | dev_set_drvdata(&pdev->dev, master); |
a4d7d550 | 1705 | |
88e24c3a | 1706 | ret = request_irq(irq, &fsi_interrupt, 0, |
cc780d38 | 1707 | id_entry->name, master); |
a4d7d550 KM |
1708 | if (ret) { |
1709 | dev_err(&pdev->dev, "irq request err\n"); | |
5e97313a | 1710 | goto exit_fsib; |
a4d7d550 KM |
1711 | } |
1712 | ||
f0fba2ad | 1713 | ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform); |
a4d7d550 KM |
1714 | if (ret < 0) { |
1715 | dev_err(&pdev->dev, "cannot snd soc register\n"); | |
1716 | goto exit_free_irq; | |
1717 | } | |
1718 | ||
0b5ec87d KM |
1719 | ret = snd_soc_register_dais(&pdev->dev, fsi_soc_dai, |
1720 | ARRAY_SIZE(fsi_soc_dai)); | |
1721 | if (ret < 0) { | |
1722 | dev_err(&pdev->dev, "cannot snd dai register\n"); | |
1723 | goto exit_snd_soc; | |
1724 | } | |
a4d7d550 | 1725 | |
0b5ec87d KM |
1726 | return ret; |
1727 | ||
1728 | exit_snd_soc: | |
1729 | snd_soc_unregister_platform(&pdev->dev); | |
a4d7d550 KM |
1730 | exit_free_irq: |
1731 | free_irq(irq, master); | |
5e97313a KM |
1732 | exit_fsib: |
1733 | fsi_stream_remove(&master->fsib); | |
1734 | exit_fsia: | |
1735 | fsi_stream_remove(&master->fsia); | |
a4d7d550 KM |
1736 | exit_iounmap: |
1737 | iounmap(master->base); | |
785d1c45 | 1738 | pm_runtime_disable(&pdev->dev); |
a4d7d550 KM |
1739 | exit_kfree: |
1740 | kfree(master); | |
1741 | master = NULL; | |
1742 | exit: | |
1743 | return ret; | |
1744 | } | |
1745 | ||
1746 | static int fsi_remove(struct platform_device *pdev) | |
1747 | { | |
71f6e064 KM |
1748 | struct fsi_master *master; |
1749 | ||
f0fba2ad | 1750 | master = dev_get_drvdata(&pdev->dev); |
71f6e064 | 1751 | |
d985f27e | 1752 | free_irq(master->irq, master); |
785d1c45 | 1753 | pm_runtime_disable(&pdev->dev); |
a4d7d550 | 1754 | |
d985f27e KM |
1755 | snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(fsi_soc_dai)); |
1756 | snd_soc_unregister_platform(&pdev->dev); | |
a4d7d550 | 1757 | |
5e97313a KM |
1758 | fsi_stream_remove(&master->fsia); |
1759 | fsi_stream_remove(&master->fsib); | |
1760 | ||
a4d7d550 KM |
1761 | iounmap(master->base); |
1762 | kfree(master); | |
71f6e064 | 1763 | |
a4d7d550 KM |
1764 | return 0; |
1765 | } | |
1766 | ||
106c79ec | 1767 | static void __fsi_suspend(struct fsi_priv *fsi, |
938e2a8d | 1768 | struct fsi_stream *io, |
4f56cde1 | 1769 | struct device *dev) |
106c79ec | 1770 | { |
938e2a8d | 1771 | if (!fsi_stream_is_working(fsi, io)) |
cda828ca | 1772 | return; |
106c79ec | 1773 | |
180346ed | 1774 | fsi_stream_stop(fsi, io); |
41bba151 | 1775 | fsi_hw_shutdown(fsi, dev); |
106c79ec KM |
1776 | } |
1777 | ||
1778 | static void __fsi_resume(struct fsi_priv *fsi, | |
938e2a8d | 1779 | struct fsi_stream *io, |
4f56cde1 | 1780 | struct device *dev) |
106c79ec | 1781 | { |
938e2a8d | 1782 | if (!fsi_stream_is_working(fsi, io)) |
cda828ca | 1783 | return; |
106c79ec | 1784 | |
938e2a8d | 1785 | fsi_hw_startup(fsi, io, dev); |
cda828ca KM |
1786 | |
1787 | if (fsi_is_clk_master(fsi) && fsi->rate) | |
4f56cde1 | 1788 | fsi_set_master_clk(dev, fsi, fsi->rate, 1); |
cda828ca | 1789 | |
180346ed | 1790 | fsi_stream_start(fsi, io); |
106c79ec KM |
1791 | } |
1792 | ||
1793 | static int fsi_suspend(struct device *dev) | |
1794 | { | |
1795 | struct fsi_master *master = dev_get_drvdata(dev); | |
cda828ca KM |
1796 | struct fsi_priv *fsia = &master->fsia; |
1797 | struct fsi_priv *fsib = &master->fsib; | |
106c79ec | 1798 | |
938e2a8d KM |
1799 | __fsi_suspend(fsia, &fsia->playback, dev); |
1800 | __fsi_suspend(fsia, &fsia->capture, dev); | |
106c79ec | 1801 | |
938e2a8d KM |
1802 | __fsi_suspend(fsib, &fsib->playback, dev); |
1803 | __fsi_suspend(fsib, &fsib->capture, dev); | |
106c79ec KM |
1804 | |
1805 | return 0; | |
1806 | } | |
1807 | ||
1808 | static int fsi_resume(struct device *dev) | |
1809 | { | |
1810 | struct fsi_master *master = dev_get_drvdata(dev); | |
cda828ca KM |
1811 | struct fsi_priv *fsia = &master->fsia; |
1812 | struct fsi_priv *fsib = &master->fsib; | |
106c79ec | 1813 | |
938e2a8d KM |
1814 | __fsi_resume(fsia, &fsia->playback, dev); |
1815 | __fsi_resume(fsia, &fsia->capture, dev); | |
106c79ec | 1816 | |
938e2a8d KM |
1817 | __fsi_resume(fsib, &fsib->playback, dev); |
1818 | __fsi_resume(fsib, &fsib->capture, dev); | |
106c79ec KM |
1819 | |
1820 | return 0; | |
1821 | } | |
1822 | ||
785d1c45 | 1823 | static struct dev_pm_ops fsi_pm_ops = { |
106c79ec KM |
1824 | .suspend = fsi_suspend, |
1825 | .resume = fsi_resume, | |
785d1c45 KM |
1826 | }; |
1827 | ||
73b92c1f KM |
1828 | static struct fsi_core fsi1_core = { |
1829 | .ver = 1, | |
1830 | ||
1831 | /* Interrupt */ | |
cc780d38 KM |
1832 | .int_st = INT_ST, |
1833 | .iemsk = IEMSK, | |
1834 | .imsk = IMSK, | |
1835 | }; | |
1836 | ||
73b92c1f KM |
1837 | static struct fsi_core fsi2_core = { |
1838 | .ver = 2, | |
1839 | ||
1840 | /* Interrupt */ | |
cc780d38 KM |
1841 | .int_st = CPU_INT_ST, |
1842 | .iemsk = CPU_IEMSK, | |
1843 | .imsk = CPU_IMSK, | |
2b0e7302 KM |
1844 | .a_mclk = A_MST_CTLR, |
1845 | .b_mclk = B_MST_CTLR, | |
cc780d38 KM |
1846 | }; |
1847 | ||
1848 | static struct platform_device_id fsi_id_table[] = { | |
73b92c1f KM |
1849 | { "sh_fsi", (kernel_ulong_t)&fsi1_core }, |
1850 | { "sh_fsi2", (kernel_ulong_t)&fsi2_core }, | |
05c69450 | 1851 | {}, |
cc780d38 | 1852 | }; |
d85a6d7b | 1853 | MODULE_DEVICE_TABLE(platform, fsi_id_table); |
cc780d38 | 1854 | |
a4d7d550 KM |
1855 | static struct platform_driver fsi_driver = { |
1856 | .driver = { | |
f0fba2ad | 1857 | .name = "fsi-pcm-audio", |
785d1c45 | 1858 | .pm = &fsi_pm_ops, |
a4d7d550 KM |
1859 | }, |
1860 | .probe = fsi_probe, | |
1861 | .remove = fsi_remove, | |
cc780d38 | 1862 | .id_table = fsi_id_table, |
a4d7d550 KM |
1863 | }; |
1864 | ||
cb5e8738 | 1865 | module_platform_driver(fsi_driver); |
a4d7d550 KM |
1866 | |
1867 | MODULE_LICENSE("GPL"); | |
1868 | MODULE_DESCRIPTION("SuperH onchip FSI audio driver"); | |
1869 | MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>"); | |
b3c27b51 | 1870 | MODULE_ALIAS("platform:fsi-pcm-audio"); |