Commit | Line | Data |
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a4d7d550 KM |
1 | /* |
2 | * Fifo-attached Serial Interface (FSI) support for SH7724 | |
3 | * | |
4 | * Copyright (C) 2009 Renesas Solutions Corp. | |
5 | * Kuninori Morimoto <morimoto.kuninori@renesas.com> | |
6 | * | |
7 | * Based on ssi.c | |
8 | * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
a4d7d550 | 15 | #include <linux/delay.h> |
785d1c45 | 16 | #include <linux/pm_runtime.h> |
a4d7d550 | 17 | #include <linux/io.h> |
5a0e3ad6 | 18 | #include <linux/slab.h> |
a4d7d550 | 19 | #include <sound/soc.h> |
a4d7d550 | 20 | #include <sound/sh_fsi.h> |
a4d7d550 | 21 | |
e8c8b631 KM |
22 | /* PortA/PortB register */ |
23 | #define REG_DO_FMT 0x0000 | |
24 | #define REG_DOFF_CTL 0x0004 | |
25 | #define REG_DOFF_ST 0x0008 | |
26 | #define REG_DI_FMT 0x000C | |
27 | #define REG_DIFF_CTL 0x0010 | |
28 | #define REG_DIFF_ST 0x0014 | |
29 | #define REG_CKG1 0x0018 | |
30 | #define REG_CKG2 0x001C | |
31 | #define REG_DIDT 0x0020 | |
32 | #define REG_DODT 0x0024 | |
33 | #define REG_MUTE_ST 0x0028 | |
34 | #define REG_OUT_SEL 0x0030 | |
cc780d38 | 35 | |
43fa95ca KM |
36 | /* master register */ |
37 | #define MST_CLK_RST 0x0210 | |
38 | #define MST_SOFT_RST 0x0214 | |
39 | #define MST_FIFO_SZ 0x0218 | |
40 | ||
41 | /* core register (depend on FSI version) */ | |
3bc28070 KM |
42 | #define A_MST_CTLR 0x0180 |
43 | #define B_MST_CTLR 0x01A0 | |
cc780d38 KM |
44 | #define CPU_INT_ST 0x01F4 |
45 | #define CPU_IEMSK 0x01F8 | |
46 | #define CPU_IMSK 0x01FC | |
a4d7d550 KM |
47 | #define INT_ST 0x0200 |
48 | #define IEMSK 0x0204 | |
49 | #define IMSK 0x0208 | |
a4d7d550 KM |
50 | |
51 | /* DO_FMT */ | |
52 | /* DI_FMT */ | |
f7d711e3 KM |
53 | #define CR_BWS_24 (0x0 << 20) /* FSI2 */ |
54 | #define CR_BWS_16 (0x1 << 20) /* FSI2 */ | |
55 | #define CR_BWS_20 (0x2 << 20) /* FSI2 */ | |
56 | ||
57 | #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */ | |
58 | #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */ | |
59 | #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */ | |
60 | ||
a7ffb52b KM |
61 | #define CR_MONO (0x0 << 4) |
62 | #define CR_MONO_D (0x1 << 4) | |
63 | #define CR_PCM (0x2 << 4) | |
64 | #define CR_I2S (0x3 << 4) | |
65 | #define CR_TDM (0x4 << 4) | |
66 | #define CR_TDM_D (0x5 << 4) | |
a4d7d550 KM |
67 | |
68 | /* DOFF_CTL */ | |
69 | /* DIFF_CTL */ | |
70 | #define IRQ_HALF 0x00100000 | |
71 | #define FIFO_CLR 0x00000001 | |
72 | ||
73 | /* DOFF_ST */ | |
74 | #define ERR_OVER 0x00000010 | |
75 | #define ERR_UNDER 0x00000001 | |
59c3b003 | 76 | #define ST_ERR (ERR_OVER | ERR_UNDER) |
a4d7d550 | 77 | |
ccad7b44 KM |
78 | /* CKG1 */ |
79 | #define ACKMD_MASK 0x00007000 | |
80 | #define BPFMD_MASK 0x00000700 | |
4d805f7b KM |
81 | #define DIMD (1 << 4) |
82 | #define DOMD (1 << 0) | |
ccad7b44 | 83 | |
3bc28070 KM |
84 | /* A/B MST_CTLR */ |
85 | #define BP (1 << 4) /* Fix the signal of Biphase output */ | |
86 | #define SE (1 << 0) /* Fix the master clock */ | |
87 | ||
a4d7d550 | 88 | /* CLK_RST */ |
1f5e2a31 KM |
89 | #define CRB (1 << 4) |
90 | #define CRA (1 << 0) | |
a4d7d550 | 91 | |
cf6edd00 KM |
92 | /* IO SHIFT / MACRO */ |
93 | #define BI_SHIFT 12 | |
94 | #define BO_SHIFT 8 | |
95 | #define AI_SHIFT 4 | |
96 | #define AO_SHIFT 0 | |
97 | #define AB_IO(param, shift) (param << shift) | |
a4d7d550 | 98 | |
feb58cff KM |
99 | /* SOFT_RST */ |
100 | #define PBSR (1 << 12) /* Port B Software Reset */ | |
101 | #define PASR (1 << 8) /* Port A Software Reset */ | |
102 | #define IR (1 << 4) /* Interrupt Reset */ | |
103 | #define FSISR (1 << 0) /* Software Reset */ | |
104 | ||
f7d711e3 KM |
105 | /* OUT_SEL (FSI2) */ |
106 | #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */ | |
107 | /* 1: Biphase and serial */ | |
108 | ||
4a942b45 | 109 | /* FIFO_SZ */ |
cf6edd00 | 110 | #define FIFO_SZ_MASK 0x7 |
4a942b45 | 111 | |
a4d7d550 KM |
112 | #define FSI_RATES SNDRV_PCM_RATE_8000_96000 |
113 | ||
114 | #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE) | |
115 | ||
d7c5762b KM |
116 | typedef int (*set_rate_func)(struct device *dev, int is_porta, int rate, int enable); |
117 | ||
5bfb9ad0 KM |
118 | /* |
119 | * FSI driver use below type name for variable | |
120 | * | |
5bfb9ad0 | 121 | * xxx_num : number of data |
2e651baf KM |
122 | * xxx_pos : position of data |
123 | * xxx_capa : capacity of data | |
124 | */ | |
125 | ||
126 | /* | |
127 | * period/frame/sample image | |
128 | * | |
129 | * ex) PCM (2ch) | |
130 | * | |
131 | * period pos period pos | |
132 | * [n] [n + 1] | |
133 | * |<-------------------- period--------------------->| | |
134 | * ==|============================================ ... =|== | |
135 | * | | | |
136 | * ||<----- frame ----->|<------ frame ----->| ... | | |
137 | * |+--------------------+--------------------+- ... | | |
138 | * ||[ sample ][ sample ]|[ sample ][ sample ]| ... | | |
139 | * |+--------------------+--------------------+- ... | | |
140 | * ==|============================================ ... =|== | |
141 | */ | |
142 | ||
143 | /* | |
144 | * FSI FIFO image | |
145 | * | |
146 | * | | | |
147 | * | | | |
148 | * | [ sample ] | | |
149 | * | [ sample ] | | |
150 | * | [ sample ] | | |
151 | * | [ sample ] | | |
152 | * --> go to codecs | |
5bfb9ad0 KM |
153 | */ |
154 | ||
c8fe2574 KM |
155 | /* |
156 | * struct | |
157 | */ | |
a4d7d550 | 158 | |
93193c2b | 159 | struct fsi_stream { |
a4d7d550 KM |
160 | struct snd_pcm_substream *substream; |
161 | ||
2e651baf KM |
162 | int fifo_sample_capa; /* sample capacity of FSI FIFO */ |
163 | int buff_sample_capa; /* sample capacity of ALSA buffer */ | |
164 | int buff_sample_pos; /* sample position of ALSA buffer */ | |
165 | int period_samples; /* sample number / 1 period */ | |
166 | int period_pos; /* current period position */ | |
1ec9bc35 KM |
167 | |
168 | int uerr_num; | |
169 | int oerr_num; | |
93193c2b KM |
170 | }; |
171 | ||
172 | struct fsi_priv { | |
173 | void __iomem *base; | |
174 | struct fsi_master *master; | |
175 | ||
176 | struct fsi_stream playback; | |
177 | struct fsi_stream capture; | |
3bc28070 | 178 | |
9478e0b6 KM |
179 | u32 do_fmt; |
180 | u32 di_fmt; | |
181 | ||
6a9ebad8 KM |
182 | int chan_num:16; |
183 | int clk_master:1; | |
9478e0b6 | 184 | int spdif:1; |
6a9ebad8 | 185 | |
d4bc99b9 | 186 | long rate; |
a4d7d550 KM |
187 | }; |
188 | ||
73b92c1f KM |
189 | struct fsi_core { |
190 | int ver; | |
191 | ||
cc780d38 KM |
192 | u32 int_st; |
193 | u32 iemsk; | |
194 | u32 imsk; | |
2b0e7302 KM |
195 | u32 a_mclk; |
196 | u32 b_mclk; | |
cc780d38 KM |
197 | }; |
198 | ||
a4d7d550 KM |
199 | struct fsi_master { |
200 | void __iomem *base; | |
201 | int irq; | |
a4d7d550 KM |
202 | struct fsi_priv fsia; |
203 | struct fsi_priv fsib; | |
73b92c1f | 204 | struct fsi_core *core; |
a4d7d550 | 205 | struct sh_fsi_platform_info *info; |
8fc176d5 | 206 | spinlock_t lock; |
a4d7d550 KM |
207 | }; |
208 | ||
c8fe2574 KM |
209 | /* |
210 | * basic read write function | |
211 | */ | |
a4d7d550 | 212 | |
ca7aceef | 213 | static void __fsi_reg_write(u32 __iomem *reg, u32 data) |
a4d7d550 KM |
214 | { |
215 | /* valid data area is 24bit */ | |
216 | data &= 0x00ffffff; | |
217 | ||
0f69d978 | 218 | __raw_writel(data, reg); |
a4d7d550 KM |
219 | } |
220 | ||
ca7aceef | 221 | static u32 __fsi_reg_read(u32 __iomem *reg) |
a4d7d550 | 222 | { |
0f69d978 | 223 | return __raw_readl(reg); |
a4d7d550 KM |
224 | } |
225 | ||
ca7aceef | 226 | static void __fsi_reg_mask_set(u32 __iomem *reg, u32 mask, u32 data) |
a4d7d550 KM |
227 | { |
228 | u32 val = __fsi_reg_read(reg); | |
229 | ||
230 | val &= ~mask; | |
231 | val |= data & mask; | |
232 | ||
0f69d978 | 233 | __fsi_reg_write(reg, val); |
a4d7d550 KM |
234 | } |
235 | ||
e8c8b631 KM |
236 | #define fsi_reg_write(p, r, d)\ |
237 | __fsi_reg_write((u32)(p->base + REG_##r), d) | |
a4d7d550 | 238 | |
e8c8b631 KM |
239 | #define fsi_reg_read(p, r)\ |
240 | __fsi_reg_read((u32)(p->base + REG_##r)) | |
a4d7d550 | 241 | |
e8c8b631 KM |
242 | #define fsi_reg_mask_set(p, r, m, d)\ |
243 | __fsi_reg_mask_set((u32)(p->base + REG_##r), m, d) | |
a4d7d550 | 244 | |
43fa95ca KM |
245 | #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r) |
246 | #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r) | |
247 | static u32 _fsi_master_read(struct fsi_master *master, u32 reg) | |
a4d7d550 | 248 | { |
8fc176d5 KM |
249 | u32 ret; |
250 | unsigned long flags; | |
251 | ||
8fc176d5 | 252 | spin_lock_irqsave(&master->lock, flags); |
ca7aceef | 253 | ret = __fsi_reg_read(master->base + reg); |
8fc176d5 KM |
254 | spin_unlock_irqrestore(&master->lock, flags); |
255 | ||
256 | return ret; | |
a4d7d550 KM |
257 | } |
258 | ||
43fa95ca KM |
259 | #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d) |
260 | #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d) | |
261 | static void _fsi_master_mask_set(struct fsi_master *master, | |
71f6e064 | 262 | u32 reg, u32 mask, u32 data) |
a4d7d550 | 263 | { |
8fc176d5 KM |
264 | unsigned long flags; |
265 | ||
8fc176d5 | 266 | spin_lock_irqsave(&master->lock, flags); |
ca7aceef | 267 | __fsi_reg_mask_set(master->base + reg, mask, data); |
8fc176d5 | 268 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
269 | } |
270 | ||
c8fe2574 KM |
271 | /* |
272 | * basic function | |
273 | */ | |
a4d7d550 | 274 | |
71f6e064 | 275 | static struct fsi_master *fsi_get_master(struct fsi_priv *fsi) |
a4d7d550 | 276 | { |
71f6e064 | 277 | return fsi->master; |
a4d7d550 KM |
278 | } |
279 | ||
6a9ebad8 KM |
280 | static int fsi_is_clk_master(struct fsi_priv *fsi) |
281 | { | |
282 | return fsi->clk_master; | |
283 | } | |
284 | ||
a4d7d550 KM |
285 | static int fsi_is_port_a(struct fsi_priv *fsi) |
286 | { | |
71f6e064 KM |
287 | return fsi->master->base == fsi->base; |
288 | } | |
a4d7d550 | 289 | |
9478e0b6 KM |
290 | static int fsi_is_spdif(struct fsi_priv *fsi) |
291 | { | |
292 | return fsi->spdif; | |
293 | } | |
294 | ||
142e8174 | 295 | static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream) |
71f6e064 KM |
296 | { |
297 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
142e8174 | 298 | |
f0fba2ad | 299 | return rtd->cpu_dai; |
142e8174 KM |
300 | } |
301 | ||
0d032c19 | 302 | static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai) |
142e8174 | 303 | { |
f0fba2ad | 304 | struct fsi_master *master = snd_soc_dai_get_drvdata(dai); |
a4d7d550 | 305 | |
f0fba2ad LG |
306 | if (dai->id == 0) |
307 | return &master->fsia; | |
308 | else | |
309 | return &master->fsib; | |
a4d7d550 KM |
310 | } |
311 | ||
0d032c19 KM |
312 | static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream) |
313 | { | |
314 | return fsi_get_priv_frm_dai(fsi_get_dai(substream)); | |
315 | } | |
316 | ||
d7c5762b KM |
317 | static set_rate_func fsi_get_info_set_rate(struct fsi_master *master) |
318 | { | |
319 | if (!master->info) | |
320 | return NULL; | |
321 | ||
322 | return master->info->set_rate; | |
323 | } | |
324 | ||
a4d7d550 KM |
325 | static u32 fsi_get_info_flags(struct fsi_priv *fsi) |
326 | { | |
327 | int is_porta = fsi_is_port_a(fsi); | |
71f6e064 | 328 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 329 | |
d7c5762b KM |
330 | if (!master->info) |
331 | return 0; | |
332 | ||
a4d7d550 KM |
333 | return is_porta ? master->info->porta_flags : |
334 | master->info->portb_flags; | |
335 | } | |
336 | ||
93193c2b KM |
337 | static inline int fsi_stream_is_play(int stream) |
338 | { | |
339 | return stream == SNDRV_PCM_STREAM_PLAYBACK; | |
340 | } | |
341 | ||
00545785 KM |
342 | static inline int fsi_is_play(struct snd_pcm_substream *substream) |
343 | { | |
93193c2b KM |
344 | return fsi_stream_is_play(substream->stream); |
345 | } | |
346 | ||
347 | static inline struct fsi_stream *fsi_get_stream(struct fsi_priv *fsi, | |
348 | int is_play) | |
349 | { | |
350 | return is_play ? &fsi->playback : &fsi->capture; | |
00545785 KM |
351 | } |
352 | ||
cf6edd00 | 353 | static u32 fsi_get_port_shift(struct fsi_priv *fsi, int is_play) |
a4d7d550 KM |
354 | { |
355 | int is_porta = fsi_is_port_a(fsi); | |
cf6edd00 | 356 | u32 shift; |
a4d7d550 KM |
357 | |
358 | if (is_porta) | |
cf6edd00 | 359 | shift = is_play ? AO_SHIFT : AI_SHIFT; |
a4d7d550 | 360 | else |
cf6edd00 | 361 | shift = is_play ? BO_SHIFT : BI_SHIFT; |
a4d7d550 | 362 | |
cf6edd00 | 363 | return shift; |
a4d7d550 KM |
364 | } |
365 | ||
2e651baf KM |
366 | static int fsi_frame2sample(struct fsi_priv *fsi, int frames) |
367 | { | |
368 | return frames * fsi->chan_num; | |
369 | } | |
370 | ||
371 | static int fsi_sample2frame(struct fsi_priv *fsi, int samples) | |
372 | { | |
373 | return samples / fsi->chan_num; | |
374 | } | |
375 | ||
cda828ca KM |
376 | static int fsi_stream_is_working(struct fsi_priv *fsi, |
377 | int is_play) | |
378 | { | |
379 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); | |
380 | struct fsi_master *master = fsi_get_master(fsi); | |
381 | unsigned long flags; | |
382 | int ret; | |
383 | ||
384 | spin_lock_irqsave(&master->lock, flags); | |
385 | ret = !!io->substream; | |
386 | spin_unlock_irqrestore(&master->lock, flags); | |
387 | ||
388 | return ret; | |
389 | } | |
390 | ||
a4d7d550 | 391 | static void fsi_stream_push(struct fsi_priv *fsi, |
93193c2b | 392 | int is_play, |
0ffe296a | 393 | struct snd_pcm_substream *substream) |
a4d7d550 | 394 | { |
93193c2b | 395 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); |
0ffe296a | 396 | struct snd_pcm_runtime *runtime = substream->runtime; |
2da65892 KM |
397 | struct fsi_master *master = fsi_get_master(fsi); |
398 | unsigned long flags; | |
93193c2b | 399 | |
2da65892 | 400 | spin_lock_irqsave(&master->lock, flags); |
93193c2b | 401 | io->substream = substream; |
2e651baf KM |
402 | io->buff_sample_capa = fsi_frame2sample(fsi, runtime->buffer_size); |
403 | io->buff_sample_pos = 0; | |
404 | io->period_samples = fsi_frame2sample(fsi, runtime->period_size); | |
405 | io->period_pos = 0; | |
1ec9bc35 KM |
406 | io->oerr_num = -1; /* ignore 1st err */ |
407 | io->uerr_num = -1; /* ignore 1st err */ | |
2da65892 | 408 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
409 | } |
410 | ||
93193c2b | 411 | static void fsi_stream_pop(struct fsi_priv *fsi, int is_play) |
a4d7d550 | 412 | { |
93193c2b | 413 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); |
1ec9bc35 | 414 | struct snd_soc_dai *dai = fsi_get_dai(io->substream); |
2da65892 KM |
415 | struct fsi_master *master = fsi_get_master(fsi); |
416 | unsigned long flags; | |
1ec9bc35 | 417 | |
2da65892 | 418 | spin_lock_irqsave(&master->lock, flags); |
1ec9bc35 KM |
419 | |
420 | if (io->oerr_num > 0) | |
421 | dev_err(dai->dev, "over_run = %d\n", io->oerr_num); | |
422 | ||
423 | if (io->uerr_num > 0) | |
424 | dev_err(dai->dev, "under_run = %d\n", io->uerr_num); | |
93193c2b KM |
425 | |
426 | io->substream = NULL; | |
2e651baf KM |
427 | io->buff_sample_capa = 0; |
428 | io->buff_sample_pos = 0; | |
429 | io->period_samples = 0; | |
430 | io->period_pos = 0; | |
1ec9bc35 KM |
431 | io->oerr_num = 0; |
432 | io->uerr_num = 0; | |
2da65892 | 433 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
434 | } |
435 | ||
2e651baf | 436 | static int fsi_get_current_fifo_samples(struct fsi_priv *fsi, int is_play) |
a4d7d550 KM |
437 | { |
438 | u32 status; | |
2e651baf | 439 | int frames; |
a4d7d550 | 440 | |
e8c8b631 KM |
441 | status = is_play ? |
442 | fsi_reg_read(fsi, DOFF_ST) : | |
443 | fsi_reg_read(fsi, DIFF_ST); | |
444 | ||
2e651baf | 445 | frames = 0x1ff & (status >> 8); |
5bfb9ad0 | 446 | |
2e651baf | 447 | return fsi_frame2sample(fsi, frames); |
cca1b235 KM |
448 | } |
449 | ||
1ec9bc35 KM |
450 | static void fsi_count_fifo_err(struct fsi_priv *fsi) |
451 | { | |
452 | u32 ostatus = fsi_reg_read(fsi, DOFF_ST); | |
453 | u32 istatus = fsi_reg_read(fsi, DIFF_ST); | |
454 | ||
455 | if (ostatus & ERR_OVER) | |
456 | fsi->playback.oerr_num++; | |
457 | ||
458 | if (ostatus & ERR_UNDER) | |
459 | fsi->playback.uerr_num++; | |
460 | ||
461 | if (istatus & ERR_OVER) | |
462 | fsi->capture.oerr_num++; | |
463 | ||
464 | if (istatus & ERR_UNDER) | |
465 | fsi->capture.uerr_num++; | |
466 | ||
467 | fsi_reg_write(fsi, DOFF_ST, 0); | |
468 | fsi_reg_write(fsi, DIFF_ST, 0); | |
469 | } | |
470 | ||
b9fde18c KM |
471 | /* |
472 | * dma function | |
473 | */ | |
474 | ||
93193c2b | 475 | static u8 *fsi_dma_get_area(struct fsi_priv *fsi, int stream) |
c79eab3e | 476 | { |
93193c2b KM |
477 | int is_play = fsi_stream_is_play(stream); |
478 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); | |
2e651baf | 479 | struct snd_pcm_runtime *runtime = io->substream->runtime; |
93193c2b | 480 | |
2e651baf KM |
481 | return runtime->dma_area + |
482 | samples_to_bytes(runtime, io->buff_sample_pos); | |
c79eab3e KM |
483 | } |
484 | ||
5bfb9ad0 | 485 | static void fsi_dma_soft_push16(struct fsi_priv *fsi, int num) |
b9fde18c KM |
486 | { |
487 | u16 *start; | |
488 | int i; | |
489 | ||
93193c2b | 490 | start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK); |
b9fde18c | 491 | |
5bfb9ad0 | 492 | for (i = 0; i < num; i++) |
b9fde18c KM |
493 | fsi_reg_write(fsi, DODT, ((u32)*(start + i) << 8)); |
494 | } | |
495 | ||
5bfb9ad0 | 496 | static void fsi_dma_soft_pop16(struct fsi_priv *fsi, int num) |
b9fde18c KM |
497 | { |
498 | u16 *start; | |
499 | int i; | |
500 | ||
93193c2b KM |
501 | start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE); |
502 | ||
b9fde18c | 503 | |
5bfb9ad0 | 504 | for (i = 0; i < num; i++) |
b9fde18c KM |
505 | *(start + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8); |
506 | } | |
507 | ||
5bfb9ad0 | 508 | static void fsi_dma_soft_push32(struct fsi_priv *fsi, int num) |
b9fde18c KM |
509 | { |
510 | u32 *start; | |
511 | int i; | |
512 | ||
93193c2b KM |
513 | start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK); |
514 | ||
b9fde18c | 515 | |
5bfb9ad0 | 516 | for (i = 0; i < num; i++) |
b9fde18c KM |
517 | fsi_reg_write(fsi, DODT, *(start + i)); |
518 | } | |
519 | ||
5bfb9ad0 | 520 | static void fsi_dma_soft_pop32(struct fsi_priv *fsi, int num) |
b9fde18c KM |
521 | { |
522 | u32 *start; | |
523 | int i; | |
524 | ||
93193c2b | 525 | start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE); |
b9fde18c | 526 | |
5bfb9ad0 | 527 | for (i = 0; i < num; i++) |
b9fde18c KM |
528 | *(start + i) = fsi_reg_read(fsi, DIDT); |
529 | } | |
530 | ||
c8fe2574 KM |
531 | /* |
532 | * irq function | |
533 | */ | |
a4d7d550 | 534 | |
a4d7d550 KM |
535 | static void fsi_irq_enable(struct fsi_priv *fsi, int is_play) |
536 | { | |
cf6edd00 | 537 | u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play)); |
71f6e064 | 538 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 539 | |
43fa95ca KM |
540 | fsi_core_mask_set(master, imsk, data, data); |
541 | fsi_core_mask_set(master, iemsk, data, data); | |
a4d7d550 KM |
542 | } |
543 | ||
544 | static void fsi_irq_disable(struct fsi_priv *fsi, int is_play) | |
545 | { | |
cf6edd00 | 546 | u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play)); |
71f6e064 | 547 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 548 | |
43fa95ca KM |
549 | fsi_core_mask_set(master, imsk, data, 0); |
550 | fsi_core_mask_set(master, iemsk, data, 0); | |
a4d7d550 KM |
551 | } |
552 | ||
10ea76cc KM |
553 | static u32 fsi_irq_get_status(struct fsi_master *master) |
554 | { | |
43fa95ca | 555 | return fsi_core_read(master, int_st); |
10ea76cc KM |
556 | } |
557 | ||
10ea76cc KM |
558 | static void fsi_irq_clear_status(struct fsi_priv *fsi) |
559 | { | |
560 | u32 data = 0; | |
561 | struct fsi_master *master = fsi_get_master(fsi); | |
562 | ||
cf6edd00 KM |
563 | data |= AB_IO(1, fsi_get_port_shift(fsi, 0)); |
564 | data |= AB_IO(1, fsi_get_port_shift(fsi, 1)); | |
10ea76cc KM |
565 | |
566 | /* clear interrupt factor */ | |
43fa95ca | 567 | fsi_core_mask_set(master, int_st, data, 0); |
10ea76cc KM |
568 | } |
569 | ||
c8fe2574 KM |
570 | /* |
571 | * SPDIF master clock function | |
572 | * | |
573 | * These functions are used later FSI2 | |
574 | */ | |
3bc28070 KM |
575 | static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable) |
576 | { | |
577 | struct fsi_master *master = fsi_get_master(fsi); | |
2b0e7302 | 578 | u32 mask, val; |
3bc28070 KM |
579 | |
580 | if (master->core->ver < 2) { | |
581 | pr_err("fsi: register access err (%s)\n", __func__); | |
582 | return; | |
583 | } | |
584 | ||
2b0e7302 KM |
585 | mask = BP | SE; |
586 | val = enable ? mask : 0; | |
587 | ||
588 | fsi_is_port_a(fsi) ? | |
43fa95ca KM |
589 | fsi_core_mask_set(master, a_mclk, mask, val) : |
590 | fsi_core_mask_set(master, b_mclk, mask, val); | |
3bc28070 KM |
591 | } |
592 | ||
c8fe2574 | 593 | /* |
1f5e2a31 | 594 | * clock function |
c8fe2574 | 595 | */ |
4f56cde1 KM |
596 | static int fsi_set_master_clk(struct device *dev, struct fsi_priv *fsi, |
597 | long rate, int enable) | |
598 | { | |
599 | struct fsi_master *master = fsi_get_master(fsi); | |
600 | set_rate_func set_rate = fsi_get_info_set_rate(master); | |
601 | int fsi_ver = master->core->ver; | |
602 | int ret; | |
603 | ||
604 | ret = set_rate(dev, fsi_is_port_a(fsi), rate, enable); | |
605 | if (ret < 0) /* error */ | |
606 | return ret; | |
607 | ||
608 | if (!enable) | |
609 | return 0; | |
610 | ||
611 | if (ret > 0) { | |
612 | u32 data = 0; | |
613 | ||
614 | switch (ret & SH_FSI_ACKMD_MASK) { | |
615 | default: | |
616 | /* FALL THROUGH */ | |
617 | case SH_FSI_ACKMD_512: | |
618 | data |= (0x0 << 12); | |
619 | break; | |
620 | case SH_FSI_ACKMD_256: | |
621 | data |= (0x1 << 12); | |
622 | break; | |
623 | case SH_FSI_ACKMD_128: | |
624 | data |= (0x2 << 12); | |
625 | break; | |
626 | case SH_FSI_ACKMD_64: | |
627 | data |= (0x3 << 12); | |
628 | break; | |
629 | case SH_FSI_ACKMD_32: | |
630 | if (fsi_ver < 2) | |
631 | dev_err(dev, "unsupported ACKMD\n"); | |
632 | else | |
633 | data |= (0x4 << 12); | |
634 | break; | |
635 | } | |
636 | ||
637 | switch (ret & SH_FSI_BPFMD_MASK) { | |
638 | default: | |
639 | /* FALL THROUGH */ | |
640 | case SH_FSI_BPFMD_32: | |
641 | data |= (0x0 << 8); | |
642 | break; | |
643 | case SH_FSI_BPFMD_64: | |
644 | data |= (0x1 << 8); | |
645 | break; | |
646 | case SH_FSI_BPFMD_128: | |
647 | data |= (0x2 << 8); | |
648 | break; | |
649 | case SH_FSI_BPFMD_256: | |
650 | data |= (0x3 << 8); | |
651 | break; | |
652 | case SH_FSI_BPFMD_512: | |
653 | data |= (0x4 << 8); | |
654 | break; | |
655 | case SH_FSI_BPFMD_16: | |
656 | if (fsi_ver < 2) | |
657 | dev_err(dev, "unsupported ACKMD\n"); | |
658 | else | |
659 | data |= (0x7 << 8); | |
660 | break; | |
661 | } | |
662 | ||
663 | fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data); | |
664 | udelay(10); | |
665 | ret = 0; | |
666 | } | |
667 | ||
668 | return ret; | |
4f56cde1 KM |
669 | } |
670 | ||
1ddddd36 KM |
671 | #define fsi_port_start(f, i) __fsi_port_clk_ctrl(f, i, 1) |
672 | #define fsi_port_stop(f, i) __fsi_port_clk_ctrl(f, i, 0) | |
673 | static void __fsi_port_clk_ctrl(struct fsi_priv *fsi, int is_play, int enable) | |
a4d7d550 | 674 | { |
71f6e064 | 675 | struct fsi_master *master = fsi_get_master(fsi); |
1f5e2a31 | 676 | u32 clk = fsi_is_port_a(fsi) ? CRA : CRB; |
a4d7d550 | 677 | |
1ddddd36 KM |
678 | if (enable) |
679 | fsi_irq_enable(fsi, is_play); | |
680 | else | |
681 | fsi_irq_disable(fsi, is_play); | |
682 | ||
cda828ca | 683 | if (fsi_is_clk_master(fsi)) |
1f5e2a31 | 684 | fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0); |
a4d7d550 KM |
685 | } |
686 | ||
1f5e2a31 KM |
687 | /* |
688 | * ctrl function | |
689 | */ | |
4a942b45 KM |
690 | static void fsi_fifo_init(struct fsi_priv *fsi, |
691 | int is_play, | |
23ca8533 | 692 | struct device *dev) |
a4d7d550 | 693 | { |
4a942b45 | 694 | struct fsi_master *master = fsi_get_master(fsi); |
93193c2b | 695 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); |
e8c8b631 | 696 | u32 shift, i; |
2e651baf | 697 | int frame_capa; |
a4d7d550 | 698 | |
4a942b45 KM |
699 | /* get on-chip RAM capacity */ |
700 | shift = fsi_master_read(master, FIFO_SZ); | |
cf6edd00 KM |
701 | shift >>= fsi_get_port_shift(fsi, is_play); |
702 | shift &= FIFO_SZ_MASK; | |
2e651baf | 703 | frame_capa = 256 << shift; |
23ca8533 | 704 | dev_dbg(dev, "fifo = %d words\n", frame_capa); |
a4d7d550 | 705 | |
4a942b45 KM |
706 | /* |
707 | * The maximum number of sample data varies depending | |
708 | * on the number of channels selected for the format. | |
709 | * | |
710 | * FIFOs are used in 4-channel units in 3-channel mode | |
711 | * and in 8-channel units in 5- to 7-channel mode | |
712 | * meaning that more FIFOs than the required size of DPRAM | |
713 | * are used. | |
714 | * | |
715 | * ex) if 256 words of DP-RAM is connected | |
716 | * 1 channel: 256 (256 x 1 = 256) | |
717 | * 2 channels: 128 (128 x 2 = 256) | |
718 | * 3 channels: 64 ( 64 x 3 = 192) | |
719 | * 4 channels: 64 ( 64 x 4 = 256) | |
720 | * 5 channels: 32 ( 32 x 5 = 160) | |
721 | * 6 channels: 32 ( 32 x 6 = 192) | |
722 | * 7 channels: 32 ( 32 x 7 = 224) | |
723 | * 8 channels: 32 ( 32 x 8 = 256) | |
724 | */ | |
160afa7f | 725 | for (i = 1; i < fsi->chan_num; i <<= 1) |
2e651baf | 726 | frame_capa >>= 1; |
23ca8533 | 727 | dev_dbg(dev, "%d channel %d store\n", |
2e651baf KM |
728 | fsi->chan_num, frame_capa); |
729 | ||
730 | io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa); | |
a4d7d550 | 731 | |
e8c8b631 KM |
732 | /* |
733 | * set interrupt generation factor | |
734 | * clear FIFO | |
735 | */ | |
736 | if (is_play) { | |
737 | fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF); | |
738 | fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR); | |
739 | } else { | |
740 | fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF); | |
741 | fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR); | |
742 | } | |
a4d7d550 KM |
743 | } |
744 | ||
1ec9bc35 | 745 | static int fsi_fifo_data_ctrl(struct fsi_priv *fsi, int stream) |
a4d7d550 KM |
746 | { |
747 | struct snd_pcm_runtime *runtime; | |
748 | struct snd_pcm_substream *substream = NULL; | |
93193c2b KM |
749 | int is_play = fsi_stream_is_play(stream); |
750 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); | |
2e651baf KM |
751 | int sample_residues; |
752 | int sample_width; | |
753 | int samples; | |
754 | int samples_max; | |
b9fde18c | 755 | int over_period; |
d8b33534 | 756 | void (*fn)(struct fsi_priv *fsi, int size); |
a4d7d550 KM |
757 | |
758 | if (!fsi || | |
93193c2b KM |
759 | !io->substream || |
760 | !io->substream->runtime) | |
a4d7d550 KM |
761 | return -EINVAL; |
762 | ||
1c418d1f | 763 | over_period = 0; |
93193c2b | 764 | substream = io->substream; |
1c418d1f | 765 | runtime = substream->runtime; |
a4d7d550 KM |
766 | |
767 | /* FSI FIFO has limit. | |
768 | * So, this driver can not send periods data at a time | |
769 | */ | |
2e651baf KM |
770 | if (io->buff_sample_pos >= |
771 | io->period_samples * (io->period_pos + 1)) { | |
a4d7d550 | 772 | |
1c418d1f | 773 | over_period = 1; |
2e651baf | 774 | io->period_pos = (io->period_pos + 1) % runtime->periods; |
a4d7d550 | 775 | |
2e651baf KM |
776 | if (0 == io->period_pos) |
777 | io->buff_sample_pos = 0; | |
a4d7d550 KM |
778 | } |
779 | ||
2e651baf KM |
780 | /* get 1 sample data width */ |
781 | sample_width = samples_to_bytes(runtime, 1); | |
a4d7d550 | 782 | |
2e651baf KM |
783 | /* get number of residue samples */ |
784 | sample_residues = io->buff_sample_capa - io->buff_sample_pos; | |
d8b33534 KM |
785 | |
786 | if (is_play) { | |
787 | /* | |
788 | * for play-back | |
789 | * | |
2e651baf KM |
790 | * samples_max : number of FSI fifo free samples space |
791 | * samples : number of ALSA residue samples | |
d8b33534 | 792 | */ |
2e651baf KM |
793 | samples_max = io->fifo_sample_capa; |
794 | samples_max -= fsi_get_current_fifo_samples(fsi, is_play); | |
d8b33534 | 795 | |
2e651baf | 796 | samples = sample_residues; |
d8b33534 | 797 | |
2e651baf | 798 | switch (sample_width) { |
d8b33534 KM |
799 | case 2: |
800 | fn = fsi_dma_soft_push16; | |
801 | break; | |
802 | case 4: | |
803 | fn = fsi_dma_soft_push32; | |
804 | break; | |
805 | default: | |
806 | return -EINVAL; | |
807 | } | |
808 | } else { | |
809 | /* | |
810 | * for capture | |
811 | * | |
2e651baf KM |
812 | * samples_max : number of ALSA free samples space |
813 | * samples : number of samples in FSI fifo | |
d8b33534 | 814 | */ |
2e651baf KM |
815 | samples_max = sample_residues; |
816 | samples = fsi_get_current_fifo_samples(fsi, is_play); | |
d8b33534 | 817 | |
2e651baf | 818 | switch (sample_width) { |
d8b33534 KM |
819 | case 2: |
820 | fn = fsi_dma_soft_pop16; | |
821 | break; | |
822 | case 4: | |
823 | fn = fsi_dma_soft_pop32; | |
824 | break; | |
825 | default: | |
826 | return -EINVAL; | |
827 | } | |
828 | } | |
a4d7d550 | 829 | |
2e651baf | 830 | samples = min(samples, samples_max); |
a4d7d550 | 831 | |
2e651baf | 832 | fn(fsi, samples); |
a4d7d550 | 833 | |
2e651baf KM |
834 | /* update buff_sample_pos */ |
835 | io->buff_sample_pos += samples; | |
a4d7d550 | 836 | |
1c418d1f | 837 | if (over_period) |
a4d7d550 KM |
838 | snd_pcm_period_elapsed(substream); |
839 | ||
47fc9a0a | 840 | return 0; |
a4d7d550 KM |
841 | } |
842 | ||
1ec9bc35 | 843 | static int fsi_data_pop(struct fsi_priv *fsi) |
07102f3c | 844 | { |
1ec9bc35 | 845 | return fsi_fifo_data_ctrl(fsi, SNDRV_PCM_STREAM_CAPTURE); |
d8b33534 | 846 | } |
07102f3c | 847 | |
1ec9bc35 | 848 | static int fsi_data_push(struct fsi_priv *fsi) |
d8b33534 | 849 | { |
1ec9bc35 | 850 | return fsi_fifo_data_ctrl(fsi, SNDRV_PCM_STREAM_PLAYBACK); |
07102f3c KM |
851 | } |
852 | ||
a4d7d550 KM |
853 | static irqreturn_t fsi_interrupt(int irq, void *data) |
854 | { | |
71f6e064 | 855 | struct fsi_master *master = data; |
10ea76cc | 856 | u32 int_st = fsi_irq_get_status(master); |
a4d7d550 KM |
857 | |
858 | /* clear irq status */ | |
feb58cff KM |
859 | fsi_master_mask_set(master, SOFT_RST, IR, 0); |
860 | fsi_master_mask_set(master, SOFT_RST, IR, IR); | |
a4d7d550 | 861 | |
cf6edd00 | 862 | if (int_st & AB_IO(1, AO_SHIFT)) |
1ec9bc35 | 863 | fsi_data_push(&master->fsia); |
cf6edd00 | 864 | if (int_st & AB_IO(1, BO_SHIFT)) |
1ec9bc35 | 865 | fsi_data_push(&master->fsib); |
cf6edd00 | 866 | if (int_st & AB_IO(1, AI_SHIFT)) |
1ec9bc35 | 867 | fsi_data_pop(&master->fsia); |
cf6edd00 | 868 | if (int_st & AB_IO(1, BI_SHIFT)) |
1ec9bc35 KM |
869 | fsi_data_pop(&master->fsib); |
870 | ||
871 | fsi_count_fifo_err(&master->fsia); | |
872 | fsi_count_fifo_err(&master->fsib); | |
a4d7d550 | 873 | |
48d78e58 KM |
874 | fsi_irq_clear_status(&master->fsia); |
875 | fsi_irq_clear_status(&master->fsib); | |
a4d7d550 KM |
876 | |
877 | return IRQ_HANDLED; | |
878 | } | |
879 | ||
c8fe2574 KM |
880 | /* |
881 | * dai ops | |
882 | */ | |
a4d7d550 | 883 | |
23ca8533 KM |
884 | static int fsi_hw_startup(struct fsi_priv *fsi, |
885 | int is_play, | |
886 | struct device *dev) | |
a4d7d550 | 887 | { |
93193c2b | 888 | u32 flags = fsi_get_info_flags(fsi); |
9478e0b6 | 889 | u32 data = 0; |
a4d7d550 | 890 | |
23ca8533 | 891 | pm_runtime_get_sync(dev); |
a4d7d550 | 892 | |
9478e0b6 KM |
893 | /* clock setting */ |
894 | if (fsi_is_clk_master(fsi)) | |
895 | data = DIMD | DOMD; | |
896 | ||
897 | fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data); | |
a4d7d550 KM |
898 | |
899 | /* clock inversion (CKG2) */ | |
900 | data = 0; | |
b427b44c KM |
901 | if (SH_FSI_LRM_INV & flags) |
902 | data |= 1 << 12; | |
903 | if (SH_FSI_BRM_INV & flags) | |
904 | data |= 1 << 8; | |
905 | if (SH_FSI_LRS_INV & flags) | |
906 | data |= 1 << 4; | |
907 | if (SH_FSI_BRS_INV & flags) | |
908 | data |= 1 << 0; | |
909 | ||
a4d7d550 KM |
910 | fsi_reg_write(fsi, CKG2, data); |
911 | ||
9478e0b6 KM |
912 | /* set format */ |
913 | fsi_reg_write(fsi, DO_FMT, fsi->do_fmt); | |
914 | fsi_reg_write(fsi, DI_FMT, fsi->di_fmt); | |
915 | ||
916 | /* spdif ? */ | |
917 | if (fsi_is_spdif(fsi)) { | |
918 | fsi_spdif_clk_ctrl(fsi, 1); | |
919 | fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD); | |
920 | } | |
921 | ||
10ea76cc KM |
922 | /* irq clear */ |
923 | fsi_irq_disable(fsi, is_play); | |
924 | fsi_irq_clear_status(fsi); | |
925 | ||
926 | /* fifo init */ | |
23ca8533 | 927 | fsi_fifo_init(fsi, is_play, dev); |
a4d7d550 | 928 | |
a68a3b4e | 929 | return 0; |
a4d7d550 KM |
930 | } |
931 | ||
23ca8533 KM |
932 | static void fsi_hw_shutdown(struct fsi_priv *fsi, |
933 | int is_play, | |
934 | struct device *dev) | |
935 | { | |
936 | if (fsi_is_clk_master(fsi)) | |
937 | fsi_set_master_clk(dev, fsi, fsi->rate, 0); | |
938 | ||
939 | pm_runtime_put_sync(dev); | |
940 | } | |
941 | ||
942 | static int fsi_dai_startup(struct snd_pcm_substream *substream, | |
943 | struct snd_soc_dai *dai) | |
944 | { | |
945 | struct fsi_priv *fsi = fsi_get_priv(substream); | |
946 | int is_play = fsi_is_play(substream); | |
947 | ||
948 | return fsi_hw_startup(fsi, is_play, dai->dev); | |
949 | } | |
950 | ||
a4d7d550 KM |
951 | static void fsi_dai_shutdown(struct snd_pcm_substream *substream, |
952 | struct snd_soc_dai *dai) | |
953 | { | |
71f6e064 | 954 | struct fsi_priv *fsi = fsi_get_priv(substream); |
23ca8533 | 955 | int is_play = fsi_is_play(substream); |
a4d7d550 | 956 | |
23ca8533 | 957 | fsi_hw_shutdown(fsi, is_play, dai->dev); |
d4bc99b9 | 958 | fsi->rate = 0; |
a4d7d550 KM |
959 | } |
960 | ||
961 | static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd, | |
962 | struct snd_soc_dai *dai) | |
963 | { | |
71f6e064 | 964 | struct fsi_priv *fsi = fsi_get_priv(substream); |
00545785 | 965 | int is_play = fsi_is_play(substream); |
a4d7d550 KM |
966 | int ret = 0; |
967 | ||
a4d7d550 KM |
968 | switch (cmd) { |
969 | case SNDRV_PCM_TRIGGER_START: | |
0ffe296a | 970 | fsi_stream_push(fsi, is_play, substream); |
1ec9bc35 | 971 | ret = is_play ? fsi_data_push(fsi) : fsi_data_pop(fsi); |
1ddddd36 | 972 | fsi_port_start(fsi, is_play); |
a4d7d550 KM |
973 | break; |
974 | case SNDRV_PCM_TRIGGER_STOP: | |
1ddddd36 | 975 | fsi_port_stop(fsi, is_play); |
93193c2b | 976 | fsi_stream_pop(fsi, is_play); |
a4d7d550 KM |
977 | break; |
978 | } | |
979 | ||
980 | return ret; | |
981 | } | |
982 | ||
f17c13ca KM |
983 | static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt) |
984 | { | |
985 | u32 data = 0; | |
986 | ||
987 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
988 | case SND_SOC_DAIFMT_I2S: | |
989 | data = CR_I2S; | |
990 | fsi->chan_num = 2; | |
991 | break; | |
992 | case SND_SOC_DAIFMT_LEFT_J: | |
993 | data = CR_PCM; | |
994 | fsi->chan_num = 2; | |
995 | break; | |
996 | default: | |
997 | return -EINVAL; | |
998 | } | |
999 | ||
9478e0b6 KM |
1000 | fsi->do_fmt = data; |
1001 | fsi->di_fmt = data; | |
f17c13ca KM |
1002 | |
1003 | return 0; | |
1004 | } | |
1005 | ||
1006 | static int fsi_set_fmt_spdif(struct fsi_priv *fsi) | |
1007 | { | |
1008 | struct fsi_master *master = fsi_get_master(fsi); | |
1009 | u32 data = 0; | |
1010 | ||
1011 | if (master->core->ver < 2) | |
1012 | return -EINVAL; | |
1013 | ||
1014 | data = CR_BWS_16 | CR_DTMD_SPDIF_PCM | CR_PCM; | |
1015 | fsi->chan_num = 2; | |
9478e0b6 | 1016 | fsi->spdif = 1; |
f17c13ca | 1017 | |
9478e0b6 KM |
1018 | fsi->do_fmt = data; |
1019 | fsi->di_fmt = data; | |
f17c13ca KM |
1020 | |
1021 | return 0; | |
1022 | } | |
1023 | ||
4d805f7b KM |
1024 | static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) |
1025 | { | |
1026 | struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai); | |
6a9ebad8 KM |
1027 | struct fsi_master *master = fsi_get_master(fsi); |
1028 | set_rate_func set_rate = fsi_get_info_set_rate(master); | |
f17c13ca | 1029 | u32 flags = fsi_get_info_flags(fsi); |
4d805f7b KM |
1030 | int ret; |
1031 | ||
4d805f7b KM |
1032 | /* set master/slave audio interface */ |
1033 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1034 | case SND_SOC_DAIFMT_CBM_CFM: | |
6a9ebad8 | 1035 | fsi->clk_master = 1; |
4d805f7b KM |
1036 | break; |
1037 | case SND_SOC_DAIFMT_CBS_CFS: | |
1038 | break; | |
1039 | default: | |
9478e0b6 | 1040 | return -EINVAL; |
4d805f7b | 1041 | } |
6a9ebad8 KM |
1042 | |
1043 | if (fsi_is_clk_master(fsi) && !set_rate) { | |
1044 | dev_err(dai->dev, "platform doesn't have set_rate\n"); | |
9478e0b6 | 1045 | return -EINVAL; |
6a9ebad8 KM |
1046 | } |
1047 | ||
f17c13ca KM |
1048 | /* set format */ |
1049 | switch (flags & SH_FSI_FMT_MASK) { | |
1050 | case SH_FSI_FMT_DAI: | |
1051 | ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK); | |
1052 | break; | |
1053 | case SH_FSI_FMT_SPDIF: | |
1054 | ret = fsi_set_fmt_spdif(fsi); | |
1055 | break; | |
1056 | default: | |
1057 | ret = -EINVAL; | |
1058 | } | |
4d805f7b | 1059 | |
4d805f7b KM |
1060 | return ret; |
1061 | } | |
1062 | ||
ccad7b44 KM |
1063 | static int fsi_dai_hw_params(struct snd_pcm_substream *substream, |
1064 | struct snd_pcm_hw_params *params, | |
1065 | struct snd_soc_dai *dai) | |
1066 | { | |
1067 | struct fsi_priv *fsi = fsi_get_priv(substream); | |
d4bc99b9 | 1068 | long rate = params_rate(params); |
ccad7b44 KM |
1069 | int ret; |
1070 | ||
6a9ebad8 | 1071 | if (!fsi_is_clk_master(fsi)) |
ccad7b44 KM |
1072 | return 0; |
1073 | ||
4f56cde1 KM |
1074 | ret = fsi_set_master_clk(dai->dev, fsi, rate, 1); |
1075 | if (ret < 0) | |
d4bc99b9 | 1076 | return ret; |
ccad7b44 | 1077 | |
d4bc99b9 | 1078 | fsi->rate = rate; |
ccad7b44 KM |
1079 | |
1080 | return ret; | |
ccad7b44 KM |
1081 | } |
1082 | ||
a4d7d550 KM |
1083 | static struct snd_soc_dai_ops fsi_dai_ops = { |
1084 | .startup = fsi_dai_startup, | |
1085 | .shutdown = fsi_dai_shutdown, | |
1086 | .trigger = fsi_dai_trigger, | |
4d805f7b | 1087 | .set_fmt = fsi_dai_set_fmt, |
ccad7b44 | 1088 | .hw_params = fsi_dai_hw_params, |
a4d7d550 KM |
1089 | }; |
1090 | ||
c8fe2574 KM |
1091 | /* |
1092 | * pcm ops | |
1093 | */ | |
a4d7d550 | 1094 | |
a4d7d550 KM |
1095 | static struct snd_pcm_hardware fsi_pcm_hardware = { |
1096 | .info = SNDRV_PCM_INFO_INTERLEAVED | | |
1097 | SNDRV_PCM_INFO_MMAP | | |
1098 | SNDRV_PCM_INFO_MMAP_VALID | | |
1099 | SNDRV_PCM_INFO_PAUSE, | |
1100 | .formats = FSI_FMTS, | |
1101 | .rates = FSI_RATES, | |
1102 | .rate_min = 8000, | |
1103 | .rate_max = 192000, | |
1104 | .channels_min = 1, | |
1105 | .channels_max = 2, | |
1106 | .buffer_bytes_max = 64 * 1024, | |
1107 | .period_bytes_min = 32, | |
1108 | .period_bytes_max = 8192, | |
1109 | .periods_min = 1, | |
1110 | .periods_max = 32, | |
1111 | .fifo_size = 256, | |
1112 | }; | |
1113 | ||
1114 | static int fsi_pcm_open(struct snd_pcm_substream *substream) | |
1115 | { | |
1116 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1117 | int ret = 0; | |
1118 | ||
1119 | snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware); | |
1120 | ||
1121 | ret = snd_pcm_hw_constraint_integer(runtime, | |
1122 | SNDRV_PCM_HW_PARAM_PERIODS); | |
1123 | ||
1124 | return ret; | |
1125 | } | |
1126 | ||
1127 | static int fsi_hw_params(struct snd_pcm_substream *substream, | |
1128 | struct snd_pcm_hw_params *hw_params) | |
1129 | { | |
1130 | return snd_pcm_lib_malloc_pages(substream, | |
1131 | params_buffer_bytes(hw_params)); | |
1132 | } | |
1133 | ||
1134 | static int fsi_hw_free(struct snd_pcm_substream *substream) | |
1135 | { | |
1136 | return snd_pcm_lib_free_pages(substream); | |
1137 | } | |
1138 | ||
1139 | static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream) | |
1140 | { | |
71f6e064 | 1141 | struct fsi_priv *fsi = fsi_get_priv(substream); |
93193c2b | 1142 | struct fsi_stream *io = fsi_get_stream(fsi, fsi_is_play(substream)); |
2e651baf | 1143 | int samples_pos = io->buff_sample_pos - 1; |
a4d7d550 | 1144 | |
2e651baf KM |
1145 | if (samples_pos < 0) |
1146 | samples_pos = 0; | |
a4d7d550 | 1147 | |
2e651baf | 1148 | return fsi_sample2frame(fsi, samples_pos); |
a4d7d550 KM |
1149 | } |
1150 | ||
1151 | static struct snd_pcm_ops fsi_pcm_ops = { | |
1152 | .open = fsi_pcm_open, | |
1153 | .ioctl = snd_pcm_lib_ioctl, | |
1154 | .hw_params = fsi_hw_params, | |
1155 | .hw_free = fsi_hw_free, | |
1156 | .pointer = fsi_pointer, | |
1157 | }; | |
1158 | ||
c8fe2574 KM |
1159 | /* |
1160 | * snd_soc_platform | |
1161 | */ | |
a4d7d550 | 1162 | |
a4d7d550 KM |
1163 | #define PREALLOC_BUFFER (32 * 1024) |
1164 | #define PREALLOC_BUFFER_MAX (32 * 1024) | |
1165 | ||
1166 | static void fsi_pcm_free(struct snd_pcm *pcm) | |
1167 | { | |
1168 | snd_pcm_lib_preallocate_free_for_all(pcm); | |
1169 | } | |
1170 | ||
552d1ef6 | 1171 | static int fsi_pcm_new(struct snd_soc_pcm_runtime *rtd) |
a4d7d550 | 1172 | { |
552d1ef6 LG |
1173 | struct snd_pcm *pcm = rtd->pcm; |
1174 | ||
a4d7d550 KM |
1175 | /* |
1176 | * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel | |
1177 | * in MMAP mode (i.e. aplay -M) | |
1178 | */ | |
1179 | return snd_pcm_lib_preallocate_pages_for_all( | |
1180 | pcm, | |
1181 | SNDRV_DMA_TYPE_CONTINUOUS, | |
1182 | snd_dma_continuous_data(GFP_KERNEL), | |
1183 | PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); | |
1184 | } | |
1185 | ||
c8fe2574 KM |
1186 | /* |
1187 | * alsa struct | |
1188 | */ | |
a4d7d550 | 1189 | |
f0fba2ad | 1190 | static struct snd_soc_dai_driver fsi_soc_dai[] = { |
a4d7d550 | 1191 | { |
f0fba2ad | 1192 | .name = "fsia-dai", |
a4d7d550 KM |
1193 | .playback = { |
1194 | .rates = FSI_RATES, | |
1195 | .formats = FSI_FMTS, | |
1196 | .channels_min = 1, | |
1197 | .channels_max = 8, | |
1198 | }, | |
07102f3c KM |
1199 | .capture = { |
1200 | .rates = FSI_RATES, | |
1201 | .formats = FSI_FMTS, | |
1202 | .channels_min = 1, | |
1203 | .channels_max = 8, | |
1204 | }, | |
a4d7d550 KM |
1205 | .ops = &fsi_dai_ops, |
1206 | }, | |
1207 | { | |
f0fba2ad | 1208 | .name = "fsib-dai", |
a4d7d550 KM |
1209 | .playback = { |
1210 | .rates = FSI_RATES, | |
1211 | .formats = FSI_FMTS, | |
1212 | .channels_min = 1, | |
1213 | .channels_max = 8, | |
1214 | }, | |
07102f3c KM |
1215 | .capture = { |
1216 | .rates = FSI_RATES, | |
1217 | .formats = FSI_FMTS, | |
1218 | .channels_min = 1, | |
1219 | .channels_max = 8, | |
1220 | }, | |
a4d7d550 KM |
1221 | .ops = &fsi_dai_ops, |
1222 | }, | |
1223 | }; | |
a4d7d550 | 1224 | |
f0fba2ad LG |
1225 | static struct snd_soc_platform_driver fsi_soc_platform = { |
1226 | .ops = &fsi_pcm_ops, | |
a4d7d550 KM |
1227 | .pcm_new = fsi_pcm_new, |
1228 | .pcm_free = fsi_pcm_free, | |
1229 | }; | |
a4d7d550 | 1230 | |
c8fe2574 KM |
1231 | /* |
1232 | * platform function | |
1233 | */ | |
a4d7d550 | 1234 | |
a4d7d550 KM |
1235 | static int fsi_probe(struct platform_device *pdev) |
1236 | { | |
71f6e064 | 1237 | struct fsi_master *master; |
cc780d38 | 1238 | const struct platform_device_id *id_entry; |
a4d7d550 | 1239 | struct resource *res; |
a4d7d550 KM |
1240 | unsigned int irq; |
1241 | int ret; | |
1242 | ||
cc780d38 KM |
1243 | id_entry = pdev->id_entry; |
1244 | if (!id_entry) { | |
1245 | dev_err(&pdev->dev, "unknown fsi device\n"); | |
1246 | return -ENODEV; | |
1247 | } | |
1248 | ||
a4d7d550 KM |
1249 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1250 | irq = platform_get_irq(pdev, 0); | |
b6aa1793 | 1251 | if (!res || (int)irq <= 0) { |
a4d7d550 KM |
1252 | dev_err(&pdev->dev, "Not enough FSI platform resources.\n"); |
1253 | ret = -ENODEV; | |
1254 | goto exit; | |
1255 | } | |
1256 | ||
1257 | master = kzalloc(sizeof(*master), GFP_KERNEL); | |
1258 | if (!master) { | |
1259 | dev_err(&pdev->dev, "Could not allocate master\n"); | |
1260 | ret = -ENOMEM; | |
1261 | goto exit; | |
1262 | } | |
1263 | ||
1264 | master->base = ioremap_nocache(res->start, resource_size(res)); | |
1265 | if (!master->base) { | |
1266 | ret = -ENXIO; | |
1267 | dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n"); | |
1268 | goto exit_kfree; | |
1269 | } | |
1270 | ||
3bc28070 | 1271 | /* master setting */ |
a4d7d550 KM |
1272 | master->irq = irq; |
1273 | master->info = pdev->dev.platform_data; | |
3bc28070 KM |
1274 | master->core = (struct fsi_core *)id_entry->driver_data; |
1275 | spin_lock_init(&master->lock); | |
1276 | ||
1277 | /* FSI A setting */ | |
a4d7d550 | 1278 | master->fsia.base = master->base; |
71f6e064 | 1279 | master->fsia.master = master; |
3bc28070 KM |
1280 | |
1281 | /* FSI B setting */ | |
a4d7d550 | 1282 | master->fsib.base = master->base + 0x40; |
71f6e064 | 1283 | master->fsib.master = master; |
a4d7d550 | 1284 | |
785d1c45 | 1285 | pm_runtime_enable(&pdev->dev); |
f0fba2ad | 1286 | dev_set_drvdata(&pdev->dev, master); |
a4d7d550 | 1287 | |
88e24c3a | 1288 | ret = request_irq(irq, &fsi_interrupt, 0, |
cc780d38 | 1289 | id_entry->name, master); |
a4d7d550 KM |
1290 | if (ret) { |
1291 | dev_err(&pdev->dev, "irq request err\n"); | |
9ddc9aa9 | 1292 | goto exit_iounmap; |
a4d7d550 KM |
1293 | } |
1294 | ||
f0fba2ad | 1295 | ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform); |
a4d7d550 KM |
1296 | if (ret < 0) { |
1297 | dev_err(&pdev->dev, "cannot snd soc register\n"); | |
1298 | goto exit_free_irq; | |
1299 | } | |
1300 | ||
0b5ec87d KM |
1301 | ret = snd_soc_register_dais(&pdev->dev, fsi_soc_dai, |
1302 | ARRAY_SIZE(fsi_soc_dai)); | |
1303 | if (ret < 0) { | |
1304 | dev_err(&pdev->dev, "cannot snd dai register\n"); | |
1305 | goto exit_snd_soc; | |
1306 | } | |
a4d7d550 | 1307 | |
0b5ec87d KM |
1308 | return ret; |
1309 | ||
1310 | exit_snd_soc: | |
1311 | snd_soc_unregister_platform(&pdev->dev); | |
a4d7d550 KM |
1312 | exit_free_irq: |
1313 | free_irq(irq, master); | |
a4d7d550 KM |
1314 | exit_iounmap: |
1315 | iounmap(master->base); | |
785d1c45 | 1316 | pm_runtime_disable(&pdev->dev); |
a4d7d550 KM |
1317 | exit_kfree: |
1318 | kfree(master); | |
1319 | master = NULL; | |
1320 | exit: | |
1321 | return ret; | |
1322 | } | |
1323 | ||
1324 | static int fsi_remove(struct platform_device *pdev) | |
1325 | { | |
71f6e064 KM |
1326 | struct fsi_master *master; |
1327 | ||
f0fba2ad | 1328 | master = dev_get_drvdata(&pdev->dev); |
71f6e064 | 1329 | |
d985f27e | 1330 | free_irq(master->irq, master); |
785d1c45 | 1331 | pm_runtime_disable(&pdev->dev); |
a4d7d550 | 1332 | |
d985f27e KM |
1333 | snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(fsi_soc_dai)); |
1334 | snd_soc_unregister_platform(&pdev->dev); | |
a4d7d550 KM |
1335 | |
1336 | iounmap(master->base); | |
1337 | kfree(master); | |
71f6e064 | 1338 | |
a4d7d550 KM |
1339 | return 0; |
1340 | } | |
1341 | ||
106c79ec | 1342 | static void __fsi_suspend(struct fsi_priv *fsi, |
cda828ca | 1343 | int is_play, |
4f56cde1 | 1344 | struct device *dev) |
106c79ec | 1345 | { |
cda828ca KM |
1346 | if (!fsi_stream_is_working(fsi, is_play)) |
1347 | return; | |
106c79ec | 1348 | |
cda828ca KM |
1349 | fsi_port_stop(fsi, is_play); |
1350 | fsi_hw_shutdown(fsi, is_play, dev); | |
106c79ec KM |
1351 | } |
1352 | ||
1353 | static void __fsi_resume(struct fsi_priv *fsi, | |
cda828ca | 1354 | int is_play, |
4f56cde1 | 1355 | struct device *dev) |
106c79ec | 1356 | { |
cda828ca KM |
1357 | if (!fsi_stream_is_working(fsi, is_play)) |
1358 | return; | |
106c79ec | 1359 | |
cda828ca KM |
1360 | fsi_hw_startup(fsi, is_play, dev); |
1361 | ||
1362 | if (fsi_is_clk_master(fsi) && fsi->rate) | |
4f56cde1 | 1363 | fsi_set_master_clk(dev, fsi, fsi->rate, 1); |
cda828ca KM |
1364 | |
1365 | fsi_port_start(fsi, is_play); | |
1366 | ||
106c79ec KM |
1367 | } |
1368 | ||
1369 | static int fsi_suspend(struct device *dev) | |
1370 | { | |
1371 | struct fsi_master *master = dev_get_drvdata(dev); | |
cda828ca KM |
1372 | struct fsi_priv *fsia = &master->fsia; |
1373 | struct fsi_priv *fsib = &master->fsib; | |
106c79ec | 1374 | |
cda828ca KM |
1375 | __fsi_suspend(fsia, 1, dev); |
1376 | __fsi_suspend(fsia, 0, dev); | |
106c79ec | 1377 | |
cda828ca KM |
1378 | __fsi_suspend(fsib, 1, dev); |
1379 | __fsi_suspend(fsib, 0, dev); | |
106c79ec KM |
1380 | |
1381 | return 0; | |
1382 | } | |
1383 | ||
1384 | static int fsi_resume(struct device *dev) | |
1385 | { | |
1386 | struct fsi_master *master = dev_get_drvdata(dev); | |
cda828ca KM |
1387 | struct fsi_priv *fsia = &master->fsia; |
1388 | struct fsi_priv *fsib = &master->fsib; | |
106c79ec | 1389 | |
cda828ca KM |
1390 | __fsi_resume(fsia, 1, dev); |
1391 | __fsi_resume(fsia, 0, dev); | |
106c79ec | 1392 | |
cda828ca KM |
1393 | __fsi_resume(fsib, 1, dev); |
1394 | __fsi_resume(fsib, 0, dev); | |
106c79ec KM |
1395 | |
1396 | return 0; | |
1397 | } | |
1398 | ||
785d1c45 KM |
1399 | static int fsi_runtime_nop(struct device *dev) |
1400 | { | |
1401 | /* Runtime PM callback shared between ->runtime_suspend() | |
1402 | * and ->runtime_resume(). Simply returns success. | |
1403 | * | |
1404 | * This driver re-initializes all registers after | |
1405 | * pm_runtime_get_sync() anyway so there is no need | |
1406 | * to save and restore registers here. | |
1407 | */ | |
1408 | return 0; | |
1409 | } | |
1410 | ||
1411 | static struct dev_pm_ops fsi_pm_ops = { | |
106c79ec KM |
1412 | .suspend = fsi_suspend, |
1413 | .resume = fsi_resume, | |
785d1c45 KM |
1414 | .runtime_suspend = fsi_runtime_nop, |
1415 | .runtime_resume = fsi_runtime_nop, | |
1416 | }; | |
1417 | ||
73b92c1f KM |
1418 | static struct fsi_core fsi1_core = { |
1419 | .ver = 1, | |
1420 | ||
1421 | /* Interrupt */ | |
cc780d38 KM |
1422 | .int_st = INT_ST, |
1423 | .iemsk = IEMSK, | |
1424 | .imsk = IMSK, | |
1425 | }; | |
1426 | ||
73b92c1f KM |
1427 | static struct fsi_core fsi2_core = { |
1428 | .ver = 2, | |
1429 | ||
1430 | /* Interrupt */ | |
cc780d38 KM |
1431 | .int_st = CPU_INT_ST, |
1432 | .iemsk = CPU_IEMSK, | |
1433 | .imsk = CPU_IMSK, | |
2b0e7302 KM |
1434 | .a_mclk = A_MST_CTLR, |
1435 | .b_mclk = B_MST_CTLR, | |
cc780d38 KM |
1436 | }; |
1437 | ||
1438 | static struct platform_device_id fsi_id_table[] = { | |
73b92c1f KM |
1439 | { "sh_fsi", (kernel_ulong_t)&fsi1_core }, |
1440 | { "sh_fsi2", (kernel_ulong_t)&fsi2_core }, | |
05c69450 | 1441 | {}, |
cc780d38 | 1442 | }; |
d85a6d7b | 1443 | MODULE_DEVICE_TABLE(platform, fsi_id_table); |
cc780d38 | 1444 | |
a4d7d550 KM |
1445 | static struct platform_driver fsi_driver = { |
1446 | .driver = { | |
f0fba2ad | 1447 | .name = "fsi-pcm-audio", |
785d1c45 | 1448 | .pm = &fsi_pm_ops, |
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1449 | }, |
1450 | .probe = fsi_probe, | |
1451 | .remove = fsi_remove, | |
cc780d38 | 1452 | .id_table = fsi_id_table, |
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1453 | }; |
1454 | ||
1455 | static int __init fsi_mobile_init(void) | |
1456 | { | |
1457 | return platform_driver_register(&fsi_driver); | |
1458 | } | |
1459 | ||
1460 | static void __exit fsi_mobile_exit(void) | |
1461 | { | |
1462 | platform_driver_unregister(&fsi_driver); | |
1463 | } | |
d85a6d7b | 1464 | |
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1465 | module_init(fsi_mobile_init); |
1466 | module_exit(fsi_mobile_exit); | |
1467 | ||
1468 | MODULE_LICENSE("GPL"); | |
1469 | MODULE_DESCRIPTION("SuperH onchip FSI audio driver"); | |
1470 | MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>"); | |
b3c27b51 | 1471 | MODULE_ALIAS("platform:fsi-pcm-audio"); |