Commit | Line | Data |
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a4d7d550 KM |
1 | /* |
2 | * Fifo-attached Serial Interface (FSI) support for SH7724 | |
3 | * | |
4 | * Copyright (C) 2009 Renesas Solutions Corp. | |
5 | * Kuninori Morimoto <morimoto.kuninori@renesas.com> | |
6 | * | |
7 | * Based on ssi.c | |
8 | * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
a4d7d550 | 15 | #include <linux/delay.h> |
785d1c45 | 16 | #include <linux/pm_runtime.h> |
a4d7d550 | 17 | #include <linux/io.h> |
5a0e3ad6 | 18 | #include <linux/slab.h> |
da155d5b | 19 | #include <linux/module.h> |
a4d7d550 | 20 | #include <sound/soc.h> |
a4d7d550 | 21 | #include <sound/sh_fsi.h> |
a4d7d550 | 22 | |
e8c8b631 KM |
23 | /* PortA/PortB register */ |
24 | #define REG_DO_FMT 0x0000 | |
25 | #define REG_DOFF_CTL 0x0004 | |
26 | #define REG_DOFF_ST 0x0008 | |
27 | #define REG_DI_FMT 0x000C | |
28 | #define REG_DIFF_CTL 0x0010 | |
29 | #define REG_DIFF_ST 0x0014 | |
30 | #define REG_CKG1 0x0018 | |
31 | #define REG_CKG2 0x001C | |
32 | #define REG_DIDT 0x0020 | |
33 | #define REG_DODT 0x0024 | |
34 | #define REG_MUTE_ST 0x0028 | |
35 | #define REG_OUT_SEL 0x0030 | |
cc780d38 | 36 | |
43fa95ca KM |
37 | /* master register */ |
38 | #define MST_CLK_RST 0x0210 | |
39 | #define MST_SOFT_RST 0x0214 | |
40 | #define MST_FIFO_SZ 0x0218 | |
41 | ||
42 | /* core register (depend on FSI version) */ | |
3bc28070 KM |
43 | #define A_MST_CTLR 0x0180 |
44 | #define B_MST_CTLR 0x01A0 | |
cc780d38 KM |
45 | #define CPU_INT_ST 0x01F4 |
46 | #define CPU_IEMSK 0x01F8 | |
47 | #define CPU_IMSK 0x01FC | |
a4d7d550 KM |
48 | #define INT_ST 0x0200 |
49 | #define IEMSK 0x0204 | |
50 | #define IMSK 0x0208 | |
a4d7d550 KM |
51 | |
52 | /* DO_FMT */ | |
53 | /* DI_FMT */ | |
f7d711e3 KM |
54 | #define CR_BWS_24 (0x0 << 20) /* FSI2 */ |
55 | #define CR_BWS_16 (0x1 << 20) /* FSI2 */ | |
56 | #define CR_BWS_20 (0x2 << 20) /* FSI2 */ | |
57 | ||
58 | #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */ | |
59 | #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */ | |
60 | #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */ | |
61 | ||
a7ffb52b KM |
62 | #define CR_MONO (0x0 << 4) |
63 | #define CR_MONO_D (0x1 << 4) | |
64 | #define CR_PCM (0x2 << 4) | |
65 | #define CR_I2S (0x3 << 4) | |
66 | #define CR_TDM (0x4 << 4) | |
67 | #define CR_TDM_D (0x5 << 4) | |
a4d7d550 KM |
68 | |
69 | /* DOFF_CTL */ | |
70 | /* DIFF_CTL */ | |
71 | #define IRQ_HALF 0x00100000 | |
72 | #define FIFO_CLR 0x00000001 | |
73 | ||
74 | /* DOFF_ST */ | |
75 | #define ERR_OVER 0x00000010 | |
76 | #define ERR_UNDER 0x00000001 | |
59c3b003 | 77 | #define ST_ERR (ERR_OVER | ERR_UNDER) |
a4d7d550 | 78 | |
ccad7b44 KM |
79 | /* CKG1 */ |
80 | #define ACKMD_MASK 0x00007000 | |
81 | #define BPFMD_MASK 0x00000700 | |
4d805f7b KM |
82 | #define DIMD (1 << 4) |
83 | #define DOMD (1 << 0) | |
ccad7b44 | 84 | |
3bc28070 KM |
85 | /* A/B MST_CTLR */ |
86 | #define BP (1 << 4) /* Fix the signal of Biphase output */ | |
87 | #define SE (1 << 0) /* Fix the master clock */ | |
88 | ||
a4d7d550 | 89 | /* CLK_RST */ |
1f5e2a31 KM |
90 | #define CRB (1 << 4) |
91 | #define CRA (1 << 0) | |
a4d7d550 | 92 | |
cf6edd00 KM |
93 | /* IO SHIFT / MACRO */ |
94 | #define BI_SHIFT 12 | |
95 | #define BO_SHIFT 8 | |
96 | #define AI_SHIFT 4 | |
97 | #define AO_SHIFT 0 | |
98 | #define AB_IO(param, shift) (param << shift) | |
a4d7d550 | 99 | |
feb58cff KM |
100 | /* SOFT_RST */ |
101 | #define PBSR (1 << 12) /* Port B Software Reset */ | |
102 | #define PASR (1 << 8) /* Port A Software Reset */ | |
103 | #define IR (1 << 4) /* Interrupt Reset */ | |
104 | #define FSISR (1 << 0) /* Software Reset */ | |
105 | ||
f7d711e3 KM |
106 | /* OUT_SEL (FSI2) */ |
107 | #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */ | |
108 | /* 1: Biphase and serial */ | |
109 | ||
4a942b45 | 110 | /* FIFO_SZ */ |
cf6edd00 | 111 | #define FIFO_SZ_MASK 0x7 |
4a942b45 | 112 | |
a4d7d550 KM |
113 | #define FSI_RATES SNDRV_PCM_RATE_8000_96000 |
114 | ||
115 | #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE) | |
116 | ||
d7c5762b KM |
117 | typedef int (*set_rate_func)(struct device *dev, int is_porta, int rate, int enable); |
118 | ||
5bfb9ad0 KM |
119 | /* |
120 | * FSI driver use below type name for variable | |
121 | * | |
5bfb9ad0 | 122 | * xxx_num : number of data |
2e651baf KM |
123 | * xxx_pos : position of data |
124 | * xxx_capa : capacity of data | |
125 | */ | |
126 | ||
127 | /* | |
128 | * period/frame/sample image | |
129 | * | |
130 | * ex) PCM (2ch) | |
131 | * | |
132 | * period pos period pos | |
133 | * [n] [n + 1] | |
134 | * |<-------------------- period--------------------->| | |
135 | * ==|============================================ ... =|== | |
136 | * | | | |
137 | * ||<----- frame ----->|<------ frame ----->| ... | | |
138 | * |+--------------------+--------------------+- ... | | |
139 | * ||[ sample ][ sample ]|[ sample ][ sample ]| ... | | |
140 | * |+--------------------+--------------------+- ... | | |
141 | * ==|============================================ ... =|== | |
142 | */ | |
143 | ||
144 | /* | |
145 | * FSI FIFO image | |
146 | * | |
147 | * | | | |
148 | * | | | |
149 | * | [ sample ] | | |
150 | * | [ sample ] | | |
151 | * | [ sample ] | | |
152 | * | [ sample ] | | |
153 | * --> go to codecs | |
5bfb9ad0 KM |
154 | */ |
155 | ||
c8fe2574 KM |
156 | /* |
157 | * struct | |
158 | */ | |
a4d7d550 | 159 | |
93193c2b | 160 | struct fsi_stream { |
a4d7d550 KM |
161 | struct snd_pcm_substream *substream; |
162 | ||
2e651baf KM |
163 | int fifo_sample_capa; /* sample capacity of FSI FIFO */ |
164 | int buff_sample_capa; /* sample capacity of ALSA buffer */ | |
165 | int buff_sample_pos; /* sample position of ALSA buffer */ | |
166 | int period_samples; /* sample number / 1 period */ | |
167 | int period_pos; /* current period position */ | |
1ec9bc35 KM |
168 | |
169 | int uerr_num; | |
170 | int oerr_num; | |
93193c2b KM |
171 | }; |
172 | ||
173 | struct fsi_priv { | |
174 | void __iomem *base; | |
175 | struct fsi_master *master; | |
176 | ||
177 | struct fsi_stream playback; | |
178 | struct fsi_stream capture; | |
3bc28070 | 179 | |
9478e0b6 KM |
180 | u32 do_fmt; |
181 | u32 di_fmt; | |
182 | ||
6a9ebad8 KM |
183 | int chan_num:16; |
184 | int clk_master:1; | |
9478e0b6 | 185 | int spdif:1; |
6a9ebad8 | 186 | |
d4bc99b9 | 187 | long rate; |
a4d7d550 KM |
188 | }; |
189 | ||
73b92c1f KM |
190 | struct fsi_core { |
191 | int ver; | |
192 | ||
cc780d38 KM |
193 | u32 int_st; |
194 | u32 iemsk; | |
195 | u32 imsk; | |
2b0e7302 KM |
196 | u32 a_mclk; |
197 | u32 b_mclk; | |
cc780d38 KM |
198 | }; |
199 | ||
a4d7d550 KM |
200 | struct fsi_master { |
201 | void __iomem *base; | |
202 | int irq; | |
a4d7d550 KM |
203 | struct fsi_priv fsia; |
204 | struct fsi_priv fsib; | |
73b92c1f | 205 | struct fsi_core *core; |
a4d7d550 | 206 | struct sh_fsi_platform_info *info; |
8fc176d5 | 207 | spinlock_t lock; |
a4d7d550 KM |
208 | }; |
209 | ||
c8fe2574 KM |
210 | /* |
211 | * basic read write function | |
212 | */ | |
a4d7d550 | 213 | |
ca7aceef | 214 | static void __fsi_reg_write(u32 __iomem *reg, u32 data) |
a4d7d550 KM |
215 | { |
216 | /* valid data area is 24bit */ | |
217 | data &= 0x00ffffff; | |
218 | ||
0f69d978 | 219 | __raw_writel(data, reg); |
a4d7d550 KM |
220 | } |
221 | ||
ca7aceef | 222 | static u32 __fsi_reg_read(u32 __iomem *reg) |
a4d7d550 | 223 | { |
0f69d978 | 224 | return __raw_readl(reg); |
a4d7d550 KM |
225 | } |
226 | ||
ca7aceef | 227 | static void __fsi_reg_mask_set(u32 __iomem *reg, u32 mask, u32 data) |
a4d7d550 KM |
228 | { |
229 | u32 val = __fsi_reg_read(reg); | |
230 | ||
231 | val &= ~mask; | |
232 | val |= data & mask; | |
233 | ||
0f69d978 | 234 | __fsi_reg_write(reg, val); |
a4d7d550 KM |
235 | } |
236 | ||
e8c8b631 | 237 | #define fsi_reg_write(p, r, d)\ |
8918b843 | 238 | __fsi_reg_write((p->base + REG_##r), d) |
a4d7d550 | 239 | |
e8c8b631 | 240 | #define fsi_reg_read(p, r)\ |
8918b843 | 241 | __fsi_reg_read((p->base + REG_##r)) |
a4d7d550 | 242 | |
e8c8b631 | 243 | #define fsi_reg_mask_set(p, r, m, d)\ |
8918b843 | 244 | __fsi_reg_mask_set((p->base + REG_##r), m, d) |
a4d7d550 | 245 | |
43fa95ca KM |
246 | #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r) |
247 | #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r) | |
248 | static u32 _fsi_master_read(struct fsi_master *master, u32 reg) | |
a4d7d550 | 249 | { |
8fc176d5 KM |
250 | u32 ret; |
251 | unsigned long flags; | |
252 | ||
8fc176d5 | 253 | spin_lock_irqsave(&master->lock, flags); |
ca7aceef | 254 | ret = __fsi_reg_read(master->base + reg); |
8fc176d5 KM |
255 | spin_unlock_irqrestore(&master->lock, flags); |
256 | ||
257 | return ret; | |
a4d7d550 KM |
258 | } |
259 | ||
43fa95ca KM |
260 | #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d) |
261 | #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d) | |
262 | static void _fsi_master_mask_set(struct fsi_master *master, | |
71f6e064 | 263 | u32 reg, u32 mask, u32 data) |
a4d7d550 | 264 | { |
8fc176d5 KM |
265 | unsigned long flags; |
266 | ||
8fc176d5 | 267 | spin_lock_irqsave(&master->lock, flags); |
ca7aceef | 268 | __fsi_reg_mask_set(master->base + reg, mask, data); |
8fc176d5 | 269 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
270 | } |
271 | ||
c8fe2574 KM |
272 | /* |
273 | * basic function | |
274 | */ | |
a4d7d550 | 275 | |
71f6e064 | 276 | static struct fsi_master *fsi_get_master(struct fsi_priv *fsi) |
a4d7d550 | 277 | { |
71f6e064 | 278 | return fsi->master; |
a4d7d550 KM |
279 | } |
280 | ||
6a9ebad8 KM |
281 | static int fsi_is_clk_master(struct fsi_priv *fsi) |
282 | { | |
283 | return fsi->clk_master; | |
284 | } | |
285 | ||
a4d7d550 KM |
286 | static int fsi_is_port_a(struct fsi_priv *fsi) |
287 | { | |
71f6e064 KM |
288 | return fsi->master->base == fsi->base; |
289 | } | |
a4d7d550 | 290 | |
9478e0b6 KM |
291 | static int fsi_is_spdif(struct fsi_priv *fsi) |
292 | { | |
293 | return fsi->spdif; | |
294 | } | |
295 | ||
142e8174 | 296 | static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream) |
71f6e064 KM |
297 | { |
298 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
142e8174 | 299 | |
f0fba2ad | 300 | return rtd->cpu_dai; |
142e8174 KM |
301 | } |
302 | ||
0d032c19 | 303 | static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai) |
142e8174 | 304 | { |
f0fba2ad | 305 | struct fsi_master *master = snd_soc_dai_get_drvdata(dai); |
a4d7d550 | 306 | |
f0fba2ad LG |
307 | if (dai->id == 0) |
308 | return &master->fsia; | |
309 | else | |
310 | return &master->fsib; | |
a4d7d550 KM |
311 | } |
312 | ||
0d032c19 KM |
313 | static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream) |
314 | { | |
315 | return fsi_get_priv_frm_dai(fsi_get_dai(substream)); | |
316 | } | |
317 | ||
d7c5762b KM |
318 | static set_rate_func fsi_get_info_set_rate(struct fsi_master *master) |
319 | { | |
320 | if (!master->info) | |
321 | return NULL; | |
322 | ||
323 | return master->info->set_rate; | |
324 | } | |
325 | ||
a4d7d550 KM |
326 | static u32 fsi_get_info_flags(struct fsi_priv *fsi) |
327 | { | |
328 | int is_porta = fsi_is_port_a(fsi); | |
71f6e064 | 329 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 330 | |
d7c5762b KM |
331 | if (!master->info) |
332 | return 0; | |
333 | ||
a4d7d550 KM |
334 | return is_porta ? master->info->porta_flags : |
335 | master->info->portb_flags; | |
336 | } | |
337 | ||
93193c2b KM |
338 | static inline int fsi_stream_is_play(int stream) |
339 | { | |
340 | return stream == SNDRV_PCM_STREAM_PLAYBACK; | |
341 | } | |
342 | ||
00545785 KM |
343 | static inline int fsi_is_play(struct snd_pcm_substream *substream) |
344 | { | |
93193c2b KM |
345 | return fsi_stream_is_play(substream->stream); |
346 | } | |
347 | ||
348 | static inline struct fsi_stream *fsi_get_stream(struct fsi_priv *fsi, | |
349 | int is_play) | |
350 | { | |
351 | return is_play ? &fsi->playback : &fsi->capture; | |
00545785 KM |
352 | } |
353 | ||
cf6edd00 | 354 | static u32 fsi_get_port_shift(struct fsi_priv *fsi, int is_play) |
a4d7d550 KM |
355 | { |
356 | int is_porta = fsi_is_port_a(fsi); | |
cf6edd00 | 357 | u32 shift; |
a4d7d550 KM |
358 | |
359 | if (is_porta) | |
cf6edd00 | 360 | shift = is_play ? AO_SHIFT : AI_SHIFT; |
a4d7d550 | 361 | else |
cf6edd00 | 362 | shift = is_play ? BO_SHIFT : BI_SHIFT; |
a4d7d550 | 363 | |
cf6edd00 | 364 | return shift; |
a4d7d550 KM |
365 | } |
366 | ||
2e651baf KM |
367 | static int fsi_frame2sample(struct fsi_priv *fsi, int frames) |
368 | { | |
369 | return frames * fsi->chan_num; | |
370 | } | |
371 | ||
372 | static int fsi_sample2frame(struct fsi_priv *fsi, int samples) | |
373 | { | |
374 | return samples / fsi->chan_num; | |
375 | } | |
376 | ||
cda828ca KM |
377 | static int fsi_stream_is_working(struct fsi_priv *fsi, |
378 | int is_play) | |
379 | { | |
380 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); | |
381 | struct fsi_master *master = fsi_get_master(fsi); | |
382 | unsigned long flags; | |
383 | int ret; | |
384 | ||
385 | spin_lock_irqsave(&master->lock, flags); | |
386 | ret = !!io->substream; | |
387 | spin_unlock_irqrestore(&master->lock, flags); | |
388 | ||
389 | return ret; | |
390 | } | |
391 | ||
a4d7d550 | 392 | static void fsi_stream_push(struct fsi_priv *fsi, |
93193c2b | 393 | int is_play, |
0ffe296a | 394 | struct snd_pcm_substream *substream) |
a4d7d550 | 395 | { |
93193c2b | 396 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); |
0ffe296a | 397 | struct snd_pcm_runtime *runtime = substream->runtime; |
2da65892 KM |
398 | struct fsi_master *master = fsi_get_master(fsi); |
399 | unsigned long flags; | |
93193c2b | 400 | |
2da65892 | 401 | spin_lock_irqsave(&master->lock, flags); |
93193c2b | 402 | io->substream = substream; |
2e651baf KM |
403 | io->buff_sample_capa = fsi_frame2sample(fsi, runtime->buffer_size); |
404 | io->buff_sample_pos = 0; | |
405 | io->period_samples = fsi_frame2sample(fsi, runtime->period_size); | |
406 | io->period_pos = 0; | |
1ec9bc35 KM |
407 | io->oerr_num = -1; /* ignore 1st err */ |
408 | io->uerr_num = -1; /* ignore 1st err */ | |
2da65892 | 409 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
410 | } |
411 | ||
93193c2b | 412 | static void fsi_stream_pop(struct fsi_priv *fsi, int is_play) |
a4d7d550 | 413 | { |
93193c2b | 414 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); |
1ec9bc35 | 415 | struct snd_soc_dai *dai = fsi_get_dai(io->substream); |
2da65892 KM |
416 | struct fsi_master *master = fsi_get_master(fsi); |
417 | unsigned long flags; | |
1ec9bc35 | 418 | |
2da65892 | 419 | spin_lock_irqsave(&master->lock, flags); |
1ec9bc35 KM |
420 | |
421 | if (io->oerr_num > 0) | |
422 | dev_err(dai->dev, "over_run = %d\n", io->oerr_num); | |
423 | ||
424 | if (io->uerr_num > 0) | |
425 | dev_err(dai->dev, "under_run = %d\n", io->uerr_num); | |
93193c2b KM |
426 | |
427 | io->substream = NULL; | |
2e651baf KM |
428 | io->buff_sample_capa = 0; |
429 | io->buff_sample_pos = 0; | |
430 | io->period_samples = 0; | |
431 | io->period_pos = 0; | |
1ec9bc35 KM |
432 | io->oerr_num = 0; |
433 | io->uerr_num = 0; | |
2da65892 | 434 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
435 | } |
436 | ||
2e651baf | 437 | static int fsi_get_current_fifo_samples(struct fsi_priv *fsi, int is_play) |
a4d7d550 KM |
438 | { |
439 | u32 status; | |
2e651baf | 440 | int frames; |
a4d7d550 | 441 | |
e8c8b631 KM |
442 | status = is_play ? |
443 | fsi_reg_read(fsi, DOFF_ST) : | |
444 | fsi_reg_read(fsi, DIFF_ST); | |
445 | ||
2e651baf | 446 | frames = 0x1ff & (status >> 8); |
5bfb9ad0 | 447 | |
2e651baf | 448 | return fsi_frame2sample(fsi, frames); |
cca1b235 KM |
449 | } |
450 | ||
1ec9bc35 KM |
451 | static void fsi_count_fifo_err(struct fsi_priv *fsi) |
452 | { | |
453 | u32 ostatus = fsi_reg_read(fsi, DOFF_ST); | |
454 | u32 istatus = fsi_reg_read(fsi, DIFF_ST); | |
455 | ||
456 | if (ostatus & ERR_OVER) | |
457 | fsi->playback.oerr_num++; | |
458 | ||
459 | if (ostatus & ERR_UNDER) | |
460 | fsi->playback.uerr_num++; | |
461 | ||
462 | if (istatus & ERR_OVER) | |
463 | fsi->capture.oerr_num++; | |
464 | ||
465 | if (istatus & ERR_UNDER) | |
466 | fsi->capture.uerr_num++; | |
467 | ||
468 | fsi_reg_write(fsi, DOFF_ST, 0); | |
469 | fsi_reg_write(fsi, DIFF_ST, 0); | |
470 | } | |
471 | ||
b9fde18c KM |
472 | /* |
473 | * dma function | |
474 | */ | |
475 | ||
93193c2b | 476 | static u8 *fsi_dma_get_area(struct fsi_priv *fsi, int stream) |
c79eab3e | 477 | { |
93193c2b KM |
478 | int is_play = fsi_stream_is_play(stream); |
479 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); | |
2e651baf | 480 | struct snd_pcm_runtime *runtime = io->substream->runtime; |
93193c2b | 481 | |
2e651baf KM |
482 | return runtime->dma_area + |
483 | samples_to_bytes(runtime, io->buff_sample_pos); | |
c79eab3e KM |
484 | } |
485 | ||
5bfb9ad0 | 486 | static void fsi_dma_soft_push16(struct fsi_priv *fsi, int num) |
b9fde18c KM |
487 | { |
488 | u16 *start; | |
489 | int i; | |
490 | ||
93193c2b | 491 | start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK); |
b9fde18c | 492 | |
5bfb9ad0 | 493 | for (i = 0; i < num; i++) |
b9fde18c KM |
494 | fsi_reg_write(fsi, DODT, ((u32)*(start + i) << 8)); |
495 | } | |
496 | ||
5bfb9ad0 | 497 | static void fsi_dma_soft_pop16(struct fsi_priv *fsi, int num) |
b9fde18c KM |
498 | { |
499 | u16 *start; | |
500 | int i; | |
501 | ||
93193c2b KM |
502 | start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE); |
503 | ||
b9fde18c | 504 | |
5bfb9ad0 | 505 | for (i = 0; i < num; i++) |
b9fde18c KM |
506 | *(start + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8); |
507 | } | |
508 | ||
5bfb9ad0 | 509 | static void fsi_dma_soft_push32(struct fsi_priv *fsi, int num) |
b9fde18c KM |
510 | { |
511 | u32 *start; | |
512 | int i; | |
513 | ||
93193c2b KM |
514 | start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK); |
515 | ||
b9fde18c | 516 | |
5bfb9ad0 | 517 | for (i = 0; i < num; i++) |
b9fde18c KM |
518 | fsi_reg_write(fsi, DODT, *(start + i)); |
519 | } | |
520 | ||
5bfb9ad0 | 521 | static void fsi_dma_soft_pop32(struct fsi_priv *fsi, int num) |
b9fde18c KM |
522 | { |
523 | u32 *start; | |
524 | int i; | |
525 | ||
93193c2b | 526 | start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE); |
b9fde18c | 527 | |
5bfb9ad0 | 528 | for (i = 0; i < num; i++) |
b9fde18c KM |
529 | *(start + i) = fsi_reg_read(fsi, DIDT); |
530 | } | |
531 | ||
c8fe2574 KM |
532 | /* |
533 | * irq function | |
534 | */ | |
a4d7d550 | 535 | |
a4d7d550 KM |
536 | static void fsi_irq_enable(struct fsi_priv *fsi, int is_play) |
537 | { | |
cf6edd00 | 538 | u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play)); |
71f6e064 | 539 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 540 | |
43fa95ca KM |
541 | fsi_core_mask_set(master, imsk, data, data); |
542 | fsi_core_mask_set(master, iemsk, data, data); | |
a4d7d550 KM |
543 | } |
544 | ||
545 | static void fsi_irq_disable(struct fsi_priv *fsi, int is_play) | |
546 | { | |
cf6edd00 | 547 | u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play)); |
71f6e064 | 548 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 549 | |
43fa95ca KM |
550 | fsi_core_mask_set(master, imsk, data, 0); |
551 | fsi_core_mask_set(master, iemsk, data, 0); | |
a4d7d550 KM |
552 | } |
553 | ||
10ea76cc KM |
554 | static u32 fsi_irq_get_status(struct fsi_master *master) |
555 | { | |
43fa95ca | 556 | return fsi_core_read(master, int_st); |
10ea76cc KM |
557 | } |
558 | ||
10ea76cc KM |
559 | static void fsi_irq_clear_status(struct fsi_priv *fsi) |
560 | { | |
561 | u32 data = 0; | |
562 | struct fsi_master *master = fsi_get_master(fsi); | |
563 | ||
cf6edd00 KM |
564 | data |= AB_IO(1, fsi_get_port_shift(fsi, 0)); |
565 | data |= AB_IO(1, fsi_get_port_shift(fsi, 1)); | |
10ea76cc KM |
566 | |
567 | /* clear interrupt factor */ | |
43fa95ca | 568 | fsi_core_mask_set(master, int_st, data, 0); |
10ea76cc KM |
569 | } |
570 | ||
c8fe2574 KM |
571 | /* |
572 | * SPDIF master clock function | |
573 | * | |
574 | * These functions are used later FSI2 | |
575 | */ | |
3bc28070 KM |
576 | static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable) |
577 | { | |
578 | struct fsi_master *master = fsi_get_master(fsi); | |
2b0e7302 | 579 | u32 mask, val; |
3bc28070 KM |
580 | |
581 | if (master->core->ver < 2) { | |
582 | pr_err("fsi: register access err (%s)\n", __func__); | |
583 | return; | |
584 | } | |
585 | ||
2b0e7302 KM |
586 | mask = BP | SE; |
587 | val = enable ? mask : 0; | |
588 | ||
589 | fsi_is_port_a(fsi) ? | |
43fa95ca KM |
590 | fsi_core_mask_set(master, a_mclk, mask, val) : |
591 | fsi_core_mask_set(master, b_mclk, mask, val); | |
3bc28070 KM |
592 | } |
593 | ||
c8fe2574 | 594 | /* |
1f5e2a31 | 595 | * clock function |
c8fe2574 | 596 | */ |
4f56cde1 KM |
597 | static int fsi_set_master_clk(struct device *dev, struct fsi_priv *fsi, |
598 | long rate, int enable) | |
599 | { | |
600 | struct fsi_master *master = fsi_get_master(fsi); | |
601 | set_rate_func set_rate = fsi_get_info_set_rate(master); | |
602 | int fsi_ver = master->core->ver; | |
603 | int ret; | |
604 | ||
605 | ret = set_rate(dev, fsi_is_port_a(fsi), rate, enable); | |
606 | if (ret < 0) /* error */ | |
607 | return ret; | |
608 | ||
609 | if (!enable) | |
610 | return 0; | |
611 | ||
612 | if (ret > 0) { | |
613 | u32 data = 0; | |
614 | ||
615 | switch (ret & SH_FSI_ACKMD_MASK) { | |
616 | default: | |
617 | /* FALL THROUGH */ | |
618 | case SH_FSI_ACKMD_512: | |
619 | data |= (0x0 << 12); | |
620 | break; | |
621 | case SH_FSI_ACKMD_256: | |
622 | data |= (0x1 << 12); | |
623 | break; | |
624 | case SH_FSI_ACKMD_128: | |
625 | data |= (0x2 << 12); | |
626 | break; | |
627 | case SH_FSI_ACKMD_64: | |
628 | data |= (0x3 << 12); | |
629 | break; | |
630 | case SH_FSI_ACKMD_32: | |
631 | if (fsi_ver < 2) | |
632 | dev_err(dev, "unsupported ACKMD\n"); | |
633 | else | |
634 | data |= (0x4 << 12); | |
635 | break; | |
636 | } | |
637 | ||
638 | switch (ret & SH_FSI_BPFMD_MASK) { | |
639 | default: | |
640 | /* FALL THROUGH */ | |
641 | case SH_FSI_BPFMD_32: | |
642 | data |= (0x0 << 8); | |
643 | break; | |
644 | case SH_FSI_BPFMD_64: | |
645 | data |= (0x1 << 8); | |
646 | break; | |
647 | case SH_FSI_BPFMD_128: | |
648 | data |= (0x2 << 8); | |
649 | break; | |
650 | case SH_FSI_BPFMD_256: | |
651 | data |= (0x3 << 8); | |
652 | break; | |
653 | case SH_FSI_BPFMD_512: | |
654 | data |= (0x4 << 8); | |
655 | break; | |
656 | case SH_FSI_BPFMD_16: | |
657 | if (fsi_ver < 2) | |
658 | dev_err(dev, "unsupported ACKMD\n"); | |
659 | else | |
660 | data |= (0x7 << 8); | |
661 | break; | |
662 | } | |
663 | ||
664 | fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data); | |
665 | udelay(10); | |
666 | ret = 0; | |
667 | } | |
668 | ||
669 | return ret; | |
4f56cde1 KM |
670 | } |
671 | ||
1ddddd36 KM |
672 | #define fsi_port_start(f, i) __fsi_port_clk_ctrl(f, i, 1) |
673 | #define fsi_port_stop(f, i) __fsi_port_clk_ctrl(f, i, 0) | |
674 | static void __fsi_port_clk_ctrl(struct fsi_priv *fsi, int is_play, int enable) | |
a4d7d550 | 675 | { |
71f6e064 | 676 | struct fsi_master *master = fsi_get_master(fsi); |
1f5e2a31 | 677 | u32 clk = fsi_is_port_a(fsi) ? CRA : CRB; |
a4d7d550 | 678 | |
1ddddd36 KM |
679 | if (enable) |
680 | fsi_irq_enable(fsi, is_play); | |
681 | else | |
682 | fsi_irq_disable(fsi, is_play); | |
683 | ||
cda828ca | 684 | if (fsi_is_clk_master(fsi)) |
1f5e2a31 | 685 | fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0); |
a4d7d550 KM |
686 | } |
687 | ||
1f5e2a31 KM |
688 | /* |
689 | * ctrl function | |
690 | */ | |
4a942b45 KM |
691 | static void fsi_fifo_init(struct fsi_priv *fsi, |
692 | int is_play, | |
23ca8533 | 693 | struct device *dev) |
a4d7d550 | 694 | { |
4a942b45 | 695 | struct fsi_master *master = fsi_get_master(fsi); |
93193c2b | 696 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); |
e8c8b631 | 697 | u32 shift, i; |
2e651baf | 698 | int frame_capa; |
a4d7d550 | 699 | |
4a942b45 KM |
700 | /* get on-chip RAM capacity */ |
701 | shift = fsi_master_read(master, FIFO_SZ); | |
cf6edd00 KM |
702 | shift >>= fsi_get_port_shift(fsi, is_play); |
703 | shift &= FIFO_SZ_MASK; | |
2e651baf | 704 | frame_capa = 256 << shift; |
23ca8533 | 705 | dev_dbg(dev, "fifo = %d words\n", frame_capa); |
a4d7d550 | 706 | |
4a942b45 KM |
707 | /* |
708 | * The maximum number of sample data varies depending | |
709 | * on the number of channels selected for the format. | |
710 | * | |
711 | * FIFOs are used in 4-channel units in 3-channel mode | |
712 | * and in 8-channel units in 5- to 7-channel mode | |
713 | * meaning that more FIFOs than the required size of DPRAM | |
714 | * are used. | |
715 | * | |
716 | * ex) if 256 words of DP-RAM is connected | |
717 | * 1 channel: 256 (256 x 1 = 256) | |
718 | * 2 channels: 128 (128 x 2 = 256) | |
719 | * 3 channels: 64 ( 64 x 3 = 192) | |
720 | * 4 channels: 64 ( 64 x 4 = 256) | |
721 | * 5 channels: 32 ( 32 x 5 = 160) | |
722 | * 6 channels: 32 ( 32 x 6 = 192) | |
723 | * 7 channels: 32 ( 32 x 7 = 224) | |
724 | * 8 channels: 32 ( 32 x 8 = 256) | |
725 | */ | |
160afa7f | 726 | for (i = 1; i < fsi->chan_num; i <<= 1) |
2e651baf | 727 | frame_capa >>= 1; |
23ca8533 | 728 | dev_dbg(dev, "%d channel %d store\n", |
2e651baf KM |
729 | fsi->chan_num, frame_capa); |
730 | ||
731 | io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa); | |
a4d7d550 | 732 | |
e8c8b631 KM |
733 | /* |
734 | * set interrupt generation factor | |
735 | * clear FIFO | |
736 | */ | |
737 | if (is_play) { | |
738 | fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF); | |
739 | fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR); | |
740 | } else { | |
741 | fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF); | |
742 | fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR); | |
743 | } | |
a4d7d550 KM |
744 | } |
745 | ||
1ec9bc35 | 746 | static int fsi_fifo_data_ctrl(struct fsi_priv *fsi, int stream) |
a4d7d550 KM |
747 | { |
748 | struct snd_pcm_runtime *runtime; | |
749 | struct snd_pcm_substream *substream = NULL; | |
93193c2b KM |
750 | int is_play = fsi_stream_is_play(stream); |
751 | struct fsi_stream *io = fsi_get_stream(fsi, is_play); | |
2e651baf KM |
752 | int sample_residues; |
753 | int sample_width; | |
754 | int samples; | |
755 | int samples_max; | |
b9fde18c | 756 | int over_period; |
d8b33534 | 757 | void (*fn)(struct fsi_priv *fsi, int size); |
a4d7d550 KM |
758 | |
759 | if (!fsi || | |
93193c2b KM |
760 | !io->substream || |
761 | !io->substream->runtime) | |
a4d7d550 KM |
762 | return -EINVAL; |
763 | ||
1c418d1f | 764 | over_period = 0; |
93193c2b | 765 | substream = io->substream; |
1c418d1f | 766 | runtime = substream->runtime; |
a4d7d550 KM |
767 | |
768 | /* FSI FIFO has limit. | |
769 | * So, this driver can not send periods data at a time | |
770 | */ | |
2e651baf KM |
771 | if (io->buff_sample_pos >= |
772 | io->period_samples * (io->period_pos + 1)) { | |
a4d7d550 | 773 | |
1c418d1f | 774 | over_period = 1; |
2e651baf | 775 | io->period_pos = (io->period_pos + 1) % runtime->periods; |
a4d7d550 | 776 | |
2e651baf KM |
777 | if (0 == io->period_pos) |
778 | io->buff_sample_pos = 0; | |
a4d7d550 KM |
779 | } |
780 | ||
2e651baf KM |
781 | /* get 1 sample data width */ |
782 | sample_width = samples_to_bytes(runtime, 1); | |
a4d7d550 | 783 | |
2e651baf KM |
784 | /* get number of residue samples */ |
785 | sample_residues = io->buff_sample_capa - io->buff_sample_pos; | |
d8b33534 KM |
786 | |
787 | if (is_play) { | |
788 | /* | |
789 | * for play-back | |
790 | * | |
2e651baf KM |
791 | * samples_max : number of FSI fifo free samples space |
792 | * samples : number of ALSA residue samples | |
d8b33534 | 793 | */ |
2e651baf KM |
794 | samples_max = io->fifo_sample_capa; |
795 | samples_max -= fsi_get_current_fifo_samples(fsi, is_play); | |
d8b33534 | 796 | |
2e651baf | 797 | samples = sample_residues; |
d8b33534 | 798 | |
2e651baf | 799 | switch (sample_width) { |
d8b33534 KM |
800 | case 2: |
801 | fn = fsi_dma_soft_push16; | |
802 | break; | |
803 | case 4: | |
804 | fn = fsi_dma_soft_push32; | |
805 | break; | |
806 | default: | |
807 | return -EINVAL; | |
808 | } | |
809 | } else { | |
810 | /* | |
811 | * for capture | |
812 | * | |
2e651baf KM |
813 | * samples_max : number of ALSA free samples space |
814 | * samples : number of samples in FSI fifo | |
d8b33534 | 815 | */ |
2e651baf KM |
816 | samples_max = sample_residues; |
817 | samples = fsi_get_current_fifo_samples(fsi, is_play); | |
d8b33534 | 818 | |
2e651baf | 819 | switch (sample_width) { |
d8b33534 KM |
820 | case 2: |
821 | fn = fsi_dma_soft_pop16; | |
822 | break; | |
823 | case 4: | |
824 | fn = fsi_dma_soft_pop32; | |
825 | break; | |
826 | default: | |
827 | return -EINVAL; | |
828 | } | |
829 | } | |
a4d7d550 | 830 | |
2e651baf | 831 | samples = min(samples, samples_max); |
a4d7d550 | 832 | |
2e651baf | 833 | fn(fsi, samples); |
a4d7d550 | 834 | |
2e651baf KM |
835 | /* update buff_sample_pos */ |
836 | io->buff_sample_pos += samples; | |
a4d7d550 | 837 | |
1c418d1f | 838 | if (over_period) |
a4d7d550 KM |
839 | snd_pcm_period_elapsed(substream); |
840 | ||
47fc9a0a | 841 | return 0; |
a4d7d550 KM |
842 | } |
843 | ||
1ec9bc35 | 844 | static int fsi_data_pop(struct fsi_priv *fsi) |
07102f3c | 845 | { |
1ec9bc35 | 846 | return fsi_fifo_data_ctrl(fsi, SNDRV_PCM_STREAM_CAPTURE); |
d8b33534 | 847 | } |
07102f3c | 848 | |
1ec9bc35 | 849 | static int fsi_data_push(struct fsi_priv *fsi) |
d8b33534 | 850 | { |
1ec9bc35 | 851 | return fsi_fifo_data_ctrl(fsi, SNDRV_PCM_STREAM_PLAYBACK); |
07102f3c KM |
852 | } |
853 | ||
a4d7d550 KM |
854 | static irqreturn_t fsi_interrupt(int irq, void *data) |
855 | { | |
71f6e064 | 856 | struct fsi_master *master = data; |
10ea76cc | 857 | u32 int_st = fsi_irq_get_status(master); |
a4d7d550 KM |
858 | |
859 | /* clear irq status */ | |
feb58cff KM |
860 | fsi_master_mask_set(master, SOFT_RST, IR, 0); |
861 | fsi_master_mask_set(master, SOFT_RST, IR, IR); | |
a4d7d550 | 862 | |
cf6edd00 | 863 | if (int_st & AB_IO(1, AO_SHIFT)) |
1ec9bc35 | 864 | fsi_data_push(&master->fsia); |
cf6edd00 | 865 | if (int_st & AB_IO(1, BO_SHIFT)) |
1ec9bc35 | 866 | fsi_data_push(&master->fsib); |
cf6edd00 | 867 | if (int_st & AB_IO(1, AI_SHIFT)) |
1ec9bc35 | 868 | fsi_data_pop(&master->fsia); |
cf6edd00 | 869 | if (int_st & AB_IO(1, BI_SHIFT)) |
1ec9bc35 KM |
870 | fsi_data_pop(&master->fsib); |
871 | ||
872 | fsi_count_fifo_err(&master->fsia); | |
873 | fsi_count_fifo_err(&master->fsib); | |
a4d7d550 | 874 | |
48d78e58 KM |
875 | fsi_irq_clear_status(&master->fsia); |
876 | fsi_irq_clear_status(&master->fsib); | |
a4d7d550 KM |
877 | |
878 | return IRQ_HANDLED; | |
879 | } | |
880 | ||
c8fe2574 KM |
881 | /* |
882 | * dai ops | |
883 | */ | |
a4d7d550 | 884 | |
23ca8533 KM |
885 | static int fsi_hw_startup(struct fsi_priv *fsi, |
886 | int is_play, | |
887 | struct device *dev) | |
a4d7d550 | 888 | { |
93193c2b | 889 | u32 flags = fsi_get_info_flags(fsi); |
9478e0b6 | 890 | u32 data = 0; |
a4d7d550 | 891 | |
23ca8533 | 892 | pm_runtime_get_sync(dev); |
a4d7d550 | 893 | |
9478e0b6 KM |
894 | /* clock setting */ |
895 | if (fsi_is_clk_master(fsi)) | |
896 | data = DIMD | DOMD; | |
897 | ||
898 | fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data); | |
a4d7d550 KM |
899 | |
900 | /* clock inversion (CKG2) */ | |
901 | data = 0; | |
b427b44c KM |
902 | if (SH_FSI_LRM_INV & flags) |
903 | data |= 1 << 12; | |
904 | if (SH_FSI_BRM_INV & flags) | |
905 | data |= 1 << 8; | |
906 | if (SH_FSI_LRS_INV & flags) | |
907 | data |= 1 << 4; | |
908 | if (SH_FSI_BRS_INV & flags) | |
909 | data |= 1 << 0; | |
910 | ||
a4d7d550 KM |
911 | fsi_reg_write(fsi, CKG2, data); |
912 | ||
9478e0b6 KM |
913 | /* set format */ |
914 | fsi_reg_write(fsi, DO_FMT, fsi->do_fmt); | |
915 | fsi_reg_write(fsi, DI_FMT, fsi->di_fmt); | |
916 | ||
917 | /* spdif ? */ | |
918 | if (fsi_is_spdif(fsi)) { | |
919 | fsi_spdif_clk_ctrl(fsi, 1); | |
920 | fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD); | |
921 | } | |
922 | ||
10ea76cc KM |
923 | /* irq clear */ |
924 | fsi_irq_disable(fsi, is_play); | |
925 | fsi_irq_clear_status(fsi); | |
926 | ||
927 | /* fifo init */ | |
23ca8533 | 928 | fsi_fifo_init(fsi, is_play, dev); |
a4d7d550 | 929 | |
a68a3b4e | 930 | return 0; |
a4d7d550 KM |
931 | } |
932 | ||
23ca8533 KM |
933 | static void fsi_hw_shutdown(struct fsi_priv *fsi, |
934 | int is_play, | |
935 | struct device *dev) | |
936 | { | |
937 | if (fsi_is_clk_master(fsi)) | |
938 | fsi_set_master_clk(dev, fsi, fsi->rate, 0); | |
939 | ||
940 | pm_runtime_put_sync(dev); | |
941 | } | |
942 | ||
943 | static int fsi_dai_startup(struct snd_pcm_substream *substream, | |
944 | struct snd_soc_dai *dai) | |
945 | { | |
946 | struct fsi_priv *fsi = fsi_get_priv(substream); | |
947 | int is_play = fsi_is_play(substream); | |
948 | ||
949 | return fsi_hw_startup(fsi, is_play, dai->dev); | |
950 | } | |
951 | ||
a4d7d550 KM |
952 | static void fsi_dai_shutdown(struct snd_pcm_substream *substream, |
953 | struct snd_soc_dai *dai) | |
954 | { | |
71f6e064 | 955 | struct fsi_priv *fsi = fsi_get_priv(substream); |
23ca8533 | 956 | int is_play = fsi_is_play(substream); |
a4d7d550 | 957 | |
23ca8533 | 958 | fsi_hw_shutdown(fsi, is_play, dai->dev); |
d4bc99b9 | 959 | fsi->rate = 0; |
a4d7d550 KM |
960 | } |
961 | ||
962 | static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd, | |
963 | struct snd_soc_dai *dai) | |
964 | { | |
71f6e064 | 965 | struct fsi_priv *fsi = fsi_get_priv(substream); |
00545785 | 966 | int is_play = fsi_is_play(substream); |
a4d7d550 KM |
967 | int ret = 0; |
968 | ||
a4d7d550 KM |
969 | switch (cmd) { |
970 | case SNDRV_PCM_TRIGGER_START: | |
0ffe296a | 971 | fsi_stream_push(fsi, is_play, substream); |
1ec9bc35 | 972 | ret = is_play ? fsi_data_push(fsi) : fsi_data_pop(fsi); |
1ddddd36 | 973 | fsi_port_start(fsi, is_play); |
a4d7d550 KM |
974 | break; |
975 | case SNDRV_PCM_TRIGGER_STOP: | |
1ddddd36 | 976 | fsi_port_stop(fsi, is_play); |
93193c2b | 977 | fsi_stream_pop(fsi, is_play); |
a4d7d550 KM |
978 | break; |
979 | } | |
980 | ||
981 | return ret; | |
982 | } | |
983 | ||
f17c13ca KM |
984 | static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt) |
985 | { | |
986 | u32 data = 0; | |
987 | ||
988 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
989 | case SND_SOC_DAIFMT_I2S: | |
990 | data = CR_I2S; | |
991 | fsi->chan_num = 2; | |
992 | break; | |
993 | case SND_SOC_DAIFMT_LEFT_J: | |
994 | data = CR_PCM; | |
995 | fsi->chan_num = 2; | |
996 | break; | |
997 | default: | |
998 | return -EINVAL; | |
999 | } | |
1000 | ||
9478e0b6 KM |
1001 | fsi->do_fmt = data; |
1002 | fsi->di_fmt = data; | |
f17c13ca KM |
1003 | |
1004 | return 0; | |
1005 | } | |
1006 | ||
1007 | static int fsi_set_fmt_spdif(struct fsi_priv *fsi) | |
1008 | { | |
1009 | struct fsi_master *master = fsi_get_master(fsi); | |
1010 | u32 data = 0; | |
1011 | ||
1012 | if (master->core->ver < 2) | |
1013 | return -EINVAL; | |
1014 | ||
1015 | data = CR_BWS_16 | CR_DTMD_SPDIF_PCM | CR_PCM; | |
1016 | fsi->chan_num = 2; | |
9478e0b6 | 1017 | fsi->spdif = 1; |
f17c13ca | 1018 | |
9478e0b6 KM |
1019 | fsi->do_fmt = data; |
1020 | fsi->di_fmt = data; | |
f17c13ca KM |
1021 | |
1022 | return 0; | |
1023 | } | |
1024 | ||
4d805f7b KM |
1025 | static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) |
1026 | { | |
1027 | struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai); | |
6a9ebad8 KM |
1028 | struct fsi_master *master = fsi_get_master(fsi); |
1029 | set_rate_func set_rate = fsi_get_info_set_rate(master); | |
f17c13ca | 1030 | u32 flags = fsi_get_info_flags(fsi); |
4d805f7b KM |
1031 | int ret; |
1032 | ||
4d805f7b KM |
1033 | /* set master/slave audio interface */ |
1034 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1035 | case SND_SOC_DAIFMT_CBM_CFM: | |
6a9ebad8 | 1036 | fsi->clk_master = 1; |
4d805f7b KM |
1037 | break; |
1038 | case SND_SOC_DAIFMT_CBS_CFS: | |
1039 | break; | |
1040 | default: | |
9478e0b6 | 1041 | return -EINVAL; |
4d805f7b | 1042 | } |
6a9ebad8 KM |
1043 | |
1044 | if (fsi_is_clk_master(fsi) && !set_rate) { | |
1045 | dev_err(dai->dev, "platform doesn't have set_rate\n"); | |
9478e0b6 | 1046 | return -EINVAL; |
6a9ebad8 KM |
1047 | } |
1048 | ||
f17c13ca KM |
1049 | /* set format */ |
1050 | switch (flags & SH_FSI_FMT_MASK) { | |
1051 | case SH_FSI_FMT_DAI: | |
1052 | ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK); | |
1053 | break; | |
1054 | case SH_FSI_FMT_SPDIF: | |
1055 | ret = fsi_set_fmt_spdif(fsi); | |
1056 | break; | |
1057 | default: | |
1058 | ret = -EINVAL; | |
1059 | } | |
4d805f7b | 1060 | |
4d805f7b KM |
1061 | return ret; |
1062 | } | |
1063 | ||
ccad7b44 KM |
1064 | static int fsi_dai_hw_params(struct snd_pcm_substream *substream, |
1065 | struct snd_pcm_hw_params *params, | |
1066 | struct snd_soc_dai *dai) | |
1067 | { | |
1068 | struct fsi_priv *fsi = fsi_get_priv(substream); | |
d4bc99b9 | 1069 | long rate = params_rate(params); |
ccad7b44 KM |
1070 | int ret; |
1071 | ||
6a9ebad8 | 1072 | if (!fsi_is_clk_master(fsi)) |
ccad7b44 KM |
1073 | return 0; |
1074 | ||
4f56cde1 KM |
1075 | ret = fsi_set_master_clk(dai->dev, fsi, rate, 1); |
1076 | if (ret < 0) | |
d4bc99b9 | 1077 | return ret; |
ccad7b44 | 1078 | |
d4bc99b9 | 1079 | fsi->rate = rate; |
ccad7b44 KM |
1080 | |
1081 | return ret; | |
ccad7b44 KM |
1082 | } |
1083 | ||
a4d7d550 KM |
1084 | static struct snd_soc_dai_ops fsi_dai_ops = { |
1085 | .startup = fsi_dai_startup, | |
1086 | .shutdown = fsi_dai_shutdown, | |
1087 | .trigger = fsi_dai_trigger, | |
4d805f7b | 1088 | .set_fmt = fsi_dai_set_fmt, |
ccad7b44 | 1089 | .hw_params = fsi_dai_hw_params, |
a4d7d550 KM |
1090 | }; |
1091 | ||
c8fe2574 KM |
1092 | /* |
1093 | * pcm ops | |
1094 | */ | |
a4d7d550 | 1095 | |
a4d7d550 KM |
1096 | static struct snd_pcm_hardware fsi_pcm_hardware = { |
1097 | .info = SNDRV_PCM_INFO_INTERLEAVED | | |
1098 | SNDRV_PCM_INFO_MMAP | | |
1099 | SNDRV_PCM_INFO_MMAP_VALID | | |
1100 | SNDRV_PCM_INFO_PAUSE, | |
1101 | .formats = FSI_FMTS, | |
1102 | .rates = FSI_RATES, | |
1103 | .rate_min = 8000, | |
1104 | .rate_max = 192000, | |
1105 | .channels_min = 1, | |
1106 | .channels_max = 2, | |
1107 | .buffer_bytes_max = 64 * 1024, | |
1108 | .period_bytes_min = 32, | |
1109 | .period_bytes_max = 8192, | |
1110 | .periods_min = 1, | |
1111 | .periods_max = 32, | |
1112 | .fifo_size = 256, | |
1113 | }; | |
1114 | ||
1115 | static int fsi_pcm_open(struct snd_pcm_substream *substream) | |
1116 | { | |
1117 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1118 | int ret = 0; | |
1119 | ||
1120 | snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware); | |
1121 | ||
1122 | ret = snd_pcm_hw_constraint_integer(runtime, | |
1123 | SNDRV_PCM_HW_PARAM_PERIODS); | |
1124 | ||
1125 | return ret; | |
1126 | } | |
1127 | ||
1128 | static int fsi_hw_params(struct snd_pcm_substream *substream, | |
1129 | struct snd_pcm_hw_params *hw_params) | |
1130 | { | |
1131 | return snd_pcm_lib_malloc_pages(substream, | |
1132 | params_buffer_bytes(hw_params)); | |
1133 | } | |
1134 | ||
1135 | static int fsi_hw_free(struct snd_pcm_substream *substream) | |
1136 | { | |
1137 | return snd_pcm_lib_free_pages(substream); | |
1138 | } | |
1139 | ||
1140 | static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream) | |
1141 | { | |
71f6e064 | 1142 | struct fsi_priv *fsi = fsi_get_priv(substream); |
93193c2b | 1143 | struct fsi_stream *io = fsi_get_stream(fsi, fsi_is_play(substream)); |
2e651baf | 1144 | int samples_pos = io->buff_sample_pos - 1; |
a4d7d550 | 1145 | |
2e651baf KM |
1146 | if (samples_pos < 0) |
1147 | samples_pos = 0; | |
a4d7d550 | 1148 | |
2e651baf | 1149 | return fsi_sample2frame(fsi, samples_pos); |
a4d7d550 KM |
1150 | } |
1151 | ||
1152 | static struct snd_pcm_ops fsi_pcm_ops = { | |
1153 | .open = fsi_pcm_open, | |
1154 | .ioctl = snd_pcm_lib_ioctl, | |
1155 | .hw_params = fsi_hw_params, | |
1156 | .hw_free = fsi_hw_free, | |
1157 | .pointer = fsi_pointer, | |
1158 | }; | |
1159 | ||
c8fe2574 KM |
1160 | /* |
1161 | * snd_soc_platform | |
1162 | */ | |
a4d7d550 | 1163 | |
a4d7d550 KM |
1164 | #define PREALLOC_BUFFER (32 * 1024) |
1165 | #define PREALLOC_BUFFER_MAX (32 * 1024) | |
1166 | ||
1167 | static void fsi_pcm_free(struct snd_pcm *pcm) | |
1168 | { | |
1169 | snd_pcm_lib_preallocate_free_for_all(pcm); | |
1170 | } | |
1171 | ||
552d1ef6 | 1172 | static int fsi_pcm_new(struct snd_soc_pcm_runtime *rtd) |
a4d7d550 | 1173 | { |
552d1ef6 LG |
1174 | struct snd_pcm *pcm = rtd->pcm; |
1175 | ||
a4d7d550 KM |
1176 | /* |
1177 | * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel | |
1178 | * in MMAP mode (i.e. aplay -M) | |
1179 | */ | |
1180 | return snd_pcm_lib_preallocate_pages_for_all( | |
1181 | pcm, | |
1182 | SNDRV_DMA_TYPE_CONTINUOUS, | |
1183 | snd_dma_continuous_data(GFP_KERNEL), | |
1184 | PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); | |
1185 | } | |
1186 | ||
c8fe2574 KM |
1187 | /* |
1188 | * alsa struct | |
1189 | */ | |
a4d7d550 | 1190 | |
f0fba2ad | 1191 | static struct snd_soc_dai_driver fsi_soc_dai[] = { |
a4d7d550 | 1192 | { |
f0fba2ad | 1193 | .name = "fsia-dai", |
a4d7d550 KM |
1194 | .playback = { |
1195 | .rates = FSI_RATES, | |
1196 | .formats = FSI_FMTS, | |
1197 | .channels_min = 1, | |
1198 | .channels_max = 8, | |
1199 | }, | |
07102f3c KM |
1200 | .capture = { |
1201 | .rates = FSI_RATES, | |
1202 | .formats = FSI_FMTS, | |
1203 | .channels_min = 1, | |
1204 | .channels_max = 8, | |
1205 | }, | |
a4d7d550 KM |
1206 | .ops = &fsi_dai_ops, |
1207 | }, | |
1208 | { | |
f0fba2ad | 1209 | .name = "fsib-dai", |
a4d7d550 KM |
1210 | .playback = { |
1211 | .rates = FSI_RATES, | |
1212 | .formats = FSI_FMTS, | |
1213 | .channels_min = 1, | |
1214 | .channels_max = 8, | |
1215 | }, | |
07102f3c KM |
1216 | .capture = { |
1217 | .rates = FSI_RATES, | |
1218 | .formats = FSI_FMTS, | |
1219 | .channels_min = 1, | |
1220 | .channels_max = 8, | |
1221 | }, | |
a4d7d550 KM |
1222 | .ops = &fsi_dai_ops, |
1223 | }, | |
1224 | }; | |
a4d7d550 | 1225 | |
f0fba2ad LG |
1226 | static struct snd_soc_platform_driver fsi_soc_platform = { |
1227 | .ops = &fsi_pcm_ops, | |
a4d7d550 KM |
1228 | .pcm_new = fsi_pcm_new, |
1229 | .pcm_free = fsi_pcm_free, | |
1230 | }; | |
a4d7d550 | 1231 | |
c8fe2574 KM |
1232 | /* |
1233 | * platform function | |
1234 | */ | |
a4d7d550 | 1235 | |
a4d7d550 KM |
1236 | static int fsi_probe(struct platform_device *pdev) |
1237 | { | |
71f6e064 | 1238 | struct fsi_master *master; |
cc780d38 | 1239 | const struct platform_device_id *id_entry; |
a4d7d550 | 1240 | struct resource *res; |
a4d7d550 KM |
1241 | unsigned int irq; |
1242 | int ret; | |
1243 | ||
cc780d38 KM |
1244 | id_entry = pdev->id_entry; |
1245 | if (!id_entry) { | |
1246 | dev_err(&pdev->dev, "unknown fsi device\n"); | |
1247 | return -ENODEV; | |
1248 | } | |
1249 | ||
a4d7d550 KM |
1250 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1251 | irq = platform_get_irq(pdev, 0); | |
b6aa1793 | 1252 | if (!res || (int)irq <= 0) { |
a4d7d550 KM |
1253 | dev_err(&pdev->dev, "Not enough FSI platform resources.\n"); |
1254 | ret = -ENODEV; | |
1255 | goto exit; | |
1256 | } | |
1257 | ||
1258 | master = kzalloc(sizeof(*master), GFP_KERNEL); | |
1259 | if (!master) { | |
1260 | dev_err(&pdev->dev, "Could not allocate master\n"); | |
1261 | ret = -ENOMEM; | |
1262 | goto exit; | |
1263 | } | |
1264 | ||
1265 | master->base = ioremap_nocache(res->start, resource_size(res)); | |
1266 | if (!master->base) { | |
1267 | ret = -ENXIO; | |
1268 | dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n"); | |
1269 | goto exit_kfree; | |
1270 | } | |
1271 | ||
3bc28070 | 1272 | /* master setting */ |
a4d7d550 KM |
1273 | master->irq = irq; |
1274 | master->info = pdev->dev.platform_data; | |
3bc28070 KM |
1275 | master->core = (struct fsi_core *)id_entry->driver_data; |
1276 | spin_lock_init(&master->lock); | |
1277 | ||
1278 | /* FSI A setting */ | |
a4d7d550 | 1279 | master->fsia.base = master->base; |
71f6e064 | 1280 | master->fsia.master = master; |
3bc28070 KM |
1281 | |
1282 | /* FSI B setting */ | |
a4d7d550 | 1283 | master->fsib.base = master->base + 0x40; |
71f6e064 | 1284 | master->fsib.master = master; |
a4d7d550 | 1285 | |
785d1c45 | 1286 | pm_runtime_enable(&pdev->dev); |
f0fba2ad | 1287 | dev_set_drvdata(&pdev->dev, master); |
a4d7d550 | 1288 | |
88e24c3a | 1289 | ret = request_irq(irq, &fsi_interrupt, 0, |
cc780d38 | 1290 | id_entry->name, master); |
a4d7d550 KM |
1291 | if (ret) { |
1292 | dev_err(&pdev->dev, "irq request err\n"); | |
9ddc9aa9 | 1293 | goto exit_iounmap; |
a4d7d550 KM |
1294 | } |
1295 | ||
f0fba2ad | 1296 | ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform); |
a4d7d550 KM |
1297 | if (ret < 0) { |
1298 | dev_err(&pdev->dev, "cannot snd soc register\n"); | |
1299 | goto exit_free_irq; | |
1300 | } | |
1301 | ||
0b5ec87d KM |
1302 | ret = snd_soc_register_dais(&pdev->dev, fsi_soc_dai, |
1303 | ARRAY_SIZE(fsi_soc_dai)); | |
1304 | if (ret < 0) { | |
1305 | dev_err(&pdev->dev, "cannot snd dai register\n"); | |
1306 | goto exit_snd_soc; | |
1307 | } | |
a4d7d550 | 1308 | |
0b5ec87d KM |
1309 | return ret; |
1310 | ||
1311 | exit_snd_soc: | |
1312 | snd_soc_unregister_platform(&pdev->dev); | |
a4d7d550 KM |
1313 | exit_free_irq: |
1314 | free_irq(irq, master); | |
a4d7d550 KM |
1315 | exit_iounmap: |
1316 | iounmap(master->base); | |
785d1c45 | 1317 | pm_runtime_disable(&pdev->dev); |
a4d7d550 KM |
1318 | exit_kfree: |
1319 | kfree(master); | |
1320 | master = NULL; | |
1321 | exit: | |
1322 | return ret; | |
1323 | } | |
1324 | ||
1325 | static int fsi_remove(struct platform_device *pdev) | |
1326 | { | |
71f6e064 KM |
1327 | struct fsi_master *master; |
1328 | ||
f0fba2ad | 1329 | master = dev_get_drvdata(&pdev->dev); |
71f6e064 | 1330 | |
d985f27e | 1331 | free_irq(master->irq, master); |
785d1c45 | 1332 | pm_runtime_disable(&pdev->dev); |
a4d7d550 | 1333 | |
d985f27e KM |
1334 | snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(fsi_soc_dai)); |
1335 | snd_soc_unregister_platform(&pdev->dev); | |
a4d7d550 KM |
1336 | |
1337 | iounmap(master->base); | |
1338 | kfree(master); | |
71f6e064 | 1339 | |
a4d7d550 KM |
1340 | return 0; |
1341 | } | |
1342 | ||
106c79ec | 1343 | static void __fsi_suspend(struct fsi_priv *fsi, |
cda828ca | 1344 | int is_play, |
4f56cde1 | 1345 | struct device *dev) |
106c79ec | 1346 | { |
cda828ca KM |
1347 | if (!fsi_stream_is_working(fsi, is_play)) |
1348 | return; | |
106c79ec | 1349 | |
cda828ca KM |
1350 | fsi_port_stop(fsi, is_play); |
1351 | fsi_hw_shutdown(fsi, is_play, dev); | |
106c79ec KM |
1352 | } |
1353 | ||
1354 | static void __fsi_resume(struct fsi_priv *fsi, | |
cda828ca | 1355 | int is_play, |
4f56cde1 | 1356 | struct device *dev) |
106c79ec | 1357 | { |
cda828ca KM |
1358 | if (!fsi_stream_is_working(fsi, is_play)) |
1359 | return; | |
106c79ec | 1360 | |
cda828ca KM |
1361 | fsi_hw_startup(fsi, is_play, dev); |
1362 | ||
1363 | if (fsi_is_clk_master(fsi) && fsi->rate) | |
4f56cde1 | 1364 | fsi_set_master_clk(dev, fsi, fsi->rate, 1); |
cda828ca KM |
1365 | |
1366 | fsi_port_start(fsi, is_play); | |
1367 | ||
106c79ec KM |
1368 | } |
1369 | ||
1370 | static int fsi_suspend(struct device *dev) | |
1371 | { | |
1372 | struct fsi_master *master = dev_get_drvdata(dev); | |
cda828ca KM |
1373 | struct fsi_priv *fsia = &master->fsia; |
1374 | struct fsi_priv *fsib = &master->fsib; | |
106c79ec | 1375 | |
cda828ca KM |
1376 | __fsi_suspend(fsia, 1, dev); |
1377 | __fsi_suspend(fsia, 0, dev); | |
106c79ec | 1378 | |
cda828ca KM |
1379 | __fsi_suspend(fsib, 1, dev); |
1380 | __fsi_suspend(fsib, 0, dev); | |
106c79ec KM |
1381 | |
1382 | return 0; | |
1383 | } | |
1384 | ||
1385 | static int fsi_resume(struct device *dev) | |
1386 | { | |
1387 | struct fsi_master *master = dev_get_drvdata(dev); | |
cda828ca KM |
1388 | struct fsi_priv *fsia = &master->fsia; |
1389 | struct fsi_priv *fsib = &master->fsib; | |
106c79ec | 1390 | |
cda828ca KM |
1391 | __fsi_resume(fsia, 1, dev); |
1392 | __fsi_resume(fsia, 0, dev); | |
106c79ec | 1393 | |
cda828ca KM |
1394 | __fsi_resume(fsib, 1, dev); |
1395 | __fsi_resume(fsib, 0, dev); | |
106c79ec KM |
1396 | |
1397 | return 0; | |
1398 | } | |
1399 | ||
785d1c45 KM |
1400 | static int fsi_runtime_nop(struct device *dev) |
1401 | { | |
1402 | /* Runtime PM callback shared between ->runtime_suspend() | |
1403 | * and ->runtime_resume(). Simply returns success. | |
1404 | * | |
1405 | * This driver re-initializes all registers after | |
1406 | * pm_runtime_get_sync() anyway so there is no need | |
1407 | * to save and restore registers here. | |
1408 | */ | |
1409 | return 0; | |
1410 | } | |
1411 | ||
1412 | static struct dev_pm_ops fsi_pm_ops = { | |
106c79ec KM |
1413 | .suspend = fsi_suspend, |
1414 | .resume = fsi_resume, | |
785d1c45 KM |
1415 | .runtime_suspend = fsi_runtime_nop, |
1416 | .runtime_resume = fsi_runtime_nop, | |
1417 | }; | |
1418 | ||
73b92c1f KM |
1419 | static struct fsi_core fsi1_core = { |
1420 | .ver = 1, | |
1421 | ||
1422 | /* Interrupt */ | |
cc780d38 KM |
1423 | .int_st = INT_ST, |
1424 | .iemsk = IEMSK, | |
1425 | .imsk = IMSK, | |
1426 | }; | |
1427 | ||
73b92c1f KM |
1428 | static struct fsi_core fsi2_core = { |
1429 | .ver = 2, | |
1430 | ||
1431 | /* Interrupt */ | |
cc780d38 KM |
1432 | .int_st = CPU_INT_ST, |
1433 | .iemsk = CPU_IEMSK, | |
1434 | .imsk = CPU_IMSK, | |
2b0e7302 KM |
1435 | .a_mclk = A_MST_CTLR, |
1436 | .b_mclk = B_MST_CTLR, | |
cc780d38 KM |
1437 | }; |
1438 | ||
1439 | static struct platform_device_id fsi_id_table[] = { | |
73b92c1f KM |
1440 | { "sh_fsi", (kernel_ulong_t)&fsi1_core }, |
1441 | { "sh_fsi2", (kernel_ulong_t)&fsi2_core }, | |
05c69450 | 1442 | {}, |
cc780d38 | 1443 | }; |
d85a6d7b | 1444 | MODULE_DEVICE_TABLE(platform, fsi_id_table); |
cc780d38 | 1445 | |
a4d7d550 KM |
1446 | static struct platform_driver fsi_driver = { |
1447 | .driver = { | |
f0fba2ad | 1448 | .name = "fsi-pcm-audio", |
785d1c45 | 1449 | .pm = &fsi_pm_ops, |
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1450 | }, |
1451 | .probe = fsi_probe, | |
1452 | .remove = fsi_remove, | |
cc780d38 | 1453 | .id_table = fsi_id_table, |
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1454 | }; |
1455 | ||
1456 | static int __init fsi_mobile_init(void) | |
1457 | { | |
1458 | return platform_driver_register(&fsi_driver); | |
1459 | } | |
1460 | ||
1461 | static void __exit fsi_mobile_exit(void) | |
1462 | { | |
1463 | platform_driver_unregister(&fsi_driver); | |
1464 | } | |
d85a6d7b | 1465 | |
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1466 | module_init(fsi_mobile_init); |
1467 | module_exit(fsi_mobile_exit); | |
1468 | ||
1469 | MODULE_LICENSE("GPL"); | |
1470 | MODULE_DESCRIPTION("SuperH onchip FSI audio driver"); | |
1471 | MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>"); | |
b3c27b51 | 1472 | MODULE_ALIAS("platform:fsi-pcm-audio"); |