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a4d7d550 KM |
1 | /* |
2 | * Fifo-attached Serial Interface (FSI) support for SH7724 | |
3 | * | |
4 | * Copyright (C) 2009 Renesas Solutions Corp. | |
5 | * Kuninori Morimoto <morimoto.kuninori@renesas.com> | |
6 | * | |
7 | * Based on ssi.c | |
8 | * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
a4d7d550 | 15 | #include <linux/delay.h> |
785d1c45 | 16 | #include <linux/pm_runtime.h> |
a4d7d550 | 17 | #include <linux/io.h> |
5a0e3ad6 | 18 | #include <linux/slab.h> |
a4d7d550 | 19 | #include <sound/soc.h> |
a4d7d550 | 20 | #include <sound/sh_fsi.h> |
a4d7d550 KM |
21 | |
22 | #define DO_FMT 0x0000 | |
23 | #define DOFF_CTL 0x0004 | |
24 | #define DOFF_ST 0x0008 | |
25 | #define DI_FMT 0x000C | |
26 | #define DIFF_CTL 0x0010 | |
27 | #define DIFF_ST 0x0014 | |
28 | #define CKG1 0x0018 | |
29 | #define CKG2 0x001C | |
30 | #define DIDT 0x0020 | |
31 | #define DODT 0x0024 | |
32 | #define MUTE_ST 0x0028 | |
3bc28070 KM |
33 | #define OUT_SEL 0x0030 |
34 | #define REG_END OUT_SEL | |
cc780d38 | 35 | |
3bc28070 KM |
36 | #define A_MST_CTLR 0x0180 |
37 | #define B_MST_CTLR 0x01A0 | |
cc780d38 KM |
38 | #define CPU_INT_ST 0x01F4 |
39 | #define CPU_IEMSK 0x01F8 | |
40 | #define CPU_IMSK 0x01FC | |
a4d7d550 KM |
41 | #define INT_ST 0x0200 |
42 | #define IEMSK 0x0204 | |
43 | #define IMSK 0x0208 | |
44 | #define MUTE 0x020C | |
45 | #define CLK_RST 0x0210 | |
46 | #define SOFT_RST 0x0214 | |
4a942b45 | 47 | #define FIFO_SZ 0x0218 |
3bc28070 | 48 | #define MREG_START A_MST_CTLR |
4a942b45 | 49 | #define MREG_END FIFO_SZ |
a4d7d550 KM |
50 | |
51 | /* DO_FMT */ | |
52 | /* DI_FMT */ | |
a7ffb52b KM |
53 | #define CR_MONO (0x0 << 4) |
54 | #define CR_MONO_D (0x1 << 4) | |
55 | #define CR_PCM (0x2 << 4) | |
56 | #define CR_I2S (0x3 << 4) | |
57 | #define CR_TDM (0x4 << 4) | |
58 | #define CR_TDM_D (0x5 << 4) | |
3bc28070 | 59 | #define CR_SPDIF 0x00100120 |
a4d7d550 KM |
60 | |
61 | /* DOFF_CTL */ | |
62 | /* DIFF_CTL */ | |
63 | #define IRQ_HALF 0x00100000 | |
64 | #define FIFO_CLR 0x00000001 | |
65 | ||
66 | /* DOFF_ST */ | |
67 | #define ERR_OVER 0x00000010 | |
68 | #define ERR_UNDER 0x00000001 | |
59c3b003 | 69 | #define ST_ERR (ERR_OVER | ERR_UNDER) |
a4d7d550 | 70 | |
ccad7b44 KM |
71 | /* CKG1 */ |
72 | #define ACKMD_MASK 0x00007000 | |
73 | #define BPFMD_MASK 0x00000700 | |
74 | ||
3bc28070 KM |
75 | /* A/B MST_CTLR */ |
76 | #define BP (1 << 4) /* Fix the signal of Biphase output */ | |
77 | #define SE (1 << 0) /* Fix the master clock */ | |
78 | ||
a4d7d550 KM |
79 | /* CLK_RST */ |
80 | #define B_CLK 0x00000010 | |
81 | #define A_CLK 0x00000001 | |
82 | ||
83 | /* INT_ST */ | |
84 | #define INT_B_IN (1 << 12) | |
85 | #define INT_B_OUT (1 << 8) | |
86 | #define INT_A_IN (1 << 4) | |
87 | #define INT_A_OUT (1 << 0) | |
88 | ||
feb58cff KM |
89 | /* SOFT_RST */ |
90 | #define PBSR (1 << 12) /* Port B Software Reset */ | |
91 | #define PASR (1 << 8) /* Port A Software Reset */ | |
92 | #define IR (1 << 4) /* Interrupt Reset */ | |
93 | #define FSISR (1 << 0) /* Software Reset */ | |
94 | ||
4a942b45 KM |
95 | /* FIFO_SZ */ |
96 | #define OUT_SZ_MASK 0x7 | |
97 | #define BO_SZ_SHIFT 8 | |
98 | #define AO_SZ_SHIFT 0 | |
99 | ||
a4d7d550 KM |
100 | #define FSI_RATES SNDRV_PCM_RATE_8000_96000 |
101 | ||
102 | #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE) | |
103 | ||
104 | /************************************************************************ | |
105 | ||
106 | ||
107 | struct | |
108 | ||
109 | ||
110 | ************************************************************************/ | |
111 | struct fsi_priv { | |
112 | void __iomem *base; | |
113 | struct snd_pcm_substream *substream; | |
71f6e064 | 114 | struct fsi_master *master; |
a4d7d550 KM |
115 | |
116 | int fifo_max; | |
117 | int chan; | |
a4d7d550 KM |
118 | |
119 | int byte_offset; | |
120 | int period_len; | |
121 | int buffer_len; | |
122 | int periods; | |
3bc28070 KM |
123 | |
124 | u32 mst_ctrl; | |
a4d7d550 KM |
125 | }; |
126 | ||
73b92c1f KM |
127 | struct fsi_core { |
128 | int ver; | |
129 | ||
cc780d38 KM |
130 | u32 int_st; |
131 | u32 iemsk; | |
132 | u32 imsk; | |
133 | }; | |
134 | ||
a4d7d550 KM |
135 | struct fsi_master { |
136 | void __iomem *base; | |
137 | int irq; | |
a4d7d550 KM |
138 | struct fsi_priv fsia; |
139 | struct fsi_priv fsib; | |
73b92c1f | 140 | struct fsi_core *core; |
a4d7d550 | 141 | struct sh_fsi_platform_info *info; |
8fc176d5 | 142 | spinlock_t lock; |
a4d7d550 KM |
143 | }; |
144 | ||
a4d7d550 KM |
145 | /************************************************************************ |
146 | ||
147 | ||
148 | basic read write function | |
149 | ||
150 | ||
151 | ************************************************************************/ | |
0f69d978 | 152 | static void __fsi_reg_write(u32 reg, u32 data) |
a4d7d550 KM |
153 | { |
154 | /* valid data area is 24bit */ | |
155 | data &= 0x00ffffff; | |
156 | ||
0f69d978 | 157 | __raw_writel(data, reg); |
a4d7d550 KM |
158 | } |
159 | ||
160 | static u32 __fsi_reg_read(u32 reg) | |
161 | { | |
0f69d978 | 162 | return __raw_readl(reg); |
a4d7d550 KM |
163 | } |
164 | ||
0f69d978 | 165 | static void __fsi_reg_mask_set(u32 reg, u32 mask, u32 data) |
a4d7d550 KM |
166 | { |
167 | u32 val = __fsi_reg_read(reg); | |
168 | ||
169 | val &= ~mask; | |
170 | val |= data & mask; | |
171 | ||
0f69d978 | 172 | __fsi_reg_write(reg, val); |
a4d7d550 KM |
173 | } |
174 | ||
0f69d978 | 175 | static void fsi_reg_write(struct fsi_priv *fsi, u32 reg, u32 data) |
a4d7d550 | 176 | { |
d7854147 KM |
177 | if (reg > REG_END) { |
178 | pr_err("fsi: register access err (%s)\n", __func__); | |
0f69d978 | 179 | return; |
d7854147 | 180 | } |
a4d7d550 | 181 | |
0f69d978 | 182 | __fsi_reg_write((u32)(fsi->base + reg), data); |
a4d7d550 KM |
183 | } |
184 | ||
185 | static u32 fsi_reg_read(struct fsi_priv *fsi, u32 reg) | |
186 | { | |
d7854147 KM |
187 | if (reg > REG_END) { |
188 | pr_err("fsi: register access err (%s)\n", __func__); | |
a4d7d550 | 189 | return 0; |
d7854147 | 190 | } |
a4d7d550 KM |
191 | |
192 | return __fsi_reg_read((u32)(fsi->base + reg)); | |
193 | } | |
194 | ||
0f69d978 | 195 | static void fsi_reg_mask_set(struct fsi_priv *fsi, u32 reg, u32 mask, u32 data) |
a4d7d550 | 196 | { |
d7854147 KM |
197 | if (reg > REG_END) { |
198 | pr_err("fsi: register access err (%s)\n", __func__); | |
0f69d978 | 199 | return; |
d7854147 | 200 | } |
a4d7d550 | 201 | |
0f69d978 | 202 | __fsi_reg_mask_set((u32)(fsi->base + reg), mask, data); |
a4d7d550 KM |
203 | } |
204 | ||
0f69d978 | 205 | static void fsi_master_write(struct fsi_master *master, u32 reg, u32 data) |
a4d7d550 | 206 | { |
8fc176d5 KM |
207 | unsigned long flags; |
208 | ||
a4d7d550 | 209 | if ((reg < MREG_START) || |
d7854147 KM |
210 | (reg > MREG_END)) { |
211 | pr_err("fsi: register access err (%s)\n", __func__); | |
0f69d978 | 212 | return; |
d7854147 | 213 | } |
a4d7d550 | 214 | |
8fc176d5 | 215 | spin_lock_irqsave(&master->lock, flags); |
0f69d978 | 216 | __fsi_reg_write((u32)(master->base + reg), data); |
8fc176d5 | 217 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
218 | } |
219 | ||
71f6e064 | 220 | static u32 fsi_master_read(struct fsi_master *master, u32 reg) |
a4d7d550 | 221 | { |
8fc176d5 KM |
222 | u32 ret; |
223 | unsigned long flags; | |
224 | ||
a4d7d550 | 225 | if ((reg < MREG_START) || |
d7854147 KM |
226 | (reg > MREG_END)) { |
227 | pr_err("fsi: register access err (%s)\n", __func__); | |
a4d7d550 | 228 | return 0; |
d7854147 | 229 | } |
a4d7d550 | 230 | |
8fc176d5 KM |
231 | spin_lock_irqsave(&master->lock, flags); |
232 | ret = __fsi_reg_read((u32)(master->base + reg)); | |
233 | spin_unlock_irqrestore(&master->lock, flags); | |
234 | ||
235 | return ret; | |
a4d7d550 KM |
236 | } |
237 | ||
0f69d978 | 238 | static void fsi_master_mask_set(struct fsi_master *master, |
71f6e064 | 239 | u32 reg, u32 mask, u32 data) |
a4d7d550 | 240 | { |
8fc176d5 KM |
241 | unsigned long flags; |
242 | ||
a4d7d550 | 243 | if ((reg < MREG_START) || |
d7854147 KM |
244 | (reg > MREG_END)) { |
245 | pr_err("fsi: register access err (%s)\n", __func__); | |
0f69d978 | 246 | return; |
d7854147 | 247 | } |
a4d7d550 | 248 | |
8fc176d5 | 249 | spin_lock_irqsave(&master->lock, flags); |
0f69d978 | 250 | __fsi_reg_mask_set((u32)(master->base + reg), mask, data); |
8fc176d5 | 251 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
252 | } |
253 | ||
254 | /************************************************************************ | |
255 | ||
256 | ||
257 | basic function | |
258 | ||
259 | ||
260 | ************************************************************************/ | |
71f6e064 | 261 | static struct fsi_master *fsi_get_master(struct fsi_priv *fsi) |
a4d7d550 | 262 | { |
71f6e064 | 263 | return fsi->master; |
a4d7d550 KM |
264 | } |
265 | ||
266 | static int fsi_is_port_a(struct fsi_priv *fsi) | |
267 | { | |
71f6e064 KM |
268 | return fsi->master->base == fsi->base; |
269 | } | |
a4d7d550 | 270 | |
142e8174 | 271 | static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream) |
71f6e064 KM |
272 | { |
273 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
142e8174 | 274 | |
f0fba2ad | 275 | return rtd->cpu_dai; |
142e8174 KM |
276 | } |
277 | ||
278 | static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream) | |
279 | { | |
280 | struct snd_soc_dai *dai = fsi_get_dai(substream); | |
f0fba2ad | 281 | struct fsi_master *master = snd_soc_dai_get_drvdata(dai); |
a4d7d550 | 282 | |
f0fba2ad LG |
283 | if (dai->id == 0) |
284 | return &master->fsia; | |
285 | else | |
286 | return &master->fsib; | |
a4d7d550 KM |
287 | } |
288 | ||
289 | static u32 fsi_get_info_flags(struct fsi_priv *fsi) | |
290 | { | |
291 | int is_porta = fsi_is_port_a(fsi); | |
71f6e064 | 292 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 KM |
293 | |
294 | return is_porta ? master->info->porta_flags : | |
295 | master->info->portb_flags; | |
296 | } | |
297 | ||
298 | static int fsi_is_master_mode(struct fsi_priv *fsi, int is_play) | |
299 | { | |
300 | u32 mode; | |
301 | u32 flags = fsi_get_info_flags(fsi); | |
302 | ||
303 | mode = is_play ? SH_FSI_OUT_SLAVE_MODE : SH_FSI_IN_SLAVE_MODE; | |
304 | ||
305 | /* return | |
306 | * 1 : master mode | |
307 | * 0 : slave mode | |
308 | */ | |
309 | ||
310 | return (mode & flags) != mode; | |
311 | } | |
312 | ||
313 | static u32 fsi_port_ab_io_bit(struct fsi_priv *fsi, int is_play) | |
314 | { | |
315 | int is_porta = fsi_is_port_a(fsi); | |
316 | u32 data; | |
317 | ||
318 | if (is_porta) | |
319 | data = is_play ? (1 << 0) : (1 << 4); | |
320 | else | |
321 | data = is_play ? (1 << 8) : (1 << 12); | |
322 | ||
323 | return data; | |
324 | } | |
325 | ||
326 | static void fsi_stream_push(struct fsi_priv *fsi, | |
327 | struct snd_pcm_substream *substream, | |
328 | u32 buffer_len, | |
329 | u32 period_len) | |
330 | { | |
331 | fsi->substream = substream; | |
332 | fsi->buffer_len = buffer_len; | |
333 | fsi->period_len = period_len; | |
334 | fsi->byte_offset = 0; | |
335 | fsi->periods = 0; | |
336 | } | |
337 | ||
338 | static void fsi_stream_pop(struct fsi_priv *fsi) | |
339 | { | |
340 | fsi->substream = NULL; | |
341 | fsi->buffer_len = 0; | |
342 | fsi->period_len = 0; | |
343 | fsi->byte_offset = 0; | |
344 | fsi->periods = 0; | |
345 | } | |
346 | ||
347 | static int fsi_get_fifo_residue(struct fsi_priv *fsi, int is_play) | |
348 | { | |
349 | u32 status; | |
350 | u32 reg = is_play ? DOFF_ST : DIFF_ST; | |
351 | int residue; | |
352 | ||
353 | status = fsi_reg_read(fsi, reg); | |
354 | residue = 0x1ff & (status >> 8); | |
355 | residue *= fsi->chan; | |
356 | ||
357 | return residue; | |
358 | } | |
359 | ||
a4d7d550 KM |
360 | /************************************************************************ |
361 | ||
362 | ||
10ea76cc | 363 | irq function |
a4d7d550 KM |
364 | |
365 | ||
366 | ************************************************************************/ | |
367 | static void fsi_irq_enable(struct fsi_priv *fsi, int is_play) | |
368 | { | |
369 | u32 data = fsi_port_ab_io_bit(fsi, is_play); | |
71f6e064 | 370 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 371 | |
73b92c1f KM |
372 | fsi_master_mask_set(master, master->core->imsk, data, data); |
373 | fsi_master_mask_set(master, master->core->iemsk, data, data); | |
a4d7d550 KM |
374 | } |
375 | ||
376 | static void fsi_irq_disable(struct fsi_priv *fsi, int is_play) | |
377 | { | |
378 | u32 data = fsi_port_ab_io_bit(fsi, is_play); | |
71f6e064 | 379 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 380 | |
73b92c1f KM |
381 | fsi_master_mask_set(master, master->core->imsk, data, 0); |
382 | fsi_master_mask_set(master, master->core->iemsk, data, 0); | |
a4d7d550 KM |
383 | } |
384 | ||
10ea76cc KM |
385 | static u32 fsi_irq_get_status(struct fsi_master *master) |
386 | { | |
73b92c1f | 387 | return fsi_master_read(master, master->core->int_st); |
10ea76cc KM |
388 | } |
389 | ||
390 | static void fsi_irq_clear_all_status(struct fsi_master *master) | |
391 | { | |
73b92c1f | 392 | fsi_master_write(master, master->core->int_st, 0); |
a4d7d550 KM |
393 | } |
394 | ||
10ea76cc KM |
395 | static void fsi_irq_clear_status(struct fsi_priv *fsi) |
396 | { | |
397 | u32 data = 0; | |
398 | struct fsi_master *master = fsi_get_master(fsi); | |
399 | ||
400 | data |= fsi_port_ab_io_bit(fsi, 0); | |
401 | data |= fsi_port_ab_io_bit(fsi, 1); | |
402 | ||
403 | /* clear interrupt factor */ | |
73b92c1f | 404 | fsi_master_mask_set(master, master->core->int_st, data, 0); |
10ea76cc KM |
405 | } |
406 | ||
3bc28070 KM |
407 | /************************************************************************ |
408 | ||
409 | ||
410 | SPDIF master clock function | |
411 | ||
412 | These functions are used later FSI2 | |
413 | ************************************************************************/ | |
414 | static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable) | |
415 | { | |
416 | struct fsi_master *master = fsi_get_master(fsi); | |
417 | u32 val = BP | SE; | |
418 | ||
419 | if (master->core->ver < 2) { | |
420 | pr_err("fsi: register access err (%s)\n", __func__); | |
421 | return; | |
422 | } | |
423 | ||
424 | if (enable) | |
425 | fsi_master_mask_set(master, fsi->mst_ctrl, val, val); | |
426 | else | |
427 | fsi_master_mask_set(master, fsi->mst_ctrl, val, 0); | |
428 | } | |
429 | ||
10ea76cc KM |
430 | /************************************************************************ |
431 | ||
432 | ||
433 | ctrl function | |
434 | ||
435 | ||
436 | ************************************************************************/ | |
a4d7d550 KM |
437 | static void fsi_clk_ctrl(struct fsi_priv *fsi, int enable) |
438 | { | |
439 | u32 val = fsi_is_port_a(fsi) ? (1 << 0) : (1 << 4); | |
71f6e064 | 440 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 KM |
441 | |
442 | if (enable) | |
71f6e064 | 443 | fsi_master_mask_set(master, CLK_RST, val, val); |
a4d7d550 | 444 | else |
71f6e064 | 445 | fsi_master_mask_set(master, CLK_RST, val, 0); |
a4d7d550 KM |
446 | } |
447 | ||
4a942b45 KM |
448 | static void fsi_fifo_init(struct fsi_priv *fsi, |
449 | int is_play, | |
450 | struct snd_soc_dai *dai) | |
a4d7d550 | 451 | { |
4a942b45 KM |
452 | struct fsi_master *master = fsi_get_master(fsi); |
453 | u32 ctrl, shift, i; | |
a4d7d550 | 454 | |
4a942b45 KM |
455 | /* get on-chip RAM capacity */ |
456 | shift = fsi_master_read(master, FIFO_SZ); | |
457 | shift >>= fsi_is_port_a(fsi) ? AO_SZ_SHIFT : BO_SZ_SHIFT; | |
458 | shift &= OUT_SZ_MASK; | |
459 | fsi->fifo_max = 256 << shift; | |
460 | dev_dbg(dai->dev, "fifo = %d words\n", fsi->fifo_max); | |
a4d7d550 | 461 | |
4a942b45 KM |
462 | /* |
463 | * The maximum number of sample data varies depending | |
464 | * on the number of channels selected for the format. | |
465 | * | |
466 | * FIFOs are used in 4-channel units in 3-channel mode | |
467 | * and in 8-channel units in 5- to 7-channel mode | |
468 | * meaning that more FIFOs than the required size of DPRAM | |
469 | * are used. | |
470 | * | |
471 | * ex) if 256 words of DP-RAM is connected | |
472 | * 1 channel: 256 (256 x 1 = 256) | |
473 | * 2 channels: 128 (128 x 2 = 256) | |
474 | * 3 channels: 64 ( 64 x 3 = 192) | |
475 | * 4 channels: 64 ( 64 x 4 = 256) | |
476 | * 5 channels: 32 ( 32 x 5 = 160) | |
477 | * 6 channels: 32 ( 32 x 6 = 192) | |
478 | * 7 channels: 32 ( 32 x 7 = 224) | |
479 | * 8 channels: 32 ( 32 x 8 = 256) | |
480 | */ | |
481 | for (i = 1; i < fsi->chan; i <<= 1) | |
482 | fsi->fifo_max >>= 1; | |
483 | dev_dbg(dai->dev, "%d channel %d store\n", fsi->chan, fsi->fifo_max); | |
a4d7d550 | 484 | |
a4d7d550 | 485 | ctrl = is_play ? DOFF_CTL : DIFF_CTL; |
a4d7d550 KM |
486 | |
487 | /* set interrupt generation factor */ | |
488 | fsi_reg_write(fsi, ctrl, IRQ_HALF); | |
489 | ||
490 | /* clear FIFO */ | |
491 | fsi_reg_mask_set(fsi, ctrl, FIFO_CLR, FIFO_CLR); | |
a4d7d550 KM |
492 | } |
493 | ||
71f6e064 | 494 | static void fsi_soft_all_reset(struct fsi_master *master) |
a4d7d550 | 495 | { |
a4d7d550 | 496 | /* port AB reset */ |
feb58cff | 497 | fsi_master_mask_set(master, SOFT_RST, PASR | PBSR, 0); |
a4d7d550 KM |
498 | mdelay(10); |
499 | ||
500 | /* soft reset */ | |
feb58cff KM |
501 | fsi_master_mask_set(master, SOFT_RST, FSISR, 0); |
502 | fsi_master_mask_set(master, SOFT_RST, FSISR, FSISR); | |
a4d7d550 KM |
503 | mdelay(10); |
504 | } | |
505 | ||
a4d7d550 | 506 | /* playback interrupt */ |
47fc9a0a | 507 | static int fsi_data_push(struct fsi_priv *fsi, int startup) |
a4d7d550 KM |
508 | { |
509 | struct snd_pcm_runtime *runtime; | |
510 | struct snd_pcm_substream *substream = NULL; | |
59c3b003 | 511 | u32 status; |
a4d7d550 KM |
512 | int send; |
513 | int fifo_free; | |
514 | int width; | |
9ddc9aa9 | 515 | u8 *start; |
47fc9a0a | 516 | int i, over_period; |
a4d7d550 KM |
517 | |
518 | if (!fsi || | |
519 | !fsi->substream || | |
520 | !fsi->substream->runtime) | |
521 | return -EINVAL; | |
522 | ||
1c418d1f KM |
523 | over_period = 0; |
524 | substream = fsi->substream; | |
525 | runtime = substream->runtime; | |
a4d7d550 KM |
526 | |
527 | /* FSI FIFO has limit. | |
528 | * So, this driver can not send periods data at a time | |
529 | */ | |
530 | if (fsi->byte_offset >= | |
531 | fsi->period_len * (fsi->periods + 1)) { | |
532 | ||
1c418d1f | 533 | over_period = 1; |
a4d7d550 KM |
534 | fsi->periods = (fsi->periods + 1) % runtime->periods; |
535 | ||
536 | if (0 == fsi->periods) | |
537 | fsi->byte_offset = 0; | |
538 | } | |
539 | ||
540 | /* get 1 channel data width */ | |
541 | width = frames_to_bytes(runtime, 1) / fsi->chan; | |
542 | ||
543 | /* get send size for alsa */ | |
544 | send = (fsi->buffer_len - fsi->byte_offset) / width; | |
545 | ||
546 | /* get FIFO free size */ | |
547 | fifo_free = (fsi->fifo_max * fsi->chan) - fsi_get_fifo_residue(fsi, 1); | |
548 | ||
549 | /* size check */ | |
550 | if (fifo_free < send) | |
551 | send = fifo_free; | |
552 | ||
9ddc9aa9 KM |
553 | start = runtime->dma_area; |
554 | start += fsi->byte_offset; | |
555 | ||
556 | switch (width) { | |
557 | case 2: | |
558 | for (i = 0; i < send; i++) | |
559 | fsi_reg_write(fsi, DODT, | |
560 | ((u32)*((u16 *)start + i) << 8)); | |
561 | break; | |
562 | case 4: | |
563 | for (i = 0; i < send; i++) | |
564 | fsi_reg_write(fsi, DODT, *((u32 *)start + i)); | |
565 | break; | |
566 | default: | |
a4d7d550 | 567 | return -EINVAL; |
9ddc9aa9 | 568 | } |
a4d7d550 KM |
569 | |
570 | fsi->byte_offset += send * width; | |
571 | ||
59c3b003 | 572 | status = fsi_reg_read(fsi, DOFF_ST); |
47fc9a0a | 573 | if (!startup) { |
59c3b003 | 574 | struct snd_soc_dai *dai = fsi_get_dai(substream); |
47fc9a0a KM |
575 | |
576 | if (status & ERR_OVER) | |
577 | dev_err(dai->dev, "over run\n"); | |
578 | if (status & ERR_UNDER) | |
579 | dev_err(dai->dev, "under run\n"); | |
59c3b003 | 580 | } |
47fc9a0a | 581 | fsi_reg_write(fsi, DOFF_ST, 0); |
59c3b003 | 582 | |
a4d7d550 KM |
583 | fsi_irq_enable(fsi, 1); |
584 | ||
1c418d1f | 585 | if (over_period) |
a4d7d550 KM |
586 | snd_pcm_period_elapsed(substream); |
587 | ||
47fc9a0a | 588 | return 0; |
a4d7d550 KM |
589 | } |
590 | ||
47fc9a0a | 591 | static int fsi_data_pop(struct fsi_priv *fsi, int startup) |
07102f3c KM |
592 | { |
593 | struct snd_pcm_runtime *runtime; | |
594 | struct snd_pcm_substream *substream = NULL; | |
59c3b003 | 595 | u32 status; |
07102f3c KM |
596 | int free; |
597 | int fifo_fill; | |
598 | int width; | |
599 | u8 *start; | |
47fc9a0a | 600 | int i, over_period; |
07102f3c KM |
601 | |
602 | if (!fsi || | |
603 | !fsi->substream || | |
604 | !fsi->substream->runtime) | |
605 | return -EINVAL; | |
606 | ||
1c418d1f KM |
607 | over_period = 0; |
608 | substream = fsi->substream; | |
609 | runtime = substream->runtime; | |
07102f3c KM |
610 | |
611 | /* FSI FIFO has limit. | |
612 | * So, this driver can not send periods data at a time | |
613 | */ | |
614 | if (fsi->byte_offset >= | |
615 | fsi->period_len * (fsi->periods + 1)) { | |
616 | ||
1c418d1f | 617 | over_period = 1; |
07102f3c KM |
618 | fsi->periods = (fsi->periods + 1) % runtime->periods; |
619 | ||
620 | if (0 == fsi->periods) | |
621 | fsi->byte_offset = 0; | |
622 | } | |
623 | ||
624 | /* get 1 channel data width */ | |
625 | width = frames_to_bytes(runtime, 1) / fsi->chan; | |
626 | ||
627 | /* get free space for alsa */ | |
628 | free = (fsi->buffer_len - fsi->byte_offset) / width; | |
629 | ||
630 | /* get recv size */ | |
631 | fifo_fill = fsi_get_fifo_residue(fsi, 0); | |
632 | ||
633 | if (free < fifo_fill) | |
634 | fifo_fill = free; | |
635 | ||
636 | start = runtime->dma_area; | |
637 | start += fsi->byte_offset; | |
638 | ||
639 | switch (width) { | |
640 | case 2: | |
641 | for (i = 0; i < fifo_fill; i++) | |
642 | *((u16 *)start + i) = | |
643 | (u16)(fsi_reg_read(fsi, DIDT) >> 8); | |
644 | break; | |
645 | case 4: | |
646 | for (i = 0; i < fifo_fill; i++) | |
647 | *((u32 *)start + i) = fsi_reg_read(fsi, DIDT); | |
648 | break; | |
649 | default: | |
650 | return -EINVAL; | |
651 | } | |
652 | ||
653 | fsi->byte_offset += fifo_fill * width; | |
654 | ||
59c3b003 | 655 | status = fsi_reg_read(fsi, DIFF_ST); |
47fc9a0a | 656 | if (!startup) { |
59c3b003 | 657 | struct snd_soc_dai *dai = fsi_get_dai(substream); |
47fc9a0a KM |
658 | |
659 | if (status & ERR_OVER) | |
660 | dev_err(dai->dev, "over run\n"); | |
661 | if (status & ERR_UNDER) | |
662 | dev_err(dai->dev, "under run\n"); | |
59c3b003 | 663 | } |
47fc9a0a | 664 | fsi_reg_write(fsi, DIFF_ST, 0); |
59c3b003 | 665 | |
07102f3c KM |
666 | fsi_irq_enable(fsi, 0); |
667 | ||
1c418d1f | 668 | if (over_period) |
07102f3c KM |
669 | snd_pcm_period_elapsed(substream); |
670 | ||
47fc9a0a | 671 | return 0; |
07102f3c KM |
672 | } |
673 | ||
a4d7d550 KM |
674 | static irqreturn_t fsi_interrupt(int irq, void *data) |
675 | { | |
71f6e064 | 676 | struct fsi_master *master = data; |
10ea76cc | 677 | u32 int_st = fsi_irq_get_status(master); |
a4d7d550 KM |
678 | |
679 | /* clear irq status */ | |
feb58cff KM |
680 | fsi_master_mask_set(master, SOFT_RST, IR, 0); |
681 | fsi_master_mask_set(master, SOFT_RST, IR, IR); | |
a4d7d550 KM |
682 | |
683 | if (int_st & INT_A_OUT) | |
47fc9a0a | 684 | fsi_data_push(&master->fsia, 0); |
a4d7d550 | 685 | if (int_st & INT_B_OUT) |
47fc9a0a | 686 | fsi_data_push(&master->fsib, 0); |
07102f3c | 687 | if (int_st & INT_A_IN) |
47fc9a0a | 688 | fsi_data_pop(&master->fsia, 0); |
07102f3c | 689 | if (int_st & INT_B_IN) |
47fc9a0a | 690 | fsi_data_pop(&master->fsib, 0); |
a4d7d550 | 691 | |
10ea76cc | 692 | fsi_irq_clear_all_status(master); |
a4d7d550 KM |
693 | |
694 | return IRQ_HANDLED; | |
695 | } | |
696 | ||
697 | /************************************************************************ | |
698 | ||
699 | ||
700 | dai ops | |
701 | ||
702 | ||
703 | ************************************************************************/ | |
704 | static int fsi_dai_startup(struct snd_pcm_substream *substream, | |
705 | struct snd_soc_dai *dai) | |
706 | { | |
71f6e064 | 707 | struct fsi_priv *fsi = fsi_get_priv(substream); |
a4d7d550 | 708 | u32 flags = fsi_get_info_flags(fsi); |
3bc28070 | 709 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 KM |
710 | u32 fmt; |
711 | u32 reg; | |
712 | u32 data; | |
713 | int is_play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); | |
714 | int is_master; | |
715 | int ret = 0; | |
716 | ||
785d1c45 | 717 | pm_runtime_get_sync(dai->dev); |
a4d7d550 KM |
718 | |
719 | /* CKG1 */ | |
720 | data = is_play ? (1 << 0) : (1 << 4); | |
721 | is_master = fsi_is_master_mode(fsi, is_play); | |
722 | if (is_master) | |
723 | fsi_reg_mask_set(fsi, CKG1, data, data); | |
724 | else | |
725 | fsi_reg_mask_set(fsi, CKG1, data, 0); | |
726 | ||
727 | /* clock inversion (CKG2) */ | |
728 | data = 0; | |
b427b44c KM |
729 | if (SH_FSI_LRM_INV & flags) |
730 | data |= 1 << 12; | |
731 | if (SH_FSI_BRM_INV & flags) | |
732 | data |= 1 << 8; | |
733 | if (SH_FSI_LRS_INV & flags) | |
734 | data |= 1 << 4; | |
735 | if (SH_FSI_BRS_INV & flags) | |
736 | data |= 1 << 0; | |
737 | ||
a4d7d550 KM |
738 | fsi_reg_write(fsi, CKG2, data); |
739 | ||
740 | /* do fmt, di fmt */ | |
741 | data = 0; | |
742 | reg = is_play ? DO_FMT : DI_FMT; | |
743 | fmt = is_play ? SH_FSI_GET_OFMT(flags) : SH_FSI_GET_IFMT(flags); | |
744 | switch (fmt) { | |
745 | case SH_FSI_FMT_MONO: | |
a7ffb52b | 746 | data = CR_MONO; |
a4d7d550 KM |
747 | fsi->chan = 1; |
748 | break; | |
749 | case SH_FSI_FMT_MONO_DELAY: | |
a7ffb52b | 750 | data = CR_MONO_D; |
a4d7d550 KM |
751 | fsi->chan = 1; |
752 | break; | |
753 | case SH_FSI_FMT_PCM: | |
a7ffb52b | 754 | data = CR_PCM; |
a4d7d550 KM |
755 | fsi->chan = 2; |
756 | break; | |
757 | case SH_FSI_FMT_I2S: | |
a7ffb52b | 758 | data = CR_I2S; |
a4d7d550 KM |
759 | fsi->chan = 2; |
760 | break; | |
761 | case SH_FSI_FMT_TDM: | |
a4d7d550 KM |
762 | fsi->chan = is_play ? |
763 | SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags); | |
a7ffb52b | 764 | data = CR_TDM | (fsi->chan - 1); |
a4d7d550 KM |
765 | break; |
766 | case SH_FSI_FMT_TDM_DELAY: | |
a4d7d550 KM |
767 | fsi->chan = is_play ? |
768 | SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags); | |
a7ffb52b | 769 | data = CR_TDM_D | (fsi->chan - 1); |
a4d7d550 | 770 | break; |
3bc28070 KM |
771 | case SH_FSI_FMT_SPDIF: |
772 | if (master->core->ver < 2) { | |
773 | dev_err(dai->dev, "This FSI can not use SPDIF\n"); | |
774 | return -EINVAL; | |
775 | } | |
776 | data = CR_SPDIF; | |
777 | fsi->chan = 2; | |
778 | fsi_spdif_clk_ctrl(fsi, 1); | |
779 | fsi_reg_mask_set(fsi, OUT_SEL, 0x0010, 0x0010); | |
780 | break; | |
a4d7d550 KM |
781 | default: |
782 | dev_err(dai->dev, "unknown format.\n"); | |
783 | return -EINVAL; | |
784 | } | |
a4d7d550 | 785 | fsi_reg_write(fsi, reg, data); |
a4d7d550 | 786 | |
10ea76cc KM |
787 | /* irq clear */ |
788 | fsi_irq_disable(fsi, is_play); | |
789 | fsi_irq_clear_status(fsi); | |
790 | ||
791 | /* fifo init */ | |
4a942b45 | 792 | fsi_fifo_init(fsi, is_play, dai); |
a4d7d550 KM |
793 | |
794 | return ret; | |
795 | } | |
796 | ||
797 | static void fsi_dai_shutdown(struct snd_pcm_substream *substream, | |
798 | struct snd_soc_dai *dai) | |
799 | { | |
71f6e064 | 800 | struct fsi_priv *fsi = fsi_get_priv(substream); |
a4d7d550 KM |
801 | int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
802 | ||
803 | fsi_irq_disable(fsi, is_play); | |
804 | fsi_clk_ctrl(fsi, 0); | |
805 | ||
785d1c45 | 806 | pm_runtime_put_sync(dai->dev); |
a4d7d550 KM |
807 | } |
808 | ||
809 | static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd, | |
810 | struct snd_soc_dai *dai) | |
811 | { | |
71f6e064 | 812 | struct fsi_priv *fsi = fsi_get_priv(substream); |
a4d7d550 KM |
813 | struct snd_pcm_runtime *runtime = substream->runtime; |
814 | int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; | |
815 | int ret = 0; | |
816 | ||
a4d7d550 KM |
817 | switch (cmd) { |
818 | case SNDRV_PCM_TRIGGER_START: | |
819 | fsi_stream_push(fsi, substream, | |
820 | frames_to_bytes(runtime, runtime->buffer_size), | |
821 | frames_to_bytes(runtime, runtime->period_size)); | |
47fc9a0a | 822 | ret = is_play ? fsi_data_push(fsi, 1) : fsi_data_pop(fsi, 1); |
a4d7d550 KM |
823 | break; |
824 | case SNDRV_PCM_TRIGGER_STOP: | |
825 | fsi_irq_disable(fsi, is_play); | |
826 | fsi_stream_pop(fsi); | |
827 | break; | |
828 | } | |
829 | ||
830 | return ret; | |
831 | } | |
832 | ||
ccad7b44 KM |
833 | static int fsi_dai_hw_params(struct snd_pcm_substream *substream, |
834 | struct snd_pcm_hw_params *params, | |
835 | struct snd_soc_dai *dai) | |
836 | { | |
837 | struct fsi_priv *fsi = fsi_get_priv(substream); | |
838 | struct fsi_master *master = fsi_get_master(fsi); | |
839 | int (*set_rate)(int is_porta, int rate) = master->info->set_rate; | |
840 | int fsi_ver = master->core->ver; | |
841 | int is_play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); | |
842 | int ret; | |
843 | ||
844 | /* if slave mode, set_rate is not needed */ | |
845 | if (!fsi_is_master_mode(fsi, is_play)) | |
846 | return 0; | |
847 | ||
848 | /* it is error if no set_rate */ | |
849 | if (!set_rate) | |
850 | return -EIO; | |
851 | ||
ccad7b44 KM |
852 | ret = set_rate(fsi_is_port_a(fsi), params_rate(params)); |
853 | if (ret > 0) { | |
854 | u32 data = 0; | |
855 | ||
856 | switch (ret & SH_FSI_ACKMD_MASK) { | |
857 | default: | |
858 | /* FALL THROUGH */ | |
859 | case SH_FSI_ACKMD_512: | |
860 | data |= (0x0 << 12); | |
861 | break; | |
862 | case SH_FSI_ACKMD_256: | |
863 | data |= (0x1 << 12); | |
864 | break; | |
865 | case SH_FSI_ACKMD_128: | |
866 | data |= (0x2 << 12); | |
867 | break; | |
868 | case SH_FSI_ACKMD_64: | |
869 | data |= (0x3 << 12); | |
870 | break; | |
871 | case SH_FSI_ACKMD_32: | |
872 | if (fsi_ver < 2) | |
873 | dev_err(dai->dev, "unsupported ACKMD\n"); | |
874 | else | |
875 | data |= (0x4 << 12); | |
876 | break; | |
877 | } | |
878 | ||
879 | switch (ret & SH_FSI_BPFMD_MASK) { | |
880 | default: | |
881 | /* FALL THROUGH */ | |
882 | case SH_FSI_BPFMD_32: | |
883 | data |= (0x0 << 8); | |
884 | break; | |
885 | case SH_FSI_BPFMD_64: | |
886 | data |= (0x1 << 8); | |
887 | break; | |
888 | case SH_FSI_BPFMD_128: | |
889 | data |= (0x2 << 8); | |
890 | break; | |
891 | case SH_FSI_BPFMD_256: | |
892 | data |= (0x3 << 8); | |
893 | break; | |
894 | case SH_FSI_BPFMD_512: | |
895 | data |= (0x4 << 8); | |
896 | break; | |
897 | case SH_FSI_BPFMD_16: | |
898 | if (fsi_ver < 2) | |
899 | dev_err(dai->dev, "unsupported ACKMD\n"); | |
900 | else | |
901 | data |= (0x7 << 8); | |
902 | break; | |
903 | } | |
904 | ||
905 | fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data); | |
906 | udelay(10); | |
907 | fsi_clk_ctrl(fsi, 1); | |
908 | ret = 0; | |
909 | } | |
ccad7b44 KM |
910 | |
911 | return ret; | |
912 | ||
913 | } | |
914 | ||
a4d7d550 KM |
915 | static struct snd_soc_dai_ops fsi_dai_ops = { |
916 | .startup = fsi_dai_startup, | |
917 | .shutdown = fsi_dai_shutdown, | |
918 | .trigger = fsi_dai_trigger, | |
ccad7b44 | 919 | .hw_params = fsi_dai_hw_params, |
a4d7d550 KM |
920 | }; |
921 | ||
922 | /************************************************************************ | |
923 | ||
924 | ||
925 | pcm ops | |
926 | ||
927 | ||
928 | ************************************************************************/ | |
929 | static struct snd_pcm_hardware fsi_pcm_hardware = { | |
930 | .info = SNDRV_PCM_INFO_INTERLEAVED | | |
931 | SNDRV_PCM_INFO_MMAP | | |
932 | SNDRV_PCM_INFO_MMAP_VALID | | |
933 | SNDRV_PCM_INFO_PAUSE, | |
934 | .formats = FSI_FMTS, | |
935 | .rates = FSI_RATES, | |
936 | .rate_min = 8000, | |
937 | .rate_max = 192000, | |
938 | .channels_min = 1, | |
939 | .channels_max = 2, | |
940 | .buffer_bytes_max = 64 * 1024, | |
941 | .period_bytes_min = 32, | |
942 | .period_bytes_max = 8192, | |
943 | .periods_min = 1, | |
944 | .periods_max = 32, | |
945 | .fifo_size = 256, | |
946 | }; | |
947 | ||
948 | static int fsi_pcm_open(struct snd_pcm_substream *substream) | |
949 | { | |
950 | struct snd_pcm_runtime *runtime = substream->runtime; | |
951 | int ret = 0; | |
952 | ||
953 | snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware); | |
954 | ||
955 | ret = snd_pcm_hw_constraint_integer(runtime, | |
956 | SNDRV_PCM_HW_PARAM_PERIODS); | |
957 | ||
958 | return ret; | |
959 | } | |
960 | ||
961 | static int fsi_hw_params(struct snd_pcm_substream *substream, | |
962 | struct snd_pcm_hw_params *hw_params) | |
963 | { | |
964 | return snd_pcm_lib_malloc_pages(substream, | |
965 | params_buffer_bytes(hw_params)); | |
966 | } | |
967 | ||
968 | static int fsi_hw_free(struct snd_pcm_substream *substream) | |
969 | { | |
970 | return snd_pcm_lib_free_pages(substream); | |
971 | } | |
972 | ||
973 | static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream) | |
974 | { | |
975 | struct snd_pcm_runtime *runtime = substream->runtime; | |
71f6e064 | 976 | struct fsi_priv *fsi = fsi_get_priv(substream); |
a4d7d550 KM |
977 | long location; |
978 | ||
9ddc9aa9 | 979 | location = (fsi->byte_offset - 1); |
a4d7d550 KM |
980 | if (location < 0) |
981 | location = 0; | |
982 | ||
983 | return bytes_to_frames(runtime, location); | |
984 | } | |
985 | ||
986 | static struct snd_pcm_ops fsi_pcm_ops = { | |
987 | .open = fsi_pcm_open, | |
988 | .ioctl = snd_pcm_lib_ioctl, | |
989 | .hw_params = fsi_hw_params, | |
990 | .hw_free = fsi_hw_free, | |
991 | .pointer = fsi_pointer, | |
992 | }; | |
993 | ||
994 | /************************************************************************ | |
995 | ||
996 | ||
997 | snd_soc_platform | |
998 | ||
999 | ||
1000 | ************************************************************************/ | |
1001 | #define PREALLOC_BUFFER (32 * 1024) | |
1002 | #define PREALLOC_BUFFER_MAX (32 * 1024) | |
1003 | ||
1004 | static void fsi_pcm_free(struct snd_pcm *pcm) | |
1005 | { | |
1006 | snd_pcm_lib_preallocate_free_for_all(pcm); | |
1007 | } | |
1008 | ||
1009 | static int fsi_pcm_new(struct snd_card *card, | |
1010 | struct snd_soc_dai *dai, | |
1011 | struct snd_pcm *pcm) | |
1012 | { | |
1013 | /* | |
1014 | * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel | |
1015 | * in MMAP mode (i.e. aplay -M) | |
1016 | */ | |
1017 | return snd_pcm_lib_preallocate_pages_for_all( | |
1018 | pcm, | |
1019 | SNDRV_DMA_TYPE_CONTINUOUS, | |
1020 | snd_dma_continuous_data(GFP_KERNEL), | |
1021 | PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); | |
1022 | } | |
1023 | ||
1024 | /************************************************************************ | |
1025 | ||
1026 | ||
1027 | alsa struct | |
1028 | ||
1029 | ||
1030 | ************************************************************************/ | |
f0fba2ad | 1031 | static struct snd_soc_dai_driver fsi_soc_dai[] = { |
a4d7d550 | 1032 | { |
f0fba2ad | 1033 | .name = "fsia-dai", |
a4d7d550 KM |
1034 | .playback = { |
1035 | .rates = FSI_RATES, | |
1036 | .formats = FSI_FMTS, | |
1037 | .channels_min = 1, | |
1038 | .channels_max = 8, | |
1039 | }, | |
07102f3c KM |
1040 | .capture = { |
1041 | .rates = FSI_RATES, | |
1042 | .formats = FSI_FMTS, | |
1043 | .channels_min = 1, | |
1044 | .channels_max = 8, | |
1045 | }, | |
a4d7d550 KM |
1046 | .ops = &fsi_dai_ops, |
1047 | }, | |
1048 | { | |
f0fba2ad | 1049 | .name = "fsib-dai", |
a4d7d550 KM |
1050 | .playback = { |
1051 | .rates = FSI_RATES, | |
1052 | .formats = FSI_FMTS, | |
1053 | .channels_min = 1, | |
1054 | .channels_max = 8, | |
1055 | }, | |
07102f3c KM |
1056 | .capture = { |
1057 | .rates = FSI_RATES, | |
1058 | .formats = FSI_FMTS, | |
1059 | .channels_min = 1, | |
1060 | .channels_max = 8, | |
1061 | }, | |
a4d7d550 KM |
1062 | .ops = &fsi_dai_ops, |
1063 | }, | |
1064 | }; | |
a4d7d550 | 1065 | |
f0fba2ad LG |
1066 | static struct snd_soc_platform_driver fsi_soc_platform = { |
1067 | .ops = &fsi_pcm_ops, | |
a4d7d550 KM |
1068 | .pcm_new = fsi_pcm_new, |
1069 | .pcm_free = fsi_pcm_free, | |
1070 | }; | |
a4d7d550 KM |
1071 | |
1072 | /************************************************************************ | |
1073 | ||
1074 | ||
1075 | platform function | |
1076 | ||
1077 | ||
1078 | ************************************************************************/ | |
1079 | static int fsi_probe(struct platform_device *pdev) | |
1080 | { | |
71f6e064 | 1081 | struct fsi_master *master; |
cc780d38 | 1082 | const struct platform_device_id *id_entry; |
a4d7d550 | 1083 | struct resource *res; |
a4d7d550 KM |
1084 | unsigned int irq; |
1085 | int ret; | |
1086 | ||
cc780d38 KM |
1087 | id_entry = pdev->id_entry; |
1088 | if (!id_entry) { | |
1089 | dev_err(&pdev->dev, "unknown fsi device\n"); | |
1090 | return -ENODEV; | |
1091 | } | |
1092 | ||
a4d7d550 KM |
1093 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1094 | irq = platform_get_irq(pdev, 0); | |
b6aa1793 | 1095 | if (!res || (int)irq <= 0) { |
a4d7d550 KM |
1096 | dev_err(&pdev->dev, "Not enough FSI platform resources.\n"); |
1097 | ret = -ENODEV; | |
1098 | goto exit; | |
1099 | } | |
1100 | ||
1101 | master = kzalloc(sizeof(*master), GFP_KERNEL); | |
1102 | if (!master) { | |
1103 | dev_err(&pdev->dev, "Could not allocate master\n"); | |
1104 | ret = -ENOMEM; | |
1105 | goto exit; | |
1106 | } | |
1107 | ||
1108 | master->base = ioremap_nocache(res->start, resource_size(res)); | |
1109 | if (!master->base) { | |
1110 | ret = -ENXIO; | |
1111 | dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n"); | |
1112 | goto exit_kfree; | |
1113 | } | |
1114 | ||
3bc28070 | 1115 | /* master setting */ |
a4d7d550 KM |
1116 | master->irq = irq; |
1117 | master->info = pdev->dev.platform_data; | |
3bc28070 KM |
1118 | master->core = (struct fsi_core *)id_entry->driver_data; |
1119 | spin_lock_init(&master->lock); | |
1120 | ||
1121 | /* FSI A setting */ | |
a4d7d550 | 1122 | master->fsia.base = master->base; |
71f6e064 | 1123 | master->fsia.master = master; |
3bc28070 KM |
1124 | master->fsia.mst_ctrl = A_MST_CTLR; |
1125 | ||
1126 | /* FSI B setting */ | |
a4d7d550 | 1127 | master->fsib.base = master->base + 0x40; |
71f6e064 | 1128 | master->fsib.master = master; |
3bc28070 | 1129 | master->fsib.mst_ctrl = B_MST_CTLR; |
a4d7d550 | 1130 | |
785d1c45 KM |
1131 | pm_runtime_enable(&pdev->dev); |
1132 | pm_runtime_resume(&pdev->dev); | |
f0fba2ad | 1133 | dev_set_drvdata(&pdev->dev, master); |
a4d7d550 | 1134 | |
71f6e064 | 1135 | fsi_soft_all_reset(master); |
a4d7d550 | 1136 | |
cc780d38 KM |
1137 | ret = request_irq(irq, &fsi_interrupt, IRQF_DISABLED, |
1138 | id_entry->name, master); | |
a4d7d550 KM |
1139 | if (ret) { |
1140 | dev_err(&pdev->dev, "irq request err\n"); | |
9ddc9aa9 | 1141 | goto exit_iounmap; |
a4d7d550 KM |
1142 | } |
1143 | ||
f0fba2ad | 1144 | ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform); |
a4d7d550 KM |
1145 | if (ret < 0) { |
1146 | dev_err(&pdev->dev, "cannot snd soc register\n"); | |
1147 | goto exit_free_irq; | |
1148 | } | |
1149 | ||
f0fba2ad | 1150 | return snd_soc_register_dais(&pdev->dev, fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai)); |
a4d7d550 KM |
1151 | |
1152 | exit_free_irq: | |
1153 | free_irq(irq, master); | |
a4d7d550 KM |
1154 | exit_iounmap: |
1155 | iounmap(master->base); | |
785d1c45 | 1156 | pm_runtime_disable(&pdev->dev); |
a4d7d550 KM |
1157 | exit_kfree: |
1158 | kfree(master); | |
1159 | master = NULL; | |
1160 | exit: | |
1161 | return ret; | |
1162 | } | |
1163 | ||
1164 | static int fsi_remove(struct platform_device *pdev) | |
1165 | { | |
71f6e064 KM |
1166 | struct fsi_master *master; |
1167 | ||
f0fba2ad | 1168 | master = dev_get_drvdata(&pdev->dev); |
71f6e064 | 1169 | |
f0fba2ad LG |
1170 | snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(fsi_soc_dai)); |
1171 | snd_soc_unregister_platform(&pdev->dev); | |
a4d7d550 | 1172 | |
785d1c45 | 1173 | pm_runtime_disable(&pdev->dev); |
a4d7d550 | 1174 | |
a4d7d550 KM |
1175 | free_irq(master->irq, master); |
1176 | ||
1177 | iounmap(master->base); | |
1178 | kfree(master); | |
71f6e064 | 1179 | |
a4d7d550 KM |
1180 | return 0; |
1181 | } | |
1182 | ||
785d1c45 KM |
1183 | static int fsi_runtime_nop(struct device *dev) |
1184 | { | |
1185 | /* Runtime PM callback shared between ->runtime_suspend() | |
1186 | * and ->runtime_resume(). Simply returns success. | |
1187 | * | |
1188 | * This driver re-initializes all registers after | |
1189 | * pm_runtime_get_sync() anyway so there is no need | |
1190 | * to save and restore registers here. | |
1191 | */ | |
1192 | return 0; | |
1193 | } | |
1194 | ||
1195 | static struct dev_pm_ops fsi_pm_ops = { | |
1196 | .runtime_suspend = fsi_runtime_nop, | |
1197 | .runtime_resume = fsi_runtime_nop, | |
1198 | }; | |
1199 | ||
73b92c1f KM |
1200 | static struct fsi_core fsi1_core = { |
1201 | .ver = 1, | |
1202 | ||
1203 | /* Interrupt */ | |
cc780d38 KM |
1204 | .int_st = INT_ST, |
1205 | .iemsk = IEMSK, | |
1206 | .imsk = IMSK, | |
1207 | }; | |
1208 | ||
73b92c1f KM |
1209 | static struct fsi_core fsi2_core = { |
1210 | .ver = 2, | |
1211 | ||
1212 | /* Interrupt */ | |
cc780d38 KM |
1213 | .int_st = CPU_INT_ST, |
1214 | .iemsk = CPU_IEMSK, | |
1215 | .imsk = CPU_IMSK, | |
1216 | }; | |
1217 | ||
1218 | static struct platform_device_id fsi_id_table[] = { | |
73b92c1f KM |
1219 | { "sh_fsi", (kernel_ulong_t)&fsi1_core }, |
1220 | { "sh_fsi2", (kernel_ulong_t)&fsi2_core }, | |
cc780d38 | 1221 | }; |
d85a6d7b | 1222 | MODULE_DEVICE_TABLE(platform, fsi_id_table); |
cc780d38 | 1223 | |
a4d7d550 KM |
1224 | static struct platform_driver fsi_driver = { |
1225 | .driver = { | |
f0fba2ad | 1226 | .name = "fsi-pcm-audio", |
785d1c45 | 1227 | .pm = &fsi_pm_ops, |
a4d7d550 KM |
1228 | }, |
1229 | .probe = fsi_probe, | |
1230 | .remove = fsi_remove, | |
cc780d38 | 1231 | .id_table = fsi_id_table, |
a4d7d550 KM |
1232 | }; |
1233 | ||
1234 | static int __init fsi_mobile_init(void) | |
1235 | { | |
1236 | return platform_driver_register(&fsi_driver); | |
1237 | } | |
1238 | ||
1239 | static void __exit fsi_mobile_exit(void) | |
1240 | { | |
1241 | platform_driver_unregister(&fsi_driver); | |
1242 | } | |
d85a6d7b | 1243 | |
a4d7d550 KM |
1244 | module_init(fsi_mobile_init); |
1245 | module_exit(fsi_mobile_exit); | |
1246 | ||
1247 | MODULE_LICENSE("GPL"); | |
1248 | MODULE_DESCRIPTION("SuperH onchip FSI audio driver"); | |
1249 | MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>"); |