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a4d7d550 KM |
1 | /* |
2 | * Fifo-attached Serial Interface (FSI) support for SH7724 | |
3 | * | |
4 | * Copyright (C) 2009 Renesas Solutions Corp. | |
5 | * Kuninori Morimoto <morimoto.kuninori@renesas.com> | |
6 | * | |
7 | * Based on ssi.c | |
8 | * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
a4d7d550 | 15 | #include <linux/delay.h> |
785d1c45 | 16 | #include <linux/pm_runtime.h> |
a4d7d550 | 17 | #include <linux/io.h> |
5a0e3ad6 | 18 | #include <linux/slab.h> |
a4d7d550 | 19 | #include <sound/soc.h> |
a4d7d550 | 20 | #include <sound/sh_fsi.h> |
a4d7d550 KM |
21 | |
22 | #define DO_FMT 0x0000 | |
23 | #define DOFF_CTL 0x0004 | |
24 | #define DOFF_ST 0x0008 | |
25 | #define DI_FMT 0x000C | |
26 | #define DIFF_CTL 0x0010 | |
27 | #define DIFF_ST 0x0014 | |
28 | #define CKG1 0x0018 | |
29 | #define CKG2 0x001C | |
30 | #define DIDT 0x0020 | |
31 | #define DODT 0x0024 | |
32 | #define MUTE_ST 0x0028 | |
33 | #define REG_END MUTE_ST | |
34 | ||
cc780d38 KM |
35 | |
36 | #define CPU_INT_ST 0x01F4 | |
37 | #define CPU_IEMSK 0x01F8 | |
38 | #define CPU_IMSK 0x01FC | |
a4d7d550 KM |
39 | #define INT_ST 0x0200 |
40 | #define IEMSK 0x0204 | |
41 | #define IMSK 0x0208 | |
42 | #define MUTE 0x020C | |
43 | #define CLK_RST 0x0210 | |
44 | #define SOFT_RST 0x0214 | |
4a942b45 | 45 | #define FIFO_SZ 0x0218 |
cc780d38 | 46 | #define MREG_START CPU_INT_ST |
4a942b45 | 47 | #define MREG_END FIFO_SZ |
a4d7d550 KM |
48 | |
49 | /* DO_FMT */ | |
50 | /* DI_FMT */ | |
a7ffb52b KM |
51 | #define CR_MONO (0x0 << 4) |
52 | #define CR_MONO_D (0x1 << 4) | |
53 | #define CR_PCM (0x2 << 4) | |
54 | #define CR_I2S (0x3 << 4) | |
55 | #define CR_TDM (0x4 << 4) | |
56 | #define CR_TDM_D (0x5 << 4) | |
a4d7d550 KM |
57 | |
58 | /* DOFF_CTL */ | |
59 | /* DIFF_CTL */ | |
60 | #define IRQ_HALF 0x00100000 | |
61 | #define FIFO_CLR 0x00000001 | |
62 | ||
63 | /* DOFF_ST */ | |
64 | #define ERR_OVER 0x00000010 | |
65 | #define ERR_UNDER 0x00000001 | |
59c3b003 | 66 | #define ST_ERR (ERR_OVER | ERR_UNDER) |
a4d7d550 | 67 | |
ccad7b44 KM |
68 | /* CKG1 */ |
69 | #define ACKMD_MASK 0x00007000 | |
70 | #define BPFMD_MASK 0x00000700 | |
71 | ||
a4d7d550 KM |
72 | /* CLK_RST */ |
73 | #define B_CLK 0x00000010 | |
74 | #define A_CLK 0x00000001 | |
75 | ||
76 | /* INT_ST */ | |
77 | #define INT_B_IN (1 << 12) | |
78 | #define INT_B_OUT (1 << 8) | |
79 | #define INT_A_IN (1 << 4) | |
80 | #define INT_A_OUT (1 << 0) | |
81 | ||
feb58cff KM |
82 | /* SOFT_RST */ |
83 | #define PBSR (1 << 12) /* Port B Software Reset */ | |
84 | #define PASR (1 << 8) /* Port A Software Reset */ | |
85 | #define IR (1 << 4) /* Interrupt Reset */ | |
86 | #define FSISR (1 << 0) /* Software Reset */ | |
87 | ||
4a942b45 KM |
88 | /* FIFO_SZ */ |
89 | #define OUT_SZ_MASK 0x7 | |
90 | #define BO_SZ_SHIFT 8 | |
91 | #define AO_SZ_SHIFT 0 | |
92 | ||
a4d7d550 KM |
93 | #define FSI_RATES SNDRV_PCM_RATE_8000_96000 |
94 | ||
95 | #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE) | |
96 | ||
97 | /************************************************************************ | |
98 | ||
99 | ||
100 | struct | |
101 | ||
102 | ||
103 | ************************************************************************/ | |
104 | struct fsi_priv { | |
105 | void __iomem *base; | |
106 | struct snd_pcm_substream *substream; | |
71f6e064 | 107 | struct fsi_master *master; |
a4d7d550 KM |
108 | |
109 | int fifo_max; | |
110 | int chan; | |
a4d7d550 KM |
111 | |
112 | int byte_offset; | |
113 | int period_len; | |
114 | int buffer_len; | |
115 | int periods; | |
116 | }; | |
117 | ||
73b92c1f KM |
118 | struct fsi_core { |
119 | int ver; | |
120 | ||
cc780d38 KM |
121 | u32 int_st; |
122 | u32 iemsk; | |
123 | u32 imsk; | |
124 | }; | |
125 | ||
a4d7d550 KM |
126 | struct fsi_master { |
127 | void __iomem *base; | |
128 | int irq; | |
a4d7d550 KM |
129 | struct fsi_priv fsia; |
130 | struct fsi_priv fsib; | |
73b92c1f | 131 | struct fsi_core *core; |
a4d7d550 | 132 | struct sh_fsi_platform_info *info; |
8fc176d5 | 133 | spinlock_t lock; |
a4d7d550 KM |
134 | }; |
135 | ||
a4d7d550 KM |
136 | /************************************************************************ |
137 | ||
138 | ||
139 | basic read write function | |
140 | ||
141 | ||
142 | ************************************************************************/ | |
0f69d978 | 143 | static void __fsi_reg_write(u32 reg, u32 data) |
a4d7d550 KM |
144 | { |
145 | /* valid data area is 24bit */ | |
146 | data &= 0x00ffffff; | |
147 | ||
0f69d978 | 148 | __raw_writel(data, reg); |
a4d7d550 KM |
149 | } |
150 | ||
151 | static u32 __fsi_reg_read(u32 reg) | |
152 | { | |
0f69d978 | 153 | return __raw_readl(reg); |
a4d7d550 KM |
154 | } |
155 | ||
0f69d978 | 156 | static void __fsi_reg_mask_set(u32 reg, u32 mask, u32 data) |
a4d7d550 KM |
157 | { |
158 | u32 val = __fsi_reg_read(reg); | |
159 | ||
160 | val &= ~mask; | |
161 | val |= data & mask; | |
162 | ||
0f69d978 | 163 | __fsi_reg_write(reg, val); |
a4d7d550 KM |
164 | } |
165 | ||
0f69d978 | 166 | static void fsi_reg_write(struct fsi_priv *fsi, u32 reg, u32 data) |
a4d7d550 | 167 | { |
d7854147 KM |
168 | if (reg > REG_END) { |
169 | pr_err("fsi: register access err (%s)\n", __func__); | |
0f69d978 | 170 | return; |
d7854147 | 171 | } |
a4d7d550 | 172 | |
0f69d978 | 173 | __fsi_reg_write((u32)(fsi->base + reg), data); |
a4d7d550 KM |
174 | } |
175 | ||
176 | static u32 fsi_reg_read(struct fsi_priv *fsi, u32 reg) | |
177 | { | |
d7854147 KM |
178 | if (reg > REG_END) { |
179 | pr_err("fsi: register access err (%s)\n", __func__); | |
a4d7d550 | 180 | return 0; |
d7854147 | 181 | } |
a4d7d550 KM |
182 | |
183 | return __fsi_reg_read((u32)(fsi->base + reg)); | |
184 | } | |
185 | ||
0f69d978 | 186 | static void fsi_reg_mask_set(struct fsi_priv *fsi, u32 reg, u32 mask, u32 data) |
a4d7d550 | 187 | { |
d7854147 KM |
188 | if (reg > REG_END) { |
189 | pr_err("fsi: register access err (%s)\n", __func__); | |
0f69d978 | 190 | return; |
d7854147 | 191 | } |
a4d7d550 | 192 | |
0f69d978 | 193 | __fsi_reg_mask_set((u32)(fsi->base + reg), mask, data); |
a4d7d550 KM |
194 | } |
195 | ||
0f69d978 | 196 | static void fsi_master_write(struct fsi_master *master, u32 reg, u32 data) |
a4d7d550 | 197 | { |
8fc176d5 KM |
198 | unsigned long flags; |
199 | ||
a4d7d550 | 200 | if ((reg < MREG_START) || |
d7854147 KM |
201 | (reg > MREG_END)) { |
202 | pr_err("fsi: register access err (%s)\n", __func__); | |
0f69d978 | 203 | return; |
d7854147 | 204 | } |
a4d7d550 | 205 | |
8fc176d5 | 206 | spin_lock_irqsave(&master->lock, flags); |
0f69d978 | 207 | __fsi_reg_write((u32)(master->base + reg), data); |
8fc176d5 | 208 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
209 | } |
210 | ||
71f6e064 | 211 | static u32 fsi_master_read(struct fsi_master *master, u32 reg) |
a4d7d550 | 212 | { |
8fc176d5 KM |
213 | u32 ret; |
214 | unsigned long flags; | |
215 | ||
a4d7d550 | 216 | if ((reg < MREG_START) || |
d7854147 KM |
217 | (reg > MREG_END)) { |
218 | pr_err("fsi: register access err (%s)\n", __func__); | |
a4d7d550 | 219 | return 0; |
d7854147 | 220 | } |
a4d7d550 | 221 | |
8fc176d5 KM |
222 | spin_lock_irqsave(&master->lock, flags); |
223 | ret = __fsi_reg_read((u32)(master->base + reg)); | |
224 | spin_unlock_irqrestore(&master->lock, flags); | |
225 | ||
226 | return ret; | |
a4d7d550 KM |
227 | } |
228 | ||
0f69d978 | 229 | static void fsi_master_mask_set(struct fsi_master *master, |
71f6e064 | 230 | u32 reg, u32 mask, u32 data) |
a4d7d550 | 231 | { |
8fc176d5 KM |
232 | unsigned long flags; |
233 | ||
a4d7d550 | 234 | if ((reg < MREG_START) || |
d7854147 KM |
235 | (reg > MREG_END)) { |
236 | pr_err("fsi: register access err (%s)\n", __func__); | |
0f69d978 | 237 | return; |
d7854147 | 238 | } |
a4d7d550 | 239 | |
8fc176d5 | 240 | spin_lock_irqsave(&master->lock, flags); |
0f69d978 | 241 | __fsi_reg_mask_set((u32)(master->base + reg), mask, data); |
8fc176d5 | 242 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
243 | } |
244 | ||
245 | /************************************************************************ | |
246 | ||
247 | ||
248 | basic function | |
249 | ||
250 | ||
251 | ************************************************************************/ | |
71f6e064 | 252 | static struct fsi_master *fsi_get_master(struct fsi_priv *fsi) |
a4d7d550 | 253 | { |
71f6e064 | 254 | return fsi->master; |
a4d7d550 KM |
255 | } |
256 | ||
257 | static int fsi_is_port_a(struct fsi_priv *fsi) | |
258 | { | |
71f6e064 KM |
259 | return fsi->master->base == fsi->base; |
260 | } | |
a4d7d550 | 261 | |
142e8174 | 262 | static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream) |
71f6e064 KM |
263 | { |
264 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
265 | struct snd_soc_dai_link *machine = rtd->dai; | |
142e8174 KM |
266 | |
267 | return machine->cpu_dai; | |
268 | } | |
269 | ||
270 | static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream) | |
271 | { | |
272 | struct snd_soc_dai *dai = fsi_get_dai(substream); | |
a4d7d550 | 273 | |
71f6e064 | 274 | return dai->private_data; |
a4d7d550 KM |
275 | } |
276 | ||
277 | static u32 fsi_get_info_flags(struct fsi_priv *fsi) | |
278 | { | |
279 | int is_porta = fsi_is_port_a(fsi); | |
71f6e064 | 280 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 KM |
281 | |
282 | return is_porta ? master->info->porta_flags : | |
283 | master->info->portb_flags; | |
284 | } | |
285 | ||
286 | static int fsi_is_master_mode(struct fsi_priv *fsi, int is_play) | |
287 | { | |
288 | u32 mode; | |
289 | u32 flags = fsi_get_info_flags(fsi); | |
290 | ||
291 | mode = is_play ? SH_FSI_OUT_SLAVE_MODE : SH_FSI_IN_SLAVE_MODE; | |
292 | ||
293 | /* return | |
294 | * 1 : master mode | |
295 | * 0 : slave mode | |
296 | */ | |
297 | ||
298 | return (mode & flags) != mode; | |
299 | } | |
300 | ||
301 | static u32 fsi_port_ab_io_bit(struct fsi_priv *fsi, int is_play) | |
302 | { | |
303 | int is_porta = fsi_is_port_a(fsi); | |
304 | u32 data; | |
305 | ||
306 | if (is_porta) | |
307 | data = is_play ? (1 << 0) : (1 << 4); | |
308 | else | |
309 | data = is_play ? (1 << 8) : (1 << 12); | |
310 | ||
311 | return data; | |
312 | } | |
313 | ||
314 | static void fsi_stream_push(struct fsi_priv *fsi, | |
315 | struct snd_pcm_substream *substream, | |
316 | u32 buffer_len, | |
317 | u32 period_len) | |
318 | { | |
319 | fsi->substream = substream; | |
320 | fsi->buffer_len = buffer_len; | |
321 | fsi->period_len = period_len; | |
322 | fsi->byte_offset = 0; | |
323 | fsi->periods = 0; | |
324 | } | |
325 | ||
326 | static void fsi_stream_pop(struct fsi_priv *fsi) | |
327 | { | |
328 | fsi->substream = NULL; | |
329 | fsi->buffer_len = 0; | |
330 | fsi->period_len = 0; | |
331 | fsi->byte_offset = 0; | |
332 | fsi->periods = 0; | |
333 | } | |
334 | ||
335 | static int fsi_get_fifo_residue(struct fsi_priv *fsi, int is_play) | |
336 | { | |
337 | u32 status; | |
338 | u32 reg = is_play ? DOFF_ST : DIFF_ST; | |
339 | int residue; | |
340 | ||
341 | status = fsi_reg_read(fsi, reg); | |
342 | residue = 0x1ff & (status >> 8); | |
343 | residue *= fsi->chan; | |
344 | ||
345 | return residue; | |
346 | } | |
347 | ||
a4d7d550 KM |
348 | /************************************************************************ |
349 | ||
350 | ||
10ea76cc | 351 | irq function |
a4d7d550 KM |
352 | |
353 | ||
354 | ************************************************************************/ | |
355 | static void fsi_irq_enable(struct fsi_priv *fsi, int is_play) | |
356 | { | |
357 | u32 data = fsi_port_ab_io_bit(fsi, is_play); | |
71f6e064 | 358 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 359 | |
73b92c1f KM |
360 | fsi_master_mask_set(master, master->core->imsk, data, data); |
361 | fsi_master_mask_set(master, master->core->iemsk, data, data); | |
a4d7d550 KM |
362 | } |
363 | ||
364 | static void fsi_irq_disable(struct fsi_priv *fsi, int is_play) | |
365 | { | |
366 | u32 data = fsi_port_ab_io_bit(fsi, is_play); | |
71f6e064 | 367 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 368 | |
73b92c1f KM |
369 | fsi_master_mask_set(master, master->core->imsk, data, 0); |
370 | fsi_master_mask_set(master, master->core->iemsk, data, 0); | |
a4d7d550 KM |
371 | } |
372 | ||
10ea76cc KM |
373 | static u32 fsi_irq_get_status(struct fsi_master *master) |
374 | { | |
73b92c1f | 375 | return fsi_master_read(master, master->core->int_st); |
10ea76cc KM |
376 | } |
377 | ||
378 | static void fsi_irq_clear_all_status(struct fsi_master *master) | |
379 | { | |
73b92c1f | 380 | fsi_master_write(master, master->core->int_st, 0); |
a4d7d550 KM |
381 | } |
382 | ||
10ea76cc KM |
383 | static void fsi_irq_clear_status(struct fsi_priv *fsi) |
384 | { | |
385 | u32 data = 0; | |
386 | struct fsi_master *master = fsi_get_master(fsi); | |
387 | ||
388 | data |= fsi_port_ab_io_bit(fsi, 0); | |
389 | data |= fsi_port_ab_io_bit(fsi, 1); | |
390 | ||
391 | /* clear interrupt factor */ | |
73b92c1f | 392 | fsi_master_mask_set(master, master->core->int_st, data, 0); |
10ea76cc KM |
393 | } |
394 | ||
395 | /************************************************************************ | |
396 | ||
397 | ||
398 | ctrl function | |
399 | ||
400 | ||
401 | ************************************************************************/ | |
a4d7d550 KM |
402 | static void fsi_clk_ctrl(struct fsi_priv *fsi, int enable) |
403 | { | |
404 | u32 val = fsi_is_port_a(fsi) ? (1 << 0) : (1 << 4); | |
71f6e064 | 405 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 KM |
406 | |
407 | if (enable) | |
71f6e064 | 408 | fsi_master_mask_set(master, CLK_RST, val, val); |
a4d7d550 | 409 | else |
71f6e064 | 410 | fsi_master_mask_set(master, CLK_RST, val, 0); |
a4d7d550 KM |
411 | } |
412 | ||
4a942b45 KM |
413 | static void fsi_fifo_init(struct fsi_priv *fsi, |
414 | int is_play, | |
415 | struct snd_soc_dai *dai) | |
a4d7d550 | 416 | { |
4a942b45 KM |
417 | struct fsi_master *master = fsi_get_master(fsi); |
418 | u32 ctrl, shift, i; | |
a4d7d550 | 419 | |
4a942b45 KM |
420 | /* get on-chip RAM capacity */ |
421 | shift = fsi_master_read(master, FIFO_SZ); | |
422 | shift >>= fsi_is_port_a(fsi) ? AO_SZ_SHIFT : BO_SZ_SHIFT; | |
423 | shift &= OUT_SZ_MASK; | |
424 | fsi->fifo_max = 256 << shift; | |
425 | dev_dbg(dai->dev, "fifo = %d words\n", fsi->fifo_max); | |
a4d7d550 | 426 | |
4a942b45 KM |
427 | /* |
428 | * The maximum number of sample data varies depending | |
429 | * on the number of channels selected for the format. | |
430 | * | |
431 | * FIFOs are used in 4-channel units in 3-channel mode | |
432 | * and in 8-channel units in 5- to 7-channel mode | |
433 | * meaning that more FIFOs than the required size of DPRAM | |
434 | * are used. | |
435 | * | |
436 | * ex) if 256 words of DP-RAM is connected | |
437 | * 1 channel: 256 (256 x 1 = 256) | |
438 | * 2 channels: 128 (128 x 2 = 256) | |
439 | * 3 channels: 64 ( 64 x 3 = 192) | |
440 | * 4 channels: 64 ( 64 x 4 = 256) | |
441 | * 5 channels: 32 ( 32 x 5 = 160) | |
442 | * 6 channels: 32 ( 32 x 6 = 192) | |
443 | * 7 channels: 32 ( 32 x 7 = 224) | |
444 | * 8 channels: 32 ( 32 x 8 = 256) | |
445 | */ | |
446 | for (i = 1; i < fsi->chan; i <<= 1) | |
447 | fsi->fifo_max >>= 1; | |
448 | dev_dbg(dai->dev, "%d channel %d store\n", fsi->chan, fsi->fifo_max); | |
a4d7d550 | 449 | |
a4d7d550 | 450 | ctrl = is_play ? DOFF_CTL : DIFF_CTL; |
a4d7d550 KM |
451 | |
452 | /* set interrupt generation factor */ | |
453 | fsi_reg_write(fsi, ctrl, IRQ_HALF); | |
454 | ||
455 | /* clear FIFO */ | |
456 | fsi_reg_mask_set(fsi, ctrl, FIFO_CLR, FIFO_CLR); | |
a4d7d550 KM |
457 | } |
458 | ||
71f6e064 | 459 | static void fsi_soft_all_reset(struct fsi_master *master) |
a4d7d550 | 460 | { |
a4d7d550 | 461 | /* port AB reset */ |
feb58cff | 462 | fsi_master_mask_set(master, SOFT_RST, PASR | PBSR, 0); |
a4d7d550 KM |
463 | mdelay(10); |
464 | ||
465 | /* soft reset */ | |
feb58cff KM |
466 | fsi_master_mask_set(master, SOFT_RST, FSISR, 0); |
467 | fsi_master_mask_set(master, SOFT_RST, FSISR, FSISR); | |
a4d7d550 KM |
468 | mdelay(10); |
469 | } | |
470 | ||
a4d7d550 | 471 | /* playback interrupt */ |
47fc9a0a | 472 | static int fsi_data_push(struct fsi_priv *fsi, int startup) |
a4d7d550 KM |
473 | { |
474 | struct snd_pcm_runtime *runtime; | |
475 | struct snd_pcm_substream *substream = NULL; | |
59c3b003 | 476 | u32 status; |
a4d7d550 KM |
477 | int send; |
478 | int fifo_free; | |
479 | int width; | |
9ddc9aa9 | 480 | u8 *start; |
47fc9a0a | 481 | int i, over_period; |
a4d7d550 KM |
482 | |
483 | if (!fsi || | |
484 | !fsi->substream || | |
485 | !fsi->substream->runtime) | |
486 | return -EINVAL; | |
487 | ||
1c418d1f KM |
488 | over_period = 0; |
489 | substream = fsi->substream; | |
490 | runtime = substream->runtime; | |
a4d7d550 KM |
491 | |
492 | /* FSI FIFO has limit. | |
493 | * So, this driver can not send periods data at a time | |
494 | */ | |
495 | if (fsi->byte_offset >= | |
496 | fsi->period_len * (fsi->periods + 1)) { | |
497 | ||
1c418d1f | 498 | over_period = 1; |
a4d7d550 KM |
499 | fsi->periods = (fsi->periods + 1) % runtime->periods; |
500 | ||
501 | if (0 == fsi->periods) | |
502 | fsi->byte_offset = 0; | |
503 | } | |
504 | ||
505 | /* get 1 channel data width */ | |
506 | width = frames_to_bytes(runtime, 1) / fsi->chan; | |
507 | ||
508 | /* get send size for alsa */ | |
509 | send = (fsi->buffer_len - fsi->byte_offset) / width; | |
510 | ||
511 | /* get FIFO free size */ | |
512 | fifo_free = (fsi->fifo_max * fsi->chan) - fsi_get_fifo_residue(fsi, 1); | |
513 | ||
514 | /* size check */ | |
515 | if (fifo_free < send) | |
516 | send = fifo_free; | |
517 | ||
9ddc9aa9 KM |
518 | start = runtime->dma_area; |
519 | start += fsi->byte_offset; | |
520 | ||
521 | switch (width) { | |
522 | case 2: | |
523 | for (i = 0; i < send; i++) | |
524 | fsi_reg_write(fsi, DODT, | |
525 | ((u32)*((u16 *)start + i) << 8)); | |
526 | break; | |
527 | case 4: | |
528 | for (i = 0; i < send; i++) | |
529 | fsi_reg_write(fsi, DODT, *((u32 *)start + i)); | |
530 | break; | |
531 | default: | |
a4d7d550 | 532 | return -EINVAL; |
9ddc9aa9 | 533 | } |
a4d7d550 KM |
534 | |
535 | fsi->byte_offset += send * width; | |
536 | ||
59c3b003 | 537 | status = fsi_reg_read(fsi, DOFF_ST); |
47fc9a0a | 538 | if (!startup) { |
59c3b003 | 539 | struct snd_soc_dai *dai = fsi_get_dai(substream); |
47fc9a0a KM |
540 | |
541 | if (status & ERR_OVER) | |
542 | dev_err(dai->dev, "over run\n"); | |
543 | if (status & ERR_UNDER) | |
544 | dev_err(dai->dev, "under run\n"); | |
59c3b003 | 545 | } |
47fc9a0a | 546 | fsi_reg_write(fsi, DOFF_ST, 0); |
59c3b003 | 547 | |
a4d7d550 KM |
548 | fsi_irq_enable(fsi, 1); |
549 | ||
1c418d1f | 550 | if (over_period) |
a4d7d550 KM |
551 | snd_pcm_period_elapsed(substream); |
552 | ||
47fc9a0a | 553 | return 0; |
a4d7d550 KM |
554 | } |
555 | ||
47fc9a0a | 556 | static int fsi_data_pop(struct fsi_priv *fsi, int startup) |
07102f3c KM |
557 | { |
558 | struct snd_pcm_runtime *runtime; | |
559 | struct snd_pcm_substream *substream = NULL; | |
59c3b003 | 560 | u32 status; |
07102f3c KM |
561 | int free; |
562 | int fifo_fill; | |
563 | int width; | |
564 | u8 *start; | |
47fc9a0a | 565 | int i, over_period; |
07102f3c KM |
566 | |
567 | if (!fsi || | |
568 | !fsi->substream || | |
569 | !fsi->substream->runtime) | |
570 | return -EINVAL; | |
571 | ||
1c418d1f KM |
572 | over_period = 0; |
573 | substream = fsi->substream; | |
574 | runtime = substream->runtime; | |
07102f3c KM |
575 | |
576 | /* FSI FIFO has limit. | |
577 | * So, this driver can not send periods data at a time | |
578 | */ | |
579 | if (fsi->byte_offset >= | |
580 | fsi->period_len * (fsi->periods + 1)) { | |
581 | ||
1c418d1f | 582 | over_period = 1; |
07102f3c KM |
583 | fsi->periods = (fsi->periods + 1) % runtime->periods; |
584 | ||
585 | if (0 == fsi->periods) | |
586 | fsi->byte_offset = 0; | |
587 | } | |
588 | ||
589 | /* get 1 channel data width */ | |
590 | width = frames_to_bytes(runtime, 1) / fsi->chan; | |
591 | ||
592 | /* get free space for alsa */ | |
593 | free = (fsi->buffer_len - fsi->byte_offset) / width; | |
594 | ||
595 | /* get recv size */ | |
596 | fifo_fill = fsi_get_fifo_residue(fsi, 0); | |
597 | ||
598 | if (free < fifo_fill) | |
599 | fifo_fill = free; | |
600 | ||
601 | start = runtime->dma_area; | |
602 | start += fsi->byte_offset; | |
603 | ||
604 | switch (width) { | |
605 | case 2: | |
606 | for (i = 0; i < fifo_fill; i++) | |
607 | *((u16 *)start + i) = | |
608 | (u16)(fsi_reg_read(fsi, DIDT) >> 8); | |
609 | break; | |
610 | case 4: | |
611 | for (i = 0; i < fifo_fill; i++) | |
612 | *((u32 *)start + i) = fsi_reg_read(fsi, DIDT); | |
613 | break; | |
614 | default: | |
615 | return -EINVAL; | |
616 | } | |
617 | ||
618 | fsi->byte_offset += fifo_fill * width; | |
619 | ||
59c3b003 | 620 | status = fsi_reg_read(fsi, DIFF_ST); |
47fc9a0a | 621 | if (!startup) { |
59c3b003 | 622 | struct snd_soc_dai *dai = fsi_get_dai(substream); |
47fc9a0a KM |
623 | |
624 | if (status & ERR_OVER) | |
625 | dev_err(dai->dev, "over run\n"); | |
626 | if (status & ERR_UNDER) | |
627 | dev_err(dai->dev, "under run\n"); | |
59c3b003 | 628 | } |
47fc9a0a | 629 | fsi_reg_write(fsi, DIFF_ST, 0); |
59c3b003 | 630 | |
07102f3c KM |
631 | fsi_irq_enable(fsi, 0); |
632 | ||
1c418d1f | 633 | if (over_period) |
07102f3c KM |
634 | snd_pcm_period_elapsed(substream); |
635 | ||
47fc9a0a | 636 | return 0; |
07102f3c KM |
637 | } |
638 | ||
a4d7d550 KM |
639 | static irqreturn_t fsi_interrupt(int irq, void *data) |
640 | { | |
71f6e064 | 641 | struct fsi_master *master = data; |
10ea76cc | 642 | u32 int_st = fsi_irq_get_status(master); |
a4d7d550 KM |
643 | |
644 | /* clear irq status */ | |
feb58cff KM |
645 | fsi_master_mask_set(master, SOFT_RST, IR, 0); |
646 | fsi_master_mask_set(master, SOFT_RST, IR, IR); | |
a4d7d550 KM |
647 | |
648 | if (int_st & INT_A_OUT) | |
47fc9a0a | 649 | fsi_data_push(&master->fsia, 0); |
a4d7d550 | 650 | if (int_st & INT_B_OUT) |
47fc9a0a | 651 | fsi_data_push(&master->fsib, 0); |
07102f3c | 652 | if (int_st & INT_A_IN) |
47fc9a0a | 653 | fsi_data_pop(&master->fsia, 0); |
07102f3c | 654 | if (int_st & INT_B_IN) |
47fc9a0a | 655 | fsi_data_pop(&master->fsib, 0); |
a4d7d550 | 656 | |
10ea76cc | 657 | fsi_irq_clear_all_status(master); |
a4d7d550 KM |
658 | |
659 | return IRQ_HANDLED; | |
660 | } | |
661 | ||
662 | /************************************************************************ | |
663 | ||
664 | ||
665 | dai ops | |
666 | ||
667 | ||
668 | ************************************************************************/ | |
669 | static int fsi_dai_startup(struct snd_pcm_substream *substream, | |
670 | struct snd_soc_dai *dai) | |
671 | { | |
71f6e064 | 672 | struct fsi_priv *fsi = fsi_get_priv(substream); |
a4d7d550 KM |
673 | u32 flags = fsi_get_info_flags(fsi); |
674 | u32 fmt; | |
675 | u32 reg; | |
676 | u32 data; | |
677 | int is_play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); | |
678 | int is_master; | |
679 | int ret = 0; | |
680 | ||
785d1c45 | 681 | pm_runtime_get_sync(dai->dev); |
a4d7d550 KM |
682 | |
683 | /* CKG1 */ | |
684 | data = is_play ? (1 << 0) : (1 << 4); | |
685 | is_master = fsi_is_master_mode(fsi, is_play); | |
686 | if (is_master) | |
687 | fsi_reg_mask_set(fsi, CKG1, data, data); | |
688 | else | |
689 | fsi_reg_mask_set(fsi, CKG1, data, 0); | |
690 | ||
691 | /* clock inversion (CKG2) */ | |
692 | data = 0; | |
b427b44c KM |
693 | if (SH_FSI_LRM_INV & flags) |
694 | data |= 1 << 12; | |
695 | if (SH_FSI_BRM_INV & flags) | |
696 | data |= 1 << 8; | |
697 | if (SH_FSI_LRS_INV & flags) | |
698 | data |= 1 << 4; | |
699 | if (SH_FSI_BRS_INV & flags) | |
700 | data |= 1 << 0; | |
701 | ||
a4d7d550 KM |
702 | fsi_reg_write(fsi, CKG2, data); |
703 | ||
704 | /* do fmt, di fmt */ | |
705 | data = 0; | |
706 | reg = is_play ? DO_FMT : DI_FMT; | |
707 | fmt = is_play ? SH_FSI_GET_OFMT(flags) : SH_FSI_GET_IFMT(flags); | |
708 | switch (fmt) { | |
709 | case SH_FSI_FMT_MONO: | |
a7ffb52b | 710 | data = CR_MONO; |
a4d7d550 KM |
711 | fsi->chan = 1; |
712 | break; | |
713 | case SH_FSI_FMT_MONO_DELAY: | |
a7ffb52b | 714 | data = CR_MONO_D; |
a4d7d550 KM |
715 | fsi->chan = 1; |
716 | break; | |
717 | case SH_FSI_FMT_PCM: | |
a7ffb52b | 718 | data = CR_PCM; |
a4d7d550 KM |
719 | fsi->chan = 2; |
720 | break; | |
721 | case SH_FSI_FMT_I2S: | |
a7ffb52b | 722 | data = CR_I2S; |
a4d7d550 KM |
723 | fsi->chan = 2; |
724 | break; | |
725 | case SH_FSI_FMT_TDM: | |
a4d7d550 KM |
726 | fsi->chan = is_play ? |
727 | SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags); | |
a7ffb52b | 728 | data = CR_TDM | (fsi->chan - 1); |
a4d7d550 KM |
729 | break; |
730 | case SH_FSI_FMT_TDM_DELAY: | |
a4d7d550 KM |
731 | fsi->chan = is_play ? |
732 | SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags); | |
a7ffb52b | 733 | data = CR_TDM_D | (fsi->chan - 1); |
a4d7d550 KM |
734 | break; |
735 | default: | |
736 | dev_err(dai->dev, "unknown format.\n"); | |
737 | return -EINVAL; | |
738 | } | |
a4d7d550 | 739 | fsi_reg_write(fsi, reg, data); |
a4d7d550 | 740 | |
10ea76cc KM |
741 | /* irq clear */ |
742 | fsi_irq_disable(fsi, is_play); | |
743 | fsi_irq_clear_status(fsi); | |
744 | ||
745 | /* fifo init */ | |
4a942b45 | 746 | fsi_fifo_init(fsi, is_play, dai); |
a4d7d550 KM |
747 | |
748 | return ret; | |
749 | } | |
750 | ||
751 | static void fsi_dai_shutdown(struct snd_pcm_substream *substream, | |
752 | struct snd_soc_dai *dai) | |
753 | { | |
71f6e064 | 754 | struct fsi_priv *fsi = fsi_get_priv(substream); |
a4d7d550 KM |
755 | int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
756 | ||
757 | fsi_irq_disable(fsi, is_play); | |
758 | fsi_clk_ctrl(fsi, 0); | |
759 | ||
785d1c45 | 760 | pm_runtime_put_sync(dai->dev); |
a4d7d550 KM |
761 | } |
762 | ||
763 | static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd, | |
764 | struct snd_soc_dai *dai) | |
765 | { | |
71f6e064 | 766 | struct fsi_priv *fsi = fsi_get_priv(substream); |
a4d7d550 KM |
767 | struct snd_pcm_runtime *runtime = substream->runtime; |
768 | int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; | |
769 | int ret = 0; | |
770 | ||
a4d7d550 KM |
771 | switch (cmd) { |
772 | case SNDRV_PCM_TRIGGER_START: | |
773 | fsi_stream_push(fsi, substream, | |
774 | frames_to_bytes(runtime, runtime->buffer_size), | |
775 | frames_to_bytes(runtime, runtime->period_size)); | |
47fc9a0a | 776 | ret = is_play ? fsi_data_push(fsi, 1) : fsi_data_pop(fsi, 1); |
a4d7d550 KM |
777 | break; |
778 | case SNDRV_PCM_TRIGGER_STOP: | |
779 | fsi_irq_disable(fsi, is_play); | |
780 | fsi_stream_pop(fsi); | |
781 | break; | |
782 | } | |
783 | ||
784 | return ret; | |
785 | } | |
786 | ||
ccad7b44 KM |
787 | static int fsi_dai_hw_params(struct snd_pcm_substream *substream, |
788 | struct snd_pcm_hw_params *params, | |
789 | struct snd_soc_dai *dai) | |
790 | { | |
791 | struct fsi_priv *fsi = fsi_get_priv(substream); | |
792 | struct fsi_master *master = fsi_get_master(fsi); | |
793 | int (*set_rate)(int is_porta, int rate) = master->info->set_rate; | |
794 | int fsi_ver = master->core->ver; | |
795 | int is_play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); | |
796 | int ret; | |
797 | ||
798 | /* if slave mode, set_rate is not needed */ | |
799 | if (!fsi_is_master_mode(fsi, is_play)) | |
800 | return 0; | |
801 | ||
802 | /* it is error if no set_rate */ | |
803 | if (!set_rate) | |
804 | return -EIO; | |
805 | ||
806 | /* clock stop */ | |
807 | pm_runtime_put_sync(dai->dev); | |
808 | fsi_clk_ctrl(fsi, 0); | |
809 | ||
810 | ret = set_rate(fsi_is_port_a(fsi), params_rate(params)); | |
811 | if (ret > 0) { | |
812 | u32 data = 0; | |
813 | ||
814 | switch (ret & SH_FSI_ACKMD_MASK) { | |
815 | default: | |
816 | /* FALL THROUGH */ | |
817 | case SH_FSI_ACKMD_512: | |
818 | data |= (0x0 << 12); | |
819 | break; | |
820 | case SH_FSI_ACKMD_256: | |
821 | data |= (0x1 << 12); | |
822 | break; | |
823 | case SH_FSI_ACKMD_128: | |
824 | data |= (0x2 << 12); | |
825 | break; | |
826 | case SH_FSI_ACKMD_64: | |
827 | data |= (0x3 << 12); | |
828 | break; | |
829 | case SH_FSI_ACKMD_32: | |
830 | if (fsi_ver < 2) | |
831 | dev_err(dai->dev, "unsupported ACKMD\n"); | |
832 | else | |
833 | data |= (0x4 << 12); | |
834 | break; | |
835 | } | |
836 | ||
837 | switch (ret & SH_FSI_BPFMD_MASK) { | |
838 | default: | |
839 | /* FALL THROUGH */ | |
840 | case SH_FSI_BPFMD_32: | |
841 | data |= (0x0 << 8); | |
842 | break; | |
843 | case SH_FSI_BPFMD_64: | |
844 | data |= (0x1 << 8); | |
845 | break; | |
846 | case SH_FSI_BPFMD_128: | |
847 | data |= (0x2 << 8); | |
848 | break; | |
849 | case SH_FSI_BPFMD_256: | |
850 | data |= (0x3 << 8); | |
851 | break; | |
852 | case SH_FSI_BPFMD_512: | |
853 | data |= (0x4 << 8); | |
854 | break; | |
855 | case SH_FSI_BPFMD_16: | |
856 | if (fsi_ver < 2) | |
857 | dev_err(dai->dev, "unsupported ACKMD\n"); | |
858 | else | |
859 | data |= (0x7 << 8); | |
860 | break; | |
861 | } | |
862 | ||
863 | fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data); | |
864 | udelay(10); | |
865 | fsi_clk_ctrl(fsi, 1); | |
866 | ret = 0; | |
867 | } | |
868 | pm_runtime_get_sync(dai->dev); | |
869 | ||
870 | return ret; | |
871 | ||
872 | } | |
873 | ||
a4d7d550 KM |
874 | static struct snd_soc_dai_ops fsi_dai_ops = { |
875 | .startup = fsi_dai_startup, | |
876 | .shutdown = fsi_dai_shutdown, | |
877 | .trigger = fsi_dai_trigger, | |
ccad7b44 | 878 | .hw_params = fsi_dai_hw_params, |
a4d7d550 KM |
879 | }; |
880 | ||
881 | /************************************************************************ | |
882 | ||
883 | ||
884 | pcm ops | |
885 | ||
886 | ||
887 | ************************************************************************/ | |
888 | static struct snd_pcm_hardware fsi_pcm_hardware = { | |
889 | .info = SNDRV_PCM_INFO_INTERLEAVED | | |
890 | SNDRV_PCM_INFO_MMAP | | |
891 | SNDRV_PCM_INFO_MMAP_VALID | | |
892 | SNDRV_PCM_INFO_PAUSE, | |
893 | .formats = FSI_FMTS, | |
894 | .rates = FSI_RATES, | |
895 | .rate_min = 8000, | |
896 | .rate_max = 192000, | |
897 | .channels_min = 1, | |
898 | .channels_max = 2, | |
899 | .buffer_bytes_max = 64 * 1024, | |
900 | .period_bytes_min = 32, | |
901 | .period_bytes_max = 8192, | |
902 | .periods_min = 1, | |
903 | .periods_max = 32, | |
904 | .fifo_size = 256, | |
905 | }; | |
906 | ||
907 | static int fsi_pcm_open(struct snd_pcm_substream *substream) | |
908 | { | |
909 | struct snd_pcm_runtime *runtime = substream->runtime; | |
910 | int ret = 0; | |
911 | ||
912 | snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware); | |
913 | ||
914 | ret = snd_pcm_hw_constraint_integer(runtime, | |
915 | SNDRV_PCM_HW_PARAM_PERIODS); | |
916 | ||
917 | return ret; | |
918 | } | |
919 | ||
920 | static int fsi_hw_params(struct snd_pcm_substream *substream, | |
921 | struct snd_pcm_hw_params *hw_params) | |
922 | { | |
923 | return snd_pcm_lib_malloc_pages(substream, | |
924 | params_buffer_bytes(hw_params)); | |
925 | } | |
926 | ||
927 | static int fsi_hw_free(struct snd_pcm_substream *substream) | |
928 | { | |
929 | return snd_pcm_lib_free_pages(substream); | |
930 | } | |
931 | ||
932 | static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream) | |
933 | { | |
934 | struct snd_pcm_runtime *runtime = substream->runtime; | |
71f6e064 | 935 | struct fsi_priv *fsi = fsi_get_priv(substream); |
a4d7d550 KM |
936 | long location; |
937 | ||
9ddc9aa9 | 938 | location = (fsi->byte_offset - 1); |
a4d7d550 KM |
939 | if (location < 0) |
940 | location = 0; | |
941 | ||
942 | return bytes_to_frames(runtime, location); | |
943 | } | |
944 | ||
945 | static struct snd_pcm_ops fsi_pcm_ops = { | |
946 | .open = fsi_pcm_open, | |
947 | .ioctl = snd_pcm_lib_ioctl, | |
948 | .hw_params = fsi_hw_params, | |
949 | .hw_free = fsi_hw_free, | |
950 | .pointer = fsi_pointer, | |
951 | }; | |
952 | ||
953 | /************************************************************************ | |
954 | ||
955 | ||
956 | snd_soc_platform | |
957 | ||
958 | ||
959 | ************************************************************************/ | |
960 | #define PREALLOC_BUFFER (32 * 1024) | |
961 | #define PREALLOC_BUFFER_MAX (32 * 1024) | |
962 | ||
963 | static void fsi_pcm_free(struct snd_pcm *pcm) | |
964 | { | |
965 | snd_pcm_lib_preallocate_free_for_all(pcm); | |
966 | } | |
967 | ||
968 | static int fsi_pcm_new(struct snd_card *card, | |
969 | struct snd_soc_dai *dai, | |
970 | struct snd_pcm *pcm) | |
971 | { | |
972 | /* | |
973 | * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel | |
974 | * in MMAP mode (i.e. aplay -M) | |
975 | */ | |
976 | return snd_pcm_lib_preallocate_pages_for_all( | |
977 | pcm, | |
978 | SNDRV_DMA_TYPE_CONTINUOUS, | |
979 | snd_dma_continuous_data(GFP_KERNEL), | |
980 | PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); | |
981 | } | |
982 | ||
983 | /************************************************************************ | |
984 | ||
985 | ||
986 | alsa struct | |
987 | ||
988 | ||
989 | ************************************************************************/ | |
990 | struct snd_soc_dai fsi_soc_dai[] = { | |
991 | { | |
992 | .name = "FSIA", | |
993 | .id = 0, | |
994 | .playback = { | |
995 | .rates = FSI_RATES, | |
996 | .formats = FSI_FMTS, | |
997 | .channels_min = 1, | |
998 | .channels_max = 8, | |
999 | }, | |
07102f3c KM |
1000 | .capture = { |
1001 | .rates = FSI_RATES, | |
1002 | .formats = FSI_FMTS, | |
1003 | .channels_min = 1, | |
1004 | .channels_max = 8, | |
1005 | }, | |
a4d7d550 KM |
1006 | .ops = &fsi_dai_ops, |
1007 | }, | |
1008 | { | |
1009 | .name = "FSIB", | |
1010 | .id = 1, | |
1011 | .playback = { | |
1012 | .rates = FSI_RATES, | |
1013 | .formats = FSI_FMTS, | |
1014 | .channels_min = 1, | |
1015 | .channels_max = 8, | |
1016 | }, | |
07102f3c KM |
1017 | .capture = { |
1018 | .rates = FSI_RATES, | |
1019 | .formats = FSI_FMTS, | |
1020 | .channels_min = 1, | |
1021 | .channels_max = 8, | |
1022 | }, | |
a4d7d550 KM |
1023 | .ops = &fsi_dai_ops, |
1024 | }, | |
1025 | }; | |
1026 | EXPORT_SYMBOL_GPL(fsi_soc_dai); | |
1027 | ||
1028 | struct snd_soc_platform fsi_soc_platform = { | |
1029 | .name = "fsi-pcm", | |
1030 | .pcm_ops = &fsi_pcm_ops, | |
1031 | .pcm_new = fsi_pcm_new, | |
1032 | .pcm_free = fsi_pcm_free, | |
1033 | }; | |
1034 | EXPORT_SYMBOL_GPL(fsi_soc_platform); | |
1035 | ||
1036 | /************************************************************************ | |
1037 | ||
1038 | ||
1039 | platform function | |
1040 | ||
1041 | ||
1042 | ************************************************************************/ | |
1043 | static int fsi_probe(struct platform_device *pdev) | |
1044 | { | |
71f6e064 | 1045 | struct fsi_master *master; |
cc780d38 | 1046 | const struct platform_device_id *id_entry; |
a4d7d550 | 1047 | struct resource *res; |
a4d7d550 KM |
1048 | unsigned int irq; |
1049 | int ret; | |
1050 | ||
71f6e064 KM |
1051 | if (0 != pdev->id) { |
1052 | dev_err(&pdev->dev, "current fsi support id 0 only now\n"); | |
1053 | return -ENODEV; | |
1054 | } | |
1055 | ||
cc780d38 KM |
1056 | id_entry = pdev->id_entry; |
1057 | if (!id_entry) { | |
1058 | dev_err(&pdev->dev, "unknown fsi device\n"); | |
1059 | return -ENODEV; | |
1060 | } | |
1061 | ||
a4d7d550 KM |
1062 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1063 | irq = platform_get_irq(pdev, 0); | |
b6aa1793 | 1064 | if (!res || (int)irq <= 0) { |
a4d7d550 KM |
1065 | dev_err(&pdev->dev, "Not enough FSI platform resources.\n"); |
1066 | ret = -ENODEV; | |
1067 | goto exit; | |
1068 | } | |
1069 | ||
1070 | master = kzalloc(sizeof(*master), GFP_KERNEL); | |
1071 | if (!master) { | |
1072 | dev_err(&pdev->dev, "Could not allocate master\n"); | |
1073 | ret = -ENOMEM; | |
1074 | goto exit; | |
1075 | } | |
1076 | ||
1077 | master->base = ioremap_nocache(res->start, resource_size(res)); | |
1078 | if (!master->base) { | |
1079 | ret = -ENXIO; | |
1080 | dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n"); | |
1081 | goto exit_kfree; | |
1082 | } | |
1083 | ||
1084 | master->irq = irq; | |
1085 | master->info = pdev->dev.platform_data; | |
1086 | master->fsia.base = master->base; | |
71f6e064 | 1087 | master->fsia.master = master; |
a4d7d550 | 1088 | master->fsib.base = master->base + 0x40; |
71f6e064 | 1089 | master->fsib.master = master; |
73b92c1f | 1090 | master->core = (struct fsi_core *)id_entry->driver_data; |
8fc176d5 | 1091 | spin_lock_init(&master->lock); |
a4d7d550 | 1092 | |
785d1c45 KM |
1093 | pm_runtime_enable(&pdev->dev); |
1094 | pm_runtime_resume(&pdev->dev); | |
a4d7d550 KM |
1095 | |
1096 | fsi_soc_dai[0].dev = &pdev->dev; | |
71f6e064 | 1097 | fsi_soc_dai[0].private_data = &master->fsia; |
a4d7d550 | 1098 | fsi_soc_dai[1].dev = &pdev->dev; |
71f6e064 | 1099 | fsi_soc_dai[1].private_data = &master->fsib; |
a4d7d550 | 1100 | |
71f6e064 | 1101 | fsi_soft_all_reset(master); |
a4d7d550 | 1102 | |
cc780d38 KM |
1103 | ret = request_irq(irq, &fsi_interrupt, IRQF_DISABLED, |
1104 | id_entry->name, master); | |
a4d7d550 KM |
1105 | if (ret) { |
1106 | dev_err(&pdev->dev, "irq request err\n"); | |
9ddc9aa9 | 1107 | goto exit_iounmap; |
a4d7d550 KM |
1108 | } |
1109 | ||
1110 | ret = snd_soc_register_platform(&fsi_soc_platform); | |
1111 | if (ret < 0) { | |
1112 | dev_err(&pdev->dev, "cannot snd soc register\n"); | |
1113 | goto exit_free_irq; | |
1114 | } | |
1115 | ||
1116 | return snd_soc_register_dais(fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai)); | |
1117 | ||
1118 | exit_free_irq: | |
1119 | free_irq(irq, master); | |
a4d7d550 KM |
1120 | exit_iounmap: |
1121 | iounmap(master->base); | |
785d1c45 | 1122 | pm_runtime_disable(&pdev->dev); |
a4d7d550 KM |
1123 | exit_kfree: |
1124 | kfree(master); | |
1125 | master = NULL; | |
1126 | exit: | |
1127 | return ret; | |
1128 | } | |
1129 | ||
1130 | static int fsi_remove(struct platform_device *pdev) | |
1131 | { | |
71f6e064 KM |
1132 | struct fsi_master *master; |
1133 | ||
1134 | master = fsi_get_master(fsi_soc_dai[0].private_data); | |
1135 | ||
a4d7d550 KM |
1136 | snd_soc_unregister_dais(fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai)); |
1137 | snd_soc_unregister_platform(&fsi_soc_platform); | |
1138 | ||
785d1c45 | 1139 | pm_runtime_disable(&pdev->dev); |
a4d7d550 | 1140 | |
a4d7d550 KM |
1141 | free_irq(master->irq, master); |
1142 | ||
1143 | iounmap(master->base); | |
1144 | kfree(master); | |
71f6e064 KM |
1145 | |
1146 | fsi_soc_dai[0].dev = NULL; | |
1147 | fsi_soc_dai[0].private_data = NULL; | |
1148 | fsi_soc_dai[1].dev = NULL; | |
1149 | fsi_soc_dai[1].private_data = NULL; | |
1150 | ||
a4d7d550 KM |
1151 | return 0; |
1152 | } | |
1153 | ||
785d1c45 KM |
1154 | static int fsi_runtime_nop(struct device *dev) |
1155 | { | |
1156 | /* Runtime PM callback shared between ->runtime_suspend() | |
1157 | * and ->runtime_resume(). Simply returns success. | |
1158 | * | |
1159 | * This driver re-initializes all registers after | |
1160 | * pm_runtime_get_sync() anyway so there is no need | |
1161 | * to save and restore registers here. | |
1162 | */ | |
1163 | return 0; | |
1164 | } | |
1165 | ||
1166 | static struct dev_pm_ops fsi_pm_ops = { | |
1167 | .runtime_suspend = fsi_runtime_nop, | |
1168 | .runtime_resume = fsi_runtime_nop, | |
1169 | }; | |
1170 | ||
73b92c1f KM |
1171 | static struct fsi_core fsi1_core = { |
1172 | .ver = 1, | |
1173 | ||
1174 | /* Interrupt */ | |
cc780d38 KM |
1175 | .int_st = INT_ST, |
1176 | .iemsk = IEMSK, | |
1177 | .imsk = IMSK, | |
1178 | }; | |
1179 | ||
73b92c1f KM |
1180 | static struct fsi_core fsi2_core = { |
1181 | .ver = 2, | |
1182 | ||
1183 | /* Interrupt */ | |
cc780d38 KM |
1184 | .int_st = CPU_INT_ST, |
1185 | .iemsk = CPU_IEMSK, | |
1186 | .imsk = CPU_IMSK, | |
1187 | }; | |
1188 | ||
1189 | static struct platform_device_id fsi_id_table[] = { | |
73b92c1f KM |
1190 | { "sh_fsi", (kernel_ulong_t)&fsi1_core }, |
1191 | { "sh_fsi2", (kernel_ulong_t)&fsi2_core }, | |
cc780d38 KM |
1192 | }; |
1193 | ||
a4d7d550 KM |
1194 | static struct platform_driver fsi_driver = { |
1195 | .driver = { | |
1196 | .name = "sh_fsi", | |
785d1c45 | 1197 | .pm = &fsi_pm_ops, |
a4d7d550 KM |
1198 | }, |
1199 | .probe = fsi_probe, | |
1200 | .remove = fsi_remove, | |
cc780d38 | 1201 | .id_table = fsi_id_table, |
a4d7d550 KM |
1202 | }; |
1203 | ||
1204 | static int __init fsi_mobile_init(void) | |
1205 | { | |
1206 | return platform_driver_register(&fsi_driver); | |
1207 | } | |
1208 | ||
1209 | static void __exit fsi_mobile_exit(void) | |
1210 | { | |
1211 | platform_driver_unregister(&fsi_driver); | |
1212 | } | |
1213 | module_init(fsi_mobile_init); | |
1214 | module_exit(fsi_mobile_exit); | |
1215 | ||
1216 | MODULE_LICENSE("GPL"); | |
1217 | MODULE_DESCRIPTION("SuperH onchip FSI audio driver"); | |
1218 | MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>"); |