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a4d7d550 KM |
1 | /* |
2 | * Fifo-attached Serial Interface (FSI) support for SH7724 | |
3 | * | |
4 | * Copyright (C) 2009 Renesas Solutions Corp. | |
5 | * Kuninori Morimoto <morimoto.kuninori@renesas.com> | |
6 | * | |
7 | * Based on ssi.c | |
8 | * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include <linux/init.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/list.h> | |
785d1c45 | 20 | #include <linux/pm_runtime.h> |
a4d7d550 KM |
21 | #include <linux/io.h> |
22 | #include <sound/core.h> | |
23 | #include <sound/pcm.h> | |
24 | #include <sound/initval.h> | |
25 | #include <sound/soc.h> | |
26 | #include <sound/pcm_params.h> | |
27 | #include <sound/sh_fsi.h> | |
28 | #include <asm/atomic.h> | |
a4d7d550 KM |
29 | |
30 | #define DO_FMT 0x0000 | |
31 | #define DOFF_CTL 0x0004 | |
32 | #define DOFF_ST 0x0008 | |
33 | #define DI_FMT 0x000C | |
34 | #define DIFF_CTL 0x0010 | |
35 | #define DIFF_ST 0x0014 | |
36 | #define CKG1 0x0018 | |
37 | #define CKG2 0x001C | |
38 | #define DIDT 0x0020 | |
39 | #define DODT 0x0024 | |
40 | #define MUTE_ST 0x0028 | |
41 | #define REG_END MUTE_ST | |
42 | ||
43 | #define INT_ST 0x0200 | |
44 | #define IEMSK 0x0204 | |
45 | #define IMSK 0x0208 | |
46 | #define MUTE 0x020C | |
47 | #define CLK_RST 0x0210 | |
48 | #define SOFT_RST 0x0214 | |
49 | #define MREG_START INT_ST | |
50 | #define MREG_END SOFT_RST | |
51 | ||
52 | /* DO_FMT */ | |
53 | /* DI_FMT */ | |
54 | #define CR_FMT(param) ((param) << 4) | |
55 | # define CR_MONO 0x0 | |
56 | # define CR_MONO_D 0x1 | |
57 | # define CR_PCM 0x2 | |
58 | # define CR_I2S 0x3 | |
59 | # define CR_TDM 0x4 | |
60 | # define CR_TDM_D 0x5 | |
61 | ||
62 | /* DOFF_CTL */ | |
63 | /* DIFF_CTL */ | |
64 | #define IRQ_HALF 0x00100000 | |
65 | #define FIFO_CLR 0x00000001 | |
66 | ||
67 | /* DOFF_ST */ | |
68 | #define ERR_OVER 0x00000010 | |
69 | #define ERR_UNDER 0x00000001 | |
59c3b003 | 70 | #define ST_ERR (ERR_OVER | ERR_UNDER) |
a4d7d550 KM |
71 | |
72 | /* CLK_RST */ | |
73 | #define B_CLK 0x00000010 | |
74 | #define A_CLK 0x00000001 | |
75 | ||
76 | /* INT_ST */ | |
77 | #define INT_B_IN (1 << 12) | |
78 | #define INT_B_OUT (1 << 8) | |
79 | #define INT_A_IN (1 << 4) | |
80 | #define INT_A_OUT (1 << 0) | |
81 | ||
82 | #define FSI_RATES SNDRV_PCM_RATE_8000_96000 | |
83 | ||
84 | #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE) | |
85 | ||
86 | /************************************************************************ | |
87 | ||
88 | ||
89 | struct | |
90 | ||
91 | ||
92 | ************************************************************************/ | |
93 | struct fsi_priv { | |
94 | void __iomem *base; | |
95 | struct snd_pcm_substream *substream; | |
71f6e064 | 96 | struct fsi_master *master; |
a4d7d550 KM |
97 | |
98 | int fifo_max; | |
99 | int chan; | |
a4d7d550 KM |
100 | |
101 | int byte_offset; | |
102 | int period_len; | |
103 | int buffer_len; | |
104 | int periods; | |
105 | }; | |
106 | ||
107 | struct fsi_master { | |
108 | void __iomem *base; | |
109 | int irq; | |
a4d7d550 KM |
110 | struct fsi_priv fsia; |
111 | struct fsi_priv fsib; | |
112 | struct sh_fsi_platform_info *info; | |
8fc176d5 | 113 | spinlock_t lock; |
a4d7d550 KM |
114 | }; |
115 | ||
a4d7d550 KM |
116 | /************************************************************************ |
117 | ||
118 | ||
119 | basic read write function | |
120 | ||
121 | ||
122 | ************************************************************************/ | |
0f69d978 | 123 | static void __fsi_reg_write(u32 reg, u32 data) |
a4d7d550 KM |
124 | { |
125 | /* valid data area is 24bit */ | |
126 | data &= 0x00ffffff; | |
127 | ||
0f69d978 | 128 | __raw_writel(data, reg); |
a4d7d550 KM |
129 | } |
130 | ||
131 | static u32 __fsi_reg_read(u32 reg) | |
132 | { | |
0f69d978 | 133 | return __raw_readl(reg); |
a4d7d550 KM |
134 | } |
135 | ||
0f69d978 | 136 | static void __fsi_reg_mask_set(u32 reg, u32 mask, u32 data) |
a4d7d550 KM |
137 | { |
138 | u32 val = __fsi_reg_read(reg); | |
139 | ||
140 | val &= ~mask; | |
141 | val |= data & mask; | |
142 | ||
0f69d978 | 143 | __fsi_reg_write(reg, val); |
a4d7d550 KM |
144 | } |
145 | ||
0f69d978 | 146 | static void fsi_reg_write(struct fsi_priv *fsi, u32 reg, u32 data) |
a4d7d550 KM |
147 | { |
148 | if (reg > REG_END) | |
0f69d978 | 149 | return; |
a4d7d550 | 150 | |
0f69d978 | 151 | __fsi_reg_write((u32)(fsi->base + reg), data); |
a4d7d550 KM |
152 | } |
153 | ||
154 | static u32 fsi_reg_read(struct fsi_priv *fsi, u32 reg) | |
155 | { | |
156 | if (reg > REG_END) | |
157 | return 0; | |
158 | ||
159 | return __fsi_reg_read((u32)(fsi->base + reg)); | |
160 | } | |
161 | ||
0f69d978 | 162 | static void fsi_reg_mask_set(struct fsi_priv *fsi, u32 reg, u32 mask, u32 data) |
a4d7d550 KM |
163 | { |
164 | if (reg > REG_END) | |
0f69d978 | 165 | return; |
a4d7d550 | 166 | |
0f69d978 | 167 | __fsi_reg_mask_set((u32)(fsi->base + reg), mask, data); |
a4d7d550 KM |
168 | } |
169 | ||
0f69d978 | 170 | static void fsi_master_write(struct fsi_master *master, u32 reg, u32 data) |
a4d7d550 | 171 | { |
8fc176d5 KM |
172 | unsigned long flags; |
173 | ||
a4d7d550 KM |
174 | if ((reg < MREG_START) || |
175 | (reg > MREG_END)) | |
0f69d978 | 176 | return; |
a4d7d550 | 177 | |
8fc176d5 | 178 | spin_lock_irqsave(&master->lock, flags); |
0f69d978 | 179 | __fsi_reg_write((u32)(master->base + reg), data); |
8fc176d5 | 180 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
181 | } |
182 | ||
71f6e064 | 183 | static u32 fsi_master_read(struct fsi_master *master, u32 reg) |
a4d7d550 | 184 | { |
8fc176d5 KM |
185 | u32 ret; |
186 | unsigned long flags; | |
187 | ||
a4d7d550 KM |
188 | if ((reg < MREG_START) || |
189 | (reg > MREG_END)) | |
190 | return 0; | |
191 | ||
8fc176d5 KM |
192 | spin_lock_irqsave(&master->lock, flags); |
193 | ret = __fsi_reg_read((u32)(master->base + reg)); | |
194 | spin_unlock_irqrestore(&master->lock, flags); | |
195 | ||
196 | return ret; | |
a4d7d550 KM |
197 | } |
198 | ||
0f69d978 | 199 | static void fsi_master_mask_set(struct fsi_master *master, |
71f6e064 | 200 | u32 reg, u32 mask, u32 data) |
a4d7d550 | 201 | { |
8fc176d5 KM |
202 | unsigned long flags; |
203 | ||
a4d7d550 KM |
204 | if ((reg < MREG_START) || |
205 | (reg > MREG_END)) | |
0f69d978 | 206 | return; |
a4d7d550 | 207 | |
8fc176d5 | 208 | spin_lock_irqsave(&master->lock, flags); |
0f69d978 | 209 | __fsi_reg_mask_set((u32)(master->base + reg), mask, data); |
8fc176d5 | 210 | spin_unlock_irqrestore(&master->lock, flags); |
a4d7d550 KM |
211 | } |
212 | ||
213 | /************************************************************************ | |
214 | ||
215 | ||
216 | basic function | |
217 | ||
218 | ||
219 | ************************************************************************/ | |
71f6e064 | 220 | static struct fsi_master *fsi_get_master(struct fsi_priv *fsi) |
a4d7d550 | 221 | { |
71f6e064 | 222 | return fsi->master; |
a4d7d550 KM |
223 | } |
224 | ||
225 | static int fsi_is_port_a(struct fsi_priv *fsi) | |
226 | { | |
71f6e064 KM |
227 | return fsi->master->base == fsi->base; |
228 | } | |
a4d7d550 | 229 | |
142e8174 | 230 | static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream) |
71f6e064 KM |
231 | { |
232 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
233 | struct snd_soc_dai_link *machine = rtd->dai; | |
142e8174 KM |
234 | |
235 | return machine->cpu_dai; | |
236 | } | |
237 | ||
238 | static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream) | |
239 | { | |
240 | struct snd_soc_dai *dai = fsi_get_dai(substream); | |
a4d7d550 | 241 | |
71f6e064 | 242 | return dai->private_data; |
a4d7d550 KM |
243 | } |
244 | ||
245 | static u32 fsi_get_info_flags(struct fsi_priv *fsi) | |
246 | { | |
247 | int is_porta = fsi_is_port_a(fsi); | |
71f6e064 | 248 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 KM |
249 | |
250 | return is_porta ? master->info->porta_flags : | |
251 | master->info->portb_flags; | |
252 | } | |
253 | ||
254 | static int fsi_is_master_mode(struct fsi_priv *fsi, int is_play) | |
255 | { | |
256 | u32 mode; | |
257 | u32 flags = fsi_get_info_flags(fsi); | |
258 | ||
259 | mode = is_play ? SH_FSI_OUT_SLAVE_MODE : SH_FSI_IN_SLAVE_MODE; | |
260 | ||
261 | /* return | |
262 | * 1 : master mode | |
263 | * 0 : slave mode | |
264 | */ | |
265 | ||
266 | return (mode & flags) != mode; | |
267 | } | |
268 | ||
269 | static u32 fsi_port_ab_io_bit(struct fsi_priv *fsi, int is_play) | |
270 | { | |
271 | int is_porta = fsi_is_port_a(fsi); | |
272 | u32 data; | |
273 | ||
274 | if (is_porta) | |
275 | data = is_play ? (1 << 0) : (1 << 4); | |
276 | else | |
277 | data = is_play ? (1 << 8) : (1 << 12); | |
278 | ||
279 | return data; | |
280 | } | |
281 | ||
282 | static void fsi_stream_push(struct fsi_priv *fsi, | |
283 | struct snd_pcm_substream *substream, | |
284 | u32 buffer_len, | |
285 | u32 period_len) | |
286 | { | |
287 | fsi->substream = substream; | |
288 | fsi->buffer_len = buffer_len; | |
289 | fsi->period_len = period_len; | |
290 | fsi->byte_offset = 0; | |
291 | fsi->periods = 0; | |
292 | } | |
293 | ||
294 | static void fsi_stream_pop(struct fsi_priv *fsi) | |
295 | { | |
296 | fsi->substream = NULL; | |
297 | fsi->buffer_len = 0; | |
298 | fsi->period_len = 0; | |
299 | fsi->byte_offset = 0; | |
300 | fsi->periods = 0; | |
301 | } | |
302 | ||
303 | static int fsi_get_fifo_residue(struct fsi_priv *fsi, int is_play) | |
304 | { | |
305 | u32 status; | |
306 | u32 reg = is_play ? DOFF_ST : DIFF_ST; | |
307 | int residue; | |
308 | ||
309 | status = fsi_reg_read(fsi, reg); | |
310 | residue = 0x1ff & (status >> 8); | |
311 | residue *= fsi->chan; | |
312 | ||
313 | return residue; | |
314 | } | |
315 | ||
a4d7d550 KM |
316 | /************************************************************************ |
317 | ||
318 | ||
319 | ctrl function | |
320 | ||
321 | ||
322 | ************************************************************************/ | |
323 | static void fsi_irq_enable(struct fsi_priv *fsi, int is_play) | |
324 | { | |
325 | u32 data = fsi_port_ab_io_bit(fsi, is_play); | |
71f6e064 | 326 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 327 | |
71f6e064 KM |
328 | fsi_master_mask_set(master, IMSK, data, data); |
329 | fsi_master_mask_set(master, IEMSK, data, data); | |
a4d7d550 KM |
330 | } |
331 | ||
332 | static void fsi_irq_disable(struct fsi_priv *fsi, int is_play) | |
333 | { | |
334 | u32 data = fsi_port_ab_io_bit(fsi, is_play); | |
71f6e064 | 335 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 | 336 | |
71f6e064 KM |
337 | fsi_master_mask_set(master, IMSK, data, 0); |
338 | fsi_master_mask_set(master, IEMSK, data, 0); | |
a4d7d550 KM |
339 | } |
340 | ||
341 | static void fsi_clk_ctrl(struct fsi_priv *fsi, int enable) | |
342 | { | |
343 | u32 val = fsi_is_port_a(fsi) ? (1 << 0) : (1 << 4); | |
71f6e064 | 344 | struct fsi_master *master = fsi_get_master(fsi); |
a4d7d550 KM |
345 | |
346 | if (enable) | |
71f6e064 | 347 | fsi_master_mask_set(master, CLK_RST, val, val); |
a4d7d550 | 348 | else |
71f6e064 | 349 | fsi_master_mask_set(master, CLK_RST, val, 0); |
a4d7d550 KM |
350 | } |
351 | ||
352 | static void fsi_irq_init(struct fsi_priv *fsi, int is_play) | |
353 | { | |
354 | u32 data; | |
355 | u32 ctrl; | |
356 | ||
357 | data = fsi_port_ab_io_bit(fsi, is_play); | |
358 | ctrl = is_play ? DOFF_CTL : DIFF_CTL; | |
359 | ||
360 | /* set IMSK */ | |
361 | fsi_irq_disable(fsi, is_play); | |
362 | ||
363 | /* set interrupt generation factor */ | |
364 | fsi_reg_write(fsi, ctrl, IRQ_HALF); | |
365 | ||
366 | /* clear FIFO */ | |
367 | fsi_reg_mask_set(fsi, ctrl, FIFO_CLR, FIFO_CLR); | |
368 | ||
369 | /* clear interrupt factor */ | |
71f6e064 | 370 | fsi_master_mask_set(fsi_get_master(fsi), INT_ST, data, 0); |
a4d7d550 KM |
371 | } |
372 | ||
71f6e064 | 373 | static void fsi_soft_all_reset(struct fsi_master *master) |
a4d7d550 | 374 | { |
71f6e064 | 375 | u32 status = fsi_master_read(master, SOFT_RST); |
a4d7d550 KM |
376 | |
377 | /* port AB reset */ | |
378 | status &= 0x000000ff; | |
71f6e064 | 379 | fsi_master_write(master, SOFT_RST, status); |
a4d7d550 KM |
380 | mdelay(10); |
381 | ||
382 | /* soft reset */ | |
383 | status &= 0x000000f0; | |
71f6e064 | 384 | fsi_master_write(master, SOFT_RST, status); |
a4d7d550 | 385 | status |= 0x00000001; |
71f6e064 | 386 | fsi_master_write(master, SOFT_RST, status); |
a4d7d550 KM |
387 | mdelay(10); |
388 | } | |
389 | ||
a4d7d550 KM |
390 | /* playback interrupt */ |
391 | static int fsi_data_push(struct fsi_priv *fsi) | |
392 | { | |
393 | struct snd_pcm_runtime *runtime; | |
394 | struct snd_pcm_substream *substream = NULL; | |
59c3b003 | 395 | u32 status; |
a4d7d550 KM |
396 | int send; |
397 | int fifo_free; | |
398 | int width; | |
9ddc9aa9 | 399 | u8 *start; |
59c3b003 | 400 | int i, ret, over_period; |
a4d7d550 KM |
401 | |
402 | if (!fsi || | |
403 | !fsi->substream || | |
404 | !fsi->substream->runtime) | |
405 | return -EINVAL; | |
406 | ||
1c418d1f KM |
407 | over_period = 0; |
408 | substream = fsi->substream; | |
409 | runtime = substream->runtime; | |
a4d7d550 KM |
410 | |
411 | /* FSI FIFO has limit. | |
412 | * So, this driver can not send periods data at a time | |
413 | */ | |
414 | if (fsi->byte_offset >= | |
415 | fsi->period_len * (fsi->periods + 1)) { | |
416 | ||
1c418d1f | 417 | over_period = 1; |
a4d7d550 KM |
418 | fsi->periods = (fsi->periods + 1) % runtime->periods; |
419 | ||
420 | if (0 == fsi->periods) | |
421 | fsi->byte_offset = 0; | |
422 | } | |
423 | ||
424 | /* get 1 channel data width */ | |
425 | width = frames_to_bytes(runtime, 1) / fsi->chan; | |
426 | ||
427 | /* get send size for alsa */ | |
428 | send = (fsi->buffer_len - fsi->byte_offset) / width; | |
429 | ||
430 | /* get FIFO free size */ | |
431 | fifo_free = (fsi->fifo_max * fsi->chan) - fsi_get_fifo_residue(fsi, 1); | |
432 | ||
433 | /* size check */ | |
434 | if (fifo_free < send) | |
435 | send = fifo_free; | |
436 | ||
9ddc9aa9 KM |
437 | start = runtime->dma_area; |
438 | start += fsi->byte_offset; | |
439 | ||
440 | switch (width) { | |
441 | case 2: | |
442 | for (i = 0; i < send; i++) | |
443 | fsi_reg_write(fsi, DODT, | |
444 | ((u32)*((u16 *)start + i) << 8)); | |
445 | break; | |
446 | case 4: | |
447 | for (i = 0; i < send; i++) | |
448 | fsi_reg_write(fsi, DODT, *((u32 *)start + i)); | |
449 | break; | |
450 | default: | |
a4d7d550 | 451 | return -EINVAL; |
9ddc9aa9 | 452 | } |
a4d7d550 KM |
453 | |
454 | fsi->byte_offset += send * width; | |
455 | ||
59c3b003 KM |
456 | ret = 0; |
457 | status = fsi_reg_read(fsi, DOFF_ST); | |
458 | if (status & ERR_OVER) { | |
459 | struct snd_soc_dai *dai = fsi_get_dai(substream); | |
460 | dev_err(dai->dev, "over run error\n"); | |
461 | fsi_reg_write(fsi, DOFF_ST, status & ~ST_ERR); | |
462 | ret = -EIO; | |
463 | } | |
464 | ||
a4d7d550 KM |
465 | fsi_irq_enable(fsi, 1); |
466 | ||
1c418d1f | 467 | if (over_period) |
a4d7d550 KM |
468 | snd_pcm_period_elapsed(substream); |
469 | ||
59c3b003 | 470 | return ret; |
a4d7d550 KM |
471 | } |
472 | ||
07102f3c KM |
473 | static int fsi_data_pop(struct fsi_priv *fsi) |
474 | { | |
475 | struct snd_pcm_runtime *runtime; | |
476 | struct snd_pcm_substream *substream = NULL; | |
59c3b003 | 477 | u32 status; |
07102f3c KM |
478 | int free; |
479 | int fifo_fill; | |
480 | int width; | |
481 | u8 *start; | |
59c3b003 | 482 | int i, ret, over_period; |
07102f3c KM |
483 | |
484 | if (!fsi || | |
485 | !fsi->substream || | |
486 | !fsi->substream->runtime) | |
487 | return -EINVAL; | |
488 | ||
1c418d1f KM |
489 | over_period = 0; |
490 | substream = fsi->substream; | |
491 | runtime = substream->runtime; | |
07102f3c KM |
492 | |
493 | /* FSI FIFO has limit. | |
494 | * So, this driver can not send periods data at a time | |
495 | */ | |
496 | if (fsi->byte_offset >= | |
497 | fsi->period_len * (fsi->periods + 1)) { | |
498 | ||
1c418d1f | 499 | over_period = 1; |
07102f3c KM |
500 | fsi->periods = (fsi->periods + 1) % runtime->periods; |
501 | ||
502 | if (0 == fsi->periods) | |
503 | fsi->byte_offset = 0; | |
504 | } | |
505 | ||
506 | /* get 1 channel data width */ | |
507 | width = frames_to_bytes(runtime, 1) / fsi->chan; | |
508 | ||
509 | /* get free space for alsa */ | |
510 | free = (fsi->buffer_len - fsi->byte_offset) / width; | |
511 | ||
512 | /* get recv size */ | |
513 | fifo_fill = fsi_get_fifo_residue(fsi, 0); | |
514 | ||
515 | if (free < fifo_fill) | |
516 | fifo_fill = free; | |
517 | ||
518 | start = runtime->dma_area; | |
519 | start += fsi->byte_offset; | |
520 | ||
521 | switch (width) { | |
522 | case 2: | |
523 | for (i = 0; i < fifo_fill; i++) | |
524 | *((u16 *)start + i) = | |
525 | (u16)(fsi_reg_read(fsi, DIDT) >> 8); | |
526 | break; | |
527 | case 4: | |
528 | for (i = 0; i < fifo_fill; i++) | |
529 | *((u32 *)start + i) = fsi_reg_read(fsi, DIDT); | |
530 | break; | |
531 | default: | |
532 | return -EINVAL; | |
533 | } | |
534 | ||
535 | fsi->byte_offset += fifo_fill * width; | |
536 | ||
59c3b003 KM |
537 | ret = 0; |
538 | status = fsi_reg_read(fsi, DIFF_ST); | |
539 | if (status & ERR_UNDER) { | |
540 | struct snd_soc_dai *dai = fsi_get_dai(substream); | |
541 | dev_err(dai->dev, "under run error\n"); | |
542 | fsi_reg_write(fsi, DIFF_ST, status & ~ST_ERR); | |
543 | ret = -EIO; | |
544 | } | |
545 | ||
07102f3c KM |
546 | fsi_irq_enable(fsi, 0); |
547 | ||
1c418d1f | 548 | if (over_period) |
07102f3c KM |
549 | snd_pcm_period_elapsed(substream); |
550 | ||
59c3b003 | 551 | return ret; |
07102f3c KM |
552 | } |
553 | ||
a4d7d550 KM |
554 | static irqreturn_t fsi_interrupt(int irq, void *data) |
555 | { | |
71f6e064 KM |
556 | struct fsi_master *master = data; |
557 | u32 status = fsi_master_read(master, SOFT_RST) & ~0x00000010; | |
558 | u32 int_st = fsi_master_read(master, INT_ST); | |
a4d7d550 KM |
559 | |
560 | /* clear irq status */ | |
71f6e064 KM |
561 | fsi_master_write(master, SOFT_RST, status); |
562 | fsi_master_write(master, SOFT_RST, status | 0x00000010); | |
a4d7d550 KM |
563 | |
564 | if (int_st & INT_A_OUT) | |
565 | fsi_data_push(&master->fsia); | |
566 | if (int_st & INT_B_OUT) | |
567 | fsi_data_push(&master->fsib); | |
07102f3c KM |
568 | if (int_st & INT_A_IN) |
569 | fsi_data_pop(&master->fsia); | |
570 | if (int_st & INT_B_IN) | |
571 | fsi_data_pop(&master->fsib); | |
a4d7d550 | 572 | |
71f6e064 | 573 | fsi_master_write(master, INT_ST, 0x0000000); |
a4d7d550 KM |
574 | |
575 | return IRQ_HANDLED; | |
576 | } | |
577 | ||
578 | /************************************************************************ | |
579 | ||
580 | ||
581 | dai ops | |
582 | ||
583 | ||
584 | ************************************************************************/ | |
585 | static int fsi_dai_startup(struct snd_pcm_substream *substream, | |
586 | struct snd_soc_dai *dai) | |
587 | { | |
71f6e064 | 588 | struct fsi_priv *fsi = fsi_get_priv(substream); |
a4d7d550 KM |
589 | const char *msg; |
590 | u32 flags = fsi_get_info_flags(fsi); | |
591 | u32 fmt; | |
592 | u32 reg; | |
593 | u32 data; | |
594 | int is_play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); | |
595 | int is_master; | |
596 | int ret = 0; | |
597 | ||
785d1c45 | 598 | pm_runtime_get_sync(dai->dev); |
a4d7d550 KM |
599 | |
600 | /* CKG1 */ | |
601 | data = is_play ? (1 << 0) : (1 << 4); | |
602 | is_master = fsi_is_master_mode(fsi, is_play); | |
603 | if (is_master) | |
604 | fsi_reg_mask_set(fsi, CKG1, data, data); | |
605 | else | |
606 | fsi_reg_mask_set(fsi, CKG1, data, 0); | |
607 | ||
608 | /* clock inversion (CKG2) */ | |
609 | data = 0; | |
610 | switch (SH_FSI_INVERSION_MASK & flags) { | |
611 | case SH_FSI_LRM_INV: | |
612 | data = 1 << 12; | |
613 | break; | |
614 | case SH_FSI_BRM_INV: | |
615 | data = 1 << 8; | |
616 | break; | |
617 | case SH_FSI_LRS_INV: | |
618 | data = 1 << 4; | |
619 | break; | |
620 | case SH_FSI_BRS_INV: | |
621 | data = 1 << 0; | |
622 | break; | |
623 | } | |
624 | fsi_reg_write(fsi, CKG2, data); | |
625 | ||
626 | /* do fmt, di fmt */ | |
627 | data = 0; | |
628 | reg = is_play ? DO_FMT : DI_FMT; | |
629 | fmt = is_play ? SH_FSI_GET_OFMT(flags) : SH_FSI_GET_IFMT(flags); | |
630 | switch (fmt) { | |
631 | case SH_FSI_FMT_MONO: | |
632 | msg = "MONO"; | |
633 | data = CR_FMT(CR_MONO); | |
634 | fsi->chan = 1; | |
635 | break; | |
636 | case SH_FSI_FMT_MONO_DELAY: | |
637 | msg = "MONO Delay"; | |
638 | data = CR_FMT(CR_MONO_D); | |
639 | fsi->chan = 1; | |
640 | break; | |
641 | case SH_FSI_FMT_PCM: | |
642 | msg = "PCM"; | |
643 | data = CR_FMT(CR_PCM); | |
644 | fsi->chan = 2; | |
645 | break; | |
646 | case SH_FSI_FMT_I2S: | |
647 | msg = "I2S"; | |
648 | data = CR_FMT(CR_I2S); | |
649 | fsi->chan = 2; | |
650 | break; | |
651 | case SH_FSI_FMT_TDM: | |
652 | msg = "TDM"; | |
653 | data = CR_FMT(CR_TDM) | (fsi->chan - 1); | |
654 | fsi->chan = is_play ? | |
655 | SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags); | |
656 | break; | |
657 | case SH_FSI_FMT_TDM_DELAY: | |
658 | msg = "TDM Delay"; | |
659 | data = CR_FMT(CR_TDM_D) | (fsi->chan - 1); | |
660 | fsi->chan = is_play ? | |
661 | SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags); | |
662 | break; | |
663 | default: | |
664 | dev_err(dai->dev, "unknown format.\n"); | |
665 | return -EINVAL; | |
666 | } | |
667 | ||
668 | switch (fsi->chan) { | |
669 | case 1: | |
670 | fsi->fifo_max = 256; | |
671 | break; | |
672 | case 2: | |
673 | fsi->fifo_max = 128; | |
674 | break; | |
675 | case 3: | |
676 | case 4: | |
677 | fsi->fifo_max = 64; | |
678 | break; | |
679 | case 5: | |
680 | case 6: | |
681 | case 7: | |
682 | case 8: | |
683 | fsi->fifo_max = 32; | |
684 | break; | |
685 | default: | |
686 | dev_err(dai->dev, "channel size error.\n"); | |
687 | return -EINVAL; | |
688 | } | |
689 | ||
690 | fsi_reg_write(fsi, reg, data); | |
a4d7d550 KM |
691 | |
692 | /* | |
693 | * clear clk reset if master mode | |
694 | */ | |
695 | if (is_master) | |
696 | fsi_clk_ctrl(fsi, 1); | |
697 | ||
698 | /* irq setting */ | |
699 | fsi_irq_init(fsi, is_play); | |
700 | ||
701 | return ret; | |
702 | } | |
703 | ||
704 | static void fsi_dai_shutdown(struct snd_pcm_substream *substream, | |
705 | struct snd_soc_dai *dai) | |
706 | { | |
71f6e064 | 707 | struct fsi_priv *fsi = fsi_get_priv(substream); |
a4d7d550 KM |
708 | int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
709 | ||
710 | fsi_irq_disable(fsi, is_play); | |
711 | fsi_clk_ctrl(fsi, 0); | |
712 | ||
785d1c45 | 713 | pm_runtime_put_sync(dai->dev); |
a4d7d550 KM |
714 | } |
715 | ||
716 | static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd, | |
717 | struct snd_soc_dai *dai) | |
718 | { | |
71f6e064 | 719 | struct fsi_priv *fsi = fsi_get_priv(substream); |
a4d7d550 KM |
720 | struct snd_pcm_runtime *runtime = substream->runtime; |
721 | int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; | |
722 | int ret = 0; | |
723 | ||
a4d7d550 KM |
724 | switch (cmd) { |
725 | case SNDRV_PCM_TRIGGER_START: | |
726 | fsi_stream_push(fsi, substream, | |
727 | frames_to_bytes(runtime, runtime->buffer_size), | |
728 | frames_to_bytes(runtime, runtime->period_size)); | |
07102f3c | 729 | ret = is_play ? fsi_data_push(fsi) : fsi_data_pop(fsi); |
a4d7d550 KM |
730 | break; |
731 | case SNDRV_PCM_TRIGGER_STOP: | |
732 | fsi_irq_disable(fsi, is_play); | |
733 | fsi_stream_pop(fsi); | |
734 | break; | |
735 | } | |
736 | ||
737 | return ret; | |
738 | } | |
739 | ||
740 | static struct snd_soc_dai_ops fsi_dai_ops = { | |
741 | .startup = fsi_dai_startup, | |
742 | .shutdown = fsi_dai_shutdown, | |
743 | .trigger = fsi_dai_trigger, | |
744 | }; | |
745 | ||
746 | /************************************************************************ | |
747 | ||
748 | ||
749 | pcm ops | |
750 | ||
751 | ||
752 | ************************************************************************/ | |
753 | static struct snd_pcm_hardware fsi_pcm_hardware = { | |
754 | .info = SNDRV_PCM_INFO_INTERLEAVED | | |
755 | SNDRV_PCM_INFO_MMAP | | |
756 | SNDRV_PCM_INFO_MMAP_VALID | | |
757 | SNDRV_PCM_INFO_PAUSE, | |
758 | .formats = FSI_FMTS, | |
759 | .rates = FSI_RATES, | |
760 | .rate_min = 8000, | |
761 | .rate_max = 192000, | |
762 | .channels_min = 1, | |
763 | .channels_max = 2, | |
764 | .buffer_bytes_max = 64 * 1024, | |
765 | .period_bytes_min = 32, | |
766 | .period_bytes_max = 8192, | |
767 | .periods_min = 1, | |
768 | .periods_max = 32, | |
769 | .fifo_size = 256, | |
770 | }; | |
771 | ||
772 | static int fsi_pcm_open(struct snd_pcm_substream *substream) | |
773 | { | |
774 | struct snd_pcm_runtime *runtime = substream->runtime; | |
775 | int ret = 0; | |
776 | ||
777 | snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware); | |
778 | ||
779 | ret = snd_pcm_hw_constraint_integer(runtime, | |
780 | SNDRV_PCM_HW_PARAM_PERIODS); | |
781 | ||
782 | return ret; | |
783 | } | |
784 | ||
785 | static int fsi_hw_params(struct snd_pcm_substream *substream, | |
786 | struct snd_pcm_hw_params *hw_params) | |
787 | { | |
788 | return snd_pcm_lib_malloc_pages(substream, | |
789 | params_buffer_bytes(hw_params)); | |
790 | } | |
791 | ||
792 | static int fsi_hw_free(struct snd_pcm_substream *substream) | |
793 | { | |
794 | return snd_pcm_lib_free_pages(substream); | |
795 | } | |
796 | ||
797 | static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream) | |
798 | { | |
799 | struct snd_pcm_runtime *runtime = substream->runtime; | |
71f6e064 | 800 | struct fsi_priv *fsi = fsi_get_priv(substream); |
a4d7d550 KM |
801 | long location; |
802 | ||
9ddc9aa9 | 803 | location = (fsi->byte_offset - 1); |
a4d7d550 KM |
804 | if (location < 0) |
805 | location = 0; | |
806 | ||
807 | return bytes_to_frames(runtime, location); | |
808 | } | |
809 | ||
810 | static struct snd_pcm_ops fsi_pcm_ops = { | |
811 | .open = fsi_pcm_open, | |
812 | .ioctl = snd_pcm_lib_ioctl, | |
813 | .hw_params = fsi_hw_params, | |
814 | .hw_free = fsi_hw_free, | |
815 | .pointer = fsi_pointer, | |
816 | }; | |
817 | ||
818 | /************************************************************************ | |
819 | ||
820 | ||
821 | snd_soc_platform | |
822 | ||
823 | ||
824 | ************************************************************************/ | |
825 | #define PREALLOC_BUFFER (32 * 1024) | |
826 | #define PREALLOC_BUFFER_MAX (32 * 1024) | |
827 | ||
828 | static void fsi_pcm_free(struct snd_pcm *pcm) | |
829 | { | |
830 | snd_pcm_lib_preallocate_free_for_all(pcm); | |
831 | } | |
832 | ||
833 | static int fsi_pcm_new(struct snd_card *card, | |
834 | struct snd_soc_dai *dai, | |
835 | struct snd_pcm *pcm) | |
836 | { | |
837 | /* | |
838 | * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel | |
839 | * in MMAP mode (i.e. aplay -M) | |
840 | */ | |
841 | return snd_pcm_lib_preallocate_pages_for_all( | |
842 | pcm, | |
843 | SNDRV_DMA_TYPE_CONTINUOUS, | |
844 | snd_dma_continuous_data(GFP_KERNEL), | |
845 | PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); | |
846 | } | |
847 | ||
848 | /************************************************************************ | |
849 | ||
850 | ||
851 | alsa struct | |
852 | ||
853 | ||
854 | ************************************************************************/ | |
855 | struct snd_soc_dai fsi_soc_dai[] = { | |
856 | { | |
857 | .name = "FSIA", | |
858 | .id = 0, | |
859 | .playback = { | |
860 | .rates = FSI_RATES, | |
861 | .formats = FSI_FMTS, | |
862 | .channels_min = 1, | |
863 | .channels_max = 8, | |
864 | }, | |
07102f3c KM |
865 | .capture = { |
866 | .rates = FSI_RATES, | |
867 | .formats = FSI_FMTS, | |
868 | .channels_min = 1, | |
869 | .channels_max = 8, | |
870 | }, | |
a4d7d550 KM |
871 | .ops = &fsi_dai_ops, |
872 | }, | |
873 | { | |
874 | .name = "FSIB", | |
875 | .id = 1, | |
876 | .playback = { | |
877 | .rates = FSI_RATES, | |
878 | .formats = FSI_FMTS, | |
879 | .channels_min = 1, | |
880 | .channels_max = 8, | |
881 | }, | |
07102f3c KM |
882 | .capture = { |
883 | .rates = FSI_RATES, | |
884 | .formats = FSI_FMTS, | |
885 | .channels_min = 1, | |
886 | .channels_max = 8, | |
887 | }, | |
a4d7d550 KM |
888 | .ops = &fsi_dai_ops, |
889 | }, | |
890 | }; | |
891 | EXPORT_SYMBOL_GPL(fsi_soc_dai); | |
892 | ||
893 | struct snd_soc_platform fsi_soc_platform = { | |
894 | .name = "fsi-pcm", | |
895 | .pcm_ops = &fsi_pcm_ops, | |
896 | .pcm_new = fsi_pcm_new, | |
897 | .pcm_free = fsi_pcm_free, | |
898 | }; | |
899 | EXPORT_SYMBOL_GPL(fsi_soc_platform); | |
900 | ||
901 | /************************************************************************ | |
902 | ||
903 | ||
904 | platform function | |
905 | ||
906 | ||
907 | ************************************************************************/ | |
908 | static int fsi_probe(struct platform_device *pdev) | |
909 | { | |
71f6e064 | 910 | struct fsi_master *master; |
a4d7d550 | 911 | struct resource *res; |
a4d7d550 KM |
912 | unsigned int irq; |
913 | int ret; | |
914 | ||
71f6e064 KM |
915 | if (0 != pdev->id) { |
916 | dev_err(&pdev->dev, "current fsi support id 0 only now\n"); | |
917 | return -ENODEV; | |
918 | } | |
919 | ||
a4d7d550 KM |
920 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
921 | irq = platform_get_irq(pdev, 0); | |
b6aa1793 | 922 | if (!res || (int)irq <= 0) { |
a4d7d550 KM |
923 | dev_err(&pdev->dev, "Not enough FSI platform resources.\n"); |
924 | ret = -ENODEV; | |
925 | goto exit; | |
926 | } | |
927 | ||
928 | master = kzalloc(sizeof(*master), GFP_KERNEL); | |
929 | if (!master) { | |
930 | dev_err(&pdev->dev, "Could not allocate master\n"); | |
931 | ret = -ENOMEM; | |
932 | goto exit; | |
933 | } | |
934 | ||
935 | master->base = ioremap_nocache(res->start, resource_size(res)); | |
936 | if (!master->base) { | |
937 | ret = -ENXIO; | |
938 | dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n"); | |
939 | goto exit_kfree; | |
940 | } | |
941 | ||
942 | master->irq = irq; | |
943 | master->info = pdev->dev.platform_data; | |
944 | master->fsia.base = master->base; | |
71f6e064 | 945 | master->fsia.master = master; |
a4d7d550 | 946 | master->fsib.base = master->base + 0x40; |
71f6e064 | 947 | master->fsib.master = master; |
8fc176d5 | 948 | spin_lock_init(&master->lock); |
a4d7d550 | 949 | |
785d1c45 KM |
950 | pm_runtime_enable(&pdev->dev); |
951 | pm_runtime_resume(&pdev->dev); | |
a4d7d550 KM |
952 | |
953 | fsi_soc_dai[0].dev = &pdev->dev; | |
71f6e064 | 954 | fsi_soc_dai[0].private_data = &master->fsia; |
a4d7d550 | 955 | fsi_soc_dai[1].dev = &pdev->dev; |
71f6e064 | 956 | fsi_soc_dai[1].private_data = &master->fsib; |
a4d7d550 | 957 | |
71f6e064 | 958 | fsi_soft_all_reset(master); |
a4d7d550 KM |
959 | |
960 | ret = request_irq(irq, &fsi_interrupt, IRQF_DISABLED, "fsi", master); | |
961 | if (ret) { | |
962 | dev_err(&pdev->dev, "irq request err\n"); | |
9ddc9aa9 | 963 | goto exit_iounmap; |
a4d7d550 KM |
964 | } |
965 | ||
966 | ret = snd_soc_register_platform(&fsi_soc_platform); | |
967 | if (ret < 0) { | |
968 | dev_err(&pdev->dev, "cannot snd soc register\n"); | |
969 | goto exit_free_irq; | |
970 | } | |
971 | ||
972 | return snd_soc_register_dais(fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai)); | |
973 | ||
974 | exit_free_irq: | |
975 | free_irq(irq, master); | |
a4d7d550 KM |
976 | exit_iounmap: |
977 | iounmap(master->base); | |
785d1c45 | 978 | pm_runtime_disable(&pdev->dev); |
a4d7d550 KM |
979 | exit_kfree: |
980 | kfree(master); | |
981 | master = NULL; | |
982 | exit: | |
983 | return ret; | |
984 | } | |
985 | ||
986 | static int fsi_remove(struct platform_device *pdev) | |
987 | { | |
71f6e064 KM |
988 | struct fsi_master *master; |
989 | ||
990 | master = fsi_get_master(fsi_soc_dai[0].private_data); | |
991 | ||
a4d7d550 KM |
992 | snd_soc_unregister_dais(fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai)); |
993 | snd_soc_unregister_platform(&fsi_soc_platform); | |
994 | ||
785d1c45 | 995 | pm_runtime_disable(&pdev->dev); |
a4d7d550 | 996 | |
a4d7d550 KM |
997 | free_irq(master->irq, master); |
998 | ||
999 | iounmap(master->base); | |
1000 | kfree(master); | |
71f6e064 KM |
1001 | |
1002 | fsi_soc_dai[0].dev = NULL; | |
1003 | fsi_soc_dai[0].private_data = NULL; | |
1004 | fsi_soc_dai[1].dev = NULL; | |
1005 | fsi_soc_dai[1].private_data = NULL; | |
1006 | ||
a4d7d550 KM |
1007 | return 0; |
1008 | } | |
1009 | ||
785d1c45 KM |
1010 | static int fsi_runtime_nop(struct device *dev) |
1011 | { | |
1012 | /* Runtime PM callback shared between ->runtime_suspend() | |
1013 | * and ->runtime_resume(). Simply returns success. | |
1014 | * | |
1015 | * This driver re-initializes all registers after | |
1016 | * pm_runtime_get_sync() anyway so there is no need | |
1017 | * to save and restore registers here. | |
1018 | */ | |
1019 | return 0; | |
1020 | } | |
1021 | ||
1022 | static struct dev_pm_ops fsi_pm_ops = { | |
1023 | .runtime_suspend = fsi_runtime_nop, | |
1024 | .runtime_resume = fsi_runtime_nop, | |
1025 | }; | |
1026 | ||
a4d7d550 KM |
1027 | static struct platform_driver fsi_driver = { |
1028 | .driver = { | |
1029 | .name = "sh_fsi", | |
785d1c45 | 1030 | .pm = &fsi_pm_ops, |
a4d7d550 KM |
1031 | }, |
1032 | .probe = fsi_probe, | |
1033 | .remove = fsi_remove, | |
1034 | }; | |
1035 | ||
1036 | static int __init fsi_mobile_init(void) | |
1037 | { | |
1038 | return platform_driver_register(&fsi_driver); | |
1039 | } | |
1040 | ||
1041 | static void __exit fsi_mobile_exit(void) | |
1042 | { | |
1043 | platform_driver_unregister(&fsi_driver); | |
1044 | } | |
1045 | module_init(fsi_mobile_init); | |
1046 | module_exit(fsi_mobile_exit); | |
1047 | ||
1048 | MODULE_LICENSE("GPL"); | |
1049 | MODULE_DESCRIPTION("SuperH onchip FSI audio driver"); | |
1050 | MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>"); |