[deliverable/linux.git] / sound / soc / sh / rcar / adg.c

/*
 * Helper routines for R-Car sound ADG.
 *
 *  Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/sh_clk.h>
#include "rsnd.h"

#define CLKA	0
#define CLKB	1
#define CLKC	2
#define CLKI	3
#define CLKMAX	4

struct rsnd_adg {
	struct clk *clk[CLKMAX];

	int rbga_rate_for_441khz_div_6;	/* RBGA */
	int rbgb_rate_for_48khz_div_6;	/* RBGB */
	u32 ckr;
};

#define for_each_rsnd_clk(pos, adg, i)		\
	for (i = 0;				\
	     (i < CLKMAX) &&			\
	     ((pos) = adg->clk[i]);		\
	     i++)
#define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)


static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io)
{
	struct rsnd_mod *mod = rsnd_io_to_mod_ssi(io);
	struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
	int id = rsnd_mod_id(mod);
	int ws = id;

	if (rsnd_ssi_is_pin_sharing(rsnd_ssi_mod_get(priv, id))) {
		switch (id) {
		case 1:
		case 2:
			ws = 0;
			break;
		case 4:
			ws = 3;
			break;
		case 8:
			ws = 7;
			break;
		}
	}

	return (0x6 + ws) << 8;
}

int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_dai *rdai,
				 struct rsnd_mod *mod,
				 struct rsnd_dai_stream *io)
{
	int id = rsnd_mod_id(mod);
	int shift = (id % 2) ? 16 : 0;
	u32 mask, val;

	val = rsnd_adg_ssi_ws_timing_gen2(io);

	val  = val	<< shift;
	mask = 0xffff	<< shift;

	rsnd_mod_bset(mod, CMDOUT_TIMSEL, mask, val);

	return 0;
}

static int rsnd_adg_set_src_timsel_gen2(struct rsnd_dai *rdai,
					struct rsnd_mod *mod,
					struct rsnd_dai_stream *io,
					u32 timsel)
{
	int is_play = rsnd_dai_is_play(rdai, io);
	int id = rsnd_mod_id(mod);
	int shift = (id % 2) ? 16 : 0;
	u32 mask, ws;
	u32 in, out;

	ws = rsnd_adg_ssi_ws_timing_gen2(io);

	in  = (is_play) ? timsel : ws;
	out = (is_play) ? ws     : timsel;

	in   = in	<< shift;
	out  = out	<< shift;
	mask = 0xffff	<< shift;

	switch (id / 2) {
	case 0:
		rsnd_mod_bset(mod, SRCIN_TIMSEL0,  mask, in);
		rsnd_mod_bset(mod, SRCOUT_TIMSEL0, mask, out);
		break;
	case 1:
		rsnd_mod_bset(mod, SRCIN_TIMSEL1,  mask, in);
		rsnd_mod_bset(mod, SRCOUT_TIMSEL1, mask, out);
		break;
	case 2:
		rsnd_mod_bset(mod, SRCIN_TIMSEL2,  mask, in);
		rsnd_mod_bset(mod, SRCOUT_TIMSEL2, mask, out);
		break;
	case 3:
		rsnd_mod_bset(mod, SRCIN_TIMSEL3,  mask, in);
		rsnd_mod_bset(mod, SRCOUT_TIMSEL3, mask, out);
		break;
	case 4:
		rsnd_mod_bset(mod, SRCIN_TIMSEL4,  mask, in);
		rsnd_mod_bset(mod, SRCOUT_TIMSEL4, mask, out);
		break;
	}

	return 0;
}

int rsnd_adg_set_convert_clk_gen2(struct rsnd_mod *mod,
				  struct rsnd_dai *rdai,
				  struct rsnd_dai_stream *io,
				  unsigned int src_rate,
				  unsigned int dst_rate)
{
	struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
	struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
	struct device *dev = rsnd_priv_to_dev(priv);
	int idx, sel, div, step, ret;
	u32 val, en;
	unsigned int min, diff;
	unsigned int sel_rate [] = {
		clk_get_rate(adg->clk[CLKA]),	/* 0000: CLKA */
		clk_get_rate(adg->clk[CLKB]),	/* 0001: CLKB */
		clk_get_rate(adg->clk[CLKC]),	/* 0010: CLKC */
		adg->rbga_rate_for_441khz_div_6,/* 0011: RBGA */
		adg->rbgb_rate_for_48khz_div_6,	/* 0100: RBGB */
	};

	min = ~0;
	val = 0;
	en = 0;
	for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
		idx = 0;
		step = 2;

		if (!sel_rate[sel])
			continue;

		for (div = 2; div <= 98304; div += step) {
			diff = abs(src_rate - sel_rate[sel] / div);
			if (min > diff) {
				val = (sel << 8) | idx;
				min = diff;
				en = 1 << (sel + 1); /* fixme */
			}

			/*
			 * step of 0_0000 / 0_0001 / 0_1101
			 * are out of order
			 */
			if ((idx > 2) && (idx % 2))
				step *= 2;
			if (idx == 0x1c) {
				div += step;
				step *= 2;
			}
			idx++;
		}
	}

	if (min == ~0) {
		dev_err(dev, "no Input clock\n");
		return -EIO;
	}

	ret = rsnd_adg_set_src_timsel_gen2(rdai, mod, io, val);
	if (ret < 0) {
		dev_err(dev, "timsel error\n");
		return ret;
	}

	rsnd_mod_bset(mod, DIV_EN, en, en);

	return 0;
}

int rsnd_adg_set_convert_timing_gen2(struct rsnd_mod *mod,
				     struct rsnd_dai *rdai,
				     struct rsnd_dai_stream *io)
{
	u32 val = rsnd_adg_ssi_ws_timing_gen2(io);

	return rsnd_adg_set_src_timsel_gen2(rdai, mod, io, val);
}

int rsnd_adg_set_convert_clk_gen1(struct rsnd_priv *priv,
				  struct rsnd_mod *mod,
				  unsigned int src_rate,
				  unsigned int dst_rate)
{
	struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
	struct device *dev = rsnd_priv_to_dev(priv);
	int idx, sel, div, shift;
	u32 mask, val;
	int id = rsnd_mod_id(mod);
	unsigned int sel_rate [] = {
		clk_get_rate(adg->clk[CLKA]),	/* 000: CLKA */
		clk_get_rate(adg->clk[CLKB]),	/* 001: CLKB */
		clk_get_rate(adg->clk[CLKC]),	/* 010: CLKC */
		0,				/* 011: MLBCLK (not used) */
		adg->rbga_rate_for_441khz_div_6,/* 100: RBGA */
		adg->rbgb_rate_for_48khz_div_6,	/* 101: RBGB */
	};

	/* find div (= 1/128, 1/256, 1/512, 1/1024, 1/2048 */
	for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
		for (div  = 128,	idx = 0;
		     div <= 2048;
		     div *= 2,		idx++) {
			if (src_rate == sel_rate[sel] / div) {
				val = (idx << 4) | sel;
				goto find_rate;
			}
		}
	}
	dev_err(dev, "can't find convert src clk\n");
	return -EINVAL;

find_rate:
	shift	= (id % 4) * 8;
	mask	= 0xFF << shift;
	val	= val << shift;

	dev_dbg(dev, "adg convert src clk = %02x\n", val);

	switch (id / 4) {
	case 0:
		rsnd_mod_bset(mod, AUDIO_CLK_SEL3, mask, val);
		break;
	case 1:
		rsnd_mod_bset(mod, AUDIO_CLK_SEL4, mask, val);
		break;
	case 2:
		rsnd_mod_bset(mod, AUDIO_CLK_SEL5, mask, val);
		break;
	}

	/*
	 * Gen1 doesn't need dst_rate settings,
	 * since it uses SSI WS pin.
	 * see also rsnd_src_set_route_if_gen1()
	 */

	return 0;
}

static void rsnd_adg_set_ssi_clk(struct rsnd_mod *mod, u32 val)
{
	int id = rsnd_mod_id(mod);
	int shift = (id % 4) * 8;
	u32 mask = 0xFF << shift;

	val = val << shift;

	/*
	 * SSI 8 is not connected to ADG.
	 * it works with SSI 7
	 */
	if (id == 8)
		return;

	switch (id / 4) {
	case 0:
		rsnd_mod_bset(mod, AUDIO_CLK_SEL0, mask, val);
		break;
	case 1:
		rsnd_mod_bset(mod, AUDIO_CLK_SEL1, mask, val);
		break;
	case 2:
		rsnd_mod_bset(mod, AUDIO_CLK_SEL2, mask, val);
		break;
	}
}

int rsnd_adg_ssi_clk_stop(struct rsnd_mod *mod)
{
	/*
	 * "mod" = "ssi" here.
	 * we can get "ssi id" from mod
	 */
	rsnd_adg_set_ssi_clk(mod, 0);

	return 0;
}

int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *mod, unsigned int rate)
{
	struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
	struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
	struct device *dev = rsnd_priv_to_dev(priv);
	struct clk *clk;
	int i;
	u32 data;
	int sel_table[] = {
		[CLKA] = 0x1,
		[CLKB] = 0x2,
		[CLKC] = 0x3,
		[CLKI] = 0x0,
	};

	dev_dbg(dev, "request clock = %d\n", rate);

	/*
	 * find suitable clock from
	 * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
	 */
	data = 0;
	for_each_rsnd_clk(clk, adg, i) {
		if (rate == clk_get_rate(clk)) {
			data = sel_table[i];
			goto found_clock;
		}
	}

	/*
	 * find 1/6 clock from BRGA/BRGB
	 */
	if (rate == adg->rbga_rate_for_441khz_div_6) {
		data = 0x10;
		goto found_clock;
	}

	if (rate == adg->rbgb_rate_for_48khz_div_6) {
		data = 0x20;
		goto found_clock;
	}

	return -EIO;

found_clock:

	/* see rsnd_adg_ssi_clk_init() */
	rsnd_mod_bset(mod, SSICKR, 0x00FF0000, adg->ckr);
	rsnd_mod_write(mod, BRRA,  0x00000002); /* 1/6 */
	rsnd_mod_write(mod, BRRB,  0x00000002); /* 1/6 */

	/*
	 * This "mod" = "ssi" here.
	 * we can get "ssi id" from mod
	 */
	rsnd_adg_set_ssi_clk(mod, data);

	dev_dbg(dev, "ADG: ssi%d selects clk%d = %d",
		rsnd_mod_id(mod), i, rate);

	return 0;
}

static void rsnd_adg_ssi_clk_init(struct rsnd_priv *priv, struct rsnd_adg *adg)
{
	struct clk *clk;
	unsigned long rate;
	u32 ckr;
	int i;
	int brg_table[] = {
		[CLKA] = 0x0,
		[CLKB] = 0x1,
		[CLKC] = 0x4,
		[CLKI] = 0x2,
	};

	/*
	 * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
	 * have 44.1kHz or 48kHz base clocks for now.
	 *
	 * SSI itself can divide parent clock by 1/1 - 1/16
	 * So,  BRGA outputs 44.1kHz base parent clock 1/32,
	 * and, BRGB outputs 48.0kHz base parent clock 1/32 here.
	 * see
	 *	rsnd_adg_ssi_clk_try_start()
	 */
	ckr = 0;
	adg->rbga_rate_for_441khz_div_6 = 0;
	adg->rbgb_rate_for_48khz_div_6  = 0;
	for_each_rsnd_clk(clk, adg, i) {
		rate = clk_get_rate(clk);

		if (0 == rate) /* not used */
			continue;

		/* RBGA */
		if (!adg->rbga_rate_for_441khz_div_6 && (0 == rate % 44100)) {
			adg->rbga_rate_for_441khz_div_6 = rate / 6;
			ckr |= brg_table[i] << 20;
		}

		/* RBGB */
		if (!adg->rbgb_rate_for_48khz_div_6 && (0 == rate % 48000)) {
			adg->rbgb_rate_for_48khz_div_6 = rate / 6;
			ckr |= brg_table[i] << 16;
		}
	}

	adg->ckr = ckr;
}

int rsnd_adg_probe(struct platform_device *pdev,
		   const struct rsnd_of_data *of_data,
		   struct rsnd_priv *priv)
{
	struct rsnd_adg *adg;
	struct device *dev = rsnd_priv_to_dev(priv);
	struct clk *clk;
	int i;

	adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
	if (!adg) {
		dev_err(dev, "ADG allocate failed\n");
		return -ENOMEM;
	}

	adg->clk[CLKA]	= devm_clk_get(dev, "clk_a");
	adg->clk[CLKB]	= devm_clk_get(dev, "clk_b");
	adg->clk[CLKC]	= devm_clk_get(dev, "clk_c");
	adg->clk[CLKI]	= devm_clk_get(dev, "clk_i");

	for_each_rsnd_clk(clk, adg, i)
		dev_dbg(dev, "clk %d : %p\n", i, clk);

	rsnd_adg_ssi_clk_init(priv, adg);

	priv->adg = adg;

	dev_dbg(dev, "adg probed\n");

	return 0;
}
Commit	Line	Data
dfc9403b KM	1	/*
	2	* Helper routines for R-Car sound ADG.
	3	*
	4	* Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10	#include <linux/sh_clk.h>
dfc9403b KM	11	#include "rsnd.h"
	12
	13	#define CLKA 0
	14	#define CLKB 1
	15	#define CLKC 2
	16	#define CLKI 3
	17	#define CLKMAX 4
	18
	19	struct rsnd_adg {
	20	struct clk *clk[CLKMAX];
	21
7808aa30 KM	22	int rbga_rate_for_441khz_div_6; /* RBGA */
7808aa30 KM	23	int rbgb_rate_for_48khz_div_6; /* RBGB */
efeb970e	24	u32 ckr;
dfc9403b KM	25	};
	26
	27	#define for_each_rsnd_clk(pos, adg, i) \
00463c11 KM	28	for (i = 0; \
	29	(i < CLKMAX) && \
	30	((pos) = adg->clk[i]); \
	31	i++)
dfc9403b KM	32	#define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
dfc9403b KM	33
629509c5	34
8467dedc	35	static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io)
629509c5	36	{
8467dedc	37	struct rsnd_mod *mod = rsnd_io_to_mod_ssi(io);
629509c5 KM	38	struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
	39	int id = rsnd_mod_id(mod);
	40	int ws = id;
	41
	42	if (rsnd_ssi_is_pin_sharing(rsnd_ssi_mod_get(priv, id))) {
	43	switch (id) {
	44	case 1:
	45	case 2:
	46	ws = 0;
	47	break;
	48	case 4:
	49	ws = 3;
	50	break;
	51	case 8:
	52	ws = 7;
	53	break;
	54	}
	55	}
	56
	57	return (0x6 + ws) << 8;
	58	}
	59
bff58ea4 KM	60	int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_dai *rdai,
	61	struct rsnd_mod *mod,
	62	struct rsnd_dai_stream *io)
	63	{
	64	int id = rsnd_mod_id(mod);
	65	int shift = (id % 2) ? 16 : 0;
	66	u32 mask, val;
	67
	68	val = rsnd_adg_ssi_ws_timing_gen2(io);
	69
	70	val = val << shift;
	71	mask = 0xffff << shift;
	72
	73	rsnd_mod_bset(mod, CMDOUT_TIMSEL, mask, val);
	74
	75	return 0;
	76	}
	77
629509c5 KM	78	static int rsnd_adg_set_src_timsel_gen2(struct rsnd_dai *rdai,
	79	struct rsnd_mod *mod,
	80	struct rsnd_dai_stream *io,
	81	u32 timsel)
	82	{
	83	int is_play = rsnd_dai_is_play(rdai, io);
	84	int id = rsnd_mod_id(mod);
	85	int shift = (id % 2) ? 16 : 0;
	86	u32 mask, ws;
	87	u32 in, out;
	88
8467dedc	89	ws = rsnd_adg_ssi_ws_timing_gen2(io);
629509c5 KM	90
	91	in = (is_play) ? timsel : ws;
	92	out = (is_play) ? ws : timsel;
	93
	94	in = in << shift;
	95	out = out << shift;
	96	mask = 0xffff << shift;
	97
	98	switch (id / 2) {
	99	case 0:
	100	rsnd_mod_bset(mod, SRCIN_TIMSEL0, mask, in);
	101	rsnd_mod_bset(mod, SRCOUT_TIMSEL0, mask, out);
	102	break;
	103	case 1:
	104	rsnd_mod_bset(mod, SRCIN_TIMSEL1, mask, in);
	105	rsnd_mod_bset(mod, SRCOUT_TIMSEL1, mask, out);
	106	break;
	107	case 2:
	108	rsnd_mod_bset(mod, SRCIN_TIMSEL2, mask, in);
	109	rsnd_mod_bset(mod, SRCOUT_TIMSEL2, mask, out);
	110	break;
	111	case 3:
	112	rsnd_mod_bset(mod, SRCIN_TIMSEL3, mask, in);
	113	rsnd_mod_bset(mod, SRCOUT_TIMSEL3, mask, out);
	114	break;
	115	case 4:
	116	rsnd_mod_bset(mod, SRCIN_TIMSEL4, mask, in);
	117	rsnd_mod_bset(mod, SRCOUT_TIMSEL4, mask, out);
	118	break;
	119	}
	120
	121	return 0;
	122	}
	123
	124	int rsnd_adg_set_convert_clk_gen2(struct rsnd_mod *mod,
	125	struct rsnd_dai *rdai,
	126	struct rsnd_dai_stream *io,
	127	unsigned int src_rate,
	128	unsigned int dst_rate)
	129	{
	130	struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
	131	struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
	132	struct device *dev = rsnd_priv_to_dev(priv);
ee2c828d KM	133	int idx, sel, div, step, ret;
ee2c828d KM	134	u32 val, en;
629509c5 KM	135	unsigned int min, diff;
	136	unsigned int sel_rate [] = {
	137	clk_get_rate(adg->clk[CLKA]), /* 0000: CLKA */
	138	clk_get_rate(adg->clk[CLKB]), /* 0001: CLKB */
	139	clk_get_rate(adg->clk[CLKC]), /* 0010: CLKC */
	140	adg->rbga_rate_for_441khz_div_6,/* 0011: RBGA */
	141	adg->rbgb_rate_for_48khz_div_6, /* 0100: RBGB */
	142	};
	143
	144	min = ~0;
	145	val = 0;
ee2c828d	146	en = 0;
629509c5 KM	147	for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
	148	idx = 0;
	149	step = 2;
	150
	151	if (!sel_rate[sel])
	152	continue;
	153
	154	for (div = 2; div <= 98304; div += step) {
	155	diff = abs(src_rate - sel_rate[sel] / div);
	156	if (min > diff) {
	157	val = (sel << 8) \| idx;
	158	min = diff;
ee2c828d	159	en = 1 << (sel + 1); /* fixme */
629509c5 KM	160	}
	161
	162	/*
	163	* step of 0_0000 / 0_0001 / 0_1101
	164	* are out of order
	165	*/
	166	if ((idx > 2) && (idx % 2))
	167	step *= 2;
	168	if (idx == 0x1c) {
	169	div += step;
	170	step *= 2;
	171	}
	172	idx++;
	173	}
	174	}
	175
	176	if (min == ~0) {
	177	dev_err(dev, "no Input clock\n");
	178	return -EIO;
	179	}
	180
ee2c828d KM	181	ret = rsnd_adg_set_src_timsel_gen2(rdai, mod, io, val);
	182	if (ret < 0) {
	183	dev_err(dev, "timsel error\n");
	184	return ret;
	185	}
	186
	187	rsnd_mod_bset(mod, DIV_EN, en, en);
	188
	189	return 0;
629509c5 KM	190	}
	191
	192	int rsnd_adg_set_convert_timing_gen2(struct rsnd_mod *mod,
	193	struct rsnd_dai *rdai,
	194	struct rsnd_dai_stream *io)
	195	{
8467dedc	196	u32 val = rsnd_adg_ssi_ws_timing_gen2(io);
629509c5 KM	197
	198	return rsnd_adg_set_src_timsel_gen2(rdai, mod, io, val);
	199	}
	200
28dc4b63 KM	201	int rsnd_adg_set_convert_clk_gen1(struct rsnd_priv *priv,
	202	struct rsnd_mod *mod,
	203	unsigned int src_rate,
	204	unsigned int dst_rate)
ef749400 KM	205	{
	206	struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
	207	struct device *dev = rsnd_priv_to_dev(priv);
	208	int idx, sel, div, shift;
	209	u32 mask, val;
	210	int id = rsnd_mod_id(mod);
	211	unsigned int sel_rate [] = {
	212	clk_get_rate(adg->clk[CLKA]), /* 000: CLKA */
	213	clk_get_rate(adg->clk[CLKB]), /* 001: CLKB */
	214	clk_get_rate(adg->clk[CLKC]), /* 010: CLKC */
	215	0, /* 011: MLBCLK (not used) */
	216	adg->rbga_rate_for_441khz_div_6,/* 100: RBGA */
	217	adg->rbgb_rate_for_48khz_div_6, /* 101: RBGB */
	218	};
	219
	220	/* find div (= 1/128, 1/256, 1/512, 1/1024, 1/2048 */
	221	for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
	222	for (div = 128, idx = 0;
	223	div <= 2048;
	224	div *= 2, idx++) {
	225	if (src_rate == sel_rate[sel] / div) {
	226	val = (idx << 4) \| sel;
	227	goto find_rate;
	228	}
	229	}
	230	}
	231	dev_err(dev, "can't find convert src clk\n");
	232	return -EINVAL;
	233
	234	find_rate:
	235	shift = (id % 4) * 8;
	236	mask = 0xFF << shift;
	237	val = val << shift;
	238
	239	dev_dbg(dev, "adg convert src clk = %02x\n", val);
	240
	241	switch (id / 4) {
	242	case 0:
	243	rsnd_mod_bset(mod, AUDIO_CLK_SEL3, mask, val);
	244	break;
	245	case 1:
	246	rsnd_mod_bset(mod, AUDIO_CLK_SEL4, mask, val);
	247	break;
	248	case 2:
	249	rsnd_mod_bset(mod, AUDIO_CLK_SEL5, mask, val);
	250	break;
	251	}
	252
	253	/*
	254	* Gen1 doesn't need dst_rate settings,
	255	* since it uses SSI WS pin.
	256	* see also rsnd_src_set_route_if_gen1()
	257	*/
	258
	259	return 0;
	260	}
	261
e337853e	262	static void rsnd_adg_set_ssi_clk(struct rsnd_mod *mod, u32 val)
dfc9403b	263	{
e337853e KM	264	int id = rsnd_mod_id(mod);
	265	int shift = (id % 4) * 8;
	266	u32 mask = 0xFF << shift;
	267
	268	val = val << shift;
dfc9403b KM	269
	270	/*
	271	* SSI 8 is not connected to ADG.
	272	* it works with SSI 7
	273	*/
	274	if (id == 8)
e337853e KM	275	return;
	276
	277	switch (id / 4) {
	278	case 0:
	279	rsnd_mod_bset(mod, AUDIO_CLK_SEL0, mask, val);
	280	break;
	281	case 1:
	282	rsnd_mod_bset(mod, AUDIO_CLK_SEL1, mask, val);
	283	break;
	284	case 2:
	285	rsnd_mod_bset(mod, AUDIO_CLK_SEL2, mask, val);
	286	break;
	287	}
dfc9403b KM	288	}
	289
	290	int rsnd_adg_ssi_clk_stop(struct rsnd_mod *mod)
	291	{
dfc9403b KM	292	/*
	293	* "mod" = "ssi" here.
	294	* we can get "ssi id" from mod
	295	*/
e337853e	296	rsnd_adg_set_ssi_clk(mod, 0);
dfc9403b KM	297
	298	return 0;
	299	}
	300
	301	int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *mod, unsigned int rate)
	302	{
	303	struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
	304	struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
	305	struct device *dev = rsnd_priv_to_dev(priv);
	306	struct clk *clk;
e337853e	307	int i;
dfc9403b KM	308	u32 data;
	309	int sel_table[] = {
	310	[CLKA] = 0x1,
	311	[CLKB] = 0x2,
	312	[CLKC] = 0x3,
	313	[CLKI] = 0x0,
	314	};
	315
	316	dev_dbg(dev, "request clock = %d\n", rate);
	317
	318	/*
	319	* find suitable clock from
	320	* AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
	321	*/
	322	data = 0;
	323	for_each_rsnd_clk(clk, adg, i) {
	324	if (rate == clk_get_rate(clk)) {
	325	data = sel_table[i];
	326	goto found_clock;
	327	}
	328	}
	329
	330	/*
	331	* find 1/6 clock from BRGA/BRGB
	332	*/
7808aa30	333	if (rate == adg->rbga_rate_for_441khz_div_6) {
dfc9403b KM	334	data = 0x10;
	335	goto found_clock;
	336	}
	337
7808aa30	338	if (rate == adg->rbgb_rate_for_48khz_div_6) {
dfc9403b KM	339	data = 0x20;
	340	goto found_clock;
	341	}
	342
	343	return -EIO;
	344
	345	found_clock:
	346
efeb970e KM	347	/* see rsnd_adg_ssi_clk_init() */
	348	rsnd_mod_bset(mod, SSICKR, 0x00FF0000, adg->ckr);
	349	rsnd_mod_write(mod, BRRA, 0x00000002); /* 1/6 */
	350	rsnd_mod_write(mod, BRRB, 0x00000002); /* 1/6 */
	351
dfc9403b KM	352	/*
	353	* This "mod" = "ssi" here.
	354	* we can get "ssi id" from mod
	355	*/
e337853e	356	rsnd_adg_set_ssi_clk(mod, data);
dfc9403b	357
e337853e KM	358	dev_dbg(dev, "ADG: ssi%d selects clk%d = %d",
e337853e KM	359	rsnd_mod_id(mod), i, rate);
dfc9403b KM	360
	361	return 0;
	362	}
	363
	364	static void rsnd_adg_ssi_clk_init(struct rsnd_priv priv, struct rsnd_adg adg)
	365	{
	366	struct clk *clk;
	367	unsigned long rate;
	368	u32 ckr;
	369	int i;
	370	int brg_table[] = {
	371	[CLKA] = 0x0,
	372	[CLKB] = 0x1,
	373	[CLKC] = 0x4,
	374	[CLKI] = 0x2,
	375	};
	376
	377	/*
	378	* This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
	379	* have 44.1kHz or 48kHz base clocks for now.
	380	*
	381	* SSI itself can divide parent clock by 1/1 - 1/16
	382	* So, BRGA outputs 44.1kHz base parent clock 1/32,
	383	* and, BRGB outputs 48.0kHz base parent clock 1/32 here.
	384	* see
	385	* rsnd_adg_ssi_clk_try_start()
	386	*/
	387	ckr = 0;
7808aa30 KM	388	adg->rbga_rate_for_441khz_div_6 = 0;
7808aa30 KM	389	adg->rbgb_rate_for_48khz_div_6 = 0;
dfc9403b KM	390	for_each_rsnd_clk(clk, adg, i) {
	391	rate = clk_get_rate(clk);
	392
	393	if (0 == rate) /* not used */
	394	continue;
	395
	396	/* RBGA */
7808aa30 KM	397	if (!adg->rbga_rate_for_441khz_div_6 && (0 == rate % 44100)) {
7808aa30 KM	398	adg->rbga_rate_for_441khz_div_6 = rate / 6;
dfc9403b KM	399	ckr \|= brg_table[i] << 20;
	400	}
	401
	402	/* RBGB */
7808aa30 KM	403	if (!adg->rbgb_rate_for_48khz_div_6 && (0 == rate % 48000)) {
7808aa30 KM	404	adg->rbgb_rate_for_48khz_div_6 = rate / 6;
dfc9403b KM	405	ckr \|= brg_table[i] << 16;
	406	}
	407	}
	408
efeb970e	409	adg->ckr = ckr;
dfc9403b KM	410	}
	411
	412	int rsnd_adg_probe(struct platform_device *pdev,
90e8e50f	413	const struct rsnd_of_data *of_data,
dfc9403b KM	414	struct rsnd_priv *priv)
	415	{
	416	struct rsnd_adg *adg;
	417	struct device *dev = rsnd_priv_to_dev(priv);
5e392ea0	418	struct clk *clk;
dfc9403b KM	419	int i;
	420
	421	adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
	422	if (!adg) {
	423	dev_err(dev, "ADG allocate failed\n");
	424	return -ENOMEM;
	425	}
	426
468be93e KM	427	adg->clk[CLKA] = devm_clk_get(dev, "clk_a");
	428	adg->clk[CLKB] = devm_clk_get(dev, "clk_b");
	429	adg->clk[CLKC] = devm_clk_get(dev, "clk_c");
	430	adg->clk[CLKI] = devm_clk_get(dev, "clk_i");
8691d074	431
5e392ea0 KM	432	for_each_rsnd_clk(clk, adg, i)
5e392ea0 KM	433	dev_dbg(dev, "clk %d : %p\n", i, clk);
dfc9403b KM	434
	435	rsnd_adg_ssi_clk_init(priv, adg);
	436
	437	priv->adg = adg;
	438
	439	dev_dbg(dev, "adg probed\n");
	440
	441	return 0;
	442	}