[deliverable/linux.git] / sound / soc / tegra / tegra20_i2s.h

/*
 * tegra20_i2s.h - Definitions for Tegra20 I2S driver
 *
 * Author: Stephen Warren <swarren@nvidia.com>
 * Copyright (C) 2010,2012 - NVIDIA, Inc.
 *
 * Based on code copyright/by:
 *
 * Copyright (c) 2009-2010, NVIDIA Corporation.
 * Scott Peterson <speterson@nvidia.com>
 *
 * Copyright (C) 2010 Google, Inc.
 * Iliyan Malchev <malchev@google.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#ifndef __TEGRA20_I2S_H__
#define __TEGRA20_I2S_H__

#include "tegra_pcm.h"

/* Register offsets from TEGRA20_I2S1_BASE and TEGRA20_I2S2_BASE */

#define TEGRA20_I2S_CTRL				0x00
#define TEGRA20_I2S_STATUS				0x04
#define TEGRA20_I2S_TIMING				0x08
#define TEGRA20_I2S_FIFO_SCR				0x0c
#define TEGRA20_I2S_PCM_CTRL				0x10
#define TEGRA20_I2S_NW_CTRL				0x14
#define TEGRA20_I2S_TDM_CTRL				0x20
#define TEGRA20_I2S_TDM_TX_RX_CTRL			0x24
#define TEGRA20_I2S_FIFO1				0x40
#define TEGRA20_I2S_FIFO2				0x80

/* Fields in TEGRA20_I2S_CTRL */

#define TEGRA20_I2S_CTRL_FIFO2_TX_ENABLE		(1 << 30)
#define TEGRA20_I2S_CTRL_FIFO1_ENABLE			(1 << 29)
#define TEGRA20_I2S_CTRL_FIFO2_ENABLE			(1 << 28)
#define TEGRA20_I2S_CTRL_FIFO1_RX_ENABLE		(1 << 27)
#define TEGRA20_I2S_CTRL_FIFO_LPBK_ENABLE		(1 << 26)
#define TEGRA20_I2S_CTRL_MASTER_ENABLE			(1 << 25)

#define TEGRA20_I2S_LRCK_LEFT_LOW				0
#define TEGRA20_I2S_LRCK_RIGHT_LOW			1

#define TEGRA20_I2S_CTRL_LRCK_SHIFT			24
#define TEGRA20_I2S_CTRL_LRCK_MASK			(1                          << TEGRA20_I2S_CTRL_LRCK_SHIFT)
#define TEGRA20_I2S_CTRL_LRCK_L_LOW			(TEGRA20_I2S_LRCK_LEFT_LOW  << TEGRA20_I2S_CTRL_LRCK_SHIFT)
#define TEGRA20_I2S_CTRL_LRCK_R_LOW			(TEGRA20_I2S_LRCK_RIGHT_LOW << TEGRA20_I2S_CTRL_LRCK_SHIFT)

#define TEGRA20_I2S_BIT_FORMAT_I2S			0
#define TEGRA20_I2S_BIT_FORMAT_RJM			1
#define TEGRA20_I2S_BIT_FORMAT_LJM			2
#define TEGRA20_I2S_BIT_FORMAT_DSP			3

#define TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT		10
#define TEGRA20_I2S_CTRL_BIT_FORMAT_MASK		(3                          << TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT)
#define TEGRA20_I2S_CTRL_BIT_FORMAT_I2S			(TEGRA20_I2S_BIT_FORMAT_I2S << TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT)
#define TEGRA20_I2S_CTRL_BIT_FORMAT_RJM			(TEGRA20_I2S_BIT_FORMAT_RJM << TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT)
#define TEGRA20_I2S_CTRL_BIT_FORMAT_LJM			(TEGRA20_I2S_BIT_FORMAT_LJM << TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT)
#define TEGRA20_I2S_CTRL_BIT_FORMAT_DSP			(TEGRA20_I2S_BIT_FORMAT_DSP << TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT)

#define TEGRA20_I2S_BIT_SIZE_16				0
#define TEGRA20_I2S_BIT_SIZE_20				1
#define TEGRA20_I2S_BIT_SIZE_24				2
#define TEGRA20_I2S_BIT_SIZE_32				3

#define TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT			8
#define TEGRA20_I2S_CTRL_BIT_SIZE_MASK			(3                       << TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT)
#define TEGRA20_I2S_CTRL_BIT_SIZE_16			(TEGRA20_I2S_BIT_SIZE_16 << TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT)
#define TEGRA20_I2S_CTRL_BIT_SIZE_20			(TEGRA20_I2S_BIT_SIZE_20 << TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT)
#define TEGRA20_I2S_CTRL_BIT_SIZE_24			(TEGRA20_I2S_BIT_SIZE_24 << TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT)
#define TEGRA20_I2S_CTRL_BIT_SIZE_32			(TEGRA20_I2S_BIT_SIZE_32 << TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT)

#define TEGRA20_I2S_FIFO_16_LSB				0
#define TEGRA20_I2S_FIFO_20_LSB				1
#define TEGRA20_I2S_FIFO_24_LSB				2
#define TEGRA20_I2S_FIFO_32				3
#define TEGRA20_I2S_FIFO_PACKED				7

#define TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT		4
#define TEGRA20_I2S_CTRL_FIFO_FORMAT_MASK		(7                       << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)
#define TEGRA20_I2S_CTRL_FIFO_FORMAT_16_LSB		(TEGRA20_I2S_FIFO_16_LSB << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)
#define TEGRA20_I2S_CTRL_FIFO_FORMAT_20_LSB		(TEGRA20_I2S_FIFO_20_LSB << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)
#define TEGRA20_I2S_CTRL_FIFO_FORMAT_24_LSB		(TEGRA20_I2S_FIFO_24_LSB << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)
#define TEGRA20_I2S_CTRL_FIFO_FORMAT_32			(TEGRA20_I2S_FIFO_32     << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)
#define TEGRA20_I2S_CTRL_FIFO_FORMAT_PACKED		(TEGRA20_I2S_FIFO_PACKED << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)

#define TEGRA20_I2S_CTRL_IE_FIFO1_ERR			(1 << 3)
#define TEGRA20_I2S_CTRL_IE_FIFO2_ERR			(1 << 2)
#define TEGRA20_I2S_CTRL_QE_FIFO1			(1 << 1)
#define TEGRA20_I2S_CTRL_QE_FIFO2			(1 << 0)

/* Fields in TEGRA20_I2S_STATUS */

#define TEGRA20_I2S_STATUS_FIFO1_RDY			(1 << 31)
#define TEGRA20_I2S_STATUS_FIFO2_RDY			(1 << 30)
#define TEGRA20_I2S_STATUS_FIFO1_BSY			(1 << 29)
#define TEGRA20_I2S_STATUS_FIFO2_BSY			(1 << 28)
#define TEGRA20_I2S_STATUS_FIFO1_ERR			(1 << 3)
#define TEGRA20_I2S_STATUS_FIFO2_ERR			(1 << 2)
#define TEGRA20_I2S_STATUS_QS_FIFO1			(1 << 1)
#define TEGRA20_I2S_STATUS_QS_FIFO2			(1 << 0)

/* Fields in TEGRA20_I2S_TIMING */

#define TEGRA20_I2S_TIMING_NON_SYM_ENABLE		(1 << 12)
#define TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT	0
#define TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US	0x7ff
#define TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK	(TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US << TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT)

/* Fields in TEGRA20_I2S_FIFO_SCR */

#define TEGRA20_I2S_FIFO_SCR_FIFO2_FULL_EMPTY_COUNT_SHIFT	24
#define TEGRA20_I2S_FIFO_SCR_FIFO1_FULL_EMPTY_COUNT_SHIFT	16
#define TEGRA20_I2S_FIFO_SCR_FIFO_FULL_EMPTY_COUNT_MASK		0x3f

#define TEGRA20_I2S_FIFO_SCR_FIFO2_CLR			(1 << 12)
#define TEGRA20_I2S_FIFO_SCR_FIFO1_CLR			(1 << 8)

#define TEGRA20_I2S_FIFO_ATN_LVL_ONE_SLOT		0
#define TEGRA20_I2S_FIFO_ATN_LVL_FOUR_SLOTS		1
#define TEGRA20_I2S_FIFO_ATN_LVL_EIGHT_SLOTS		2
#define TEGRA20_I2S_FIFO_ATN_LVL_TWELVE_SLOTS		3

#define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT	4
#define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_MASK		(3 << TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT)
#define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_ONE_SLOT	(TEGRA20_I2S_FIFO_ATN_LVL_ONE_SLOT     << TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT)
#define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS	(TEGRA20_I2S_FIFO_ATN_LVL_FOUR_SLOTS   << TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT)
#define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_EIGHT_SLOTS	(TEGRA20_I2S_FIFO_ATN_LVL_EIGHT_SLOTS  << TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT)
#define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_TWELVE_SLOTS	(TEGRA20_I2S_FIFO_ATN_LVL_TWELVE_SLOTS << TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT)

#define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT	0
#define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_MASK		(3 << TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT)
#define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_ONE_SLOT	(TEGRA20_I2S_FIFO_ATN_LVL_ONE_SLOT     << TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT)
#define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS	(TEGRA20_I2S_FIFO_ATN_LVL_FOUR_SLOTS   << TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT)
#define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_EIGHT_SLOTS	(TEGRA20_I2S_FIFO_ATN_LVL_EIGHT_SLOTS  << TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT)
#define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_TWELVE_SLOTS	(TEGRA20_I2S_FIFO_ATN_LVL_TWELVE_SLOTS << TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT)

struct tegra20_i2s {
	struct snd_soc_dai_driver dai;
	struct clk *clk_i2s;
	struct snd_dmaengine_dai_dma_data capture_dma_data;
	struct snd_dmaengine_dai_dma_data playback_dma_data;
	struct regmap *regmap;
};

#endif
Commit	Line	Data
71f78e22	1	/*
ef280d39	2	* tegra20_i2s.h - Definitions for Tegra20 I2S driver
71f78e22 SW	3	*
71f78e22 SW	4	* Author: Stephen Warren <swarren@nvidia.com>
896637ac	5	* Copyright (C) 2010,2012 - NVIDIA, Inc.
71f78e22 SW	6	*
	7	* Based on code copyright/by:
	8	*
	9	* Copyright (c) 2009-2010, NVIDIA Corporation.
	10	* Scott Peterson <speterson@nvidia.com>
	11	*
	12	* Copyright (C) 2010 Google, Inc.
	13	* Iliyan Malchev <malchev@google.com>
	14	*
	15	* This program is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License
	17	* version 2 as published by the Free Software Foundation.
	18	*
	19	* This program is distributed in the hope that it will be useful, but
	20	* WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	22	* General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	27	* 02110-1301 USA
	28	*
	29	*/
	30
896637ac SW	31	#ifndef __TEGRA20_I2S_H__
896637ac SW	32	#define __TEGRA20_I2S_H__
71f78e22 SW	33
	34	#include "tegra_pcm.h"
	35
896637ac SW	36	/* Register offsets from TEGRA20_I2S1_BASE and TEGRA20_I2S2_BASE */
	37
	38	#define TEGRA20_I2S_CTRL 0x00
	39	#define TEGRA20_I2S_STATUS 0x04
	40	#define TEGRA20_I2S_TIMING 0x08
	41	#define TEGRA20_I2S_FIFO_SCR 0x0c
	42	#define TEGRA20_I2S_PCM_CTRL 0x10
	43	#define TEGRA20_I2S_NW_CTRL 0x14
	44	#define TEGRA20_I2S_TDM_CTRL 0x20
	45	#define TEGRA20_I2S_TDM_TX_RX_CTRL 0x24
	46	#define TEGRA20_I2S_FIFO1 0x40
	47	#define TEGRA20_I2S_FIFO2 0x80
	48
	49	/* Fields in TEGRA20_I2S_CTRL */
	50
	51	#define TEGRA20_I2S_CTRL_FIFO2_TX_ENABLE (1 << 30)
	52	#define TEGRA20_I2S_CTRL_FIFO1_ENABLE (1 << 29)
	53	#define TEGRA20_I2S_CTRL_FIFO2_ENABLE (1 << 28)
	54	#define TEGRA20_I2S_CTRL_FIFO1_RX_ENABLE (1 << 27)
	55	#define TEGRA20_I2S_CTRL_FIFO_LPBK_ENABLE (1 << 26)
	56	#define TEGRA20_I2S_CTRL_MASTER_ENABLE (1 << 25)
	57
	58	#define TEGRA20_I2S_LRCK_LEFT_LOW 0
	59	#define TEGRA20_I2S_LRCK_RIGHT_LOW 1
	60
	61	#define TEGRA20_I2S_CTRL_LRCK_SHIFT 24
	62	#define TEGRA20_I2S_CTRL_LRCK_MASK (1 << TEGRA20_I2S_CTRL_LRCK_SHIFT)
	63	#define TEGRA20_I2S_CTRL_LRCK_L_LOW (TEGRA20_I2S_LRCK_LEFT_LOW << TEGRA20_I2S_CTRL_LRCK_SHIFT)
	64	#define TEGRA20_I2S_CTRL_LRCK_R_LOW (TEGRA20_I2S_LRCK_RIGHT_LOW << TEGRA20_I2S_CTRL_LRCK_SHIFT)
	65
	66	#define TEGRA20_I2S_BIT_FORMAT_I2S 0
	67	#define TEGRA20_I2S_BIT_FORMAT_RJM 1
	68	#define TEGRA20_I2S_BIT_FORMAT_LJM 2
	69	#define TEGRA20_I2S_BIT_FORMAT_DSP 3
	70
	71	#define TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT 10
	72	#define TEGRA20_I2S_CTRL_BIT_FORMAT_MASK (3 << TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT)
	73	#define TEGRA20_I2S_CTRL_BIT_FORMAT_I2S (TEGRA20_I2S_BIT_FORMAT_I2S << TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT)
	74	#define TEGRA20_I2S_CTRL_BIT_FORMAT_RJM (TEGRA20_I2S_BIT_FORMAT_RJM << TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT)
	75	#define TEGRA20_I2S_CTRL_BIT_FORMAT_LJM (TEGRA20_I2S_BIT_FORMAT_LJM << TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT)
	76	#define TEGRA20_I2S_CTRL_BIT_FORMAT_DSP (TEGRA20_I2S_BIT_FORMAT_DSP << TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT)
	77
	78	#define TEGRA20_I2S_BIT_SIZE_16 0
	79	#define TEGRA20_I2S_BIT_SIZE_20 1
	80	#define TEGRA20_I2S_BIT_SIZE_24 2
	81	#define TEGRA20_I2S_BIT_SIZE_32 3
	82
	83	#define TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT 8
	84	#define TEGRA20_I2S_CTRL_BIT_SIZE_MASK (3 << TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT)
	85	#define TEGRA20_I2S_CTRL_BIT_SIZE_16 (TEGRA20_I2S_BIT_SIZE_16 << TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT)
	86	#define TEGRA20_I2S_CTRL_BIT_SIZE_20 (TEGRA20_I2S_BIT_SIZE_20 << TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT)
	87	#define TEGRA20_I2S_CTRL_BIT_SIZE_24 (TEGRA20_I2S_BIT_SIZE_24 << TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT)
	88	#define TEGRA20_I2S_CTRL_BIT_SIZE_32 (TEGRA20_I2S_BIT_SIZE_32 << TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT)
	89
	90	#define TEGRA20_I2S_FIFO_16_LSB 0
	91	#define TEGRA20_I2S_FIFO_20_LSB 1
	92	#define TEGRA20_I2S_FIFO_24_LSB 2
	93	#define TEGRA20_I2S_FIFO_32 3
	94	#define TEGRA20_I2S_FIFO_PACKED 7
	95
	96	#define TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT 4
	97	#define TEGRA20_I2S_CTRL_FIFO_FORMAT_MASK (7 << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)
	98	#define TEGRA20_I2S_CTRL_FIFO_FORMAT_16_LSB (TEGRA20_I2S_FIFO_16_LSB << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)
	99	#define TEGRA20_I2S_CTRL_FIFO_FORMAT_20_LSB (TEGRA20_I2S_FIFO_20_LSB << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)
100	#define TEGRA20_I2S_CTRL_FIFO_FORMAT_24_LSB (TEGRA20_I2S_FIFO_24_LSB << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)
101	#define TEGRA20_I2S_CTRL_FIFO_FORMAT_32 (TEGRA20_I2S_FIFO_32 << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)
102	#define TEGRA20_I2S_CTRL_FIFO_FORMAT_PACKED (TEGRA20_I2S_FIFO_PACKED << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)
103
104	#define TEGRA20_I2S_CTRL_IE_FIFO1_ERR (1 << 3)
105	#define TEGRA20_I2S_CTRL_IE_FIFO2_ERR (1 << 2)
106	#define TEGRA20_I2S_CTRL_QE_FIFO1 (1 << 1)
107	#define TEGRA20_I2S_CTRL_QE_FIFO2 (1 << 0)
108
109	/* Fields in TEGRA20_I2S_STATUS */
110
111	#define TEGRA20_I2S_STATUS_FIFO1_RDY (1 << 31)
112	#define TEGRA20_I2S_STATUS_FIFO2_RDY (1 << 30)
113	#define TEGRA20_I2S_STATUS_FIFO1_BSY (1 << 29)
114	#define TEGRA20_I2S_STATUS_FIFO2_BSY (1 << 28)
115	#define TEGRA20_I2S_STATUS_FIFO1_ERR (1 << 3)
116	#define TEGRA20_I2S_STATUS_FIFO2_ERR (1 << 2)
117	#define TEGRA20_I2S_STATUS_QS_FIFO1 (1 << 1)
118	#define TEGRA20_I2S_STATUS_QS_FIFO2 (1 << 0)
119
120	/* Fields in TEGRA20_I2S_TIMING */
121
122	#define TEGRA20_I2S_TIMING_NON_SYM_ENABLE (1 << 12)
123	#define TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT 0
0af18c5c	124	#define TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US 0x7ff
896637ac SW	125	#define TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK (TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US << TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT)
	126
	127	/* Fields in TEGRA20_I2S_FIFO_SCR */
	128
	129	#define TEGRA20_I2S_FIFO_SCR_FIFO2_FULL_EMPTY_COUNT_SHIFT 24
	130	#define TEGRA20_I2S_FIFO_SCR_FIFO1_FULL_EMPTY_COUNT_SHIFT 16
	131	#define TEGRA20_I2S_FIFO_SCR_FIFO_FULL_EMPTY_COUNT_MASK 0x3f
	132
	133	#define TEGRA20_I2S_FIFO_SCR_FIFO2_CLR (1 << 12)
	134	#define TEGRA20_I2S_FIFO_SCR_FIFO1_CLR (1 << 8)
	135
	136	#define TEGRA20_I2S_FIFO_ATN_LVL_ONE_SLOT 0
	137	#define TEGRA20_I2S_FIFO_ATN_LVL_FOUR_SLOTS 1
	138	#define TEGRA20_I2S_FIFO_ATN_LVL_EIGHT_SLOTS 2
	139	#define TEGRA20_I2S_FIFO_ATN_LVL_TWELVE_SLOTS 3
	140
	141	#define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT 4
	142	#define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_MASK (3 << TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT)
	143	#define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_ONE_SLOT (TEGRA20_I2S_FIFO_ATN_LVL_ONE_SLOT << TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT)
	144	#define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS (TEGRA20_I2S_FIFO_ATN_LVL_FOUR_SLOTS << TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT)
	145	#define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_EIGHT_SLOTS (TEGRA20_I2S_FIFO_ATN_LVL_EIGHT_SLOTS << TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT)
	146	#define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_TWELVE_SLOTS (TEGRA20_I2S_FIFO_ATN_LVL_TWELVE_SLOTS << TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT)
	147
	148	#define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT 0
	149	#define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_MASK (3 << TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT)
	150	#define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_ONE_SLOT (TEGRA20_I2S_FIFO_ATN_LVL_ONE_SLOT << TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT)
	151	#define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS (TEGRA20_I2S_FIFO_ATN_LVL_FOUR_SLOTS << TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT)
	152	#define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_EIGHT_SLOTS (TEGRA20_I2S_FIFO_ATN_LVL_EIGHT_SLOTS << TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT)
	153	#define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_TWELVE_SLOTS (TEGRA20_I2S_FIFO_ATN_LVL_TWELVE_SLOTS << TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT)
	154
	155	struct tegra20_i2s {
d4a2eca7	156	struct snd_soc_dai_driver dai;
71f78e22	157	struct clk *clk_i2s;
3489d506 LPC	158	struct snd_dmaengine_dai_dma_data capture_dma_data;
3489d506 LPC	159	struct snd_dmaengine_dai_dma_data playback_dma_data;
c1607416	160	struct regmap *regmap;
71f78e22 SW	161	};
	162
	163	#endif