[deliverable/linux.git] / sound / soc / tegra / tegra20_spdif.c

/*
 * tegra20_spdif.c - Tegra20 SPDIF driver
 *
 * Author: Stephen Warren <swarren@nvidia.com>
 * Copyright (C) 2011-2012 - NVIDIA, Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#include <linux/clk.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/dmaengine_pcm.h>

#include "tegra20_spdif.h"

#define DRV_NAME "tegra20-spdif"

static int tegra20_spdif_runtime_suspend(struct device *dev)
{
	struct tegra20_spdif *spdif = dev_get_drvdata(dev);

	clk_disable_unprepare(spdif->clk_spdif_out);

	return 0;
}

static int tegra20_spdif_runtime_resume(struct device *dev)
{
	struct tegra20_spdif *spdif = dev_get_drvdata(dev);
	int ret;

	ret = clk_prepare_enable(spdif->clk_spdif_out);
	if (ret) {
		dev_err(dev, "clk_enable failed: %d\n", ret);
		return ret;
	}

	return 0;
}

static int tegra20_spdif_hw_params(struct snd_pcm_substream *substream,
				struct snd_pcm_hw_params *params,
				struct snd_soc_dai *dai)
{
	struct device *dev = dai->dev;
	struct tegra20_spdif *spdif = snd_soc_dai_get_drvdata(dai);
	unsigned int mask, val;
	int ret, spdifclock;

	mask = TEGRA20_SPDIF_CTRL_PACK |
	       TEGRA20_SPDIF_CTRL_BIT_MODE_MASK;
	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S16_LE:
		val = TEGRA20_SPDIF_CTRL_PACK |
		      TEGRA20_SPDIF_CTRL_BIT_MODE_16BIT;
		break;
	default:
		return -EINVAL;
	}

	regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL, mask, val);

	switch (params_rate(params)) {
	case 32000:
		spdifclock = 4096000;
		break;
	case 44100:
		spdifclock = 5644800;
		break;
	case 48000:
		spdifclock = 6144000;
		break;
	case 88200:
		spdifclock = 11289600;
		break;
	case 96000:
		spdifclock = 12288000;
		break;
	case 176400:
		spdifclock = 22579200;
		break;
	case 192000:
		spdifclock = 24576000;
		break;
	default:
		return -EINVAL;
	}

	ret = clk_set_rate(spdif->clk_spdif_out, spdifclock);
	if (ret) {
		dev_err(dev, "Can't set SPDIF clock rate: %d\n", ret);
		return ret;
	}

	return 0;
}

static void tegra20_spdif_start_playback(struct tegra20_spdif *spdif)
{
	regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL,
			   TEGRA20_SPDIF_CTRL_TX_EN,
			   TEGRA20_SPDIF_CTRL_TX_EN);
}

static void tegra20_spdif_stop_playback(struct tegra20_spdif *spdif)
{
	regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL,
			   TEGRA20_SPDIF_CTRL_TX_EN, 0);
}

static int tegra20_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
				struct snd_soc_dai *dai)
{
	struct tegra20_spdif *spdif = snd_soc_dai_get_drvdata(dai);

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	case SNDRV_PCM_TRIGGER_RESUME:
		tegra20_spdif_start_playback(spdif);
		break;
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	case SNDRV_PCM_TRIGGER_SUSPEND:
		tegra20_spdif_stop_playback(spdif);
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static int tegra20_spdif_probe(struct snd_soc_dai *dai)
{
	struct tegra20_spdif *spdif = snd_soc_dai_get_drvdata(dai);

	dai->capture_dma_data = NULL;
	dai->playback_dma_data = &spdif->playback_dma_data;

	return 0;
}

static const struct snd_soc_dai_ops tegra20_spdif_dai_ops = {
	.hw_params	= tegra20_spdif_hw_params,
	.trigger	= tegra20_spdif_trigger,
};

static struct snd_soc_dai_driver tegra20_spdif_dai = {
	.name = DRV_NAME,
	.probe = tegra20_spdif_probe,
	.playback = {
		.stream_name = "Playback",
		.channels_min = 2,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
				SNDRV_PCM_RATE_48000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,
	},
	.ops = &tegra20_spdif_dai_ops,
};

static bool tegra20_spdif_wr_rd_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case TEGRA20_SPDIF_CTRL:
	case TEGRA20_SPDIF_STATUS:
	case TEGRA20_SPDIF_STROBE_CTRL:
	case TEGRA20_SPDIF_DATA_FIFO_CSR:
	case TEGRA20_SPDIF_DATA_OUT:
	case TEGRA20_SPDIF_DATA_IN:
	case TEGRA20_SPDIF_CH_STA_RX_A:
	case TEGRA20_SPDIF_CH_STA_RX_B:
	case TEGRA20_SPDIF_CH_STA_RX_C:
	case TEGRA20_SPDIF_CH_STA_RX_D:
	case TEGRA20_SPDIF_CH_STA_RX_E:
	case TEGRA20_SPDIF_CH_STA_RX_F:
	case TEGRA20_SPDIF_CH_STA_TX_A:
	case TEGRA20_SPDIF_CH_STA_TX_B:
	case TEGRA20_SPDIF_CH_STA_TX_C:
	case TEGRA20_SPDIF_CH_STA_TX_D:
	case TEGRA20_SPDIF_CH_STA_TX_E:
	case TEGRA20_SPDIF_CH_STA_TX_F:
	case TEGRA20_SPDIF_USR_STA_RX_A:
	case TEGRA20_SPDIF_USR_DAT_TX_A:
		return true;
	default:
		return false;
	};
}

static bool tegra20_spdif_volatile_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case TEGRA20_SPDIF_STATUS:
	case TEGRA20_SPDIF_DATA_FIFO_CSR:
	case TEGRA20_SPDIF_DATA_OUT:
	case TEGRA20_SPDIF_DATA_IN:
	case TEGRA20_SPDIF_CH_STA_RX_A:
	case TEGRA20_SPDIF_CH_STA_RX_B:
	case TEGRA20_SPDIF_CH_STA_RX_C:
	case TEGRA20_SPDIF_CH_STA_RX_D:
	case TEGRA20_SPDIF_CH_STA_RX_E:
	case TEGRA20_SPDIF_CH_STA_RX_F:
	case TEGRA20_SPDIF_USR_STA_RX_A:
	case TEGRA20_SPDIF_USR_DAT_TX_A:
		return true;
	default:
		return false;
	};
}

static bool tegra20_spdif_precious_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case TEGRA20_SPDIF_DATA_OUT:
	case TEGRA20_SPDIF_DATA_IN:
	case TEGRA20_SPDIF_USR_STA_RX_A:
	case TEGRA20_SPDIF_USR_DAT_TX_A:
		return true;
	default:
		return false;
	};
}

static const struct regmap_config tegra20_spdif_regmap_config = {
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,
	.max_register = TEGRA20_SPDIF_USR_DAT_TX_A,
	.writeable_reg = tegra20_spdif_wr_rd_reg,
	.readable_reg = tegra20_spdif_wr_rd_reg,
	.volatile_reg = tegra20_spdif_volatile_reg,
	.precious_reg = tegra20_spdif_precious_reg,
	.cache_type = REGCACHE_RBTREE,
};

static int tegra20_spdif_platform_probe(struct platform_device *pdev)
{
	struct tegra20_spdif *spdif;
	struct resource *mem, *memregion, *dmareq;
	void __iomem *regs;
	int ret;

	spdif = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_spdif),
			     GFP_KERNEL);
	if (!spdif) {
		dev_err(&pdev->dev, "Can't allocate tegra20_spdif\n");
		ret = -ENOMEM;
		goto err;
	}
	dev_set_drvdata(&pdev->dev, spdif);

	spdif->clk_spdif_out = clk_get(&pdev->dev, "spdif_out");
	if (IS_ERR(spdif->clk_spdif_out)) {
		pr_err("Can't retrieve spdif clock\n");
		ret = PTR_ERR(spdif->clk_spdif_out);
		goto err;
	}

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!mem) {
		dev_err(&pdev->dev, "No memory resource\n");
		ret = -ENODEV;
		goto err_clk_put;
	}

	dmareq = platform_get_resource(pdev, IORESOURCE_DMA, 0);
	if (!dmareq) {
		dev_err(&pdev->dev, "No DMA resource\n");
		ret = -ENODEV;
		goto err_clk_put;
	}

	memregion = devm_request_mem_region(&pdev->dev, mem->start,
					    resource_size(mem), DRV_NAME);
	if (!memregion) {
		dev_err(&pdev->dev, "Memory region already claimed\n");
		ret = -EBUSY;
		goto err_clk_put;
	}

	regs = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
	if (!regs) {
		dev_err(&pdev->dev, "ioremap failed\n");
		ret = -ENOMEM;
		goto err_clk_put;
	}

	spdif->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
					    &tegra20_spdif_regmap_config);
	if (IS_ERR(spdif->regmap)) {
		dev_err(&pdev->dev, "regmap init failed\n");
		ret = PTR_ERR(spdif->regmap);
		goto err_clk_put;
	}

	spdif->playback_dma_data.addr = mem->start + TEGRA20_SPDIF_DATA_OUT;
	spdif->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	spdif->capture_dma_data.maxburst = 4;
	spdif->playback_dma_data.slave_id = dmareq->start;

	pm_runtime_enable(&pdev->dev);
	if (!pm_runtime_enabled(&pdev->dev)) {
		ret = tegra20_spdif_runtime_resume(&pdev->dev);
		if (ret)
			goto err_pm_disable;
	}

	ret = snd_soc_register_dai(&pdev->dev, &tegra20_spdif_dai);
	if (ret) {
		dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
		ret = -ENOMEM;
		goto err_suspend;
	}

	ret = tegra_pcm_platform_register(&pdev->dev);
	if (ret) {
		dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
		goto err_unregister_dai;
	}

	return 0;

err_unregister_dai:
	snd_soc_unregister_dai(&pdev->dev);
err_suspend:
	if (!pm_runtime_status_suspended(&pdev->dev))
		tegra20_spdif_runtime_suspend(&pdev->dev);
err_pm_disable:
	pm_runtime_disable(&pdev->dev);
err_clk_put:
	clk_put(spdif->clk_spdif_out);
err:
	return ret;
}

static int tegra20_spdif_platform_remove(struct platform_device *pdev)
{
	struct tegra20_spdif *spdif = dev_get_drvdata(&pdev->dev);

	pm_runtime_disable(&pdev->dev);
	if (!pm_runtime_status_suspended(&pdev->dev))
		tegra20_spdif_runtime_suspend(&pdev->dev);

	tegra_pcm_platform_unregister(&pdev->dev);
	snd_soc_unregister_dai(&pdev->dev);

	clk_put(spdif->clk_spdif_out);

	return 0;
}

static const struct dev_pm_ops tegra20_spdif_pm_ops = {
	SET_RUNTIME_PM_OPS(tegra20_spdif_runtime_suspend,
			   tegra20_spdif_runtime_resume, NULL)
};

static struct platform_driver tegra20_spdif_driver = {
	.driver = {
		.name = DRV_NAME,
		.owner = THIS_MODULE,
		.pm = &tegra20_spdif_pm_ops,
	},
	.probe = tegra20_spdif_platform_probe,
	.remove = tegra20_spdif_platform_remove,
};

module_platform_driver(tegra20_spdif_driver);

MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
MODULE_DESCRIPTION("Tegra20 SPDIF ASoC driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRV_NAME);
Commit	Line	Data
774fec33	1	/*
ef280d39	2	* tegra20_spdif.c - Tegra20 SPDIF driver
774fec33 SW	3	*
774fec33 SW	4	* Author: Stephen Warren <swarren@nvidia.com>
518de86b	5	* Copyright (C) 2011-2012 - NVIDIA, Inc.
774fec33 SW	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License
	9	* version 2 as published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful, but
	12	* WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	19	* 02110-1301 USA
	20	*
	21	*/
	22
	23	#include <linux/clk.h>
774fec33	24	#include <linux/device.h>
7613c508 SW	25	#include <linux/io.h>
7613c508 SW	26	#include <linux/module.h>
774fec33	27	#include <linux/platform_device.h>
82ef0ae4	28	#include <linux/pm_runtime.h>
5939ae74	29	#include <linux/regmap.h>
774fec33	30	#include <linux/slab.h>
774fec33 SW	31	#include <sound/core.h>
	32	#include <sound/pcm.h>
	33	#include <sound/pcm_params.h>
	34	#include <sound/soc.h>
3489d506	35	#include <sound/dmaengine_pcm.h>
774fec33	36
ef280d39	37	#include "tegra20_spdif.h"
774fec33	38
896637ac	39	#define DRV_NAME "tegra20-spdif"
774fec33	40
82ef0ae4 SW	41	static int tegra20_spdif_runtime_suspend(struct device *dev)
	42	{
	43	struct tegra20_spdif *spdif = dev_get_drvdata(dev);
	44
65d2bdd3	45	clk_disable_unprepare(spdif->clk_spdif_out);
82ef0ae4 SW	46
	47	return 0;
	48	}
	49
	50	static int tegra20_spdif_runtime_resume(struct device *dev)
	51	{
	52	struct tegra20_spdif *spdif = dev_get_drvdata(dev);
	53	int ret;
	54
65d2bdd3	55	ret = clk_prepare_enable(spdif->clk_spdif_out);
82ef0ae4 SW	56	if (ret) {
	57	dev_err(dev, "clk_enable failed: %d\n", ret);
	58	return ret;
	59	}
	60
	61	return 0;
	62	}
	63
896637ac	64	static int tegra20_spdif_hw_params(struct snd_pcm_substream *substream,
774fec33 SW	65	struct snd_pcm_hw_params *params,
	66	struct snd_soc_dai *dai)
	67	{
c92a40e3	68	struct device *dev = dai->dev;
896637ac	69	struct tegra20_spdif *spdif = snd_soc_dai_get_drvdata(dai);
0f163546	70	unsigned int mask, val;
4b8713fd	71	int ret, spdifclock;
774fec33	72
0f163546 SW	73	mask = TEGRA20_SPDIF_CTRL_PACK \|
0f163546 SW	74	TEGRA20_SPDIF_CTRL_BIT_MODE_MASK;
774fec33 SW	75	switch (params_format(params)) {
774fec33 SW	76	case SNDRV_PCM_FORMAT_S16_LE:
0f163546 SW	77	val = TEGRA20_SPDIF_CTRL_PACK \|
0f163546 SW	78	TEGRA20_SPDIF_CTRL_BIT_MODE_16BIT;
774fec33 SW	79	break;
	80	default:
	81	return -EINVAL;
	82	}
	83
0f163546 SW	84	regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL, mask, val);
0f163546 SW	85
774fec33 SW	86	switch (params_rate(params)) {
	87	case 32000:
	88	spdifclock = 4096000;
	89	break;
	90	case 44100:
	91	spdifclock = 5644800;
	92	break;
	93	case 48000:
	94	spdifclock = 6144000;
	95	break;
	96	case 88200:
	97	spdifclock = 11289600;
	98	break;
	99	case 96000:
	100	spdifclock = 12288000;
	101	break;
	102	case 176400:
	103	spdifclock = 22579200;
	104	break;
	105	case 192000:
	106	spdifclock = 24576000;
	107	break;
	108	default:
	109	return -EINVAL;
	110	}
	111
	112	ret = clk_set_rate(spdif->clk_spdif_out, spdifclock);
	113	if (ret) {
	114	dev_err(dev, "Can't set SPDIF clock rate: %d\n", ret);
	115	return ret;
	116	}
	117
	118	return 0;
	119	}
	120
896637ac	121	static void tegra20_spdif_start_playback(struct tegra20_spdif *spdif)
774fec33	122	{
0f163546 SW	123	regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL,
	124	TEGRA20_SPDIF_CTRL_TX_EN,
	125	TEGRA20_SPDIF_CTRL_TX_EN);
774fec33 SW	126	}
774fec33 SW	127
896637ac	128	static void tegra20_spdif_stop_playback(struct tegra20_spdif *spdif)
774fec33	129	{
0f163546 SW	130	regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL,
0f163546 SW	131	TEGRA20_SPDIF_CTRL_TX_EN, 0);
774fec33 SW	132	}
774fec33 SW	133
896637ac	134	static int tegra20_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
774fec33 SW	135	struct snd_soc_dai *dai)
774fec33 SW	136	{
896637ac	137	struct tegra20_spdif *spdif = snd_soc_dai_get_drvdata(dai);
774fec33 SW	138
	139	switch (cmd) {
	140	case SNDRV_PCM_TRIGGER_START:
	141	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	142	case SNDRV_PCM_TRIGGER_RESUME:
896637ac	143	tegra20_spdif_start_playback(spdif);
774fec33 SW	144	break;
	145	case SNDRV_PCM_TRIGGER_STOP:
	146	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	147	case SNDRV_PCM_TRIGGER_SUSPEND:
896637ac	148	tegra20_spdif_stop_playback(spdif);
774fec33 SW	149	break;
	150	default:
	151	return -EINVAL;
	152	}
	153
	154	return 0;
	155	}
	156
896637ac	157	static int tegra20_spdif_probe(struct snd_soc_dai *dai)
774fec33	158	{
896637ac	159	struct tegra20_spdif *spdif = snd_soc_dai_get_drvdata(dai);
774fec33 SW	160
	161	dai->capture_dma_data = NULL;
	162	dai->playback_dma_data = &spdif->playback_dma_data;
	163
	164	return 0;
	165	}
	166
896637ac SW	167	static const struct snd_soc_dai_ops tegra20_spdif_dai_ops = {
	168	.hw_params = tegra20_spdif_hw_params,
	169	.trigger = tegra20_spdif_trigger,
774fec33 SW	170	};
774fec33 SW	171
896637ac	172	static struct snd_soc_dai_driver tegra20_spdif_dai = {
774fec33	173	.name = DRV_NAME,
896637ac	174	.probe = tegra20_spdif_probe,
774fec33	175	.playback = {
9515c101	176	.stream_name = "Playback",
774fec33 SW	177	.channels_min = 2,
	178	.channels_max = 2,
	179	.rates = SNDRV_PCM_RATE_32000 \| SNDRV_PCM_RATE_44100 \|
	180	SNDRV_PCM_RATE_48000,
	181	.formats = SNDRV_PCM_FMTBIT_S16_LE,
	182	},
896637ac	183	.ops = &tegra20_spdif_dai_ops,
774fec33 SW	184	};
774fec33 SW	185
5939ae74 SW	186	static bool tegra20_spdif_wr_rd_reg(struct device *dev, unsigned int reg)
	187	{
	188	switch (reg) {
	189	case TEGRA20_SPDIF_CTRL:
	190	case TEGRA20_SPDIF_STATUS:
	191	case TEGRA20_SPDIF_STROBE_CTRL:
	192	case TEGRA20_SPDIF_DATA_FIFO_CSR:
	193	case TEGRA20_SPDIF_DATA_OUT:
	194	case TEGRA20_SPDIF_DATA_IN:
	195	case TEGRA20_SPDIF_CH_STA_RX_A:
	196	case TEGRA20_SPDIF_CH_STA_RX_B:
	197	case TEGRA20_SPDIF_CH_STA_RX_C:
	198	case TEGRA20_SPDIF_CH_STA_RX_D:
	199	case TEGRA20_SPDIF_CH_STA_RX_E:
	200	case TEGRA20_SPDIF_CH_STA_RX_F:
	201	case TEGRA20_SPDIF_CH_STA_TX_A:
	202	case TEGRA20_SPDIF_CH_STA_TX_B:
	203	case TEGRA20_SPDIF_CH_STA_TX_C:
	204	case TEGRA20_SPDIF_CH_STA_TX_D:
	205	case TEGRA20_SPDIF_CH_STA_TX_E:
	206	case TEGRA20_SPDIF_CH_STA_TX_F:
	207	case TEGRA20_SPDIF_USR_STA_RX_A:
	208	case TEGRA20_SPDIF_USR_DAT_TX_A:
	209	return true;
	210	default:
	211	return false;
	212	};
	213	}
	214
	215	static bool tegra20_spdif_volatile_reg(struct device *dev, unsigned int reg)
	216	{
	217	switch (reg) {
	218	case TEGRA20_SPDIF_STATUS:
	219	case TEGRA20_SPDIF_DATA_FIFO_CSR:
	220	case TEGRA20_SPDIF_DATA_OUT:
	221	case TEGRA20_SPDIF_DATA_IN:
	222	case TEGRA20_SPDIF_CH_STA_RX_A:
	223	case TEGRA20_SPDIF_CH_STA_RX_B:
	224	case TEGRA20_SPDIF_CH_STA_RX_C:
	225	case TEGRA20_SPDIF_CH_STA_RX_D:
	226	case TEGRA20_SPDIF_CH_STA_RX_E:
	227	case TEGRA20_SPDIF_CH_STA_RX_F:
	228	case TEGRA20_SPDIF_USR_STA_RX_A:
	229	case TEGRA20_SPDIF_USR_DAT_TX_A:
	230	return true;
	231	default:
	232	return false;
	233	};
	234	}
	235
	236	static bool tegra20_spdif_precious_reg(struct device *dev, unsigned int reg)
	237	{
	238	switch (reg) {
	239	case TEGRA20_SPDIF_DATA_OUT:
	240	case TEGRA20_SPDIF_DATA_IN:
	241	case TEGRA20_SPDIF_USR_STA_RX_A:
	242	case TEGRA20_SPDIF_USR_DAT_TX_A:
	243	return true;
	244	default:
	245	return false;
	246	};
	247	}
	248
	249	static const struct regmap_config tegra20_spdif_regmap_config = {
250	.reg_bits = 32,
251	.reg_stride = 4,
252	.val_bits = 32,
253	.max_register = TEGRA20_SPDIF_USR_DAT_TX_A,
254	.writeable_reg = tegra20_spdif_wr_rd_reg,
255	.readable_reg = tegra20_spdif_wr_rd_reg,
256	.volatile_reg = tegra20_spdif_volatile_reg,
257	.precious_reg = tegra20_spdif_precious_reg,
258	.cache_type = REGCACHE_RBTREE,
259	};
260
4652a0d0	261	static int tegra20_spdif_platform_probe(struct platform_device *pdev)
774fec33	262	{
896637ac	263	struct tegra20_spdif *spdif;
774fec33	264	struct resource mem, memregion, *dmareq;
5939ae74	265	void __iomem *regs;
774fec33 SW	266	int ret;
774fec33 SW	267
17933db2 SW	268	spdif = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_spdif),
17933db2 SW	269	GFP_KERNEL);
774fec33	270	if (!spdif) {
896637ac	271	dev_err(&pdev->dev, "Can't allocate tegra20_spdif\n");
774fec33	272	ret = -ENOMEM;
17933db2	273	goto err;
774fec33 SW	274	}
	275	dev_set_drvdata(&pdev->dev, spdif);
	276
	277	spdif->clk_spdif_out = clk_get(&pdev->dev, "spdif_out");
	278	if (IS_ERR(spdif->clk_spdif_out)) {
	279	pr_err("Can't retrieve spdif clock\n");
	280	ret = PTR_ERR(spdif->clk_spdif_out);
17933db2	281	goto err;
774fec33 SW	282	}
	283
	284	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	285	if (!mem) {
	286	dev_err(&pdev->dev, "No memory resource\n");
	287	ret = -ENODEV;
	288	goto err_clk_put;
	289	}
	290
	291	dmareq = platform_get_resource(pdev, IORESOURCE_DMA, 0);
	292	if (!dmareq) {
	293	dev_err(&pdev->dev, "No DMA resource\n");
	294	ret = -ENODEV;
	295	goto err_clk_put;
	296	}
	297
17933db2 SW	298	memregion = devm_request_mem_region(&pdev->dev, mem->start,
17933db2 SW	299	resource_size(mem), DRV_NAME);
774fec33 SW	300	if (!memregion) {
	301	dev_err(&pdev->dev, "Memory region already claimed\n");
	302	ret = -EBUSY;
	303	goto err_clk_put;
	304	}
	305
5939ae74 SW	306	regs = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
5939ae74 SW	307	if (!regs) {
774fec33 SW	308	dev_err(&pdev->dev, "ioremap failed\n");
774fec33 SW	309	ret = -ENOMEM;
17933db2	310	goto err_clk_put;
774fec33 SW	311	}
774fec33 SW	312
5939ae74 SW	313	spdif->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
	314	&tegra20_spdif_regmap_config);
	315	if (IS_ERR(spdif->regmap)) {
	316	dev_err(&pdev->dev, "regmap init failed\n");
	317	ret = PTR_ERR(spdif->regmap);
	318	goto err_clk_put;
	319	}
	320
896637ac	321	spdif->playback_dma_data.addr = mem->start + TEGRA20_SPDIF_DATA_OUT;
3489d506 LPC	322	spdif->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	323	spdif->capture_dma_data.maxburst = 4;
	324	spdif->playback_dma_data.slave_id = dmareq->start;
774fec33	325
82ef0ae4 SW	326	pm_runtime_enable(&pdev->dev);
	327	if (!pm_runtime_enabled(&pdev->dev)) {
	328	ret = tegra20_spdif_runtime_resume(&pdev->dev);
	329	if (ret)
	330	goto err_pm_disable;
	331	}
	332
896637ac	333	ret = snd_soc_register_dai(&pdev->dev, &tegra20_spdif_dai);
774fec33 SW	334	if (ret) {
	335	dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
	336	ret = -ENOMEM;
82ef0ae4	337	goto err_suspend;
774fec33 SW	338	}
774fec33 SW	339
518de86b SW	340	ret = tegra_pcm_platform_register(&pdev->dev);
	341	if (ret) {
	342	dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
	343	goto err_unregister_dai;
	344	}
	345
774fec33 SW	346	return 0;
774fec33 SW	347
518de86b SW	348	err_unregister_dai:
518de86b SW	349	snd_soc_unregister_dai(&pdev->dev);
82ef0ae4 SW	350	err_suspend:
	351	if (!pm_runtime_status_suspended(&pdev->dev))
	352	tegra20_spdif_runtime_suspend(&pdev->dev);
	353	err_pm_disable:
	354	pm_runtime_disable(&pdev->dev);
774fec33 SW	355	err_clk_put:
774fec33 SW	356	clk_put(spdif->clk_spdif_out);
17933db2	357	err:
774fec33 SW	358	return ret;
	359	}
	360
4652a0d0	361	static int tegra20_spdif_platform_remove(struct platform_device *pdev)
774fec33	362	{
896637ac	363	struct tegra20_spdif *spdif = dev_get_drvdata(&pdev->dev);
774fec33	364
82ef0ae4 SW	365	pm_runtime_disable(&pdev->dev);
	366	if (!pm_runtime_status_suspended(&pdev->dev))
	367	tegra20_spdif_runtime_suspend(&pdev->dev);
	368
518de86b	369	tegra_pcm_platform_unregister(&pdev->dev);
774fec33 SW	370	snd_soc_unregister_dai(&pdev->dev);
774fec33 SW	371
774fec33 SW	372	clk_put(spdif->clk_spdif_out);
774fec33 SW	373
774fec33 SW	374	return 0;
	375	}
	376
f6e65744	377	static const struct dev_pm_ops tegra20_spdif_pm_ops = {
82ef0ae4 SW	378	SET_RUNTIME_PM_OPS(tegra20_spdif_runtime_suspend,
	379	tegra20_spdif_runtime_resume, NULL)
	380	};
	381
896637ac	382	static struct platform_driver tegra20_spdif_driver = {
774fec33 SW	383	.driver = {
	384	.name = DRV_NAME,
	385	.owner = THIS_MODULE,
82ef0ae4	386	.pm = &tegra20_spdif_pm_ops,
774fec33	387	},
896637ac	388	.probe = tegra20_spdif_platform_probe,
4652a0d0	389	.remove = tegra20_spdif_platform_remove,
774fec33 SW	390	};
774fec33 SW	391
896637ac	392	module_platform_driver(tegra20_spdif_driver);
774fec33 SW	393
774fec33 SW	394	MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
896637ac	395	MODULE_DESCRIPTION("Tegra20 SPDIF ASoC driver");
774fec33 SW	396	MODULE_LICENSE("GPL");
774fec33 SW	397	MODULE_ALIAS("platform:" DRV_NAME);