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1 | /* |
2 | * tegra30_ahub.h - Definitions for Tegra30 AHUB driver | |
3 | * | |
4 | * Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
19 | #ifndef __TEGRA30_AHUB_H__ | |
20 | #define __TEGRA30_AHUB_H__ | |
21 | ||
22 | /* Fields in *_CIF_RX/TX_CTRL; used by AHUB FIFOs, and all other audio modules */ | |
23 | ||
24 | #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT 28 | |
25 | #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US 0xf | |
26 | #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK (TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) | |
27 | ||
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28 | #define TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT 24 |
29 | #define TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US 0x3f | |
30 | #define TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK (TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US << TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) | |
31 | ||
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32 | /* Channel count minus 1 */ |
33 | #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT 24 | |
34 | #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US 7 | |
35 | #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK (TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US << TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) | |
36 | ||
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37 | /* Channel count minus 1 */ |
38 | #define TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT 20 | |
39 | #define TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US 0xf | |
40 | #define TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK (TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US << TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) | |
41 | ||
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42 | /* Channel count minus 1 */ |
43 | #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT 16 | |
44 | #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US 7 | |
45 | #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK (TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US << TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) | |
46 | ||
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47 | /* Channel count minus 1 */ |
48 | #define TEGRA124_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT 16 | |
49 | #define TEGRA124_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US 0xf | |
50 | #define TEGRA124_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK (TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US << TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) | |
51 | ||
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52 | #define TEGRA30_AUDIOCIF_BITS_4 0 |
53 | #define TEGRA30_AUDIOCIF_BITS_8 1 | |
54 | #define TEGRA30_AUDIOCIF_BITS_12 2 | |
55 | #define TEGRA30_AUDIOCIF_BITS_16 3 | |
56 | #define TEGRA30_AUDIOCIF_BITS_20 4 | |
57 | #define TEGRA30_AUDIOCIF_BITS_24 5 | |
58 | #define TEGRA30_AUDIOCIF_BITS_28 6 | |
59 | #define TEGRA30_AUDIOCIF_BITS_32 7 | |
60 | ||
61 | #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT 12 | |
62 | #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_MASK (7 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) | |
63 | #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_4 (TEGRA30_AUDIOCIF_BITS_4 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) | |
64 | #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_8 (TEGRA30_AUDIOCIF_BITS_8 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) | |
65 | #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_12 (TEGRA30_AUDIOCIF_BITS_12 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) | |
66 | #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_16 (TEGRA30_AUDIOCIF_BITS_16 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) | |
67 | #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_20 (TEGRA30_AUDIOCIF_BITS_20 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) | |
68 | #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_24 (TEGRA30_AUDIOCIF_BITS_24 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) | |
69 | #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_28 (TEGRA30_AUDIOCIF_BITS_28 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) | |
70 | #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_32 (TEGRA30_AUDIOCIF_BITS_32 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) | |
71 | ||
72 | #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT 8 | |
73 | #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_MASK (7 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) | |
74 | #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_4 (TEGRA30_AUDIOCIF_BITS_4 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) | |
75 | #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_8 (TEGRA30_AUDIOCIF_BITS_8 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) | |
76 | #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_12 (TEGRA30_AUDIOCIF_BITS_12 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) | |
77 | #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_16 (TEGRA30_AUDIOCIF_BITS_16 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) | |
78 | #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_20 (TEGRA30_AUDIOCIF_BITS_20 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) | |
79 | #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_24 (TEGRA30_AUDIOCIF_BITS_24 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) | |
80 | #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_28 (TEGRA30_AUDIOCIF_BITS_28 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) | |
81 | #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_32 (TEGRA30_AUDIOCIF_BITS_32 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) | |
82 | ||
83 | #define TEGRA30_AUDIOCIF_EXPAND_ZERO 0 | |
84 | #define TEGRA30_AUDIOCIF_EXPAND_ONE 1 | |
85 | #define TEGRA30_AUDIOCIF_EXPAND_LFSR 2 | |
86 | ||
87 | #define TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT 6 | |
88 | #define TEGRA30_AUDIOCIF_CTRL_EXPAND_MASK (3 << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT) | |
89 | #define TEGRA30_AUDIOCIF_CTRL_EXPAND_ZERO (TEGRA30_AUDIOCIF_EXPAND_ZERO << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT) | |
90 | #define TEGRA30_AUDIOCIF_CTRL_EXPAND_ONE (TEGRA30_AUDIOCIF_EXPAND_ONE << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT) | |
91 | #define TEGRA30_AUDIOCIF_CTRL_EXPAND_LFSR (TEGRA30_AUDIOCIF_EXPAND_LFSR << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT) | |
92 | ||
93 | #define TEGRA30_AUDIOCIF_STEREO_CONV_CH0 0 | |
94 | #define TEGRA30_AUDIOCIF_STEREO_CONV_CH1 1 | |
95 | #define TEGRA30_AUDIOCIF_STEREO_CONV_AVG 2 | |
96 | ||
97 | #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT 4 | |
98 | #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_MASK (3 << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT) | |
99 | #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_CH0 (TEGRA30_AUDIOCIF_STEREO_CONV_CH0 << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT) | |
100 | #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_CH1 (TEGRA30_AUDIOCIF_STEREO_CONV_CH1 << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT) | |
101 | #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_AVG (TEGRA30_AUDIOCIF_STEREO_CONV_AVG << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT) | |
102 | ||
5e049fce | 103 | #define TEGRA30_AUDIOCIF_CTRL_REPLICATE_SHIFT 3 |
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104 | |
105 | #define TEGRA30_AUDIOCIF_DIRECTION_TX 0 | |
106 | #define TEGRA30_AUDIOCIF_DIRECTION_RX 1 | |
107 | ||
108 | #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT 2 | |
109 | #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_MASK (1 << TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT) | |
110 | #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_TX (TEGRA30_AUDIOCIF_DIRECTION_TX << TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT) | |
111 | #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_RX (TEGRA30_AUDIOCIF_DIRECTION_RX << TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT) | |
112 | ||
113 | #define TEGRA30_AUDIOCIF_TRUNCATE_ROUND 0 | |
114 | #define TEGRA30_AUDIOCIF_TRUNCATE_CHOP 1 | |
115 | ||
116 | #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT 1 | |
117 | #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_MASK (1 << TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT) | |
118 | #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_ROUND (TEGRA30_AUDIOCIF_TRUNCATE_ROUND << TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT) | |
119 | #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_CHOP (TEGRA30_AUDIOCIF_TRUNCATE_CHOP << TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT) | |
120 | ||
121 | #define TEGRA30_AUDIOCIF_MONO_CONV_ZERO 0 | |
122 | #define TEGRA30_AUDIOCIF_MONO_CONV_COPY 1 | |
123 | ||
124 | #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT 0 | |
125 | #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_MASK (1 << TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT) | |
126 | #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_ZERO (TEGRA30_AUDIOCIF_MONO_CONV_ZERO << TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT) | |
127 | #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_COPY (TEGRA30_AUDIOCIF_MONO_CONV_COPY << TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT) | |
128 | ||
129 | /* Registers within TEGRA30_AUDIO_CLUSTER_BASE */ | |
130 | ||
131 | /* TEGRA30_AHUB_CHANNEL_CTRL */ | |
132 | ||
133 | #define TEGRA30_AHUB_CHANNEL_CTRL 0x0 | |
134 | #define TEGRA30_AHUB_CHANNEL_CTRL_STRIDE 0x20 | |
135 | #define TEGRA30_AHUB_CHANNEL_CTRL_COUNT 4 | |
136 | #define TEGRA30_AHUB_CHANNEL_CTRL_TX_EN (1 << 31) | |
137 | #define TEGRA30_AHUB_CHANNEL_CTRL_RX_EN (1 << 30) | |
138 | #define TEGRA30_AHUB_CHANNEL_CTRL_LOOPBACK (1 << 29) | |
139 | ||
140 | #define TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT 16 | |
141 | #define TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK_US 0xff | |
142 | #define TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK (TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT) | |
143 | ||
144 | #define TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT 8 | |
145 | #define TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK_US 0xff | |
146 | #define TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK (TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT) | |
147 | ||
148 | #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_EN (1 << 6) | |
149 | ||
150 | #define TEGRA30_PACK_8_4 2 | |
151 | #define TEGRA30_PACK_16 3 | |
152 | ||
153 | #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT 4 | |
154 | #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK_US 3 | |
155 | #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK (TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT) | |
156 | #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_8_4 (TEGRA30_PACK_8_4 << TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT) | |
157 | #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_16 (TEGRA30_PACK_16 << TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT) | |
158 | ||
159 | #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_EN (1 << 2) | |
160 | ||
161 | #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT 0 | |
162 | #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK_US 3 | |
163 | #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK (TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT) | |
164 | #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_8_4 (TEGRA30_PACK_8_4 << TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT) | |
165 | #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_16 (TEGRA30_PACK_16 << TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT) | |
166 | ||
167 | /* TEGRA30_AHUB_CHANNEL_CLEAR */ | |
168 | ||
169 | #define TEGRA30_AHUB_CHANNEL_CLEAR 0x4 | |
170 | #define TEGRA30_AHUB_CHANNEL_CLEAR_STRIDE 0x20 | |
171 | #define TEGRA30_AHUB_CHANNEL_CLEAR_COUNT 4 | |
172 | #define TEGRA30_AHUB_CHANNEL_CLEAR_TX_SOFT_RESET (1 << 31) | |
173 | #define TEGRA30_AHUB_CHANNEL_CLEAR_RX_SOFT_RESET (1 << 30) | |
174 | ||
175 | /* TEGRA30_AHUB_CHANNEL_STATUS */ | |
176 | ||
177 | #define TEGRA30_AHUB_CHANNEL_STATUS 0x8 | |
178 | #define TEGRA30_AHUB_CHANNEL_STATUS_STRIDE 0x20 | |
179 | #define TEGRA30_AHUB_CHANNEL_STATUS_COUNT 4 | |
180 | #define TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_SHIFT 24 | |
181 | #define TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_MASK_US 0xff | |
182 | #define TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_MASK (TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_MASK_US << TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_SHIFT) | |
183 | #define TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_SHIFT 16 | |
184 | #define TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_MASK_US 0xff | |
185 | #define TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_MASK (TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_MASK_US << TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_SHIFT) | |
186 | #define TEGRA30_AHUB_CHANNEL_STATUS_TX_TRIG (1 << 1) | |
187 | #define TEGRA30_AHUB_CHANNEL_STATUS_RX_TRIG (1 << 0) | |
188 | ||
189 | /* TEGRA30_AHUB_CHANNEL_TXFIFO */ | |
190 | ||
191 | #define TEGRA30_AHUB_CHANNEL_TXFIFO 0xc | |
192 | #define TEGRA30_AHUB_CHANNEL_TXFIFO_STRIDE 0x20 | |
193 | #define TEGRA30_AHUB_CHANNEL_TXFIFO_COUNT 4 | |
194 | ||
195 | /* TEGRA30_AHUB_CHANNEL_RXFIFO */ | |
196 | ||
197 | #define TEGRA30_AHUB_CHANNEL_RXFIFO 0x10 | |
198 | #define TEGRA30_AHUB_CHANNEL_RXFIFO_STRIDE 0x20 | |
199 | #define TEGRA30_AHUB_CHANNEL_RXFIFO_COUNT 4 | |
200 | ||
201 | /* TEGRA30_AHUB_CIF_TX_CTRL */ | |
202 | ||
203 | #define TEGRA30_AHUB_CIF_TX_CTRL 0x14 | |
204 | #define TEGRA30_AHUB_CIF_TX_CTRL_STRIDE 0x20 | |
205 | #define TEGRA30_AHUB_CIF_TX_CTRL_COUNT 4 | |
206 | /* Uses field from TEGRA30_AUDIOCIF_CTRL_* */ | |
207 | ||
208 | /* TEGRA30_AHUB_CIF_RX_CTRL */ | |
209 | ||
210 | #define TEGRA30_AHUB_CIF_RX_CTRL 0x18 | |
211 | #define TEGRA30_AHUB_CIF_RX_CTRL_STRIDE 0x20 | |
212 | #define TEGRA30_AHUB_CIF_RX_CTRL_COUNT 4 | |
213 | /* Uses field from TEGRA30_AUDIOCIF_CTRL_* */ | |
214 | ||
215 | /* TEGRA30_AHUB_CONFIG_LINK_CTRL */ | |
216 | ||
217 | #define TEGRA30_AHUB_CONFIG_LINK_CTRL 0x80 | |
218 | #define TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_SHIFT 28 | |
219 | #define TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK_US 0xf | |
220 | #define TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK (TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK_US << TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_SHIFT) | |
221 | #define TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_SHIFT 16 | |
222 | #define TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK_US 0xfff | |
223 | #define TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK (TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK_US << TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_SHIFT) | |
224 | #define TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_SHIFT 4 | |
225 | #define TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK_US 0xfff | |
226 | #define TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK (TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK_US << TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_SHIFT) | |
227 | #define TEGRA30_AHUB_CONFIG_LINK_CTRL_CG_EN (1 << 2) | |
228 | #define TEGRA30_AHUB_CONFIG_LINK_CTRL_CLEAR_TIMEOUT_CNTR (1 << 1) | |
229 | #define TEGRA30_AHUB_CONFIG_LINK_CTRL_SOFT_RESET (1 << 0) | |
230 | ||
231 | /* TEGRA30_AHUB_MISC_CTRL */ | |
232 | ||
233 | #define TEGRA30_AHUB_MISC_CTRL 0x84 | |
234 | #define TEGRA30_AHUB_MISC_CTRL_AUDIO_ACTIVE (1 << 31) | |
235 | #define TEGRA30_AHUB_MISC_CTRL_AUDIO_CG_EN (1 << 8) | |
236 | #define TEGRA30_AHUB_MISC_CTRL_AUDIO_OBS_SEL_SHIFT 0 | |
237 | #define TEGRA30_AHUB_MISC_CTRL_AUDIO_OBS_SEL_MASK (0x1f << TEGRA30_AHUB_MISC_CTRL_AUDIO_OBS_SEL_SHIFT) | |
238 | ||
239 | /* TEGRA30_AHUB_APBDMA_LIVE_STATUS */ | |
240 | ||
241 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS 0x88 | |
242 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_CIF_FIFO_FULL (1 << 31) | |
243 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_CIF_FIFO_FULL (1 << 30) | |
244 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_CIF_FIFO_FULL (1 << 29) | |
245 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_CIF_FIFO_FULL (1 << 28) | |
246 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_CIF_FIFO_FULL (1 << 27) | |
247 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_CIF_FIFO_FULL (1 << 26) | |
248 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_CIF_FIFO_FULL (1 << 25) | |
249 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_FULL (1 << 24) | |
250 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_CIF_FIFO_EMPTY (1 << 23) | |
251 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_CIF_FIFO_EMPTY (1 << 22) | |
252 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_CIF_FIFO_EMPTY (1 << 21) | |
253 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_CIF_FIFO_EMPTY (1 << 20) | |
254 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_CIF_FIFO_EMPTY (1 << 19) | |
255 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_CIF_FIFO_EMPTY (1 << 18) | |
256 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_CIF_FIFO_EMPTY (1 << 17) | |
257 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_EMPTY (1 << 16) | |
258 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_DMA_FIFO_FULL (1 << 15) | |
259 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_DMA_FIFO_FULL (1 << 14) | |
260 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_DMA_FIFO_FULL (1 << 13) | |
261 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_DMA_FIFO_FULL (1 << 12) | |
262 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_DMA_FIFO_FULL (1 << 11) | |
263 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_DMA_FIFO_FULL (1 << 10) | |
264 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_DMA_FIFO_FULL (1 << 9) | |
265 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_DMA_FIFO_FULL (1 << 8) | |
266 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_DMA_FIFO_EMPTY (1 << 7) | |
267 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_DMA_FIFO_EMPTY (1 << 6) | |
268 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_DMA_FIFO_EMPTY (1 << 5) | |
269 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_DMA_FIFO_EMPTY (1 << 4) | |
270 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_DMA_FIFO_EMPTY (1 << 3) | |
271 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_DMA_FIFO_EMPTY (1 << 2) | |
272 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_DMA_FIFO_EMPTY (1 << 1) | |
273 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_DMA_FIFO_EMPTY (1 << 0) | |
274 | ||
275 | /* TEGRA30_AHUB_I2S_LIVE_STATUS */ | |
276 | ||
277 | #define TEGRA30_AHUB_I2S_LIVE_STATUS 0x8c | |
278 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_FULL (1 << 29) | |
279 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_FULL (1 << 28) | |
280 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_FULL (1 << 27) | |
281 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_FULL (1 << 26) | |
282 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_FULL (1 << 25) | |
283 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_FULL (1 << 24) | |
284 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_FULL (1 << 23) | |
285 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_FULL (1 << 22) | |
286 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_FULL (1 << 21) | |
287 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_FULL (1 << 20) | |
288 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_ENABLED (1 << 19) | |
289 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_ENABLED (1 << 18) | |
290 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_ENABLED (1 << 17) | |
291 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_ENABLED (1 << 16) | |
292 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_ENABLED (1 << 15) | |
293 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_ENABLED (1 << 14) | |
294 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_ENABLED (1 << 13) | |
295 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_ENABLED (1 << 12) | |
296 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_ENABLED (1 << 11) | |
297 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_ENABLED (1 << 10) | |
298 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_EMPTY (1 << 9) | |
299 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_EMPTY (1 << 8) | |
300 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_EMPTY (1 << 7) | |
301 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_EMPTY (1 << 6) | |
302 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_EMPTY (1 << 5) | |
303 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_EMPTY (1 << 4) | |
304 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_EMPTY (1 << 3) | |
305 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_EMPTY (1 << 2) | |
306 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_EMPTY (1 << 1) | |
307 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_EMPTY (1 << 0) | |
308 | ||
309 | /* TEGRA30_AHUB_DAM0_LIVE_STATUS */ | |
310 | ||
311 | #define TEGRA30_AHUB_DAM_LIVE_STATUS 0x90 | |
312 | #define TEGRA30_AHUB_DAM_LIVE_STATUS_STRIDE 0x8 | |
313 | #define TEGRA30_AHUB_DAM_LIVE_STATUS_COUNT 3 | |
314 | #define TEGRA30_AHUB_DAM_LIVE_STATUS_TX_ENABLED (1 << 26) | |
315 | #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX1_ENABLED (1 << 25) | |
316 | #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX0_ENABLED (1 << 24) | |
317 | #define TEGRA30_AHUB_DAM_LIVE_STATUS_TXFIFO_FULL (1 << 15) | |
318 | #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX1FIFO_FULL (1 << 9) | |
319 | #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX0FIFO_FULL (1 << 8) | |
320 | #define TEGRA30_AHUB_DAM_LIVE_STATUS_TXFIFO_EMPTY (1 << 7) | |
321 | #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX1FIFO_EMPTY (1 << 1) | |
322 | #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX0FIFO_EMPTY (1 << 0) | |
323 | ||
324 | /* TEGRA30_AHUB_SPDIF_LIVE_STATUS */ | |
325 | ||
326 | #define TEGRA30_AHUB_SPDIF_LIVE_STATUS 0xa8 | |
327 | #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TX_ENABLED (1 << 11) | |
328 | #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RX_ENABLED (1 << 10) | |
329 | #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TX_ENABLED (1 << 9) | |
330 | #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RX_ENABLED (1 << 8) | |
331 | #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_FULL (1 << 7) | |
332 | #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_FULL (1 << 6) | |
333 | #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_FULL (1 << 5) | |
334 | #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_FULL (1 << 4) | |
335 | #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_EMPTY (1 << 3) | |
336 | #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_EMPTY (1 << 2) | |
337 | #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_EMPTY (1 << 1) | |
338 | #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_EMPTY (1 << 0) | |
339 | ||
340 | /* TEGRA30_AHUB_I2S_INT_MASK */ | |
341 | ||
342 | #define TEGRA30_AHUB_I2S_INT_MASK 0xb0 | |
343 | ||
344 | /* TEGRA30_AHUB_DAM_INT_MASK */ | |
345 | ||
346 | #define TEGRA30_AHUB_DAM_INT_MASK 0xb4 | |
347 | ||
348 | /* TEGRA30_AHUB_SPDIF_INT_MASK */ | |
349 | ||
350 | #define TEGRA30_AHUB_SPDIF_INT_MASK 0xbc | |
351 | ||
352 | /* TEGRA30_AHUB_APBIF_INT_MASK */ | |
353 | ||
354 | #define TEGRA30_AHUB_APBIF_INT_MASK 0xc0 | |
355 | ||
356 | /* TEGRA30_AHUB_I2S_INT_STATUS */ | |
357 | ||
358 | #define TEGRA30_AHUB_I2S_INT_STATUS 0xc8 | |
359 | ||
360 | /* TEGRA30_AHUB_DAM_INT_STATUS */ | |
361 | ||
362 | #define TEGRA30_AHUB_DAM_INT_STATUS 0xcc | |
363 | ||
364 | /* TEGRA30_AHUB_SPDIF_INT_STATUS */ | |
365 | ||
366 | #define TEGRA30_AHUB_SPDIF_INT_STATUS 0xd4 | |
367 | ||
368 | /* TEGRA30_AHUB_APBIF_INT_STATUS */ | |
369 | ||
370 | #define TEGRA30_AHUB_APBIF_INT_STATUS 0xd8 | |
371 | ||
372 | /* TEGRA30_AHUB_I2S_INT_SOURCE */ | |
373 | ||
374 | #define TEGRA30_AHUB_I2S_INT_SOURCE 0xe0 | |
375 | ||
376 | /* TEGRA30_AHUB_DAM_INT_SOURCE */ | |
377 | ||
378 | #define TEGRA30_AHUB_DAM_INT_SOURCE 0xe4 | |
379 | ||
380 | /* TEGRA30_AHUB_SPDIF_INT_SOURCE */ | |
381 | ||
382 | #define TEGRA30_AHUB_SPDIF_INT_SOURCE 0xec | |
383 | ||
384 | /* TEGRA30_AHUB_APBIF_INT_SOURCE */ | |
385 | ||
386 | #define TEGRA30_AHUB_APBIF_INT_SOURCE 0xf0 | |
387 | ||
388 | /* TEGRA30_AHUB_I2S_INT_SET */ | |
389 | ||
390 | #define TEGRA30_AHUB_I2S_INT_SET 0xf8 | |
391 | ||
392 | /* TEGRA30_AHUB_DAM_INT_SET */ | |
393 | ||
394 | #define TEGRA30_AHUB_DAM_INT_SET 0xfc | |
395 | ||
396 | /* TEGRA30_AHUB_SPDIF_INT_SET */ | |
397 | ||
398 | #define TEGRA30_AHUB_SPDIF_INT_SET 0x100 | |
399 | ||
400 | /* TEGRA30_AHUB_APBIF_INT_SET */ | |
401 | ||
402 | #define TEGRA30_AHUB_APBIF_INT_SET 0x104 | |
403 | ||
404 | /* Registers within TEGRA30_AHUB_BASE */ | |
405 | ||
406 | #define TEGRA30_AHUB_AUDIO_RX 0x0 | |
407 | #define TEGRA30_AHUB_AUDIO_RX_STRIDE 0x4 | |
408 | #define TEGRA30_AHUB_AUDIO_RX_COUNT 17 | |
409 | /* This register repeats once for each entry in enum tegra30_ahub_rxcif */ | |
410 | /* The fields in this register are 1 bit per entry in tegra30_ahub_txcif */ | |
411 | ||
412 | /* | |
413 | * Terminology: | |
414 | * AHUB: Audio Hub; a cross-bar switch between the audio devices: DMA FIFOs, | |
415 | * I2S controllers, SPDIF controllers, and DAMs. | |
416 | * XBAR: The core cross-bar component of the AHUB. | |
417 | * CIF: Client Interface; the HW module connecting an audio device to the | |
418 | * XBAR. | |
419 | * DAM: Digital Audio Mixer: A HW module that mixes multiple audio streams, | |
420 | * possibly including sample-rate conversion. | |
421 | * | |
422 | * Each TX CIF transmits data into the XBAR. Each RX CIF can receive audio | |
423 | * transmitted by a particular TX CIF. | |
424 | * | |
425 | * This driver is currently very simplistic; many HW features are not | |
426 | * exposed; DAMs are not supported, only 16-bit stereo audio is supported, | |
427 | * etc. | |
428 | */ | |
429 | ||
430 | enum tegra30_ahub_txcif { | |
431 | TEGRA30_AHUB_TXCIF_APBIF_TX0, | |
432 | TEGRA30_AHUB_TXCIF_APBIF_TX1, | |
433 | TEGRA30_AHUB_TXCIF_APBIF_TX2, | |
434 | TEGRA30_AHUB_TXCIF_APBIF_TX3, | |
435 | TEGRA30_AHUB_TXCIF_I2S0_TX0, | |
436 | TEGRA30_AHUB_TXCIF_I2S1_TX0, | |
437 | TEGRA30_AHUB_TXCIF_I2S2_TX0, | |
438 | TEGRA30_AHUB_TXCIF_I2S3_TX0, | |
439 | TEGRA30_AHUB_TXCIF_I2S4_TX0, | |
440 | TEGRA30_AHUB_TXCIF_DAM0_TX0, | |
441 | TEGRA30_AHUB_TXCIF_DAM1_TX0, | |
442 | TEGRA30_AHUB_TXCIF_DAM2_TX0, | |
443 | TEGRA30_AHUB_TXCIF_SPDIF_TX0, | |
444 | TEGRA30_AHUB_TXCIF_SPDIF_TX1, | |
445 | }; | |
446 | ||
447 | enum tegra30_ahub_rxcif { | |
448 | TEGRA30_AHUB_RXCIF_APBIF_RX0, | |
449 | TEGRA30_AHUB_RXCIF_APBIF_RX1, | |
450 | TEGRA30_AHUB_RXcIF_APBIF_RX2, | |
451 | TEGRA30_AHUB_RXCIF_APBIF_RX3, | |
452 | TEGRA30_AHUB_RXCIF_I2S0_RX0, | |
453 | TEGRA30_AHUB_RXCIF_I2S1_RX0, | |
454 | TEGRA30_AHUB_RXCIF_I2S2_RX0, | |
455 | TEGRA30_AHUB_RXCIF_I2S3_RX0, | |
456 | TEGRA30_AHUB_RXCIF_I2S4_RX0, | |
457 | TEGRA30_AHUB_RXCIF_DAM0_RX0, | |
458 | TEGRA30_AHUB_RXCIF_DAM0_RX1, | |
459 | TEGRA30_AHUB_RXCIF_DAM1_RX0, | |
460 | TEGRA30_AHUB_RXCIF_DAM2_RX1, | |
461 | TEGRA30_AHUB_RXCIF_DAM3_RX0, | |
462 | TEGRA30_AHUB_RXCIF_DAM3_RX1, | |
463 | TEGRA30_AHUB_RXCIF_SPDIF_RX0, | |
464 | TEGRA30_AHUB_RXCIF_SPDIF_RX1, | |
465 | }; | |
466 | ||
467 | extern int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif, | |
5608bd3e SW |
468 | char *dmachan, int dmachan_len, |
469 | dma_addr_t *fiforeg); | |
be944d42 SW |
470 | extern int tegra30_ahub_enable_rx_fifo(enum tegra30_ahub_rxcif rxcif); |
471 | extern int tegra30_ahub_disable_rx_fifo(enum tegra30_ahub_rxcif rxcif); | |
472 | extern int tegra30_ahub_free_rx_fifo(enum tegra30_ahub_rxcif rxcif); | |
473 | ||
474 | extern int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif, | |
5608bd3e SW |
475 | char *dmachan, int dmachan_len, |
476 | dma_addr_t *fiforeg); | |
be944d42 SW |
477 | extern int tegra30_ahub_enable_tx_fifo(enum tegra30_ahub_txcif txcif); |
478 | extern int tegra30_ahub_disable_tx_fifo(enum tegra30_ahub_txcif txcif); | |
479 | extern int tegra30_ahub_free_tx_fifo(enum tegra30_ahub_txcif txcif); | |
480 | ||
481 | extern int tegra30_ahub_set_rx_cif_source(enum tegra30_ahub_rxcif rxcif, | |
482 | enum tegra30_ahub_txcif txcif); | |
483 | extern int tegra30_ahub_unset_rx_cif_source(enum tegra30_ahub_rxcif rxcif); | |
484 | ||
5e049fce SW |
485 | struct tegra30_ahub_cif_conf { |
486 | unsigned int threshold; | |
487 | unsigned int audio_channels; | |
488 | unsigned int client_channels; | |
489 | unsigned int audio_bits; | |
490 | unsigned int client_bits; | |
491 | unsigned int expand; | |
492 | unsigned int stereo_conv; | |
493 | unsigned int replicate; | |
494 | unsigned int direction; | |
495 | unsigned int truncate; | |
496 | unsigned int mono_conv; | |
497 | }; | |
498 | ||
499 | void tegra30_ahub_set_cif(struct regmap *regmap, unsigned int reg, | |
500 | struct tegra30_ahub_cif_conf *conf); | |
501 | void tegra124_ahub_set_cif(struct regmap *regmap, unsigned int reg, | |
502 | struct tegra30_ahub_cif_conf *conf); | |
503 | ||
95d36075 | 504 | struct tegra30_ahub_soc_data { |
5185e0ac | 505 | u32 mod_list_mask; |
5e049fce SW |
506 | void (*set_audio_cif)(struct regmap *regmap, |
507 | unsigned int reg, | |
508 | struct tegra30_ahub_cif_conf *conf); | |
95d36075 SW |
509 | /* |
510 | * FIXME: There are many more differences in HW, such as: | |
511 | * - More APBIF channels. | |
512 | * - Extra separate chunks of register address space to represent | |
513 | * the extra APBIF channels. | |
514 | * - More units connected to the AHUB, so that tegra30_ahub_[rt]xcif | |
515 | * need expansion, coupled with there being more defined bits in | |
516 | * the AHUB routing registers. | |
517 | * However, the driver doesn't support those new features yet, so we | |
518 | * don't represent them here yet. | |
519 | */ | |
520 | }; | |
521 | ||
be944d42 | 522 | struct tegra30_ahub { |
95d36075 | 523 | const struct tegra30_ahub_soc_data *soc_data; |
be944d42 SW |
524 | struct device *dev; |
525 | struct clk *clk_d_audio; | |
526 | struct clk *clk_apbif; | |
be944d42 SW |
527 | resource_size_t apbif_addr; |
528 | struct regmap *regmap_apbif; | |
529 | struct regmap *regmap_ahub; | |
530 | DECLARE_BITMAP(rx_usage, TEGRA30_AHUB_CHANNEL_CTRL_COUNT); | |
531 | DECLARE_BITMAP(tx_usage, TEGRA30_AHUB_CHANNEL_CTRL_COUNT); | |
532 | }; | |
533 | ||
534 | #endif |