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ASoC: ux500: Ensure consistent configuration between DAIs
[deliverable/linux.git] / sound / soc / ux500 / ux500_msp_dai.c
CommitLineData
3592b7f6
OL		 1/*
2 * Copyright (C) ST-Ericsson SA 2012
3 *
4 * Author: Ola Lilja <ola.o.lilja@stericsson.com>,
5 * Roger Nilsson <roger.xr.nilsson@stericsson.com>
6 * for ST-Ericsson.
7 *
8 * License terms:
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
13 */
14
15#include <linux/module.h>
16#include <linux/slab.h>
17#include <linux/bitops.h>
18#include <linux/platform_device.h>
19#include <linux/clk.h>
20#include <linux/regulator/consumer.h>
21#include <linux/mfd/dbx500-prcmu.h>
ab0fc6ce 22#include <linux/platform_data/asoc-ux500-msp.h>
3592b7f6 23
3592b7f6
OL		 24#include <sound/soc.h>
25#include <sound/soc-dai.h>
26
27#include "ux500_msp_i2s.h"
28#include "ux500_msp_dai.h"
1428c20f 29#include "ux500_pcm.h"
3592b7f6
OL		 30
31static int setup_pcm_multichan(struct snd_soc_dai *dai,
32 struct ux500_msp_config *msp_config)
33{
34 struct ux500_msp_i2s_drvdata *drvdata = dev_get_drvdata(dai->dev);
35 struct msp_multichannel_config *multi =
36 &msp_config->multichannel_config;
37
38 if (drvdata->slots > 1) {
39 msp_config->multichannel_configured = 1;
40
41 multi->tx_multichannel_enable = true;
42 multi->rx_multichannel_enable = true;
43 multi->rx_comparison_enable_mode = MSP_COMPARISON_DISABLED;
44
45 multi->tx_channel_0_enable = drvdata->tx_mask;
46 multi->tx_channel_1_enable = 0;
47 multi->tx_channel_2_enable = 0;
48 multi->tx_channel_3_enable = 0;
49
50 multi->rx_channel_0_enable = drvdata->rx_mask;
51 multi->rx_channel_1_enable = 0;
52 multi->rx_channel_2_enable = 0;
53 multi->rx_channel_3_enable = 0;
54
55 dev_dbg(dai->dev,
56 "%s: Multichannel enabled. Slots: %d, TX: %u, RX: %u\n",
57 __func__, drvdata->slots, multi->tx_channel_0_enable,
58 multi->rx_channel_0_enable);
59 }
60
61 return 0;
62}
63
64static int setup_frameper(struct snd_soc_dai *dai, unsigned int rate,
65 struct msp_protdesc *prot_desc)
66{
67 struct ux500_msp_i2s_drvdata *drvdata = dev_get_drvdata(dai->dev);
68
69 switch (drvdata->slots) {
70 case 1:
71 switch (rate) {
72 case 8000:
73 prot_desc->frame_period =
74 FRAME_PER_SINGLE_SLOT_8_KHZ;
75 break;
76
77 case 16000:
78 prot_desc->frame_period =
79 FRAME_PER_SINGLE_SLOT_16_KHZ;
80 break;
81
82 case 44100:
83 prot_desc->frame_period =
84 FRAME_PER_SINGLE_SLOT_44_1_KHZ;
85 break;
86
87 case 48000:
88 prot_desc->frame_period =
89 FRAME_PER_SINGLE_SLOT_48_KHZ;
90 break;
91
92 default:
93 dev_err(dai->dev,
94 "%s: Error: Unsupported sample-rate (freq = %d)!\n",
95 __func__, rate);
96 return -EINVAL;
97 }
98 break;
99
100 case 2:
101 prot_desc->frame_period = FRAME_PER_2_SLOTS;
102 break;
103
104 case 8:
105 prot_desc->frame_period = FRAME_PER_8_SLOTS;
106 break;
107
108 case 16:
109 prot_desc->frame_period = FRAME_PER_16_SLOTS;
110 break;
111 default:
112 dev_err(dai->dev,
113 "%s: Error: Unsupported slot-count (slots = %d)!\n",
114 __func__, drvdata->slots);
115 return -EINVAL;
116 }
117
118 prot_desc->clocks_per_frame =
119 prot_desc->frame_period+1;
120
121 dev_dbg(dai->dev, "%s: Clocks per frame: %u\n",
122 __func__,
123 prot_desc->clocks_per_frame);
124
125 return 0;
126}
127
128static int setup_pcm_framing(struct snd_soc_dai *dai, unsigned int rate,
129 struct msp_protdesc *prot_desc)
130{
131 struct ux500_msp_i2s_drvdata *drvdata = dev_get_drvdata(dai->dev);
132
133 u32 frame_length = MSP_FRAME_LEN_1;
134 prot_desc->frame_width = 0;
135
136 switch (drvdata->slots) {
137 case 1:
138 frame_length = MSP_FRAME_LEN_1;
139 break;
140
141 case 2:
142 frame_length = MSP_FRAME_LEN_2;
143 break;
144
145 case 8:
146 frame_length = MSP_FRAME_LEN_8;
147 break;
148
149 case 16:
150 frame_length = MSP_FRAME_LEN_16;
151 break;
152 default:
153 dev_err(dai->dev,
154 "%s: Error: Unsupported slot-count (slots = %d)!\n",
155 __func__, drvdata->slots);
156 return -EINVAL;
157 }
158
159 prot_desc->tx_frame_len_1 = frame_length;
160 prot_desc->rx_frame_len_1 = frame_length;
161 prot_desc->tx_frame_len_2 = frame_length;
162 prot_desc->rx_frame_len_2 = frame_length;
163
164 prot_desc->tx_elem_len_1 = MSP_ELEM_LEN_16;
165 prot_desc->rx_elem_len_1 = MSP_ELEM_LEN_16;
166 prot_desc->tx_elem_len_2 = MSP_ELEM_LEN_16;
167 prot_desc->rx_elem_len_2 = MSP_ELEM_LEN_16;
168
169 return setup_frameper(dai, rate, prot_desc);
170}
171
172static int setup_clocking(struct snd_soc_dai *dai,
173 unsigned int fmt,
174 struct ux500_msp_config *msp_config)
175{
176 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
177 case SND_SOC_DAIFMT_NB_NF:
178 break;
179
180 case SND_SOC_DAIFMT_NB_IF:
181 msp_config->tx_fsync_pol ^= 1 << TFSPOL_SHIFT;
182 msp_config->rx_fsync_pol ^= 1 << RFSPOL_SHIFT;
183
184 break;
185
186 default:
187 dev_err(dai->dev,
188 "%s: Error: Unsopported inversion (fmt = 0x%x)!\n",
189 __func__, fmt);
190
191 return -EINVAL;
192 }
193
194 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
195 case SND_SOC_DAIFMT_CBM_CFM:
196 dev_dbg(dai->dev, "%s: Codec is master.\n", __func__);
197
198 msp_config->iodelay = 0x20;
199 msp_config->rx_fsync_sel = 0;
200 msp_config->tx_fsync_sel = 1 << TFSSEL_SHIFT;
201 msp_config->tx_clk_sel = 0;
202 msp_config->rx_clk_sel = 0;
203 msp_config->srg_clk_sel = 0x2 << SCKSEL_SHIFT;
204
205 break;
206
207 case SND_SOC_DAIFMT_CBS_CFS:
208 dev_dbg(dai->dev, "%s: Codec is slave.\n", __func__);
209
210 msp_config->tx_clk_sel = TX_CLK_SEL_SRG;
211 msp_config->tx_fsync_sel = TX_SYNC_SRG_PROG;
212 msp_config->rx_clk_sel = RX_CLK_SEL_SRG;
213 msp_config->rx_fsync_sel = RX_SYNC_SRG;
214 msp_config->srg_clk_sel = 1 << SCKSEL_SHIFT;
215
216 break;
217
218 default:
219 dev_err(dai->dev, "%s: Error: Unsopported master (fmt = 0x%x)!\n",
220 __func__, fmt);
221
222 return -EINVAL;
223 }
224
225 return 0;
226}
227
228static int setup_pcm_protdesc(struct snd_soc_dai *dai,
229 unsigned int fmt,
230 struct msp_protdesc *prot_desc)
231{
232 prot_desc->rx_phase_mode = MSP_SINGLE_PHASE;
233 prot_desc->tx_phase_mode = MSP_SINGLE_PHASE;
234 prot_desc->rx_phase2_start_mode = MSP_PHASE2_START_MODE_IMEDIATE;
235 prot_desc->tx_phase2_start_mode = MSP_PHASE2_START_MODE_IMEDIATE;
236 prot_desc->rx_byte_order = MSP_BTF_MS_BIT_FIRST;
237 prot_desc->tx_byte_order = MSP_BTF_MS_BIT_FIRST;
238 prot_desc->tx_fsync_pol = MSP_FSYNC_POL(MSP_FSYNC_POL_ACT_HI);
239 prot_desc->rx_fsync_pol = MSP_FSYNC_POL_ACT_HI << RFSPOL_SHIFT;
240
241 if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_DSP_A) {
242 dev_dbg(dai->dev, "%s: DSP_A.\n", __func__);
243 prot_desc->rx_clk_pol = MSP_RISING_EDGE;
244 prot_desc->tx_clk_pol = MSP_FALLING_EDGE;
245
246 prot_desc->rx_data_delay = MSP_DELAY_1;
247 prot_desc->tx_data_delay = MSP_DELAY_1;
248 } else {
249 dev_dbg(dai->dev, "%s: DSP_B.\n", __func__);
250 prot_desc->rx_clk_pol = MSP_FALLING_EDGE;
251 prot_desc->tx_clk_pol = MSP_RISING_EDGE;
252
253 prot_desc->rx_data_delay = MSP_DELAY_0;
254 prot_desc->tx_data_delay = MSP_DELAY_0;
255 }
256
257 prot_desc->rx_half_word_swap = MSP_SWAP_NONE;
258 prot_desc->tx_half_word_swap = MSP_SWAP_NONE;
259 prot_desc->compression_mode = MSP_COMPRESS_MODE_LINEAR;
260 prot_desc->expansion_mode = MSP_EXPAND_MODE_LINEAR;
261 prot_desc->frame_sync_ignore = MSP_FSYNC_IGNORE;
262
263 return 0;
264}
265
266static int setup_i2s_protdesc(struct msp_protdesc *prot_desc)
267{
268 prot_desc->rx_phase_mode = MSP_DUAL_PHASE;
269 prot_desc->tx_phase_mode = MSP_DUAL_PHASE;
270 prot_desc->rx_phase2_start_mode = MSP_PHASE2_START_MODE_FSYNC;
271 prot_desc->tx_phase2_start_mode = MSP_PHASE2_START_MODE_FSYNC;
272 prot_desc->rx_byte_order = MSP_BTF_MS_BIT_FIRST;
273 prot_desc->tx_byte_order = MSP_BTF_MS_BIT_FIRST;
274 prot_desc->tx_fsync_pol = MSP_FSYNC_POL(MSP_FSYNC_POL_ACT_LO);
275 prot_desc->rx_fsync_pol = MSP_FSYNC_POL_ACT_LO << RFSPOL_SHIFT;
276
277 prot_desc->rx_frame_len_1 = MSP_FRAME_LEN_1;
278 prot_desc->rx_frame_len_2 = MSP_FRAME_LEN_1;
279 prot_desc->tx_frame_len_1 = MSP_FRAME_LEN_1;
280 prot_desc->tx_frame_len_2 = MSP_FRAME_LEN_1;
281 prot_desc->rx_elem_len_1 = MSP_ELEM_LEN_16;
282 prot_desc->rx_elem_len_2 = MSP_ELEM_LEN_16;
283 prot_desc->tx_elem_len_1 = MSP_ELEM_LEN_16;
284 prot_desc->tx_elem_len_2 = MSP_ELEM_LEN_16;
285
286 prot_desc->rx_clk_pol = MSP_RISING_EDGE;
287 prot_desc->tx_clk_pol = MSP_FALLING_EDGE;
288
289 prot_desc->rx_data_delay = MSP_DELAY_0;
290 prot_desc->tx_data_delay = MSP_DELAY_0;
291
292 prot_desc->tx_half_word_swap = MSP_SWAP_NONE;
293 prot_desc->rx_half_word_swap = MSP_SWAP_NONE;
294 prot_desc->compression_mode = MSP_COMPRESS_MODE_LINEAR;
295 prot_desc->expansion_mode = MSP_EXPAND_MODE_LINEAR;
296 prot_desc->frame_sync_ignore = MSP_FSYNC_IGNORE;
297
298 return 0;
299}
300
301static int setup_msp_config(struct snd_pcm_substream *substream,
302 struct snd_soc_dai *dai,
303 struct ux500_msp_config *msp_config)
304{
305 struct ux500_msp_i2s_drvdata *drvdata = dev_get_drvdata(dai->dev);
306 struct msp_protdesc *prot_desc = &msp_config->protdesc;
307 struct snd_pcm_runtime *runtime = substream->runtime;
308 unsigned int fmt = drvdata->fmt;
309 int ret;
310
311 memset(msp_config, 0, sizeof(*msp_config));
312
313 msp_config->f_inputclk = drvdata->master_clk;
314
315 msp_config->tx_fifo_config = TX_FIFO_ENABLE;
316 msp_config->rx_fifo_config = RX_FIFO_ENABLE;
317 msp_config->def_elem_len = 1;
318 msp_config->direction = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
319 MSP_DIR_TX : MSP_DIR_RX;
320 msp_config->data_size = MSP_DATA_BITS_32;
321 msp_config->frame_freq = runtime->rate;
322
323 dev_dbg(dai->dev, "%s: f_inputclk = %u, frame_freq = %u.\n",
324 __func__, msp_config->f_inputclk, msp_config->frame_freq);
325 /* To avoid division by zero */
326 prot_desc->clocks_per_frame = 1;
327
328 dev_dbg(dai->dev, "%s: rate: %u, channels: %d.\n", __func__,
329 runtime->rate, runtime->channels);
330 switch (fmt &
331 (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_MASTER_MASK)) {
332 case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS:
333 dev_dbg(dai->dev, "%s: SND_SOC_DAIFMT_I2S.\n", __func__);
334
335 msp_config->default_protdesc = 1;
336 msp_config->protocol = MSP_I2S_PROTOCOL;
337 break;
338
339 case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM:
340 dev_dbg(dai->dev, "%s: SND_SOC_DAIFMT_I2S.\n", __func__);
341
342 msp_config->data_size = MSP_DATA_BITS_16;
343 msp_config->protocol = MSP_I2S_PROTOCOL;
344
345 ret = setup_i2s_protdesc(prot_desc);
346 if (ret < 0)
347 return ret;
348
349 break;
350
351 case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBS_CFS:
352 case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBM_CFM:
353 case SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_CBS_CFS:
354 case SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_CBM_CFM:
355 dev_dbg(dai->dev, "%s: PCM format.\n", __func__);
356
357 msp_config->data_size = MSP_DATA_BITS_16;
358 msp_config->protocol = MSP_PCM_PROTOCOL;
359
360 ret = setup_pcm_protdesc(dai, fmt, prot_desc);
361 if (ret < 0)
362 return ret;
363
364 ret = setup_pcm_multichan(dai, msp_config);
365 if (ret < 0)
366 return ret;
367
368 ret = setup_pcm_framing(dai, runtime->rate, prot_desc);
369 if (ret < 0)
370 return ret;
371
372 break;
373
374 default:
375 dev_err(dai->dev, "%s: Error: Unsopported format (%d)!\n",
376 __func__, fmt);
377 return -EINVAL;
378 }
379
380 return setup_clocking(dai, fmt, msp_config);
381}
382
383static int ux500_msp_dai_startup(struct snd_pcm_substream *substream,
384 struct snd_soc_dai *dai)
385{
386 int ret = 0;
387 struct ux500_msp_i2s_drvdata *drvdata = dev_get_drvdata(dai->dev);
388
389 dev_dbg(dai->dev, "%s: MSP %d (%s): Enter.\n", __func__, dai->id,
390 snd_pcm_stream_str(substream));
391
392 /* Enable regulator */
393 ret = regulator_enable(drvdata->reg_vape);
394 if (ret != 0) {
395 dev_err(drvdata->msp->dev,
396 "%s: Failed to enable regulator!\n", __func__);
397 return ret;
398 }
399
f61ab093
UH		 400 /* Prepare and enable clocks */
401 dev_dbg(dai->dev, "%s: Enabling MSP-clocks.\n", __func__);
402 ret = clk_prepare_enable(drvdata->pclk);
403 if (ret) {
404 dev_err(drvdata->msp->dev,
405 "%s: Failed to prepare/enable pclk!\n", __func__);
406 goto err_pclk;
407 }
408
fe36a0b2 409 ret = clk_prepare_enable(drvdata->clk);
f61ab093
UH		 410 if (ret) {
411 dev_err(drvdata->msp->dev,
412 "%s: Failed to prepare/enable clk!\n", __func__);
413 goto err_clk;
414 }
3592b7f6 415
f61ab093
UH		 416 return ret;
417err_clk:
418 clk_disable_unprepare(drvdata->pclk);
419err_pclk:
420 regulator_disable(drvdata->reg_vape);
fe36a0b2 421 return ret;
3592b7f6
OL		 422}
423
424static void ux500_msp_dai_shutdown(struct snd_pcm_substream *substream,
425 struct snd_soc_dai *dai)
426{
427 int ret;
428 struct ux500_msp_i2s_drvdata *drvdata = dev_get_drvdata(dai->dev);
429 bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
430
431 dev_dbg(dai->dev, "%s: MSP %d (%s): Enter.\n", __func__, dai->id,
432 snd_pcm_stream_str(substream));
433
434 if (drvdata->vape_opp_constraint == 1) {
435 prcmu_qos_update_requirement(PRCMU_QOS_APE_OPP,
436 "ux500_msp_i2s", 50);
437 drvdata->vape_opp_constraint = 0;
438 }
439
440 if (ux500_msp_i2s_close(drvdata->msp,
441 is_playback ? MSP_DIR_TX : MSP_DIR_RX)) {
442 dev_err(dai->dev,
443 "%s: Error: MSP %d (%s): Unable to close i2s.\n",
444 __func__, dai->id, snd_pcm_stream_str(substream));
445 }
446
f61ab093 447 /* Disable and unprepare clocks */
fe36a0b2 448 clk_disable_unprepare(drvdata->clk);
f61ab093 449 clk_disable_unprepare(drvdata->pclk);
3592b7f6
OL		 450
451 /* Disable regulator */
452 ret = regulator_disable(drvdata->reg_vape);
453 if (ret < 0)
454 dev_err(dai->dev,
455 "%s: ERROR: Failed to disable regulator (%d)!\n",
456 __func__, ret);
457}
458
459static int ux500_msp_dai_prepare(struct snd_pcm_substream *substream,
460 struct snd_soc_dai *dai)
461{
462 int ret = 0;
463 struct ux500_msp_i2s_drvdata *drvdata = dev_get_drvdata(dai->dev);
464 struct snd_pcm_runtime *runtime = substream->runtime;
465 struct ux500_msp_config msp_config;
466
467 dev_dbg(dai->dev, "%s: MSP %d (%s): Enter (rate = %d).\n", __func__,
468 dai->id, snd_pcm_stream_str(substream), runtime->rate);
469
470 setup_msp_config(substream, dai, &msp_config);
471
472 ret = ux500_msp_i2s_open(drvdata->msp, &msp_config);
473 if (ret < 0) {
474 dev_err(dai->dev, "%s: Error: msp_setup failed (ret = %d)!\n",
475 __func__, ret);
476 return ret;
477 }
478
479 /* Set OPP-level */
480 if ((drvdata->fmt & SND_SOC_DAIFMT_MASTER_MASK) &&
481 (drvdata->msp->f_bitclk > 19200000)) {
482 /* If the bit-clock is higher than 19.2MHz, Vape should be
483 * run in 100% OPP. Only when bit-clock is used (MSP master) */
484 prcmu_qos_update_requirement(PRCMU_QOS_APE_OPP,
485 "ux500-msp-i2s", 100);
486 drvdata->vape_opp_constraint = 1;
487 } else {
488 prcmu_qos_update_requirement(PRCMU_QOS_APE_OPP,
489 "ux500-msp-i2s", 50);
490 drvdata->vape_opp_constraint = 0;
491 }
492
493 return ret;
494}
495
496static int ux500_msp_dai_hw_params(struct snd_pcm_substream *substream,
497 struct snd_pcm_hw_params *params,
498 struct snd_soc_dai *dai)
499{
500 unsigned int mask, slots_active;
501 struct snd_pcm_runtime *runtime = substream->runtime;
502 struct ux500_msp_i2s_drvdata *drvdata = dev_get_drvdata(dai->dev);
503
504 dev_dbg(dai->dev, "%s: MSP %d (%s): Enter.\n",
505 __func__, dai->id, snd_pcm_stream_str(substream));
506
507 switch (drvdata->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
508 case SND_SOC_DAIFMT_I2S:
509 snd_pcm_hw_constraint_minmax(runtime,
510 SNDRV_PCM_HW_PARAM_CHANNELS,
511 1, 2);
512 break;
513
514 case SND_SOC_DAIFMT_DSP_B:
515 case SND_SOC_DAIFMT_DSP_A:
516 mask = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
517 drvdata->tx_mask :
518 drvdata->rx_mask;
519
520 slots_active = hweight32(mask);
521 dev_dbg(dai->dev, "TDM-slots active: %d", slots_active);
522
523 snd_pcm_hw_constraint_minmax(runtime,
524 SNDRV_PCM_HW_PARAM_CHANNELS,
525 slots_active, slots_active);
526 break;
527
528 default:
529 dev_err(dai->dev,
530 "%s: Error: Unsupported protocol (fmt = 0x%x)!\n",
531 __func__, drvdata->fmt);
532 return -EINVAL;
533 }
534
535 return 0;
536}
537
538static int ux500_msp_dai_set_dai_fmt(struct snd_soc_dai *dai,
539 unsigned int fmt)
540{
541 struct ux500_msp_i2s_drvdata *drvdata = dev_get_drvdata(dai->dev);
542
543 dev_dbg(dai->dev, "%s: MSP %d: Enter.\n", __func__, dai->id);
544
545 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
546 SND_SOC_DAIFMT_MASTER_MASK)) {
547 case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS:
548 case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM:
549 case SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_CBS_CFS:
550 case SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_CBM_CFM:
551 case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBS_CFS:
552 case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBM_CFM:
553 break;
554
555 default:
556 dev_err(dai->dev,
557 "%s: Error: Unsupported protocol/master (fmt = 0x%x)!\n",
558 __func__, drvdata->fmt);
559 return -EINVAL;
560 }
561
562 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
563 case SND_SOC_DAIFMT_NB_NF:
564 case SND_SOC_DAIFMT_NB_IF:
565 case SND_SOC_DAIFMT_IB_IF:
566 break;
567
568 default:
569 dev_err(dai->dev,
570 "%s: Error: Unsupported inversion (fmt = 0x%x)!\n",
571 __func__, drvdata->fmt);
572 return -EINVAL;
573 }
574
575 drvdata->fmt = fmt;
576 return 0;
577}
578
579static int ux500_msp_dai_set_tdm_slot(struct snd_soc_dai *dai,
580 unsigned int tx_mask,
581 unsigned int rx_mask,
582 int slots, int slot_width)
583{
584 struct ux500_msp_i2s_drvdata *drvdata = dev_get_drvdata(dai->dev);
585 unsigned int cap;
586
587 switch (slots) {
588 case 1:
589 cap = 0x01;
590 break;
591 case 2:
592 cap = 0x03;
593 break;
594 case 8:
595 cap = 0xFF;
596 break;
597 case 16:
598 cap = 0xFFFF;
599 break;
600 default:
601 dev_err(dai->dev, "%s: Error: Unsupported slot-count (%d)!\n",
602 __func__, slots);
603 return -EINVAL;
604 }
605 drvdata->slots = slots;
606
607 if (!(slot_width == 16)) {
608 dev_err(dai->dev, "%s: Error: Unsupported slot-width (%d)!\n",
609 __func__, slot_width);
610 return -EINVAL;
611 }
612 drvdata->slot_width = slot_width;
613
614 drvdata->tx_mask = tx_mask & cap;
615 drvdata->rx_mask = rx_mask & cap;
616
617 return 0;
618}
619
620static int ux500_msp_dai_set_dai_sysclk(struct snd_soc_dai *dai,
621 int clk_id, unsigned int freq, int dir)
622{
623 struct ux500_msp_i2s_drvdata *drvdata = dev_get_drvdata(dai->dev);
624
625 dev_dbg(dai->dev, "%s: MSP %d: Enter. clk-id: %d, freq: %u.\n",
626 __func__, dai->id, clk_id, freq);
627
628 switch (clk_id) {
629 case UX500_MSP_MASTER_CLOCK:
630 drvdata->master_clk = freq;
631 break;
632
633 default:
634 dev_err(dai->dev, "%s: MSP %d: Invalid clk-id (%d)!\n",
635 __func__, dai->id, clk_id);
636 return -EINVAL;
637 }
638
639 return 0;
640}
641
642static int ux500_msp_dai_trigger(struct snd_pcm_substream *substream,
643 int cmd, struct snd_soc_dai *dai)
644{
645 int ret = 0;
646 struct ux500_msp_i2s_drvdata *drvdata = dev_get_drvdata(dai->dev);
647
648 dev_dbg(dai->dev, "%s: MSP %d (%s): Enter (msp->id = %d, cmd = %d).\n",
649 __func__, dai->id, snd_pcm_stream_str(substream),
650 (int)drvdata->msp->id, cmd);
651
652 ret = ux500_msp_i2s_trigger(drvdata->msp, cmd, substream->stream);
653
654 return ret;
655}
656
657static int ux500_msp_dai_probe(struct snd_soc_dai *dai)
658{
659 struct ux500_msp_i2s_drvdata *drvdata = dev_get_drvdata(dai->dev);
660
661 drvdata->playback_dma_data.dma_cfg = drvdata->msp->dma_cfg_tx;
662 drvdata->capture_dma_data.dma_cfg = drvdata->msp->dma_cfg_rx;
663
664 dai->playback_dma_data = &drvdata->playback_dma_data;
665 dai->capture_dma_data = &drvdata->capture_dma_data;
666
667 drvdata->playback_dma_data.data_size = drvdata->slot_width;
668 drvdata->capture_dma_data.data_size = drvdata->slot_width;
669
670 return 0;
671}
672
673static struct snd_soc_dai_ops ux500_msp_dai_ops[] = {
674 {
675 .set_sysclk = ux500_msp_dai_set_dai_sysclk,
676 .set_fmt = ux500_msp_dai_set_dai_fmt,
677 .set_tdm_slot = ux500_msp_dai_set_tdm_slot,
678 .startup = ux500_msp_dai_startup,
679 .shutdown = ux500_msp_dai_shutdown,
680 .prepare = ux500_msp_dai_prepare,
681 .trigger = ux500_msp_dai_trigger,
682 .hw_params = ux500_msp_dai_hw_params,
683 }
684};
685
686static struct snd_soc_dai_driver ux500_msp_dai_drv[UX500_NBR_OF_DAI] = {
687 {
688 .name = "ux500-msp-i2s.0",
689 .probe = ux500_msp_dai_probe,
690 .id = 0,
691 .suspend = NULL,
692 .resume = NULL,
693 .playback = {
694 .channels_min = UX500_MSP_MIN_CHANNELS,
695 .channels_max = UX500_MSP_MAX_CHANNELS,
696 .rates = UX500_I2S_RATES,
697 .formats = UX500_I2S_FORMATS,
698 },
699 .capture = {
700 .channels_min = UX500_MSP_MIN_CHANNELS,
701 .channels_max = UX500_MSP_MAX_CHANNELS,
702 .rates = UX500_I2S_RATES,
703 .formats = UX500_I2S_FORMATS,
704 },
705 .ops = ux500_msp_dai_ops,
706 },
707 {
708 .name = "ux500-msp-i2s.1",
709 .probe = ux500_msp_dai_probe,
710 .id = 1,
711 .suspend = NULL,
712 .resume = NULL,
713 .playback = {
714 .channels_min = UX500_MSP_MIN_CHANNELS,
715 .channels_max = UX500_MSP_MAX_CHANNELS,
716 .rates = UX500_I2S_RATES,
717 .formats = UX500_I2S_FORMATS,
718 },
719 .capture = {
720 .channels_min = UX500_MSP_MIN_CHANNELS,
721 .channels_max = UX500_MSP_MAX_CHANNELS,
722 .rates = UX500_I2S_RATES,
723 .formats = UX500_I2S_FORMATS,
724 },
725 .ops = ux500_msp_dai_ops,
726 },
727 {
728 .name = "ux500-msp-i2s.2",
729 .id = 2,
730 .probe = ux500_msp_dai_probe,
731 .suspend = NULL,
732 .resume = NULL,
733 .playback = {
734 .channels_min = UX500_MSP_MIN_CHANNELS,
735 .channels_max = UX500_MSP_MAX_CHANNELS,
736 .rates = UX500_I2S_RATES,
737 .formats = UX500_I2S_FORMATS,
738 },
739 .capture = {
740 .channels_min = UX500_MSP_MIN_CHANNELS,
741 .channels_max = UX500_MSP_MAX_CHANNELS,
742 .rates = UX500_I2S_RATES,
743 .formats = UX500_I2S_FORMATS,
744 },
745 .ops = ux500_msp_dai_ops,
746 },
747 {
748 .name = "ux500-msp-i2s.3",
749 .probe = ux500_msp_dai_probe,
750 .id = 3,
751 .suspend = NULL,
752 .resume = NULL,
753 .playback = {
754 .channels_min = UX500_MSP_MIN_CHANNELS,
755 .channels_max = UX500_MSP_MAX_CHANNELS,
756 .rates = UX500_I2S_RATES,
757 .formats = UX500_I2S_FORMATS,
758 },
759 .capture = {
760 .channels_min = UX500_MSP_MIN_CHANNELS,
761 .channels_max = UX500_MSP_MAX_CHANNELS,
762 .rates = UX500_I2S_RATES,
763 .formats = UX500_I2S_FORMATS,
764 },
765 .ops = ux500_msp_dai_ops,
766 },
767};
768
42277bdd
KM		 769static const struct snd_soc_component_driver ux500_msp_component = {
770 .name = "ux500-msp",
771};
772
773
da794876 774static int ux500_msp_drv_probe(struct platform_device *pdev)
3592b7f6
OL		 775{
776 struct ux500_msp_i2s_drvdata *drvdata;
777 int ret = 0;
778
779 dev_dbg(&pdev->dev, "%s: Enter (pdev->name = %s).\n", __func__,
780 pdev->name);
781
782 drvdata = devm_kzalloc(&pdev->dev,
783 sizeof(struct ux500_msp_i2s_drvdata),
784 GFP_KERNEL);
0dcd4742
LJ		 785 if (!drvdata)
786 return -ENOMEM;
787
3592b7f6
OL		 788 drvdata->fmt = 0;
789 drvdata->slots = 1;
790 drvdata->tx_mask = 0x01;
791 drvdata->rx_mask = 0x01;
792 drvdata->slot_width = 16;
793 drvdata->master_clk = MSP_INPUT_FREQ_APB;
794
795 drvdata->reg_vape = devm_regulator_get(&pdev->dev, "v-ape");
796 if (IS_ERR(drvdata->reg_vape)) {
797 ret = (int)PTR_ERR(drvdata->reg_vape);
798 dev_err(&pdev->dev,
799 "%s: ERROR: Failed to get Vape supply (%d)!\n",
800 __func__, ret);
801 return ret;
802 }
803 prcmu_qos_add_requirement(PRCMU_QOS_APE_OPP, (char *)pdev->name, 50);
804
f61ab093
UH		 805 drvdata->pclk = clk_get(&pdev->dev, "apb_pclk");
806 if (IS_ERR(drvdata->pclk)) {
807 ret = (int)PTR_ERR(drvdata->pclk);
808 dev_err(&pdev->dev, "%s: ERROR: clk_get of pclk failed (%d)!\n",
809 __func__, ret);
810 goto err_pclk;
811 }
812
3592b7f6
OL		 813 drvdata->clk = clk_get(&pdev->dev, NULL);
814 if (IS_ERR(drvdata->clk)) {
815 ret = (int)PTR_ERR(drvdata->clk);
816 dev_err(&pdev->dev, "%s: ERROR: clk_get failed (%d)!\n",
817 __func__, ret);
818 goto err_clk;
819 }
820
821 ret = ux500_msp_i2s_init_msp(pdev, &drvdata->msp,
822 pdev->dev.platform_data);
823 if (!drvdata->msp) {
824 dev_err(&pdev->dev,
825 "%s: ERROR: Failed to init MSP-struct (%d)!",
826 __func__, ret);
827 goto err_init_msp;
828 }
829 dev_set_drvdata(&pdev->dev, drvdata);
830
42277bdd
KM		 831 ret = snd_soc_register_component(&pdev->dev, &ux500_msp_component,
832 &ux500_msp_dai_drv[drvdata->msp->id], 1);
3592b7f6
OL		 833 if (ret < 0) {
834 dev_err(&pdev->dev, "Error: %s: Failed to register MSP%d!\n",
835 __func__, drvdata->msp->id);
836 goto err_init_msp;
837 }
838
1428c20f
LJ		 839 ret = ux500_pcm_register_platform(pdev);
840 if (ret < 0) {
841 dev_err(&pdev->dev,
842 "Error: %s: Failed to register PCM platform device!\n",
843 __func__);
844 goto err_reg_plat;
845 }
846
3592b7f6
OL		 847 return 0;
848
1428c20f 849err_reg_plat:
42277bdd 850 snd_soc_unregister_component(&pdev->dev);
3592b7f6
OL		 851err_init_msp:
852 clk_put(drvdata->clk);
3592b7f6 853err_clk:
f61ab093
UH		 854 clk_put(drvdata->pclk);
855err_pclk:
3592b7f6
OL		 856 devm_regulator_put(drvdata->reg_vape);
857
858 return ret;
859}
860
da794876 861static int ux500_msp_drv_remove(struct platform_device *pdev)
3592b7f6
OL		 862{
863 struct ux500_msp_i2s_drvdata *drvdata = dev_get_drvdata(&pdev->dev);
864
1428c20f
LJ		 865 ux500_pcm_unregister_platform(pdev);
866
42277bdd 867 snd_soc_unregister_component(&pdev->dev);
3592b7f6
OL		 868
869 devm_regulator_put(drvdata->reg_vape);
870 prcmu_qos_remove_requirement(PRCMU_QOS_APE_OPP, "ux500_msp_i2s");
871
872 clk_put(drvdata->clk);
f61ab093 873 clk_put(drvdata->pclk);
3592b7f6
OL		 874
875 ux500_msp_i2s_cleanup_msp(pdev, drvdata->msp);
876
877 return 0;
878}
879
49731c23
LJ		 880static const struct of_device_id ux500_msp_i2s_match[] = {
881 { .compatible = "stericsson,ux500-msp-i2s", },
882 {},
883};
884
3592b7f6
OL		 885static struct platform_driver msp_i2s_driver = {
886 .driver = {
887 .name = "ux500-msp-i2s",
888 .owner = THIS_MODULE,
49731c23 889 .of_match_table = ux500_msp_i2s_match,
3592b7f6
OL		 890 },
891 .probe = ux500_msp_drv_probe,
892 .remove = ux500_msp_drv_remove,
893};
894module_platform_driver(msp_i2s_driver);
895
85f24391 896MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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