| 1 | /* |
| 2 | * linux/arch/alpha/kernel/sys_eiger.c |
| 3 | * |
| 4 | * Copyright (C) 1995 David A Rusling |
| 5 | * Copyright (C) 1996, 1999 Jay A Estabrook |
| 6 | * Copyright (C) 1998, 1999 Richard Henderson |
| 7 | * Copyright (C) 1999 Iain Grant |
| 8 | * |
| 9 | * Code supporting the EIGER (EV6+TSUNAMI). |
| 10 | */ |
| 11 | |
| 12 | #include <linux/kernel.h> |
| 13 | #include <linux/types.h> |
| 14 | #include <linux/mm.h> |
| 15 | #include <linux/sched.h> |
| 16 | #include <linux/pci.h> |
| 17 | #include <linux/init.h> |
| 18 | #include <linux/bitops.h> |
| 19 | |
| 20 | #include <asm/ptrace.h> |
| 21 | #include <asm/dma.h> |
| 22 | #include <asm/irq.h> |
| 23 | #include <asm/mmu_context.h> |
| 24 | #include <asm/io.h> |
| 25 | #include <asm/pgtable.h> |
| 26 | #include <asm/core_tsunami.h> |
| 27 | #include <asm/hwrpb.h> |
| 28 | #include <asm/tlbflush.h> |
| 29 | |
| 30 | #include "proto.h" |
| 31 | #include "irq_impl.h" |
| 32 | #include "pci_impl.h" |
| 33 | #include "machvec_impl.h" |
| 34 | |
| 35 | |
| 36 | /* Note that this interrupt code is identical to TAKARA. */ |
| 37 | |
| 38 | /* Note mask bit is true for DISABLED irqs. */ |
| 39 | static unsigned long cached_irq_mask[2] = { -1, -1 }; |
| 40 | |
| 41 | static inline void |
| 42 | eiger_update_irq_hw(unsigned long irq, unsigned long mask) |
| 43 | { |
| 44 | int regaddr; |
| 45 | |
| 46 | mask = (irq >= 64 ? mask << 16 : mask >> ((irq - 16) & 0x30)); |
| 47 | regaddr = 0x510 + (((irq - 16) >> 2) & 0x0c); |
| 48 | outl(mask & 0xffff0000UL, regaddr); |
| 49 | } |
| 50 | |
| 51 | static inline void |
| 52 | eiger_enable_irq(struct irq_data *d) |
| 53 | { |
| 54 | unsigned int irq = d->irq; |
| 55 | unsigned long mask; |
| 56 | mask = (cached_irq_mask[irq >= 64] &= ~(1UL << (irq & 63))); |
| 57 | eiger_update_irq_hw(irq, mask); |
| 58 | } |
| 59 | |
| 60 | static void |
| 61 | eiger_disable_irq(struct irq_data *d) |
| 62 | { |
| 63 | unsigned int irq = d->irq; |
| 64 | unsigned long mask; |
| 65 | mask = (cached_irq_mask[irq >= 64] |= 1UL << (irq & 63)); |
| 66 | eiger_update_irq_hw(irq, mask); |
| 67 | } |
| 68 | |
| 69 | static struct irq_chip eiger_irq_type = { |
| 70 | .name = "EIGER", |
| 71 | .irq_unmask = eiger_enable_irq, |
| 72 | .irq_mask = eiger_disable_irq, |
| 73 | .irq_mask_ack = eiger_disable_irq, |
| 74 | }; |
| 75 | |
| 76 | static void |
| 77 | eiger_device_interrupt(unsigned long vector) |
| 78 | { |
| 79 | unsigned intstatus; |
| 80 | |
| 81 | /* |
| 82 | * The PALcode will have passed us vectors 0x800 or 0x810, |
| 83 | * which are fairly arbitrary values and serve only to tell |
| 84 | * us whether an interrupt has come in on IRQ0 or IRQ1. If |
| 85 | * it's IRQ1 it's a PCI interrupt; if it's IRQ0, it's |
| 86 | * probably ISA, but PCI interrupts can come through IRQ0 |
| 87 | * as well if the interrupt controller isn't in accelerated |
| 88 | * mode. |
| 89 | * |
| 90 | * OTOH, the accelerator thing doesn't seem to be working |
| 91 | * overly well, so what we'll do instead is try directly |
| 92 | * examining the Master Interrupt Register to see if it's a |
| 93 | * PCI interrupt, and if _not_ then we'll pass it on to the |
| 94 | * ISA handler. |
| 95 | */ |
| 96 | |
| 97 | intstatus = inw(0x500) & 15; |
| 98 | if (intstatus) { |
| 99 | /* |
| 100 | * This is a PCI interrupt. Check each bit and |
| 101 | * despatch an interrupt if it's set. |
| 102 | */ |
| 103 | |
| 104 | if (intstatus & 8) handle_irq(16+3); |
| 105 | if (intstatus & 4) handle_irq(16+2); |
| 106 | if (intstatus & 2) handle_irq(16+1); |
| 107 | if (intstatus & 1) handle_irq(16+0); |
| 108 | } else { |
| 109 | isa_device_interrupt(vector); |
| 110 | } |
| 111 | } |
| 112 | |
| 113 | static void |
| 114 | eiger_srm_device_interrupt(unsigned long vector) |
| 115 | { |
| 116 | int irq = (vector - 0x800) >> 4; |
| 117 | handle_irq(irq); |
| 118 | } |
| 119 | |
| 120 | static void __init |
| 121 | eiger_init_irq(void) |
| 122 | { |
| 123 | long i; |
| 124 | |
| 125 | outb(0, DMA1_RESET_REG); |
| 126 | outb(0, DMA2_RESET_REG); |
| 127 | outb(DMA_MODE_CASCADE, DMA2_MODE_REG); |
| 128 | outb(0, DMA2_MASK_REG); |
| 129 | |
| 130 | if (alpha_using_srm) |
| 131 | alpha_mv.device_interrupt = eiger_srm_device_interrupt; |
| 132 | |
| 133 | for (i = 16; i < 128; i += 16) |
| 134 | eiger_update_irq_hw(i, -1); |
| 135 | |
| 136 | init_i8259a_irqs(); |
| 137 | |
| 138 | for (i = 16; i < 128; ++i) { |
| 139 | irq_set_chip_and_handler(i, &eiger_irq_type, handle_level_irq); |
| 140 | irq_set_status_flags(i, IRQ_LEVEL); |
| 141 | } |
| 142 | } |
| 143 | |
| 144 | static int __init |
| 145 | eiger_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
| 146 | { |
| 147 | u8 irq_orig; |
| 148 | |
| 149 | /* The SRM console has already calculated out the IRQ value's for |
| 150 | option cards. As this works lets just read in the value already |
| 151 | set and change it to a useable value by Linux. |
| 152 | |
| 153 | All the IRQ values generated by the console are greater than 90, |
| 154 | so we subtract 80 because it is (90 - allocated ISA IRQ's). */ |
| 155 | |
| 156 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq_orig); |
| 157 | |
| 158 | return irq_orig - 0x80; |
| 159 | } |
| 160 | |
| 161 | static u8 __init |
| 162 | eiger_swizzle(struct pci_dev *dev, u8 *pinp) |
| 163 | { |
| 164 | struct pci_controller *hose = dev->sysdata; |
| 165 | int slot, pin = *pinp; |
| 166 | int bridge_count = 0; |
| 167 | |
| 168 | /* Find the number of backplane bridges. */ |
| 169 | int backplane = inw(0x502) & 0x0f; |
| 170 | |
| 171 | switch (backplane) |
| 172 | { |
| 173 | case 0x00: bridge_count = 0; break; /* No bridges */ |
| 174 | case 0x01: bridge_count = 1; break; /* 1 */ |
| 175 | case 0x03: bridge_count = 2; break; /* 2 */ |
| 176 | case 0x07: bridge_count = 3; break; /* 3 */ |
| 177 | case 0x0f: bridge_count = 4; break; /* 4 */ |
| 178 | }; |
| 179 | |
| 180 | slot = PCI_SLOT(dev->devfn); |
| 181 | while (dev->bus->self) { |
| 182 | /* Check for built-in bridges on hose 0. */ |
| 183 | if (hose->index == 0 |
| 184 | && (PCI_SLOT(dev->bus->self->devfn) |
| 185 | > 20 - bridge_count)) { |
| 186 | slot = PCI_SLOT(dev->devfn); |
| 187 | break; |
| 188 | } |
| 189 | /* Must be a card-based bridge. */ |
| 190 | pin = pci_swizzle_interrupt_pin(dev, pin); |
| 191 | |
| 192 | /* Move up the chain of bridges. */ |
| 193 | dev = dev->bus->self; |
| 194 | } |
| 195 | *pinp = pin; |
| 196 | return slot; |
| 197 | } |
| 198 | |
| 199 | /* |
| 200 | * The System Vectors |
| 201 | */ |
| 202 | |
| 203 | struct alpha_machine_vector eiger_mv __initmv = { |
| 204 | .vector_name = "Eiger", |
| 205 | DO_EV6_MMU, |
| 206 | DO_DEFAULT_RTC, |
| 207 | DO_TSUNAMI_IO, |
| 208 | .machine_check = tsunami_machine_check, |
| 209 | .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, |
| 210 | .min_io_address = DEFAULT_IO_BASE, |
| 211 | .min_mem_address = DEFAULT_MEM_BASE, |
| 212 | .pci_dac_offset = TSUNAMI_DAC_OFFSET, |
| 213 | |
| 214 | .nr_irqs = 128, |
| 215 | .device_interrupt = eiger_device_interrupt, |
| 216 | |
| 217 | .init_arch = tsunami_init_arch, |
| 218 | .init_irq = eiger_init_irq, |
| 219 | .init_rtc = common_init_rtc, |
| 220 | .init_pci = common_init_pci, |
| 221 | .kill_arch = tsunami_kill_arch, |
| 222 | .pci_map_irq = eiger_map_irq, |
| 223 | .pci_swizzle = eiger_swizzle, |
| 224 | }; |
| 225 | ALIAS_MV(eiger) |