| 1 | /* |
| 2 | * Low Level Interrupts/Traps/Exceptions(non-TLB) Handling for ARC |
| 3 | * |
| 4 | * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * vineetg: May 2011 |
| 11 | * -Userspace unaligned access emulation |
| 12 | * |
| 13 | * vineetg: Feb 2011 (ptrace low level code fixes) |
| 14 | * -traced syscall return code (r0) was not saved into pt_regs for restoring |
| 15 | * into user reg-file when traded task rets to user space. |
| 16 | * -syscalls needing arch-wrappers (mainly for passing sp as pt_regs) |
| 17 | * were not invoking post-syscall trace hook (jumping directly into |
| 18 | * ret_from_system_call) |
| 19 | * |
| 20 | * vineetg: Nov 2010: |
| 21 | * -Vector table jumps (@8 bytes) converted into branches (@4 bytes) |
| 22 | * -To maintain the slot size of 8 bytes/vector, added nop, which is |
| 23 | * not executed at runtime. |
| 24 | * |
| 25 | * vineetg: Nov 2009 (Everything needed for TIF_RESTORE_SIGMASK) |
| 26 | * -do_signal()invoked upon TIF_RESTORE_SIGMASK as well |
| 27 | * -Wrappers for sys_{,rt_}sigsuspend() nolonger needed as they don't |
| 28 | * need ptregs anymore |
| 29 | * |
| 30 | * Vineetg: Oct 2009 |
| 31 | * -In a rare scenario, Process gets a Priv-V exception and gets scheduled |
| 32 | * out. Since we don't do FAKE RTIE for Priv-V, CPU excpetion state remains |
| 33 | * active (AE bit enabled). This causes a double fault for a subseq valid |
| 34 | * exception. Thus FAKE RTIE needed in low level Priv-Violation handler. |
| 35 | * Instr Error could also cause similar scenario, so same there as well. |
| 36 | * |
| 37 | * Vineetg: March 2009 (Supporting 2 levels of Interrupts) |
| 38 | * |
| 39 | * Vineetg: Aug 28th 2008: Bug #94984 |
| 40 | * -Zero Overhead Loop Context shd be cleared when entering IRQ/EXcp/Trap |
| 41 | * Normally CPU does this automatically, however when doing FAKE rtie, |
| 42 | * we need to explicitly do this. The problem in macros |
| 43 | * FAKE_RET_FROM_EXCPN and FAKE_RET_FROM_EXCPN_LOCK_IRQ was that this bit |
| 44 | * was being "CLEARED" rather then "SET". Since it is Loop INHIBIT Bit, |
| 45 | * setting it and not clearing it clears ZOL context |
| 46 | * |
| 47 | * Vineetg: May 16th, 2008 |
| 48 | * - r25 now contains the Current Task when in kernel |
| 49 | * |
| 50 | * Vineetg: Dec 22, 2007 |
| 51 | * Minor Surgery of Low Level ISR to make it SMP safe |
| 52 | * - MMU_SCRATCH0 Reg used for freeing up r9 in Level 1 ISR |
| 53 | * - _current_task is made an array of NR_CPUS |
| 54 | * - Access of _current_task wrapped inside a macro so that if hardware |
| 55 | * team agrees for a dedicated reg, no other code is touched |
| 56 | * |
| 57 | * Amit Bhor, Rahul Trivedi, Kanika Nema, Sameer Dhavale : Codito Tech 2004 |
| 58 | */ |
| 59 | |
| 60 | /*------------------------------------------------------------------ |
| 61 | * Function ABI |
| 62 | *------------------------------------------------------------------ |
| 63 | * |
| 64 | * Arguments r0 - r7 |
| 65 | * Caller Saved Registers r0 - r12 |
| 66 | * Callee Saved Registers r13- r25 |
| 67 | * Global Pointer (gp) r26 |
| 68 | * Frame Pointer (fp) r27 |
| 69 | * Stack Pointer (sp) r28 |
| 70 | * Interrupt link register (ilink1) r29 |
| 71 | * Interrupt link register (ilink2) r30 |
| 72 | * Branch link register (blink) r31 |
| 73 | *------------------------------------------------------------------ |
| 74 | */ |
| 75 | |
| 76 | .cpu A7 |
| 77 | |
| 78 | ;############################ Vector Table ################################# |
| 79 | |
| 80 | .macro VECTOR lbl |
| 81 | #if 1 /* Just in case, build breaks */ |
| 82 | j \lbl |
| 83 | #else |
| 84 | b \lbl |
| 85 | nop |
| 86 | #endif |
| 87 | .endm |
| 88 | |
| 89 | .section .vector, "ax",@progbits |
| 90 | .align 4 |
| 91 | |
| 92 | /* Each entry in the vector table must occupy 2 words. Since it is a jump |
| 93 | * across sections (.vector to .text) we are gauranteed that 'j somewhere' |
| 94 | * will use the 'j limm' form of the intrsuction as long as somewhere is in |
| 95 | * a section other than .vector. |
| 96 | */ |
| 97 | |
| 98 | ; ********* Critical System Events ********************** |
| 99 | VECTOR res_service ; 0x0, Restart Vector (0x0) |
| 100 | VECTOR mem_service ; 0x8, Mem exception (0x1) |
| 101 | VECTOR instr_service ; 0x10, Instrn Error (0x2) |
| 102 | |
| 103 | ; ******************** Device ISRs ********************** |
| 104 | #ifdef CONFIG_ARC_IRQ3_LV2 |
| 105 | VECTOR handle_interrupt_level2 |
| 106 | #else |
| 107 | VECTOR handle_interrupt_level1 |
| 108 | #endif |
| 109 | |
| 110 | VECTOR handle_interrupt_level1 |
| 111 | |
| 112 | #ifdef CONFIG_ARC_IRQ5_LV2 |
| 113 | VECTOR handle_interrupt_level2 |
| 114 | #else |
| 115 | VECTOR handle_interrupt_level1 |
| 116 | #endif |
| 117 | |
| 118 | #ifdef CONFIG_ARC_IRQ6_LV2 |
| 119 | VECTOR handle_interrupt_level2 |
| 120 | #else |
| 121 | VECTOR handle_interrupt_level1 |
| 122 | #endif |
| 123 | |
| 124 | .rept 25 |
| 125 | VECTOR handle_interrupt_level1 ; Other devices |
| 126 | .endr |
| 127 | |
| 128 | /* FOR ARC600: timer = 0x3, uart = 0x8, emac = 0x10 */ |
| 129 | |
| 130 | ; ******************** Exceptions ********************** |
| 131 | VECTOR EV_MachineCheck ; 0x100, Fatal Machine check (0x20) |
| 132 | VECTOR EV_TLBMissI ; 0x108, Intruction TLB miss (0x21) |
| 133 | VECTOR EV_TLBMissD ; 0x110, Data TLB miss (0x22) |
| 134 | VECTOR EV_TLBProtV ; 0x118, Protection Violation (0x23) |
| 135 | ; or Misaligned Access |
| 136 | VECTOR EV_PrivilegeV ; 0x120, Privilege Violation (0x24) |
| 137 | VECTOR EV_Trap ; 0x128, Trap exception (0x25) |
| 138 | VECTOR EV_Extension ; 0x130, Extn Intruction Excp (0x26) |
| 139 | |
| 140 | .rept 24 |
| 141 | VECTOR reserved ; Reserved Exceptions |
| 142 | .endr |
| 143 | |
| 144 | #include <linux/linkage.h> /* ARC_{EXTRY,EXIT} */ |
| 145 | #include <asm/entry.h> /* SAVE_ALL_{INT1,INT2,SYS...} */ |
| 146 | #include <asm/errno.h> |
| 147 | #include <asm/arcregs.h> |
| 148 | #include <asm/irqflags.h> |
| 149 | |
| 150 | ;##################### Scratch Mem for IRQ stack switching ############# |
| 151 | |
| 152 | ARCFP_DATA int1_saved_reg |
| 153 | .align 32 |
| 154 | .type int1_saved_reg, @object |
| 155 | .size int1_saved_reg, 4 |
| 156 | int1_saved_reg: |
| 157 | .zero 4 |
| 158 | |
| 159 | /* Each Interrupt level needs it's own scratch */ |
| 160 | #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS |
| 161 | |
| 162 | ARCFP_DATA int2_saved_reg |
| 163 | .type int2_saved_reg, @object |
| 164 | .size int2_saved_reg, 4 |
| 165 | int2_saved_reg: |
| 166 | .zero 4 |
| 167 | |
| 168 | #endif |
| 169 | |
| 170 | ; --------------------------------------------- |
| 171 | .section .text, "ax",@progbits |
| 172 | |
| 173 | res_service: ; processor restart |
| 174 | flag 0x1 ; not implemented |
| 175 | nop |
| 176 | nop |
| 177 | |
| 178 | reserved: ; processor restart |
| 179 | rtie ; jump to processor initializations |
| 180 | |
| 181 | ;##################### Interrupt Handling ############################## |
| 182 | |
| 183 | #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS |
| 184 | ; --------------------------------------------- |
| 185 | ; Level 2 ISR: Can interrupt a Level 1 ISR |
| 186 | ; --------------------------------------------- |
| 187 | ARC_ENTRY handle_interrupt_level2 |
| 188 | |
| 189 | ; TODO-vineetg for SMP this wont work |
| 190 | ; free up r9 as scratchpad |
| 191 | st r9, [@int2_saved_reg] |
| 192 | |
| 193 | ;Which mode (user/kernel) was the system in when intr occured |
| 194 | lr r9, [status32_l2] |
| 195 | |
| 196 | SWITCH_TO_KERNEL_STK |
| 197 | SAVE_ALL_INT2 |
| 198 | |
| 199 | ;------------------------------------------------------ |
| 200 | ; if L2 IRQ interrupted a L1 ISR, disable preemption |
| 201 | ;------------------------------------------------------ |
| 202 | |
| 203 | ld r9, [sp, PT_status32] ; get statu32_l2 (saved in pt_regs) |
| 204 | bbit0 r9, STATUS_A1_BIT, 1f ; L1 not active when L2 IRQ, so normal |
| 205 | |
| 206 | ; A1 is set in status32_l2 |
| 207 | ; bump thread_info->preempt_count (Disable preemption) |
| 208 | GET_CURR_THR_INFO_FROM_SP r10 |
| 209 | ld r9, [r10, THREAD_INFO_PREEMPT_COUNT] |
| 210 | add r9, r9, 1 |
| 211 | st r9, [r10, THREAD_INFO_PREEMPT_COUNT] |
| 212 | |
| 213 | 1: |
| 214 | ;------------------------------------------------------ |
| 215 | ; setup params for Linux common ISR and invoke it |
| 216 | ;------------------------------------------------------ |
| 217 | lr r0, [icause2] |
| 218 | and r0, r0, 0x1f |
| 219 | |
| 220 | bl.d @arch_do_IRQ |
| 221 | mov r1, sp |
| 222 | |
| 223 | mov r8,0x2 |
| 224 | sr r8, [AUX_IRQ_LV12] ; clear bit in Sticky Status Reg |
| 225 | |
| 226 | b ret_from_exception |
| 227 | |
| 228 | ARC_EXIT handle_interrupt_level2 |
| 229 | |
| 230 | #endif |
| 231 | |
| 232 | ; --------------------------------------------- |
| 233 | ; Level 1 ISR |
| 234 | ; --------------------------------------------- |
| 235 | ARC_ENTRY handle_interrupt_level1 |
| 236 | |
| 237 | /* free up r9 as scratchpad */ |
| 238 | #ifdef CONFIG_SMP |
| 239 | sr r9, [ARC_REG_SCRATCH_DATA0] |
| 240 | #else |
| 241 | st r9, [@int1_saved_reg] |
| 242 | #endif |
| 243 | |
| 244 | ;Which mode (user/kernel) was the system in when intr occured |
| 245 | lr r9, [status32_l1] |
| 246 | |
| 247 | SWITCH_TO_KERNEL_STK |
| 248 | SAVE_ALL_INT1 |
| 249 | |
| 250 | lr r0, [icause1] |
| 251 | and r0, r0, 0x1f |
| 252 | |
| 253 | #ifdef CONFIG_TRACE_IRQFLAGS |
| 254 | ; icause1 needs to be read early, before calling tracing, which |
| 255 | ; can clobber scratch regs, hence use of stack to stash it |
| 256 | push r0 |
| 257 | TRACE_ASM_IRQ_DISABLE |
| 258 | pop r0 |
| 259 | #endif |
| 260 | |
| 261 | bl.d @arch_do_IRQ |
| 262 | mov r1, sp |
| 263 | |
| 264 | mov r8,0x1 |
| 265 | sr r8, [AUX_IRQ_LV12] ; clear bit in Sticky Status Reg |
| 266 | |
| 267 | b ret_from_exception |
| 268 | ARC_EXIT handle_interrupt_level1 |
| 269 | |
| 270 | ;################### Non TLB Exception Handling ############################# |
| 271 | |
| 272 | ; --------------------------------------------- |
| 273 | ; Instruction Error Exception Handler |
| 274 | ; --------------------------------------------- |
| 275 | |
| 276 | ARC_ENTRY instr_service |
| 277 | |
| 278 | EXCEPTION_PROLOGUE |
| 279 | |
| 280 | lr r0, [efa] |
| 281 | mov r1, sp |
| 282 | |
| 283 | FAKE_RET_FROM_EXCPN r9 |
| 284 | |
| 285 | bl do_insterror_or_kprobe |
| 286 | b ret_from_exception |
| 287 | ARC_EXIT instr_service |
| 288 | |
| 289 | ; --------------------------------------------- |
| 290 | ; Memory Error Exception Handler |
| 291 | ; --------------------------------------------- |
| 292 | |
| 293 | ARC_ENTRY mem_service |
| 294 | |
| 295 | EXCEPTION_PROLOGUE |
| 296 | |
| 297 | lr r0, [efa] |
| 298 | mov r1, sp |
| 299 | |
| 300 | FAKE_RET_FROM_EXCPN r9 |
| 301 | |
| 302 | bl do_memory_error |
| 303 | b ret_from_exception |
| 304 | ARC_EXIT mem_service |
| 305 | |
| 306 | ; --------------------------------------------- |
| 307 | ; Machine Check Exception Handler |
| 308 | ; --------------------------------------------- |
| 309 | |
| 310 | ARC_ENTRY EV_MachineCheck |
| 311 | |
| 312 | EXCEPTION_PROLOGUE |
| 313 | |
| 314 | lr r2, [ecr] |
| 315 | lr r0, [efa] |
| 316 | mov r1, sp |
| 317 | |
| 318 | lsr r3, r2, 8 |
| 319 | bmsk r3, r3, 7 |
| 320 | brne r3, ECR_C_MCHK_DUP_TLB, 1f |
| 321 | |
| 322 | bl do_tlb_overlap_fault |
| 323 | b ret_from_exception |
| 324 | |
| 325 | 1: |
| 326 | ; DEAD END: can't do much, display Regs and HALT |
| 327 | SAVE_CALLEE_SAVED_USER |
| 328 | |
| 329 | GET_CURR_TASK_FIELD_PTR TASK_THREAD, r10 |
| 330 | st sp, [r10, THREAD_CALLEE_REG] |
| 331 | |
| 332 | j do_machine_check_fault |
| 333 | |
| 334 | ARC_EXIT EV_MachineCheck |
| 335 | |
| 336 | ; --------------------------------------------- |
| 337 | ; Protection Violation Exception Handler |
| 338 | ; --------------------------------------------- |
| 339 | |
| 340 | ARC_ENTRY EV_TLBProtV |
| 341 | |
| 342 | EXCEPTION_PROLOGUE |
| 343 | |
| 344 | ;---------(3) Save some more regs----------------- |
| 345 | ; vineetg: Mar 6th: Random Seg Fault issue #1 |
| 346 | ; ecr and efa were not saved in case an Intr sneaks in |
| 347 | ; after fake rtie |
| 348 | |
| 349 | lr r2, [ecr] |
| 350 | lr r0, [efa] ; Faulting Data address |
| 351 | |
| 352 | ; --------(4) Return from CPU Exception Mode --------- |
| 353 | ; Fake a rtie, but rtie to next label |
| 354 | ; That way, subsequently, do_page_fault ( ) executes in pure kernel |
| 355 | ; mode with further Exceptions enabled |
| 356 | |
| 357 | FAKE_RET_FROM_EXCPN r9 |
| 358 | |
| 359 | mov r1, sp |
| 360 | |
| 361 | ;------ (5) Type of Protection Violation? ---------- |
| 362 | ; |
| 363 | ; ProtV Hardware Exception is triggered for Access Faults of 2 types |
| 364 | ; -Access Violaton : 00_23_(00|01|02|03)_00 |
| 365 | ; x r w r+w |
| 366 | ; -Unaligned Access : 00_23_04_00 |
| 367 | ; |
| 368 | bbit1 r2, ECR_C_BIT_PROTV_MISALIG_DATA, 4f |
| 369 | |
| 370 | ;========= (6a) Access Violation Processing ======== |
| 371 | bl do_page_fault |
| 372 | b ret_from_exception |
| 373 | |
| 374 | ;========== (6b) Non aligned access ============ |
| 375 | 4: |
| 376 | |
| 377 | SAVE_CALLEE_SAVED_USER |
| 378 | mov r2, sp ; callee_regs |
| 379 | |
| 380 | bl do_misaligned_access |
| 381 | |
| 382 | ; TBD: optimize - do this only if a callee reg was involved |
| 383 | ; either a dst of emulated LD/ST or src with address-writeback |
| 384 | RESTORE_CALLEE_SAVED_USER |
| 385 | |
| 386 | b ret_from_exception |
| 387 | |
| 388 | ARC_EXIT EV_TLBProtV |
| 389 | |
| 390 | ; --------------------------------------------- |
| 391 | ; Privilege Violation Exception Handler |
| 392 | ; --------------------------------------------- |
| 393 | ARC_ENTRY EV_PrivilegeV |
| 394 | |
| 395 | EXCEPTION_PROLOGUE |
| 396 | |
| 397 | lr r0, [efa] |
| 398 | mov r1, sp |
| 399 | |
| 400 | FAKE_RET_FROM_EXCPN r9 |
| 401 | |
| 402 | bl do_privilege_fault |
| 403 | b ret_from_exception |
| 404 | ARC_EXIT EV_PrivilegeV |
| 405 | |
| 406 | ; --------------------------------------------- |
| 407 | ; Extension Instruction Exception Handler |
| 408 | ; --------------------------------------------- |
| 409 | ARC_ENTRY EV_Extension |
| 410 | |
| 411 | EXCEPTION_PROLOGUE |
| 412 | |
| 413 | lr r0, [efa] |
| 414 | mov r1, sp |
| 415 | |
| 416 | FAKE_RET_FROM_EXCPN r9 |
| 417 | |
| 418 | bl do_extension_fault |
| 419 | b ret_from_exception |
| 420 | ARC_EXIT EV_Extension |
| 421 | |
| 422 | ;######################### System Call Tracing ######################### |
| 423 | |
| 424 | tracesys: |
| 425 | ; save EFA in case tracer wants the PC of traced task |
| 426 | ; using ERET won't work since next-PC has already committed |
| 427 | lr r12, [efa] |
| 428 | GET_CURR_TASK_FIELD_PTR TASK_THREAD, r11 |
| 429 | st r12, [r11, THREAD_FAULT_ADDR] ; thread.fault_address |
| 430 | |
| 431 | ; PRE Sys Call Ptrace hook |
| 432 | mov r0, sp ; pt_regs needed |
| 433 | bl @syscall_trace_entry |
| 434 | |
| 435 | ; Tracing code now returns the syscall num (orig or modif) |
| 436 | mov r8, r0 |
| 437 | |
| 438 | ; Do the Sys Call as we normally would. |
| 439 | ; Validate the Sys Call number |
| 440 | cmp r8, NR_syscalls |
| 441 | mov.hi r0, -ENOSYS |
| 442 | bhi tracesys_exit |
| 443 | |
| 444 | ; Restore the sys-call args. Mere invocation of the hook abv could have |
| 445 | ; clobbered them (since they are in scratch regs). The tracer could also |
| 446 | ; have deliberately changed the syscall args: r0-r7 |
| 447 | ld r0, [sp, PT_r0] |
| 448 | ld r1, [sp, PT_r1] |
| 449 | ld r2, [sp, PT_r2] |
| 450 | ld r3, [sp, PT_r3] |
| 451 | ld r4, [sp, PT_r4] |
| 452 | ld r5, [sp, PT_r5] |
| 453 | ld r6, [sp, PT_r6] |
| 454 | ld r7, [sp, PT_r7] |
| 455 | ld.as r9, [sys_call_table, r8] |
| 456 | jl [r9] ; Entry into Sys Call Handler |
| 457 | |
| 458 | tracesys_exit: |
| 459 | st r0, [sp, PT_r0] ; sys call return value in pt_regs |
| 460 | |
| 461 | ;POST Sys Call Ptrace Hook |
| 462 | bl @syscall_trace_exit |
| 463 | b ret_from_exception ; NOT ret_from_system_call at is saves r0 which |
| 464 | ; we'd done before calling post hook above |
| 465 | |
| 466 | ;################### Break Point TRAP ########################## |
| 467 | |
| 468 | ; ======= (5b) Trap is due to Break-Point ========= |
| 469 | |
| 470 | trap_with_param: |
| 471 | |
| 472 | ; stop_pc info by gdb needs this info |
| 473 | lr r0, [efa] |
| 474 | mov r1, sp |
| 475 | |
| 476 | ; Now that we have read EFA, its safe to do "fake" rtie |
| 477 | ; and get out of CPU exception mode |
| 478 | FAKE_RET_FROM_EXCPN r11 |
| 479 | |
| 480 | ; Save callee regs in case gdb wants to have a look |
| 481 | ; SP will grow up by size of CALLEE Reg-File |
| 482 | ; NOTE: clobbers r12 |
| 483 | SAVE_CALLEE_SAVED_USER |
| 484 | |
| 485 | ; save location of saved Callee Regs @ thread_struct->pc |
| 486 | GET_CURR_TASK_FIELD_PTR TASK_THREAD, r10 |
| 487 | st sp, [r10, THREAD_CALLEE_REG] |
| 488 | |
| 489 | ; Call the trap handler |
| 490 | bl do_non_swi_trap |
| 491 | |
| 492 | ; unwind stack to discard Callee saved Regs |
| 493 | DISCARD_CALLEE_SAVED_USER |
| 494 | |
| 495 | b ret_from_exception |
| 496 | |
| 497 | ;##################### Trap Handling ############################## |
| 498 | ; |
| 499 | ; EV_Trap caused by TRAP_S and TRAP0 instructions. |
| 500 | ;------------------------------------------------------------------ |
| 501 | ; (1) System Calls |
| 502 | ; :parameters in r0-r7. |
| 503 | ; :r8 has the system call number |
| 504 | ; (2) Break Points |
| 505 | ;------------------------------------------------------------------ |
| 506 | |
| 507 | ARC_ENTRY EV_Trap |
| 508 | |
| 509 | EXCEPTION_PROLOGUE |
| 510 | |
| 511 | ;------- (4) What caused the Trap -------------- |
| 512 | lr r12, [ecr] |
| 513 | bmsk.f 0, r12, 7 |
| 514 | bnz trap_with_param |
| 515 | |
| 516 | ; ======= (5a) Trap is due to System Call ======== |
| 517 | |
| 518 | ; Before doing anything, return from CPU Exception Mode |
| 519 | FAKE_RET_FROM_EXCPN r11 |
| 520 | |
| 521 | ; If syscall tracing ongoing, invoke pre-pos-hooks |
| 522 | GET_CURR_THR_INFO_FLAGS r10 |
| 523 | btst r10, TIF_SYSCALL_TRACE |
| 524 | bnz tracesys ; this never comes back |
| 525 | |
| 526 | ;============ This is normal System Call case ========== |
| 527 | ; Sys-call num shd not exceed the total system calls avail |
| 528 | cmp r8, NR_syscalls |
| 529 | mov.hi r0, -ENOSYS |
| 530 | bhi ret_from_system_call |
| 531 | |
| 532 | ; Offset into the syscall_table and call handler |
| 533 | ld.as r9,[sys_call_table, r8] |
| 534 | jl [r9] ; Entry into Sys Call Handler |
| 535 | |
| 536 | ; fall through to ret_from_system_call |
| 537 | ARC_EXIT EV_Trap |
| 538 | |
| 539 | ARC_ENTRY ret_from_system_call |
| 540 | |
| 541 | st r0, [sp, PT_r0] ; sys call return value in pt_regs |
| 542 | |
| 543 | ; fall through yet again to ret_from_exception |
| 544 | |
| 545 | ;############# Return from Intr/Excp/Trap (Linux Specifics) ############## |
| 546 | ; |
| 547 | ; If ret to user mode do we need to handle signals, schedule() et al. |
| 548 | |
| 549 | ARC_ENTRY ret_from_exception |
| 550 | |
| 551 | ; Pre-{IRQ,Trap,Exception} K/U mode from pt_regs->status32 |
| 552 | ld r8, [sp, PT_status32] ; returning to User/Kernel Mode |
| 553 | |
| 554 | bbit0 r8, STATUS_U_BIT, resume_kernel_mode |
| 555 | |
| 556 | ; Before returning to User mode check-for-and-complete any pending work |
| 557 | ; such as rescheduling/signal-delivery etc. |
| 558 | resume_user_mode_begin: |
| 559 | |
| 560 | ; Disable IRQs to ensures that chk for pending work itself is atomic |
| 561 | ; (and we don't end up missing a NEED_RESCHED/SIGPENDING due to an |
| 562 | ; interim IRQ). |
| 563 | IRQ_DISABLE r10 |
| 564 | |
| 565 | ; Fast Path return to user mode if no pending work |
| 566 | GET_CURR_THR_INFO_FLAGS r9 |
| 567 | and.f 0, r9, _TIF_WORK_MASK |
| 568 | bz restore_regs |
| 569 | |
| 570 | ; --- (Slow Path #1) task preemption --- |
| 571 | bbit0 r9, TIF_NEED_RESCHED, .Lchk_pend_signals |
| 572 | mov blink, resume_user_mode_begin ; tail-call to U mode ret chks |
| 573 | b @schedule ; BTST+Bnz causes relo error in link |
| 574 | |
| 575 | .Lchk_pend_signals: |
| 576 | IRQ_ENABLE r10 |
| 577 | |
| 578 | ; --- (Slow Path #2) pending signal --- |
| 579 | mov r0, sp ; pt_regs for arg to do_signal()/do_notify_resume() |
| 580 | |
| 581 | GET_CURR_THR_INFO_FLAGS r9 |
| 582 | bbit0 r9, TIF_SIGPENDING, .Lchk_notify_resume |
| 583 | |
| 584 | ; Normal Trap/IRQ entry only saves Scratch (caller-saved) regs |
| 585 | ; in pt_reg since the "C" ABI (kernel code) will automatically |
| 586 | ; save/restore callee-saved regs. |
| 587 | ; |
| 588 | ; However, here we need to explicitly save callee regs because |
| 589 | ; (i) If this signal causes coredump - full regfile needed |
| 590 | ; (ii) If signal is SIGTRAP/SIGSTOP, task is being traced thus |
| 591 | ; tracer might call PEEKUSR(CALLEE reg) |
| 592 | ; |
| 593 | ; NOTE: SP will grow up by size of CALLEE Reg-File |
| 594 | SAVE_CALLEE_SAVED_USER ; clobbers r12 |
| 595 | |
| 596 | ; save location of saved Callee Regs @ thread_struct->callee |
| 597 | GET_CURR_TASK_FIELD_PTR TASK_THREAD, r10 |
| 598 | st sp, [r10, THREAD_CALLEE_REG] |
| 599 | |
| 600 | bl @do_signal |
| 601 | |
| 602 | ; Ideally we want to discard the Callee reg above, however if this was |
| 603 | ; a tracing signal, tracer could have done a POKEUSR(CALLEE reg) |
| 604 | RESTORE_CALLEE_SAVED_USER |
| 605 | |
| 606 | b resume_user_mode_begin ; loop back to start of U mode ret |
| 607 | |
| 608 | ; --- (Slow Path #3) notify_resume --- |
| 609 | .Lchk_notify_resume: |
| 610 | btst r9, TIF_NOTIFY_RESUME |
| 611 | blnz @do_notify_resume |
| 612 | b resume_user_mode_begin ; unconditionally back to U mode ret chks |
| 613 | ; for single exit point from this block |
| 614 | |
| 615 | resume_kernel_mode: |
| 616 | |
| 617 | #ifdef CONFIG_PREEMPT |
| 618 | |
| 619 | ; This is a must for preempt_schedule_irq() |
| 620 | IRQ_DISABLE r9 |
| 621 | |
| 622 | ; Can't preempt if preemption disabled |
| 623 | GET_CURR_THR_INFO_FROM_SP r10 |
| 624 | ld r8, [r10, THREAD_INFO_PREEMPT_COUNT] |
| 625 | brne r8, 0, restore_regs |
| 626 | |
| 627 | ; check if this task's NEED_RESCHED flag set |
| 628 | ld r9, [r10, THREAD_INFO_FLAGS] |
| 629 | bbit0 r9, TIF_NEED_RESCHED, restore_regs |
| 630 | |
| 631 | ; Invoke PREEMPTION |
| 632 | bl preempt_schedule_irq |
| 633 | |
| 634 | ; preempt_schedule_irq() always returns with IRQ disabled |
| 635 | #endif |
| 636 | |
| 637 | ; fall through |
| 638 | |
| 639 | ;############# Return from Intr/Excp/Trap (ARC Specifics) ############## |
| 640 | ; |
| 641 | ; Restore the saved sys context (common exit-path for EXCPN/IRQ/Trap) |
| 642 | ; IRQ shd definitely not happen between now and rtie |
| 643 | ; All 2 entry points to here already disable interrupts |
| 644 | |
| 645 | restore_regs : |
| 646 | |
| 647 | TRACE_ASM_IRQ_ENABLE |
| 648 | |
| 649 | lr r10, [status32] |
| 650 | |
| 651 | ; Restore REG File. In case multiple Events outstanding, |
| 652 | ; use the same priorty as rtie: EXCPN, L2 IRQ, L1 IRQ, None |
| 653 | ; Note that we use realtime STATUS32 (not pt_regs->status32) to |
| 654 | ; decide that. |
| 655 | |
| 656 | ; if Returning from Exception |
| 657 | bbit0 r10, STATUS_AE_BIT, not_exception |
| 658 | RESTORE_ALL_SYS |
| 659 | rtie |
| 660 | |
| 661 | ; Not Exception so maybe Interrupts (Level 1 or 2) |
| 662 | |
| 663 | not_exception: |
| 664 | |
| 665 | #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS |
| 666 | |
| 667 | ; Level 2 interrupt return Path - from hardware standpoint |
| 668 | bbit0 r10, STATUS_A2_BIT, not_level2_interrupt |
| 669 | |
| 670 | ;------------------------------------------------------------------ |
| 671 | ; However the context returning might not have taken L2 intr itself |
| 672 | ; e.g. Task'A' user-code -> L2 intr -> schedule -> 'B' user-code ret |
| 673 | ; Special considerations needed for the context which took L2 intr |
| 674 | |
| 675 | ld r9, [sp, PT_event] ; Ensure this is L2 intr context |
| 676 | brne r9, event_IRQ2, 149f |
| 677 | |
| 678 | ;------------------------------------------------------------------ |
| 679 | ; if L2 IRQ interrupted a L1 ISR, we'd disbaled preemption earlier |
| 680 | ; so that sched doesnt move to new task, causing L1 to be delayed |
| 681 | ; undeterministically. Now that we've achieved that, lets reset |
| 682 | ; things to what they were, before returning from L2 context |
| 683 | ;---------------------------------------------------------------- |
| 684 | |
| 685 | ld r9, [sp, PT_status32] ; get statu32_l2 (saved in pt_regs) |
| 686 | bbit0 r9, STATUS_A1_BIT, 149f ; L1 not active when L2 IRQ, so normal |
| 687 | |
| 688 | ; decrement thread_info->preempt_count (re-enable preemption) |
| 689 | GET_CURR_THR_INFO_FROM_SP r10 |
| 690 | ld r9, [r10, THREAD_INFO_PREEMPT_COUNT] |
| 691 | |
| 692 | ; paranoid check, given A1 was active when A2 happened, preempt count |
| 693 | ; must not be 0 because we would have incremented it. |
| 694 | ; If this does happen we simply HALT as it means a BUG !!! |
| 695 | cmp r9, 0 |
| 696 | bnz 2f |
| 697 | flag 1 |
| 698 | |
| 699 | 2: |
| 700 | sub r9, r9, 1 |
| 701 | st r9, [r10, THREAD_INFO_PREEMPT_COUNT] |
| 702 | |
| 703 | 149: |
| 704 | ;return from level 2 |
| 705 | RESTORE_ALL_INT2 |
| 706 | debug_marker_l2: |
| 707 | rtie |
| 708 | |
| 709 | not_level2_interrupt: |
| 710 | |
| 711 | #endif |
| 712 | |
| 713 | bbit0 r10, STATUS_A1_BIT, not_level1_interrupt |
| 714 | |
| 715 | ;return from level 1 |
| 716 | |
| 717 | RESTORE_ALL_INT1 |
| 718 | debug_marker_l1: |
| 719 | rtie |
| 720 | |
| 721 | not_level1_interrupt: |
| 722 | |
| 723 | ;this case is for syscalls or Exceptions (with fake rtie) |
| 724 | |
| 725 | RESTORE_ALL_SYS |
| 726 | debug_marker_syscall: |
| 727 | rtie |
| 728 | |
| 729 | ARC_EXIT ret_from_exception |
| 730 | |
| 731 | ARC_ENTRY ret_from_fork |
| 732 | ; when the forked child comes here from the __switch_to function |
| 733 | ; r0 has the last task pointer. |
| 734 | ; put last task in scheduler queue |
| 735 | bl @schedule_tail |
| 736 | |
| 737 | ; If kernel thread, jump to it's entry-point |
| 738 | ld r9, [sp, PT_status32] |
| 739 | brne r9, 0, 1f |
| 740 | |
| 741 | jl.d [r14] |
| 742 | mov r0, r13 ; arg to payload |
| 743 | |
| 744 | 1: |
| 745 | ; special case of kernel_thread entry point returning back due to |
| 746 | ; kernel_execve() - pretend return from syscall to ret to userland |
| 747 | b ret_from_exception |
| 748 | ARC_EXIT ret_from_fork |
| 749 | |
| 750 | ;################### Special Sys Call Wrappers ########################## |
| 751 | |
| 752 | ARC_ENTRY sys_clone_wrapper |
| 753 | SAVE_CALLEE_SAVED_USER |
| 754 | bl @sys_clone |
| 755 | DISCARD_CALLEE_SAVED_USER |
| 756 | |
| 757 | GET_CURR_THR_INFO_FLAGS r10 |
| 758 | btst r10, TIF_SYSCALL_TRACE |
| 759 | bnz tracesys_exit |
| 760 | |
| 761 | b ret_from_system_call |
| 762 | ARC_EXIT sys_clone_wrapper |
| 763 | |
| 764 | #ifdef CONFIG_ARC_DW2_UNWIND |
| 765 | ; Workaround for bug 94179 (STAR ): |
| 766 | ; Despite -fasynchronous-unwind-tables, linker is not making dwarf2 unwinder |
| 767 | ; section (.debug_frame) as loadable. So we force it here. |
| 768 | ; This also fixes STAR 9000487933 where the prev-workaround (objcopy --setflag) |
| 769 | ; would not work after a clean build due to kernel build system dependencies. |
| 770 | .section .debug_frame, "wa",@progbits |
| 771 | #endif |