| 1 | config ARM64 |
| 2 | def_bool y |
| 3 | select ACPI_CCA_REQUIRED if ACPI |
| 4 | select ACPI_GENERIC_GSI if ACPI |
| 5 | select ACPI_REDUCED_HARDWARE_ONLY if ACPI |
| 6 | select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE |
| 7 | select ARCH_HAS_ELF_RANDOMIZE |
| 8 | select ARCH_HAS_GCOV_PROFILE_ALL |
| 9 | select ARCH_HAS_SG_CHAIN |
| 10 | select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST |
| 11 | select ARCH_USE_CMPXCHG_LOCKREF |
| 12 | select ARCH_SUPPORTS_ATOMIC_RMW |
| 13 | select ARCH_WANT_OPTIONAL_GPIOLIB |
| 14 | select ARCH_WANT_COMPAT_IPC_PARSE_VERSION |
| 15 | select ARCH_WANT_FRAME_POINTERS |
| 16 | select ARM_AMBA |
| 17 | select ARM_ARCH_TIMER |
| 18 | select ARM_GIC |
| 19 | select AUDIT_ARCH_COMPAT_GENERIC |
| 20 | select ARM_GIC_V2M if PCI_MSI |
| 21 | select ARM_GIC_V3 |
| 22 | select ARM_GIC_V3_ITS if PCI_MSI |
| 23 | select ARM_PSCI_FW |
| 24 | select BUILDTIME_EXTABLE_SORT |
| 25 | select CLONE_BACKWARDS |
| 26 | select COMMON_CLK |
| 27 | select CPU_PM if (SUSPEND || CPU_IDLE) |
| 28 | select DCACHE_WORD_ACCESS |
| 29 | select EDAC_SUPPORT |
| 30 | select GENERIC_ALLOCATOR |
| 31 | select GENERIC_CLOCKEVENTS |
| 32 | select GENERIC_CLOCKEVENTS_BROADCAST |
| 33 | select GENERIC_CPU_AUTOPROBE |
| 34 | select GENERIC_EARLY_IOREMAP |
| 35 | select GENERIC_IDLE_POLL_SETUP |
| 36 | select GENERIC_IRQ_PROBE |
| 37 | select GENERIC_IRQ_SHOW |
| 38 | select GENERIC_IRQ_SHOW_LEVEL |
| 39 | select GENERIC_PCI_IOMAP |
| 40 | select GENERIC_SCHED_CLOCK |
| 41 | select GENERIC_SMP_IDLE_THREAD |
| 42 | select GENERIC_STRNCPY_FROM_USER |
| 43 | select GENERIC_STRNLEN_USER |
| 44 | select GENERIC_TIME_VSYSCALL |
| 45 | select HANDLE_DOMAIN_IRQ |
| 46 | select HARDIRQS_SW_RESEND |
| 47 | select HAVE_ALIGNED_STRUCT_PAGE if SLUB |
| 48 | select HAVE_ARCH_AUDITSYSCALL |
| 49 | select HAVE_ARCH_BITREVERSE |
| 50 | select HAVE_ARCH_JUMP_LABEL |
| 51 | select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP |
| 52 | select HAVE_ARCH_KGDB |
| 53 | select HAVE_ARCH_SECCOMP_FILTER |
| 54 | select HAVE_ARCH_TRACEHOOK |
| 55 | select HAVE_BPF_JIT |
| 56 | select HAVE_C_RECORDMCOUNT |
| 57 | select HAVE_CC_STACKPROTECTOR |
| 58 | select HAVE_CMPXCHG_DOUBLE |
| 59 | select HAVE_CMPXCHG_LOCAL |
| 60 | select HAVE_DEBUG_BUGVERBOSE |
| 61 | select HAVE_DEBUG_KMEMLEAK |
| 62 | select HAVE_DMA_API_DEBUG |
| 63 | select HAVE_DMA_ATTRS |
| 64 | select HAVE_DMA_CONTIGUOUS |
| 65 | select HAVE_DYNAMIC_FTRACE |
| 66 | select HAVE_EFFICIENT_UNALIGNED_ACCESS |
| 67 | select HAVE_FTRACE_MCOUNT_RECORD |
| 68 | select HAVE_FUNCTION_TRACER |
| 69 | select HAVE_FUNCTION_GRAPH_TRACER |
| 70 | select HAVE_GENERIC_DMA_COHERENT |
| 71 | select HAVE_HW_BREAKPOINT if PERF_EVENTS |
| 72 | select HAVE_MEMBLOCK |
| 73 | select HAVE_PATA_PLATFORM |
| 74 | select HAVE_PERF_EVENTS |
| 75 | select HAVE_PERF_REGS |
| 76 | select HAVE_PERF_USER_STACK_DUMP |
| 77 | select HAVE_RCU_TABLE_FREE |
| 78 | select HAVE_SYSCALL_TRACEPOINTS |
| 79 | select IRQ_DOMAIN |
| 80 | select IRQ_FORCED_THREADING |
| 81 | select MODULES_USE_ELF_RELA |
| 82 | select NO_BOOTMEM |
| 83 | select OF |
| 84 | select OF_EARLY_FLATTREE |
| 85 | select OF_RESERVED_MEM |
| 86 | select PERF_USE_VMALLOC |
| 87 | select POWER_RESET |
| 88 | select POWER_SUPPLY |
| 89 | select RTC_LIB |
| 90 | select SPARSE_IRQ |
| 91 | select SYSCTL_EXCEPTION_TRACE |
| 92 | select HAVE_CONTEXT_TRACKING |
| 93 | help |
| 94 | ARM 64-bit (AArch64) Linux support. |
| 95 | |
| 96 | config 64BIT |
| 97 | def_bool y |
| 98 | |
| 99 | config ARCH_PHYS_ADDR_T_64BIT |
| 100 | def_bool y |
| 101 | |
| 102 | config MMU |
| 103 | def_bool y |
| 104 | |
| 105 | config NO_IOPORT_MAP |
| 106 | def_bool y if !PCI |
| 107 | |
| 108 | config STACKTRACE_SUPPORT |
| 109 | def_bool y |
| 110 | |
| 111 | config ILLEGAL_POINTER_VALUE |
| 112 | hex |
| 113 | default 0xdead000000000000 |
| 114 | |
| 115 | config LOCKDEP_SUPPORT |
| 116 | def_bool y |
| 117 | |
| 118 | config TRACE_IRQFLAGS_SUPPORT |
| 119 | def_bool y |
| 120 | |
| 121 | config RWSEM_XCHGADD_ALGORITHM |
| 122 | def_bool y |
| 123 | |
| 124 | config GENERIC_BUG |
| 125 | def_bool y |
| 126 | depends on BUG |
| 127 | |
| 128 | config GENERIC_BUG_RELATIVE_POINTERS |
| 129 | def_bool y |
| 130 | depends on GENERIC_BUG |
| 131 | |
| 132 | config GENERIC_HWEIGHT |
| 133 | def_bool y |
| 134 | |
| 135 | config GENERIC_CSUM |
| 136 | def_bool y |
| 137 | |
| 138 | config GENERIC_CALIBRATE_DELAY |
| 139 | def_bool y |
| 140 | |
| 141 | config ZONE_DMA |
| 142 | def_bool y |
| 143 | |
| 144 | config HAVE_GENERIC_RCU_GUP |
| 145 | def_bool y |
| 146 | |
| 147 | config ARCH_DMA_ADDR_T_64BIT |
| 148 | def_bool y |
| 149 | |
| 150 | config NEED_DMA_MAP_STATE |
| 151 | def_bool y |
| 152 | |
| 153 | config NEED_SG_DMA_LENGTH |
| 154 | def_bool y |
| 155 | |
| 156 | config SMP |
| 157 | def_bool y |
| 158 | |
| 159 | config SWIOTLB |
| 160 | def_bool y |
| 161 | |
| 162 | config IOMMU_HELPER |
| 163 | def_bool SWIOTLB |
| 164 | |
| 165 | config KERNEL_MODE_NEON |
| 166 | def_bool y |
| 167 | |
| 168 | config FIX_EARLYCON_MEM |
| 169 | def_bool y |
| 170 | |
| 171 | config PGTABLE_LEVELS |
| 172 | int |
| 173 | default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 |
| 174 | default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 |
| 175 | default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48 |
| 176 | default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 |
| 177 | default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 |
| 178 | default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 |
| 179 | |
| 180 | source "init/Kconfig" |
| 181 | |
| 182 | source "kernel/Kconfig.freezer" |
| 183 | |
| 184 | source "arch/arm64/Kconfig.platforms" |
| 185 | |
| 186 | menu "Bus support" |
| 187 | |
| 188 | config PCI |
| 189 | bool "PCI support" |
| 190 | help |
| 191 | This feature enables support for PCI bus system. If you say Y |
| 192 | here, the kernel will include drivers and infrastructure code |
| 193 | to support PCI bus devices. |
| 194 | |
| 195 | config PCI_DOMAINS |
| 196 | def_bool PCI |
| 197 | |
| 198 | config PCI_DOMAINS_GENERIC |
| 199 | def_bool PCI |
| 200 | |
| 201 | config PCI_SYSCALL |
| 202 | def_bool PCI |
| 203 | |
| 204 | source "drivers/pci/Kconfig" |
| 205 | source "drivers/pci/pcie/Kconfig" |
| 206 | source "drivers/pci/hotplug/Kconfig" |
| 207 | |
| 208 | endmenu |
| 209 | |
| 210 | menu "Kernel Features" |
| 211 | |
| 212 | menu "ARM errata workarounds via the alternatives framework" |
| 213 | |
| 214 | config ARM64_ERRATUM_826319 |
| 215 | bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" |
| 216 | default y |
| 217 | help |
| 218 | This option adds an alternative code sequence to work around ARM |
| 219 | erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or |
| 220 | AXI master interface and an L2 cache. |
| 221 | |
| 222 | If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors |
| 223 | and is unable to accept a certain write via this interface, it will |
| 224 | not progress on read data presented on the read data channel and the |
| 225 | system can deadlock. |
| 226 | |
| 227 | The workaround promotes data cache clean instructions to |
| 228 | data cache clean-and-invalidate. |
| 229 | Please note that this does not necessarily enable the workaround, |
| 230 | as it depends on the alternative framework, which will only patch |
| 231 | the kernel if an affected CPU is detected. |
| 232 | |
| 233 | If unsure, say Y. |
| 234 | |
| 235 | config ARM64_ERRATUM_827319 |
| 236 | bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" |
| 237 | default y |
| 238 | help |
| 239 | This option adds an alternative code sequence to work around ARM |
| 240 | erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI |
| 241 | master interface and an L2 cache. |
| 242 | |
| 243 | Under certain conditions this erratum can cause a clean line eviction |
| 244 | to occur at the same time as another transaction to the same address |
| 245 | on the AMBA 5 CHI interface, which can cause data corruption if the |
| 246 | interconnect reorders the two transactions. |
| 247 | |
| 248 | The workaround promotes data cache clean instructions to |
| 249 | data cache clean-and-invalidate. |
| 250 | Please note that this does not necessarily enable the workaround, |
| 251 | as it depends on the alternative framework, which will only patch |
| 252 | the kernel if an affected CPU is detected. |
| 253 | |
| 254 | If unsure, say Y. |
| 255 | |
| 256 | config ARM64_ERRATUM_824069 |
| 257 | bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" |
| 258 | default y |
| 259 | help |
| 260 | This option adds an alternative code sequence to work around ARM |
| 261 | erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected |
| 262 | to a coherent interconnect. |
| 263 | |
| 264 | If a Cortex-A53 processor is executing a store or prefetch for |
| 265 | write instruction at the same time as a processor in another |
| 266 | cluster is executing a cache maintenance operation to the same |
| 267 | address, then this erratum might cause a clean cache line to be |
| 268 | incorrectly marked as dirty. |
| 269 | |
| 270 | The workaround promotes data cache clean instructions to |
| 271 | data cache clean-and-invalidate. |
| 272 | Please note that this option does not necessarily enable the |
| 273 | workaround, as it depends on the alternative framework, which will |
| 274 | only patch the kernel if an affected CPU is detected. |
| 275 | |
| 276 | If unsure, say Y. |
| 277 | |
| 278 | config ARM64_ERRATUM_819472 |
| 279 | bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" |
| 280 | default y |
| 281 | help |
| 282 | This option adds an alternative code sequence to work around ARM |
| 283 | erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache |
| 284 | present when it is connected to a coherent interconnect. |
| 285 | |
| 286 | If the processor is executing a load and store exclusive sequence at |
| 287 | the same time as a processor in another cluster is executing a cache |
| 288 | maintenance operation to the same address, then this erratum might |
| 289 | cause data corruption. |
| 290 | |
| 291 | The workaround promotes data cache clean instructions to |
| 292 | data cache clean-and-invalidate. |
| 293 | Please note that this does not necessarily enable the workaround, |
| 294 | as it depends on the alternative framework, which will only patch |
| 295 | the kernel if an affected CPU is detected. |
| 296 | |
| 297 | If unsure, say Y. |
| 298 | |
| 299 | config ARM64_ERRATUM_832075 |
| 300 | bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" |
| 301 | default y |
| 302 | help |
| 303 | This option adds an alternative code sequence to work around ARM |
| 304 | erratum 832075 on Cortex-A57 parts up to r1p2. |
| 305 | |
| 306 | Affected Cortex-A57 parts might deadlock when exclusive load/store |
| 307 | instructions to Write-Back memory are mixed with Device loads. |
| 308 | |
| 309 | The workaround is to promote device loads to use Load-Acquire |
| 310 | semantics. |
| 311 | Please note that this does not necessarily enable the workaround, |
| 312 | as it depends on the alternative framework, which will only patch |
| 313 | the kernel if an affected CPU is detected. |
| 314 | |
| 315 | If unsure, say Y. |
| 316 | |
| 317 | config ARM64_ERRATUM_845719 |
| 318 | bool "Cortex-A53: 845719: a load might read incorrect data" |
| 319 | depends on COMPAT |
| 320 | default y |
| 321 | help |
| 322 | This option adds an alternative code sequence to work around ARM |
| 323 | erratum 845719 on Cortex-A53 parts up to r0p4. |
| 324 | |
| 325 | When running a compat (AArch32) userspace on an affected Cortex-A53 |
| 326 | part, a load at EL0 from a virtual address that matches the bottom 32 |
| 327 | bits of the virtual address used by a recent load at (AArch64) EL1 |
| 328 | might return incorrect data. |
| 329 | |
| 330 | The workaround is to write the contextidr_el1 register on exception |
| 331 | return to a 32-bit task. |
| 332 | Please note that this does not necessarily enable the workaround, |
| 333 | as it depends on the alternative framework, which will only patch |
| 334 | the kernel if an affected CPU is detected. |
| 335 | |
| 336 | If unsure, say Y. |
| 337 | |
| 338 | config ARM64_ERRATUM_843419 |
| 339 | bool "Cortex-A53: 843419: A load or store might access an incorrect address" |
| 340 | depends on MODULES |
| 341 | default y |
| 342 | help |
| 343 | This option builds kernel modules using the large memory model in |
| 344 | order to avoid the use of the ADRP instruction, which can cause |
| 345 | a subsequent memory access to use an incorrect address on Cortex-A53 |
| 346 | parts up to r0p4. |
| 347 | |
| 348 | Note that the kernel itself must be linked with a version of ld |
| 349 | which fixes potentially affected ADRP instructions through the |
| 350 | use of veneers. |
| 351 | |
| 352 | If unsure, say Y. |
| 353 | |
| 354 | config CAVIUM_ERRATUM_22375 |
| 355 | bool "Cavium erratum 22375, 24313" |
| 356 | default y |
| 357 | help |
| 358 | Enable workaround for erratum 22375, 24313. |
| 359 | |
| 360 | This implements two gicv3-its errata workarounds for ThunderX. Both |
| 361 | with small impact affecting only ITS table allocation. |
| 362 | |
| 363 | erratum 22375: only alloc 8MB table size |
| 364 | erratum 24313: ignore memory access type |
| 365 | |
| 366 | The fixes are in ITS initialization and basically ignore memory access |
| 367 | type and table size provided by the TYPER and BASER registers. |
| 368 | |
| 369 | If unsure, say Y. |
| 370 | |
| 371 | config CAVIUM_ERRATUM_23154 |
| 372 | bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed" |
| 373 | default y |
| 374 | help |
| 375 | The gicv3 of ThunderX requires a modified version for |
| 376 | reading the IAR status to ensure data synchronization |
| 377 | (access to icc_iar1_el1 is not sync'ed before and after). |
| 378 | |
| 379 | If unsure, say Y. |
| 380 | |
| 381 | endmenu |
| 382 | |
| 383 | |
| 384 | choice |
| 385 | prompt "Page size" |
| 386 | default ARM64_4K_PAGES |
| 387 | help |
| 388 | Page size (translation granule) configuration. |
| 389 | |
| 390 | config ARM64_4K_PAGES |
| 391 | bool "4KB" |
| 392 | help |
| 393 | This feature enables 4KB pages support. |
| 394 | |
| 395 | config ARM64_16K_PAGES |
| 396 | bool "16KB" |
| 397 | help |
| 398 | The system will use 16KB pages support. AArch32 emulation |
| 399 | requires applications compiled with 16K (or a multiple of 16K) |
| 400 | aligned segments. |
| 401 | |
| 402 | config ARM64_64K_PAGES |
| 403 | bool "64KB" |
| 404 | help |
| 405 | This feature enables 64KB pages support (4KB by default) |
| 406 | allowing only two levels of page tables and faster TLB |
| 407 | look-up. AArch32 emulation requires applications compiled |
| 408 | with 64K aligned segments. |
| 409 | |
| 410 | endchoice |
| 411 | |
| 412 | choice |
| 413 | prompt "Virtual address space size" |
| 414 | default ARM64_VA_BITS_39 if ARM64_4K_PAGES |
| 415 | default ARM64_VA_BITS_47 if ARM64_16K_PAGES |
| 416 | default ARM64_VA_BITS_42 if ARM64_64K_PAGES |
| 417 | help |
| 418 | Allows choosing one of multiple possible virtual address |
| 419 | space sizes. The level of translation table is determined by |
| 420 | a combination of page size and virtual address space size. |
| 421 | |
| 422 | config ARM64_VA_BITS_36 |
| 423 | bool "36-bit" if EXPERT |
| 424 | depends on ARM64_16K_PAGES |
| 425 | |
| 426 | config ARM64_VA_BITS_39 |
| 427 | bool "39-bit" |
| 428 | depends on ARM64_4K_PAGES |
| 429 | |
| 430 | config ARM64_VA_BITS_42 |
| 431 | bool "42-bit" |
| 432 | depends on ARM64_64K_PAGES |
| 433 | |
| 434 | config ARM64_VA_BITS_47 |
| 435 | bool "47-bit" |
| 436 | depends on ARM64_16K_PAGES |
| 437 | |
| 438 | config ARM64_VA_BITS_48 |
| 439 | bool "48-bit" |
| 440 | |
| 441 | endchoice |
| 442 | |
| 443 | config ARM64_VA_BITS |
| 444 | int |
| 445 | default 36 if ARM64_VA_BITS_36 |
| 446 | default 39 if ARM64_VA_BITS_39 |
| 447 | default 42 if ARM64_VA_BITS_42 |
| 448 | default 47 if ARM64_VA_BITS_47 |
| 449 | default 48 if ARM64_VA_BITS_48 |
| 450 | |
| 451 | config CPU_BIG_ENDIAN |
| 452 | bool "Build big-endian kernel" |
| 453 | help |
| 454 | Say Y if you plan on running a kernel in big-endian mode. |
| 455 | |
| 456 | config SCHED_MC |
| 457 | bool "Multi-core scheduler support" |
| 458 | help |
| 459 | Multi-core scheduler support improves the CPU scheduler's decision |
| 460 | making when dealing with multi-core CPU chips at a cost of slightly |
| 461 | increased overhead in some places. If unsure say N here. |
| 462 | |
| 463 | config SCHED_SMT |
| 464 | bool "SMT scheduler support" |
| 465 | help |
| 466 | Improves the CPU scheduler's decision making when dealing with |
| 467 | MultiThreading at a cost of slightly increased overhead in some |
| 468 | places. If unsure say N here. |
| 469 | |
| 470 | config NR_CPUS |
| 471 | int "Maximum number of CPUs (2-4096)" |
| 472 | range 2 4096 |
| 473 | # These have to remain sorted largest to smallest |
| 474 | default "64" |
| 475 | |
| 476 | config HOTPLUG_CPU |
| 477 | bool "Support for hot-pluggable CPUs" |
| 478 | select GENERIC_IRQ_MIGRATION |
| 479 | help |
| 480 | Say Y here to experiment with turning CPUs off and on. CPUs |
| 481 | can be controlled through /sys/devices/system/cpu. |
| 482 | |
| 483 | source kernel/Kconfig.preempt |
| 484 | source kernel/Kconfig.hz |
| 485 | |
| 486 | config ARCH_HAS_HOLES_MEMORYMODEL |
| 487 | def_bool y if SPARSEMEM |
| 488 | |
| 489 | config ARCH_SPARSEMEM_ENABLE |
| 490 | def_bool y |
| 491 | select SPARSEMEM_VMEMMAP_ENABLE |
| 492 | |
| 493 | config ARCH_SPARSEMEM_DEFAULT |
| 494 | def_bool ARCH_SPARSEMEM_ENABLE |
| 495 | |
| 496 | config ARCH_SELECT_MEMORY_MODEL |
| 497 | def_bool ARCH_SPARSEMEM_ENABLE |
| 498 | |
| 499 | config HAVE_ARCH_PFN_VALID |
| 500 | def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM |
| 501 | |
| 502 | config HW_PERF_EVENTS |
| 503 | def_bool y |
| 504 | depends on ARM_PMU |
| 505 | |
| 506 | config SYS_SUPPORTS_HUGETLBFS |
| 507 | def_bool y |
| 508 | |
| 509 | config ARCH_WANT_GENERAL_HUGETLB |
| 510 | def_bool y |
| 511 | |
| 512 | config ARCH_WANT_HUGE_PMD_SHARE |
| 513 | def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) |
| 514 | |
| 515 | config HAVE_ARCH_TRANSPARENT_HUGEPAGE |
| 516 | def_bool y |
| 517 | |
| 518 | config ARCH_HAS_CACHE_LINE_SIZE |
| 519 | def_bool y |
| 520 | |
| 521 | source "mm/Kconfig" |
| 522 | |
| 523 | config SECCOMP |
| 524 | bool "Enable seccomp to safely compute untrusted bytecode" |
| 525 | ---help--- |
| 526 | This kernel feature is useful for number crunching applications |
| 527 | that may need to compute untrusted bytecode during their |
| 528 | execution. By using pipes or other transports made available to |
| 529 | the process as file descriptors supporting the read/write |
| 530 | syscalls, it's possible to isolate those applications in |
| 531 | their own address space using seccomp. Once seccomp is |
| 532 | enabled via prctl(PR_SET_SECCOMP), it cannot be disabled |
| 533 | and the task is only allowed to execute a few safe syscalls |
| 534 | defined by each seccomp mode. |
| 535 | |
| 536 | config XEN_DOM0 |
| 537 | def_bool y |
| 538 | depends on XEN |
| 539 | |
| 540 | config XEN |
| 541 | bool "Xen guest support on ARM64" |
| 542 | depends on ARM64 && OF |
| 543 | select SWIOTLB_XEN |
| 544 | help |
| 545 | Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. |
| 546 | |
| 547 | config FORCE_MAX_ZONEORDER |
| 548 | int |
| 549 | default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE) |
| 550 | default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE) |
| 551 | default "11" |
| 552 | help |
| 553 | The kernel memory allocator divides physically contiguous memory |
| 554 | blocks into "zones", where each zone is a power of two number of |
| 555 | pages. This option selects the largest power of two that the kernel |
| 556 | keeps in the memory allocator. If you need to allocate very large |
| 557 | blocks of physically contiguous memory, then you may need to |
| 558 | increase this value. |
| 559 | |
| 560 | This config option is actually maximum order plus one. For example, |
| 561 | a value of 11 means that the largest free memory block is 2^10 pages. |
| 562 | |
| 563 | We make sure that we can allocate upto a HugePage size for each configuration. |
| 564 | Hence we have : |
| 565 | MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2 |
| 566 | |
| 567 | However for 4K, we choose a higher default value, 11 as opposed to 10, giving us |
| 568 | 4M allocations matching the default size used by generic code. |
| 569 | |
| 570 | menuconfig ARMV8_DEPRECATED |
| 571 | bool "Emulate deprecated/obsolete ARMv8 instructions" |
| 572 | depends on COMPAT |
| 573 | help |
| 574 | Legacy software support may require certain instructions |
| 575 | that have been deprecated or obsoleted in the architecture. |
| 576 | |
| 577 | Enable this config to enable selective emulation of these |
| 578 | features. |
| 579 | |
| 580 | If unsure, say Y |
| 581 | |
| 582 | if ARMV8_DEPRECATED |
| 583 | |
| 584 | config SWP_EMULATION |
| 585 | bool "Emulate SWP/SWPB instructions" |
| 586 | help |
| 587 | ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that |
| 588 | they are always undefined. Say Y here to enable software |
| 589 | emulation of these instructions for userspace using LDXR/STXR. |
| 590 | |
| 591 | In some older versions of glibc [<=2.8] SWP is used during futex |
| 592 | trylock() operations with the assumption that the code will not |
| 593 | be preempted. This invalid assumption may be more likely to fail |
| 594 | with SWP emulation enabled, leading to deadlock of the user |
| 595 | application. |
| 596 | |
| 597 | NOTE: when accessing uncached shared regions, LDXR/STXR rely |
| 598 | on an external transaction monitoring block called a global |
| 599 | monitor to maintain update atomicity. If your system does not |
| 600 | implement a global monitor, this option can cause programs that |
| 601 | perform SWP operations to uncached memory to deadlock. |
| 602 | |
| 603 | If unsure, say Y |
| 604 | |
| 605 | config CP15_BARRIER_EMULATION |
| 606 | bool "Emulate CP15 Barrier instructions" |
| 607 | help |
| 608 | The CP15 barrier instructions - CP15ISB, CP15DSB, and |
| 609 | CP15DMB - are deprecated in ARMv8 (and ARMv7). It is |
| 610 | strongly recommended to use the ISB, DSB, and DMB |
| 611 | instructions instead. |
| 612 | |
| 613 | Say Y here to enable software emulation of these |
| 614 | instructions for AArch32 userspace code. When this option is |
| 615 | enabled, CP15 barrier usage is traced which can help |
| 616 | identify software that needs updating. |
| 617 | |
| 618 | If unsure, say Y |
| 619 | |
| 620 | config SETEND_EMULATION |
| 621 | bool "Emulate SETEND instruction" |
| 622 | help |
| 623 | The SETEND instruction alters the data-endianness of the |
| 624 | AArch32 EL0, and is deprecated in ARMv8. |
| 625 | |
| 626 | Say Y here to enable software emulation of the instruction |
| 627 | for AArch32 userspace code. |
| 628 | |
| 629 | Note: All the cpus on the system must have mixed endian support at EL0 |
| 630 | for this feature to be enabled. If a new CPU - which doesn't support mixed |
| 631 | endian - is hotplugged in after this feature has been enabled, there could |
| 632 | be unexpected results in the applications. |
| 633 | |
| 634 | If unsure, say Y |
| 635 | endif |
| 636 | |
| 637 | menu "ARMv8.1 architectural features" |
| 638 | |
| 639 | config ARM64_HW_AFDBM |
| 640 | bool "Support for hardware updates of the Access and Dirty page flags" |
| 641 | default y |
| 642 | help |
| 643 | The ARMv8.1 architecture extensions introduce support for |
| 644 | hardware updates of the access and dirty information in page |
| 645 | table entries. When enabled in TCR_EL1 (HA and HD bits) on |
| 646 | capable processors, accesses to pages with PTE_AF cleared will |
| 647 | set this bit instead of raising an access flag fault. |
| 648 | Similarly, writes to read-only pages with the DBM bit set will |
| 649 | clear the read-only bit (AP[2]) instead of raising a |
| 650 | permission fault. |
| 651 | |
| 652 | Kernels built with this configuration option enabled continue |
| 653 | to work on pre-ARMv8.1 hardware and the performance impact is |
| 654 | minimal. If unsure, say Y. |
| 655 | |
| 656 | config ARM64_PAN |
| 657 | bool "Enable support for Privileged Access Never (PAN)" |
| 658 | default y |
| 659 | help |
| 660 | Privileged Access Never (PAN; part of the ARMv8.1 Extensions) |
| 661 | prevents the kernel or hypervisor from accessing user-space (EL0) |
| 662 | memory directly. |
| 663 | |
| 664 | Choosing this option will cause any unprotected (not using |
| 665 | copy_to_user et al) memory access to fail with a permission fault. |
| 666 | |
| 667 | The feature is detected at runtime, and will remain as a 'nop' |
| 668 | instruction if the cpu does not implement the feature. |
| 669 | |
| 670 | config ARM64_LSE_ATOMICS |
| 671 | bool "Atomic instructions" |
| 672 | help |
| 673 | As part of the Large System Extensions, ARMv8.1 introduces new |
| 674 | atomic instructions that are designed specifically to scale in |
| 675 | very large systems. |
| 676 | |
| 677 | Say Y here to make use of these instructions for the in-kernel |
| 678 | atomic routines. This incurs a small overhead on CPUs that do |
| 679 | not support these instructions and requires the kernel to be |
| 680 | built with binutils >= 2.25. |
| 681 | |
| 682 | endmenu |
| 683 | |
| 684 | endmenu |
| 685 | |
| 686 | menu "Boot options" |
| 687 | |
| 688 | config CMDLINE |
| 689 | string "Default kernel command string" |
| 690 | default "" |
| 691 | help |
| 692 | Provide a set of default command-line options at build time by |
| 693 | entering them here. As a minimum, you should specify the the |
| 694 | root device (e.g. root=/dev/nfs). |
| 695 | |
| 696 | config CMDLINE_FORCE |
| 697 | bool "Always use the default kernel command string" |
| 698 | help |
| 699 | Always use the default kernel command string, even if the boot |
| 700 | loader passes other arguments to the kernel. |
| 701 | This is useful if you cannot or don't want to change the |
| 702 | command-line options your boot loader passes to the kernel. |
| 703 | |
| 704 | config EFI_STUB |
| 705 | bool |
| 706 | |
| 707 | config EFI |
| 708 | bool "UEFI runtime support" |
| 709 | depends on OF && !CPU_BIG_ENDIAN |
| 710 | select LIBFDT |
| 711 | select UCS2_STRING |
| 712 | select EFI_PARAMS_FROM_FDT |
| 713 | select EFI_RUNTIME_WRAPPERS |
| 714 | select EFI_STUB |
| 715 | select EFI_ARMSTUB |
| 716 | default y |
| 717 | help |
| 718 | This option provides support for runtime services provided |
| 719 | by UEFI firmware (such as non-volatile variables, realtime |
| 720 | clock, and platform reset). A UEFI stub is also provided to |
| 721 | allow the kernel to be booted as an EFI application. This |
| 722 | is only useful on systems that have UEFI firmware. |
| 723 | |
| 724 | config DMI |
| 725 | bool "Enable support for SMBIOS (DMI) tables" |
| 726 | depends on EFI |
| 727 | default y |
| 728 | help |
| 729 | This enables SMBIOS/DMI feature for systems. |
| 730 | |
| 731 | This option is only useful on systems that have UEFI firmware. |
| 732 | However, even with this option, the resultant kernel should |
| 733 | continue to boot on existing non-UEFI platforms. |
| 734 | |
| 735 | endmenu |
| 736 | |
| 737 | menu "Userspace binary formats" |
| 738 | |
| 739 | source "fs/Kconfig.binfmt" |
| 740 | |
| 741 | config COMPAT |
| 742 | bool "Kernel support for 32-bit EL0" |
| 743 | depends on ARM64_4K_PAGES || EXPERT |
| 744 | select COMPAT_BINFMT_ELF |
| 745 | select HAVE_UID16 |
| 746 | select OLD_SIGSUSPEND3 |
| 747 | select COMPAT_OLD_SIGACTION |
| 748 | help |
| 749 | This option enables support for a 32-bit EL0 running under a 64-bit |
| 750 | kernel at EL1. AArch32-specific components such as system calls, |
| 751 | the user helper functions, VFP support and the ptrace interface are |
| 752 | handled appropriately by the kernel. |
| 753 | |
| 754 | If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware |
| 755 | that you will only be able to execute AArch32 binaries that were compiled |
| 756 | with page size aligned segments. |
| 757 | |
| 758 | If you want to execute 32-bit userspace applications, say Y. |
| 759 | |
| 760 | config SYSVIPC_COMPAT |
| 761 | def_bool y |
| 762 | depends on COMPAT && SYSVIPC |
| 763 | |
| 764 | endmenu |
| 765 | |
| 766 | menu "Power management options" |
| 767 | |
| 768 | source "kernel/power/Kconfig" |
| 769 | |
| 770 | config ARCH_SUSPEND_POSSIBLE |
| 771 | def_bool y |
| 772 | |
| 773 | endmenu |
| 774 | |
| 775 | menu "CPU Power Management" |
| 776 | |
| 777 | source "drivers/cpuidle/Kconfig" |
| 778 | |
| 779 | source "drivers/cpufreq/Kconfig" |
| 780 | |
| 781 | endmenu |
| 782 | |
| 783 | source "net/Kconfig" |
| 784 | |
| 785 | source "drivers/Kconfig" |
| 786 | |
| 787 | source "drivers/firmware/Kconfig" |
| 788 | |
| 789 | source "drivers/acpi/Kconfig" |
| 790 | |
| 791 | source "fs/Kconfig" |
| 792 | |
| 793 | source "arch/arm64/kvm/Kconfig" |
| 794 | |
| 795 | source "arch/arm64/Kconfig.debug" |
| 796 | |
| 797 | source "security/Kconfig" |
| 798 | |
| 799 | source "crypto/Kconfig" |
| 800 | if CRYPTO |
| 801 | source "arch/arm64/crypto/Kconfig" |
| 802 | endif |
| 803 | |
| 804 | source "lib/Kconfig" |