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powerpc: Split __SYSFS_SPRSETUP macro
[deliverable/linux.git] / arch / powerpc / kernel / sysfs.c
... / ...
CommitLineData
1#include <linux/device.h>
2#include <linux/cpu.h>
3#include <linux/smp.h>
4#include <linux/percpu.h>
5#include <linux/init.h>
6#include <linux/sched.h>
7#include <linux/export.h>
8#include <linux/nodemask.h>
9#include <linux/cpumask.h>
10#include <linux/notifier.h>
11
12#include <asm/current.h>
13#include <asm/processor.h>
14#include <asm/cputable.h>
15#include <asm/hvcall.h>
16#include <asm/prom.h>
17#include <asm/machdep.h>
18#include <asm/smp.h>
19#include <asm/pmc.h>
20#include <asm/firmware.h>
21
22#include "cacheinfo.h"
23
24#ifdef CONFIG_PPC64
25#include <asm/paca.h>
26#include <asm/lppaca.h>
27#endif
28
29static DEFINE_PER_CPU(struct cpu, cpu_devices);
30
31/*
32 * SMT snooze delay stuff, 64-bit only for now
33 */
34
35#ifdef CONFIG_PPC64
36
37/* Time in microseconds we delay before sleeping in the idle loop */
38DEFINE_PER_CPU(long, smt_snooze_delay) = { 100 };
39
40static ssize_t store_smt_snooze_delay(struct device *dev,
41 struct device_attribute *attr,
42 const char *buf,
43 size_t count)
44{
45 struct cpu *cpu = container_of(dev, struct cpu, dev);
46 ssize_t ret;
47 long snooze;
48
49 ret = sscanf(buf, "%ld", &snooze);
50 if (ret != 1)
51 return -EINVAL;
52
53 per_cpu(smt_snooze_delay, cpu->dev.id) = snooze;
54 return count;
55}
56
57static ssize_t show_smt_snooze_delay(struct device *dev,
58 struct device_attribute *attr,
59 char *buf)
60{
61 struct cpu *cpu = container_of(dev, struct cpu, dev);
62
63 return sprintf(buf, "%ld\n", per_cpu(smt_snooze_delay, cpu->dev.id));
64}
65
66static DEVICE_ATTR(smt_snooze_delay, 0644, show_smt_snooze_delay,
67 store_smt_snooze_delay);
68
69static int __init setup_smt_snooze_delay(char *str)
70{
71 unsigned int cpu;
72 long snooze;
73
74 if (!cpu_has_feature(CPU_FTR_SMT))
75 return 1;
76
77 snooze = simple_strtol(str, NULL, 10);
78 for_each_possible_cpu(cpu)
79 per_cpu(smt_snooze_delay, cpu) = snooze;
80
81 return 1;
82}
83__setup("smt-snooze-delay=", setup_smt_snooze_delay);
84
85#endif /* CONFIG_PPC64 */
86
87#ifdef CONFIG_PPC_FSL_BOOK3E
88#define MAX_BIT 63
89
90static u64 pw20_wt;
91static u64 altivec_idle_wt;
92
93static unsigned int get_idle_ticks_bit(u64 ns)
94{
95 u64 cycle;
96
97 if (ns >= 10000)
98 cycle = div_u64(ns + 500, 1000) * tb_ticks_per_usec;
99 else
100 cycle = div_u64(ns * tb_ticks_per_usec, 1000);
101
102 if (!cycle)
103 return 0;
104
105 return ilog2(cycle);
106}
107
108static void do_show_pwrmgtcr0(void *val)
109{
110 u32 *value = val;
111
112 *value = mfspr(SPRN_PWRMGTCR0);
113}
114
115static ssize_t show_pw20_state(struct device *dev,
116 struct device_attribute *attr, char *buf)
117{
118 u32 value;
119 unsigned int cpu = dev->id;
120
121 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
122
123 value &= PWRMGTCR0_PW20_WAIT;
124
125 return sprintf(buf, "%u\n", value ? 1 : 0);
126}
127
128static void do_store_pw20_state(void *val)
129{
130 u32 *value = val;
131 u32 pw20_state;
132
133 pw20_state = mfspr(SPRN_PWRMGTCR0);
134
135 if (*value)
136 pw20_state |= PWRMGTCR0_PW20_WAIT;
137 else
138 pw20_state &= ~PWRMGTCR0_PW20_WAIT;
139
140 mtspr(SPRN_PWRMGTCR0, pw20_state);
141}
142
143static ssize_t store_pw20_state(struct device *dev,
144 struct device_attribute *attr,
145 const char *buf, size_t count)
146{
147 u32 value;
148 unsigned int cpu = dev->id;
149
150 if (kstrtou32(buf, 0, &value))
151 return -EINVAL;
152
153 if (value > 1)
154 return -EINVAL;
155
156 smp_call_function_single(cpu, do_store_pw20_state, &value, 1);
157
158 return count;
159}
160
161static ssize_t show_pw20_wait_time(struct device *dev,
162 struct device_attribute *attr, char *buf)
163{
164 u32 value;
165 u64 tb_cycle = 1;
166 u64 time;
167
168 unsigned int cpu = dev->id;
169
170 if (!pw20_wt) {
171 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
172 value = (value & PWRMGTCR0_PW20_ENT) >>
173 PWRMGTCR0_PW20_ENT_SHIFT;
174
175 tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
176 /* convert ms to ns */
177 if (tb_ticks_per_usec > 1000) {
178 time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
179 } else {
180 u32 rem_us;
181
182 time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
183 &rem_us);
184 time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
185 }
186 } else {
187 time = pw20_wt;
188 }
189
190 return sprintf(buf, "%llu\n", time > 0 ? time : 0);
191}
192
193static void set_pw20_wait_entry_bit(void *val)
194{
195 u32 *value = val;
196 u32 pw20_idle;
197
198 pw20_idle = mfspr(SPRN_PWRMGTCR0);
199
200 /* Set Automatic PW20 Core Idle Count */
201 /* clear count */
202 pw20_idle &= ~PWRMGTCR0_PW20_ENT;
203
204 /* set count */
205 pw20_idle |= ((MAX_BIT - *value) << PWRMGTCR0_PW20_ENT_SHIFT);
206
207 mtspr(SPRN_PWRMGTCR0, pw20_idle);
208}
209
210static ssize_t store_pw20_wait_time(struct device *dev,
211 struct device_attribute *attr,
212 const char *buf, size_t count)
213{
214 u32 entry_bit;
215 u64 value;
216
217 unsigned int cpu = dev->id;
218
219 if (kstrtou64(buf, 0, &value))
220 return -EINVAL;
221
222 if (!value)
223 return -EINVAL;
224
225 entry_bit = get_idle_ticks_bit(value);
226 if (entry_bit > MAX_BIT)
227 return -EINVAL;
228
229 pw20_wt = value;
230
231 smp_call_function_single(cpu, set_pw20_wait_entry_bit,
232 &entry_bit, 1);
233
234 return count;
235}
236
237static ssize_t show_altivec_idle(struct device *dev,
238 struct device_attribute *attr, char *buf)
239{
240 u32 value;
241 unsigned int cpu = dev->id;
242
243 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
244
245 value &= PWRMGTCR0_AV_IDLE_PD_EN;
246
247 return sprintf(buf, "%u\n", value ? 1 : 0);
248}
249
250static void do_store_altivec_idle(void *val)
251{
252 u32 *value = val;
253 u32 altivec_idle;
254
255 altivec_idle = mfspr(SPRN_PWRMGTCR0);
256
257 if (*value)
258 altivec_idle |= PWRMGTCR0_AV_IDLE_PD_EN;
259 else
260 altivec_idle &= ~PWRMGTCR0_AV_IDLE_PD_EN;
261
262 mtspr(SPRN_PWRMGTCR0, altivec_idle);
263}
264
265static ssize_t store_altivec_idle(struct device *dev,
266 struct device_attribute *attr,
267 const char *buf, size_t count)
268{
269 u32 value;
270 unsigned int cpu = dev->id;
271
272 if (kstrtou32(buf, 0, &value))
273 return -EINVAL;
274
275 if (value > 1)
276 return -EINVAL;
277
278 smp_call_function_single(cpu, do_store_altivec_idle, &value, 1);
279
280 return count;
281}
282
283static ssize_t show_altivec_idle_wait_time(struct device *dev,
284 struct device_attribute *attr, char *buf)
285{
286 u32 value;
287 u64 tb_cycle = 1;
288 u64 time;
289
290 unsigned int cpu = dev->id;
291
292 if (!altivec_idle_wt) {
293 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
294 value = (value & PWRMGTCR0_AV_IDLE_CNT) >>
295 PWRMGTCR0_AV_IDLE_CNT_SHIFT;
296
297 tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
298 /* convert ms to ns */
299 if (tb_ticks_per_usec > 1000) {
300 time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
301 } else {
302 u32 rem_us;
303
304 time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
305 &rem_us);
306 time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
307 }
308 } else {
309 time = altivec_idle_wt;
310 }
311
312 return sprintf(buf, "%llu\n", time > 0 ? time : 0);
313}
314
315static void set_altivec_idle_wait_entry_bit(void *val)
316{
317 u32 *value = val;
318 u32 altivec_idle;
319
320 altivec_idle = mfspr(SPRN_PWRMGTCR0);
321
322 /* Set Automatic AltiVec Idle Count */
323 /* clear count */
324 altivec_idle &= ~PWRMGTCR0_AV_IDLE_CNT;
325
326 /* set count */
327 altivec_idle |= ((MAX_BIT - *value) << PWRMGTCR0_AV_IDLE_CNT_SHIFT);
328
329 mtspr(SPRN_PWRMGTCR0, altivec_idle);
330}
331
332static ssize_t store_altivec_idle_wait_time(struct device *dev,
333 struct device_attribute *attr,
334 const char *buf, size_t count)
335{
336 u32 entry_bit;
337 u64 value;
338
339 unsigned int cpu = dev->id;
340
341 if (kstrtou64(buf, 0, &value))
342 return -EINVAL;
343
344 if (!value)
345 return -EINVAL;
346
347 entry_bit = get_idle_ticks_bit(value);
348 if (entry_bit > MAX_BIT)
349 return -EINVAL;
350
351 altivec_idle_wt = value;
352
353 smp_call_function_single(cpu, set_altivec_idle_wait_entry_bit,
354 &entry_bit, 1);
355
356 return count;
357}
358
359/*
360 * Enable/Disable interface:
361 * 0, disable. 1, enable.
362 */
363static DEVICE_ATTR(pw20_state, 0600, show_pw20_state, store_pw20_state);
364static DEVICE_ATTR(altivec_idle, 0600, show_altivec_idle, store_altivec_idle);
365
366/*
367 * Set wait time interface:(Nanosecond)
368 * Example: Base on TBfreq is 41MHZ.
369 * 1~48(ns): TB[63]
370 * 49~97(ns): TB[62]
371 * 98~195(ns): TB[61]
372 * 196~390(ns): TB[60]
373 * 391~780(ns): TB[59]
374 * 781~1560(ns): TB[58]
375 * ...
376 */
377static DEVICE_ATTR(pw20_wait_time, 0600,
378 show_pw20_wait_time,
379 store_pw20_wait_time);
380static DEVICE_ATTR(altivec_idle_wait_time, 0600,
381 show_altivec_idle_wait_time,
382 store_altivec_idle_wait_time);
383#endif
384
385/*
386 * Enabling PMCs will slow partition context switch times so we only do
387 * it the first time we write to the PMCs.
388 */
389
390static DEFINE_PER_CPU(char, pmcs_enabled);
391
392void ppc_enable_pmcs(void)
393{
394 ppc_set_pmu_inuse(1);
395
396 /* Only need to enable them once */
397 if (__get_cpu_var(pmcs_enabled))
398 return;
399
400 __get_cpu_var(pmcs_enabled) = 1;
401
402 if (ppc_md.enable_pmcs)
403 ppc_md.enable_pmcs();
404}
405EXPORT_SYMBOL(ppc_enable_pmcs);
406
407#define __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, EXTRA) \
408static void read_##NAME(void *val) \
409{ \
410 *(unsigned long *)val = mfspr(ADDRESS); \
411} \
412static void write_##NAME(void *val) \
413{ \
414 EXTRA; \
415 mtspr(ADDRESS, *(unsigned long *)val); \
416}
417
418#define __SYSFS_SPRSETUP_SHOW_STORE(NAME) \
419static ssize_t show_##NAME(struct device *dev, \
420 struct device_attribute *attr, \
421 char *buf) \
422{ \
423 struct cpu *cpu = container_of(dev, struct cpu, dev); \
424 unsigned long val; \
425 smp_call_function_single(cpu->dev.id, read_##NAME, &val, 1); \
426 return sprintf(buf, "%lx\n", val); \
427} \
428static ssize_t __used \
429 store_##NAME(struct device *dev, struct device_attribute *attr, \
430 const char *buf, size_t count) \
431{ \
432 struct cpu *cpu = container_of(dev, struct cpu, dev); \
433 unsigned long val; \
434 int ret = sscanf(buf, "%lx", &val); \
435 if (ret != 1) \
436 return -EINVAL; \
437 smp_call_function_single(cpu->dev.id, write_##NAME, &val, 1); \
438 return count; \
439}
440
441#define SYSFS_PMCSETUP(NAME, ADDRESS) \
442 __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ppc_enable_pmcs()) \
443 __SYSFS_SPRSETUP_SHOW_STORE(NAME)
444#define SYSFS_SPRSETUP(NAME, ADDRESS) \
445 __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ) \
446 __SYSFS_SPRSETUP_SHOW_STORE(NAME)
447
448#define SYSFS_SPRSETUP_SHOW_STORE(NAME) \
449 __SYSFS_SPRSETUP_SHOW_STORE(NAME)
450
451/* Let's define all possible registers, we'll only hook up the ones
452 * that are implemented on the current processor
453 */
454
455#if defined(CONFIG_PPC64)
456#define HAS_PPC_PMC_CLASSIC 1
457#define HAS_PPC_PMC_IBM 1
458#define HAS_PPC_PMC_PA6T 1
459#elif defined(CONFIG_6xx)
460#define HAS_PPC_PMC_CLASSIC 1
461#define HAS_PPC_PMC_IBM 1
462#define HAS_PPC_PMC_G4 1
463#endif
464
465
466#ifdef HAS_PPC_PMC_CLASSIC
467SYSFS_PMCSETUP(mmcr0, SPRN_MMCR0);
468SYSFS_PMCSETUP(mmcr1, SPRN_MMCR1);
469SYSFS_PMCSETUP(pmc1, SPRN_PMC1);
470SYSFS_PMCSETUP(pmc2, SPRN_PMC2);
471SYSFS_PMCSETUP(pmc3, SPRN_PMC3);
472SYSFS_PMCSETUP(pmc4, SPRN_PMC4);
473SYSFS_PMCSETUP(pmc5, SPRN_PMC5);
474SYSFS_PMCSETUP(pmc6, SPRN_PMC6);
475
476#ifdef HAS_PPC_PMC_G4
477SYSFS_PMCSETUP(mmcr2, SPRN_MMCR2);
478#endif
479
480#ifdef CONFIG_PPC64
481SYSFS_PMCSETUP(pmc7, SPRN_PMC7);
482SYSFS_PMCSETUP(pmc8, SPRN_PMC8);
483
484SYSFS_PMCSETUP(mmcra, SPRN_MMCRA);
485SYSFS_SPRSETUP(purr, SPRN_PURR);
486SYSFS_SPRSETUP(spurr, SPRN_SPURR);
487SYSFS_SPRSETUP(dscr, SPRN_DSCR);
488SYSFS_SPRSETUP(pir, SPRN_PIR);
489
490/*
491 Lets only enable read for phyp resources and
492 enable write when needed with a separate function.
493 Lets be conservative and default to pseries.
494*/
495static DEVICE_ATTR(mmcra, 0600, show_mmcra, store_mmcra);
496static DEVICE_ATTR(spurr, 0400, show_spurr, NULL);
497static DEVICE_ATTR(dscr, 0600, show_dscr, store_dscr);
498static DEVICE_ATTR(purr, 0400, show_purr, store_purr);
499static DEVICE_ATTR(pir, 0400, show_pir, NULL);
500
501unsigned long dscr_default = 0;
502EXPORT_SYMBOL(dscr_default);
503
504static void add_write_permission_dev_attr(struct device_attribute *attr)
505{
506 attr->attr.mode |= 0200;
507}
508
509static ssize_t show_dscr_default(struct device *dev,
510 struct device_attribute *attr, char *buf)
511{
512 return sprintf(buf, "%lx\n", dscr_default);
513}
514
515static void update_dscr(void *dummy)
516{
517 if (!current->thread.dscr_inherit) {
518 current->thread.dscr = dscr_default;
519 mtspr(SPRN_DSCR, dscr_default);
520 }
521}
522
523static ssize_t __used store_dscr_default(struct device *dev,
524 struct device_attribute *attr, const char *buf,
525 size_t count)
526{
527 unsigned long val;
528 int ret = 0;
529
530 ret = sscanf(buf, "%lx", &val);
531 if (ret != 1)
532 return -EINVAL;
533 dscr_default = val;
534
535 on_each_cpu(update_dscr, NULL, 1);
536
537 return count;
538}
539
540static DEVICE_ATTR(dscr_default, 0600,
541 show_dscr_default, store_dscr_default);
542
543static void sysfs_create_dscr_default(void)
544{
545 int err = 0;
546 if (cpu_has_feature(CPU_FTR_DSCR))
547 err = device_create_file(cpu_subsys.dev_root, &dev_attr_dscr_default);
548}
549#endif /* CONFIG_PPC64 */
550
551#ifdef HAS_PPC_PMC_PA6T
552SYSFS_PMCSETUP(pa6t_pmc0, SPRN_PA6T_PMC0);
553SYSFS_PMCSETUP(pa6t_pmc1, SPRN_PA6T_PMC1);
554SYSFS_PMCSETUP(pa6t_pmc2, SPRN_PA6T_PMC2);
555SYSFS_PMCSETUP(pa6t_pmc3, SPRN_PA6T_PMC3);
556SYSFS_PMCSETUP(pa6t_pmc4, SPRN_PA6T_PMC4);
557SYSFS_PMCSETUP(pa6t_pmc5, SPRN_PA6T_PMC5);
558#ifdef CONFIG_DEBUG_KERNEL
559SYSFS_SPRSETUP(hid0, SPRN_HID0);
560SYSFS_SPRSETUP(hid1, SPRN_HID1);
561SYSFS_SPRSETUP(hid4, SPRN_HID4);
562SYSFS_SPRSETUP(hid5, SPRN_HID5);
563SYSFS_SPRSETUP(ima0, SPRN_PA6T_IMA0);
564SYSFS_SPRSETUP(ima1, SPRN_PA6T_IMA1);
565SYSFS_SPRSETUP(ima2, SPRN_PA6T_IMA2);
566SYSFS_SPRSETUP(ima3, SPRN_PA6T_IMA3);
567SYSFS_SPRSETUP(ima4, SPRN_PA6T_IMA4);
568SYSFS_SPRSETUP(ima5, SPRN_PA6T_IMA5);
569SYSFS_SPRSETUP(ima6, SPRN_PA6T_IMA6);
570SYSFS_SPRSETUP(ima7, SPRN_PA6T_IMA7);
571SYSFS_SPRSETUP(ima8, SPRN_PA6T_IMA8);
572SYSFS_SPRSETUP(ima9, SPRN_PA6T_IMA9);
573SYSFS_SPRSETUP(imaat, SPRN_PA6T_IMAAT);
574SYSFS_SPRSETUP(btcr, SPRN_PA6T_BTCR);
575SYSFS_SPRSETUP(pccr, SPRN_PA6T_PCCR);
576SYSFS_SPRSETUP(rpccr, SPRN_PA6T_RPCCR);
577SYSFS_SPRSETUP(der, SPRN_PA6T_DER);
578SYSFS_SPRSETUP(mer, SPRN_PA6T_MER);
579SYSFS_SPRSETUP(ber, SPRN_PA6T_BER);
580SYSFS_SPRSETUP(ier, SPRN_PA6T_IER);
581SYSFS_SPRSETUP(sier, SPRN_PA6T_SIER);
582SYSFS_SPRSETUP(siar, SPRN_PA6T_SIAR);
583SYSFS_SPRSETUP(tsr0, SPRN_PA6T_TSR0);
584SYSFS_SPRSETUP(tsr1, SPRN_PA6T_TSR1);
585SYSFS_SPRSETUP(tsr2, SPRN_PA6T_TSR2);
586SYSFS_SPRSETUP(tsr3, SPRN_PA6T_TSR3);
587#endif /* CONFIG_DEBUG_KERNEL */
588#endif /* HAS_PPC_PMC_PA6T */
589
590#ifdef HAS_PPC_PMC_IBM
591static struct device_attribute ibm_common_attrs[] = {
592 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
593 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
594};
595#endif /* HAS_PPC_PMC_G4 */
596
597#ifdef HAS_PPC_PMC_G4
598static struct device_attribute g4_common_attrs[] = {
599 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
600 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
601 __ATTR(mmcr2, 0600, show_mmcr2, store_mmcr2),
602};
603#endif /* HAS_PPC_PMC_G4 */
604
605static struct device_attribute classic_pmc_attrs[] = {
606 __ATTR(pmc1, 0600, show_pmc1, store_pmc1),
607 __ATTR(pmc2, 0600, show_pmc2, store_pmc2),
608 __ATTR(pmc3, 0600, show_pmc3, store_pmc3),
609 __ATTR(pmc4, 0600, show_pmc4, store_pmc4),
610 __ATTR(pmc5, 0600, show_pmc5, store_pmc5),
611 __ATTR(pmc6, 0600, show_pmc6, store_pmc6),
612#ifdef CONFIG_PPC64
613 __ATTR(pmc7, 0600, show_pmc7, store_pmc7),
614 __ATTR(pmc8, 0600, show_pmc8, store_pmc8),
615#endif
616};
617
618#ifdef HAS_PPC_PMC_PA6T
619static struct device_attribute pa6t_attrs[] = {
620 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
621 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
622 __ATTR(pmc0, 0600, show_pa6t_pmc0, store_pa6t_pmc0),
623 __ATTR(pmc1, 0600, show_pa6t_pmc1, store_pa6t_pmc1),
624 __ATTR(pmc2, 0600, show_pa6t_pmc2, store_pa6t_pmc2),
625 __ATTR(pmc3, 0600, show_pa6t_pmc3, store_pa6t_pmc3),
626 __ATTR(pmc4, 0600, show_pa6t_pmc4, store_pa6t_pmc4),
627 __ATTR(pmc5, 0600, show_pa6t_pmc5, store_pa6t_pmc5),
628#ifdef CONFIG_DEBUG_KERNEL
629 __ATTR(hid0, 0600, show_hid0, store_hid0),
630 __ATTR(hid1, 0600, show_hid1, store_hid1),
631 __ATTR(hid4, 0600, show_hid4, store_hid4),
632 __ATTR(hid5, 0600, show_hid5, store_hid5),
633 __ATTR(ima0, 0600, show_ima0, store_ima0),
634 __ATTR(ima1, 0600, show_ima1, store_ima1),
635 __ATTR(ima2, 0600, show_ima2, store_ima2),
636 __ATTR(ima3, 0600, show_ima3, store_ima3),
637 __ATTR(ima4, 0600, show_ima4, store_ima4),
638 __ATTR(ima5, 0600, show_ima5, store_ima5),
639 __ATTR(ima6, 0600, show_ima6, store_ima6),
640 __ATTR(ima7, 0600, show_ima7, store_ima7),
641 __ATTR(ima8, 0600, show_ima8, store_ima8),
642 __ATTR(ima9, 0600, show_ima9, store_ima9),
643 __ATTR(imaat, 0600, show_imaat, store_imaat),
644 __ATTR(btcr, 0600, show_btcr, store_btcr),
645 __ATTR(pccr, 0600, show_pccr, store_pccr),
646 __ATTR(rpccr, 0600, show_rpccr, store_rpccr),
647 __ATTR(der, 0600, show_der, store_der),
648 __ATTR(mer, 0600, show_mer, store_mer),
649 __ATTR(ber, 0600, show_ber, store_ber),
650 __ATTR(ier, 0600, show_ier, store_ier),
651 __ATTR(sier, 0600, show_sier, store_sier),
652 __ATTR(siar, 0600, show_siar, store_siar),
653 __ATTR(tsr0, 0600, show_tsr0, store_tsr0),
654 __ATTR(tsr1, 0600, show_tsr1, store_tsr1),
655 __ATTR(tsr2, 0600, show_tsr2, store_tsr2),
656 __ATTR(tsr3, 0600, show_tsr3, store_tsr3),
657#endif /* CONFIG_DEBUG_KERNEL */
658};
659#endif /* HAS_PPC_PMC_PA6T */
660#endif /* HAS_PPC_PMC_CLASSIC */
661
662static void register_cpu_online(unsigned int cpu)
663{
664 struct cpu *c = &per_cpu(cpu_devices, cpu);
665 struct device *s = &c->dev;
666 struct device_attribute *attrs, *pmc_attrs;
667 int i, nattrs;
668
669#ifdef CONFIG_PPC64
670 if (cpu_has_feature(CPU_FTR_SMT))
671 device_create_file(s, &dev_attr_smt_snooze_delay);
672#endif
673
674 /* PMC stuff */
675 switch (cur_cpu_spec->pmc_type) {
676#ifdef HAS_PPC_PMC_IBM
677 case PPC_PMC_IBM:
678 attrs = ibm_common_attrs;
679 nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute);
680 pmc_attrs = classic_pmc_attrs;
681 break;
682#endif /* HAS_PPC_PMC_IBM */
683#ifdef HAS_PPC_PMC_G4
684 case PPC_PMC_G4:
685 attrs = g4_common_attrs;
686 nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute);
687 pmc_attrs = classic_pmc_attrs;
688 break;
689#endif /* HAS_PPC_PMC_G4 */
690#ifdef HAS_PPC_PMC_PA6T
691 case PPC_PMC_PA6T:
692 /* PA Semi starts counting at PMC0 */
693 attrs = pa6t_attrs;
694 nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute);
695 pmc_attrs = NULL;
696 break;
697#endif /* HAS_PPC_PMC_PA6T */
698 default:
699 attrs = NULL;
700 nattrs = 0;
701 pmc_attrs = NULL;
702 }
703
704 for (i = 0; i < nattrs; i++)
705 device_create_file(s, &attrs[i]);
706
707 if (pmc_attrs)
708 for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
709 device_create_file(s, &pmc_attrs[i]);
710
711#ifdef CONFIG_PPC64
712 if (cpu_has_feature(CPU_FTR_MMCRA))
713 device_create_file(s, &dev_attr_mmcra);
714
715 if (cpu_has_feature(CPU_FTR_PURR)) {
716 if (!firmware_has_feature(FW_FEATURE_LPAR))
717 add_write_permission_dev_attr(&dev_attr_purr);
718 device_create_file(s, &dev_attr_purr);
719 }
720
721 if (cpu_has_feature(CPU_FTR_SPURR))
722 device_create_file(s, &dev_attr_spurr);
723
724 if (cpu_has_feature(CPU_FTR_DSCR))
725 device_create_file(s, &dev_attr_dscr);
726
727 if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
728 device_create_file(s, &dev_attr_pir);
729#endif /* CONFIG_PPC64 */
730
731#ifdef CONFIG_PPC_FSL_BOOK3E
732 if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
733 device_create_file(s, &dev_attr_pw20_state);
734 device_create_file(s, &dev_attr_pw20_wait_time);
735
736 device_create_file(s, &dev_attr_altivec_idle);
737 device_create_file(s, &dev_attr_altivec_idle_wait_time);
738 }
739#endif
740 cacheinfo_cpu_online(cpu);
741}
742
743#ifdef CONFIG_HOTPLUG_CPU
744static void unregister_cpu_online(unsigned int cpu)
745{
746 struct cpu *c = &per_cpu(cpu_devices, cpu);
747 struct device *s = &c->dev;
748 struct device_attribute *attrs, *pmc_attrs;
749 int i, nattrs;
750
751 BUG_ON(!c->hotpluggable);
752
753#ifdef CONFIG_PPC64
754 if (cpu_has_feature(CPU_FTR_SMT))
755 device_remove_file(s, &dev_attr_smt_snooze_delay);
756#endif
757
758 /* PMC stuff */
759 switch (cur_cpu_spec->pmc_type) {
760#ifdef HAS_PPC_PMC_IBM
761 case PPC_PMC_IBM:
762 attrs = ibm_common_attrs;
763 nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute);
764 pmc_attrs = classic_pmc_attrs;
765 break;
766#endif /* HAS_PPC_PMC_IBM */
767#ifdef HAS_PPC_PMC_G4
768 case PPC_PMC_G4:
769 attrs = g4_common_attrs;
770 nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute);
771 pmc_attrs = classic_pmc_attrs;
772 break;
773#endif /* HAS_PPC_PMC_G4 */
774#ifdef HAS_PPC_PMC_PA6T
775 case PPC_PMC_PA6T:
776 /* PA Semi starts counting at PMC0 */
777 attrs = pa6t_attrs;
778 nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute);
779 pmc_attrs = NULL;
780 break;
781#endif /* HAS_PPC_PMC_PA6T */
782 default:
783 attrs = NULL;
784 nattrs = 0;
785 pmc_attrs = NULL;
786 }
787
788 for (i = 0; i < nattrs; i++)
789 device_remove_file(s, &attrs[i]);
790
791 if (pmc_attrs)
792 for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
793 device_remove_file(s, &pmc_attrs[i]);
794
795#ifdef CONFIG_PPC64
796 if (cpu_has_feature(CPU_FTR_MMCRA))
797 device_remove_file(s, &dev_attr_mmcra);
798
799 if (cpu_has_feature(CPU_FTR_PURR))
800 device_remove_file(s, &dev_attr_purr);
801
802 if (cpu_has_feature(CPU_FTR_SPURR))
803 device_remove_file(s, &dev_attr_spurr);
804
805 if (cpu_has_feature(CPU_FTR_DSCR))
806 device_remove_file(s, &dev_attr_dscr);
807
808 if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
809 device_remove_file(s, &dev_attr_pir);
810#endif /* CONFIG_PPC64 */
811
812#ifdef CONFIG_PPC_FSL_BOOK3E
813 if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
814 device_remove_file(s, &dev_attr_pw20_state);
815 device_remove_file(s, &dev_attr_pw20_wait_time);
816
817 device_remove_file(s, &dev_attr_altivec_idle);
818 device_remove_file(s, &dev_attr_altivec_idle_wait_time);
819 }
820#endif
821 cacheinfo_cpu_offline(cpu);
822}
823
824#ifdef CONFIG_ARCH_CPU_PROBE_RELEASE
825ssize_t arch_cpu_probe(const char *buf, size_t count)
826{
827 if (ppc_md.cpu_probe)
828 return ppc_md.cpu_probe(buf, count);
829
830 return -EINVAL;
831}
832
833ssize_t arch_cpu_release(const char *buf, size_t count)
834{
835 if (ppc_md.cpu_release)
836 return ppc_md.cpu_release(buf, count);
837
838 return -EINVAL;
839}
840#endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */
841
842#endif /* CONFIG_HOTPLUG_CPU */
843
844static int sysfs_cpu_notify(struct notifier_block *self,
845 unsigned long action, void *hcpu)
846{
847 unsigned int cpu = (unsigned int)(long)hcpu;
848
849 switch (action) {
850 case CPU_ONLINE:
851 case CPU_ONLINE_FROZEN:
852 register_cpu_online(cpu);
853 break;
854#ifdef CONFIG_HOTPLUG_CPU
855 case CPU_DEAD:
856 case CPU_DEAD_FROZEN:
857 unregister_cpu_online(cpu);
858 break;
859#endif
860 }
861 return NOTIFY_OK;
862}
863
864static struct notifier_block sysfs_cpu_nb = {
865 .notifier_call = sysfs_cpu_notify,
866};
867
868static DEFINE_MUTEX(cpu_mutex);
869
870int cpu_add_dev_attr(struct device_attribute *attr)
871{
872 int cpu;
873
874 mutex_lock(&cpu_mutex);
875
876 for_each_possible_cpu(cpu) {
877 device_create_file(get_cpu_device(cpu), attr);
878 }
879
880 mutex_unlock(&cpu_mutex);
881 return 0;
882}
883EXPORT_SYMBOL_GPL(cpu_add_dev_attr);
884
885int cpu_add_dev_attr_group(struct attribute_group *attrs)
886{
887 int cpu;
888 struct device *dev;
889 int ret;
890
891 mutex_lock(&cpu_mutex);
892
893 for_each_possible_cpu(cpu) {
894 dev = get_cpu_device(cpu);
895 ret = sysfs_create_group(&dev->kobj, attrs);
896 WARN_ON(ret != 0);
897 }
898
899 mutex_unlock(&cpu_mutex);
900 return 0;
901}
902EXPORT_SYMBOL_GPL(cpu_add_dev_attr_group);
903
904
905void cpu_remove_dev_attr(struct device_attribute *attr)
906{
907 int cpu;
908
909 mutex_lock(&cpu_mutex);
910
911 for_each_possible_cpu(cpu) {
912 device_remove_file(get_cpu_device(cpu), attr);
913 }
914
915 mutex_unlock(&cpu_mutex);
916}
917EXPORT_SYMBOL_GPL(cpu_remove_dev_attr);
918
919void cpu_remove_dev_attr_group(struct attribute_group *attrs)
920{
921 int cpu;
922 struct device *dev;
923
924 mutex_lock(&cpu_mutex);
925
926 for_each_possible_cpu(cpu) {
927 dev = get_cpu_device(cpu);
928 sysfs_remove_group(&dev->kobj, attrs);
929 }
930
931 mutex_unlock(&cpu_mutex);
932}
933EXPORT_SYMBOL_GPL(cpu_remove_dev_attr_group);
934
935
936/* NUMA stuff */
937
938#ifdef CONFIG_NUMA
939static void register_nodes(void)
940{
941 int i;
942
943 for (i = 0; i < MAX_NUMNODES; i++)
944 register_one_node(i);
945}
946
947int sysfs_add_device_to_node(struct device *dev, int nid)
948{
949 struct node *node = node_devices[nid];
950 return sysfs_create_link(&node->dev.kobj, &dev->kobj,
951 kobject_name(&dev->kobj));
952}
953EXPORT_SYMBOL_GPL(sysfs_add_device_to_node);
954
955void sysfs_remove_device_from_node(struct device *dev, int nid)
956{
957 struct node *node = node_devices[nid];
958 sysfs_remove_link(&node->dev.kobj, kobject_name(&dev->kobj));
959}
960EXPORT_SYMBOL_GPL(sysfs_remove_device_from_node);
961
962#else
963static void register_nodes(void)
964{
965 return;
966}
967
968#endif
969
970/* Only valid if CPU is present. */
971static ssize_t show_physical_id(struct device *dev,
972 struct device_attribute *attr, char *buf)
973{
974 struct cpu *cpu = container_of(dev, struct cpu, dev);
975
976 return sprintf(buf, "%d\n", get_hard_smp_processor_id(cpu->dev.id));
977}
978static DEVICE_ATTR(physical_id, 0444, show_physical_id, NULL);
979
980static int __init topology_init(void)
981{
982 int cpu;
983
984 register_nodes();
985
986 cpu_notifier_register_begin();
987
988 for_each_possible_cpu(cpu) {
989 struct cpu *c = &per_cpu(cpu_devices, cpu);
990
991 /*
992 * For now, we just see if the system supports making
993 * the RTAS calls for CPU hotplug. But, there may be a
994 * more comprehensive way to do this for an individual
995 * CPU. For instance, the boot cpu might never be valid
996 * for hotplugging.
997 */
998 if (ppc_md.cpu_die)
999 c->hotpluggable = 1;
1000
1001 if (cpu_online(cpu) || c->hotpluggable) {
1002 register_cpu(c, cpu);
1003
1004 device_create_file(&c->dev, &dev_attr_physical_id);
1005 }
1006
1007 if (cpu_online(cpu))
1008 register_cpu_online(cpu);
1009 }
1010
1011 __register_cpu_notifier(&sysfs_cpu_nb);
1012
1013 cpu_notifier_register_done();
1014
1015#ifdef CONFIG_PPC64
1016 sysfs_create_dscr_default();
1017#endif /* CONFIG_PPC64 */
1018
1019 return 0;
1020}
1021subsys_initcall(topology_init);
Linux kernel - Deliverables
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