| 1 | /* $Id: entry.S,v 1.144 2002/02/09 19:49:30 davem Exp $ |
| 2 | * arch/sparc64/kernel/entry.S: Sparc64 trap low-level entry points. |
| 3 | * |
| 4 | * Copyright (C) 1995,1997 David S. Miller (davem@caip.rutgers.edu) |
| 5 | * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be) |
| 6 | * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx) |
| 7 | * Copyright (C) 1996,98,99 Jakub Jelinek (jj@sunsite.mff.cuni.cz) |
| 8 | */ |
| 9 | |
| 10 | #include <linux/errno.h> |
| 11 | |
| 12 | #include <asm/head.h> |
| 13 | #include <asm/asi.h> |
| 14 | #include <asm/smp.h> |
| 15 | #include <asm/ptrace.h> |
| 16 | #include <asm/page.h> |
| 17 | #include <asm/signal.h> |
| 18 | #include <asm/pgtable.h> |
| 19 | #include <asm/processor.h> |
| 20 | #include <asm/visasm.h> |
| 21 | #include <asm/estate.h> |
| 22 | #include <asm/auxio.h> |
| 23 | #include <asm/sfafsr.h> |
| 24 | #include <asm/pil.h> |
| 25 | #include <asm/unistd.h> |
| 26 | |
| 27 | #define curptr g6 |
| 28 | |
| 29 | .text |
| 30 | .align 32 |
| 31 | |
| 32 | /* This is trivial with the new code... */ |
| 33 | .globl do_fpdis |
| 34 | do_fpdis: |
| 35 | sethi %hi(TSTATE_PEF), %g4 |
| 36 | rdpr %tstate, %g5 |
| 37 | andcc %g5, %g4, %g0 |
| 38 | be,pt %xcc, 1f |
| 39 | nop |
| 40 | rd %fprs, %g5 |
| 41 | andcc %g5, FPRS_FEF, %g0 |
| 42 | be,pt %xcc, 1f |
| 43 | nop |
| 44 | |
| 45 | /* Legal state when DCR_IFPOE is set in Cheetah %dcr. */ |
| 46 | sethi %hi(109f), %g7 |
| 47 | ba,pt %xcc, etrap |
| 48 | 109: or %g7, %lo(109b), %g7 |
| 49 | add %g0, %g0, %g0 |
| 50 | ba,a,pt %xcc, rtrap_clr_l6 |
| 51 | |
| 52 | 1: TRAP_LOAD_THREAD_REG(%g6, %g1) |
| 53 | ldub [%g6 + TI_FPSAVED], %g5 |
| 54 | wr %g0, FPRS_FEF, %fprs |
| 55 | andcc %g5, FPRS_FEF, %g0 |
| 56 | be,a,pt %icc, 1f |
| 57 | clr %g7 |
| 58 | ldx [%g6 + TI_GSR], %g7 |
| 59 | 1: andcc %g5, FPRS_DL, %g0 |
| 60 | bne,pn %icc, 2f |
| 61 | fzero %f0 |
| 62 | andcc %g5, FPRS_DU, %g0 |
| 63 | bne,pn %icc, 1f |
| 64 | fzero %f2 |
| 65 | faddd %f0, %f2, %f4 |
| 66 | fmuld %f0, %f2, %f6 |
| 67 | faddd %f0, %f2, %f8 |
| 68 | fmuld %f0, %f2, %f10 |
| 69 | faddd %f0, %f2, %f12 |
| 70 | fmuld %f0, %f2, %f14 |
| 71 | faddd %f0, %f2, %f16 |
| 72 | fmuld %f0, %f2, %f18 |
| 73 | faddd %f0, %f2, %f20 |
| 74 | fmuld %f0, %f2, %f22 |
| 75 | faddd %f0, %f2, %f24 |
| 76 | fmuld %f0, %f2, %f26 |
| 77 | faddd %f0, %f2, %f28 |
| 78 | fmuld %f0, %f2, %f30 |
| 79 | faddd %f0, %f2, %f32 |
| 80 | fmuld %f0, %f2, %f34 |
| 81 | faddd %f0, %f2, %f36 |
| 82 | fmuld %f0, %f2, %f38 |
| 83 | faddd %f0, %f2, %f40 |
| 84 | fmuld %f0, %f2, %f42 |
| 85 | faddd %f0, %f2, %f44 |
| 86 | fmuld %f0, %f2, %f46 |
| 87 | faddd %f0, %f2, %f48 |
| 88 | fmuld %f0, %f2, %f50 |
| 89 | faddd %f0, %f2, %f52 |
| 90 | fmuld %f0, %f2, %f54 |
| 91 | faddd %f0, %f2, %f56 |
| 92 | fmuld %f0, %f2, %f58 |
| 93 | b,pt %xcc, fpdis_exit2 |
| 94 | faddd %f0, %f2, %f60 |
| 95 | 1: mov SECONDARY_CONTEXT, %g3 |
| 96 | add %g6, TI_FPREGS + 0x80, %g1 |
| 97 | faddd %f0, %f2, %f4 |
| 98 | fmuld %f0, %f2, %f6 |
| 99 | |
| 100 | 661: ldxa [%g3] ASI_DMMU, %g5 |
| 101 | .section .sun4v_1insn_patch, "ax" |
| 102 | .word 661b |
| 103 | ldxa [%g3] ASI_MMU, %g5 |
| 104 | .previous |
| 105 | |
| 106 | sethi %hi(sparc64_kern_sec_context), %g2 |
| 107 | ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2 |
| 108 | |
| 109 | 661: stxa %g2, [%g3] ASI_DMMU |
| 110 | .section .sun4v_1insn_patch, "ax" |
| 111 | .word 661b |
| 112 | stxa %g2, [%g3] ASI_MMU |
| 113 | .previous |
| 114 | |
| 115 | membar #Sync |
| 116 | add %g6, TI_FPREGS + 0xc0, %g2 |
| 117 | faddd %f0, %f2, %f8 |
| 118 | fmuld %f0, %f2, %f10 |
| 119 | membar #Sync |
| 120 | ldda [%g1] ASI_BLK_S, %f32 |
| 121 | ldda [%g2] ASI_BLK_S, %f48 |
| 122 | membar #Sync |
| 123 | faddd %f0, %f2, %f12 |
| 124 | fmuld %f0, %f2, %f14 |
| 125 | faddd %f0, %f2, %f16 |
| 126 | fmuld %f0, %f2, %f18 |
| 127 | faddd %f0, %f2, %f20 |
| 128 | fmuld %f0, %f2, %f22 |
| 129 | faddd %f0, %f2, %f24 |
| 130 | fmuld %f0, %f2, %f26 |
| 131 | faddd %f0, %f2, %f28 |
| 132 | fmuld %f0, %f2, %f30 |
| 133 | b,pt %xcc, fpdis_exit |
| 134 | nop |
| 135 | 2: andcc %g5, FPRS_DU, %g0 |
| 136 | bne,pt %icc, 3f |
| 137 | fzero %f32 |
| 138 | mov SECONDARY_CONTEXT, %g3 |
| 139 | fzero %f34 |
| 140 | |
| 141 | 661: ldxa [%g3] ASI_DMMU, %g5 |
| 142 | .section .sun4v_1insn_patch, "ax" |
| 143 | .word 661b |
| 144 | ldxa [%g3] ASI_MMU, %g5 |
| 145 | .previous |
| 146 | |
| 147 | add %g6, TI_FPREGS, %g1 |
| 148 | sethi %hi(sparc64_kern_sec_context), %g2 |
| 149 | ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2 |
| 150 | |
| 151 | 661: stxa %g2, [%g3] ASI_DMMU |
| 152 | .section .sun4v_1insn_patch, "ax" |
| 153 | .word 661b |
| 154 | stxa %g2, [%g3] ASI_MMU |
| 155 | .previous |
| 156 | |
| 157 | membar #Sync |
| 158 | add %g6, TI_FPREGS + 0x40, %g2 |
| 159 | faddd %f32, %f34, %f36 |
| 160 | fmuld %f32, %f34, %f38 |
| 161 | membar #Sync |
| 162 | ldda [%g1] ASI_BLK_S, %f0 |
| 163 | ldda [%g2] ASI_BLK_S, %f16 |
| 164 | membar #Sync |
| 165 | faddd %f32, %f34, %f40 |
| 166 | fmuld %f32, %f34, %f42 |
| 167 | faddd %f32, %f34, %f44 |
| 168 | fmuld %f32, %f34, %f46 |
| 169 | faddd %f32, %f34, %f48 |
| 170 | fmuld %f32, %f34, %f50 |
| 171 | faddd %f32, %f34, %f52 |
| 172 | fmuld %f32, %f34, %f54 |
| 173 | faddd %f32, %f34, %f56 |
| 174 | fmuld %f32, %f34, %f58 |
| 175 | faddd %f32, %f34, %f60 |
| 176 | fmuld %f32, %f34, %f62 |
| 177 | ba,pt %xcc, fpdis_exit |
| 178 | nop |
| 179 | 3: mov SECONDARY_CONTEXT, %g3 |
| 180 | add %g6, TI_FPREGS, %g1 |
| 181 | |
| 182 | 661: ldxa [%g3] ASI_DMMU, %g5 |
| 183 | .section .sun4v_1insn_patch, "ax" |
| 184 | .word 661b |
| 185 | ldxa [%g3] ASI_MMU, %g5 |
| 186 | .previous |
| 187 | |
| 188 | sethi %hi(sparc64_kern_sec_context), %g2 |
| 189 | ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2 |
| 190 | |
| 191 | 661: stxa %g2, [%g3] ASI_DMMU |
| 192 | .section .sun4v_1insn_patch, "ax" |
| 193 | .word 661b |
| 194 | stxa %g2, [%g3] ASI_MMU |
| 195 | .previous |
| 196 | |
| 197 | membar #Sync |
| 198 | mov 0x40, %g2 |
| 199 | membar #Sync |
| 200 | ldda [%g1] ASI_BLK_S, %f0 |
| 201 | ldda [%g1 + %g2] ASI_BLK_S, %f16 |
| 202 | add %g1, 0x80, %g1 |
| 203 | ldda [%g1] ASI_BLK_S, %f32 |
| 204 | ldda [%g1 + %g2] ASI_BLK_S, %f48 |
| 205 | membar #Sync |
| 206 | fpdis_exit: |
| 207 | |
| 208 | 661: stxa %g5, [%g3] ASI_DMMU |
| 209 | .section .sun4v_1insn_patch, "ax" |
| 210 | .word 661b |
| 211 | stxa %g5, [%g3] ASI_MMU |
| 212 | .previous |
| 213 | |
| 214 | membar #Sync |
| 215 | fpdis_exit2: |
| 216 | wr %g7, 0, %gsr |
| 217 | ldx [%g6 + TI_XFSR], %fsr |
| 218 | rdpr %tstate, %g3 |
| 219 | or %g3, %g4, %g3 ! anal... |
| 220 | wrpr %g3, %tstate |
| 221 | wr %g0, FPRS_FEF, %fprs ! clean DU/DL bits |
| 222 | retry |
| 223 | |
| 224 | .align 32 |
| 225 | fp_other_bounce: |
| 226 | call do_fpother |
| 227 | add %sp, PTREGS_OFF, %o0 |
| 228 | ba,pt %xcc, rtrap |
| 229 | clr %l6 |
| 230 | |
| 231 | .globl do_fpother_check_fitos |
| 232 | .align 32 |
| 233 | do_fpother_check_fitos: |
| 234 | TRAP_LOAD_THREAD_REG(%g6, %g1) |
| 235 | sethi %hi(fp_other_bounce - 4), %g7 |
| 236 | or %g7, %lo(fp_other_bounce - 4), %g7 |
| 237 | |
| 238 | /* NOTE: Need to preserve %g7 until we fully commit |
| 239 | * to the fitos fixup. |
| 240 | */ |
| 241 | stx %fsr, [%g6 + TI_XFSR] |
| 242 | rdpr %tstate, %g3 |
| 243 | andcc %g3, TSTATE_PRIV, %g0 |
| 244 | bne,pn %xcc, do_fptrap_after_fsr |
| 245 | nop |
| 246 | ldx [%g6 + TI_XFSR], %g3 |
| 247 | srlx %g3, 14, %g1 |
| 248 | and %g1, 7, %g1 |
| 249 | cmp %g1, 2 ! Unfinished FP-OP |
| 250 | bne,pn %xcc, do_fptrap_after_fsr |
| 251 | sethi %hi(1 << 23), %g1 ! Inexact |
| 252 | andcc %g3, %g1, %g0 |
| 253 | bne,pn %xcc, do_fptrap_after_fsr |
| 254 | rdpr %tpc, %g1 |
| 255 | lduwa [%g1] ASI_AIUP, %g3 ! This cannot ever fail |
| 256 | #define FITOS_MASK 0xc1f83fe0 |
| 257 | #define FITOS_COMPARE 0x81a01880 |
| 258 | sethi %hi(FITOS_MASK), %g1 |
| 259 | or %g1, %lo(FITOS_MASK), %g1 |
| 260 | and %g3, %g1, %g1 |
| 261 | sethi %hi(FITOS_COMPARE), %g2 |
| 262 | or %g2, %lo(FITOS_COMPARE), %g2 |
| 263 | cmp %g1, %g2 |
| 264 | bne,pn %xcc, do_fptrap_after_fsr |
| 265 | nop |
| 266 | std %f62, [%g6 + TI_FPREGS + (62 * 4)] |
| 267 | sethi %hi(fitos_table_1), %g1 |
| 268 | and %g3, 0x1f, %g2 |
| 269 | or %g1, %lo(fitos_table_1), %g1 |
| 270 | sllx %g2, 2, %g2 |
| 271 | jmpl %g1 + %g2, %g0 |
| 272 | ba,pt %xcc, fitos_emul_continue |
| 273 | |
| 274 | fitos_table_1: |
| 275 | fitod %f0, %f62 |
| 276 | fitod %f1, %f62 |
| 277 | fitod %f2, %f62 |
| 278 | fitod %f3, %f62 |
| 279 | fitod %f4, %f62 |
| 280 | fitod %f5, %f62 |
| 281 | fitod %f6, %f62 |
| 282 | fitod %f7, %f62 |
| 283 | fitod %f8, %f62 |
| 284 | fitod %f9, %f62 |
| 285 | fitod %f10, %f62 |
| 286 | fitod %f11, %f62 |
| 287 | fitod %f12, %f62 |
| 288 | fitod %f13, %f62 |
| 289 | fitod %f14, %f62 |
| 290 | fitod %f15, %f62 |
| 291 | fitod %f16, %f62 |
| 292 | fitod %f17, %f62 |
| 293 | fitod %f18, %f62 |
| 294 | fitod %f19, %f62 |
| 295 | fitod %f20, %f62 |
| 296 | fitod %f21, %f62 |
| 297 | fitod %f22, %f62 |
| 298 | fitod %f23, %f62 |
| 299 | fitod %f24, %f62 |
| 300 | fitod %f25, %f62 |
| 301 | fitod %f26, %f62 |
| 302 | fitod %f27, %f62 |
| 303 | fitod %f28, %f62 |
| 304 | fitod %f29, %f62 |
| 305 | fitod %f30, %f62 |
| 306 | fitod %f31, %f62 |
| 307 | |
| 308 | fitos_emul_continue: |
| 309 | sethi %hi(fitos_table_2), %g1 |
| 310 | srl %g3, 25, %g2 |
| 311 | or %g1, %lo(fitos_table_2), %g1 |
| 312 | and %g2, 0x1f, %g2 |
| 313 | sllx %g2, 2, %g2 |
| 314 | jmpl %g1 + %g2, %g0 |
| 315 | ba,pt %xcc, fitos_emul_fini |
| 316 | |
| 317 | fitos_table_2: |
| 318 | fdtos %f62, %f0 |
| 319 | fdtos %f62, %f1 |
| 320 | fdtos %f62, %f2 |
| 321 | fdtos %f62, %f3 |
| 322 | fdtos %f62, %f4 |
| 323 | fdtos %f62, %f5 |
| 324 | fdtos %f62, %f6 |
| 325 | fdtos %f62, %f7 |
| 326 | fdtos %f62, %f8 |
| 327 | fdtos %f62, %f9 |
| 328 | fdtos %f62, %f10 |
| 329 | fdtos %f62, %f11 |
| 330 | fdtos %f62, %f12 |
| 331 | fdtos %f62, %f13 |
| 332 | fdtos %f62, %f14 |
| 333 | fdtos %f62, %f15 |
| 334 | fdtos %f62, %f16 |
| 335 | fdtos %f62, %f17 |
| 336 | fdtos %f62, %f18 |
| 337 | fdtos %f62, %f19 |
| 338 | fdtos %f62, %f20 |
| 339 | fdtos %f62, %f21 |
| 340 | fdtos %f62, %f22 |
| 341 | fdtos %f62, %f23 |
| 342 | fdtos %f62, %f24 |
| 343 | fdtos %f62, %f25 |
| 344 | fdtos %f62, %f26 |
| 345 | fdtos %f62, %f27 |
| 346 | fdtos %f62, %f28 |
| 347 | fdtos %f62, %f29 |
| 348 | fdtos %f62, %f30 |
| 349 | fdtos %f62, %f31 |
| 350 | |
| 351 | fitos_emul_fini: |
| 352 | ldd [%g6 + TI_FPREGS + (62 * 4)], %f62 |
| 353 | done |
| 354 | |
| 355 | .globl do_fptrap |
| 356 | .align 32 |
| 357 | do_fptrap: |
| 358 | TRAP_LOAD_THREAD_REG(%g6, %g1) |
| 359 | stx %fsr, [%g6 + TI_XFSR] |
| 360 | do_fptrap_after_fsr: |
| 361 | ldub [%g6 + TI_FPSAVED], %g3 |
| 362 | rd %fprs, %g1 |
| 363 | or %g3, %g1, %g3 |
| 364 | stb %g3, [%g6 + TI_FPSAVED] |
| 365 | rd %gsr, %g3 |
| 366 | stx %g3, [%g6 + TI_GSR] |
| 367 | mov SECONDARY_CONTEXT, %g3 |
| 368 | |
| 369 | 661: ldxa [%g3] ASI_DMMU, %g5 |
| 370 | .section .sun4v_1insn_patch, "ax" |
| 371 | .word 661b |
| 372 | ldxa [%g3] ASI_MMU, %g5 |
| 373 | .previous |
| 374 | |
| 375 | sethi %hi(sparc64_kern_sec_context), %g2 |
| 376 | ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2 |
| 377 | |
| 378 | 661: stxa %g2, [%g3] ASI_DMMU |
| 379 | .section .sun4v_1insn_patch, "ax" |
| 380 | .word 661b |
| 381 | stxa %g2, [%g3] ASI_MMU |
| 382 | .previous |
| 383 | |
| 384 | membar #Sync |
| 385 | add %g6, TI_FPREGS, %g2 |
| 386 | andcc %g1, FPRS_DL, %g0 |
| 387 | be,pn %icc, 4f |
| 388 | mov 0x40, %g3 |
| 389 | stda %f0, [%g2] ASI_BLK_S |
| 390 | stda %f16, [%g2 + %g3] ASI_BLK_S |
| 391 | andcc %g1, FPRS_DU, %g0 |
| 392 | be,pn %icc, 5f |
| 393 | 4: add %g2, 128, %g2 |
| 394 | stda %f32, [%g2] ASI_BLK_S |
| 395 | stda %f48, [%g2 + %g3] ASI_BLK_S |
| 396 | 5: mov SECONDARY_CONTEXT, %g1 |
| 397 | membar #Sync |
| 398 | |
| 399 | 661: stxa %g5, [%g1] ASI_DMMU |
| 400 | .section .sun4v_1insn_patch, "ax" |
| 401 | .word 661b |
| 402 | stxa %g5, [%g1] ASI_MMU |
| 403 | .previous |
| 404 | |
| 405 | membar #Sync |
| 406 | ba,pt %xcc, etrap |
| 407 | wr %g0, 0, %fprs |
| 408 | |
| 409 | /* The registers for cross calls will be: |
| 410 | * |
| 411 | * DATA 0: [low 32-bits] Address of function to call, jmp to this |
| 412 | * [high 32-bits] MMU Context Argument 0, place in %g5 |
| 413 | * DATA 1: Address Argument 1, place in %g1 |
| 414 | * DATA 2: Address Argument 2, place in %g7 |
| 415 | * |
| 416 | * With this method we can do most of the cross-call tlb/cache |
| 417 | * flushing very quickly. |
| 418 | */ |
| 419 | .text |
| 420 | .align 32 |
| 421 | .globl do_ivec |
| 422 | do_ivec: |
| 423 | mov 0x40, %g3 |
| 424 | ldxa [%g3 + %g0] ASI_INTR_R, %g3 |
| 425 | sethi %hi(KERNBASE), %g4 |
| 426 | cmp %g3, %g4 |
| 427 | bgeu,pn %xcc, do_ivec_xcall |
| 428 | srlx %g3, 32, %g5 |
| 429 | stxa %g0, [%g0] ASI_INTR_RECEIVE |
| 430 | membar #Sync |
| 431 | |
| 432 | sethi %hi(ivector_table), %g2 |
| 433 | sllx %g3, 3, %g3 |
| 434 | or %g2, %lo(ivector_table), %g2 |
| 435 | add %g2, %g3, %g3 |
| 436 | |
| 437 | TRAP_LOAD_IRQ_WORK(%g6, %g1) |
| 438 | |
| 439 | lduw [%g6], %g5 /* g5 = irq_work(cpu) */ |
| 440 | stw %g5, [%g3 + 0x00] /* bucket->irq_chain = g5 */ |
| 441 | stw %g3, [%g6] /* irq_work(cpu) = bucket */ |
| 442 | wr %g0, 1 << PIL_DEVICE_IRQ, %set_softint |
| 443 | retry |
| 444 | do_ivec_xcall: |
| 445 | mov 0x50, %g1 |
| 446 | ldxa [%g1 + %g0] ASI_INTR_R, %g1 |
| 447 | srl %g3, 0, %g3 |
| 448 | |
| 449 | mov 0x60, %g7 |
| 450 | ldxa [%g7 + %g0] ASI_INTR_R, %g7 |
| 451 | stxa %g0, [%g0] ASI_INTR_RECEIVE |
| 452 | membar #Sync |
| 453 | ba,pt %xcc, 1f |
| 454 | nop |
| 455 | |
| 456 | .align 32 |
| 457 | 1: jmpl %g3, %g0 |
| 458 | nop |
| 459 | |
| 460 | .globl getcc, setcc |
| 461 | getcc: |
| 462 | ldx [%o0 + PT_V9_TSTATE], %o1 |
| 463 | srlx %o1, 32, %o1 |
| 464 | and %o1, 0xf, %o1 |
| 465 | retl |
| 466 | stx %o1, [%o0 + PT_V9_G1] |
| 467 | setcc: |
| 468 | ldx [%o0 + PT_V9_TSTATE], %o1 |
| 469 | ldx [%o0 + PT_V9_G1], %o2 |
| 470 | or %g0, %ulo(TSTATE_ICC), %o3 |
| 471 | sllx %o3, 32, %o3 |
| 472 | andn %o1, %o3, %o1 |
| 473 | sllx %o2, 32, %o2 |
| 474 | and %o2, %o3, %o2 |
| 475 | or %o1, %o2, %o1 |
| 476 | retl |
| 477 | stx %o1, [%o0 + PT_V9_TSTATE] |
| 478 | |
| 479 | .globl utrap_trap |
| 480 | utrap_trap: /* %g3=handler,%g4=level */ |
| 481 | TRAP_LOAD_THREAD_REG(%g6, %g1) |
| 482 | ldx [%g6 + TI_UTRAPS], %g1 |
| 483 | brnz,pt %g1, invoke_utrap |
| 484 | nop |
| 485 | |
| 486 | ba,pt %xcc, etrap |
| 487 | rd %pc, %g7 |
| 488 | mov %l4, %o1 |
| 489 | call bad_trap |
| 490 | add %sp, PTREGS_OFF, %o0 |
| 491 | ba,pt %xcc, rtrap |
| 492 | clr %l6 |
| 493 | |
| 494 | invoke_utrap: |
| 495 | sllx %g3, 3, %g3 |
| 496 | ldx [%g1 + %g3], %g1 |
| 497 | save %sp, -128, %sp |
| 498 | rdpr %tstate, %l6 |
| 499 | rdpr %cwp, %l7 |
| 500 | andn %l6, TSTATE_CWP, %l6 |
| 501 | wrpr %l6, %l7, %tstate |
| 502 | rdpr %tpc, %l6 |
| 503 | rdpr %tnpc, %l7 |
| 504 | wrpr %g1, 0, %tnpc |
| 505 | done |
| 506 | |
| 507 | /* We need to carefully read the error status, ACK |
| 508 | * the errors, prevent recursive traps, and pass the |
| 509 | * information on to C code for logging. |
| 510 | * |
| 511 | * We pass the AFAR in as-is, and we encode the status |
| 512 | * information as described in asm-sparc64/sfafsr.h |
| 513 | */ |
| 514 | .globl __spitfire_access_error |
| 515 | __spitfire_access_error: |
| 516 | /* Disable ESTATE error reporting so that we do not |
| 517 | * take recursive traps and RED state the processor. |
| 518 | */ |
| 519 | stxa %g0, [%g0] ASI_ESTATE_ERROR_EN |
| 520 | membar #Sync |
| 521 | |
| 522 | mov UDBE_UE, %g1 |
| 523 | ldxa [%g0] ASI_AFSR, %g4 ! Get AFSR |
| 524 | |
| 525 | /* __spitfire_cee_trap branches here with AFSR in %g4 and |
| 526 | * UDBE_CE in %g1. It only clears ESTATE_ERR_CE in the |
| 527 | * ESTATE Error Enable register. |
| 528 | */ |
| 529 | __spitfire_cee_trap_continue: |
| 530 | ldxa [%g0] ASI_AFAR, %g5 ! Get AFAR |
| 531 | |
| 532 | rdpr %tt, %g3 |
| 533 | and %g3, 0x1ff, %g3 ! Paranoia |
| 534 | sllx %g3, SFSTAT_TRAP_TYPE_SHIFT, %g3 |
| 535 | or %g4, %g3, %g4 |
| 536 | rdpr %tl, %g3 |
| 537 | cmp %g3, 1 |
| 538 | mov 1, %g3 |
| 539 | bleu %xcc, 1f |
| 540 | sllx %g3, SFSTAT_TL_GT_ONE_SHIFT, %g3 |
| 541 | |
| 542 | or %g4, %g3, %g4 |
| 543 | |
| 544 | /* Read in the UDB error register state, clearing the |
| 545 | * sticky error bits as-needed. We only clear them if |
| 546 | * the UE bit is set. Likewise, __spitfire_cee_trap |
| 547 | * below will only do so if the CE bit is set. |
| 548 | * |
| 549 | * NOTE: UltraSparc-I/II have high and low UDB error |
| 550 | * registers, corresponding to the two UDB units |
| 551 | * present on those chips. UltraSparc-IIi only |
| 552 | * has a single UDB, called "SDB" in the manual. |
| 553 | * For IIi the upper UDB register always reads |
| 554 | * as zero so for our purposes things will just |
| 555 | * work with the checks below. |
| 556 | */ |
| 557 | 1: ldxa [%g0] ASI_UDBH_ERROR_R, %g3 |
| 558 | and %g3, 0x3ff, %g7 ! Paranoia |
| 559 | sllx %g7, SFSTAT_UDBH_SHIFT, %g7 |
| 560 | or %g4, %g7, %g4 |
| 561 | andcc %g3, %g1, %g3 ! UDBE_UE or UDBE_CE |
| 562 | be,pn %xcc, 1f |
| 563 | nop |
| 564 | stxa %g3, [%g0] ASI_UDB_ERROR_W |
| 565 | membar #Sync |
| 566 | |
| 567 | 1: mov 0x18, %g3 |
| 568 | ldxa [%g3] ASI_UDBL_ERROR_R, %g3 |
| 569 | and %g3, 0x3ff, %g7 ! Paranoia |
| 570 | sllx %g7, SFSTAT_UDBL_SHIFT, %g7 |
| 571 | or %g4, %g7, %g4 |
| 572 | andcc %g3, %g1, %g3 ! UDBE_UE or UDBE_CE |
| 573 | be,pn %xcc, 1f |
| 574 | nop |
| 575 | mov 0x18, %g7 |
| 576 | stxa %g3, [%g7] ASI_UDB_ERROR_W |
| 577 | membar #Sync |
| 578 | |
| 579 | 1: /* Ok, now that we've latched the error state, |
| 580 | * clear the sticky bits in the AFSR. |
| 581 | */ |
| 582 | stxa %g4, [%g0] ASI_AFSR |
| 583 | membar #Sync |
| 584 | |
| 585 | rdpr %tl, %g2 |
| 586 | cmp %g2, 1 |
| 587 | rdpr %pil, %g2 |
| 588 | bleu,pt %xcc, 1f |
| 589 | wrpr %g0, 15, %pil |
| 590 | |
| 591 | ba,pt %xcc, etraptl1 |
| 592 | rd %pc, %g7 |
| 593 | |
| 594 | ba,pt %xcc, 2f |
| 595 | nop |
| 596 | |
| 597 | 1: ba,pt %xcc, etrap_irq |
| 598 | rd %pc, %g7 |
| 599 | |
| 600 | 2: |
| 601 | #ifdef CONFIG_TRACE_IRQFLAGS |
| 602 | call trace_hardirqs_off |
| 603 | nop |
| 604 | #endif |
| 605 | mov %l4, %o1 |
| 606 | mov %l5, %o2 |
| 607 | call spitfire_access_error |
| 608 | add %sp, PTREGS_OFF, %o0 |
| 609 | ba,pt %xcc, rtrap |
| 610 | clr %l6 |
| 611 | |
| 612 | /* This is the trap handler entry point for ECC correctable |
| 613 | * errors. They are corrected, but we listen for the trap |
| 614 | * so that the event can be logged. |
| 615 | * |
| 616 | * Disrupting errors are either: |
| 617 | * 1) single-bit ECC errors during UDB reads to system |
| 618 | * memory |
| 619 | * 2) data parity errors during write-back events |
| 620 | * |
| 621 | * As far as I can make out from the manual, the CEE trap |
| 622 | * is only for correctable errors during memory read |
| 623 | * accesses by the front-end of the processor. |
| 624 | * |
| 625 | * The code below is only for trap level 1 CEE events, |
| 626 | * as it is the only situation where we can safely record |
| 627 | * and log. For trap level >1 we just clear the CE bit |
| 628 | * in the AFSR and return. |
| 629 | * |
| 630 | * This is just like __spiftire_access_error above, but it |
| 631 | * specifically handles correctable errors. If an |
| 632 | * uncorrectable error is indicated in the AFSR we |
| 633 | * will branch directly above to __spitfire_access_error |
| 634 | * to handle it instead. Uncorrectable therefore takes |
| 635 | * priority over correctable, and the error logging |
| 636 | * C code will notice this case by inspecting the |
| 637 | * trap type. |
| 638 | */ |
| 639 | .globl __spitfire_cee_trap |
| 640 | __spitfire_cee_trap: |
| 641 | ldxa [%g0] ASI_AFSR, %g4 ! Get AFSR |
| 642 | mov 1, %g3 |
| 643 | sllx %g3, SFAFSR_UE_SHIFT, %g3 |
| 644 | andcc %g4, %g3, %g0 ! Check for UE |
| 645 | bne,pn %xcc, __spitfire_access_error |
| 646 | nop |
| 647 | |
| 648 | /* Ok, in this case we only have a correctable error. |
| 649 | * Indicate we only wish to capture that state in register |
| 650 | * %g1, and we only disable CE error reporting unlike UE |
| 651 | * handling which disables all errors. |
| 652 | */ |
| 653 | ldxa [%g0] ASI_ESTATE_ERROR_EN, %g3 |
| 654 | andn %g3, ESTATE_ERR_CE, %g3 |
| 655 | stxa %g3, [%g0] ASI_ESTATE_ERROR_EN |
| 656 | membar #Sync |
| 657 | |
| 658 | /* Preserve AFSR in %g4, indicate UDB state to capture in %g1 */ |
| 659 | ba,pt %xcc, __spitfire_cee_trap_continue |
| 660 | mov UDBE_CE, %g1 |
| 661 | |
| 662 | .globl __spitfire_data_access_exception |
| 663 | .globl __spitfire_data_access_exception_tl1 |
| 664 | __spitfire_data_access_exception_tl1: |
| 665 | rdpr %pstate, %g4 |
| 666 | wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate |
| 667 | mov TLB_SFSR, %g3 |
| 668 | mov DMMU_SFAR, %g5 |
| 669 | ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR |
| 670 | ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR |
| 671 | stxa %g0, [%g3] ASI_DMMU ! Clear SFSR.FaultValid bit |
| 672 | membar #Sync |
| 673 | rdpr %tt, %g3 |
| 674 | cmp %g3, 0x80 ! first win spill/fill trap |
| 675 | blu,pn %xcc, 1f |
| 676 | cmp %g3, 0xff ! last win spill/fill trap |
| 677 | bgu,pn %xcc, 1f |
| 678 | nop |
| 679 | ba,pt %xcc, winfix_dax |
| 680 | rdpr %tpc, %g3 |
| 681 | 1: sethi %hi(109f), %g7 |
| 682 | ba,pt %xcc, etraptl1 |
| 683 | 109: or %g7, %lo(109b), %g7 |
| 684 | mov %l4, %o1 |
| 685 | mov %l5, %o2 |
| 686 | call spitfire_data_access_exception_tl1 |
| 687 | add %sp, PTREGS_OFF, %o0 |
| 688 | ba,pt %xcc, rtrap |
| 689 | clr %l6 |
| 690 | |
| 691 | __spitfire_data_access_exception: |
| 692 | rdpr %pstate, %g4 |
| 693 | wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate |
| 694 | mov TLB_SFSR, %g3 |
| 695 | mov DMMU_SFAR, %g5 |
| 696 | ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR |
| 697 | ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR |
| 698 | stxa %g0, [%g3] ASI_DMMU ! Clear SFSR.FaultValid bit |
| 699 | membar #Sync |
| 700 | sethi %hi(109f), %g7 |
| 701 | ba,pt %xcc, etrap |
| 702 | 109: or %g7, %lo(109b), %g7 |
| 703 | mov %l4, %o1 |
| 704 | mov %l5, %o2 |
| 705 | call spitfire_data_access_exception |
| 706 | add %sp, PTREGS_OFF, %o0 |
| 707 | ba,pt %xcc, rtrap |
| 708 | clr %l6 |
| 709 | |
| 710 | .globl __spitfire_insn_access_exception |
| 711 | .globl __spitfire_insn_access_exception_tl1 |
| 712 | __spitfire_insn_access_exception_tl1: |
| 713 | rdpr %pstate, %g4 |
| 714 | wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate |
| 715 | mov TLB_SFSR, %g3 |
| 716 | ldxa [%g3] ASI_IMMU, %g4 ! Get SFSR |
| 717 | rdpr %tpc, %g5 ! IMMU has no SFAR, use TPC |
| 718 | stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit |
| 719 | membar #Sync |
| 720 | sethi %hi(109f), %g7 |
| 721 | ba,pt %xcc, etraptl1 |
| 722 | 109: or %g7, %lo(109b), %g7 |
| 723 | mov %l4, %o1 |
| 724 | mov %l5, %o2 |
| 725 | call spitfire_insn_access_exception_tl1 |
| 726 | add %sp, PTREGS_OFF, %o0 |
| 727 | ba,pt %xcc, rtrap |
| 728 | clr %l6 |
| 729 | |
| 730 | __spitfire_insn_access_exception: |
| 731 | rdpr %pstate, %g4 |
| 732 | wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate |
| 733 | mov TLB_SFSR, %g3 |
| 734 | ldxa [%g3] ASI_IMMU, %g4 ! Get SFSR |
| 735 | rdpr %tpc, %g5 ! IMMU has no SFAR, use TPC |
| 736 | stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit |
| 737 | membar #Sync |
| 738 | sethi %hi(109f), %g7 |
| 739 | ba,pt %xcc, etrap |
| 740 | 109: or %g7, %lo(109b), %g7 |
| 741 | mov %l4, %o1 |
| 742 | mov %l5, %o2 |
| 743 | call spitfire_insn_access_exception |
| 744 | add %sp, PTREGS_OFF, %o0 |
| 745 | ba,pt %xcc, rtrap |
| 746 | clr %l6 |
| 747 | |
| 748 | /* These get patched into the trap table at boot time |
| 749 | * once we know we have a cheetah processor. |
| 750 | */ |
| 751 | .globl cheetah_fecc_trap_vector, cheetah_fecc_trap_vector_tl1 |
| 752 | cheetah_fecc_trap_vector: |
| 753 | membar #Sync |
| 754 | ldxa [%g0] ASI_DCU_CONTROL_REG, %g1 |
| 755 | andn %g1, DCU_DC | DCU_IC, %g1 |
| 756 | stxa %g1, [%g0] ASI_DCU_CONTROL_REG |
| 757 | membar #Sync |
| 758 | sethi %hi(cheetah_fast_ecc), %g2 |
| 759 | jmpl %g2 + %lo(cheetah_fast_ecc), %g0 |
| 760 | mov 0, %g1 |
| 761 | cheetah_fecc_trap_vector_tl1: |
| 762 | membar #Sync |
| 763 | ldxa [%g0] ASI_DCU_CONTROL_REG, %g1 |
| 764 | andn %g1, DCU_DC | DCU_IC, %g1 |
| 765 | stxa %g1, [%g0] ASI_DCU_CONTROL_REG |
| 766 | membar #Sync |
| 767 | sethi %hi(cheetah_fast_ecc), %g2 |
| 768 | jmpl %g2 + %lo(cheetah_fast_ecc), %g0 |
| 769 | mov 1, %g1 |
| 770 | .globl cheetah_cee_trap_vector, cheetah_cee_trap_vector_tl1 |
| 771 | cheetah_cee_trap_vector: |
| 772 | membar #Sync |
| 773 | ldxa [%g0] ASI_DCU_CONTROL_REG, %g1 |
| 774 | andn %g1, DCU_IC, %g1 |
| 775 | stxa %g1, [%g0] ASI_DCU_CONTROL_REG |
| 776 | membar #Sync |
| 777 | sethi %hi(cheetah_cee), %g2 |
| 778 | jmpl %g2 + %lo(cheetah_cee), %g0 |
| 779 | mov 0, %g1 |
| 780 | cheetah_cee_trap_vector_tl1: |
| 781 | membar #Sync |
| 782 | ldxa [%g0] ASI_DCU_CONTROL_REG, %g1 |
| 783 | andn %g1, DCU_IC, %g1 |
| 784 | stxa %g1, [%g0] ASI_DCU_CONTROL_REG |
| 785 | membar #Sync |
| 786 | sethi %hi(cheetah_cee), %g2 |
| 787 | jmpl %g2 + %lo(cheetah_cee), %g0 |
| 788 | mov 1, %g1 |
| 789 | .globl cheetah_deferred_trap_vector, cheetah_deferred_trap_vector_tl1 |
| 790 | cheetah_deferred_trap_vector: |
| 791 | membar #Sync |
| 792 | ldxa [%g0] ASI_DCU_CONTROL_REG, %g1; |
| 793 | andn %g1, DCU_DC | DCU_IC, %g1; |
| 794 | stxa %g1, [%g0] ASI_DCU_CONTROL_REG; |
| 795 | membar #Sync; |
| 796 | sethi %hi(cheetah_deferred_trap), %g2 |
| 797 | jmpl %g2 + %lo(cheetah_deferred_trap), %g0 |
| 798 | mov 0, %g1 |
| 799 | cheetah_deferred_trap_vector_tl1: |
| 800 | membar #Sync; |
| 801 | ldxa [%g0] ASI_DCU_CONTROL_REG, %g1; |
| 802 | andn %g1, DCU_DC | DCU_IC, %g1; |
| 803 | stxa %g1, [%g0] ASI_DCU_CONTROL_REG; |
| 804 | membar #Sync; |
| 805 | sethi %hi(cheetah_deferred_trap), %g2 |
| 806 | jmpl %g2 + %lo(cheetah_deferred_trap), %g0 |
| 807 | mov 1, %g1 |
| 808 | |
| 809 | /* Cheetah+ specific traps. These are for the new I/D cache parity |
| 810 | * error traps. The first argument to cheetah_plus_parity_handler |
| 811 | * is encoded as follows: |
| 812 | * |
| 813 | * Bit0: 0=dcache,1=icache |
| 814 | * Bit1: 0=recoverable,1=unrecoverable |
| 815 | */ |
| 816 | .globl cheetah_plus_dcpe_trap_vector, cheetah_plus_dcpe_trap_vector_tl1 |
| 817 | cheetah_plus_dcpe_trap_vector: |
| 818 | membar #Sync |
| 819 | sethi %hi(do_cheetah_plus_data_parity), %g7 |
| 820 | jmpl %g7 + %lo(do_cheetah_plus_data_parity), %g0 |
| 821 | nop |
| 822 | nop |
| 823 | nop |
| 824 | nop |
| 825 | nop |
| 826 | |
| 827 | do_cheetah_plus_data_parity: |
| 828 | rdpr %pil, %g2 |
| 829 | wrpr %g0, 15, %pil |
| 830 | ba,pt %xcc, etrap_irq |
| 831 | rd %pc, %g7 |
| 832 | #ifdef CONFIG_TRACE_IRQFLAGS |
| 833 | call trace_hardirqs_off |
| 834 | nop |
| 835 | #endif |
| 836 | mov 0x0, %o0 |
| 837 | call cheetah_plus_parity_error |
| 838 | add %sp, PTREGS_OFF, %o1 |
| 839 | ba,a,pt %xcc, rtrap_irq |
| 840 | |
| 841 | cheetah_plus_dcpe_trap_vector_tl1: |
| 842 | membar #Sync |
| 843 | wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate |
| 844 | sethi %hi(do_dcpe_tl1), %g3 |
| 845 | jmpl %g3 + %lo(do_dcpe_tl1), %g0 |
| 846 | nop |
| 847 | nop |
| 848 | nop |
| 849 | nop |
| 850 | |
| 851 | .globl cheetah_plus_icpe_trap_vector, cheetah_plus_icpe_trap_vector_tl1 |
| 852 | cheetah_plus_icpe_trap_vector: |
| 853 | membar #Sync |
| 854 | sethi %hi(do_cheetah_plus_insn_parity), %g7 |
| 855 | jmpl %g7 + %lo(do_cheetah_plus_insn_parity), %g0 |
| 856 | nop |
| 857 | nop |
| 858 | nop |
| 859 | nop |
| 860 | nop |
| 861 | |
| 862 | do_cheetah_plus_insn_parity: |
| 863 | rdpr %pil, %g2 |
| 864 | wrpr %g0, 15, %pil |
| 865 | ba,pt %xcc, etrap_irq |
| 866 | rd %pc, %g7 |
| 867 | #ifdef CONFIG_TRACE_IRQFLAGS |
| 868 | call trace_hardirqs_off |
| 869 | nop |
| 870 | #endif |
| 871 | mov 0x1, %o0 |
| 872 | call cheetah_plus_parity_error |
| 873 | add %sp, PTREGS_OFF, %o1 |
| 874 | ba,a,pt %xcc, rtrap_irq |
| 875 | |
| 876 | cheetah_plus_icpe_trap_vector_tl1: |
| 877 | membar #Sync |
| 878 | wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate |
| 879 | sethi %hi(do_icpe_tl1), %g3 |
| 880 | jmpl %g3 + %lo(do_icpe_tl1), %g0 |
| 881 | nop |
| 882 | nop |
| 883 | nop |
| 884 | nop |
| 885 | |
| 886 | /* If we take one of these traps when tl >= 1, then we |
| 887 | * jump to interrupt globals. If some trap level above us |
| 888 | * was also using interrupt globals, we cannot recover. |
| 889 | * We may use all interrupt global registers except %g6. |
| 890 | */ |
| 891 | .globl do_dcpe_tl1, do_icpe_tl1 |
| 892 | do_dcpe_tl1: |
| 893 | rdpr %tl, %g1 ! Save original trap level |
| 894 | mov 1, %g2 ! Setup TSTATE checking loop |
| 895 | sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit |
| 896 | 1: wrpr %g2, %tl ! Set trap level to check |
| 897 | rdpr %tstate, %g4 ! Read TSTATE for this level |
| 898 | andcc %g4, %g3, %g0 ! Interrupt globals in use? |
| 899 | bne,a,pn %xcc, do_dcpe_tl1_fatal ! Yep, irrecoverable |
| 900 | wrpr %g1, %tl ! Restore original trap level |
| 901 | add %g2, 1, %g2 ! Next trap level |
| 902 | cmp %g2, %g1 ! Hit them all yet? |
| 903 | ble,pt %icc, 1b ! Not yet |
| 904 | nop |
| 905 | wrpr %g1, %tl ! Restore original trap level |
| 906 | do_dcpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */ |
| 907 | sethi %hi(dcache_parity_tl1_occurred), %g2 |
| 908 | lduw [%g2 + %lo(dcache_parity_tl1_occurred)], %g1 |
| 909 | add %g1, 1, %g1 |
| 910 | stw %g1, [%g2 + %lo(dcache_parity_tl1_occurred)] |
| 911 | /* Reset D-cache parity */ |
| 912 | sethi %hi(1 << 16), %g1 ! D-cache size |
| 913 | mov (1 << 5), %g2 ! D-cache line size |
| 914 | sub %g1, %g2, %g1 ! Move down 1 cacheline |
| 915 | 1: srl %g1, 14, %g3 ! Compute UTAG |
| 916 | membar #Sync |
| 917 | stxa %g3, [%g1] ASI_DCACHE_UTAG |
| 918 | membar #Sync |
| 919 | sub %g2, 8, %g3 ! 64-bit data word within line |
| 920 | 2: membar #Sync |
| 921 | stxa %g0, [%g1 + %g3] ASI_DCACHE_DATA |
| 922 | membar #Sync |
| 923 | subcc %g3, 8, %g3 ! Next 64-bit data word |
| 924 | bge,pt %icc, 2b |
| 925 | nop |
| 926 | subcc %g1, %g2, %g1 ! Next cacheline |
| 927 | bge,pt %icc, 1b |
| 928 | nop |
| 929 | ba,pt %xcc, dcpe_icpe_tl1_common |
| 930 | nop |
| 931 | |
| 932 | do_dcpe_tl1_fatal: |
| 933 | sethi %hi(1f), %g7 |
| 934 | ba,pt %xcc, etraptl1 |
| 935 | 1: or %g7, %lo(1b), %g7 |
| 936 | mov 0x2, %o0 |
| 937 | call cheetah_plus_parity_error |
| 938 | add %sp, PTREGS_OFF, %o1 |
| 939 | ba,pt %xcc, rtrap |
| 940 | clr %l6 |
| 941 | |
| 942 | do_icpe_tl1: |
| 943 | rdpr %tl, %g1 ! Save original trap level |
| 944 | mov 1, %g2 ! Setup TSTATE checking loop |
| 945 | sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit |
| 946 | 1: wrpr %g2, %tl ! Set trap level to check |
| 947 | rdpr %tstate, %g4 ! Read TSTATE for this level |
| 948 | andcc %g4, %g3, %g0 ! Interrupt globals in use? |
| 949 | bne,a,pn %xcc, do_icpe_tl1_fatal ! Yep, irrecoverable |
| 950 | wrpr %g1, %tl ! Restore original trap level |
| 951 | add %g2, 1, %g2 ! Next trap level |
| 952 | cmp %g2, %g1 ! Hit them all yet? |
| 953 | ble,pt %icc, 1b ! Not yet |
| 954 | nop |
| 955 | wrpr %g1, %tl ! Restore original trap level |
| 956 | do_icpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */ |
| 957 | sethi %hi(icache_parity_tl1_occurred), %g2 |
| 958 | lduw [%g2 + %lo(icache_parity_tl1_occurred)], %g1 |
| 959 | add %g1, 1, %g1 |
| 960 | stw %g1, [%g2 + %lo(icache_parity_tl1_occurred)] |
| 961 | /* Flush I-cache */ |
| 962 | sethi %hi(1 << 15), %g1 ! I-cache size |
| 963 | mov (1 << 5), %g2 ! I-cache line size |
| 964 | sub %g1, %g2, %g1 |
| 965 | 1: or %g1, (2 << 3), %g3 |
| 966 | stxa %g0, [%g3] ASI_IC_TAG |
| 967 | membar #Sync |
| 968 | subcc %g1, %g2, %g1 |
| 969 | bge,pt %icc, 1b |
| 970 | nop |
| 971 | ba,pt %xcc, dcpe_icpe_tl1_common |
| 972 | nop |
| 973 | |
| 974 | do_icpe_tl1_fatal: |
| 975 | sethi %hi(1f), %g7 |
| 976 | ba,pt %xcc, etraptl1 |
| 977 | 1: or %g7, %lo(1b), %g7 |
| 978 | mov 0x3, %o0 |
| 979 | call cheetah_plus_parity_error |
| 980 | add %sp, PTREGS_OFF, %o1 |
| 981 | ba,pt %xcc, rtrap |
| 982 | clr %l6 |
| 983 | |
| 984 | dcpe_icpe_tl1_common: |
| 985 | /* Flush D-cache, re-enable D/I caches in DCU and finally |
| 986 | * retry the trapping instruction. |
| 987 | */ |
| 988 | sethi %hi(1 << 16), %g1 ! D-cache size |
| 989 | mov (1 << 5), %g2 ! D-cache line size |
| 990 | sub %g1, %g2, %g1 |
| 991 | 1: stxa %g0, [%g1] ASI_DCACHE_TAG |
| 992 | membar #Sync |
| 993 | subcc %g1, %g2, %g1 |
| 994 | bge,pt %icc, 1b |
| 995 | nop |
| 996 | ldxa [%g0] ASI_DCU_CONTROL_REG, %g1 |
| 997 | or %g1, (DCU_DC | DCU_IC), %g1 |
| 998 | stxa %g1, [%g0] ASI_DCU_CONTROL_REG |
| 999 | membar #Sync |
| 1000 | retry |
| 1001 | |
| 1002 | /* Capture I/D/E-cache state into per-cpu error scoreboard. |
| 1003 | * |
| 1004 | * %g1: (TL>=0) ? 1 : 0 |
| 1005 | * %g2: scratch |
| 1006 | * %g3: scratch |
| 1007 | * %g4: AFSR |
| 1008 | * %g5: AFAR |
| 1009 | * %g6: unused, will have current thread ptr after etrap |
| 1010 | * %g7: scratch |
| 1011 | */ |
| 1012 | __cheetah_log_error: |
| 1013 | /* Put "TL1" software bit into AFSR. */ |
| 1014 | and %g1, 0x1, %g1 |
| 1015 | sllx %g1, 63, %g2 |
| 1016 | or %g4, %g2, %g4 |
| 1017 | |
| 1018 | /* Get log entry pointer for this cpu at this trap level. */ |
| 1019 | BRANCH_IF_JALAPENO(g2,g3,50f) |
| 1020 | ldxa [%g0] ASI_SAFARI_CONFIG, %g2 |
| 1021 | srlx %g2, 17, %g2 |
| 1022 | ba,pt %xcc, 60f |
| 1023 | and %g2, 0x3ff, %g2 |
| 1024 | |
| 1025 | 50: ldxa [%g0] ASI_JBUS_CONFIG, %g2 |
| 1026 | srlx %g2, 17, %g2 |
| 1027 | and %g2, 0x1f, %g2 |
| 1028 | |
| 1029 | 60: sllx %g2, 9, %g2 |
| 1030 | sethi %hi(cheetah_error_log), %g3 |
| 1031 | ldx [%g3 + %lo(cheetah_error_log)], %g3 |
| 1032 | brz,pn %g3, 80f |
| 1033 | nop |
| 1034 | |
| 1035 | add %g3, %g2, %g3 |
| 1036 | sllx %g1, 8, %g1 |
| 1037 | add %g3, %g1, %g1 |
| 1038 | |
| 1039 | /* %g1 holds pointer to the top of the logging scoreboard */ |
| 1040 | ldx [%g1 + 0x0], %g7 |
| 1041 | cmp %g7, -1 |
| 1042 | bne,pn %xcc, 80f |
| 1043 | nop |
| 1044 | |
| 1045 | stx %g4, [%g1 + 0x0] |
| 1046 | stx %g5, [%g1 + 0x8] |
| 1047 | add %g1, 0x10, %g1 |
| 1048 | |
| 1049 | /* %g1 now points to D-cache logging area */ |
| 1050 | set 0x3ff8, %g2 /* DC_addr mask */ |
| 1051 | and %g5, %g2, %g2 /* DC_addr bits of AFAR */ |
| 1052 | srlx %g5, 12, %g3 |
| 1053 | or %g3, 1, %g3 /* PHYS tag + valid */ |
| 1054 | |
| 1055 | 10: ldxa [%g2] ASI_DCACHE_TAG, %g7 |
| 1056 | cmp %g3, %g7 /* TAG match? */ |
| 1057 | bne,pt %xcc, 13f |
| 1058 | nop |
| 1059 | |
| 1060 | /* Yep, what we want, capture state. */ |
| 1061 | stx %g2, [%g1 + 0x20] |
| 1062 | stx %g7, [%g1 + 0x28] |
| 1063 | |
| 1064 | /* A membar Sync is required before and after utag access. */ |
| 1065 | membar #Sync |
| 1066 | ldxa [%g2] ASI_DCACHE_UTAG, %g7 |
| 1067 | membar #Sync |
| 1068 | stx %g7, [%g1 + 0x30] |
| 1069 | ldxa [%g2] ASI_DCACHE_SNOOP_TAG, %g7 |
| 1070 | stx %g7, [%g1 + 0x38] |
| 1071 | clr %g3 |
| 1072 | |
| 1073 | 12: ldxa [%g2 + %g3] ASI_DCACHE_DATA, %g7 |
| 1074 | stx %g7, [%g1] |
| 1075 | add %g3, (1 << 5), %g3 |
| 1076 | cmp %g3, (4 << 5) |
| 1077 | bl,pt %xcc, 12b |
| 1078 | add %g1, 0x8, %g1 |
| 1079 | |
| 1080 | ba,pt %xcc, 20f |
| 1081 | add %g1, 0x20, %g1 |
| 1082 | |
| 1083 | 13: sethi %hi(1 << 14), %g7 |
| 1084 | add %g2, %g7, %g2 |
| 1085 | srlx %g2, 14, %g7 |
| 1086 | cmp %g7, 4 |
| 1087 | bl,pt %xcc, 10b |
| 1088 | nop |
| 1089 | |
| 1090 | add %g1, 0x40, %g1 |
| 1091 | |
| 1092 | /* %g1 now points to I-cache logging area */ |
| 1093 | 20: set 0x1fe0, %g2 /* IC_addr mask */ |
| 1094 | and %g5, %g2, %g2 /* IC_addr bits of AFAR */ |
| 1095 | sllx %g2, 1, %g2 /* IC_addr[13:6]==VA[12:5] */ |
| 1096 | srlx %g5, (13 - 8), %g3 /* Make PTAG */ |
| 1097 | andn %g3, 0xff, %g3 /* Mask off undefined bits */ |
| 1098 | |
| 1099 | 21: ldxa [%g2] ASI_IC_TAG, %g7 |
| 1100 | andn %g7, 0xff, %g7 |
| 1101 | cmp %g3, %g7 |
| 1102 | bne,pt %xcc, 23f |
| 1103 | nop |
| 1104 | |
| 1105 | /* Yep, what we want, capture state. */ |
| 1106 | stx %g2, [%g1 + 0x40] |
| 1107 | stx %g7, [%g1 + 0x48] |
| 1108 | add %g2, (1 << 3), %g2 |
| 1109 | ldxa [%g2] ASI_IC_TAG, %g7 |
| 1110 | add %g2, (1 << 3), %g2 |
| 1111 | stx %g7, [%g1 + 0x50] |
| 1112 | ldxa [%g2] ASI_IC_TAG, %g7 |
| 1113 | add %g2, (1 << 3), %g2 |
| 1114 | stx %g7, [%g1 + 0x60] |
| 1115 | ldxa [%g2] ASI_IC_TAG, %g7 |
| 1116 | stx %g7, [%g1 + 0x68] |
| 1117 | sub %g2, (3 << 3), %g2 |
| 1118 | ldxa [%g2] ASI_IC_STAG, %g7 |
| 1119 | stx %g7, [%g1 + 0x58] |
| 1120 | clr %g3 |
| 1121 | srlx %g2, 2, %g2 |
| 1122 | |
| 1123 | 22: ldxa [%g2 + %g3] ASI_IC_INSTR, %g7 |
| 1124 | stx %g7, [%g1] |
| 1125 | add %g3, (1 << 3), %g3 |
| 1126 | cmp %g3, (8 << 3) |
| 1127 | bl,pt %xcc, 22b |
| 1128 | add %g1, 0x8, %g1 |
| 1129 | |
| 1130 | ba,pt %xcc, 30f |
| 1131 | add %g1, 0x30, %g1 |
| 1132 | |
| 1133 | 23: sethi %hi(1 << 14), %g7 |
| 1134 | add %g2, %g7, %g2 |
| 1135 | srlx %g2, 14, %g7 |
| 1136 | cmp %g7, 4 |
| 1137 | bl,pt %xcc, 21b |
| 1138 | nop |
| 1139 | |
| 1140 | add %g1, 0x70, %g1 |
| 1141 | |
| 1142 | /* %g1 now points to E-cache logging area */ |
| 1143 | 30: andn %g5, (32 - 1), %g2 |
| 1144 | stx %g2, [%g1 + 0x20] |
| 1145 | ldxa [%g2] ASI_EC_TAG_DATA, %g7 |
| 1146 | stx %g7, [%g1 + 0x28] |
| 1147 | ldxa [%g2] ASI_EC_R, %g0 |
| 1148 | clr %g3 |
| 1149 | |
| 1150 | 31: ldxa [%g3] ASI_EC_DATA, %g7 |
| 1151 | stx %g7, [%g1 + %g3] |
| 1152 | add %g3, 0x8, %g3 |
| 1153 | cmp %g3, 0x20 |
| 1154 | |
| 1155 | bl,pt %xcc, 31b |
| 1156 | nop |
| 1157 | 80: |
| 1158 | rdpr %tt, %g2 |
| 1159 | cmp %g2, 0x70 |
| 1160 | be c_fast_ecc |
| 1161 | cmp %g2, 0x63 |
| 1162 | be c_cee |
| 1163 | nop |
| 1164 | ba,pt %xcc, c_deferred |
| 1165 | |
| 1166 | /* Cheetah FECC trap handling, we get here from tl{0,1}_fecc |
| 1167 | * in the trap table. That code has done a memory barrier |
| 1168 | * and has disabled both the I-cache and D-cache in the DCU |
| 1169 | * control register. The I-cache is disabled so that we may |
| 1170 | * capture the corrupted cache line, and the D-cache is disabled |
| 1171 | * because corrupt data may have been placed there and we don't |
| 1172 | * want to reference it. |
| 1173 | * |
| 1174 | * %g1 is one if this trap occurred at %tl >= 1. |
| 1175 | * |
| 1176 | * Next, we turn off error reporting so that we don't recurse. |
| 1177 | */ |
| 1178 | .globl cheetah_fast_ecc |
| 1179 | cheetah_fast_ecc: |
| 1180 | ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2 |
| 1181 | andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2 |
| 1182 | stxa %g2, [%g0] ASI_ESTATE_ERROR_EN |
| 1183 | membar #Sync |
| 1184 | |
| 1185 | /* Fetch and clear AFSR/AFAR */ |
| 1186 | ldxa [%g0] ASI_AFSR, %g4 |
| 1187 | ldxa [%g0] ASI_AFAR, %g5 |
| 1188 | stxa %g4, [%g0] ASI_AFSR |
| 1189 | membar #Sync |
| 1190 | |
| 1191 | ba,pt %xcc, __cheetah_log_error |
| 1192 | nop |
| 1193 | |
| 1194 | c_fast_ecc: |
| 1195 | rdpr %pil, %g2 |
| 1196 | wrpr %g0, 15, %pil |
| 1197 | ba,pt %xcc, etrap_irq |
| 1198 | rd %pc, %g7 |
| 1199 | #ifdef CONFIG_TRACE_IRQFLAGS |
| 1200 | call trace_hardirqs_off |
| 1201 | nop |
| 1202 | #endif |
| 1203 | mov %l4, %o1 |
| 1204 | mov %l5, %o2 |
| 1205 | call cheetah_fecc_handler |
| 1206 | add %sp, PTREGS_OFF, %o0 |
| 1207 | ba,a,pt %xcc, rtrap_irq |
| 1208 | |
| 1209 | /* Our caller has disabled I-cache and performed membar Sync. */ |
| 1210 | .globl cheetah_cee |
| 1211 | cheetah_cee: |
| 1212 | ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2 |
| 1213 | andn %g2, ESTATE_ERROR_CEEN, %g2 |
| 1214 | stxa %g2, [%g0] ASI_ESTATE_ERROR_EN |
| 1215 | membar #Sync |
| 1216 | |
| 1217 | /* Fetch and clear AFSR/AFAR */ |
| 1218 | ldxa [%g0] ASI_AFSR, %g4 |
| 1219 | ldxa [%g0] ASI_AFAR, %g5 |
| 1220 | stxa %g4, [%g0] ASI_AFSR |
| 1221 | membar #Sync |
| 1222 | |
| 1223 | ba,pt %xcc, __cheetah_log_error |
| 1224 | nop |
| 1225 | |
| 1226 | c_cee: |
| 1227 | rdpr %pil, %g2 |
| 1228 | wrpr %g0, 15, %pil |
| 1229 | ba,pt %xcc, etrap_irq |
| 1230 | rd %pc, %g7 |
| 1231 | #ifdef CONFIG_TRACE_IRQFLAGS |
| 1232 | call trace_hardirqs_off |
| 1233 | nop |
| 1234 | #endif |
| 1235 | mov %l4, %o1 |
| 1236 | mov %l5, %o2 |
| 1237 | call cheetah_cee_handler |
| 1238 | add %sp, PTREGS_OFF, %o0 |
| 1239 | ba,a,pt %xcc, rtrap_irq |
| 1240 | |
| 1241 | /* Our caller has disabled I-cache+D-cache and performed membar Sync. */ |
| 1242 | .globl cheetah_deferred_trap |
| 1243 | cheetah_deferred_trap: |
| 1244 | ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2 |
| 1245 | andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2 |
| 1246 | stxa %g2, [%g0] ASI_ESTATE_ERROR_EN |
| 1247 | membar #Sync |
| 1248 | |
| 1249 | /* Fetch and clear AFSR/AFAR */ |
| 1250 | ldxa [%g0] ASI_AFSR, %g4 |
| 1251 | ldxa [%g0] ASI_AFAR, %g5 |
| 1252 | stxa %g4, [%g0] ASI_AFSR |
| 1253 | membar #Sync |
| 1254 | |
| 1255 | ba,pt %xcc, __cheetah_log_error |
| 1256 | nop |
| 1257 | |
| 1258 | c_deferred: |
| 1259 | rdpr %pil, %g2 |
| 1260 | wrpr %g0, 15, %pil |
| 1261 | ba,pt %xcc, etrap_irq |
| 1262 | rd %pc, %g7 |
| 1263 | #ifdef CONFIG_TRACE_IRQFLAGS |
| 1264 | call trace_hardirqs_off |
| 1265 | nop |
| 1266 | #endif |
| 1267 | mov %l4, %o1 |
| 1268 | mov %l5, %o2 |
| 1269 | call cheetah_deferred_handler |
| 1270 | add %sp, PTREGS_OFF, %o0 |
| 1271 | ba,a,pt %xcc, rtrap_irq |
| 1272 | |
| 1273 | .globl __do_privact |
| 1274 | __do_privact: |
| 1275 | mov TLB_SFSR, %g3 |
| 1276 | stxa %g0, [%g3] ASI_DMMU ! Clear FaultValid bit |
| 1277 | membar #Sync |
| 1278 | sethi %hi(109f), %g7 |
| 1279 | ba,pt %xcc, etrap |
| 1280 | 109: or %g7, %lo(109b), %g7 |
| 1281 | call do_privact |
| 1282 | add %sp, PTREGS_OFF, %o0 |
| 1283 | ba,pt %xcc, rtrap |
| 1284 | clr %l6 |
| 1285 | |
| 1286 | .globl do_mna |
| 1287 | do_mna: |
| 1288 | rdpr %tl, %g3 |
| 1289 | cmp %g3, 1 |
| 1290 | |
| 1291 | /* Setup %g4/%g5 now as they are used in the |
| 1292 | * winfixup code. |
| 1293 | */ |
| 1294 | mov TLB_SFSR, %g3 |
| 1295 | mov DMMU_SFAR, %g4 |
| 1296 | ldxa [%g4] ASI_DMMU, %g4 |
| 1297 | ldxa [%g3] ASI_DMMU, %g5 |
| 1298 | stxa %g0, [%g3] ASI_DMMU ! Clear FaultValid bit |
| 1299 | membar #Sync |
| 1300 | bgu,pn %icc, winfix_mna |
| 1301 | rdpr %tpc, %g3 |
| 1302 | |
| 1303 | 1: sethi %hi(109f), %g7 |
| 1304 | ba,pt %xcc, etrap |
| 1305 | 109: or %g7, %lo(109b), %g7 |
| 1306 | mov %l4, %o1 |
| 1307 | mov %l5, %o2 |
| 1308 | call mem_address_unaligned |
| 1309 | add %sp, PTREGS_OFF, %o0 |
| 1310 | ba,pt %xcc, rtrap |
| 1311 | clr %l6 |
| 1312 | |
| 1313 | .globl do_lddfmna |
| 1314 | do_lddfmna: |
| 1315 | sethi %hi(109f), %g7 |
| 1316 | mov TLB_SFSR, %g4 |
| 1317 | ldxa [%g4] ASI_DMMU, %g5 |
| 1318 | stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit |
| 1319 | membar #Sync |
| 1320 | mov DMMU_SFAR, %g4 |
| 1321 | ldxa [%g4] ASI_DMMU, %g4 |
| 1322 | ba,pt %xcc, etrap |
| 1323 | 109: or %g7, %lo(109b), %g7 |
| 1324 | mov %l4, %o1 |
| 1325 | mov %l5, %o2 |
| 1326 | call handle_lddfmna |
| 1327 | add %sp, PTREGS_OFF, %o0 |
| 1328 | ba,pt %xcc, rtrap |
| 1329 | clr %l6 |
| 1330 | |
| 1331 | .globl do_stdfmna |
| 1332 | do_stdfmna: |
| 1333 | sethi %hi(109f), %g7 |
| 1334 | mov TLB_SFSR, %g4 |
| 1335 | ldxa [%g4] ASI_DMMU, %g5 |
| 1336 | stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit |
| 1337 | membar #Sync |
| 1338 | mov DMMU_SFAR, %g4 |
| 1339 | ldxa [%g4] ASI_DMMU, %g4 |
| 1340 | ba,pt %xcc, etrap |
| 1341 | 109: or %g7, %lo(109b), %g7 |
| 1342 | mov %l4, %o1 |
| 1343 | mov %l5, %o2 |
| 1344 | call handle_stdfmna |
| 1345 | add %sp, PTREGS_OFF, %o0 |
| 1346 | ba,pt %xcc, rtrap |
| 1347 | clr %l6 |
| 1348 | |
| 1349 | .globl breakpoint_trap |
| 1350 | breakpoint_trap: |
| 1351 | call sparc_breakpoint |
| 1352 | add %sp, PTREGS_OFF, %o0 |
| 1353 | ba,pt %xcc, rtrap |
| 1354 | nop |
| 1355 | |
| 1356 | #if defined(CONFIG_SUNOS_EMUL) || defined(CONFIG_SOLARIS_EMUL) || \ |
| 1357 | defined(CONFIG_SOLARIS_EMUL_MODULE) |
| 1358 | /* SunOS uses syscall zero as the 'indirect syscall' it looks |
| 1359 | * like indir_syscall(scall_num, arg0, arg1, arg2...); etc. |
| 1360 | * This is complete brain damage. |
| 1361 | */ |
| 1362 | .globl sunos_indir |
| 1363 | sunos_indir: |
| 1364 | srl %o0, 0, %o0 |
| 1365 | mov %o7, %l4 |
| 1366 | cmp %o0, NR_SYSCALLS |
| 1367 | blu,a,pt %icc, 1f |
| 1368 | sll %o0, 0x2, %o0 |
| 1369 | sethi %hi(sunos_nosys), %l6 |
| 1370 | b,pt %xcc, 2f |
| 1371 | or %l6, %lo(sunos_nosys), %l6 |
| 1372 | 1: sethi %hi(sunos_sys_table), %l7 |
| 1373 | or %l7, %lo(sunos_sys_table), %l7 |
| 1374 | lduw [%l7 + %o0], %l6 |
| 1375 | 2: mov %o1, %o0 |
| 1376 | mov %o2, %o1 |
| 1377 | mov %o3, %o2 |
| 1378 | mov %o4, %o3 |
| 1379 | mov %o5, %o4 |
| 1380 | call %l6 |
| 1381 | mov %l4, %o7 |
| 1382 | |
| 1383 | .globl sunos_getpid |
| 1384 | sunos_getpid: |
| 1385 | call sys_getppid |
| 1386 | nop |
| 1387 | call sys_getpid |
| 1388 | stx %o0, [%sp + PTREGS_OFF + PT_V9_I1] |
| 1389 | b,pt %xcc, ret_sys_call |
| 1390 | stx %o0, [%sp + PTREGS_OFF + PT_V9_I0] |
| 1391 | |
| 1392 | /* SunOS getuid() returns uid in %o0 and euid in %o1 */ |
| 1393 | .globl sunos_getuid |
| 1394 | sunos_getuid: |
| 1395 | call sys32_geteuid16 |
| 1396 | nop |
| 1397 | call sys32_getuid16 |
| 1398 | stx %o0, [%sp + PTREGS_OFF + PT_V9_I1] |
| 1399 | b,pt %xcc, ret_sys_call |
| 1400 | stx %o0, [%sp + PTREGS_OFF + PT_V9_I0] |
| 1401 | |
| 1402 | /* SunOS getgid() returns gid in %o0 and egid in %o1 */ |
| 1403 | .globl sunos_getgid |
| 1404 | sunos_getgid: |
| 1405 | call sys32_getegid16 |
| 1406 | nop |
| 1407 | call sys32_getgid16 |
| 1408 | stx %o0, [%sp + PTREGS_OFF + PT_V9_I1] |
| 1409 | b,pt %xcc, ret_sys_call |
| 1410 | stx %o0, [%sp + PTREGS_OFF + PT_V9_I0] |
| 1411 | #endif |
| 1412 | |
| 1413 | /* SunOS's execv() call only specifies the argv argument, the |
| 1414 | * environment settings are the same as the calling processes. |
| 1415 | */ |
| 1416 | .globl sunos_execv |
| 1417 | sys_execve: |
| 1418 | sethi %hi(sparc_execve), %g1 |
| 1419 | ba,pt %xcc, execve_merge |
| 1420 | or %g1, %lo(sparc_execve), %g1 |
| 1421 | #ifdef CONFIG_COMPAT |
| 1422 | .globl sys_execve |
| 1423 | sunos_execv: |
| 1424 | stx %g0, [%sp + PTREGS_OFF + PT_V9_I2] |
| 1425 | .globl sys32_execve |
| 1426 | sys32_execve: |
| 1427 | sethi %hi(sparc32_execve), %g1 |
| 1428 | or %g1, %lo(sparc32_execve), %g1 |
| 1429 | #endif |
| 1430 | execve_merge: |
| 1431 | flushw |
| 1432 | jmpl %g1, %g0 |
| 1433 | add %sp, PTREGS_OFF, %o0 |
| 1434 | |
| 1435 | .globl sys_pipe, sys_sigpause, sys_nis_syscall |
| 1436 | .globl sys_rt_sigreturn |
| 1437 | .globl sys_ptrace |
| 1438 | .globl sys_sigaltstack |
| 1439 | .align 32 |
| 1440 | sys_pipe: ba,pt %xcc, sparc_pipe |
| 1441 | add %sp, PTREGS_OFF, %o0 |
| 1442 | sys_nis_syscall:ba,pt %xcc, c_sys_nis_syscall |
| 1443 | add %sp, PTREGS_OFF, %o0 |
| 1444 | sys_memory_ordering: |
| 1445 | ba,pt %xcc, sparc_memory_ordering |
| 1446 | add %sp, PTREGS_OFF, %o1 |
| 1447 | sys_sigaltstack:ba,pt %xcc, do_sigaltstack |
| 1448 | add %i6, STACK_BIAS, %o2 |
| 1449 | #ifdef CONFIG_COMPAT |
| 1450 | .globl sys32_sigstack |
| 1451 | sys32_sigstack: ba,pt %xcc, do_sys32_sigstack |
| 1452 | mov %i6, %o2 |
| 1453 | .globl sys32_sigaltstack |
| 1454 | sys32_sigaltstack: |
| 1455 | ba,pt %xcc, do_sys32_sigaltstack |
| 1456 | mov %i6, %o2 |
| 1457 | #endif |
| 1458 | .align 32 |
| 1459 | #ifdef CONFIG_COMPAT |
| 1460 | .globl sys32_sigreturn |
| 1461 | sys32_sigreturn: |
| 1462 | add %sp, PTREGS_OFF, %o0 |
| 1463 | call do_sigreturn32 |
| 1464 | add %o7, 1f-.-4, %o7 |
| 1465 | nop |
| 1466 | #endif |
| 1467 | sys_rt_sigreturn: |
| 1468 | add %sp, PTREGS_OFF, %o0 |
| 1469 | call do_rt_sigreturn |
| 1470 | add %o7, 1f-.-4, %o7 |
| 1471 | nop |
| 1472 | #ifdef CONFIG_COMPAT |
| 1473 | .globl sys32_rt_sigreturn |
| 1474 | sys32_rt_sigreturn: |
| 1475 | add %sp, PTREGS_OFF, %o0 |
| 1476 | call do_rt_sigreturn32 |
| 1477 | add %o7, 1f-.-4, %o7 |
| 1478 | nop |
| 1479 | #endif |
| 1480 | sys_ptrace: add %sp, PTREGS_OFF, %o0 |
| 1481 | call do_ptrace |
| 1482 | add %o7, 1f-.-4, %o7 |
| 1483 | nop |
| 1484 | .align 32 |
| 1485 | 1: ldx [%curptr + TI_FLAGS], %l5 |
| 1486 | andcc %l5, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0 |
| 1487 | be,pt %icc, rtrap |
| 1488 | clr %l6 |
| 1489 | add %sp, PTREGS_OFF, %o0 |
| 1490 | call syscall_trace |
| 1491 | mov 1, %o1 |
| 1492 | |
| 1493 | ba,pt %xcc, rtrap |
| 1494 | clr %l6 |
| 1495 | |
| 1496 | /* This is how fork() was meant to be done, 8 instruction entry. |
| 1497 | * |
| 1498 | * I questioned the following code briefly, let me clear things |
| 1499 | * up so you must not reason on it like I did. |
| 1500 | * |
| 1501 | * Know the fork_kpsr etc. we use in the sparc32 port? We don't |
| 1502 | * need it here because the only piece of window state we copy to |
| 1503 | * the child is the CWP register. Even if the parent sleeps, |
| 1504 | * we are safe because we stuck it into pt_regs of the parent |
| 1505 | * so it will not change. |
| 1506 | * |
| 1507 | * XXX This raises the question, whether we can do the same on |
| 1508 | * XXX sparc32 to get rid of fork_kpsr _and_ fork_kwim. The |
| 1509 | * XXX answer is yes. We stick fork_kpsr in UREG_G0 and |
| 1510 | * XXX fork_kwim in UREG_G1 (global registers are considered |
| 1511 | * XXX volatile across a system call in the sparc ABI I think |
| 1512 | * XXX if it isn't we can use regs->y instead, anyone who depends |
| 1513 | * XXX upon the Y register being preserved across a fork deserves |
| 1514 | * XXX to lose). |
| 1515 | * |
| 1516 | * In fact we should take advantage of that fact for other things |
| 1517 | * during system calls... |
| 1518 | */ |
| 1519 | .globl sys_fork, sys_vfork, sys_clone, sparc_exit |
| 1520 | .globl ret_from_syscall |
| 1521 | .align 32 |
| 1522 | sys_vfork: /* Under Linux, vfork and fork are just special cases of clone. */ |
| 1523 | sethi %hi(0x4000 | 0x0100 | SIGCHLD), %o0 |
| 1524 | or %o0, %lo(0x4000 | 0x0100 | SIGCHLD), %o0 |
| 1525 | ba,pt %xcc, sys_clone |
| 1526 | sys_fork: clr %o1 |
| 1527 | mov SIGCHLD, %o0 |
| 1528 | sys_clone: flushw |
| 1529 | movrz %o1, %fp, %o1 |
| 1530 | mov 0, %o3 |
| 1531 | ba,pt %xcc, sparc_do_fork |
| 1532 | add %sp, PTREGS_OFF, %o2 |
| 1533 | ret_from_syscall: |
| 1534 | /* Clear current_thread_info()->new_child, and |
| 1535 | * check performance counter stuff too. |
| 1536 | */ |
| 1537 | stb %g0, [%g6 + TI_NEW_CHILD] |
| 1538 | ldx [%g6 + TI_FLAGS], %l0 |
| 1539 | call schedule_tail |
| 1540 | mov %g7, %o0 |
| 1541 | andcc %l0, _TIF_PERFCTR, %g0 |
| 1542 | be,pt %icc, 1f |
| 1543 | nop |
| 1544 | ldx [%g6 + TI_PCR], %o7 |
| 1545 | wr %g0, %o7, %pcr |
| 1546 | |
| 1547 | /* Blackbird errata workaround. See commentary in |
| 1548 | * smp.c:smp_percpu_timer_interrupt() for more |
| 1549 | * information. |
| 1550 | */ |
| 1551 | ba,pt %xcc, 99f |
| 1552 | nop |
| 1553 | .align 64 |
| 1554 | 99: wr %g0, %g0, %pic |
| 1555 | rd %pic, %g0 |
| 1556 | |
| 1557 | 1: b,pt %xcc, ret_sys_call |
| 1558 | ldx [%sp + PTREGS_OFF + PT_V9_I0], %o0 |
| 1559 | sparc_exit: rdpr %pstate, %g2 |
| 1560 | wrpr %g2, PSTATE_IE, %pstate |
| 1561 | rdpr %otherwin, %g1 |
| 1562 | rdpr %cansave, %g3 |
| 1563 | add %g3, %g1, %g3 |
| 1564 | wrpr %g3, 0x0, %cansave |
| 1565 | wrpr %g0, 0x0, %otherwin |
| 1566 | wrpr %g2, 0x0, %pstate |
| 1567 | ba,pt %xcc, sys_exit |
| 1568 | stb %g0, [%g6 + TI_WSAVED] |
| 1569 | |
| 1570 | linux_sparc_ni_syscall: |
| 1571 | sethi %hi(sys_ni_syscall), %l7 |
| 1572 | b,pt %xcc, 4f |
| 1573 | or %l7, %lo(sys_ni_syscall), %l7 |
| 1574 | |
| 1575 | linux_syscall_trace32: |
| 1576 | add %sp, PTREGS_OFF, %o0 |
| 1577 | call syscall_trace |
| 1578 | clr %o1 |
| 1579 | srl %i0, 0, %o0 |
| 1580 | srl %i4, 0, %o4 |
| 1581 | srl %i1, 0, %o1 |
| 1582 | srl %i2, 0, %o2 |
| 1583 | b,pt %xcc, 2f |
| 1584 | srl %i3, 0, %o3 |
| 1585 | |
| 1586 | linux_syscall_trace: |
| 1587 | add %sp, PTREGS_OFF, %o0 |
| 1588 | call syscall_trace |
| 1589 | clr %o1 |
| 1590 | mov %i0, %o0 |
| 1591 | mov %i1, %o1 |
| 1592 | mov %i2, %o2 |
| 1593 | mov %i3, %o3 |
| 1594 | b,pt %xcc, 2f |
| 1595 | mov %i4, %o4 |
| 1596 | |
| 1597 | |
| 1598 | /* Linux 32-bit and SunOS system calls enter here... */ |
| 1599 | .align 32 |
| 1600 | .globl linux_sparc_syscall32 |
| 1601 | linux_sparc_syscall32: |
| 1602 | /* Direct access to user regs, much faster. */ |
| 1603 | cmp %g1, NR_SYSCALLS ! IEU1 Group |
| 1604 | bgeu,pn %xcc, linux_sparc_ni_syscall ! CTI |
| 1605 | srl %i0, 0, %o0 ! IEU0 |
| 1606 | sll %g1, 2, %l4 ! IEU0 Group |
| 1607 | srl %i4, 0, %o4 ! IEU1 |
| 1608 | lduw [%l7 + %l4], %l7 ! Load |
| 1609 | srl %i1, 0, %o1 ! IEU0 Group |
| 1610 | ldx [%curptr + TI_FLAGS], %l0 ! Load |
| 1611 | |
| 1612 | srl %i5, 0, %o5 ! IEU1 |
| 1613 | srl %i2, 0, %o2 ! IEU0 Group |
| 1614 | andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0 |
| 1615 | bne,pn %icc, linux_syscall_trace32 ! CTI |
| 1616 | mov %i0, %l5 ! IEU1 |
| 1617 | call %l7 ! CTI Group brk forced |
| 1618 | srl %i3, 0, %o3 ! IEU0 |
| 1619 | ba,a,pt %xcc, 3f |
| 1620 | |
| 1621 | /* Linux native and SunOS system calls enter here... */ |
| 1622 | .align 32 |
| 1623 | .globl linux_sparc_syscall, ret_sys_call |
| 1624 | linux_sparc_syscall: |
| 1625 | /* Direct access to user regs, much faster. */ |
| 1626 | cmp %g1, NR_SYSCALLS ! IEU1 Group |
| 1627 | bgeu,pn %xcc, linux_sparc_ni_syscall ! CTI |
| 1628 | mov %i0, %o0 ! IEU0 |
| 1629 | sll %g1, 2, %l4 ! IEU0 Group |
| 1630 | mov %i1, %o1 ! IEU1 |
| 1631 | lduw [%l7 + %l4], %l7 ! Load |
| 1632 | 4: mov %i2, %o2 ! IEU0 Group |
| 1633 | ldx [%curptr + TI_FLAGS], %l0 ! Load |
| 1634 | |
| 1635 | mov %i3, %o3 ! IEU1 |
| 1636 | mov %i4, %o4 ! IEU0 Group |
| 1637 | andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0 |
| 1638 | bne,pn %icc, linux_syscall_trace ! CTI Group |
| 1639 | mov %i0, %l5 ! IEU0 |
| 1640 | 2: call %l7 ! CTI Group brk forced |
| 1641 | mov %i5, %o5 ! IEU0 |
| 1642 | nop |
| 1643 | |
| 1644 | 3: stx %o0, [%sp + PTREGS_OFF + PT_V9_I0] |
| 1645 | ret_sys_call: |
| 1646 | ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %g3 |
| 1647 | ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %l1 ! pc = npc |
| 1648 | sra %o0, 0, %o0 |
| 1649 | mov %ulo(TSTATE_XCARRY | TSTATE_ICARRY), %g2 |
| 1650 | sllx %g2, 32, %g2 |
| 1651 | |
| 1652 | /* Check if force_successful_syscall_return() |
| 1653 | * was invoked. |
| 1654 | */ |
| 1655 | ldub [%curptr + TI_SYS_NOERROR], %l2 |
| 1656 | brnz,a,pn %l2, 80f |
| 1657 | stb %g0, [%curptr + TI_SYS_NOERROR] |
| 1658 | |
| 1659 | cmp %o0, -ERESTART_RESTARTBLOCK |
| 1660 | bgeu,pn %xcc, 1f |
| 1661 | andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %l6 |
| 1662 | 80: |
| 1663 | /* System call success, clear Carry condition code. */ |
| 1664 | andn %g3, %g2, %g3 |
| 1665 | stx %g3, [%sp + PTREGS_OFF + PT_V9_TSTATE] |
| 1666 | bne,pn %icc, linux_syscall_trace2 |
| 1667 | add %l1, 0x4, %l2 ! npc = npc+4 |
| 1668 | stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC] |
| 1669 | ba,pt %xcc, rtrap_clr_l6 |
| 1670 | stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC] |
| 1671 | |
| 1672 | 1: |
| 1673 | /* System call failure, set Carry condition code. |
| 1674 | * Also, get abs(errno) to return to the process. |
| 1675 | */ |
| 1676 | andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %l6 |
| 1677 | sub %g0, %o0, %o0 |
| 1678 | or %g3, %g2, %g3 |
| 1679 | stx %o0, [%sp + PTREGS_OFF + PT_V9_I0] |
| 1680 | mov 1, %l6 |
| 1681 | stx %g3, [%sp + PTREGS_OFF + PT_V9_TSTATE] |
| 1682 | bne,pn %icc, linux_syscall_trace2 |
| 1683 | add %l1, 0x4, %l2 ! npc = npc+4 |
| 1684 | stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC] |
| 1685 | |
| 1686 | b,pt %xcc, rtrap |
| 1687 | stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC] |
| 1688 | linux_syscall_trace2: |
| 1689 | add %sp, PTREGS_OFF, %o0 |
| 1690 | call syscall_trace |
| 1691 | mov 1, %o1 |
| 1692 | stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC] |
| 1693 | ba,pt %xcc, rtrap |
| 1694 | stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC] |
| 1695 | |
| 1696 | .align 32 |
| 1697 | .globl __flushw_user |
| 1698 | __flushw_user: |
| 1699 | rdpr %otherwin, %g1 |
| 1700 | brz,pn %g1, 2f |
| 1701 | clr %g2 |
| 1702 | 1: save %sp, -128, %sp |
| 1703 | rdpr %otherwin, %g1 |
| 1704 | brnz,pt %g1, 1b |
| 1705 | add %g2, 1, %g2 |
| 1706 | 1: sub %g2, 1, %g2 |
| 1707 | brnz,pt %g2, 1b |
| 1708 | restore %g0, %g0, %g0 |
| 1709 | 2: retl |
| 1710 | nop |
| 1711 | |
| 1712 | #ifdef CONFIG_SMP |
| 1713 | .globl hard_smp_processor_id |
| 1714 | hard_smp_processor_id: |
| 1715 | #endif |
| 1716 | .globl real_hard_smp_processor_id |
| 1717 | real_hard_smp_processor_id: |
| 1718 | __GET_CPUID(%o0) |
| 1719 | retl |
| 1720 | nop |
| 1721 | |
| 1722 | /* %o0: devhandle |
| 1723 | * %o1: devino |
| 1724 | * |
| 1725 | * returns %o0: sysino |
| 1726 | */ |
| 1727 | .globl sun4v_devino_to_sysino |
| 1728 | .type sun4v_devino_to_sysino,#function |
| 1729 | sun4v_devino_to_sysino: |
| 1730 | mov HV_FAST_INTR_DEVINO2SYSINO, %o5 |
| 1731 | ta HV_FAST_TRAP |
| 1732 | retl |
| 1733 | mov %o1, %o0 |
| 1734 | .size sun4v_devino_to_sysino, .-sun4v_devino_to_sysino |
| 1735 | |
| 1736 | /* %o0: sysino |
| 1737 | * |
| 1738 | * returns %o0: intr_enabled (HV_INTR_{DISABLED,ENABLED}) |
| 1739 | */ |
| 1740 | .globl sun4v_intr_getenabled |
| 1741 | .type sun4v_intr_getenabled,#function |
| 1742 | sun4v_intr_getenabled: |
| 1743 | mov HV_FAST_INTR_GETENABLED, %o5 |
| 1744 | ta HV_FAST_TRAP |
| 1745 | retl |
| 1746 | mov %o1, %o0 |
| 1747 | .size sun4v_intr_getenabled, .-sun4v_intr_getenabled |
| 1748 | |
| 1749 | /* %o0: sysino |
| 1750 | * %o1: intr_enabled (HV_INTR_{DISABLED,ENABLED}) |
| 1751 | */ |
| 1752 | .globl sun4v_intr_setenabled |
| 1753 | .type sun4v_intr_setenabled,#function |
| 1754 | sun4v_intr_setenabled: |
| 1755 | mov HV_FAST_INTR_SETENABLED, %o5 |
| 1756 | ta HV_FAST_TRAP |
| 1757 | retl |
| 1758 | nop |
| 1759 | .size sun4v_intr_setenabled, .-sun4v_intr_setenabled |
| 1760 | |
| 1761 | /* %o0: sysino |
| 1762 | * |
| 1763 | * returns %o0: intr_state (HV_INTR_STATE_*) |
| 1764 | */ |
| 1765 | .globl sun4v_intr_getstate |
| 1766 | .type sun4v_intr_getstate,#function |
| 1767 | sun4v_intr_getstate: |
| 1768 | mov HV_FAST_INTR_GETSTATE, %o5 |
| 1769 | ta HV_FAST_TRAP |
| 1770 | retl |
| 1771 | mov %o1, %o0 |
| 1772 | .size sun4v_intr_getstate, .-sun4v_intr_getstate |
| 1773 | |
| 1774 | /* %o0: sysino |
| 1775 | * %o1: intr_state (HV_INTR_STATE_*) |
| 1776 | */ |
| 1777 | .globl sun4v_intr_setstate |
| 1778 | .type sun4v_intr_setstate,#function |
| 1779 | sun4v_intr_setstate: |
| 1780 | mov HV_FAST_INTR_SETSTATE, %o5 |
| 1781 | ta HV_FAST_TRAP |
| 1782 | retl |
| 1783 | nop |
| 1784 | .size sun4v_intr_setstate, .-sun4v_intr_setstate |
| 1785 | |
| 1786 | /* %o0: sysino |
| 1787 | * |
| 1788 | * returns %o0: cpuid |
| 1789 | */ |
| 1790 | .globl sun4v_intr_gettarget |
| 1791 | .type sun4v_intr_gettarget,#function |
| 1792 | sun4v_intr_gettarget: |
| 1793 | mov HV_FAST_INTR_GETTARGET, %o5 |
| 1794 | ta HV_FAST_TRAP |
| 1795 | retl |
| 1796 | mov %o1, %o0 |
| 1797 | .size sun4v_intr_gettarget, .-sun4v_intr_gettarget |
| 1798 | |
| 1799 | /* %o0: sysino |
| 1800 | * %o1: cpuid |
| 1801 | */ |
| 1802 | .globl sun4v_intr_settarget |
| 1803 | .type sun4v_intr_settarget,#function |
| 1804 | sun4v_intr_settarget: |
| 1805 | mov HV_FAST_INTR_SETTARGET, %o5 |
| 1806 | ta HV_FAST_TRAP |
| 1807 | retl |
| 1808 | nop |
| 1809 | .size sun4v_intr_settarget, .-sun4v_intr_settarget |
| 1810 | |
| 1811 | /* %o0: cpuid |
| 1812 | * %o1: pc |
| 1813 | * %o2: rtba |
| 1814 | * %o3: arg0 |
| 1815 | * |
| 1816 | * returns %o0: status |
| 1817 | */ |
| 1818 | .globl sun4v_cpu_start |
| 1819 | .type sun4v_cpu_start,#function |
| 1820 | sun4v_cpu_start: |
| 1821 | mov HV_FAST_CPU_START, %o5 |
| 1822 | ta HV_FAST_TRAP |
| 1823 | retl |
| 1824 | nop |
| 1825 | .size sun4v_cpu_start, .-sun4v_cpu_start |
| 1826 | |
| 1827 | /* %o0: cpuid |
| 1828 | * |
| 1829 | * returns %o0: status |
| 1830 | */ |
| 1831 | .globl sun4v_cpu_stop |
| 1832 | .type sun4v_cpu_stop,#function |
| 1833 | sun4v_cpu_stop: |
| 1834 | mov HV_FAST_CPU_STOP, %o5 |
| 1835 | ta HV_FAST_TRAP |
| 1836 | retl |
| 1837 | nop |
| 1838 | .size sun4v_cpu_stop, .-sun4v_cpu_stop |
| 1839 | |
| 1840 | /* returns %o0: status */ |
| 1841 | .globl sun4v_cpu_yield |
| 1842 | .type sun4v_cpu_yield, #function |
| 1843 | sun4v_cpu_yield: |
| 1844 | mov HV_FAST_CPU_YIELD, %o5 |
| 1845 | ta HV_FAST_TRAP |
| 1846 | retl |
| 1847 | nop |
| 1848 | .size sun4v_cpu_yield, .-sun4v_cpu_yield |
| 1849 | |
| 1850 | /* %o0: type |
| 1851 | * %o1: queue paddr |
| 1852 | * %o2: num queue entries |
| 1853 | * |
| 1854 | * returns %o0: status |
| 1855 | */ |
| 1856 | .globl sun4v_cpu_qconf |
| 1857 | .type sun4v_cpu_qconf,#function |
| 1858 | sun4v_cpu_qconf: |
| 1859 | mov HV_FAST_CPU_QCONF, %o5 |
| 1860 | ta HV_FAST_TRAP |
| 1861 | retl |
| 1862 | nop |
| 1863 | .size sun4v_cpu_qconf, .-sun4v_cpu_qconf |
| 1864 | |
| 1865 | /* %o0: num cpus in cpu list |
| 1866 | * %o1: cpu list paddr |
| 1867 | * %o2: mondo block paddr |
| 1868 | * |
| 1869 | * returns %o0: status |
| 1870 | */ |
| 1871 | .globl sun4v_cpu_mondo_send |
| 1872 | .type sun4v_cpu_mondo_send,#function |
| 1873 | sun4v_cpu_mondo_send: |
| 1874 | mov HV_FAST_CPU_MONDO_SEND, %o5 |
| 1875 | ta HV_FAST_TRAP |
| 1876 | retl |
| 1877 | nop |
| 1878 | .size sun4v_cpu_mondo_send, .-sun4v_cpu_mondo_send |
| 1879 | |
| 1880 | /* %o0: CPU ID |
| 1881 | * |
| 1882 | * returns %o0: -status if status non-zero, else |
| 1883 | * %o0: cpu state as HV_CPU_STATE_* |
| 1884 | */ |
| 1885 | .globl sun4v_cpu_state |
| 1886 | .type sun4v_cpu_state,#function |
| 1887 | sun4v_cpu_state: |
| 1888 | mov HV_FAST_CPU_STATE, %o5 |
| 1889 | ta HV_FAST_TRAP |
| 1890 | brnz,pn %o0, 1f |
| 1891 | sub %g0, %o0, %o0 |
| 1892 | mov %o1, %o0 |
| 1893 | 1: retl |
| 1894 | nop |
| 1895 | .size sun4v_cpu_state, .-sun4v_cpu_state |
| 1896 | |
| 1897 | /* %o0: virtual address |
| 1898 | * %o1: must be zero |
| 1899 | * %o2: TTE |
| 1900 | * %o3: HV_MMU_* flags |
| 1901 | * |
| 1902 | * returns %o0: status |
| 1903 | */ |
| 1904 | .globl sun4v_mmu_map_perm_addr |
| 1905 | .type sun4v_mmu_map_perm_addr,#function |
| 1906 | sun4v_mmu_map_perm_addr: |
| 1907 | mov HV_FAST_MMU_MAP_PERM_ADDR, %o5 |
| 1908 | ta HV_FAST_TRAP |
| 1909 | retl |
| 1910 | nop |
| 1911 | .size sun4v_mmu_map_perm_addr, .-sun4v_mmu_map_perm_addr |
| 1912 | |
| 1913 | /* %o0: number of TSB descriptions |
| 1914 | * %o1: TSB descriptions real address |
| 1915 | * |
| 1916 | * returns %o0: status |
| 1917 | */ |
| 1918 | .globl sun4v_mmu_tsb_ctx0 |
| 1919 | .type sun4v_mmu_tsb_ctx0,#function |
| 1920 | sun4v_mmu_tsb_ctx0: |
| 1921 | mov HV_FAST_MMU_TSB_CTX0, %o5 |
| 1922 | ta HV_FAST_TRAP |
| 1923 | retl |
| 1924 | nop |
| 1925 | .size sun4v_mmu_tsb_ctx0, .-sun4v_mmu_tsb_ctx0 |
| 1926 | |
| 1927 | /* %o0: API group number |
| 1928 | * %o1: pointer to unsigned long major number storage |
| 1929 | * %o2: pointer to unsigned long minor number storage |
| 1930 | * |
| 1931 | * returns %o0: status |
| 1932 | */ |
| 1933 | .globl sun4v_get_version |
| 1934 | .type sun4v_get_version,#function |
| 1935 | sun4v_get_version: |
| 1936 | mov HV_CORE_GET_VER, %o5 |
| 1937 | mov %o1, %o3 |
| 1938 | mov %o2, %o4 |
| 1939 | ta HV_CORE_TRAP |
| 1940 | stx %o1, [%o3] |
| 1941 | retl |
| 1942 | stx %o2, [%o4] |
| 1943 | .size sun4v_get_version, .-sun4v_get_version |
| 1944 | |
| 1945 | /* %o0: API group number |
| 1946 | * %o1: desired major number |
| 1947 | * %o2: desired minor number |
| 1948 | * %o3: pointer to unsigned long actual minor number storage |
| 1949 | * |
| 1950 | * returns %o0: status |
| 1951 | */ |
| 1952 | .globl sun4v_set_version |
| 1953 | .type sun4v_set_version,#function |
| 1954 | sun4v_set_version: |
| 1955 | mov HV_CORE_SET_VER, %o5 |
| 1956 | mov %o3, %o4 |
| 1957 | ta HV_CORE_TRAP |
| 1958 | retl |
| 1959 | stx %o1, [%o4] |
| 1960 | .size sun4v_set_version, .-sun4v_set_version |
| 1961 | |
| 1962 | /* %o0: pointer to unsigned long time |
| 1963 | * |
| 1964 | * returns %o0: status |
| 1965 | */ |
| 1966 | .globl sun4v_tod_get |
| 1967 | .type sun4v_tod_get,#function |
| 1968 | sun4v_tod_get: |
| 1969 | mov %o0, %o4 |
| 1970 | mov HV_FAST_TOD_GET, %o5 |
| 1971 | ta HV_FAST_TRAP |
| 1972 | stx %o1, [%o4] |
| 1973 | retl |
| 1974 | nop |
| 1975 | .size sun4v_tod_get, .-sun4v_tod_get |
| 1976 | |
| 1977 | /* %o0: time |
| 1978 | * |
| 1979 | * returns %o0: status |
| 1980 | */ |
| 1981 | .globl sun4v_tod_set |
| 1982 | .type sun4v_tod_set,#function |
| 1983 | sun4v_tod_set: |
| 1984 | mov HV_FAST_TOD_SET, %o5 |
| 1985 | ta HV_FAST_TRAP |
| 1986 | retl |
| 1987 | nop |
| 1988 | .size sun4v_tod_set, .-sun4v_tod_set |
| 1989 | |
| 1990 | /* %o0: pointer to unsigned long status |
| 1991 | * |
| 1992 | * returns %o0: signed character |
| 1993 | */ |
| 1994 | .globl sun4v_con_getchar |
| 1995 | .type sun4v_con_getchar,#function |
| 1996 | sun4v_con_getchar: |
| 1997 | mov %o0, %o4 |
| 1998 | mov HV_FAST_CONS_GETCHAR, %o5 |
| 1999 | clr %o0 |
| 2000 | clr %o1 |
| 2001 | ta HV_FAST_TRAP |
| 2002 | stx %o0, [%o4] |
| 2003 | retl |
| 2004 | sra %o1, 0, %o0 |
| 2005 | .size sun4v_con_getchar, .-sun4v_con_getchar |
| 2006 | |
| 2007 | /* %o0: signed long character |
| 2008 | * |
| 2009 | * returns %o0: status |
| 2010 | */ |
| 2011 | .globl sun4v_con_putchar |
| 2012 | .type sun4v_con_putchar,#function |
| 2013 | sun4v_con_putchar: |
| 2014 | mov HV_FAST_CONS_PUTCHAR, %o5 |
| 2015 | ta HV_FAST_TRAP |
| 2016 | retl |
| 2017 | sra %o0, 0, %o0 |
| 2018 | .size sun4v_con_putchar, .-sun4v_con_putchar |
| 2019 | |
| 2020 | /* %o0: buffer real address |
| 2021 | * %o1: buffer size |
| 2022 | * %o2: pointer to unsigned long bytes_read |
| 2023 | * |
| 2024 | * returns %o0: status |
| 2025 | */ |
| 2026 | .globl sun4v_con_read |
| 2027 | .type sun4v_con_read,#function |
| 2028 | sun4v_con_read: |
| 2029 | mov %o2, %o4 |
| 2030 | mov HV_FAST_CONS_READ, %o5 |
| 2031 | ta HV_FAST_TRAP |
| 2032 | brnz %o0, 1f |
| 2033 | cmp %o1, -1 /* break */ |
| 2034 | be,a,pn %icc, 1f |
| 2035 | mov %o1, %o0 |
| 2036 | cmp %o1, -2 /* hup */ |
| 2037 | be,a,pn %icc, 1f |
| 2038 | mov %o1, %o0 |
| 2039 | stx %o1, [%o4] |
| 2040 | 1: retl |
| 2041 | nop |
| 2042 | .size sun4v_con_read, .-sun4v_con_read |
| 2043 | |
| 2044 | /* %o0: buffer real address |
| 2045 | * %o1: buffer size |
| 2046 | * %o2: pointer to unsigned long bytes_written |
| 2047 | * |
| 2048 | * returns %o0: status |
| 2049 | */ |
| 2050 | .globl sun4v_con_write |
| 2051 | .type sun4v_con_write,#function |
| 2052 | sun4v_con_write: |
| 2053 | mov %o2, %o4 |
| 2054 | mov HV_FAST_CONS_WRITE, %o5 |
| 2055 | ta HV_FAST_TRAP |
| 2056 | stx %o1, [%o4] |
| 2057 | retl |
| 2058 | nop |
| 2059 | .size sun4v_con_write, .-sun4v_con_write |
| 2060 | |
| 2061 | /* %o0: soft state |
| 2062 | * %o1: address of description string |
| 2063 | * |
| 2064 | * returns %o0: status |
| 2065 | */ |
| 2066 | .globl sun4v_mach_set_soft_state |
| 2067 | .type sun4v_mach_set_soft_state,#function |
| 2068 | sun4v_mach_set_soft_state: |
| 2069 | mov HV_FAST_MACH_SET_SOFT_STATE, %o5 |
| 2070 | ta HV_FAST_TRAP |
| 2071 | retl |
| 2072 | nop |
| 2073 | .size sun4v_mach_set_soft_state, .-sun4v_mach_set_soft_state |
| 2074 | |
| 2075 | /* %o0: exit code |
| 2076 | * |
| 2077 | * Does not return. |
| 2078 | */ |
| 2079 | .globl sun4v_mach_exit |
| 2080 | .type sun4v_mach_exit,#function |
| 2081 | sun4v_mach_exit: |
| 2082 | mov HV_FAST_MACH_EXIT, %o5 |
| 2083 | ta HV_FAST_TRAP |
| 2084 | retl |
| 2085 | nop |
| 2086 | .size sun4v_mach_exit, .-sun4v_mach_exit |
| 2087 | |
| 2088 | /* %o0: buffer real address |
| 2089 | * %o1: buffer length |
| 2090 | * %o2: pointer to unsigned long real_buf_len |
| 2091 | * |
| 2092 | * returns %o0: status |
| 2093 | */ |
| 2094 | .globl sun4v_mach_desc |
| 2095 | .type sun4v_mach_desc,#function |
| 2096 | sun4v_mach_desc: |
| 2097 | mov %o2, %o4 |
| 2098 | mov HV_FAST_MACH_DESC, %o5 |
| 2099 | ta HV_FAST_TRAP |
| 2100 | stx %o1, [%o4] |
| 2101 | retl |
| 2102 | nop |
| 2103 | .size sun4v_mach_desc, .-sun4v_mach_desc |
| 2104 | |
| 2105 | /* %o0: new timeout in milliseconds |
| 2106 | * %o1: pointer to unsigned long orig_timeout |
| 2107 | * |
| 2108 | * returns %o0: status |
| 2109 | */ |
| 2110 | .globl sun4v_mach_set_watchdog |
| 2111 | .type sun4v_mach_set_watchdog,#function |
| 2112 | sun4v_mach_set_watchdog: |
| 2113 | mov %o1, %o4 |
| 2114 | mov HV_FAST_MACH_SET_WATCHDOG, %o5 |
| 2115 | ta HV_FAST_TRAP |
| 2116 | stx %o1, [%o4] |
| 2117 | retl |
| 2118 | nop |
| 2119 | .size sun4v_mach_set_watchdog, .-sun4v_mach_set_watchdog |
| 2120 | |
| 2121 | /* No inputs and does not return. */ |
| 2122 | .globl sun4v_mach_sir |
| 2123 | .type sun4v_mach_sir,#function |
| 2124 | sun4v_mach_sir: |
| 2125 | mov %o1, %o4 |
| 2126 | mov HV_FAST_MACH_SIR, %o5 |
| 2127 | ta HV_FAST_TRAP |
| 2128 | stx %o1, [%o4] |
| 2129 | retl |
| 2130 | nop |
| 2131 | .size sun4v_mach_sir, .-sun4v_mach_sir |
| 2132 | |
| 2133 | /* %o0: channel |
| 2134 | * %o1: ra |
| 2135 | * %o2: num_entries |
| 2136 | * |
| 2137 | * returns %o0: status |
| 2138 | */ |
| 2139 | .globl sun4v_ldc_tx_qconf |
| 2140 | .type sun4v_ldc_tx_qconf,#function |
| 2141 | sun4v_ldc_tx_qconf: |
| 2142 | mov HV_FAST_LDC_TX_QCONF, %o5 |
| 2143 | ta HV_FAST_TRAP |
| 2144 | retl |
| 2145 | nop |
| 2146 | .size sun4v_ldc_tx_qconf, .-sun4v_ldc_tx_qconf |
| 2147 | |
| 2148 | /* %o0: channel |
| 2149 | * %o1: pointer to unsigned long ra |
| 2150 | * %o2: pointer to unsigned long num_entries |
| 2151 | * |
| 2152 | * returns %o0: status |
| 2153 | */ |
| 2154 | .globl sun4v_ldc_tx_qinfo |
| 2155 | .type sun4v_ldc_tx_qinfo,#function |
| 2156 | sun4v_ldc_tx_qinfo: |
| 2157 | mov %o1, %g1 |
| 2158 | mov %o2, %g2 |
| 2159 | mov HV_FAST_LDC_TX_QINFO, %o5 |
| 2160 | ta HV_FAST_TRAP |
| 2161 | stx %o1, [%g1] |
| 2162 | stx %o2, [%g2] |
| 2163 | retl |
| 2164 | nop |
| 2165 | .size sun4v_ldc_tx_qinfo, .-sun4v_ldc_tx_qinfo |
| 2166 | |
| 2167 | /* %o0: channel |
| 2168 | * %o1: pointer to unsigned long head_off |
| 2169 | * %o2: pointer to unsigned long tail_off |
| 2170 | * %o2: pointer to unsigned long chan_state |
| 2171 | * |
| 2172 | * returns %o0: status |
| 2173 | */ |
| 2174 | .globl sun4v_ldc_tx_get_state |
| 2175 | .type sun4v_ldc_tx_get_state,#function |
| 2176 | sun4v_ldc_tx_get_state: |
| 2177 | mov %o1, %g1 |
| 2178 | mov %o2, %g2 |
| 2179 | mov %o3, %g3 |
| 2180 | mov HV_FAST_LDC_TX_GET_STATE, %o5 |
| 2181 | ta HV_FAST_TRAP |
| 2182 | stx %o1, [%g1] |
| 2183 | stx %o2, [%g2] |
| 2184 | stx %o3, [%g3] |
| 2185 | retl |
| 2186 | nop |
| 2187 | .size sun4v_ldc_tx_get_state, .-sun4v_ldc_tx_get_state |
| 2188 | |
| 2189 | /* %o0: channel |
| 2190 | * %o1: tail_off |
| 2191 | * |
| 2192 | * returns %o0: status |
| 2193 | */ |
| 2194 | .globl sun4v_ldc_tx_set_qtail |
| 2195 | .type sun4v_ldc_tx_set_qtail,#function |
| 2196 | sun4v_ldc_tx_set_qtail: |
| 2197 | mov HV_FAST_LDC_TX_SET_QTAIL, %o5 |
| 2198 | ta HV_FAST_TRAP |
| 2199 | retl |
| 2200 | nop |
| 2201 | .size sun4v_ldc_tx_set_qtail, .-sun4v_ldc_tx_set_qtail |
| 2202 | |
| 2203 | /* %o0: channel |
| 2204 | * %o1: ra |
| 2205 | * %o2: num_entries |
| 2206 | * |
| 2207 | * returns %o0: status |
| 2208 | */ |
| 2209 | .globl sun4v_ldc_rx_qconf |
| 2210 | .type sun4v_ldc_rx_qconf,#function |
| 2211 | sun4v_ldc_rx_qconf: |
| 2212 | mov HV_FAST_LDC_RX_QCONF, %o5 |
| 2213 | ta HV_FAST_TRAP |
| 2214 | retl |
| 2215 | nop |
| 2216 | .size sun4v_ldc_rx_qconf, .-sun4v_ldc_rx_qconf |
| 2217 | |
| 2218 | /* %o0: channel |
| 2219 | * %o1: pointer to unsigned long ra |
| 2220 | * %o2: pointer to unsigned long num_entries |
| 2221 | * |
| 2222 | * returns %o0: status |
| 2223 | */ |
| 2224 | .globl sun4v_ldc_rx_qinfo |
| 2225 | .type sun4v_ldc_rx_qinfo,#function |
| 2226 | sun4v_ldc_rx_qinfo: |
| 2227 | mov %o1, %g1 |
| 2228 | mov %o2, %g2 |
| 2229 | mov HV_FAST_LDC_RX_QINFO, %o5 |
| 2230 | ta HV_FAST_TRAP |
| 2231 | stx %o1, [%g1] |
| 2232 | stx %o2, [%g2] |
| 2233 | retl |
| 2234 | nop |
| 2235 | .size sun4v_ldc_rx_qinfo, .-sun4v_ldc_rx_qinfo |
| 2236 | |
| 2237 | /* %o0: channel |
| 2238 | * %o1: pointer to unsigned long head_off |
| 2239 | * %o2: pointer to unsigned long tail_off |
| 2240 | * %o2: pointer to unsigned long chan_state |
| 2241 | * |
| 2242 | * returns %o0: status |
| 2243 | */ |
| 2244 | .globl sun4v_ldc_rx_get_state |
| 2245 | .type sun4v_ldc_rx_get_state,#function |
| 2246 | sun4v_ldc_rx_get_state: |
| 2247 | mov %o1, %g1 |
| 2248 | mov %o2, %g2 |
| 2249 | mov %o3, %g3 |
| 2250 | mov HV_FAST_LDC_RX_GET_STATE, %o5 |
| 2251 | ta HV_FAST_TRAP |
| 2252 | stx %o1, [%g1] |
| 2253 | stx %o2, [%g2] |
| 2254 | stx %o3, [%g3] |
| 2255 | retl |
| 2256 | nop |
| 2257 | .size sun4v_ldc_rx_get_state, .-sun4v_ldc_rx_get_state |
| 2258 | |
| 2259 | /* %o0: channel |
| 2260 | * %o1: head_off |
| 2261 | * |
| 2262 | * returns %o0: status |
| 2263 | */ |
| 2264 | .globl sun4v_ldc_rx_set_qhead |
| 2265 | .type sun4v_ldc_rx_set_qhead,#function |
| 2266 | sun4v_ldc_rx_set_qhead: |
| 2267 | mov HV_FAST_LDC_RX_SET_QHEAD, %o5 |
| 2268 | ta HV_FAST_TRAP |
| 2269 | retl |
| 2270 | nop |
| 2271 | .size sun4v_ldc_rx_set_qhead, .-sun4v_ldc_rx_set_qhead |
| 2272 | |
| 2273 | /* %o0: channel |
| 2274 | * %o1: ra |
| 2275 | * %o2: num_entries |
| 2276 | * |
| 2277 | * returns %o0: status |
| 2278 | */ |
| 2279 | .globl sun4v_ldc_set_map_table |
| 2280 | .type sun4v_ldc_set_map_table,#function |
| 2281 | sun4v_ldc_set_map_table: |
| 2282 | mov HV_FAST_LDC_SET_MAP_TABLE, %o5 |
| 2283 | ta HV_FAST_TRAP |
| 2284 | retl |
| 2285 | nop |
| 2286 | .size sun4v_ldc_set_map_table, .-sun4v_ldc_set_map_table |
| 2287 | |
| 2288 | /* %o0: channel |
| 2289 | * %o1: pointer to unsigned long ra |
| 2290 | * %o2: pointer to unsigned long num_entries |
| 2291 | * |
| 2292 | * returns %o0: status |
| 2293 | */ |
| 2294 | .globl sun4v_ldc_get_map_table |
| 2295 | .type sun4v_ldc_get_map_table,#function |
| 2296 | sun4v_ldc_get_map_table: |
| 2297 | mov %o1, %g1 |
| 2298 | mov %o2, %g2 |
| 2299 | mov HV_FAST_LDC_GET_MAP_TABLE, %o5 |
| 2300 | ta HV_FAST_TRAP |
| 2301 | stx %o1, [%g1] |
| 2302 | stx %o2, [%g2] |
| 2303 | retl |
| 2304 | nop |
| 2305 | .size sun4v_ldc_get_map_table, .-sun4v_ldc_get_map_table |
| 2306 | |
| 2307 | /* %o0: channel |
| 2308 | * %o1: dir_code |
| 2309 | * %o2: tgt_raddr |
| 2310 | * %o3: lcl_raddr |
| 2311 | * %o4: len |
| 2312 | * %o5: pointer to unsigned long actual_len |
| 2313 | * |
| 2314 | * returns %o0: status |
| 2315 | */ |
| 2316 | .globl sun4v_ldc_copy |
| 2317 | .type sun4v_ldc_copy,#function |
| 2318 | sun4v_ldc_copy: |
| 2319 | mov %o5, %g1 |
| 2320 | mov HV_FAST_LDC_COPY, %o5 |
| 2321 | ta HV_FAST_TRAP |
| 2322 | stx %o1, [%g1] |
| 2323 | retl |
| 2324 | nop |
| 2325 | .size sun4v_ldc_copy, .-sun4v_ldc_copy |
| 2326 | |
| 2327 | /* %o0: channel |
| 2328 | * %o1: cookie |
| 2329 | * %o2: pointer to unsigned long ra |
| 2330 | * %o3: pointer to unsigned long perm |
| 2331 | * |
| 2332 | * returns %o0: status |
| 2333 | */ |
| 2334 | .globl sun4v_ldc_mapin |
| 2335 | .type sun4v_ldc_mapin,#function |
| 2336 | sun4v_ldc_mapin: |
| 2337 | mov %o2, %g1 |
| 2338 | mov %o3, %g2 |
| 2339 | mov HV_FAST_LDC_MAPIN, %o5 |
| 2340 | ta HV_FAST_TRAP |
| 2341 | stx %o1, [%g1] |
| 2342 | stx %o2, [%g2] |
| 2343 | retl |
| 2344 | nop |
| 2345 | .size sun4v_ldc_mapin, .-sun4v_ldc_mapin |
| 2346 | |
| 2347 | /* %o0: ra |
| 2348 | * |
| 2349 | * returns %o0: status |
| 2350 | */ |
| 2351 | .globl sun4v_ldc_unmap |
| 2352 | .type sun4v_ldc_unmap,#function |
| 2353 | sun4v_ldc_unmap: |
| 2354 | mov HV_FAST_LDC_UNMAP, %o5 |
| 2355 | ta HV_FAST_TRAP |
| 2356 | retl |
| 2357 | nop |
| 2358 | .size sun4v_ldc_unmap, .-sun4v_ldc_unmap |
| 2359 | |
| 2360 | /* %o0: cookie |
| 2361 | * %o1: mte_cookie |
| 2362 | * |
| 2363 | * returns %o0: status |
| 2364 | */ |
| 2365 | .globl sun4v_ldc_revoke |
| 2366 | .type sun4v_ldc_revoke,#function |
| 2367 | sun4v_ldc_revoke: |
| 2368 | mov HV_FAST_LDC_REVOKE, %o5 |
| 2369 | ta HV_FAST_TRAP |
| 2370 | retl |
| 2371 | nop |
| 2372 | .size sun4v_ldc_revoke, .-sun4v_ldc_revoke |
| 2373 | |
| 2374 | /* %o0: device handle |
| 2375 | * %o1: device INO |
| 2376 | * %o2: pointer to unsigned long cookie |
| 2377 | * |
| 2378 | * returns %o0: status |
| 2379 | */ |
| 2380 | .globl sun4v_vintr_get_cookie |
| 2381 | .type sun4v_vintr_get_cookie,#function |
| 2382 | sun4v_vintr_get_cookie: |
| 2383 | mov %o2, %g1 |
| 2384 | mov HV_FAST_VINTR_GET_COOKIE, %o5 |
| 2385 | ta HV_FAST_TRAP |
| 2386 | stx %o1, [%g1] |
| 2387 | retl |
| 2388 | nop |
| 2389 | .size sun4v_vintr_get_cookie, .-sun4v_vintr_get_cookie |
| 2390 | |
| 2391 | /* %o0: device handle |
| 2392 | * %o1: device INO |
| 2393 | * %o2: cookie |
| 2394 | * |
| 2395 | * returns %o0: status |
| 2396 | */ |
| 2397 | .globl sun4v_vintr_set_cookie |
| 2398 | .type sun4v_vintr_set_cookie,#function |
| 2399 | sun4v_vintr_set_cookie: |
| 2400 | mov HV_FAST_VINTR_SET_COOKIE, %o5 |
| 2401 | ta HV_FAST_TRAP |
| 2402 | retl |
| 2403 | nop |
| 2404 | .size sun4v_vintr_set_cookie, .-sun4v_vintr_set_cookie |
| 2405 | |
| 2406 | /* %o0: device handle |
| 2407 | * %o1: device INO |
| 2408 | * %o2: pointer to unsigned long valid_state |
| 2409 | * |
| 2410 | * returns %o0: status |
| 2411 | */ |
| 2412 | .globl sun4v_vintr_get_valid |
| 2413 | .type sun4v_vintr_get_valid,#function |
| 2414 | sun4v_vintr_get_valid: |
| 2415 | mov %o2, %g1 |
| 2416 | mov HV_FAST_VINTR_GET_VALID, %o5 |
| 2417 | ta HV_FAST_TRAP |
| 2418 | stx %o1, [%g1] |
| 2419 | retl |
| 2420 | nop |
| 2421 | .size sun4v_vintr_get_valid, .-sun4v_vintr_get_valid |
| 2422 | |
| 2423 | /* %o0: device handle |
| 2424 | * %o1: device INO |
| 2425 | * %o2: valid_state |
| 2426 | * |
| 2427 | * returns %o0: status |
| 2428 | */ |
| 2429 | .globl sun4v_vintr_set_valid |
| 2430 | .type sun4v_vintr_set_valid,#function |
| 2431 | sun4v_vintr_set_valid: |
| 2432 | mov HV_FAST_VINTR_SET_VALID, %o5 |
| 2433 | ta HV_FAST_TRAP |
| 2434 | retl |
| 2435 | nop |
| 2436 | .size sun4v_vintr_set_valid, .-sun4v_vintr_set_valid |
| 2437 | |
| 2438 | /* %o0: device handle |
| 2439 | * %o1: device INO |
| 2440 | * %o2: pointer to unsigned long state |
| 2441 | * |
| 2442 | * returns %o0: status |
| 2443 | */ |
| 2444 | .globl sun4v_vintr_get_state |
| 2445 | .type sun4v_vintr_get_state,#function |
| 2446 | sun4v_vintr_get_state: |
| 2447 | mov %o2, %g1 |
| 2448 | mov HV_FAST_VINTR_GET_STATE, %o5 |
| 2449 | ta HV_FAST_TRAP |
| 2450 | stx %o1, [%g1] |
| 2451 | retl |
| 2452 | nop |
| 2453 | .size sun4v_vintr_get_state, .-sun4v_vintr_get_state |
| 2454 | |
| 2455 | /* %o0: device handle |
| 2456 | * %o1: device INO |
| 2457 | * %o2: state |
| 2458 | * |
| 2459 | * returns %o0: status |
| 2460 | */ |
| 2461 | .globl sun4v_vintr_set_state |
| 2462 | .type sun4v_vintr_set_state,#function |
| 2463 | sun4v_vintr_set_state: |
| 2464 | mov HV_FAST_VINTR_SET_STATE, %o5 |
| 2465 | ta HV_FAST_TRAP |
| 2466 | retl |
| 2467 | nop |
| 2468 | .size sun4v_vintr_set_state, .-sun4v_vintr_set_state |
| 2469 | |
| 2470 | /* %o0: device handle |
| 2471 | * %o1: device INO |
| 2472 | * %o2: pointer to unsigned long cpuid |
| 2473 | * |
| 2474 | * returns %o0: status |
| 2475 | */ |
| 2476 | .globl sun4v_vintr_get_target |
| 2477 | .type sun4v_vintr_get_target,#function |
| 2478 | sun4v_vintr_get_target: |
| 2479 | mov %o2, %g1 |
| 2480 | mov HV_FAST_VINTR_GET_TARGET, %o5 |
| 2481 | ta HV_FAST_TRAP |
| 2482 | stx %o1, [%g1] |
| 2483 | retl |
| 2484 | nop |
| 2485 | .size sun4v_vintr_get_target, .-sun4v_vintr_get_target |
| 2486 | |
| 2487 | /* %o0: device handle |
| 2488 | * %o1: device INO |
| 2489 | * %o2: cpuid |
| 2490 | * |
| 2491 | * returns %o0: status |
| 2492 | */ |
| 2493 | .globl sun4v_vintr_set_target |
| 2494 | .type sun4v_vintr_set_target,#function |
| 2495 | sun4v_vintr_set_target: |
| 2496 | mov HV_FAST_VINTR_SET_TARGET, %o5 |
| 2497 | ta HV_FAST_TRAP |
| 2498 | retl |
| 2499 | nop |
| 2500 | .size sun4v_vintr_set_target, .-sun4v_vintr_set_target |
| 2501 | |
| 2502 | /* %o0: NCS sub-function |
| 2503 | * %o1: sub-function arg real-address |
| 2504 | * %o2: sub-function arg size |
| 2505 | * |
| 2506 | * returns %o0: status |
| 2507 | */ |
| 2508 | .globl sun4v_ncs_request |
| 2509 | .type sun4v_ncs_request,#function |
| 2510 | sun4v_ncs_request: |
| 2511 | mov HV_FAST_NCS_REQUEST, %o5 |
| 2512 | ta HV_FAST_TRAP |
| 2513 | retl |
| 2514 | nop |
| 2515 | .size sun4v_ncs_request, .-sun4v_ncs_request |
| 2516 | |
| 2517 | .globl sun4v_scv_send |
| 2518 | .type sun4v_scv_send,#function |
| 2519 | sun4v_scv_send: |
| 2520 | save %sp, -192, %sp |
| 2521 | mov %i0, %o0 |
| 2522 | mov %i1, %o1 |
| 2523 | mov %i2, %o2 |
| 2524 | mov HV_FAST_SVC_SEND, %o5 |
| 2525 | ta HV_FAST_TRAP |
| 2526 | stx %o1, [%i3] |
| 2527 | ret |
| 2528 | restore |
| 2529 | .size sun4v_scv_send, .-sun4v_scv_send |
| 2530 | |
| 2531 | .globl sun4v_scv_recv |
| 2532 | .type sun4v_scv_recv,#function |
| 2533 | sun4v_scv_recv: |
| 2534 | save %sp, -192, %sp |
| 2535 | mov %i0, %o0 |
| 2536 | mov %i1, %o1 |
| 2537 | mov %i2, %o2 |
| 2538 | mov HV_FAST_SVC_RECV, %o5 |
| 2539 | ta HV_FAST_TRAP |
| 2540 | stx %o1, [%i3] |
| 2541 | ret |
| 2542 | restore |
| 2543 | .size sun4v_scv_recv, .-sun4v_scv_recv |
| 2544 | |
| 2545 | .globl sun4v_scv_getstatus |
| 2546 | .type sun4v_scv_getstatus,#function |
| 2547 | sun4v_scv_getstatus: |
| 2548 | mov HV_FAST_SVC_GETSTATUS, %o5 |
| 2549 | mov %o1, %o4 |
| 2550 | ta HV_FAST_TRAP |
| 2551 | stx %o1, [%o4] |
| 2552 | retl |
| 2553 | nop |
| 2554 | .size sun4v_scv_getstatus, .-sun4v_scv_getstatus |
| 2555 | |
| 2556 | .globl sun4v_scv_setstatus |
| 2557 | .type sun4v_scv_setstatus,#function |
| 2558 | sun4v_scv_setstatus: |
| 2559 | mov HV_FAST_SVC_SETSTATUS, %o5 |
| 2560 | ta HV_FAST_TRAP |
| 2561 | retl |
| 2562 | nop |
| 2563 | .size sun4v_scv_setstatus, .-sun4v_scv_setstatus |
| 2564 | |
| 2565 | .globl sun4v_scv_clrstatus |
| 2566 | .type sun4v_scv_clrstatus,#function |
| 2567 | sun4v_scv_clrstatus: |
| 2568 | mov HV_FAST_SVC_CLRSTATUS, %o5 |
| 2569 | ta HV_FAST_TRAP |
| 2570 | retl |
| 2571 | nop |
| 2572 | .size sun4v_scv_clrstatus, .-sun4v_scv_clrstatus |