| 1 | /* pci_impl.h: Helper definitions for PCI controller support. |
| 2 | * |
| 3 | * Copyright (C) 1999, 2007 David S. Miller (davem@davemloft.net) |
| 4 | */ |
| 5 | |
| 6 | #ifndef PCI_IMPL_H |
| 7 | #define PCI_IMPL_H |
| 8 | |
| 9 | #include <linux/types.h> |
| 10 | #include <linux/spinlock.h> |
| 11 | #include <linux/pci.h> |
| 12 | #include <linux/msi.h> |
| 13 | #include <asm/io.h> |
| 14 | #include <asm/prom.h> |
| 15 | #include <asm/iommu.h> |
| 16 | |
| 17 | /* The abstraction used here is that there are PCI controllers, |
| 18 | * each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules |
| 19 | * underneath. Each PCI bus module uses an IOMMU (shared by both |
| 20 | * PBMs of a controller, or per-PBM), and if a streaming buffer |
| 21 | * is present, each PCI bus module has it's own. (ie. the IOMMU |
| 22 | * might be shared between PBMs, the STC is never shared) |
| 23 | * Furthermore, each PCI bus module controls it's own autonomous |
| 24 | * PCI bus. |
| 25 | */ |
| 26 | |
| 27 | #define PCI_STC_FLUSHFLAG_INIT(STC) \ |
| 28 | (*((STC)->strbuf_flushflag) = 0UL) |
| 29 | #define PCI_STC_FLUSHFLAG_SET(STC) \ |
| 30 | (*((STC)->strbuf_flushflag) != 0UL) |
| 31 | |
| 32 | struct pci_controller_info; |
| 33 | |
| 34 | struct pci_pbm_info { |
| 35 | struct pci_pbm_info *next; |
| 36 | int index; |
| 37 | |
| 38 | /* PCI controller we sit under. */ |
| 39 | struct pci_controller_info *parent; |
| 40 | |
| 41 | /* Physical address base of controller registers. */ |
| 42 | unsigned long controller_regs; |
| 43 | |
| 44 | /* Physical address base of PBM registers. */ |
| 45 | unsigned long pbm_regs; |
| 46 | |
| 47 | /* Physical address of DMA sync register, if any. */ |
| 48 | unsigned long sync_reg; |
| 49 | |
| 50 | /* Opaque 32-bit system bus Port ID. */ |
| 51 | u32 portid; |
| 52 | |
| 53 | /* Opaque 32-bit handle used for hypervisor calls. */ |
| 54 | u32 devhandle; |
| 55 | |
| 56 | /* Chipset version information. */ |
| 57 | int chip_type; |
| 58 | #define PBM_CHIP_TYPE_SABRE 1 |
| 59 | #define PBM_CHIP_TYPE_PSYCHO 2 |
| 60 | #define PBM_CHIP_TYPE_SCHIZO 3 |
| 61 | #define PBM_CHIP_TYPE_SCHIZO_PLUS 4 |
| 62 | #define PBM_CHIP_TYPE_TOMATILLO 5 |
| 63 | int chip_version; |
| 64 | int chip_revision; |
| 65 | |
| 66 | /* Name used for top-level resources. */ |
| 67 | char *name; |
| 68 | |
| 69 | /* OBP specific information. */ |
| 70 | struct device_node *prom_node; |
| 71 | u64 ino_bitmap; |
| 72 | |
| 73 | /* PBM I/O and Memory space resources. */ |
| 74 | struct resource io_space; |
| 75 | struct resource mem_space; |
| 76 | |
| 77 | /* Base of PCI Config space, can be per-PBM or shared. */ |
| 78 | unsigned long config_space; |
| 79 | |
| 80 | /* This will be 12 on PCI-E controllers, 8 elsewhere. */ |
| 81 | unsigned long config_space_reg_bits; |
| 82 | |
| 83 | /* State of 66MHz capabilities on this PBM. */ |
| 84 | int is_66mhz_capable; |
| 85 | int all_devs_66mhz; |
| 86 | |
| 87 | #ifdef CONFIG_PCI_MSI |
| 88 | /* MSI info. */ |
| 89 | u32 msiq_num; |
| 90 | u32 msiq_ent_count; |
| 91 | u32 msiq_first; |
| 92 | u32 msiq_first_devino; |
| 93 | u32 msi_num; |
| 94 | u32 msi_first; |
| 95 | u32 msi_data_mask; |
| 96 | u32 msix_data_width; |
| 97 | u64 msi32_start; |
| 98 | u64 msi64_start; |
| 99 | u32 msi32_len; |
| 100 | u32 msi64_len; |
| 101 | void *msi_queues; |
| 102 | unsigned long *msi_bitmap; |
| 103 | int (*setup_msi_irq)(unsigned int *virt_irq_p, struct pci_dev *pdev, |
| 104 | struct msi_desc *entry); |
| 105 | void (*teardown_msi_irq)(unsigned int virt_irq, struct pci_dev *pdev); |
| 106 | #endif /* !(CONFIG_PCI_MSI) */ |
| 107 | |
| 108 | /* This PBM's streaming buffer. */ |
| 109 | struct strbuf stc; |
| 110 | |
| 111 | /* IOMMU state, potentially shared by both PBM segments. */ |
| 112 | struct iommu *iommu; |
| 113 | |
| 114 | /* Now things for the actual PCI bus probes. */ |
| 115 | unsigned int pci_first_busno; |
| 116 | unsigned int pci_last_busno; |
| 117 | struct pci_bus *pci_bus; |
| 118 | void (*scan_bus)(struct pci_pbm_info *); |
| 119 | struct pci_ops *pci_ops; |
| 120 | }; |
| 121 | |
| 122 | struct pci_controller_info { |
| 123 | /* The PCI bus modules controlled by us. */ |
| 124 | struct pci_pbm_info pbm_A; |
| 125 | struct pci_pbm_info pbm_B; |
| 126 | }; |
| 127 | |
| 128 | extern struct pci_pbm_info *pci_pbm_root; |
| 129 | extern unsigned long pci_memspace_mask; |
| 130 | |
| 131 | extern int pci_num_pbms; |
| 132 | |
| 133 | /* PCI bus scanning and fixup support. */ |
| 134 | extern void pci_iommu_table_init(struct iommu *iommu, int tsbsize, |
| 135 | u32 dma_offset, u32 dma_addr_mask); |
| 136 | extern void pci_get_pbm_props(struct pci_pbm_info *pbm); |
| 137 | extern struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm); |
| 138 | extern void pci_determine_mem_io_space(struct pci_pbm_info *pbm); |
| 139 | |
| 140 | extern int pci_host_bridge_read_pci_cfg(struct pci_bus *bus_dev, |
| 141 | unsigned int devfn, |
| 142 | int where, int size, |
| 143 | u32 *value); |
| 144 | extern int pci_host_bridge_write_pci_cfg(struct pci_bus *bus_dev, |
| 145 | unsigned int devfn, |
| 146 | int where, int size, |
| 147 | u32 value); |
| 148 | |
| 149 | /* Error reporting support. */ |
| 150 | extern void pci_scan_for_target_abort(struct pci_pbm_info *, struct pci_bus *); |
| 151 | extern void pci_scan_for_master_abort(struct pci_pbm_info *, struct pci_bus *); |
| 152 | extern void pci_scan_for_parity_error(struct pci_pbm_info *, struct pci_bus *); |
| 153 | |
| 154 | /* Configuration space access. */ |
| 155 | extern void pci_config_read8(u8 *addr, u8 *ret); |
| 156 | extern void pci_config_read16(u16 *addr, u16 *ret); |
| 157 | extern void pci_config_read32(u32 *addr, u32 *ret); |
| 158 | extern void pci_config_write8(u8 *addr, u8 val); |
| 159 | extern void pci_config_write16(u16 *addr, u16 val); |
| 160 | extern void pci_config_write32(u32 *addr, u32 val); |
| 161 | |
| 162 | extern struct pci_ops sun4u_pci_ops; |
| 163 | extern struct pci_ops sun4v_pci_ops; |
| 164 | |
| 165 | #endif /* !(PCI_IMPL_H) */ |