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Linux 2.6.39-rc7
[deliverable/linux.git] / arch / x86 / kernel / apic / x2apic_uv_x.c
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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV APIC functions (note: not an Intel compatible APIC)
7 *
8 * Copyright (C) 2007-2010 Silicon Graphics, Inc. All rights reserved.
9 */
10#include <linux/cpumask.h>
11#include <linux/hardirq.h>
12#include <linux/proc_fs.h>
13#include <linux/threads.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/string.h>
17#include <linux/ctype.h>
18#include <linux/sched.h>
19#include <linux/timer.h>
20#include <linux/slab.h>
21#include <linux/cpu.h>
22#include <linux/init.h>
23#include <linux/io.h>
24#include <linux/pci.h>
25#include <linux/kdebug.h>
26#include <linux/delay.h>
27#include <linux/crash_dump.h>
28
29#include <asm/uv/uv_mmrs.h>
30#include <asm/uv/uv_hub.h>
31#include <asm/current.h>
32#include <asm/pgtable.h>
33#include <asm/uv/bios.h>
34#include <asm/uv/uv.h>
35#include <asm/apic.h>
36#include <asm/ipi.h>
37#include <asm/smp.h>
38#include <asm/x86_init.h>
39#include <asm/emergency-restart.h>
40
41DEFINE_PER_CPU(int, x2apic_extra_bits);
42
43#define PR_DEVEL(fmt, args...) pr_devel("%s: " fmt, __func__, args)
44
45static enum uv_system_type uv_system_type;
46static u64 gru_start_paddr, gru_end_paddr;
47static union uvh_apicid uvh_apicid;
48int uv_min_hub_revision_id;
49EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
50unsigned int uv_apicid_hibits;
51EXPORT_SYMBOL_GPL(uv_apicid_hibits);
52static DEFINE_SPINLOCK(uv_nmi_lock);
53
54static unsigned long __init uv_early_read_mmr(unsigned long addr)
55{
56 unsigned long val, *mmr;
57
58 mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
59 val = *mmr;
60 early_iounmap(mmr, sizeof(*mmr));
61 return val;
62}
63
64static inline bool is_GRU_range(u64 start, u64 end)
65{
66 return start >= gru_start_paddr && end <= gru_end_paddr;
67}
68
69static bool uv_is_untracked_pat_range(u64 start, u64 end)
70{
71 return is_ISA_range(start, end) || is_GRU_range(start, end);
72}
73
74static int __init early_get_pnodeid(void)
75{
76 union uvh_node_id_u node_id;
77 union uvh_rh_gam_config_mmr_u m_n_config;
78 int pnode;
79
80 /* Currently, all blades have same revision number */
81 node_id.v = uv_early_read_mmr(UVH_NODE_ID);
82 m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR);
83 uv_min_hub_revision_id = node_id.s.revision;
84
85 pnode = (node_id.s.node_id >> 1) & ((1 << m_n_config.s.n_skt) - 1);
86 return pnode;
87}
88
89static void __init early_get_apic_pnode_shift(void)
90{
91 uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
92 if (!uvh_apicid.v)
93 /*
94 * Old bios, use default value
95 */
96 uvh_apicid.s.pnode_shift = UV_APIC_PNODE_SHIFT;
97}
98
99/*
100 * Add an extra bit as dictated by bios to the destination apicid of
101 * interrupts potentially passing through the UV HUB. This prevents
102 * a deadlock between interrupts and IO port operations.
103 */
104static void __init uv_set_apicid_hibit(void)
105{
106 union uvh_lb_target_physical_apic_id_mask_u apicid_mask;
107
108 apicid_mask.v = uv_early_read_mmr(UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK);
109 uv_apicid_hibits = apicid_mask.s.bit_enables & UV_APICID_HIBIT_MASK;
110}
111
112static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
113{
114 int pnodeid;
115
116 if (!strcmp(oem_id, "SGI")) {
117 pnodeid = early_get_pnodeid();
118 early_get_apic_pnode_shift();
119 x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range;
120 x86_platform.nmi_init = uv_nmi_init;
121 if (!strcmp(oem_table_id, "UVL"))
122 uv_system_type = UV_LEGACY_APIC;
123 else if (!strcmp(oem_table_id, "UVX"))
124 uv_system_type = UV_X2APIC;
125 else if (!strcmp(oem_table_id, "UVH")) {
126 __this_cpu_write(x2apic_extra_bits,
127 pnodeid << uvh_apicid.s.pnode_shift);
128 uv_system_type = UV_NON_UNIQUE_APIC;
129 uv_set_apicid_hibit();
130 return 1;
131 }
132 }
133 return 0;
134}
135
136enum uv_system_type get_uv_system_type(void)
137{
138 return uv_system_type;
139}
140
141int is_uv_system(void)
142{
143 return uv_system_type != UV_NONE;
144}
145EXPORT_SYMBOL_GPL(is_uv_system);
146
147DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
148EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
149
150struct uv_blade_info *uv_blade_info;
151EXPORT_SYMBOL_GPL(uv_blade_info);
152
153short *uv_node_to_blade;
154EXPORT_SYMBOL_GPL(uv_node_to_blade);
155
156short *uv_cpu_to_blade;
157EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
158
159short uv_possible_blades;
160EXPORT_SYMBOL_GPL(uv_possible_blades);
161
162unsigned long sn_rtc_cycles_per_second;
163EXPORT_SYMBOL(sn_rtc_cycles_per_second);
164
165static const struct cpumask *uv_target_cpus(void)
166{
167 return cpu_online_mask;
168}
169
170static void uv_vector_allocation_domain(int cpu, struct cpumask *retmask)
171{
172 cpumask_clear(retmask);
173 cpumask_set_cpu(cpu, retmask);
174}
175
176static int __cpuinit uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
177{
178#ifdef CONFIG_SMP
179 unsigned long val;
180 int pnode;
181
182 pnode = uv_apicid_to_pnode(phys_apicid);
183 phys_apicid |= uv_apicid_hibits;
184 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
185 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
186 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
187 APIC_DM_INIT;
188 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
189 mdelay(10);
190
191 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
192 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
193 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
194 APIC_DM_STARTUP;
195 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
196
197 atomic_set(&init_deasserted, 1);
198#endif
199 return 0;
200}
201
202static void uv_send_IPI_one(int cpu, int vector)
203{
204 unsigned long apicid;
205 int pnode;
206
207 apicid = per_cpu(x86_cpu_to_apicid, cpu);
208 pnode = uv_apicid_to_pnode(apicid);
209 uv_hub_send_ipi(pnode, apicid, vector);
210}
211
212static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
213{
214 unsigned int cpu;
215
216 for_each_cpu(cpu, mask)
217 uv_send_IPI_one(cpu, vector);
218}
219
220static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
221{
222 unsigned int this_cpu = smp_processor_id();
223 unsigned int cpu;
224
225 for_each_cpu(cpu, mask) {
226 if (cpu != this_cpu)
227 uv_send_IPI_one(cpu, vector);
228 }
229}
230
231static void uv_send_IPI_allbutself(int vector)
232{
233 unsigned int this_cpu = smp_processor_id();
234 unsigned int cpu;
235
236 for_each_online_cpu(cpu) {
237 if (cpu != this_cpu)
238 uv_send_IPI_one(cpu, vector);
239 }
240}
241
242static void uv_send_IPI_all(int vector)
243{
244 uv_send_IPI_mask(cpu_online_mask, vector);
245}
246
247static int uv_apic_id_registered(void)
248{
249 return 1;
250}
251
252static void uv_init_apic_ldr(void)
253{
254}
255
256static unsigned int uv_cpu_mask_to_apicid(const struct cpumask *cpumask)
257{
258 /*
259 * We're using fixed IRQ delivery, can only return one phys APIC ID.
260 * May as well be the first.
261 */
262 int cpu = cpumask_first(cpumask);
263
264 if ((unsigned)cpu < nr_cpu_ids)
265 return per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits;
266 else
267 return BAD_APICID;
268}
269
270static unsigned int
271uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
272 const struct cpumask *andmask)
273{
274 int cpu;
275
276 /*
277 * We're using fixed IRQ delivery, can only return one phys APIC ID.
278 * May as well be the first.
279 */
280 for_each_cpu_and(cpu, cpumask, andmask) {
281 if (cpumask_test_cpu(cpu, cpu_online_mask))
282 break;
283 }
284 return per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits;
285}
286
287static unsigned int x2apic_get_apic_id(unsigned long x)
288{
289 unsigned int id;
290
291 WARN_ON(preemptible() && num_online_cpus() > 1);
292 id = x | __this_cpu_read(x2apic_extra_bits);
293
294 return id;
295}
296
297static unsigned long set_apic_id(unsigned int id)
298{
299 unsigned long x;
300
301 /* maskout x2apic_extra_bits ? */
302 x = id;
303 return x;
304}
305
306static unsigned int uv_read_apic_id(void)
307{
308
309 return x2apic_get_apic_id(apic_read(APIC_ID));
310}
311
312static int uv_phys_pkg_id(int initial_apicid, int index_msb)
313{
314 return uv_read_apic_id() >> index_msb;
315}
316
317static void uv_send_IPI_self(int vector)
318{
319 apic_write(APIC_SELF_IPI, vector);
320}
321
322struct apic __refdata apic_x2apic_uv_x = {
323
324 .name = "UV large system",
325 .probe = NULL,
326 .acpi_madt_oem_check = uv_acpi_madt_oem_check,
327 .apic_id_registered = uv_apic_id_registered,
328
329 .irq_delivery_mode = dest_Fixed,
330 .irq_dest_mode = 0, /* physical */
331
332 .target_cpus = uv_target_cpus,
333 .disable_esr = 0,
334 .dest_logical = APIC_DEST_LOGICAL,
335 .check_apicid_used = NULL,
336 .check_apicid_present = NULL,
337
338 .vector_allocation_domain = uv_vector_allocation_domain,
339 .init_apic_ldr = uv_init_apic_ldr,
340
341 .ioapic_phys_id_map = NULL,
342 .setup_apic_routing = NULL,
343 .multi_timer_check = NULL,
344 .cpu_present_to_apicid = default_cpu_present_to_apicid,
345 .apicid_to_cpu_present = NULL,
346 .setup_portio_remap = NULL,
347 .check_phys_apicid_present = default_check_phys_apicid_present,
348 .enable_apic_mode = NULL,
349 .phys_pkg_id = uv_phys_pkg_id,
350 .mps_oem_check = NULL,
351
352 .get_apic_id = x2apic_get_apic_id,
353 .set_apic_id = set_apic_id,
354 .apic_id_mask = 0xFFFFFFFFu,
355
356 .cpu_mask_to_apicid = uv_cpu_mask_to_apicid,
357 .cpu_mask_to_apicid_and = uv_cpu_mask_to_apicid_and,
358
359 .send_IPI_mask = uv_send_IPI_mask,
360 .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself,
361 .send_IPI_allbutself = uv_send_IPI_allbutself,
362 .send_IPI_all = uv_send_IPI_all,
363 .send_IPI_self = uv_send_IPI_self,
364
365 .wakeup_secondary_cpu = uv_wakeup_secondary,
366 .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
367 .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
368 .wait_for_init_deassert = NULL,
369 .smp_callin_clear_local_apic = NULL,
370 .inquire_remote_apic = NULL,
371
372 .read = native_apic_msr_read,
373 .write = native_apic_msr_write,
374 .icr_read = native_x2apic_icr_read,
375 .icr_write = native_x2apic_icr_write,
376 .wait_icr_idle = native_x2apic_wait_icr_idle,
377 .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
378};
379
380static __cpuinit void set_x2apic_extra_bits(int pnode)
381{
382 __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift);
383}
384
385/*
386 * Called on boot cpu.
387 */
388static __init int boot_pnode_to_blade(int pnode)
389{
390 int blade;
391
392 for (blade = 0; blade < uv_num_possible_blades(); blade++)
393 if (pnode == uv_blade_info[blade].pnode)
394 return blade;
395 BUG();
396}
397
398struct redir_addr {
399 unsigned long redirect;
400 unsigned long alias;
401};
402
403#define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
404
405static __initdata struct redir_addr redir_addrs[] = {
406 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR},
407 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR},
408 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR},
409};
410
411static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
412{
413 union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias;
414 union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
415 int i;
416
417 for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
418 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
419 if (alias.s.enable && alias.s.base == 0) {
420 *size = (1UL << alias.s.m_alias);
421 redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
422 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
423 return;
424 }
425 }
426 *base = *size = 0;
427}
428
429enum map_type {map_wb, map_uc};
430
431static __init void map_high(char *id, unsigned long base, int pshift,
432 int bshift, int max_pnode, enum map_type map_type)
433{
434 unsigned long bytes, paddr;
435
436 paddr = base << pshift;
437 bytes = (1UL << bshift) * (max_pnode + 1);
438 printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
439 paddr + bytes);
440 if (map_type == map_uc)
441 init_extra_mapping_uc(paddr, bytes);
442 else
443 init_extra_mapping_wb(paddr, bytes);
444
445}
446static __init void map_gru_high(int max_pnode)
447{
448 union uvh_rh_gam_gru_overlay_config_mmr_u gru;
449 int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
450
451 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
452 if (gru.s.enable) {
453 map_high("GRU", gru.s.base, shift, shift, max_pnode, map_wb);
454 gru_start_paddr = ((u64)gru.s.base << shift);
455 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
456
457 }
458}
459
460static __init void map_mmr_high(int max_pnode)
461{
462 union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
463 int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
464
465 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
466 if (mmr.s.enable)
467 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
468}
469
470static __init void map_mmioh_high(int max_pnode)
471{
472 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
473 int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
474
475 mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
476 if (mmioh.s.enable)
477 map_high("MMIOH", mmioh.s.base, shift, mmioh.s.m_io,
478 max_pnode, map_uc);
479}
480
481static __init void map_low_mmrs(void)
482{
483 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
484 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
485}
486
487static __init void uv_rtc_init(void)
488{
489 long status;
490 u64 ticks_per_sec;
491
492 status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
493 &ticks_per_sec);
494 if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
495 printk(KERN_WARNING
496 "unable to determine platform RTC clock frequency, "
497 "guessing.\n");
498 /* BIOS gives wrong value for clock freq. so guess */
499 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
500 } else
501 sn_rtc_cycles_per_second = ticks_per_sec;
502}
503
504/*
505 * percpu heartbeat timer
506 */
507static void uv_heartbeat(unsigned long ignored)
508{
509 struct timer_list *timer = &uv_hub_info->scir.timer;
510 unsigned char bits = uv_hub_info->scir.state;
511
512 /* flip heartbeat bit */
513 bits ^= SCIR_CPU_HEARTBEAT;
514
515 /* is this cpu idle? */
516 if (idle_cpu(raw_smp_processor_id()))
517 bits &= ~SCIR_CPU_ACTIVITY;
518 else
519 bits |= SCIR_CPU_ACTIVITY;
520
521 /* update system controller interface reg */
522 uv_set_scir_bits(bits);
523
524 /* enable next timer period */
525 mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL);
526}
527
528static void __cpuinit uv_heartbeat_enable(int cpu)
529{
530 while (!uv_cpu_hub_info(cpu)->scir.enabled) {
531 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
532
533 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
534 setup_timer(timer, uv_heartbeat, cpu);
535 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
536 add_timer_on(timer, cpu);
537 uv_cpu_hub_info(cpu)->scir.enabled = 1;
538
539 /* also ensure that boot cpu is enabled */
540 cpu = 0;
541 }
542}
543
544#ifdef CONFIG_HOTPLUG_CPU
545static void __cpuinit uv_heartbeat_disable(int cpu)
546{
547 if (uv_cpu_hub_info(cpu)->scir.enabled) {
548 uv_cpu_hub_info(cpu)->scir.enabled = 0;
549 del_timer(&uv_cpu_hub_info(cpu)->scir.timer);
550 }
551 uv_set_cpu_scir_bits(cpu, 0xff);
552}
553
554/*
555 * cpu hotplug notifier
556 */
557static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self,
558 unsigned long action, void *hcpu)
559{
560 long cpu = (long)hcpu;
561
562 switch (action) {
563 case CPU_ONLINE:
564 uv_heartbeat_enable(cpu);
565 break;
566 case CPU_DOWN_PREPARE:
567 uv_heartbeat_disable(cpu);
568 break;
569 default:
570 break;
571 }
572 return NOTIFY_OK;
573}
574
575static __init void uv_scir_register_cpu_notifier(void)
576{
577 hotcpu_notifier(uv_scir_cpu_notify, 0);
578}
579
580#else /* !CONFIG_HOTPLUG_CPU */
581
582static __init void uv_scir_register_cpu_notifier(void)
583{
584}
585
586static __init int uv_init_heartbeat(void)
587{
588 int cpu;
589
590 if (is_uv_system())
591 for_each_online_cpu(cpu)
592 uv_heartbeat_enable(cpu);
593 return 0;
594}
595
596late_initcall(uv_init_heartbeat);
597
598#endif /* !CONFIG_HOTPLUG_CPU */
599
600/* Direct Legacy VGA I/O traffic to designated IOH */
601int uv_set_vga_state(struct pci_dev *pdev, bool decode,
602 unsigned int command_bits, bool change_bridge)
603{
604 int domain, bus, rc;
605
606 PR_DEVEL("devfn %x decode %d cmd %x chg_brdg %d\n",
607 pdev->devfn, decode, command_bits, change_bridge);
608
609 if (!change_bridge)
610 return 0;
611
612 if ((command_bits & PCI_COMMAND_IO) == 0)
613 return 0;
614
615 domain = pci_domain_nr(pdev->bus);
616 bus = pdev->bus->number;
617
618 rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
619 PR_DEVEL("vga decode %d %x:%x, rc: %d\n", decode, domain, bus, rc);
620
621 return rc;
622}
623
624/*
625 * Called on each cpu to initialize the per_cpu UV data area.
626 * FIXME: hotplug not supported yet
627 */
628void __cpuinit uv_cpu_init(void)
629{
630 /* CPU 0 initilization will be done via uv_system_init. */
631 if (!uv_blade_info)
632 return;
633
634 uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
635
636 if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
637 set_x2apic_extra_bits(uv_hub_info->pnode);
638}
639
640/*
641 * When NMI is received, print a stack trace.
642 */
643int uv_handle_nmi(struct notifier_block *self, unsigned long reason, void *data)
644{
645 if (reason != DIE_NMIUNKNOWN)
646 return NOTIFY_OK;
647
648 if (in_crash_kexec)
649 /* do nothing if entering the crash kernel */
650 return NOTIFY_OK;
651 /*
652 * Use a lock so only one cpu prints at a time
653 * to prevent intermixed output.
654 */
655 spin_lock(&uv_nmi_lock);
656 pr_info("NMI stack dump cpu %u:\n", smp_processor_id());
657 dump_stack();
658 spin_unlock(&uv_nmi_lock);
659
660 return NOTIFY_STOP;
661}
662
663static struct notifier_block uv_dump_stack_nmi_nb = {
664 .notifier_call = uv_handle_nmi
665};
666
667void uv_register_nmi_notifier(void)
668{
669 if (register_die_notifier(&uv_dump_stack_nmi_nb))
670 printk(KERN_WARNING "UV NMI handler failed to register\n");
671}
672
673void uv_nmi_init(void)
674{
675 unsigned int value;
676
677 /*
678 * Unmask NMI on all cpus
679 */
680 value = apic_read(APIC_LVT1) | APIC_DM_NMI;
681 value &= ~APIC_LVT_MASKED;
682 apic_write(APIC_LVT1, value);
683}
684
685void __init uv_system_init(void)
686{
687 union uvh_rh_gam_config_mmr_u m_n_config;
688 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
689 union uvh_node_id_u node_id;
690 unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
691 int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val, n_io;
692 int gnode_extra, max_pnode = 0;
693 unsigned long mmr_base, present, paddr;
694 unsigned short pnode_mask, pnode_io_mask;
695
696 map_low_mmrs();
697
698 m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR );
699 m_val = m_n_config.s.m_skt;
700 n_val = m_n_config.s.n_skt;
701 mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
702 n_io = mmioh.s.n_io;
703 mmr_base =
704 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
705 ~UV_MMR_ENABLE;
706 pnode_mask = (1 << n_val) - 1;
707 pnode_io_mask = (1 << n_io) - 1;
708
709 node_id.v = uv_read_local_mmr(UVH_NODE_ID);
710 gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1;
711 gnode_upper = ((unsigned long)gnode_extra << m_val);
712 printk(KERN_INFO "UV: N %d, M %d, N_IO: %d, gnode_upper 0x%lx, gnode_extra 0x%x, pnode_mask 0x%x, pnode_io_mask 0x%x\n",
713 n_val, m_val, n_io, gnode_upper, gnode_extra, pnode_mask, pnode_io_mask);
714
715 printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
716
717 for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
718 uv_possible_blades +=
719 hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
720 printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
721
722 bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
723 uv_blade_info = kmalloc(bytes, GFP_KERNEL);
724 BUG_ON(!uv_blade_info);
725 for (blade = 0; blade < uv_num_possible_blades(); blade++)
726 uv_blade_info[blade].memory_nid = -1;
727
728 get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
729
730 bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
731 uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
732 BUG_ON(!uv_node_to_blade);
733 memset(uv_node_to_blade, 255, bytes);
734
735 bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
736 uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
737 BUG_ON(!uv_cpu_to_blade);
738 memset(uv_cpu_to_blade, 255, bytes);
739
740 blade = 0;
741 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
742 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
743 for (j = 0; j < 64; j++) {
744 if (!test_bit(j, &present))
745 continue;
746 pnode = (i * 64 + j) & pnode_mask;
747 uv_blade_info[blade].pnode = pnode;
748 uv_blade_info[blade].nr_possible_cpus = 0;
749 uv_blade_info[blade].nr_online_cpus = 0;
750 max_pnode = max(pnode, max_pnode);
751 blade++;
752 }
753 }
754
755 uv_bios_init();
756 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id,
757 &sn_region_size, &system_serial_number);
758 uv_rtc_init();
759
760 for_each_present_cpu(cpu) {
761 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
762
763 nid = cpu_to_node(cpu);
764 /*
765 * apic_pnode_shift must be set before calling uv_apicid_to_pnode();
766 */
767 uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask;
768 uv_cpu_hub_info(cpu)->apic_pnode_shift = uvh_apicid.s.pnode_shift;
769 pnode = uv_apicid_to_pnode(apicid);
770 blade = boot_pnode_to_blade(pnode);
771 lcpu = uv_blade_info[blade].nr_possible_cpus;
772 uv_blade_info[blade].nr_possible_cpus++;
773
774 /* Any node on the blade, else will contain -1. */
775 uv_blade_info[blade].memory_nid = nid;
776
777 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
778 uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size;
779 uv_cpu_hub_info(cpu)->m_val = m_val;
780 uv_cpu_hub_info(cpu)->n_val = n_val;
781 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
782 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
783 uv_cpu_hub_info(cpu)->pnode = pnode;
784 uv_cpu_hub_info(cpu)->gpa_mask = (1UL << (m_val + n_val)) - 1;
785 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
786 uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra;
787 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
788 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
789 uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid);
790 uv_node_to_blade[nid] = blade;
791 uv_cpu_to_blade[cpu] = blade;
792 }
793
794 /* Add blade/pnode info for nodes without cpus */
795 for_each_online_node(nid) {
796 if (uv_node_to_blade[nid] >= 0)
797 continue;
798 paddr = node_start_pfn(nid) << PAGE_SHIFT;
799 paddr = uv_soc_phys_ram_to_gpa(paddr);
800 pnode = (paddr >> m_val) & pnode_mask;
801 blade = boot_pnode_to_blade(pnode);
802 uv_node_to_blade[nid] = blade;
803 }
804
805 map_gru_high(max_pnode);
806 map_mmr_high(max_pnode);
807 map_mmioh_high(max_pnode & pnode_io_mask);
808
809 uv_cpu_init();
810 uv_scir_register_cpu_notifier();
811 uv_register_nmi_notifier();
812 proc_mkdir("sgi_uv", NULL);
813
814 /* register Legacy VGA I/O redirection handler */
815 pci_register_set_vga_state(uv_set_vga_state);
816
817 /*
818 * For a kdump kernel the reset must be BOOT_ACPI, not BOOT_EFI, as
819 * EFI is not enabled in the kdump kernel.
820 */
821 if (is_kdump_kernel())
822 reboot_type = BOOT_ACPI;
823}
Linux kernel - Deliverables
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