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KVM: x86 emulator: handle "far address" source operand
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
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1/******************************************************************************
2 * emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
9 * privileged instructions:
10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22#ifndef __KERNEL__
23#include <stdio.h>
24#include <stdint.h>
25#include <public/xen.h>
26#define DPRINTF(_f, _a ...) printf(_f , ## _a)
27#else
28#include <linux/kvm_host.h>
29#include "kvm_cache_regs.h"
30#define DPRINTF(x...) do {} while (0)
31#endif
32#include <linux/module.h>
33#include <asm/kvm_emulate.h>
34
35#include "x86.h"
36#include "tss.h"
37
38/*
39 * Opcode effective-address decode tables.
40 * Note that we only emulate instructions that have at least one memory
41 * operand (excluding implicit stack references). We assume that stack
42 * references and instruction fetches will never occur in special memory
43 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
44 * not be handled.
45 */
46
47/* Operand sizes: 8-bit operands or specified/overridden size. */
48#define ByteOp (1<<0) /* 8-bit operands. */
49/* Destination operand type. */
50#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
51#define DstReg (2<<1) /* Register operand. */
52#define DstMem (3<<1) /* Memory operand. */
53#define DstAcc (4<<1) /* Destination Accumulator */
54#define DstDI (5<<1) /* Destination is in ES:(E)DI */
55#define DstMem64 (6<<1) /* 64bit memory operand */
56#define DstMask (7<<1)
57/* Source operand type. */
58#define SrcNone (0<<4) /* No source operand. */
59#define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
60#define SrcReg (1<<4) /* Register operand. */
61#define SrcMem (2<<4) /* Memory operand. */
62#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
63#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
64#define SrcImm (5<<4) /* Immediate operand. */
65#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
66#define SrcOne (7<<4) /* Implied '1' */
67#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
68#define SrcImmU (9<<4) /* Immediate operand, unsigned */
69#define SrcSI (0xa<<4) /* Source is in the DS:RSI */
70#define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
71#define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
72#define SrcMask (0xf<<4)
73/* Generic ModRM decode. */
74#define ModRM (1<<8)
75/* Destination is only written; never read. */
76#define Mov (1<<9)
77#define BitOp (1<<10)
78#define MemAbs (1<<11) /* Memory operand is absolute displacement */
79#define String (1<<12) /* String instruction (rep capable) */
80#define Stack (1<<13) /* Stack instruction (push/pop) */
81#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
82#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
83#define GroupMask 0xff /* Group number stored in bits 0:7 */
84/* Misc flags */
85#define Lock (1<<26) /* lock prefix is allowed for the instruction */
86#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
87#define No64 (1<<28)
88/* Source 2 operand type */
89#define Src2None (0<<29)
90#define Src2CL (1<<29)
91#define Src2ImmByte (2<<29)
92#define Src2One (3<<29)
93#define Src2Mask (7<<29)
94
95enum {
96 Group1_80, Group1_81, Group1_82, Group1_83,
97 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
98 Group8, Group9,
99};
100
101static u32 opcode_table[256] = {
102 /* 0x00 - 0x07 */
103 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
104 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
105 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
106 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
107 /* 0x08 - 0x0F */
108 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
109 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
110 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
111 ImplicitOps | Stack | No64, 0,
112 /* 0x10 - 0x17 */
113 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
114 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
115 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
116 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
117 /* 0x18 - 0x1F */
118 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
119 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
120 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
121 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
122 /* 0x20 - 0x27 */
123 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
124 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
125 DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0,
126 /* 0x28 - 0x2F */
127 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
128 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
129 0, 0, 0, 0,
130 /* 0x30 - 0x37 */
131 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
132 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
133 0, 0, 0, 0,
134 /* 0x38 - 0x3F */
135 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
136 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
137 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
138 0, 0,
139 /* 0x40 - 0x47 */
140 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
141 /* 0x48 - 0x4F */
142 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
143 /* 0x50 - 0x57 */
144 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
145 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
146 /* 0x58 - 0x5F */
147 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
148 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
149 /* 0x60 - 0x67 */
150 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
151 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
152 0, 0, 0, 0,
153 /* 0x68 - 0x6F */
154 SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0,
155 DstDI | ByteOp | Mov | String, DstDI | Mov | String, /* insb, insw/insd */
156 SrcSI | ByteOp | ImplicitOps | String, SrcSI | ImplicitOps | String, /* outsb, outsw/outsd */
157 /* 0x70 - 0x77 */
158 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
159 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
160 /* 0x78 - 0x7F */
161 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
162 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
163 /* 0x80 - 0x87 */
164 Group | Group1_80, Group | Group1_81,
165 Group | Group1_82, Group | Group1_83,
166 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
167 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
168 /* 0x88 - 0x8F */
169 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
170 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
171 DstMem | SrcReg | ModRM | Mov, ModRM | DstReg,
172 ImplicitOps | SrcMem | ModRM, Group | Group1A,
173 /* 0x90 - 0x97 */
174 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
175 /* 0x98 - 0x9F */
176 0, 0, SrcImmFAddr | No64, 0,
177 ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
178 /* 0xA0 - 0xA7 */
179 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
180 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
181 ByteOp | SrcSI | DstDI | Mov | String, SrcSI | DstDI | Mov | String,
182 ByteOp | SrcSI | DstDI | String, SrcSI | DstDI | String,
183 /* 0xA8 - 0xAF */
184 0, 0, ByteOp | DstDI | Mov | String, DstDI | Mov | String,
185 ByteOp | SrcSI | DstAcc | Mov | String, SrcSI | DstAcc | Mov | String,
186 ByteOp | DstDI | String, DstDI | String,
187 /* 0xB0 - 0xB7 */
188 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
189 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
190 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
191 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
192 /* 0xB8 - 0xBF */
193 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
194 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
195 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
196 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
197 /* 0xC0 - 0xC7 */
198 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
199 0, ImplicitOps | Stack, 0, 0,
200 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
201 /* 0xC8 - 0xCF */
202 0, 0, 0, ImplicitOps | Stack,
203 ImplicitOps, SrcImmByte, ImplicitOps | No64, ImplicitOps,
204 /* 0xD0 - 0xD7 */
205 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
206 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
207 0, 0, 0, 0,
208 /* 0xD8 - 0xDF */
209 0, 0, 0, 0, 0, 0, 0, 0,
210 /* 0xE0 - 0xE7 */
211 0, 0, 0, 0,
212 ByteOp | SrcImmUByte | DstAcc, SrcImmUByte | DstAcc,
213 ByteOp | SrcImmUByte | DstAcc, SrcImmUByte | DstAcc,
214 /* 0xE8 - 0xEF */
215 SrcImm | Stack, SrcImm | ImplicitOps,
216 SrcImmFAddr | No64, SrcImmByte | ImplicitOps,
217 SrcNone | ByteOp | DstAcc, SrcNone | DstAcc,
218 SrcNone | ByteOp | DstAcc, SrcNone | DstAcc,
219 /* 0xF0 - 0xF7 */
220 0, 0, 0, 0,
221 ImplicitOps | Priv, ImplicitOps, Group | Group3_Byte, Group | Group3,
222 /* 0xF8 - 0xFF */
223 ImplicitOps, 0, ImplicitOps, ImplicitOps,
224 ImplicitOps, ImplicitOps, Group | Group4, Group | Group5,
225};
226
227static u32 twobyte_table[256] = {
228 /* 0x00 - 0x0F */
229 0, Group | GroupDual | Group7, 0, 0,
230 0, ImplicitOps, ImplicitOps | Priv, 0,
231 ImplicitOps | Priv, ImplicitOps | Priv, 0, 0,
232 0, ImplicitOps | ModRM, 0, 0,
233 /* 0x10 - 0x1F */
234 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
235 /* 0x20 - 0x2F */
236 ModRM | ImplicitOps | Priv, ModRM | Priv,
237 ModRM | ImplicitOps | Priv, ModRM | Priv,
238 0, 0, 0, 0,
239 0, 0, 0, 0, 0, 0, 0, 0,
240 /* 0x30 - 0x3F */
241 ImplicitOps | Priv, 0, ImplicitOps | Priv, 0,
242 ImplicitOps, ImplicitOps | Priv, 0, 0,
243 0, 0, 0, 0, 0, 0, 0, 0,
244 /* 0x40 - 0x47 */
245 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
246 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
247 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
248 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
249 /* 0x48 - 0x4F */
250 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
251 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
252 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
253 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
254 /* 0x50 - 0x5F */
255 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
256 /* 0x60 - 0x6F */
257 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
258 /* 0x70 - 0x7F */
259 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
260 /* 0x80 - 0x8F */
261 SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm,
262 SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm,
263 /* 0x90 - 0x9F */
264 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
265 /* 0xA0 - 0xA7 */
266 ImplicitOps | Stack, ImplicitOps | Stack,
267 0, DstMem | SrcReg | ModRM | BitOp,
268 DstMem | SrcReg | Src2ImmByte | ModRM,
269 DstMem | SrcReg | Src2CL | ModRM, 0, 0,
270 /* 0xA8 - 0xAF */
271 ImplicitOps | Stack, ImplicitOps | Stack,
272 0, DstMem | SrcReg | ModRM | BitOp | Lock,
273 DstMem | SrcReg | Src2ImmByte | ModRM,
274 DstMem | SrcReg | Src2CL | ModRM,
275 ModRM, 0,
276 /* 0xB0 - 0xB7 */
277 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
278 0, DstMem | SrcReg | ModRM | BitOp | Lock,
279 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
280 DstReg | SrcMem16 | ModRM | Mov,
281 /* 0xB8 - 0xBF */
282 0, 0,
283 Group | Group8, DstMem | SrcReg | ModRM | BitOp | Lock,
284 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
285 DstReg | SrcMem16 | ModRM | Mov,
286 /* 0xC0 - 0xCF */
287 0, 0, 0, DstMem | SrcReg | ModRM | Mov,
288 0, 0, 0, Group | GroupDual | Group9,
289 0, 0, 0, 0, 0, 0, 0, 0,
290 /* 0xD0 - 0xDF */
291 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
292 /* 0xE0 - 0xEF */
293 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
294 /* 0xF0 - 0xFF */
295 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
296};
297
298static u32 group_table[] = {
299 [Group1_80*8] =
300 ByteOp | DstMem | SrcImm | ModRM | Lock,
301 ByteOp | DstMem | SrcImm | ModRM | Lock,
302 ByteOp | DstMem | SrcImm | ModRM | Lock,
303 ByteOp | DstMem | SrcImm | ModRM | Lock,
304 ByteOp | DstMem | SrcImm | ModRM | Lock,
305 ByteOp | DstMem | SrcImm | ModRM | Lock,
306 ByteOp | DstMem | SrcImm | ModRM | Lock,
307 ByteOp | DstMem | SrcImm | ModRM,
308 [Group1_81*8] =
309 DstMem | SrcImm | ModRM | Lock,
310 DstMem | SrcImm | ModRM | Lock,
311 DstMem | SrcImm | ModRM | Lock,
312 DstMem | SrcImm | ModRM | Lock,
313 DstMem | SrcImm | ModRM | Lock,
314 DstMem | SrcImm | ModRM | Lock,
315 DstMem | SrcImm | ModRM | Lock,
316 DstMem | SrcImm | ModRM,
317 [Group1_82*8] =
318 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
319 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
320 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
321 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
322 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
323 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
324 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
325 ByteOp | DstMem | SrcImm | ModRM | No64,
326 [Group1_83*8] =
327 DstMem | SrcImmByte | ModRM | Lock,
328 DstMem | SrcImmByte | ModRM | Lock,
329 DstMem | SrcImmByte | ModRM | Lock,
330 DstMem | SrcImmByte | ModRM | Lock,
331 DstMem | SrcImmByte | ModRM | Lock,
332 DstMem | SrcImmByte | ModRM | Lock,
333 DstMem | SrcImmByte | ModRM | Lock,
334 DstMem | SrcImmByte | ModRM,
335 [Group1A*8] =
336 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
337 [Group3_Byte*8] =
338 ByteOp | SrcImm | DstMem | ModRM, 0,
339 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
340 0, 0, 0, 0,
341 [Group3*8] =
342 DstMem | SrcImm | ModRM, 0,
343 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
344 0, 0, 0, 0,
345 [Group4*8] =
346 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
347 0, 0, 0, 0, 0, 0,
348 [Group5*8] =
349 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
350 SrcMem | ModRM | Stack, 0,
351 SrcMem | ModRM | Stack, SrcMemFAddr | ModRM | ImplicitOps,
352 SrcMem | ModRM | Stack, 0,
353 [Group7*8] =
354 0, 0, ModRM | SrcMem | Priv, ModRM | SrcMem | Priv,
355 SrcNone | ModRM | DstMem | Mov, 0,
356 SrcMem16 | ModRM | Mov | Priv, SrcMem | ModRM | ByteOp | Priv,
357 [Group8*8] =
358 0, 0, 0, 0,
359 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM | Lock,
360 DstMem | SrcImmByte | ModRM | Lock, DstMem | SrcImmByte | ModRM | Lock,
361 [Group9*8] =
362 0, DstMem64 | ModRM | Lock, 0, 0, 0, 0, 0, 0,
363};
364
365static u32 group2_table[] = {
366 [Group7*8] =
367 SrcNone | ModRM | Priv, 0, 0, SrcNone | ModRM | Priv,
368 SrcNone | ModRM | DstMem | Mov, 0,
369 SrcMem16 | ModRM | Mov | Priv, 0,
370 [Group9*8] =
371 0, 0, 0, 0, 0, 0, 0, 0,
372};
373
374/* EFLAGS bit definitions. */
375#define EFLG_ID (1<<21)
376#define EFLG_VIP (1<<20)
377#define EFLG_VIF (1<<19)
378#define EFLG_AC (1<<18)
379#define EFLG_VM (1<<17)
380#define EFLG_RF (1<<16)
381#define EFLG_IOPL (3<<12)
382#define EFLG_NT (1<<14)
383#define EFLG_OF (1<<11)
384#define EFLG_DF (1<<10)
385#define EFLG_IF (1<<9)
386#define EFLG_TF (1<<8)
387#define EFLG_SF (1<<7)
388#define EFLG_ZF (1<<6)
389#define EFLG_AF (1<<4)
390#define EFLG_PF (1<<2)
391#define EFLG_CF (1<<0)
392
393/*
394 * Instruction emulation:
395 * Most instructions are emulated directly via a fragment of inline assembly
396 * code. This allows us to save/restore EFLAGS and thus very easily pick up
397 * any modified flags.
398 */
399
400#if defined(CONFIG_X86_64)
401#define _LO32 "k" /* force 32-bit operand */
402#define _STK "%%rsp" /* stack pointer */
403#elif defined(__i386__)
404#define _LO32 "" /* force 32-bit operand */
405#define _STK "%%esp" /* stack pointer */
406#endif
407
408/*
409 * These EFLAGS bits are restored from saved value during emulation, and
410 * any changes are written back to the saved value after emulation.
411 */
412#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
413
414/* Before executing instruction: restore necessary bits in EFLAGS. */
415#define _PRE_EFLAGS(_sav, _msk, _tmp) \
416 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
417 "movl %"_sav",%"_LO32 _tmp"; " \
418 "push %"_tmp"; " \
419 "push %"_tmp"; " \
420 "movl %"_msk",%"_LO32 _tmp"; " \
421 "andl %"_LO32 _tmp",("_STK"); " \
422 "pushf; " \
423 "notl %"_LO32 _tmp"; " \
424 "andl %"_LO32 _tmp",("_STK"); " \
425 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
426 "pop %"_tmp"; " \
427 "orl %"_LO32 _tmp",("_STK"); " \
428 "popf; " \
429 "pop %"_sav"; "
430
431/* After executing instruction: write-back necessary bits in EFLAGS. */
432#define _POST_EFLAGS(_sav, _msk, _tmp) \
433 /* _sav |= EFLAGS & _msk; */ \
434 "pushf; " \
435 "pop %"_tmp"; " \
436 "andl %"_msk",%"_LO32 _tmp"; " \
437 "orl %"_LO32 _tmp",%"_sav"; "
438
439#ifdef CONFIG_X86_64
440#define ON64(x) x
441#else
442#define ON64(x)
443#endif
444
445#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \
446 do { \
447 __asm__ __volatile__ ( \
448 _PRE_EFLAGS("0", "4", "2") \
449 _op _suffix " %"_x"3,%1; " \
450 _POST_EFLAGS("0", "4", "2") \
451 : "=m" (_eflags), "=m" ((_dst).val), \
452 "=&r" (_tmp) \
453 : _y ((_src).val), "i" (EFLAGS_MASK)); \
454 } while (0)
455
456
457/* Raw emulation: instruction has two explicit operands. */
458#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
459 do { \
460 unsigned long _tmp; \
461 \
462 switch ((_dst).bytes) { \
463 case 2: \
464 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \
465 break; \
466 case 4: \
467 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \
468 break; \
469 case 8: \
470 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \
471 break; \
472 } \
473 } while (0)
474
475#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
476 do { \
477 unsigned long _tmp; \
478 switch ((_dst).bytes) { \
479 case 1: \
480 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \
481 break; \
482 default: \
483 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
484 _wx, _wy, _lx, _ly, _qx, _qy); \
485 break; \
486 } \
487 } while (0)
488
489/* Source operand is byte-sized and may be restricted to just %cl. */
490#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
491 __emulate_2op(_op, _src, _dst, _eflags, \
492 "b", "c", "b", "c", "b", "c", "b", "c")
493
494/* Source operand is byte, word, long or quad sized. */
495#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
496 __emulate_2op(_op, _src, _dst, _eflags, \
497 "b", "q", "w", "r", _LO32, "r", "", "r")
498
499/* Source operand is word, long or quad sized. */
500#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
501 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
502 "w", "r", _LO32, "r", "", "r")
503
504/* Instruction has three operands and one operand is stored in ECX register */
505#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
506 do { \
507 unsigned long _tmp; \
508 _type _clv = (_cl).val; \
509 _type _srcv = (_src).val; \
510 _type _dstv = (_dst).val; \
511 \
512 __asm__ __volatile__ ( \
513 _PRE_EFLAGS("0", "5", "2") \
514 _op _suffix " %4,%1 \n" \
515 _POST_EFLAGS("0", "5", "2") \
516 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
517 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
518 ); \
519 \
520 (_cl).val = (unsigned long) _clv; \
521 (_src).val = (unsigned long) _srcv; \
522 (_dst).val = (unsigned long) _dstv; \
523 } while (0)
524
525#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
526 do { \
527 switch ((_dst).bytes) { \
528 case 2: \
529 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
530 "w", unsigned short); \
531 break; \
532 case 4: \
533 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
534 "l", unsigned int); \
535 break; \
536 case 8: \
537 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
538 "q", unsigned long)); \
539 break; \
540 } \
541 } while (0)
542
543#define __emulate_1op(_op, _dst, _eflags, _suffix) \
544 do { \
545 unsigned long _tmp; \
546 \
547 __asm__ __volatile__ ( \
548 _PRE_EFLAGS("0", "3", "2") \
549 _op _suffix " %1; " \
550 _POST_EFLAGS("0", "3", "2") \
551 : "=m" (_eflags), "+m" ((_dst).val), \
552 "=&r" (_tmp) \
553 : "i" (EFLAGS_MASK)); \
554 } while (0)
555
556/* Instruction has only one explicit operand (no source operand). */
557#define emulate_1op(_op, _dst, _eflags) \
558 do { \
559 switch ((_dst).bytes) { \
560 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
561 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
562 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
563 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
564 } \
565 } while (0)
566
567/* Fetch next part of the instruction being emulated. */
568#define insn_fetch(_type, _size, _eip) \
569({ unsigned long _x; \
570 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
571 if (rc != X86EMUL_CONTINUE) \
572 goto done; \
573 (_eip) += (_size); \
574 (_type)_x; \
575})
576
577#define insn_fetch_arr(_arr, _size, _eip) \
578({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
579 if (rc != X86EMUL_CONTINUE) \
580 goto done; \
581 (_eip) += (_size); \
582})
583
584static inline unsigned long ad_mask(struct decode_cache *c)
585{
586 return (1UL << (c->ad_bytes << 3)) - 1;
587}
588
589/* Access/update address held in a register, based on addressing mode. */
590static inline unsigned long
591address_mask(struct decode_cache *c, unsigned long reg)
592{
593 if (c->ad_bytes == sizeof(unsigned long))
594 return reg;
595 else
596 return reg & ad_mask(c);
597}
598
599static inline unsigned long
600register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
601{
602 return base + address_mask(c, reg);
603}
604
605static inline void
606register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
607{
608 if (c->ad_bytes == sizeof(unsigned long))
609 *reg += inc;
610 else
611 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
612}
613
614static inline void jmp_rel(struct decode_cache *c, int rel)
615{
616 register_address_increment(c, &c->eip, rel);
617}
618
619static void set_seg_override(struct decode_cache *c, int seg)
620{
621 c->has_seg_override = true;
622 c->seg_override = seg;
623}
624
625static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
626{
627 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
628 return 0;
629
630 return kvm_x86_ops->get_segment_base(ctxt->vcpu, seg);
631}
632
633static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
634 struct decode_cache *c)
635{
636 if (!c->has_seg_override)
637 return 0;
638
639 return seg_base(ctxt, c->seg_override);
640}
641
642static unsigned long es_base(struct x86_emulate_ctxt *ctxt)
643{
644 return seg_base(ctxt, VCPU_SREG_ES);
645}
646
647static unsigned long ss_base(struct x86_emulate_ctxt *ctxt)
648{
649 return seg_base(ctxt, VCPU_SREG_SS);
650}
651
652static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
653 struct x86_emulate_ops *ops,
654 unsigned long eip, u8 *dest)
655{
656 struct fetch_cache *fc = &ctxt->decode.fetch;
657 int rc;
658 int size, cur_size;
659
660 if (eip == fc->end) {
661 cur_size = fc->end - fc->start;
662 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
663 rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size,
664 size, ctxt->vcpu, NULL);
665 if (rc != X86EMUL_CONTINUE)
666 return rc;
667 fc->end += size;
668 }
669 *dest = fc->data[eip - fc->start];
670 return X86EMUL_CONTINUE;
671}
672
673static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
674 struct x86_emulate_ops *ops,
675 unsigned long eip, void *dest, unsigned size)
676{
677 int rc;
678
679 /* x86 instructions are limited to 15 bytes. */
680 if (eip + size - ctxt->eip > 15)
681 return X86EMUL_UNHANDLEABLE;
682 while (size--) {
683 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
684 if (rc != X86EMUL_CONTINUE)
685 return rc;
686 }
687 return X86EMUL_CONTINUE;
688}
689
690/*
691 * Given the 'reg' portion of a ModRM byte, and a register block, return a
692 * pointer into the block that addresses the relevant register.
693 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
694 */
695static void *decode_register(u8 modrm_reg, unsigned long *regs,
696 int highbyte_regs)
697{
698 void *p;
699
700 p = &regs[modrm_reg];
701 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
702 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
703 return p;
704}
705
706static int read_descriptor(struct x86_emulate_ctxt *ctxt,
707 struct x86_emulate_ops *ops,
708 void *ptr,
709 u16 *size, unsigned long *address, int op_bytes)
710{
711 int rc;
712
713 if (op_bytes == 2)
714 op_bytes = 3;
715 *address = 0;
716 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
717 ctxt->vcpu, NULL);
718 if (rc != X86EMUL_CONTINUE)
719 return rc;
720 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
721 ctxt->vcpu, NULL);
722 return rc;
723}
724
725static int test_cc(unsigned int condition, unsigned int flags)
726{
727 int rc = 0;
728
729 switch ((condition & 15) >> 1) {
730 case 0: /* o */
731 rc |= (flags & EFLG_OF);
732 break;
733 case 1: /* b/c/nae */
734 rc |= (flags & EFLG_CF);
735 break;
736 case 2: /* z/e */
737 rc |= (flags & EFLG_ZF);
738 break;
739 case 3: /* be/na */
740 rc |= (flags & (EFLG_CF|EFLG_ZF));
741 break;
742 case 4: /* s */
743 rc |= (flags & EFLG_SF);
744 break;
745 case 5: /* p/pe */
746 rc |= (flags & EFLG_PF);
747 break;
748 case 7: /* le/ng */
749 rc |= (flags & EFLG_ZF);
750 /* fall through */
751 case 6: /* l/nge */
752 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
753 break;
754 }
755
756 /* Odd condition identifiers (lsb == 1) have inverted sense. */
757 return (!!rc ^ (condition & 1));
758}
759
760static void decode_register_operand(struct operand *op,
761 struct decode_cache *c,
762 int inhibit_bytereg)
763{
764 unsigned reg = c->modrm_reg;
765 int highbyte_regs = c->rex_prefix == 0;
766
767 if (!(c->d & ModRM))
768 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
769 op->type = OP_REG;
770 if ((c->d & ByteOp) && !inhibit_bytereg) {
771 op->ptr = decode_register(reg, c->regs, highbyte_regs);
772 op->val = *(u8 *)op->ptr;
773 op->bytes = 1;
774 } else {
775 op->ptr = decode_register(reg, c->regs, 0);
776 op->bytes = c->op_bytes;
777 switch (op->bytes) {
778 case 2:
779 op->val = *(u16 *)op->ptr;
780 break;
781 case 4:
782 op->val = *(u32 *)op->ptr;
783 break;
784 case 8:
785 op->val = *(u64 *) op->ptr;
786 break;
787 }
788 }
789 op->orig_val = op->val;
790}
791
792static int decode_modrm(struct x86_emulate_ctxt *ctxt,
793 struct x86_emulate_ops *ops)
794{
795 struct decode_cache *c = &ctxt->decode;
796 u8 sib;
797 int index_reg = 0, base_reg = 0, scale;
798 int rc = X86EMUL_CONTINUE;
799
800 if (c->rex_prefix) {
801 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
802 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
803 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
804 }
805
806 c->modrm = insn_fetch(u8, 1, c->eip);
807 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
808 c->modrm_reg |= (c->modrm & 0x38) >> 3;
809 c->modrm_rm |= (c->modrm & 0x07);
810 c->modrm_ea = 0;
811 c->use_modrm_ea = 1;
812
813 if (c->modrm_mod == 3) {
814 c->modrm_ptr = decode_register(c->modrm_rm,
815 c->regs, c->d & ByteOp);
816 c->modrm_val = *(unsigned long *)c->modrm_ptr;
817 return rc;
818 }
819
820 if (c->ad_bytes == 2) {
821 unsigned bx = c->regs[VCPU_REGS_RBX];
822 unsigned bp = c->regs[VCPU_REGS_RBP];
823 unsigned si = c->regs[VCPU_REGS_RSI];
824 unsigned di = c->regs[VCPU_REGS_RDI];
825
826 /* 16-bit ModR/M decode. */
827 switch (c->modrm_mod) {
828 case 0:
829 if (c->modrm_rm == 6)
830 c->modrm_ea += insn_fetch(u16, 2, c->eip);
831 break;
832 case 1:
833 c->modrm_ea += insn_fetch(s8, 1, c->eip);
834 break;
835 case 2:
836 c->modrm_ea += insn_fetch(u16, 2, c->eip);
837 break;
838 }
839 switch (c->modrm_rm) {
840 case 0:
841 c->modrm_ea += bx + si;
842 break;
843 case 1:
844 c->modrm_ea += bx + di;
845 break;
846 case 2:
847 c->modrm_ea += bp + si;
848 break;
849 case 3:
850 c->modrm_ea += bp + di;
851 break;
852 case 4:
853 c->modrm_ea += si;
854 break;
855 case 5:
856 c->modrm_ea += di;
857 break;
858 case 6:
859 if (c->modrm_mod != 0)
860 c->modrm_ea += bp;
861 break;
862 case 7:
863 c->modrm_ea += bx;
864 break;
865 }
866 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
867 (c->modrm_rm == 6 && c->modrm_mod != 0))
868 if (!c->has_seg_override)
869 set_seg_override(c, VCPU_SREG_SS);
870 c->modrm_ea = (u16)c->modrm_ea;
871 } else {
872 /* 32/64-bit ModR/M decode. */
873 if ((c->modrm_rm & 7) == 4) {
874 sib = insn_fetch(u8, 1, c->eip);
875 index_reg |= (sib >> 3) & 7;
876 base_reg |= sib & 7;
877 scale = sib >> 6;
878
879 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
880 c->modrm_ea += insn_fetch(s32, 4, c->eip);
881 else
882 c->modrm_ea += c->regs[base_reg];
883 if (index_reg != 4)
884 c->modrm_ea += c->regs[index_reg] << scale;
885 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
886 if (ctxt->mode == X86EMUL_MODE_PROT64)
887 c->rip_relative = 1;
888 } else
889 c->modrm_ea += c->regs[c->modrm_rm];
890 switch (c->modrm_mod) {
891 case 0:
892 if (c->modrm_rm == 5)
893 c->modrm_ea += insn_fetch(s32, 4, c->eip);
894 break;
895 case 1:
896 c->modrm_ea += insn_fetch(s8, 1, c->eip);
897 break;
898 case 2:
899 c->modrm_ea += insn_fetch(s32, 4, c->eip);
900 break;
901 }
902 }
903done:
904 return rc;
905}
906
907static int decode_abs(struct x86_emulate_ctxt *ctxt,
908 struct x86_emulate_ops *ops)
909{
910 struct decode_cache *c = &ctxt->decode;
911 int rc = X86EMUL_CONTINUE;
912
913 switch (c->ad_bytes) {
914 case 2:
915 c->modrm_ea = insn_fetch(u16, 2, c->eip);
916 break;
917 case 4:
918 c->modrm_ea = insn_fetch(u32, 4, c->eip);
919 break;
920 case 8:
921 c->modrm_ea = insn_fetch(u64, 8, c->eip);
922 break;
923 }
924done:
925 return rc;
926}
927
928int
929x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
930{
931 struct decode_cache *c = &ctxt->decode;
932 int rc = X86EMUL_CONTINUE;
933 int mode = ctxt->mode;
934 int def_op_bytes, def_ad_bytes, group;
935
936
937 /* we cannot decode insn before we complete previous rep insn */
938 WARN_ON(ctxt->restart);
939
940 /* Shadow copy of register state. Committed on successful emulation. */
941 memset(c, 0, sizeof(struct decode_cache));
942 c->eip = ctxt->eip;
943 c->fetch.start = c->fetch.end = c->eip;
944 ctxt->cs_base = seg_base(ctxt, VCPU_SREG_CS);
945 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
946
947 switch (mode) {
948 case X86EMUL_MODE_REAL:
949 case X86EMUL_MODE_VM86:
950 case X86EMUL_MODE_PROT16:
951 def_op_bytes = def_ad_bytes = 2;
952 break;
953 case X86EMUL_MODE_PROT32:
954 def_op_bytes = def_ad_bytes = 4;
955 break;
956#ifdef CONFIG_X86_64
957 case X86EMUL_MODE_PROT64:
958 def_op_bytes = 4;
959 def_ad_bytes = 8;
960 break;
961#endif
962 default:
963 return -1;
964 }
965
966 c->op_bytes = def_op_bytes;
967 c->ad_bytes = def_ad_bytes;
968
969 /* Legacy prefixes. */
970 for (;;) {
971 switch (c->b = insn_fetch(u8, 1, c->eip)) {
972 case 0x66: /* operand-size override */
973 /* switch between 2/4 bytes */
974 c->op_bytes = def_op_bytes ^ 6;
975 break;
976 case 0x67: /* address-size override */
977 if (mode == X86EMUL_MODE_PROT64)
978 /* switch between 4/8 bytes */
979 c->ad_bytes = def_ad_bytes ^ 12;
980 else
981 /* switch between 2/4 bytes */
982 c->ad_bytes = def_ad_bytes ^ 6;
983 break;
984 case 0x26: /* ES override */
985 case 0x2e: /* CS override */
986 case 0x36: /* SS override */
987 case 0x3e: /* DS override */
988 set_seg_override(c, (c->b >> 3) & 3);
989 break;
990 case 0x64: /* FS override */
991 case 0x65: /* GS override */
992 set_seg_override(c, c->b & 7);
993 break;
994 case 0x40 ... 0x4f: /* REX */
995 if (mode != X86EMUL_MODE_PROT64)
996 goto done_prefixes;
997 c->rex_prefix = c->b;
998 continue;
999 case 0xf0: /* LOCK */
1000 c->lock_prefix = 1;
1001 break;
1002 case 0xf2: /* REPNE/REPNZ */
1003 c->rep_prefix = REPNE_PREFIX;
1004 break;
1005 case 0xf3: /* REP/REPE/REPZ */
1006 c->rep_prefix = REPE_PREFIX;
1007 break;
1008 default:
1009 goto done_prefixes;
1010 }
1011
1012 /* Any legacy prefix after a REX prefix nullifies its effect. */
1013
1014 c->rex_prefix = 0;
1015 }
1016
1017done_prefixes:
1018
1019 /* REX prefix. */
1020 if (c->rex_prefix)
1021 if (c->rex_prefix & 8)
1022 c->op_bytes = 8; /* REX.W */
1023
1024 /* Opcode byte(s). */
1025 c->d = opcode_table[c->b];
1026 if (c->d == 0) {
1027 /* Two-byte opcode? */
1028 if (c->b == 0x0f) {
1029 c->twobyte = 1;
1030 c->b = insn_fetch(u8, 1, c->eip);
1031 c->d = twobyte_table[c->b];
1032 }
1033 }
1034
1035 if (c->d & Group) {
1036 group = c->d & GroupMask;
1037 c->modrm = insn_fetch(u8, 1, c->eip);
1038 --c->eip;
1039
1040 group = (group << 3) + ((c->modrm >> 3) & 7);
1041 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
1042 c->d = group2_table[group];
1043 else
1044 c->d = group_table[group];
1045 }
1046
1047 /* Unrecognised? */
1048 if (c->d == 0) {
1049 DPRINTF("Cannot emulate %02x\n", c->b);
1050 return -1;
1051 }
1052
1053 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
1054 c->op_bytes = 8;
1055
1056 /* ModRM and SIB bytes. */
1057 if (c->d & ModRM)
1058 rc = decode_modrm(ctxt, ops);
1059 else if (c->d & MemAbs)
1060 rc = decode_abs(ctxt, ops);
1061 if (rc != X86EMUL_CONTINUE)
1062 goto done;
1063
1064 if (!c->has_seg_override)
1065 set_seg_override(c, VCPU_SREG_DS);
1066
1067 if (!(!c->twobyte && c->b == 0x8d))
1068 c->modrm_ea += seg_override_base(ctxt, c);
1069
1070 if (c->ad_bytes != 8)
1071 c->modrm_ea = (u32)c->modrm_ea;
1072
1073 if (c->rip_relative)
1074 c->modrm_ea += c->eip;
1075
1076 /*
1077 * Decode and fetch the source operand: register, memory
1078 * or immediate.
1079 */
1080 switch (c->d & SrcMask) {
1081 case SrcNone:
1082 break;
1083 case SrcReg:
1084 decode_register_operand(&c->src, c, 0);
1085 break;
1086 case SrcMem16:
1087 c->src.bytes = 2;
1088 goto srcmem_common;
1089 case SrcMem32:
1090 c->src.bytes = 4;
1091 goto srcmem_common;
1092 case SrcMem:
1093 c->src.bytes = (c->d & ByteOp) ? 1 :
1094 c->op_bytes;
1095 /* Don't fetch the address for invlpg: it could be unmapped. */
1096 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
1097 break;
1098 srcmem_common:
1099 /*
1100 * For instructions with a ModR/M byte, switch to register
1101 * access if Mod = 3.
1102 */
1103 if ((c->d & ModRM) && c->modrm_mod == 3) {
1104 c->src.type = OP_REG;
1105 c->src.val = c->modrm_val;
1106 c->src.ptr = c->modrm_ptr;
1107 break;
1108 }
1109 c->src.type = OP_MEM;
1110 c->src.ptr = (unsigned long *)c->modrm_ea;
1111 c->src.val = 0;
1112 break;
1113 case SrcImm:
1114 case SrcImmU:
1115 c->src.type = OP_IMM;
1116 c->src.ptr = (unsigned long *)c->eip;
1117 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1118 if (c->src.bytes == 8)
1119 c->src.bytes = 4;
1120 /* NB. Immediates are sign-extended as necessary. */
1121 switch (c->src.bytes) {
1122 case 1:
1123 c->src.val = insn_fetch(s8, 1, c->eip);
1124 break;
1125 case 2:
1126 c->src.val = insn_fetch(s16, 2, c->eip);
1127 break;
1128 case 4:
1129 c->src.val = insn_fetch(s32, 4, c->eip);
1130 break;
1131 }
1132 if ((c->d & SrcMask) == SrcImmU) {
1133 switch (c->src.bytes) {
1134 case 1:
1135 c->src.val &= 0xff;
1136 break;
1137 case 2:
1138 c->src.val &= 0xffff;
1139 break;
1140 case 4:
1141 c->src.val &= 0xffffffff;
1142 break;
1143 }
1144 }
1145 break;
1146 case SrcImmByte:
1147 case SrcImmUByte:
1148 c->src.type = OP_IMM;
1149 c->src.ptr = (unsigned long *)c->eip;
1150 c->src.bytes = 1;
1151 if ((c->d & SrcMask) == SrcImmByte)
1152 c->src.val = insn_fetch(s8, 1, c->eip);
1153 else
1154 c->src.val = insn_fetch(u8, 1, c->eip);
1155 break;
1156 case SrcOne:
1157 c->src.bytes = 1;
1158 c->src.val = 1;
1159 break;
1160 case SrcSI:
1161 c->src.type = OP_MEM;
1162 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1163 c->src.ptr = (unsigned long *)
1164 register_address(c, seg_override_base(ctxt, c),
1165 c->regs[VCPU_REGS_RSI]);
1166 c->src.val = 0;
1167 break;
1168 case SrcImmFAddr:
1169 c->src.type = OP_IMM;
1170 c->src.ptr = (unsigned long *)c->eip;
1171 c->src.bytes = c->op_bytes + 2;
1172 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
1173 break;
1174 case SrcMemFAddr:
1175 c->src.type = OP_MEM;
1176 c->src.ptr = (unsigned long *)c->modrm_ea;
1177 c->src.bytes = c->op_bytes + 2;
1178 break;
1179 }
1180
1181 /*
1182 * Decode and fetch the second source operand: register, memory
1183 * or immediate.
1184 */
1185 switch (c->d & Src2Mask) {
1186 case Src2None:
1187 break;
1188 case Src2CL:
1189 c->src2.bytes = 1;
1190 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
1191 break;
1192 case Src2ImmByte:
1193 c->src2.type = OP_IMM;
1194 c->src2.ptr = (unsigned long *)c->eip;
1195 c->src2.bytes = 1;
1196 c->src2.val = insn_fetch(u8, 1, c->eip);
1197 break;
1198 case Src2One:
1199 c->src2.bytes = 1;
1200 c->src2.val = 1;
1201 break;
1202 }
1203
1204 /* Decode and fetch the destination operand: register or memory. */
1205 switch (c->d & DstMask) {
1206 case ImplicitOps:
1207 /* Special instructions do their own operand decoding. */
1208 return 0;
1209 case DstReg:
1210 decode_register_operand(&c->dst, c,
1211 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
1212 break;
1213 case DstMem:
1214 case DstMem64:
1215 if ((c->d & ModRM) && c->modrm_mod == 3) {
1216 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1217 c->dst.type = OP_REG;
1218 c->dst.val = c->dst.orig_val = c->modrm_val;
1219 c->dst.ptr = c->modrm_ptr;
1220 break;
1221 }
1222 c->dst.type = OP_MEM;
1223 c->dst.ptr = (unsigned long *)c->modrm_ea;
1224 if ((c->d & DstMask) == DstMem64)
1225 c->dst.bytes = 8;
1226 else
1227 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1228 c->dst.val = 0;
1229 if (c->d & BitOp) {
1230 unsigned long mask = ~(c->dst.bytes * 8 - 1);
1231
1232 c->dst.ptr = (void *)c->dst.ptr +
1233 (c->src.val & mask) / 8;
1234 }
1235 break;
1236 case DstAcc:
1237 c->dst.type = OP_REG;
1238 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1239 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1240 switch (c->dst.bytes) {
1241 case 1:
1242 c->dst.val = *(u8 *)c->dst.ptr;
1243 break;
1244 case 2:
1245 c->dst.val = *(u16 *)c->dst.ptr;
1246 break;
1247 case 4:
1248 c->dst.val = *(u32 *)c->dst.ptr;
1249 break;
1250 case 8:
1251 c->dst.val = *(u64 *)c->dst.ptr;
1252 break;
1253 }
1254 c->dst.orig_val = c->dst.val;
1255 break;
1256 case DstDI:
1257 c->dst.type = OP_MEM;
1258 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1259 c->dst.ptr = (unsigned long *)
1260 register_address(c, es_base(ctxt),
1261 c->regs[VCPU_REGS_RDI]);
1262 c->dst.val = 0;
1263 break;
1264 }
1265
1266done:
1267 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1268}
1269
1270static int read_emulated(struct x86_emulate_ctxt *ctxt,
1271 struct x86_emulate_ops *ops,
1272 unsigned long addr, void *dest, unsigned size)
1273{
1274 int rc;
1275 struct read_cache *mc = &ctxt->decode.mem_read;
1276
1277 while (size) {
1278 int n = min(size, 8u);
1279 size -= n;
1280 if (mc->pos < mc->end)
1281 goto read_cached;
1282
1283 rc = ops->read_emulated(addr, mc->data + mc->end, n, ctxt->vcpu);
1284 if (rc != X86EMUL_CONTINUE)
1285 return rc;
1286 mc->end += n;
1287
1288 read_cached:
1289 memcpy(dest, mc->data + mc->pos, n);
1290 mc->pos += n;
1291 dest += n;
1292 addr += n;
1293 }
1294 return X86EMUL_CONTINUE;
1295}
1296
1297static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
1298 struct x86_emulate_ops *ops,
1299 unsigned int size, unsigned short port,
1300 void *dest)
1301{
1302 struct read_cache *rc = &ctxt->decode.io_read;
1303
1304 if (rc->pos == rc->end) { /* refill pio read ahead */
1305 struct decode_cache *c = &ctxt->decode;
1306 unsigned int in_page, n;
1307 unsigned int count = c->rep_prefix ?
1308 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
1309 in_page = (ctxt->eflags & EFLG_DF) ?
1310 offset_in_page(c->regs[VCPU_REGS_RDI]) :
1311 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
1312 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1313 count);
1314 if (n == 0)
1315 n = 1;
1316 rc->pos = rc->end = 0;
1317 if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu))
1318 return 0;
1319 rc->end = n * size;
1320 }
1321
1322 memcpy(dest, rc->data + rc->pos, size);
1323 rc->pos += size;
1324 return 1;
1325}
1326
1327static u32 desc_limit_scaled(struct desc_struct *desc)
1328{
1329 u32 limit = get_desc_limit(desc);
1330
1331 return desc->g ? (limit << 12) | 0xfff : limit;
1332}
1333
1334static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1335 struct x86_emulate_ops *ops,
1336 u16 selector, struct desc_ptr *dt)
1337{
1338 if (selector & 1 << 2) {
1339 struct desc_struct desc;
1340 memset (dt, 0, sizeof *dt);
1341 if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu))
1342 return;
1343
1344 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1345 dt->address = get_desc_base(&desc);
1346 } else
1347 ops->get_gdt(dt, ctxt->vcpu);
1348}
1349
1350/* allowed just for 8 bytes segments */
1351static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1352 struct x86_emulate_ops *ops,
1353 u16 selector, struct desc_struct *desc)
1354{
1355 struct desc_ptr dt;
1356 u16 index = selector >> 3;
1357 int ret;
1358 u32 err;
1359 ulong addr;
1360
1361 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1362
1363 if (dt.size < index * 8 + 7) {
1364 kvm_inject_gp(ctxt->vcpu, selector & 0xfffc);
1365 return X86EMUL_PROPAGATE_FAULT;
1366 }
1367 addr = dt.address + index * 8;
1368 ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
1369 if (ret == X86EMUL_PROPAGATE_FAULT)
1370 kvm_inject_page_fault(ctxt->vcpu, addr, err);
1371
1372 return ret;
1373}
1374
1375/* allowed just for 8 bytes segments */
1376static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1377 struct x86_emulate_ops *ops,
1378 u16 selector, struct desc_struct *desc)
1379{
1380 struct desc_ptr dt;
1381 u16 index = selector >> 3;
1382 u32 err;
1383 ulong addr;
1384 int ret;
1385
1386 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1387
1388 if (dt.size < index * 8 + 7) {
1389 kvm_inject_gp(ctxt->vcpu, selector & 0xfffc);
1390 return X86EMUL_PROPAGATE_FAULT;
1391 }
1392
1393 addr = dt.address + index * 8;
1394 ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
1395 if (ret == X86EMUL_PROPAGATE_FAULT)
1396 kvm_inject_page_fault(ctxt->vcpu, addr, err);
1397
1398 return ret;
1399}
1400
1401static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1402 struct x86_emulate_ops *ops,
1403 u16 selector, int seg)
1404{
1405 struct desc_struct seg_desc;
1406 u8 dpl, rpl, cpl;
1407 unsigned err_vec = GP_VECTOR;
1408 u32 err_code = 0;
1409 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1410 int ret;
1411
1412 memset(&seg_desc, 0, sizeof seg_desc);
1413
1414 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1415 || ctxt->mode == X86EMUL_MODE_REAL) {
1416 /* set real mode segment descriptor */
1417 set_desc_base(&seg_desc, selector << 4);
1418 set_desc_limit(&seg_desc, 0xffff);
1419 seg_desc.type = 3;
1420 seg_desc.p = 1;
1421 seg_desc.s = 1;
1422 goto load;
1423 }
1424
1425 /* NULL selector is not valid for TR, CS and SS */
1426 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1427 && null_selector)
1428 goto exception;
1429
1430 /* TR should be in GDT only */
1431 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1432 goto exception;
1433
1434 if (null_selector) /* for NULL selector skip all following checks */
1435 goto load;
1436
1437 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
1438 if (ret != X86EMUL_CONTINUE)
1439 return ret;
1440
1441 err_code = selector & 0xfffc;
1442 err_vec = GP_VECTOR;
1443
1444 /* can't load system descriptor into segment selecor */
1445 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1446 goto exception;
1447
1448 if (!seg_desc.p) {
1449 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1450 goto exception;
1451 }
1452
1453 rpl = selector & 3;
1454 dpl = seg_desc.dpl;
1455 cpl = ops->cpl(ctxt->vcpu);
1456
1457 switch (seg) {
1458 case VCPU_SREG_SS:
1459 /*
1460 * segment is not a writable data segment or segment
1461 * selector's RPL != CPL or segment selector's RPL != CPL
1462 */
1463 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1464 goto exception;
1465 break;
1466 case VCPU_SREG_CS:
1467 if (!(seg_desc.type & 8))
1468 goto exception;
1469
1470 if (seg_desc.type & 4) {
1471 /* conforming */
1472 if (dpl > cpl)
1473 goto exception;
1474 } else {
1475 /* nonconforming */
1476 if (rpl > cpl || dpl != cpl)
1477 goto exception;
1478 }
1479 /* CS(RPL) <- CPL */
1480 selector = (selector & 0xfffc) | cpl;
1481 break;
1482 case VCPU_SREG_TR:
1483 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1484 goto exception;
1485 break;
1486 case VCPU_SREG_LDTR:
1487 if (seg_desc.s || seg_desc.type != 2)
1488 goto exception;
1489 break;
1490 default: /* DS, ES, FS, or GS */
1491 /*
1492 * segment is not a data or readable code segment or
1493 * ((segment is a data or nonconforming code segment)
1494 * and (both RPL and CPL > DPL))
1495 */
1496 if ((seg_desc.type & 0xa) == 0x8 ||
1497 (((seg_desc.type & 0xc) != 0xc) &&
1498 (rpl > dpl && cpl > dpl)))
1499 goto exception;
1500 break;
1501 }
1502
1503 if (seg_desc.s) {
1504 /* mark segment as accessed */
1505 seg_desc.type |= 1;
1506 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1507 if (ret != X86EMUL_CONTINUE)
1508 return ret;
1509 }
1510load:
1511 ops->set_segment_selector(selector, seg, ctxt->vcpu);
1512 ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu);
1513 return X86EMUL_CONTINUE;
1514exception:
1515 kvm_queue_exception_e(ctxt->vcpu, err_vec, err_code);
1516 return X86EMUL_PROPAGATE_FAULT;
1517}
1518
1519static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
1520{
1521 struct decode_cache *c = &ctxt->decode;
1522
1523 c->dst.type = OP_MEM;
1524 c->dst.bytes = c->op_bytes;
1525 c->dst.val = c->src.val;
1526 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
1527 c->dst.ptr = (void *) register_address(c, ss_base(ctxt),
1528 c->regs[VCPU_REGS_RSP]);
1529}
1530
1531static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1532 struct x86_emulate_ops *ops,
1533 void *dest, int len)
1534{
1535 struct decode_cache *c = &ctxt->decode;
1536 int rc;
1537
1538 rc = read_emulated(ctxt, ops, register_address(c, ss_base(ctxt),
1539 c->regs[VCPU_REGS_RSP]),
1540 dest, len);
1541 if (rc != X86EMUL_CONTINUE)
1542 return rc;
1543
1544 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1545 return rc;
1546}
1547
1548static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1549 struct x86_emulate_ops *ops,
1550 void *dest, int len)
1551{
1552 int rc;
1553 unsigned long val, change_mask;
1554 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1555 int cpl = ops->cpl(ctxt->vcpu);
1556
1557 rc = emulate_pop(ctxt, ops, &val, len);
1558 if (rc != X86EMUL_CONTINUE)
1559 return rc;
1560
1561 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1562 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1563
1564 switch(ctxt->mode) {
1565 case X86EMUL_MODE_PROT64:
1566 case X86EMUL_MODE_PROT32:
1567 case X86EMUL_MODE_PROT16:
1568 if (cpl == 0)
1569 change_mask |= EFLG_IOPL;
1570 if (cpl <= iopl)
1571 change_mask |= EFLG_IF;
1572 break;
1573 case X86EMUL_MODE_VM86:
1574 if (iopl < 3) {
1575 kvm_inject_gp(ctxt->vcpu, 0);
1576 return X86EMUL_PROPAGATE_FAULT;
1577 }
1578 change_mask |= EFLG_IF;
1579 break;
1580 default: /* real mode */
1581 change_mask |= (EFLG_IOPL | EFLG_IF);
1582 break;
1583 }
1584
1585 *(unsigned long *)dest =
1586 (ctxt->eflags & ~change_mask) | (val & change_mask);
1587
1588 return rc;
1589}
1590
1591static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt, int seg)
1592{
1593 struct decode_cache *c = &ctxt->decode;
1594 struct kvm_segment segment;
1595
1596 kvm_x86_ops->get_segment(ctxt->vcpu, &segment, seg);
1597
1598 c->src.val = segment.selector;
1599 emulate_push(ctxt);
1600}
1601
1602static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1603 struct x86_emulate_ops *ops, int seg)
1604{
1605 struct decode_cache *c = &ctxt->decode;
1606 unsigned long selector;
1607 int rc;
1608
1609 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1610 if (rc != X86EMUL_CONTINUE)
1611 return rc;
1612
1613 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
1614 return rc;
1615}
1616
1617static void emulate_pusha(struct x86_emulate_ctxt *ctxt)
1618{
1619 struct decode_cache *c = &ctxt->decode;
1620 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1621 int reg = VCPU_REGS_RAX;
1622
1623 while (reg <= VCPU_REGS_RDI) {
1624 (reg == VCPU_REGS_RSP) ?
1625 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
1626
1627 emulate_push(ctxt);
1628 ++reg;
1629 }
1630}
1631
1632static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1633 struct x86_emulate_ops *ops)
1634{
1635 struct decode_cache *c = &ctxt->decode;
1636 int rc = X86EMUL_CONTINUE;
1637 int reg = VCPU_REGS_RDI;
1638
1639 while (reg >= VCPU_REGS_RAX) {
1640 if (reg == VCPU_REGS_RSP) {
1641 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1642 c->op_bytes);
1643 --reg;
1644 }
1645
1646 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1647 if (rc != X86EMUL_CONTINUE)
1648 break;
1649 --reg;
1650 }
1651 return rc;
1652}
1653
1654static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1655 struct x86_emulate_ops *ops)
1656{
1657 struct decode_cache *c = &ctxt->decode;
1658
1659 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
1660}
1661
1662static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
1663{
1664 struct decode_cache *c = &ctxt->decode;
1665 switch (c->modrm_reg) {
1666 case 0: /* rol */
1667 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
1668 break;
1669 case 1: /* ror */
1670 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
1671 break;
1672 case 2: /* rcl */
1673 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
1674 break;
1675 case 3: /* rcr */
1676 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
1677 break;
1678 case 4: /* sal/shl */
1679 case 6: /* sal/shl */
1680 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
1681 break;
1682 case 5: /* shr */
1683 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
1684 break;
1685 case 7: /* sar */
1686 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
1687 break;
1688 }
1689}
1690
1691static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
1692 struct x86_emulate_ops *ops)
1693{
1694 struct decode_cache *c = &ctxt->decode;
1695
1696 switch (c->modrm_reg) {
1697 case 0 ... 1: /* test */
1698 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
1699 break;
1700 case 2: /* not */
1701 c->dst.val = ~c->dst.val;
1702 break;
1703 case 3: /* neg */
1704 emulate_1op("neg", c->dst, ctxt->eflags);
1705 break;
1706 default:
1707 return 0;
1708 }
1709 return 1;
1710}
1711
1712static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
1713 struct x86_emulate_ops *ops)
1714{
1715 struct decode_cache *c = &ctxt->decode;
1716
1717 switch (c->modrm_reg) {
1718 case 0: /* inc */
1719 emulate_1op("inc", c->dst, ctxt->eflags);
1720 break;
1721 case 1: /* dec */
1722 emulate_1op("dec", c->dst, ctxt->eflags);
1723 break;
1724 case 2: /* call near abs */ {
1725 long int old_eip;
1726 old_eip = c->eip;
1727 c->eip = c->src.val;
1728 c->src.val = old_eip;
1729 emulate_push(ctxt);
1730 break;
1731 }
1732 case 4: /* jmp abs */
1733 c->eip = c->src.val;
1734 break;
1735 case 6: /* push */
1736 emulate_push(ctxt);
1737 break;
1738 }
1739 return X86EMUL_CONTINUE;
1740}
1741
1742static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1743 struct x86_emulate_ops *ops)
1744{
1745 struct decode_cache *c = &ctxt->decode;
1746 u64 old = c->dst.orig_val;
1747
1748 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1749 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1750
1751 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1752 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
1753 ctxt->eflags &= ~EFLG_ZF;
1754 } else {
1755 c->dst.val = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1756 (u32) c->regs[VCPU_REGS_RBX];
1757
1758 ctxt->eflags |= EFLG_ZF;
1759 }
1760 return X86EMUL_CONTINUE;
1761}
1762
1763static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1764 struct x86_emulate_ops *ops)
1765{
1766 struct decode_cache *c = &ctxt->decode;
1767 int rc;
1768 unsigned long cs;
1769
1770 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1771 if (rc != X86EMUL_CONTINUE)
1772 return rc;
1773 if (c->op_bytes == 4)
1774 c->eip = (u32)c->eip;
1775 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1776 if (rc != X86EMUL_CONTINUE)
1777 return rc;
1778 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
1779 return rc;
1780}
1781
1782static inline int writeback(struct x86_emulate_ctxt *ctxt,
1783 struct x86_emulate_ops *ops)
1784{
1785 int rc;
1786 struct decode_cache *c = &ctxt->decode;
1787
1788 switch (c->dst.type) {
1789 case OP_REG:
1790 /* The 4-byte case *is* correct:
1791 * in 64-bit mode we zero-extend.
1792 */
1793 switch (c->dst.bytes) {
1794 case 1:
1795 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1796 break;
1797 case 2:
1798 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1799 break;
1800 case 4:
1801 *c->dst.ptr = (u32)c->dst.val;
1802 break; /* 64b: zero-ext */
1803 case 8:
1804 *c->dst.ptr = c->dst.val;
1805 break;
1806 }
1807 break;
1808 case OP_MEM:
1809 if (c->lock_prefix)
1810 rc = ops->cmpxchg_emulated(
1811 (unsigned long)c->dst.ptr,
1812 &c->dst.orig_val,
1813 &c->dst.val,
1814 c->dst.bytes,
1815 ctxt->vcpu);
1816 else
1817 rc = ops->write_emulated(
1818 (unsigned long)c->dst.ptr,
1819 &c->dst.val,
1820 c->dst.bytes,
1821 ctxt->vcpu);
1822 if (rc != X86EMUL_CONTINUE)
1823 return rc;
1824 break;
1825 case OP_NONE:
1826 /* no writeback */
1827 break;
1828 default:
1829 break;
1830 }
1831 return X86EMUL_CONTINUE;
1832}
1833
1834static void toggle_interruptibility(struct x86_emulate_ctxt *ctxt, u32 mask)
1835{
1836 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(ctxt->vcpu, mask);
1837 /*
1838 * an sti; sti; sequence only disable interrupts for the first
1839 * instruction. So, if the last instruction, be it emulated or
1840 * not, left the system with the INT_STI flag enabled, it
1841 * means that the last instruction is an sti. We should not
1842 * leave the flag on in this case. The same goes for mov ss
1843 */
1844 if (!(int_shadow & mask))
1845 ctxt->interruptibility = mask;
1846}
1847
1848static inline void
1849setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
1850 struct kvm_segment *cs, struct kvm_segment *ss)
1851{
1852 memset(cs, 0, sizeof(struct kvm_segment));
1853 kvm_x86_ops->get_segment(ctxt->vcpu, cs, VCPU_SREG_CS);
1854 memset(ss, 0, sizeof(struct kvm_segment));
1855
1856 cs->l = 0; /* will be adjusted later */
1857 cs->base = 0; /* flat segment */
1858 cs->g = 1; /* 4kb granularity */
1859 cs->limit = 0xffffffff; /* 4GB limit */
1860 cs->type = 0x0b; /* Read, Execute, Accessed */
1861 cs->s = 1;
1862 cs->dpl = 0; /* will be adjusted later */
1863 cs->present = 1;
1864 cs->db = 1;
1865
1866 ss->unusable = 0;
1867 ss->base = 0; /* flat segment */
1868 ss->limit = 0xffffffff; /* 4GB limit */
1869 ss->g = 1; /* 4kb granularity */
1870 ss->s = 1;
1871 ss->type = 0x03; /* Read/Write, Accessed */
1872 ss->db = 1; /* 32bit stack segment */
1873 ss->dpl = 0;
1874 ss->present = 1;
1875}
1876
1877static int
1878emulate_syscall(struct x86_emulate_ctxt *ctxt)
1879{
1880 struct decode_cache *c = &ctxt->decode;
1881 struct kvm_segment cs, ss;
1882 u64 msr_data;
1883
1884 /* syscall is not available in real mode */
1885 if (ctxt->mode == X86EMUL_MODE_REAL ||
1886 ctxt->mode == X86EMUL_MODE_VM86) {
1887 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
1888 return X86EMUL_PROPAGATE_FAULT;
1889 }
1890
1891 setup_syscalls_segments(ctxt, &cs, &ss);
1892
1893 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1894 msr_data >>= 32;
1895 cs.selector = (u16)(msr_data & 0xfffc);
1896 ss.selector = (u16)(msr_data + 8);
1897
1898 if (is_long_mode(ctxt->vcpu)) {
1899 cs.db = 0;
1900 cs.l = 1;
1901 }
1902 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
1903 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
1904
1905 c->regs[VCPU_REGS_RCX] = c->eip;
1906 if (is_long_mode(ctxt->vcpu)) {
1907#ifdef CONFIG_X86_64
1908 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1909
1910 kvm_x86_ops->get_msr(ctxt->vcpu,
1911 ctxt->mode == X86EMUL_MODE_PROT64 ?
1912 MSR_LSTAR : MSR_CSTAR, &msr_data);
1913 c->eip = msr_data;
1914
1915 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
1916 ctxt->eflags &= ~(msr_data | EFLG_RF);
1917#endif
1918 } else {
1919 /* legacy mode */
1920 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1921 c->eip = (u32)msr_data;
1922
1923 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1924 }
1925
1926 return X86EMUL_CONTINUE;
1927}
1928
1929static int
1930emulate_sysenter(struct x86_emulate_ctxt *ctxt)
1931{
1932 struct decode_cache *c = &ctxt->decode;
1933 struct kvm_segment cs, ss;
1934 u64 msr_data;
1935
1936 /* inject #GP if in real mode */
1937 if (ctxt->mode == X86EMUL_MODE_REAL) {
1938 kvm_inject_gp(ctxt->vcpu, 0);
1939 return X86EMUL_PROPAGATE_FAULT;
1940 }
1941
1942 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1943 * Therefore, we inject an #UD.
1944 */
1945 if (ctxt->mode == X86EMUL_MODE_PROT64) {
1946 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
1947 return X86EMUL_PROPAGATE_FAULT;
1948 }
1949
1950 setup_syscalls_segments(ctxt, &cs, &ss);
1951
1952 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1953 switch (ctxt->mode) {
1954 case X86EMUL_MODE_PROT32:
1955 if ((msr_data & 0xfffc) == 0x0) {
1956 kvm_inject_gp(ctxt->vcpu, 0);
1957 return X86EMUL_PROPAGATE_FAULT;
1958 }
1959 break;
1960 case X86EMUL_MODE_PROT64:
1961 if (msr_data == 0x0) {
1962 kvm_inject_gp(ctxt->vcpu, 0);
1963 return X86EMUL_PROPAGATE_FAULT;
1964 }
1965 break;
1966 }
1967
1968 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1969 cs.selector = (u16)msr_data;
1970 cs.selector &= ~SELECTOR_RPL_MASK;
1971 ss.selector = cs.selector + 8;
1972 ss.selector &= ~SELECTOR_RPL_MASK;
1973 if (ctxt->mode == X86EMUL_MODE_PROT64
1974 || is_long_mode(ctxt->vcpu)) {
1975 cs.db = 0;
1976 cs.l = 1;
1977 }
1978
1979 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
1980 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
1981
1982 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
1983 c->eip = msr_data;
1984
1985 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
1986 c->regs[VCPU_REGS_RSP] = msr_data;
1987
1988 return X86EMUL_CONTINUE;
1989}
1990
1991static int
1992emulate_sysexit(struct x86_emulate_ctxt *ctxt)
1993{
1994 struct decode_cache *c = &ctxt->decode;
1995 struct kvm_segment cs, ss;
1996 u64 msr_data;
1997 int usermode;
1998
1999 /* inject #GP if in real mode or Virtual 8086 mode */
2000 if (ctxt->mode == X86EMUL_MODE_REAL ||
2001 ctxt->mode == X86EMUL_MODE_VM86) {
2002 kvm_inject_gp(ctxt->vcpu, 0);
2003 return X86EMUL_PROPAGATE_FAULT;
2004 }
2005
2006 setup_syscalls_segments(ctxt, &cs, &ss);
2007
2008 if ((c->rex_prefix & 0x8) != 0x0)
2009 usermode = X86EMUL_MODE_PROT64;
2010 else
2011 usermode = X86EMUL_MODE_PROT32;
2012
2013 cs.dpl = 3;
2014 ss.dpl = 3;
2015 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
2016 switch (usermode) {
2017 case X86EMUL_MODE_PROT32:
2018 cs.selector = (u16)(msr_data + 16);
2019 if ((msr_data & 0xfffc) == 0x0) {
2020 kvm_inject_gp(ctxt->vcpu, 0);
2021 return X86EMUL_PROPAGATE_FAULT;
2022 }
2023 ss.selector = (u16)(msr_data + 24);
2024 break;
2025 case X86EMUL_MODE_PROT64:
2026 cs.selector = (u16)(msr_data + 32);
2027 if (msr_data == 0x0) {
2028 kvm_inject_gp(ctxt->vcpu, 0);
2029 return X86EMUL_PROPAGATE_FAULT;
2030 }
2031 ss.selector = cs.selector + 8;
2032 cs.db = 0;
2033 cs.l = 1;
2034 break;
2035 }
2036 cs.selector |= SELECTOR_RPL_MASK;
2037 ss.selector |= SELECTOR_RPL_MASK;
2038
2039 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
2040 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
2041
2042 c->eip = ctxt->vcpu->arch.regs[VCPU_REGS_RDX];
2043 c->regs[VCPU_REGS_RSP] = ctxt->vcpu->arch.regs[VCPU_REGS_RCX];
2044
2045 return X86EMUL_CONTINUE;
2046}
2047
2048static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
2049 struct x86_emulate_ops *ops)
2050{
2051 int iopl;
2052 if (ctxt->mode == X86EMUL_MODE_REAL)
2053 return false;
2054 if (ctxt->mode == X86EMUL_MODE_VM86)
2055 return true;
2056 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
2057 return ops->cpl(ctxt->vcpu) > iopl;
2058}
2059
2060static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
2061 struct x86_emulate_ops *ops,
2062 u16 port, u16 len)
2063{
2064 struct kvm_segment tr_seg;
2065 int r;
2066 u16 io_bitmap_ptr;
2067 u8 perm, bit_idx = port & 0x7;
2068 unsigned mask = (1 << len) - 1;
2069
2070 kvm_get_segment(ctxt->vcpu, &tr_seg, VCPU_SREG_TR);
2071 if (tr_seg.unusable)
2072 return false;
2073 if (tr_seg.limit < 103)
2074 return false;
2075 r = ops->read_std(tr_seg.base + 102, &io_bitmap_ptr, 2, ctxt->vcpu,
2076 NULL);
2077 if (r != X86EMUL_CONTINUE)
2078 return false;
2079 if (io_bitmap_ptr + port/8 > tr_seg.limit)
2080 return false;
2081 r = ops->read_std(tr_seg.base + io_bitmap_ptr + port/8, &perm, 1,
2082 ctxt->vcpu, NULL);
2083 if (r != X86EMUL_CONTINUE)
2084 return false;
2085 if ((perm >> bit_idx) & mask)
2086 return false;
2087 return true;
2088}
2089
2090static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
2091 struct x86_emulate_ops *ops,
2092 u16 port, u16 len)
2093{
2094 if (emulator_bad_iopl(ctxt, ops))
2095 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
2096 return false;
2097 return true;
2098}
2099
2100static u32 get_cached_descriptor_base(struct x86_emulate_ctxt *ctxt,
2101 struct x86_emulate_ops *ops,
2102 int seg)
2103{
2104 struct desc_struct desc;
2105 if (ops->get_cached_descriptor(&desc, seg, ctxt->vcpu))
2106 return get_desc_base(&desc);
2107 else
2108 return ~0;
2109}
2110
2111static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2112 struct x86_emulate_ops *ops,
2113 struct tss_segment_16 *tss)
2114{
2115 struct decode_cache *c = &ctxt->decode;
2116
2117 tss->ip = c->eip;
2118 tss->flag = ctxt->eflags;
2119 tss->ax = c->regs[VCPU_REGS_RAX];
2120 tss->cx = c->regs[VCPU_REGS_RCX];
2121 tss->dx = c->regs[VCPU_REGS_RDX];
2122 tss->bx = c->regs[VCPU_REGS_RBX];
2123 tss->sp = c->regs[VCPU_REGS_RSP];
2124 tss->bp = c->regs[VCPU_REGS_RBP];
2125 tss->si = c->regs[VCPU_REGS_RSI];
2126 tss->di = c->regs[VCPU_REGS_RDI];
2127
2128 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2129 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2130 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2131 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2132 tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2133}
2134
2135static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2136 struct x86_emulate_ops *ops,
2137 struct tss_segment_16 *tss)
2138{
2139 struct decode_cache *c = &ctxt->decode;
2140 int ret;
2141
2142 c->eip = tss->ip;
2143 ctxt->eflags = tss->flag | 2;
2144 c->regs[VCPU_REGS_RAX] = tss->ax;
2145 c->regs[VCPU_REGS_RCX] = tss->cx;
2146 c->regs[VCPU_REGS_RDX] = tss->dx;
2147 c->regs[VCPU_REGS_RBX] = tss->bx;
2148 c->regs[VCPU_REGS_RSP] = tss->sp;
2149 c->regs[VCPU_REGS_RBP] = tss->bp;
2150 c->regs[VCPU_REGS_RSI] = tss->si;
2151 c->regs[VCPU_REGS_RDI] = tss->di;
2152
2153 /*
2154 * SDM says that segment selectors are loaded before segment
2155 * descriptors
2156 */
2157 ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu);
2158 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2159 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2160 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2161 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2162
2163 /*
2164 * Now load segment descriptors. If fault happenes at this stage
2165 * it is handled in a context of new task
2166 */
2167 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
2168 if (ret != X86EMUL_CONTINUE)
2169 return ret;
2170 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2171 if (ret != X86EMUL_CONTINUE)
2172 return ret;
2173 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2174 if (ret != X86EMUL_CONTINUE)
2175 return ret;
2176 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2177 if (ret != X86EMUL_CONTINUE)
2178 return ret;
2179 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2180 if (ret != X86EMUL_CONTINUE)
2181 return ret;
2182
2183 return X86EMUL_CONTINUE;
2184}
2185
2186static int task_switch_16(struct x86_emulate_ctxt *ctxt,
2187 struct x86_emulate_ops *ops,
2188 u16 tss_selector, u16 old_tss_sel,
2189 ulong old_tss_base, struct desc_struct *new_desc)
2190{
2191 struct tss_segment_16 tss_seg;
2192 int ret;
2193 u32 err, new_tss_base = get_desc_base(new_desc);
2194
2195 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2196 &err);
2197 if (ret == X86EMUL_PROPAGATE_FAULT) {
2198 /* FIXME: need to provide precise fault address */
2199 kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err);
2200 return ret;
2201 }
2202
2203 save_state_to_tss16(ctxt, ops, &tss_seg);
2204
2205 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2206 &err);
2207 if (ret == X86EMUL_PROPAGATE_FAULT) {
2208 /* FIXME: need to provide precise fault address */
2209 kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err);
2210 return ret;
2211 }
2212
2213 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2214 &err);
2215 if (ret == X86EMUL_PROPAGATE_FAULT) {
2216 /* FIXME: need to provide precise fault address */
2217 kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err);
2218 return ret;
2219 }
2220
2221 if (old_tss_sel != 0xffff) {
2222 tss_seg.prev_task_link = old_tss_sel;
2223
2224 ret = ops->write_std(new_tss_base,
2225 &tss_seg.prev_task_link,
2226 sizeof tss_seg.prev_task_link,
2227 ctxt->vcpu, &err);
2228 if (ret == X86EMUL_PROPAGATE_FAULT) {
2229 /* FIXME: need to provide precise fault address */
2230 kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err);
2231 return ret;
2232 }
2233 }
2234
2235 return load_state_from_tss16(ctxt, ops, &tss_seg);
2236}
2237
2238static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
2239 struct x86_emulate_ops *ops,
2240 struct tss_segment_32 *tss)
2241{
2242 struct decode_cache *c = &ctxt->decode;
2243
2244 tss->cr3 = ops->get_cr(3, ctxt->vcpu);
2245 tss->eip = c->eip;
2246 tss->eflags = ctxt->eflags;
2247 tss->eax = c->regs[VCPU_REGS_RAX];
2248 tss->ecx = c->regs[VCPU_REGS_RCX];
2249 tss->edx = c->regs[VCPU_REGS_RDX];
2250 tss->ebx = c->regs[VCPU_REGS_RBX];
2251 tss->esp = c->regs[VCPU_REGS_RSP];
2252 tss->ebp = c->regs[VCPU_REGS_RBP];
2253 tss->esi = c->regs[VCPU_REGS_RSI];
2254 tss->edi = c->regs[VCPU_REGS_RDI];
2255
2256 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2257 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2258 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2259 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2260 tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu);
2261 tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu);
2262 tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2263}
2264
2265static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2266 struct x86_emulate_ops *ops,
2267 struct tss_segment_32 *tss)
2268{
2269 struct decode_cache *c = &ctxt->decode;
2270 int ret;
2271
2272 ops->set_cr(3, tss->cr3, ctxt->vcpu);
2273 c->eip = tss->eip;
2274 ctxt->eflags = tss->eflags | 2;
2275 c->regs[VCPU_REGS_RAX] = tss->eax;
2276 c->regs[VCPU_REGS_RCX] = tss->ecx;
2277 c->regs[VCPU_REGS_RDX] = tss->edx;
2278 c->regs[VCPU_REGS_RBX] = tss->ebx;
2279 c->regs[VCPU_REGS_RSP] = tss->esp;
2280 c->regs[VCPU_REGS_RBP] = tss->ebp;
2281 c->regs[VCPU_REGS_RSI] = tss->esi;
2282 c->regs[VCPU_REGS_RDI] = tss->edi;
2283
2284 /*
2285 * SDM says that segment selectors are loaded before segment
2286 * descriptors
2287 */
2288 ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu);
2289 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2290 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2291 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2292 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2293 ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu);
2294 ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu);
2295
2296 /*
2297 * Now load segment descriptors. If fault happenes at this stage
2298 * it is handled in a context of new task
2299 */
2300 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
2301 if (ret != X86EMUL_CONTINUE)
2302 return ret;
2303 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2304 if (ret != X86EMUL_CONTINUE)
2305 return ret;
2306 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2307 if (ret != X86EMUL_CONTINUE)
2308 return ret;
2309 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2310 if (ret != X86EMUL_CONTINUE)
2311 return ret;
2312 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2313 if (ret != X86EMUL_CONTINUE)
2314 return ret;
2315 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2316 if (ret != X86EMUL_CONTINUE)
2317 return ret;
2318 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2319 if (ret != X86EMUL_CONTINUE)
2320 return ret;
2321
2322 return X86EMUL_CONTINUE;
2323}
2324
2325static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2326 struct x86_emulate_ops *ops,
2327 u16 tss_selector, u16 old_tss_sel,
2328 ulong old_tss_base, struct desc_struct *new_desc)
2329{
2330 struct tss_segment_32 tss_seg;
2331 int ret;
2332 u32 err, new_tss_base = get_desc_base(new_desc);
2333
2334 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2335 &err);
2336 if (ret == X86EMUL_PROPAGATE_FAULT) {
2337 /* FIXME: need to provide precise fault address */
2338 kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err);
2339 return ret;
2340 }
2341
2342 save_state_to_tss32(ctxt, ops, &tss_seg);
2343
2344 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2345 &err);
2346 if (ret == X86EMUL_PROPAGATE_FAULT) {
2347 /* FIXME: need to provide precise fault address */
2348 kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err);
2349 return ret;
2350 }
2351
2352 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2353 &err);
2354 if (ret == X86EMUL_PROPAGATE_FAULT) {
2355 /* FIXME: need to provide precise fault address */
2356 kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err);
2357 return ret;
2358 }
2359
2360 if (old_tss_sel != 0xffff) {
2361 tss_seg.prev_task_link = old_tss_sel;
2362
2363 ret = ops->write_std(new_tss_base,
2364 &tss_seg.prev_task_link,
2365 sizeof tss_seg.prev_task_link,
2366 ctxt->vcpu, &err);
2367 if (ret == X86EMUL_PROPAGATE_FAULT) {
2368 /* FIXME: need to provide precise fault address */
2369 kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err);
2370 return ret;
2371 }
2372 }
2373
2374 return load_state_from_tss32(ctxt, ops, &tss_seg);
2375}
2376
2377static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
2378 struct x86_emulate_ops *ops,
2379 u16 tss_selector, int reason,
2380 bool has_error_code, u32 error_code)
2381{
2382 struct desc_struct curr_tss_desc, next_tss_desc;
2383 int ret;
2384 u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
2385 ulong old_tss_base =
2386 get_cached_descriptor_base(ctxt, ops, VCPU_SREG_TR);
2387 u32 desc_limit;
2388
2389 /* FIXME: old_tss_base == ~0 ? */
2390
2391 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2392 if (ret != X86EMUL_CONTINUE)
2393 return ret;
2394 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2395 if (ret != X86EMUL_CONTINUE)
2396 return ret;
2397
2398 /* FIXME: check that next_tss_desc is tss */
2399
2400 if (reason != TASK_SWITCH_IRET) {
2401 if ((tss_selector & 3) > next_tss_desc.dpl ||
2402 ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) {
2403 kvm_inject_gp(ctxt->vcpu, 0);
2404 return X86EMUL_PROPAGATE_FAULT;
2405 }
2406 }
2407
2408 desc_limit = desc_limit_scaled(&next_tss_desc);
2409 if (!next_tss_desc.p ||
2410 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2411 desc_limit < 0x2b)) {
2412 kvm_queue_exception_e(ctxt->vcpu, TS_VECTOR,
2413 tss_selector & 0xfffc);
2414 return X86EMUL_PROPAGATE_FAULT;
2415 }
2416
2417 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2418 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2419 write_segment_descriptor(ctxt, ops, old_tss_sel,
2420 &curr_tss_desc);
2421 }
2422
2423 if (reason == TASK_SWITCH_IRET)
2424 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2425
2426 /* set back link to prev task only if NT bit is set in eflags
2427 note that old_tss_sel is not used afetr this point */
2428 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2429 old_tss_sel = 0xffff;
2430
2431 if (next_tss_desc.type & 8)
2432 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2433 old_tss_base, &next_tss_desc);
2434 else
2435 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2436 old_tss_base, &next_tss_desc);
2437 if (ret != X86EMUL_CONTINUE)
2438 return ret;
2439
2440 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2441 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2442
2443 if (reason != TASK_SWITCH_IRET) {
2444 next_tss_desc.type |= (1 << 1); /* set busy flag */
2445 write_segment_descriptor(ctxt, ops, tss_selector,
2446 &next_tss_desc);
2447 }
2448
2449 ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
2450 ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu);
2451 ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu);
2452
2453 if (has_error_code) {
2454 struct decode_cache *c = &ctxt->decode;
2455
2456 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2457 c->lock_prefix = 0;
2458 c->src.val = (unsigned long) error_code;
2459 emulate_push(ctxt);
2460 }
2461
2462 return ret;
2463}
2464
2465int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2466 struct x86_emulate_ops *ops,
2467 u16 tss_selector, int reason,
2468 bool has_error_code, u32 error_code)
2469{
2470 struct decode_cache *c = &ctxt->decode;
2471 int rc;
2472
2473 memset(c, 0, sizeof(struct decode_cache));
2474 c->eip = ctxt->eip;
2475 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
2476 c->dst.type = OP_NONE;
2477
2478 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2479 has_error_code, error_code);
2480
2481 if (rc == X86EMUL_CONTINUE) {
2482 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
2483 kvm_rip_write(ctxt->vcpu, c->eip);
2484 rc = writeback(ctxt, ops);
2485 }
2486
2487 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
2488}
2489
2490static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned long base,
2491 int reg, struct operand *op)
2492{
2493 struct decode_cache *c = &ctxt->decode;
2494 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2495
2496 register_address_increment(c, &c->regs[reg], df * op->bytes);
2497 op->ptr = (unsigned long *)register_address(c, base, c->regs[reg]);
2498}
2499
2500int
2501x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
2502{
2503 u64 msr_data;
2504 struct decode_cache *c = &ctxt->decode;
2505 int rc = X86EMUL_CONTINUE;
2506 int saved_dst_type = c->dst.type;
2507
2508 ctxt->interruptibility = 0;
2509 ctxt->decode.mem_read.pos = 0;
2510
2511 /* Shadow copy of register state. Committed on successful emulation.
2512 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
2513 * modify them.
2514 */
2515
2516 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
2517
2518 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
2519 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
2520 goto done;
2521 }
2522
2523 /* LOCK prefix is allowed only with some instructions */
2524 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
2525 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
2526 goto done;
2527 }
2528
2529 /* Privileged instruction can be executed only in CPL=0 */
2530 if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
2531 kvm_inject_gp(ctxt->vcpu, 0);
2532 goto done;
2533 }
2534
2535 if (c->rep_prefix && (c->d & String)) {
2536 ctxt->restart = true;
2537 /* All REP prefixes have the same first termination condition */
2538 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
2539 string_done:
2540 ctxt->restart = false;
2541 kvm_rip_write(ctxt->vcpu, c->eip);
2542 goto done;
2543 }
2544 /* The second termination condition only applies for REPE
2545 * and REPNE. Test if the repeat string operation prefix is
2546 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
2547 * corresponding termination condition according to:
2548 * - if REPE/REPZ and ZF = 0 then done
2549 * - if REPNE/REPNZ and ZF = 1 then done
2550 */
2551 if ((c->b == 0xa6) || (c->b == 0xa7) ||
2552 (c->b == 0xae) || (c->b == 0xaf)) {
2553 if ((c->rep_prefix == REPE_PREFIX) &&
2554 ((ctxt->eflags & EFLG_ZF) == 0))
2555 goto string_done;
2556 if ((c->rep_prefix == REPNE_PREFIX) &&
2557 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))
2558 goto string_done;
2559 }
2560 c->eip = ctxt->eip;
2561 }
2562
2563 if (c->src.type == OP_MEM) {
2564 rc = read_emulated(ctxt, ops, (unsigned long)c->src.ptr,
2565 c->src.valptr, c->src.bytes);
2566 if (rc != X86EMUL_CONTINUE)
2567 goto done;
2568 c->src.orig_val = c->src.val;
2569 }
2570
2571 if (c->src2.type == OP_MEM) {
2572 rc = read_emulated(ctxt, ops, (unsigned long)c->src2.ptr,
2573 &c->src2.val, c->src2.bytes);
2574 if (rc != X86EMUL_CONTINUE)
2575 goto done;
2576 }
2577
2578 if ((c->d & DstMask) == ImplicitOps)
2579 goto special_insn;
2580
2581
2582 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
2583 /* optimisation - avoid slow emulated read if Mov */
2584 rc = read_emulated(ctxt, ops, (unsigned long)c->dst.ptr,
2585 &c->dst.val, c->dst.bytes);
2586 if (rc != X86EMUL_CONTINUE)
2587 goto done;
2588 }
2589 c->dst.orig_val = c->dst.val;
2590
2591special_insn:
2592
2593 if (c->twobyte)
2594 goto twobyte_insn;
2595
2596 switch (c->b) {
2597 case 0x00 ... 0x05:
2598 add: /* add */
2599 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
2600 break;
2601 case 0x06: /* push es */
2602 emulate_push_sreg(ctxt, VCPU_SREG_ES);
2603 break;
2604 case 0x07: /* pop es */
2605 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
2606 if (rc != X86EMUL_CONTINUE)
2607 goto done;
2608 break;
2609 case 0x08 ... 0x0d:
2610 or: /* or */
2611 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2612 break;
2613 case 0x0e: /* push cs */
2614 emulate_push_sreg(ctxt, VCPU_SREG_CS);
2615 break;
2616 case 0x10 ... 0x15:
2617 adc: /* adc */
2618 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
2619 break;
2620 case 0x16: /* push ss */
2621 emulate_push_sreg(ctxt, VCPU_SREG_SS);
2622 break;
2623 case 0x17: /* pop ss */
2624 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
2625 if (rc != X86EMUL_CONTINUE)
2626 goto done;
2627 break;
2628 case 0x18 ... 0x1d:
2629 sbb: /* sbb */
2630 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
2631 break;
2632 case 0x1e: /* push ds */
2633 emulate_push_sreg(ctxt, VCPU_SREG_DS);
2634 break;
2635 case 0x1f: /* pop ds */
2636 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
2637 if (rc != X86EMUL_CONTINUE)
2638 goto done;
2639 break;
2640 case 0x20 ... 0x25:
2641 and: /* and */
2642 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
2643 break;
2644 case 0x28 ... 0x2d:
2645 sub: /* sub */
2646 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
2647 break;
2648 case 0x30 ... 0x35:
2649 xor: /* xor */
2650 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
2651 break;
2652 case 0x38 ... 0x3d:
2653 cmp: /* cmp */
2654 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2655 break;
2656 case 0x40 ... 0x47: /* inc r16/r32 */
2657 emulate_1op("inc", c->dst, ctxt->eflags);
2658 break;
2659 case 0x48 ... 0x4f: /* dec r16/r32 */
2660 emulate_1op("dec", c->dst, ctxt->eflags);
2661 break;
2662 case 0x50 ... 0x57: /* push reg */
2663 emulate_push(ctxt);
2664 break;
2665 case 0x58 ... 0x5f: /* pop reg */
2666 pop_instruction:
2667 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
2668 if (rc != X86EMUL_CONTINUE)
2669 goto done;
2670 break;
2671 case 0x60: /* pusha */
2672 emulate_pusha(ctxt);
2673 break;
2674 case 0x61: /* popa */
2675 rc = emulate_popa(ctxt, ops);
2676 if (rc != X86EMUL_CONTINUE)
2677 goto done;
2678 break;
2679 case 0x63: /* movsxd */
2680 if (ctxt->mode != X86EMUL_MODE_PROT64)
2681 goto cannot_emulate;
2682 c->dst.val = (s32) c->src.val;
2683 break;
2684 case 0x68: /* push imm */
2685 case 0x6a: /* push imm8 */
2686 emulate_push(ctxt);
2687 break;
2688 case 0x6c: /* insb */
2689 case 0x6d: /* insw/insd */
2690 c->dst.bytes = min(c->dst.bytes, 4u);
2691 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
2692 c->dst.bytes)) {
2693 kvm_inject_gp(ctxt->vcpu, 0);
2694 goto done;
2695 }
2696 if (!pio_in_emulated(ctxt, ops, c->dst.bytes,
2697 c->regs[VCPU_REGS_RDX], &c->dst.val))
2698 goto done; /* IO is needed, skip writeback */
2699 break;
2700 case 0x6e: /* outsb */
2701 case 0x6f: /* outsw/outsd */
2702 c->src.bytes = min(c->src.bytes, 4u);
2703 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
2704 c->src.bytes)) {
2705 kvm_inject_gp(ctxt->vcpu, 0);
2706 goto done;
2707 }
2708 ops->pio_out_emulated(c->src.bytes, c->regs[VCPU_REGS_RDX],
2709 &c->src.val, 1, ctxt->vcpu);
2710
2711 c->dst.type = OP_NONE; /* nothing to writeback */
2712 break;
2713 case 0x70 ... 0x7f: /* jcc (short) */
2714 if (test_cc(c->b, ctxt->eflags))
2715 jmp_rel(c, c->src.val);
2716 break;
2717 case 0x80 ... 0x83: /* Grp1 */
2718 switch (c->modrm_reg) {
2719 case 0:
2720 goto add;
2721 case 1:
2722 goto or;
2723 case 2:
2724 goto adc;
2725 case 3:
2726 goto sbb;
2727 case 4:
2728 goto and;
2729 case 5:
2730 goto sub;
2731 case 6:
2732 goto xor;
2733 case 7:
2734 goto cmp;
2735 }
2736 break;
2737 case 0x84 ... 0x85:
2738 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
2739 break;
2740 case 0x86 ... 0x87: /* xchg */
2741 xchg:
2742 /* Write back the register source. */
2743 switch (c->dst.bytes) {
2744 case 1:
2745 *(u8 *) c->src.ptr = (u8) c->dst.val;
2746 break;
2747 case 2:
2748 *(u16 *) c->src.ptr = (u16) c->dst.val;
2749 break;
2750 case 4:
2751 *c->src.ptr = (u32) c->dst.val;
2752 break; /* 64b reg: zero-extend */
2753 case 8:
2754 *c->src.ptr = c->dst.val;
2755 break;
2756 }
2757 /*
2758 * Write back the memory destination with implicit LOCK
2759 * prefix.
2760 */
2761 c->dst.val = c->src.val;
2762 c->lock_prefix = 1;
2763 break;
2764 case 0x88 ... 0x8b: /* mov */
2765 goto mov;
2766 case 0x8c: { /* mov r/m, sreg */
2767 struct kvm_segment segreg;
2768
2769 if (c->modrm_reg <= VCPU_SREG_GS)
2770 kvm_get_segment(ctxt->vcpu, &segreg, c->modrm_reg);
2771 else {
2772 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
2773 goto done;
2774 }
2775 c->dst.val = segreg.selector;
2776 break;
2777 }
2778 case 0x8d: /* lea r16/r32, m */
2779 c->dst.val = c->modrm_ea;
2780 break;
2781 case 0x8e: { /* mov seg, r/m16 */
2782 uint16_t sel;
2783
2784 sel = c->src.val;
2785
2786 if (c->modrm_reg == VCPU_SREG_CS ||
2787 c->modrm_reg > VCPU_SREG_GS) {
2788 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
2789 goto done;
2790 }
2791
2792 if (c->modrm_reg == VCPU_SREG_SS)
2793 toggle_interruptibility(ctxt, KVM_X86_SHADOW_INT_MOV_SS);
2794
2795 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
2796
2797 c->dst.type = OP_NONE; /* Disable writeback. */
2798 break;
2799 }
2800 case 0x8f: /* pop (sole member of Grp1a) */
2801 rc = emulate_grp1a(ctxt, ops);
2802 if (rc != X86EMUL_CONTINUE)
2803 goto done;
2804 break;
2805 case 0x90: /* nop / xchg r8,rax */
2806 if (c->dst.ptr == (unsigned long *)&c->regs[VCPU_REGS_RAX]) {
2807 c->dst.type = OP_NONE; /* nop */
2808 break;
2809 }
2810 case 0x91 ... 0x97: /* xchg reg,rax */
2811 c->src.type = OP_REG;
2812 c->src.bytes = c->op_bytes;
2813 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
2814 c->src.val = *(c->src.ptr);
2815 goto xchg;
2816 case 0x9c: /* pushf */
2817 c->src.val = (unsigned long) ctxt->eflags;
2818 emulate_push(ctxt);
2819 break;
2820 case 0x9d: /* popf */
2821 c->dst.type = OP_REG;
2822 c->dst.ptr = (unsigned long *) &ctxt->eflags;
2823 c->dst.bytes = c->op_bytes;
2824 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
2825 if (rc != X86EMUL_CONTINUE)
2826 goto done;
2827 break;
2828 case 0xa0 ... 0xa1: /* mov */
2829 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
2830 c->dst.val = c->src.val;
2831 break;
2832 case 0xa2 ... 0xa3: /* mov */
2833 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
2834 break;
2835 case 0xa4 ... 0xa5: /* movs */
2836 goto mov;
2837 case 0xa6 ... 0xa7: /* cmps */
2838 c->dst.type = OP_NONE; /* Disable writeback. */
2839 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
2840 goto cmp;
2841 case 0xaa ... 0xab: /* stos */
2842 c->dst.val = c->regs[VCPU_REGS_RAX];
2843 break;
2844 case 0xac ... 0xad: /* lods */
2845 goto mov;
2846 case 0xae ... 0xaf: /* scas */
2847 DPRINTF("Urk! I don't handle SCAS.\n");
2848 goto cannot_emulate;
2849 case 0xb0 ... 0xbf: /* mov r, imm */
2850 goto mov;
2851 case 0xc0 ... 0xc1:
2852 emulate_grp2(ctxt);
2853 break;
2854 case 0xc3: /* ret */
2855 c->dst.type = OP_REG;
2856 c->dst.ptr = &c->eip;
2857 c->dst.bytes = c->op_bytes;
2858 goto pop_instruction;
2859 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
2860 mov:
2861 c->dst.val = c->src.val;
2862 break;
2863 case 0xcb: /* ret far */
2864 rc = emulate_ret_far(ctxt, ops);
2865 if (rc != X86EMUL_CONTINUE)
2866 goto done;
2867 break;
2868 case 0xd0 ... 0xd1: /* Grp2 */
2869 c->src.val = 1;
2870 emulate_grp2(ctxt);
2871 break;
2872 case 0xd2 ... 0xd3: /* Grp2 */
2873 c->src.val = c->regs[VCPU_REGS_RCX];
2874 emulate_grp2(ctxt);
2875 break;
2876 case 0xe4: /* inb */
2877 case 0xe5: /* in */
2878 goto do_io_in;
2879 case 0xe6: /* outb */
2880 case 0xe7: /* out */
2881 goto do_io_out;
2882 case 0xe8: /* call (near) */ {
2883 long int rel = c->src.val;
2884 c->src.val = (unsigned long) c->eip;
2885 jmp_rel(c, rel);
2886 emulate_push(ctxt);
2887 break;
2888 }
2889 case 0xe9: /* jmp rel */
2890 goto jmp;
2891 case 0xea: { /* jmp far */
2892 unsigned short sel;
2893 jump_far:
2894 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
2895
2896 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
2897 goto done;
2898
2899 c->eip = 0;
2900 memcpy(&c->eip, c->src.valptr, c->op_bytes);
2901 break;
2902 }
2903 case 0xeb:
2904 jmp: /* jmp rel short */
2905 jmp_rel(c, c->src.val);
2906 c->dst.type = OP_NONE; /* Disable writeback. */
2907 break;
2908 case 0xec: /* in al,dx */
2909 case 0xed: /* in (e/r)ax,dx */
2910 c->src.val = c->regs[VCPU_REGS_RDX];
2911 do_io_in:
2912 c->dst.bytes = min(c->dst.bytes, 4u);
2913 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
2914 kvm_inject_gp(ctxt->vcpu, 0);
2915 goto done;
2916 }
2917 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
2918 &c->dst.val))
2919 goto done; /* IO is needed */
2920 break;
2921 case 0xee: /* out al,dx */
2922 case 0xef: /* out (e/r)ax,dx */
2923 c->src.val = c->regs[VCPU_REGS_RDX];
2924 do_io_out:
2925 c->dst.bytes = min(c->dst.bytes, 4u);
2926 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
2927 kvm_inject_gp(ctxt->vcpu, 0);
2928 goto done;
2929 }
2930 ops->pio_out_emulated(c->dst.bytes, c->src.val, &c->dst.val, 1,
2931 ctxt->vcpu);
2932 c->dst.type = OP_NONE; /* Disable writeback. */
2933 break;
2934 case 0xf4: /* hlt */
2935 ctxt->vcpu->arch.halt_request = 1;
2936 break;
2937 case 0xf5: /* cmc */
2938 /* complement carry flag from eflags reg */
2939 ctxt->eflags ^= EFLG_CF;
2940 c->dst.type = OP_NONE; /* Disable writeback. */
2941 break;
2942 case 0xf6 ... 0xf7: /* Grp3 */
2943 if (!emulate_grp3(ctxt, ops))
2944 goto cannot_emulate;
2945 break;
2946 case 0xf8: /* clc */
2947 ctxt->eflags &= ~EFLG_CF;
2948 c->dst.type = OP_NONE; /* Disable writeback. */
2949 break;
2950 case 0xfa: /* cli */
2951 if (emulator_bad_iopl(ctxt, ops))
2952 kvm_inject_gp(ctxt->vcpu, 0);
2953 else {
2954 ctxt->eflags &= ~X86_EFLAGS_IF;
2955 c->dst.type = OP_NONE; /* Disable writeback. */
2956 }
2957 break;
2958 case 0xfb: /* sti */
2959 if (emulator_bad_iopl(ctxt, ops))
2960 kvm_inject_gp(ctxt->vcpu, 0);
2961 else {
2962 toggle_interruptibility(ctxt, KVM_X86_SHADOW_INT_STI);
2963 ctxt->eflags |= X86_EFLAGS_IF;
2964 c->dst.type = OP_NONE; /* Disable writeback. */
2965 }
2966 break;
2967 case 0xfc: /* cld */
2968 ctxt->eflags &= ~EFLG_DF;
2969 c->dst.type = OP_NONE; /* Disable writeback. */
2970 break;
2971 case 0xfd: /* std */
2972 ctxt->eflags |= EFLG_DF;
2973 c->dst.type = OP_NONE; /* Disable writeback. */
2974 break;
2975 case 0xfe: /* Grp4 */
2976 grp45:
2977 rc = emulate_grp45(ctxt, ops);
2978 if (rc != X86EMUL_CONTINUE)
2979 goto done;
2980 break;
2981 case 0xff: /* Grp5 */
2982 if (c->modrm_reg == 5)
2983 goto jump_far;
2984 goto grp45;
2985 }
2986
2987writeback:
2988 rc = writeback(ctxt, ops);
2989 if (rc != X86EMUL_CONTINUE)
2990 goto done;
2991
2992 /*
2993 * restore dst type in case the decoding will be reused
2994 * (happens for string instruction )
2995 */
2996 c->dst.type = saved_dst_type;
2997
2998 if ((c->d & SrcMask) == SrcSI)
2999 string_addr_inc(ctxt, seg_override_base(ctxt, c), VCPU_REGS_RSI,
3000 &c->src);
3001
3002 if ((c->d & DstMask) == DstDI)
3003 string_addr_inc(ctxt, es_base(ctxt), VCPU_REGS_RDI, &c->dst);
3004
3005 if (c->rep_prefix && (c->d & String)) {
3006 struct read_cache *rc = &ctxt->decode.io_read;
3007 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3008 /*
3009 * Re-enter guest when pio read ahead buffer is empty or,
3010 * if it is not used, after each 1024 iteration.
3011 */
3012 if ((rc->end == 0 && !(c->regs[VCPU_REGS_RCX] & 0x3ff)) ||
3013 (rc->end != 0 && rc->end == rc->pos))
3014 ctxt->restart = false;
3015 }
3016 /*
3017 * reset read cache here in case string instruction is restared
3018 * without decoding
3019 */
3020 ctxt->decode.mem_read.end = 0;
3021 /* Commit shadow register state. */
3022 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
3023 kvm_rip_write(ctxt->vcpu, c->eip);
3024 ops->set_rflags(ctxt->vcpu, ctxt->eflags);
3025
3026done:
3027 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
3028
3029twobyte_insn:
3030 switch (c->b) {
3031 case 0x01: /* lgdt, lidt, lmsw */
3032 switch (c->modrm_reg) {
3033 u16 size;
3034 unsigned long address;
3035
3036 case 0: /* vmcall */
3037 if (c->modrm_mod != 3 || c->modrm_rm != 1)
3038 goto cannot_emulate;
3039
3040 rc = kvm_fix_hypercall(ctxt->vcpu);
3041 if (rc != X86EMUL_CONTINUE)
3042 goto done;
3043
3044 /* Let the processor re-execute the fixed hypercall */
3045 c->eip = ctxt->eip;
3046 /* Disable writeback. */
3047 c->dst.type = OP_NONE;
3048 break;
3049 case 2: /* lgdt */
3050 rc = read_descriptor(ctxt, ops, c->src.ptr,
3051 &size, &address, c->op_bytes);
3052 if (rc != X86EMUL_CONTINUE)
3053 goto done;
3054 realmode_lgdt(ctxt->vcpu, size, address);
3055 /* Disable writeback. */
3056 c->dst.type = OP_NONE;
3057 break;
3058 case 3: /* lidt/vmmcall */
3059 if (c->modrm_mod == 3) {
3060 switch (c->modrm_rm) {
3061 case 1:
3062 rc = kvm_fix_hypercall(ctxt->vcpu);
3063 if (rc != X86EMUL_CONTINUE)
3064 goto done;
3065 break;
3066 default:
3067 goto cannot_emulate;
3068 }
3069 } else {
3070 rc = read_descriptor(ctxt, ops, c->src.ptr,
3071 &size, &address,
3072 c->op_bytes);
3073 if (rc != X86EMUL_CONTINUE)
3074 goto done;
3075 realmode_lidt(ctxt->vcpu, size, address);
3076 }
3077 /* Disable writeback. */
3078 c->dst.type = OP_NONE;
3079 break;
3080 case 4: /* smsw */
3081 c->dst.bytes = 2;
3082 c->dst.val = ops->get_cr(0, ctxt->vcpu);
3083 break;
3084 case 6: /* lmsw */
3085 ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0ful) |
3086 (c->src.val & 0x0f), ctxt->vcpu);
3087 c->dst.type = OP_NONE;
3088 break;
3089 case 5: /* not defined */
3090 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
3091 goto done;
3092 case 7: /* invlpg*/
3093 emulate_invlpg(ctxt->vcpu, c->modrm_ea);
3094 /* Disable writeback. */
3095 c->dst.type = OP_NONE;
3096 break;
3097 default:
3098 goto cannot_emulate;
3099 }
3100 break;
3101 case 0x05: /* syscall */
3102 rc = emulate_syscall(ctxt);
3103 if (rc != X86EMUL_CONTINUE)
3104 goto done;
3105 else
3106 goto writeback;
3107 break;
3108 case 0x06:
3109 emulate_clts(ctxt->vcpu);
3110 c->dst.type = OP_NONE;
3111 break;
3112 case 0x08: /* invd */
3113 case 0x09: /* wbinvd */
3114 case 0x0d: /* GrpP (prefetch) */
3115 case 0x18: /* Grp16 (prefetch/nop) */
3116 c->dst.type = OP_NONE;
3117 break;
3118 case 0x20: /* mov cr, reg */
3119 switch (c->modrm_reg) {
3120 case 1:
3121 case 5 ... 7:
3122 case 9 ... 15:
3123 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
3124 goto done;
3125 }
3126 c->regs[c->modrm_rm] = ops->get_cr(c->modrm_reg, ctxt->vcpu);
3127 c->dst.type = OP_NONE; /* no writeback */
3128 break;
3129 case 0x21: /* mov from dr to reg */
3130 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3131 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
3132 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
3133 goto done;
3134 }
3135 emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
3136 c->dst.type = OP_NONE; /* no writeback */
3137 break;
3138 case 0x22: /* mov reg, cr */
3139 ops->set_cr(c->modrm_reg, c->modrm_val, ctxt->vcpu);
3140 c->dst.type = OP_NONE;
3141 break;
3142 case 0x23: /* mov from reg to dr */
3143 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3144 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
3145 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
3146 goto done;
3147 }
3148 emulator_set_dr(ctxt, c->modrm_reg, c->regs[c->modrm_rm]);
3149 c->dst.type = OP_NONE; /* no writeback */
3150 break;
3151 case 0x30:
3152 /* wrmsr */
3153 msr_data = (u32)c->regs[VCPU_REGS_RAX]
3154 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
3155 if (kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
3156 kvm_inject_gp(ctxt->vcpu, 0);
3157 goto done;
3158 }
3159 rc = X86EMUL_CONTINUE;
3160 c->dst.type = OP_NONE;
3161 break;
3162 case 0x32:
3163 /* rdmsr */
3164 if (kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
3165 kvm_inject_gp(ctxt->vcpu, 0);
3166 goto done;
3167 } else {
3168 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
3169 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
3170 }
3171 rc = X86EMUL_CONTINUE;
3172 c->dst.type = OP_NONE;
3173 break;
3174 case 0x34: /* sysenter */
3175 rc = emulate_sysenter(ctxt);
3176 if (rc != X86EMUL_CONTINUE)
3177 goto done;
3178 else
3179 goto writeback;
3180 break;
3181 case 0x35: /* sysexit */
3182 rc = emulate_sysexit(ctxt);
3183 if (rc != X86EMUL_CONTINUE)
3184 goto done;
3185 else
3186 goto writeback;
3187 break;
3188 case 0x40 ... 0x4f: /* cmov */
3189 c->dst.val = c->dst.orig_val = c->src.val;
3190 if (!test_cc(c->b, ctxt->eflags))
3191 c->dst.type = OP_NONE; /* no writeback */
3192 break;
3193 case 0x80 ... 0x8f: /* jnz rel, etc*/
3194 if (test_cc(c->b, ctxt->eflags))
3195 jmp_rel(c, c->src.val);
3196 c->dst.type = OP_NONE;
3197 break;
3198 case 0xa0: /* push fs */
3199 emulate_push_sreg(ctxt, VCPU_SREG_FS);
3200 break;
3201 case 0xa1: /* pop fs */
3202 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
3203 if (rc != X86EMUL_CONTINUE)
3204 goto done;
3205 break;
3206 case 0xa3:
3207 bt: /* bt */
3208 c->dst.type = OP_NONE;
3209 /* only subword offset */
3210 c->src.val &= (c->dst.bytes << 3) - 1;
3211 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
3212 break;
3213 case 0xa4: /* shld imm8, r, r/m */
3214 case 0xa5: /* shld cl, r, r/m */
3215 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
3216 break;
3217 case 0xa8: /* push gs */
3218 emulate_push_sreg(ctxt, VCPU_SREG_GS);
3219 break;
3220 case 0xa9: /* pop gs */
3221 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
3222 if (rc != X86EMUL_CONTINUE)
3223 goto done;
3224 break;
3225 case 0xab:
3226 bts: /* bts */
3227 /* only subword offset */
3228 c->src.val &= (c->dst.bytes << 3) - 1;
3229 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
3230 break;
3231 case 0xac: /* shrd imm8, r, r/m */
3232 case 0xad: /* shrd cl, r, r/m */
3233 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
3234 break;
3235 case 0xae: /* clflush */
3236 break;
3237 case 0xb0 ... 0xb1: /* cmpxchg */
3238 /*
3239 * Save real source value, then compare EAX against
3240 * destination.
3241 */
3242 c->src.orig_val = c->src.val;
3243 c->src.val = c->regs[VCPU_REGS_RAX];
3244 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
3245 if (ctxt->eflags & EFLG_ZF) {
3246 /* Success: write back to memory. */
3247 c->dst.val = c->src.orig_val;
3248 } else {
3249 /* Failure: write the value we saw to EAX. */
3250 c->dst.type = OP_REG;
3251 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
3252 }
3253 break;
3254 case 0xb3:
3255 btr: /* btr */
3256 /* only subword offset */
3257 c->src.val &= (c->dst.bytes << 3) - 1;
3258 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
3259 break;
3260 case 0xb6 ... 0xb7: /* movzx */
3261 c->dst.bytes = c->op_bytes;
3262 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
3263 : (u16) c->src.val;
3264 break;
3265 case 0xba: /* Grp8 */
3266 switch (c->modrm_reg & 3) {
3267 case 0:
3268 goto bt;
3269 case 1:
3270 goto bts;
3271 case 2:
3272 goto btr;
3273 case 3:
3274 goto btc;
3275 }
3276 break;
3277 case 0xbb:
3278 btc: /* btc */
3279 /* only subword offset */
3280 c->src.val &= (c->dst.bytes << 3) - 1;
3281 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
3282 break;
3283 case 0xbe ... 0xbf: /* movsx */
3284 c->dst.bytes = c->op_bytes;
3285 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
3286 (s16) c->src.val;
3287 break;
3288 case 0xc3: /* movnti */
3289 c->dst.bytes = c->op_bytes;
3290 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
3291 (u64) c->src.val;
3292 break;
3293 case 0xc7: /* Grp9 (cmpxchg8b) */
3294 rc = emulate_grp9(ctxt, ops);
3295 if (rc != X86EMUL_CONTINUE)
3296 goto done;
3297 break;
3298 }
3299 goto writeback;
3300
3301cannot_emulate:
3302 DPRINTF("Cannot emulate %02x\n", c->b);
3303 return -1;
3304}
Linux kernel - Deliverables
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