| 1 | /* |
| 2 | * Local APIC handling, local APIC timers |
| 3 | * |
| 4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> |
| 5 | * |
| 6 | * Fixes |
| 7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; |
| 8 | * thanks to Eric Gilmore |
| 9 | * and Rolf G. Tews |
| 10 | * for testing these extensively. |
| 11 | * Maciej W. Rozycki : Various updates and fixes. |
| 12 | * Mikael Pettersson : Power Management for UP-APIC. |
| 13 | * Pavel Machek and |
| 14 | * Mikael Pettersson : PM converted to driver model. |
| 15 | */ |
| 16 | |
| 17 | #include <linux/config.h> |
| 18 | #include <linux/init.h> |
| 19 | |
| 20 | #include <linux/mm.h> |
| 21 | #include <linux/delay.h> |
| 22 | #include <linux/bootmem.h> |
| 23 | #include <linux/smp_lock.h> |
| 24 | #include <linux/interrupt.h> |
| 25 | #include <linux/mc146818rtc.h> |
| 26 | #include <linux/kernel_stat.h> |
| 27 | #include <linux/sysdev.h> |
| 28 | #include <linux/module.h> |
| 29 | |
| 30 | #include <asm/atomic.h> |
| 31 | #include <asm/smp.h> |
| 32 | #include <asm/mtrr.h> |
| 33 | #include <asm/mpspec.h> |
| 34 | #include <asm/pgalloc.h> |
| 35 | #include <asm/mach_apic.h> |
| 36 | #include <asm/nmi.h> |
| 37 | #include <asm/idle.h> |
| 38 | #include <asm/proto.h> |
| 39 | #include <asm/timex.h> |
| 40 | |
| 41 | int apic_verbosity; |
| 42 | int apic_runs_main_timer; |
| 43 | int apic_calibrate_pmtmr __initdata; |
| 44 | |
| 45 | int disable_apic_timer __initdata; |
| 46 | |
| 47 | /* |
| 48 | * cpu_mask that denotes the CPUs that needs timer interrupt coming in as |
| 49 | * IPIs in place of local APIC timers |
| 50 | */ |
| 51 | static cpumask_t timer_interrupt_broadcast_ipi_mask; |
| 52 | |
| 53 | /* Using APIC to generate smp_local_timer_interrupt? */ |
| 54 | int using_apic_timer __read_mostly = 0; |
| 55 | |
| 56 | static void apic_pm_activate(void); |
| 57 | |
| 58 | void enable_NMI_through_LVT0 (void * dummy) |
| 59 | { |
| 60 | unsigned int v; |
| 61 | |
| 62 | v = APIC_DM_NMI; /* unmask and set to NMI */ |
| 63 | apic_write(APIC_LVT0, v); |
| 64 | } |
| 65 | |
| 66 | int get_maxlvt(void) |
| 67 | { |
| 68 | unsigned int v, maxlvt; |
| 69 | |
| 70 | v = apic_read(APIC_LVR); |
| 71 | maxlvt = GET_APIC_MAXLVT(v); |
| 72 | return maxlvt; |
| 73 | } |
| 74 | |
| 75 | /* |
| 76 | * 'what should we do if we get a hw irq event on an illegal vector'. |
| 77 | * each architecture has to answer this themselves. |
| 78 | */ |
| 79 | void ack_bad_irq(unsigned int irq) |
| 80 | { |
| 81 | printk("unexpected IRQ trap at vector %02x\n", irq); |
| 82 | /* |
| 83 | * Currently unexpected vectors happen only on SMP and APIC. |
| 84 | * We _must_ ack these because every local APIC has only N |
| 85 | * irq slots per priority level, and a 'hanging, unacked' IRQ |
| 86 | * holds up an irq slot - in excessive cases (when multiple |
| 87 | * unexpected vectors occur) that might lock up the APIC |
| 88 | * completely. |
| 89 | * But don't ack when the APIC is disabled. -AK |
| 90 | */ |
| 91 | if (!disable_apic) |
| 92 | ack_APIC_irq(); |
| 93 | } |
| 94 | |
| 95 | void clear_local_APIC(void) |
| 96 | { |
| 97 | int maxlvt; |
| 98 | unsigned int v; |
| 99 | |
| 100 | maxlvt = get_maxlvt(); |
| 101 | |
| 102 | /* |
| 103 | * Masking an LVT entry on a P6 can trigger a local APIC error |
| 104 | * if the vector is zero. Mask LVTERR first to prevent this. |
| 105 | */ |
| 106 | if (maxlvt >= 3) { |
| 107 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ |
| 108 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); |
| 109 | } |
| 110 | /* |
| 111 | * Careful: we have to set masks only first to deassert |
| 112 | * any level-triggered sources. |
| 113 | */ |
| 114 | v = apic_read(APIC_LVTT); |
| 115 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); |
| 116 | v = apic_read(APIC_LVT0); |
| 117 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
| 118 | v = apic_read(APIC_LVT1); |
| 119 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); |
| 120 | if (maxlvt >= 4) { |
| 121 | v = apic_read(APIC_LVTPC); |
| 122 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); |
| 123 | } |
| 124 | |
| 125 | /* |
| 126 | * Clean APIC state for other OSs: |
| 127 | */ |
| 128 | apic_write(APIC_LVTT, APIC_LVT_MASKED); |
| 129 | apic_write(APIC_LVT0, APIC_LVT_MASKED); |
| 130 | apic_write(APIC_LVT1, APIC_LVT_MASKED); |
| 131 | if (maxlvt >= 3) |
| 132 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); |
| 133 | if (maxlvt >= 4) |
| 134 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); |
| 135 | v = GET_APIC_VERSION(apic_read(APIC_LVR)); |
| 136 | apic_write(APIC_ESR, 0); |
| 137 | apic_read(APIC_ESR); |
| 138 | } |
| 139 | |
| 140 | void __init connect_bsp_APIC(void) |
| 141 | { |
| 142 | if (pic_mode) { |
| 143 | /* |
| 144 | * Do not trust the local APIC being empty at bootup. |
| 145 | */ |
| 146 | clear_local_APIC(); |
| 147 | /* |
| 148 | * PIC mode, enable APIC mode in the IMCR, i.e. |
| 149 | * connect BSP's local APIC to INT and NMI lines. |
| 150 | */ |
| 151 | apic_printk(APIC_VERBOSE, "leaving PIC mode, enabling APIC mode.\n"); |
| 152 | outb(0x70, 0x22); |
| 153 | outb(0x01, 0x23); |
| 154 | } |
| 155 | } |
| 156 | |
| 157 | void disconnect_bsp_APIC(int virt_wire_setup) |
| 158 | { |
| 159 | if (pic_mode) { |
| 160 | /* |
| 161 | * Put the board back into PIC mode (has an effect |
| 162 | * only on certain older boards). Note that APIC |
| 163 | * interrupts, including IPIs, won't work beyond |
| 164 | * this point! The only exception are INIT IPIs. |
| 165 | */ |
| 166 | apic_printk(APIC_QUIET, "disabling APIC mode, entering PIC mode.\n"); |
| 167 | outb(0x70, 0x22); |
| 168 | outb(0x00, 0x23); |
| 169 | } |
| 170 | else { |
| 171 | /* Go back to Virtual Wire compatibility mode */ |
| 172 | unsigned long value; |
| 173 | |
| 174 | /* For the spurious interrupt use vector F, and enable it */ |
| 175 | value = apic_read(APIC_SPIV); |
| 176 | value &= ~APIC_VECTOR_MASK; |
| 177 | value |= APIC_SPIV_APIC_ENABLED; |
| 178 | value |= 0xf; |
| 179 | apic_write(APIC_SPIV, value); |
| 180 | |
| 181 | if (!virt_wire_setup) { |
| 182 | /* For LVT0 make it edge triggered, active high, external and enabled */ |
| 183 | value = apic_read(APIC_LVT0); |
| 184 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | |
| 185 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | |
| 186 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED ); |
| 187 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; |
| 188 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); |
| 189 | apic_write(APIC_LVT0, value); |
| 190 | } |
| 191 | else { |
| 192 | /* Disable LVT0 */ |
| 193 | apic_write(APIC_LVT0, APIC_LVT_MASKED); |
| 194 | } |
| 195 | |
| 196 | /* For LVT1 make it edge triggered, active high, nmi and enabled */ |
| 197 | value = apic_read(APIC_LVT1); |
| 198 | value &= ~( |
| 199 | APIC_MODE_MASK | APIC_SEND_PENDING | |
| 200 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | |
| 201 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); |
| 202 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; |
| 203 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); |
| 204 | apic_write(APIC_LVT1, value); |
| 205 | } |
| 206 | } |
| 207 | |
| 208 | void disable_local_APIC(void) |
| 209 | { |
| 210 | unsigned int value; |
| 211 | |
| 212 | clear_local_APIC(); |
| 213 | |
| 214 | /* |
| 215 | * Disable APIC (implies clearing of registers |
| 216 | * for 82489DX!). |
| 217 | */ |
| 218 | value = apic_read(APIC_SPIV); |
| 219 | value &= ~APIC_SPIV_APIC_ENABLED; |
| 220 | apic_write(APIC_SPIV, value); |
| 221 | } |
| 222 | |
| 223 | /* |
| 224 | * This is to verify that we're looking at a real local APIC. |
| 225 | * Check these against your board if the CPUs aren't getting |
| 226 | * started for no apparent reason. |
| 227 | */ |
| 228 | int __init verify_local_APIC(void) |
| 229 | { |
| 230 | unsigned int reg0, reg1; |
| 231 | |
| 232 | /* |
| 233 | * The version register is read-only in a real APIC. |
| 234 | */ |
| 235 | reg0 = apic_read(APIC_LVR); |
| 236 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); |
| 237 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); |
| 238 | reg1 = apic_read(APIC_LVR); |
| 239 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); |
| 240 | |
| 241 | /* |
| 242 | * The two version reads above should print the same |
| 243 | * numbers. If the second one is different, then we |
| 244 | * poke at a non-APIC. |
| 245 | */ |
| 246 | if (reg1 != reg0) |
| 247 | return 0; |
| 248 | |
| 249 | /* |
| 250 | * Check if the version looks reasonably. |
| 251 | */ |
| 252 | reg1 = GET_APIC_VERSION(reg0); |
| 253 | if (reg1 == 0x00 || reg1 == 0xff) |
| 254 | return 0; |
| 255 | reg1 = get_maxlvt(); |
| 256 | if (reg1 < 0x02 || reg1 == 0xff) |
| 257 | return 0; |
| 258 | |
| 259 | /* |
| 260 | * The ID register is read/write in a real APIC. |
| 261 | */ |
| 262 | reg0 = apic_read(APIC_ID); |
| 263 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); |
| 264 | apic_write(APIC_ID, reg0 ^ APIC_ID_MASK); |
| 265 | reg1 = apic_read(APIC_ID); |
| 266 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); |
| 267 | apic_write(APIC_ID, reg0); |
| 268 | if (reg1 != (reg0 ^ APIC_ID_MASK)) |
| 269 | return 0; |
| 270 | |
| 271 | /* |
| 272 | * The next two are just to see if we have sane values. |
| 273 | * They're only really relevant if we're in Virtual Wire |
| 274 | * compatibility mode, but most boxes are anymore. |
| 275 | */ |
| 276 | reg0 = apic_read(APIC_LVT0); |
| 277 | apic_printk(APIC_DEBUG,"Getting LVT0: %x\n", reg0); |
| 278 | reg1 = apic_read(APIC_LVT1); |
| 279 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); |
| 280 | |
| 281 | return 1; |
| 282 | } |
| 283 | |
| 284 | void __init sync_Arb_IDs(void) |
| 285 | { |
| 286 | /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */ |
| 287 | unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); |
| 288 | if (ver >= 0x14) /* P4 or higher */ |
| 289 | return; |
| 290 | |
| 291 | /* |
| 292 | * Wait for idle. |
| 293 | */ |
| 294 | apic_wait_icr_idle(); |
| 295 | |
| 296 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); |
| 297 | apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG |
| 298 | | APIC_DM_INIT); |
| 299 | } |
| 300 | |
| 301 | extern void __error_in_apic_c (void); |
| 302 | |
| 303 | /* |
| 304 | * An initial setup of the virtual wire mode. |
| 305 | */ |
| 306 | void __init init_bsp_APIC(void) |
| 307 | { |
| 308 | unsigned int value; |
| 309 | |
| 310 | /* |
| 311 | * Don't do the setup now if we have a SMP BIOS as the |
| 312 | * through-I/O-APIC virtual wire mode might be active. |
| 313 | */ |
| 314 | if (smp_found_config || !cpu_has_apic) |
| 315 | return; |
| 316 | |
| 317 | value = apic_read(APIC_LVR); |
| 318 | |
| 319 | /* |
| 320 | * Do not trust the local APIC being empty at bootup. |
| 321 | */ |
| 322 | clear_local_APIC(); |
| 323 | |
| 324 | /* |
| 325 | * Enable APIC. |
| 326 | */ |
| 327 | value = apic_read(APIC_SPIV); |
| 328 | value &= ~APIC_VECTOR_MASK; |
| 329 | value |= APIC_SPIV_APIC_ENABLED; |
| 330 | value |= APIC_SPIV_FOCUS_DISABLED; |
| 331 | value |= SPURIOUS_APIC_VECTOR; |
| 332 | apic_write(APIC_SPIV, value); |
| 333 | |
| 334 | /* |
| 335 | * Set up the virtual wire mode. |
| 336 | */ |
| 337 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
| 338 | value = APIC_DM_NMI; |
| 339 | apic_write(APIC_LVT1, value); |
| 340 | } |
| 341 | |
| 342 | void __cpuinit setup_local_APIC (void) |
| 343 | { |
| 344 | unsigned int value, maxlvt; |
| 345 | int i, j; |
| 346 | |
| 347 | value = apic_read(APIC_LVR); |
| 348 | |
| 349 | if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f) |
| 350 | __error_in_apic_c(); |
| 351 | |
| 352 | /* |
| 353 | * Double-check whether this APIC is really registered. |
| 354 | * This is meaningless in clustered apic mode, so we skip it. |
| 355 | */ |
| 356 | if (!apic_id_registered()) |
| 357 | BUG(); |
| 358 | |
| 359 | /* |
| 360 | * Intel recommends to set DFR, LDR and TPR before enabling |
| 361 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel |
| 362 | * document number 292116). So here it goes... |
| 363 | */ |
| 364 | init_apic_ldr(); |
| 365 | |
| 366 | /* |
| 367 | * Set Task Priority to 'accept all'. We never change this |
| 368 | * later on. |
| 369 | */ |
| 370 | value = apic_read(APIC_TASKPRI); |
| 371 | value &= ~APIC_TPRI_MASK; |
| 372 | apic_write(APIC_TASKPRI, value); |
| 373 | |
| 374 | /* |
| 375 | * After a crash, we no longer service the interrupts and a pending |
| 376 | * interrupt from previous kernel might still have ISR bit set. |
| 377 | * |
| 378 | * Most probably by now CPU has serviced that pending interrupt and |
| 379 | * it might not have done the ack_APIC_irq() because it thought, |
| 380 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it |
| 381 | * does not clear the ISR bit and cpu thinks it has already serivced |
| 382 | * the interrupt. Hence a vector might get locked. It was noticed |
| 383 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. |
| 384 | */ |
| 385 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { |
| 386 | value = apic_read(APIC_ISR + i*0x10); |
| 387 | for (j = 31; j >= 0; j--) { |
| 388 | if (value & (1<<j)) |
| 389 | ack_APIC_irq(); |
| 390 | } |
| 391 | } |
| 392 | |
| 393 | /* |
| 394 | * Now that we are all set up, enable the APIC |
| 395 | */ |
| 396 | value = apic_read(APIC_SPIV); |
| 397 | value &= ~APIC_VECTOR_MASK; |
| 398 | /* |
| 399 | * Enable APIC |
| 400 | */ |
| 401 | value |= APIC_SPIV_APIC_ENABLED; |
| 402 | |
| 403 | /* |
| 404 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with |
| 405 | * certain networking cards. If high frequency interrupts are |
| 406 | * happening on a particular IOAPIC pin, plus the IOAPIC routing |
| 407 | * entry is masked/unmasked at a high rate as well then sooner or |
| 408 | * later IOAPIC line gets 'stuck', no more interrupts are received |
| 409 | * from the device. If focus CPU is disabled then the hang goes |
| 410 | * away, oh well :-( |
| 411 | * |
| 412 | * [ This bug can be reproduced easily with a level-triggered |
| 413 | * PCI Ne2000 networking cards and PII/PIII processors, dual |
| 414 | * BX chipset. ] |
| 415 | */ |
| 416 | /* |
| 417 | * Actually disabling the focus CPU check just makes the hang less |
| 418 | * frequent as it makes the interrupt distributon model be more |
| 419 | * like LRU than MRU (the short-term load is more even across CPUs). |
| 420 | * See also the comment in end_level_ioapic_irq(). --macro |
| 421 | */ |
| 422 | #if 1 |
| 423 | /* Enable focus processor (bit==0) */ |
| 424 | value &= ~APIC_SPIV_FOCUS_DISABLED; |
| 425 | #else |
| 426 | /* Disable focus processor (bit==1) */ |
| 427 | value |= APIC_SPIV_FOCUS_DISABLED; |
| 428 | #endif |
| 429 | /* |
| 430 | * Set spurious IRQ vector |
| 431 | */ |
| 432 | value |= SPURIOUS_APIC_VECTOR; |
| 433 | apic_write(APIC_SPIV, value); |
| 434 | |
| 435 | /* |
| 436 | * Set up LVT0, LVT1: |
| 437 | * |
| 438 | * set up through-local-APIC on the BP's LINT0. This is not |
| 439 | * strictly necessary in pure symmetric-IO mode, but sometimes |
| 440 | * we delegate interrupts to the 8259A. |
| 441 | */ |
| 442 | /* |
| 443 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro |
| 444 | */ |
| 445 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; |
| 446 | if (!smp_processor_id() && (pic_mode || !value)) { |
| 447 | value = APIC_DM_EXTINT; |
| 448 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", smp_processor_id()); |
| 449 | } else { |
| 450 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; |
| 451 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", smp_processor_id()); |
| 452 | } |
| 453 | apic_write(APIC_LVT0, value); |
| 454 | |
| 455 | /* |
| 456 | * only the BP should see the LINT1 NMI signal, obviously. |
| 457 | */ |
| 458 | if (!smp_processor_id()) |
| 459 | value = APIC_DM_NMI; |
| 460 | else |
| 461 | value = APIC_DM_NMI | APIC_LVT_MASKED; |
| 462 | apic_write(APIC_LVT1, value); |
| 463 | |
| 464 | { |
| 465 | unsigned oldvalue; |
| 466 | maxlvt = get_maxlvt(); |
| 467 | oldvalue = apic_read(APIC_ESR); |
| 468 | value = ERROR_APIC_VECTOR; // enables sending errors |
| 469 | apic_write(APIC_LVTERR, value); |
| 470 | /* |
| 471 | * spec says clear errors after enabling vector. |
| 472 | */ |
| 473 | if (maxlvt > 3) |
| 474 | apic_write(APIC_ESR, 0); |
| 475 | value = apic_read(APIC_ESR); |
| 476 | if (value != oldvalue) |
| 477 | apic_printk(APIC_VERBOSE, |
| 478 | "ESR value after enabling vector: %08x, after %08x\n", |
| 479 | oldvalue, value); |
| 480 | } |
| 481 | |
| 482 | nmi_watchdog_default(); |
| 483 | if (nmi_watchdog == NMI_LOCAL_APIC) |
| 484 | setup_apic_nmi_watchdog(); |
| 485 | apic_pm_activate(); |
| 486 | } |
| 487 | |
| 488 | #ifdef CONFIG_PM |
| 489 | |
| 490 | static struct { |
| 491 | /* 'active' is true if the local APIC was enabled by us and |
| 492 | not the BIOS; this signifies that we are also responsible |
| 493 | for disabling it before entering apm/acpi suspend */ |
| 494 | int active; |
| 495 | /* r/w apic fields */ |
| 496 | unsigned int apic_id; |
| 497 | unsigned int apic_taskpri; |
| 498 | unsigned int apic_ldr; |
| 499 | unsigned int apic_dfr; |
| 500 | unsigned int apic_spiv; |
| 501 | unsigned int apic_lvtt; |
| 502 | unsigned int apic_lvtpc; |
| 503 | unsigned int apic_lvt0; |
| 504 | unsigned int apic_lvt1; |
| 505 | unsigned int apic_lvterr; |
| 506 | unsigned int apic_tmict; |
| 507 | unsigned int apic_tdcr; |
| 508 | unsigned int apic_thmr; |
| 509 | } apic_pm_state; |
| 510 | |
| 511 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) |
| 512 | { |
| 513 | unsigned long flags; |
| 514 | |
| 515 | if (!apic_pm_state.active) |
| 516 | return 0; |
| 517 | |
| 518 | apic_pm_state.apic_id = apic_read(APIC_ID); |
| 519 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
| 520 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); |
| 521 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); |
| 522 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); |
| 523 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); |
| 524 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); |
| 525 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); |
| 526 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); |
| 527 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); |
| 528 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); |
| 529 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); |
| 530 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); |
| 531 | local_save_flags(flags); |
| 532 | local_irq_disable(); |
| 533 | disable_local_APIC(); |
| 534 | local_irq_restore(flags); |
| 535 | return 0; |
| 536 | } |
| 537 | |
| 538 | static int lapic_resume(struct sys_device *dev) |
| 539 | { |
| 540 | unsigned int l, h; |
| 541 | unsigned long flags; |
| 542 | |
| 543 | if (!apic_pm_state.active) |
| 544 | return 0; |
| 545 | |
| 546 | local_irq_save(flags); |
| 547 | rdmsr(MSR_IA32_APICBASE, l, h); |
| 548 | l &= ~MSR_IA32_APICBASE_BASE; |
| 549 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; |
| 550 | wrmsr(MSR_IA32_APICBASE, l, h); |
| 551 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); |
| 552 | apic_write(APIC_ID, apic_pm_state.apic_id); |
| 553 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); |
| 554 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); |
| 555 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); |
| 556 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); |
| 557 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); |
| 558 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); |
| 559 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); |
| 560 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); |
| 561 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); |
| 562 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); |
| 563 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); |
| 564 | apic_write(APIC_ESR, 0); |
| 565 | apic_read(APIC_ESR); |
| 566 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); |
| 567 | apic_write(APIC_ESR, 0); |
| 568 | apic_read(APIC_ESR); |
| 569 | local_irq_restore(flags); |
| 570 | return 0; |
| 571 | } |
| 572 | |
| 573 | static struct sysdev_class lapic_sysclass = { |
| 574 | set_kset_name("lapic"), |
| 575 | .resume = lapic_resume, |
| 576 | .suspend = lapic_suspend, |
| 577 | }; |
| 578 | |
| 579 | static struct sys_device device_lapic = { |
| 580 | .id = 0, |
| 581 | .cls = &lapic_sysclass, |
| 582 | }; |
| 583 | |
| 584 | static void __cpuinit apic_pm_activate(void) |
| 585 | { |
| 586 | apic_pm_state.active = 1; |
| 587 | } |
| 588 | |
| 589 | static int __init init_lapic_sysfs(void) |
| 590 | { |
| 591 | int error; |
| 592 | if (!cpu_has_apic) |
| 593 | return 0; |
| 594 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ |
| 595 | error = sysdev_class_register(&lapic_sysclass); |
| 596 | if (!error) |
| 597 | error = sysdev_register(&device_lapic); |
| 598 | return error; |
| 599 | } |
| 600 | device_initcall(init_lapic_sysfs); |
| 601 | |
| 602 | #else /* CONFIG_PM */ |
| 603 | |
| 604 | static void apic_pm_activate(void) { } |
| 605 | |
| 606 | #endif /* CONFIG_PM */ |
| 607 | |
| 608 | static int __init apic_set_verbosity(char *str) |
| 609 | { |
| 610 | if (strcmp("debug", str) == 0) |
| 611 | apic_verbosity = APIC_DEBUG; |
| 612 | else if (strcmp("verbose", str) == 0) |
| 613 | apic_verbosity = APIC_VERBOSE; |
| 614 | else |
| 615 | printk(KERN_WARNING "APIC Verbosity level %s not recognised" |
| 616 | " use apic=verbose or apic=debug", str); |
| 617 | |
| 618 | return 1; |
| 619 | } |
| 620 | |
| 621 | __setup("apic=", apic_set_verbosity); |
| 622 | |
| 623 | /* |
| 624 | * Detect and enable local APICs on non-SMP boards. |
| 625 | * Original code written by Keir Fraser. |
| 626 | * On AMD64 we trust the BIOS - if it says no APIC it is likely |
| 627 | * not correctly set up (usually the APIC timer won't work etc.) |
| 628 | */ |
| 629 | |
| 630 | static int __init detect_init_APIC (void) |
| 631 | { |
| 632 | if (!cpu_has_apic) { |
| 633 | printk(KERN_INFO "No local APIC present\n"); |
| 634 | return -1; |
| 635 | } |
| 636 | |
| 637 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; |
| 638 | boot_cpu_id = 0; |
| 639 | return 0; |
| 640 | } |
| 641 | |
| 642 | void __init init_apic_mappings(void) |
| 643 | { |
| 644 | unsigned long apic_phys; |
| 645 | |
| 646 | /* |
| 647 | * If no local APIC can be found then set up a fake all |
| 648 | * zeroes page to simulate the local APIC and another |
| 649 | * one for the IO-APIC. |
| 650 | */ |
| 651 | if (!smp_found_config && detect_init_APIC()) { |
| 652 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); |
| 653 | apic_phys = __pa(apic_phys); |
| 654 | } else |
| 655 | apic_phys = mp_lapic_addr; |
| 656 | |
| 657 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); |
| 658 | apic_printk(APIC_VERBOSE,"mapped APIC to %16lx (%16lx)\n", APIC_BASE, apic_phys); |
| 659 | |
| 660 | /* |
| 661 | * Fetch the APIC ID of the BSP in case we have a |
| 662 | * default configuration (or the MP table is broken). |
| 663 | */ |
| 664 | boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID)); |
| 665 | |
| 666 | #ifdef CONFIG_X86_IO_APIC |
| 667 | { |
| 668 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; |
| 669 | int i; |
| 670 | |
| 671 | for (i = 0; i < nr_ioapics; i++) { |
| 672 | if (smp_found_config) { |
| 673 | ioapic_phys = mp_ioapics[i].mpc_apicaddr; |
| 674 | } else { |
| 675 | ioapic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); |
| 676 | ioapic_phys = __pa(ioapic_phys); |
| 677 | } |
| 678 | set_fixmap_nocache(idx, ioapic_phys); |
| 679 | apic_printk(APIC_VERBOSE,"mapped IOAPIC to %016lx (%016lx)\n", |
| 680 | __fix_to_virt(idx), ioapic_phys); |
| 681 | idx++; |
| 682 | } |
| 683 | } |
| 684 | #endif |
| 685 | } |
| 686 | |
| 687 | /* |
| 688 | * This function sets up the local APIC timer, with a timeout of |
| 689 | * 'clocks' APIC bus clock. During calibration we actually call |
| 690 | * this function twice on the boot CPU, once with a bogus timeout |
| 691 | * value, second time for real. The other (noncalibrating) CPUs |
| 692 | * call this function only once, with the real, calibrated value. |
| 693 | * |
| 694 | * We do reads before writes even if unnecessary, to get around the |
| 695 | * P5 APIC double write bug. |
| 696 | */ |
| 697 | |
| 698 | #define APIC_DIVISOR 16 |
| 699 | |
| 700 | static void __setup_APIC_LVTT(unsigned int clocks) |
| 701 | { |
| 702 | unsigned int lvtt_value, tmp_value, ver; |
| 703 | int cpu = smp_processor_id(); |
| 704 | |
| 705 | ver = GET_APIC_VERSION(apic_read(APIC_LVR)); |
| 706 | lvtt_value = APIC_LVT_TIMER_PERIODIC | LOCAL_TIMER_VECTOR; |
| 707 | |
| 708 | if (cpu_isset(cpu, timer_interrupt_broadcast_ipi_mask)) |
| 709 | lvtt_value |= APIC_LVT_MASKED; |
| 710 | |
| 711 | apic_write(APIC_LVTT, lvtt_value); |
| 712 | |
| 713 | /* |
| 714 | * Divide PICLK by 16 |
| 715 | */ |
| 716 | tmp_value = apic_read(APIC_TDCR); |
| 717 | apic_write(APIC_TDCR, (tmp_value |
| 718 | & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
| 719 | | APIC_TDR_DIV_16); |
| 720 | |
| 721 | apic_write(APIC_TMICT, clocks/APIC_DIVISOR); |
| 722 | } |
| 723 | |
| 724 | static void setup_APIC_timer(unsigned int clocks) |
| 725 | { |
| 726 | unsigned long flags; |
| 727 | |
| 728 | local_irq_save(flags); |
| 729 | |
| 730 | /* wait for irq slice */ |
| 731 | if (vxtime.hpet_address && hpet_use_timer) { |
| 732 | int trigger = hpet_readl(HPET_T0_CMP); |
| 733 | while (hpet_readl(HPET_COUNTER) >= trigger) |
| 734 | /* do nothing */ ; |
| 735 | while (hpet_readl(HPET_COUNTER) < trigger) |
| 736 | /* do nothing */ ; |
| 737 | } else { |
| 738 | int c1, c2; |
| 739 | outb_p(0x00, 0x43); |
| 740 | c2 = inb_p(0x40); |
| 741 | c2 |= inb_p(0x40) << 8; |
| 742 | do { |
| 743 | c1 = c2; |
| 744 | outb_p(0x00, 0x43); |
| 745 | c2 = inb_p(0x40); |
| 746 | c2 |= inb_p(0x40) << 8; |
| 747 | } while (c2 - c1 < 300); |
| 748 | } |
| 749 | __setup_APIC_LVTT(clocks); |
| 750 | /* Turn off PIT interrupt if we use APIC timer as main timer. |
| 751 | Only works with the PM timer right now |
| 752 | TBD fix it for HPET too. */ |
| 753 | if (vxtime.mode == VXTIME_PMTMR && |
| 754 | smp_processor_id() == boot_cpu_id && |
| 755 | apic_runs_main_timer == 1 && |
| 756 | !cpu_isset(boot_cpu_id, timer_interrupt_broadcast_ipi_mask)) { |
| 757 | stop_timer_interrupt(); |
| 758 | apic_runs_main_timer++; |
| 759 | } |
| 760 | local_irq_restore(flags); |
| 761 | } |
| 762 | |
| 763 | /* |
| 764 | * In this function we calibrate APIC bus clocks to the external |
| 765 | * timer. Unfortunately we cannot use jiffies and the timer irq |
| 766 | * to calibrate, since some later bootup code depends on getting |
| 767 | * the first irq? Ugh. |
| 768 | * |
| 769 | * We want to do the calibration only once since we |
| 770 | * want to have local timer irqs syncron. CPUs connected |
| 771 | * by the same APIC bus have the very same bus frequency. |
| 772 | * And we want to have irqs off anyways, no accidental |
| 773 | * APIC irq that way. |
| 774 | */ |
| 775 | |
| 776 | #define TICK_COUNT 100000000 |
| 777 | |
| 778 | static int __init calibrate_APIC_clock(void) |
| 779 | { |
| 780 | int apic, apic_start, tsc, tsc_start; |
| 781 | int result; |
| 782 | /* |
| 783 | * Put whatever arbitrary (but long enough) timeout |
| 784 | * value into the APIC clock, we just want to get the |
| 785 | * counter running for calibration. |
| 786 | */ |
| 787 | __setup_APIC_LVTT(1000000000); |
| 788 | |
| 789 | apic_start = apic_read(APIC_TMCCT); |
| 790 | #ifdef CONFIG_X86_PM_TIMER |
| 791 | if (apic_calibrate_pmtmr && pmtmr_ioport) { |
| 792 | pmtimer_wait(5000); /* 5ms wait */ |
| 793 | apic = apic_read(APIC_TMCCT); |
| 794 | result = (apic_start - apic) * 1000L / 5; |
| 795 | } else |
| 796 | #endif |
| 797 | { |
| 798 | rdtscl(tsc_start); |
| 799 | |
| 800 | do { |
| 801 | apic = apic_read(APIC_TMCCT); |
| 802 | rdtscl(tsc); |
| 803 | } while ((tsc - tsc_start) < TICK_COUNT && |
| 804 | (apic - apic_start) < TICK_COUNT); |
| 805 | |
| 806 | result = (apic_start - apic) * 1000L * cpu_khz / |
| 807 | (tsc - tsc_start); |
| 808 | } |
| 809 | printk("result %d\n", result); |
| 810 | |
| 811 | |
| 812 | printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n", |
| 813 | result / 1000 / 1000, result / 1000 % 1000); |
| 814 | |
| 815 | return result * APIC_DIVISOR / HZ; |
| 816 | } |
| 817 | |
| 818 | static unsigned int calibration_result; |
| 819 | |
| 820 | void __init setup_boot_APIC_clock (void) |
| 821 | { |
| 822 | if (disable_apic_timer) { |
| 823 | printk(KERN_INFO "Disabling APIC timer\n"); |
| 824 | return; |
| 825 | } |
| 826 | |
| 827 | printk(KERN_INFO "Using local APIC timer interrupts.\n"); |
| 828 | using_apic_timer = 1; |
| 829 | |
| 830 | local_irq_disable(); |
| 831 | |
| 832 | calibration_result = calibrate_APIC_clock(); |
| 833 | /* |
| 834 | * Now set up the timer for real. |
| 835 | */ |
| 836 | setup_APIC_timer(calibration_result); |
| 837 | |
| 838 | local_irq_enable(); |
| 839 | } |
| 840 | |
| 841 | void __cpuinit setup_secondary_APIC_clock(void) |
| 842 | { |
| 843 | local_irq_disable(); /* FIXME: Do we need this? --RR */ |
| 844 | setup_APIC_timer(calibration_result); |
| 845 | local_irq_enable(); |
| 846 | } |
| 847 | |
| 848 | void disable_APIC_timer(void) |
| 849 | { |
| 850 | if (using_apic_timer) { |
| 851 | unsigned long v; |
| 852 | |
| 853 | v = apic_read(APIC_LVTT); |
| 854 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); |
| 855 | } |
| 856 | } |
| 857 | |
| 858 | void enable_APIC_timer(void) |
| 859 | { |
| 860 | int cpu = smp_processor_id(); |
| 861 | |
| 862 | if (using_apic_timer && |
| 863 | !cpu_isset(cpu, timer_interrupt_broadcast_ipi_mask)) { |
| 864 | unsigned long v; |
| 865 | |
| 866 | v = apic_read(APIC_LVTT); |
| 867 | apic_write(APIC_LVTT, v & ~APIC_LVT_MASKED); |
| 868 | } |
| 869 | } |
| 870 | |
| 871 | void switch_APIC_timer_to_ipi(void *cpumask) |
| 872 | { |
| 873 | cpumask_t mask = *(cpumask_t *)cpumask; |
| 874 | int cpu = smp_processor_id(); |
| 875 | |
| 876 | if (cpu_isset(cpu, mask) && |
| 877 | !cpu_isset(cpu, timer_interrupt_broadcast_ipi_mask)) { |
| 878 | disable_APIC_timer(); |
| 879 | cpu_set(cpu, timer_interrupt_broadcast_ipi_mask); |
| 880 | } |
| 881 | } |
| 882 | EXPORT_SYMBOL(switch_APIC_timer_to_ipi); |
| 883 | |
| 884 | void smp_send_timer_broadcast_ipi(void) |
| 885 | { |
| 886 | cpumask_t mask; |
| 887 | |
| 888 | cpus_and(mask, cpu_online_map, timer_interrupt_broadcast_ipi_mask); |
| 889 | if (!cpus_empty(mask)) { |
| 890 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); |
| 891 | } |
| 892 | } |
| 893 | |
| 894 | void switch_ipi_to_APIC_timer(void *cpumask) |
| 895 | { |
| 896 | cpumask_t mask = *(cpumask_t *)cpumask; |
| 897 | int cpu = smp_processor_id(); |
| 898 | |
| 899 | if (cpu_isset(cpu, mask) && |
| 900 | cpu_isset(cpu, timer_interrupt_broadcast_ipi_mask)) { |
| 901 | cpu_clear(cpu, timer_interrupt_broadcast_ipi_mask); |
| 902 | enable_APIC_timer(); |
| 903 | } |
| 904 | } |
| 905 | EXPORT_SYMBOL(switch_ipi_to_APIC_timer); |
| 906 | |
| 907 | int setup_profiling_timer(unsigned int multiplier) |
| 908 | { |
| 909 | return -EINVAL; |
| 910 | } |
| 911 | |
| 912 | #ifdef CONFIG_X86_MCE_AMD |
| 913 | void setup_threshold_lvt(unsigned long lvt_off) |
| 914 | { |
| 915 | unsigned int v = 0; |
| 916 | unsigned long reg = (lvt_off << 4) + 0x500; |
| 917 | v |= THRESHOLD_APIC_VECTOR; |
| 918 | apic_write(reg, v); |
| 919 | } |
| 920 | #endif /* CONFIG_X86_MCE_AMD */ |
| 921 | |
| 922 | #undef APIC_DIVISOR |
| 923 | |
| 924 | /* |
| 925 | * Local timer interrupt handler. It does both profiling and |
| 926 | * process statistics/rescheduling. |
| 927 | * |
| 928 | * We do profiling in every local tick, statistics/rescheduling |
| 929 | * happen only every 'profiling multiplier' ticks. The default |
| 930 | * multiplier is 1 and it can be changed by writing the new multiplier |
| 931 | * value into /proc/profile. |
| 932 | */ |
| 933 | |
| 934 | void smp_local_timer_interrupt(struct pt_regs *regs) |
| 935 | { |
| 936 | profile_tick(CPU_PROFILING, regs); |
| 937 | #ifdef CONFIG_SMP |
| 938 | update_process_times(user_mode(regs)); |
| 939 | #endif |
| 940 | if (apic_runs_main_timer > 1 && smp_processor_id() == boot_cpu_id) |
| 941 | main_timer_handler(regs); |
| 942 | /* |
| 943 | * We take the 'long' return path, and there every subsystem |
| 944 | * grabs the appropriate locks (kernel lock/ irq lock). |
| 945 | * |
| 946 | * we might want to decouple profiling from the 'long path', |
| 947 | * and do the profiling totally in assembly. |
| 948 | * |
| 949 | * Currently this isn't too much of an issue (performance wise), |
| 950 | * we can take more than 100K local irqs per second on a 100 MHz P5. |
| 951 | */ |
| 952 | } |
| 953 | |
| 954 | /* |
| 955 | * Local APIC timer interrupt. This is the most natural way for doing |
| 956 | * local interrupts, but local timer interrupts can be emulated by |
| 957 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] |
| 958 | * |
| 959 | * [ if a single-CPU system runs an SMP kernel then we call the local |
| 960 | * interrupt as well. Thus we cannot inline the local irq ... ] |
| 961 | */ |
| 962 | void smp_apic_timer_interrupt(struct pt_regs *regs) |
| 963 | { |
| 964 | /* |
| 965 | * the NMI deadlock-detector uses this. |
| 966 | */ |
| 967 | add_pda(apic_timer_irqs, 1); |
| 968 | |
| 969 | /* |
| 970 | * NOTE! We'd better ACK the irq immediately, |
| 971 | * because timer handling can be slow. |
| 972 | */ |
| 973 | ack_APIC_irq(); |
| 974 | /* |
| 975 | * update_process_times() expects us to have done irq_enter(). |
| 976 | * Besides, if we don't timer interrupts ignore the global |
| 977 | * interrupt lock, which is the WrongThing (tm) to do. |
| 978 | */ |
| 979 | exit_idle(); |
| 980 | irq_enter(); |
| 981 | smp_local_timer_interrupt(regs); |
| 982 | irq_exit(); |
| 983 | } |
| 984 | |
| 985 | /* |
| 986 | * oem_force_hpet_timer -- force HPET mode for some boxes. |
| 987 | * |
| 988 | * Thus far, the major user of this is IBM's Summit2 series: |
| 989 | * |
| 990 | * Clustered boxes may have unsynced TSC problems if they are |
| 991 | * multi-chassis. Use available data to take a good guess. |
| 992 | * If in doubt, go HPET. |
| 993 | */ |
| 994 | __cpuinit int oem_force_hpet_timer(void) |
| 995 | { |
| 996 | int i, clusters, zeros; |
| 997 | unsigned id; |
| 998 | DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); |
| 999 | |
| 1000 | bitmap_zero(clustermap, NUM_APIC_CLUSTERS); |
| 1001 | |
| 1002 | for (i = 0; i < NR_CPUS; i++) { |
| 1003 | id = bios_cpu_apicid[i]; |
| 1004 | if (id != BAD_APICID) |
| 1005 | __set_bit(APIC_CLUSTERID(id), clustermap); |
| 1006 | } |
| 1007 | |
| 1008 | /* Problem: Partially populated chassis may not have CPUs in some of |
| 1009 | * the APIC clusters they have been allocated. Only present CPUs have |
| 1010 | * bios_cpu_apicid entries, thus causing zeroes in the bitmap. Since |
| 1011 | * clusters are allocated sequentially, count zeros only if they are |
| 1012 | * bounded by ones. |
| 1013 | */ |
| 1014 | clusters = 0; |
| 1015 | zeros = 0; |
| 1016 | for (i = 0; i < NUM_APIC_CLUSTERS; i++) { |
| 1017 | if (test_bit(i, clustermap)) { |
| 1018 | clusters += 1 + zeros; |
| 1019 | zeros = 0; |
| 1020 | } else |
| 1021 | ++zeros; |
| 1022 | } |
| 1023 | |
| 1024 | /* |
| 1025 | * If clusters > 2, then should be multi-chassis. Return 1 for HPET. |
| 1026 | * Else return 0 to use TSC. |
| 1027 | * May have to revisit this when multi-core + hyperthreaded CPUs come |
| 1028 | * out, but AFAIK this will work even for them. |
| 1029 | */ |
| 1030 | return (clusters > 2); |
| 1031 | } |
| 1032 | |
| 1033 | /* |
| 1034 | * This interrupt should _never_ happen with our APIC/SMP architecture |
| 1035 | */ |
| 1036 | asmlinkage void smp_spurious_interrupt(void) |
| 1037 | { |
| 1038 | unsigned int v; |
| 1039 | exit_idle(); |
| 1040 | irq_enter(); |
| 1041 | /* |
| 1042 | * Check if this really is a spurious interrupt and ACK it |
| 1043 | * if it is a vectored one. Just in case... |
| 1044 | * Spurious interrupts should not be ACKed. |
| 1045 | */ |
| 1046 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); |
| 1047 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) |
| 1048 | ack_APIC_irq(); |
| 1049 | |
| 1050 | #if 0 |
| 1051 | static unsigned long last_warning; |
| 1052 | static unsigned long skipped; |
| 1053 | |
| 1054 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ |
| 1055 | if (time_before(last_warning+30*HZ,jiffies)) { |
| 1056 | printk(KERN_INFO "spurious APIC interrupt on CPU#%d, %ld skipped.\n", |
| 1057 | smp_processor_id(), skipped); |
| 1058 | last_warning = jiffies; |
| 1059 | skipped = 0; |
| 1060 | } else { |
| 1061 | skipped++; |
| 1062 | } |
| 1063 | #endif |
| 1064 | irq_exit(); |
| 1065 | } |
| 1066 | |
| 1067 | /* |
| 1068 | * This interrupt should never happen with our APIC/SMP architecture |
| 1069 | */ |
| 1070 | |
| 1071 | asmlinkage void smp_error_interrupt(void) |
| 1072 | { |
| 1073 | unsigned int v, v1; |
| 1074 | |
| 1075 | exit_idle(); |
| 1076 | irq_enter(); |
| 1077 | /* First tickle the hardware, only then report what went on. -- REW */ |
| 1078 | v = apic_read(APIC_ESR); |
| 1079 | apic_write(APIC_ESR, 0); |
| 1080 | v1 = apic_read(APIC_ESR); |
| 1081 | ack_APIC_irq(); |
| 1082 | atomic_inc(&irq_err_count); |
| 1083 | |
| 1084 | /* Here is what the APIC error bits mean: |
| 1085 | 0: Send CS error |
| 1086 | 1: Receive CS error |
| 1087 | 2: Send accept error |
| 1088 | 3: Receive accept error |
| 1089 | 4: Reserved |
| 1090 | 5: Send illegal vector |
| 1091 | 6: Received illegal vector |
| 1092 | 7: Illegal register address |
| 1093 | */ |
| 1094 | printk (KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n", |
| 1095 | smp_processor_id(), v , v1); |
| 1096 | irq_exit(); |
| 1097 | } |
| 1098 | |
| 1099 | int disable_apic; |
| 1100 | |
| 1101 | /* |
| 1102 | * This initializes the IO-APIC and APIC hardware if this is |
| 1103 | * a UP kernel. |
| 1104 | */ |
| 1105 | int __init APIC_init_uniprocessor (void) |
| 1106 | { |
| 1107 | if (disable_apic) { |
| 1108 | printk(KERN_INFO "Apic disabled\n"); |
| 1109 | return -1; |
| 1110 | } |
| 1111 | if (!cpu_has_apic) { |
| 1112 | disable_apic = 1; |
| 1113 | printk(KERN_INFO "Apic disabled by BIOS\n"); |
| 1114 | return -1; |
| 1115 | } |
| 1116 | |
| 1117 | verify_local_APIC(); |
| 1118 | |
| 1119 | connect_bsp_APIC(); |
| 1120 | |
| 1121 | phys_cpu_present_map = physid_mask_of_physid(boot_cpu_id); |
| 1122 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_id)); |
| 1123 | |
| 1124 | setup_local_APIC(); |
| 1125 | |
| 1126 | #ifdef CONFIG_X86_IO_APIC |
| 1127 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) |
| 1128 | setup_IO_APIC(); |
| 1129 | else |
| 1130 | nr_ioapics = 0; |
| 1131 | #endif |
| 1132 | setup_boot_APIC_clock(); |
| 1133 | check_nmi_watchdog(); |
| 1134 | return 0; |
| 1135 | } |
| 1136 | |
| 1137 | static __init int setup_disableapic(char *str) |
| 1138 | { |
| 1139 | disable_apic = 1; |
| 1140 | return 1; |
| 1141 | } |
| 1142 | |
| 1143 | static __init int setup_nolapic(char *str) |
| 1144 | { |
| 1145 | disable_apic = 1; |
| 1146 | return 1; |
| 1147 | } |
| 1148 | |
| 1149 | static __init int setup_noapictimer(char *str) |
| 1150 | { |
| 1151 | if (str[0] != ' ' && str[0] != 0) |
| 1152 | return 0; |
| 1153 | disable_apic_timer = 1; |
| 1154 | return 1; |
| 1155 | } |
| 1156 | |
| 1157 | static __init int setup_apicmaintimer(char *str) |
| 1158 | { |
| 1159 | apic_runs_main_timer = 1; |
| 1160 | nohpet = 1; |
| 1161 | return 1; |
| 1162 | } |
| 1163 | __setup("apicmaintimer", setup_apicmaintimer); |
| 1164 | |
| 1165 | static __init int setup_noapicmaintimer(char *str) |
| 1166 | { |
| 1167 | apic_runs_main_timer = -1; |
| 1168 | return 1; |
| 1169 | } |
| 1170 | __setup("noapicmaintimer", setup_noapicmaintimer); |
| 1171 | |
| 1172 | static __init int setup_apicpmtimer(char *s) |
| 1173 | { |
| 1174 | apic_calibrate_pmtmr = 1; |
| 1175 | notsc_setup(NULL); |
| 1176 | return setup_apicmaintimer(NULL); |
| 1177 | } |
| 1178 | __setup("apicpmtimer", setup_apicpmtimer); |
| 1179 | |
| 1180 | /* dummy parsing: see setup.c */ |
| 1181 | |
| 1182 | __setup("disableapic", setup_disableapic); |
| 1183 | __setup("nolapic", setup_nolapic); /* same as disableapic, for compatibility */ |
| 1184 | |
| 1185 | __setup("noapictimer", setup_noapictimer); |
| 1186 | |
| 1187 | /* no "lapic" flag - we only use the lapic when the BIOS tells us so. */ |