| 1 | /* Xtensa configuration-specific ISA information. |
| 2 | Copyright 2003, 2004, 2005, 2007 Free Software Foundation, Inc. |
| 3 | |
| 4 | This file is part of BFD, the Binary File Descriptor library. |
| 5 | |
| 6 | This program is free software; you can redistribute it and/or |
| 7 | modify it under the terms of the GNU General Public License as |
| 8 | published by the Free Software Foundation; either version 3 of the |
| 9 | License, or (at your option) any later version. |
| 10 | |
| 11 | This program is distributed in the hope that it will be useful, |
| 12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | General Public License for more details. |
| 15 | |
| 16 | You should have received a copy of the GNU General Public License |
| 17 | along with this program; if not, write to the Free Software |
| 18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA |
| 19 | 02110-1301, USA. */ |
| 20 | |
| 21 | #include "ansidecl.h" |
| 22 | #include <xtensa-isa.h> |
| 23 | #include "xtensa-isa-internal.h" |
| 24 | |
| 25 | \f |
| 26 | /* Sysregs. */ |
| 27 | |
| 28 | static xtensa_sysreg_internal sysregs[] = { |
| 29 | { "LBEG", 0, 0 }, |
| 30 | { "LEND", 1, 0 }, |
| 31 | { "LCOUNT", 2, 0 }, |
| 32 | { "PTEVADDR", 83, 0 }, |
| 33 | { "DDR", 104, 0 }, |
| 34 | { "176", 176, 0 }, |
| 35 | { "208", 208, 0 }, |
| 36 | { "INTERRUPT", 226, 0 }, |
| 37 | { "INTCLEAR", 227, 0 }, |
| 38 | { "CCOUNT", 234, 0 }, |
| 39 | { "PRID", 235, 0 }, |
| 40 | { "ICOUNT", 236, 0 }, |
| 41 | { "CCOMPARE0", 240, 0 }, |
| 42 | { "CCOMPARE1", 241, 0 }, |
| 43 | { "CCOMPARE2", 242, 0 }, |
| 44 | { "EPC1", 177, 0 }, |
| 45 | { "EPC2", 178, 0 }, |
| 46 | { "EPC3", 179, 0 }, |
| 47 | { "EPC4", 180, 0 }, |
| 48 | { "EXCSAVE1", 209, 0 }, |
| 49 | { "EXCSAVE2", 210, 0 }, |
| 50 | { "EXCSAVE3", 211, 0 }, |
| 51 | { "EXCSAVE4", 212, 0 }, |
| 52 | { "EPS2", 194, 0 }, |
| 53 | { "EPS3", 195, 0 }, |
| 54 | { "EPS4", 196, 0 }, |
| 55 | { "EXCCAUSE", 232, 0 }, |
| 56 | { "DEPC", 192, 0 }, |
| 57 | { "EXCVADDR", 238, 0 }, |
| 58 | { "WINDOWBASE", 72, 0 }, |
| 59 | { "WINDOWSTART", 73, 0 }, |
| 60 | { "SAR", 3, 0 }, |
| 61 | { "LITBASE", 5, 0 }, |
| 62 | { "PS", 230, 0 }, |
| 63 | { "MISC0", 244, 0 }, |
| 64 | { "MISC1", 245, 0 }, |
| 65 | { "INTENABLE", 228, 0 }, |
| 66 | { "DBREAKA0", 144, 0 }, |
| 67 | { "DBREAKC0", 160, 0 }, |
| 68 | { "DBREAKA1", 145, 0 }, |
| 69 | { "DBREAKC1", 161, 0 }, |
| 70 | { "IBREAKA0", 128, 0 }, |
| 71 | { "IBREAKA1", 129, 0 }, |
| 72 | { "IBREAKENABLE", 96, 0 }, |
| 73 | { "ICOUNTLEVEL", 237, 0 }, |
| 74 | { "DEBUGCAUSE", 233, 0 }, |
| 75 | { "RASID", 90, 0 }, |
| 76 | { "ITLBCFG", 91, 0 }, |
| 77 | { "DTLBCFG", 92, 0 } |
| 78 | }; |
| 79 | |
| 80 | #define NUM_SYSREGS 49 |
| 81 | #define MAX_SPECIAL_REG 245 |
| 82 | #define MAX_USER_REG 0 |
| 83 | |
| 84 | \f |
| 85 | /* Processor states. */ |
| 86 | |
| 87 | static xtensa_state_internal states[] = { |
| 88 | { "LCOUNT", 32, 0 }, |
| 89 | { "PC", 32, 0 }, |
| 90 | { "ICOUNT", 32, 0 }, |
| 91 | { "DDR", 32, 0 }, |
| 92 | { "INTERRUPT", 17, 0 }, |
| 93 | { "CCOUNT", 32, 0 }, |
| 94 | { "XTSYNC", 1, 0 }, |
| 95 | { "EPC1", 32, 0 }, |
| 96 | { "EPC2", 32, 0 }, |
| 97 | { "EPC3", 32, 0 }, |
| 98 | { "EPC4", 32, 0 }, |
| 99 | { "EXCSAVE1", 32, 0 }, |
| 100 | { "EXCSAVE2", 32, 0 }, |
| 101 | { "EXCSAVE3", 32, 0 }, |
| 102 | { "EXCSAVE4", 32, 0 }, |
| 103 | { "EPS2", 15, 0 }, |
| 104 | { "EPS3", 15, 0 }, |
| 105 | { "EPS4", 15, 0 }, |
| 106 | { "EXCCAUSE", 6, 0 }, |
| 107 | { "PSINTLEVEL", 4, 0 }, |
| 108 | { "PSUM", 1, 0 }, |
| 109 | { "PSWOE", 1, 0 }, |
| 110 | { "PSRING", 2, 0 }, |
| 111 | { "PSEXCM", 1, 0 }, |
| 112 | { "DEPC", 32, 0 }, |
| 113 | { "EXCVADDR", 32, 0 }, |
| 114 | { "WindowBase", 4, 0 }, |
| 115 | { "WindowStart", 16, 0 }, |
| 116 | { "PSCALLINC", 2, 0 }, |
| 117 | { "PSOWB", 4, 0 }, |
| 118 | { "LBEG", 32, 0 }, |
| 119 | { "LEND", 32, 0 }, |
| 120 | { "SAR", 6, 0 }, |
| 121 | { "LITBADDR", 20, 0 }, |
| 122 | { "LITBEN", 1, 0 }, |
| 123 | { "MISC0", 32, 0 }, |
| 124 | { "MISC1", 32, 0 }, |
| 125 | { "InOCDMode", 1, 0 }, |
| 126 | { "INTENABLE", 17, 0 }, |
| 127 | { "DBREAKA0", 32, 0 }, |
| 128 | { "DBREAKC0", 8, 0 }, |
| 129 | { "DBREAKA1", 32, 0 }, |
| 130 | { "DBREAKC1", 8, 0 }, |
| 131 | { "IBREAKA0", 32, 0 }, |
| 132 | { "IBREAKA1", 32, 0 }, |
| 133 | { "IBREAKENABLE", 2, 0 }, |
| 134 | { "ICOUNTLEVEL", 4, 0 }, |
| 135 | { "DEBUGCAUSE", 6, 0 }, |
| 136 | { "DBNUM", 4, 0 }, |
| 137 | { "CCOMPARE0", 32, 0 }, |
| 138 | { "CCOMPARE1", 32, 0 }, |
| 139 | { "CCOMPARE2", 32, 0 }, |
| 140 | { "ASID3", 8, 0 }, |
| 141 | { "ASID2", 8, 0 }, |
| 142 | { "ASID1", 8, 0 }, |
| 143 | { "INSTPGSZID4", 2, 0 }, |
| 144 | { "DATAPGSZID4", 2, 0 }, |
| 145 | { "PTBASE", 10, 0 } |
| 146 | }; |
| 147 | |
| 148 | #define NUM_STATES 58 |
| 149 | |
| 150 | /* Macros for xtensa_state numbers (for use in iclasses because the |
| 151 | state numbers are not available when the iclass table is generated). */ |
| 152 | |
| 153 | #define STATE_LCOUNT 0 |
| 154 | #define STATE_PC 1 |
| 155 | #define STATE_ICOUNT 2 |
| 156 | #define STATE_DDR 3 |
| 157 | #define STATE_INTERRUPT 4 |
| 158 | #define STATE_CCOUNT 5 |
| 159 | #define STATE_XTSYNC 6 |
| 160 | #define STATE_EPC1 7 |
| 161 | #define STATE_EPC2 8 |
| 162 | #define STATE_EPC3 9 |
| 163 | #define STATE_EPC4 10 |
| 164 | #define STATE_EXCSAVE1 11 |
| 165 | #define STATE_EXCSAVE2 12 |
| 166 | #define STATE_EXCSAVE3 13 |
| 167 | #define STATE_EXCSAVE4 14 |
| 168 | #define STATE_EPS2 15 |
| 169 | #define STATE_EPS3 16 |
| 170 | #define STATE_EPS4 17 |
| 171 | #define STATE_EXCCAUSE 18 |
| 172 | #define STATE_PSINTLEVEL 19 |
| 173 | #define STATE_PSUM 20 |
| 174 | #define STATE_PSWOE 21 |
| 175 | #define STATE_PSRING 22 |
| 176 | #define STATE_PSEXCM 23 |
| 177 | #define STATE_DEPC 24 |
| 178 | #define STATE_EXCVADDR 25 |
| 179 | #define STATE_WindowBase 26 |
| 180 | #define STATE_WindowStart 27 |
| 181 | #define STATE_PSCALLINC 28 |
| 182 | #define STATE_PSOWB 29 |
| 183 | #define STATE_LBEG 30 |
| 184 | #define STATE_LEND 31 |
| 185 | #define STATE_SAR 32 |
| 186 | #define STATE_LITBADDR 33 |
| 187 | #define STATE_LITBEN 34 |
| 188 | #define STATE_MISC0 35 |
| 189 | #define STATE_MISC1 36 |
| 190 | #define STATE_InOCDMode 37 |
| 191 | #define STATE_INTENABLE 38 |
| 192 | #define STATE_DBREAKA0 39 |
| 193 | #define STATE_DBREAKC0 40 |
| 194 | #define STATE_DBREAKA1 41 |
| 195 | #define STATE_DBREAKC1 42 |
| 196 | #define STATE_IBREAKA0 43 |
| 197 | #define STATE_IBREAKA1 44 |
| 198 | #define STATE_IBREAKENABLE 45 |
| 199 | #define STATE_ICOUNTLEVEL 46 |
| 200 | #define STATE_DEBUGCAUSE 47 |
| 201 | #define STATE_DBNUM 48 |
| 202 | #define STATE_CCOMPARE0 49 |
| 203 | #define STATE_CCOMPARE1 50 |
| 204 | #define STATE_CCOMPARE2 51 |
| 205 | #define STATE_ASID3 52 |
| 206 | #define STATE_ASID2 53 |
| 207 | #define STATE_ASID1 54 |
| 208 | #define STATE_INSTPGSZID4 55 |
| 209 | #define STATE_DATAPGSZID4 56 |
| 210 | #define STATE_PTBASE 57 |
| 211 | |
| 212 | \f |
| 213 | /* Field definitions. */ |
| 214 | |
| 215 | static unsigned |
| 216 | Field_t_Slot_inst_get (const xtensa_insnbuf insn) |
| 217 | { |
| 218 | unsigned tie_t = 0; |
| 219 | tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); |
| 220 | return tie_t; |
| 221 | } |
| 222 | |
| 223 | static void |
| 224 | Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 225 | { |
| 226 | uint32 tie_t; |
| 227 | tie_t = (val << 28) >> 28; |
| 228 | insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); |
| 229 | } |
| 230 | |
| 231 | static unsigned |
| 232 | Field_s_Slot_inst_get (const xtensa_insnbuf insn) |
| 233 | { |
| 234 | unsigned tie_t = 0; |
| 235 | tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); |
| 236 | return tie_t; |
| 237 | } |
| 238 | |
| 239 | static void |
| 240 | Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 241 | { |
| 242 | uint32 tie_t; |
| 243 | tie_t = (val << 28) >> 28; |
| 244 | insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); |
| 245 | } |
| 246 | |
| 247 | static unsigned |
| 248 | Field_r_Slot_inst_get (const xtensa_insnbuf insn) |
| 249 | { |
| 250 | unsigned tie_t = 0; |
| 251 | tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); |
| 252 | return tie_t; |
| 253 | } |
| 254 | |
| 255 | static void |
| 256 | Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 257 | { |
| 258 | uint32 tie_t; |
| 259 | tie_t = (val << 28) >> 28; |
| 260 | insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); |
| 261 | } |
| 262 | |
| 263 | static unsigned |
| 264 | Field_op2_Slot_inst_get (const xtensa_insnbuf insn) |
| 265 | { |
| 266 | unsigned tie_t = 0; |
| 267 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); |
| 268 | return tie_t; |
| 269 | } |
| 270 | |
| 271 | static void |
| 272 | Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 273 | { |
| 274 | uint32 tie_t; |
| 275 | tie_t = (val << 28) >> 28; |
| 276 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); |
| 277 | } |
| 278 | |
| 279 | static unsigned |
| 280 | Field_op1_Slot_inst_get (const xtensa_insnbuf insn) |
| 281 | { |
| 282 | unsigned tie_t = 0; |
| 283 | tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); |
| 284 | return tie_t; |
| 285 | } |
| 286 | |
| 287 | static void |
| 288 | Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 289 | { |
| 290 | uint32 tie_t; |
| 291 | tie_t = (val << 28) >> 28; |
| 292 | insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); |
| 293 | } |
| 294 | |
| 295 | static unsigned |
| 296 | Field_op0_Slot_inst_get (const xtensa_insnbuf insn) |
| 297 | { |
| 298 | unsigned tie_t = 0; |
| 299 | tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); |
| 300 | return tie_t; |
| 301 | } |
| 302 | |
| 303 | static void |
| 304 | Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 305 | { |
| 306 | uint32 tie_t; |
| 307 | tie_t = (val << 28) >> 28; |
| 308 | insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); |
| 309 | } |
| 310 | |
| 311 | static unsigned |
| 312 | Field_n_Slot_inst_get (const xtensa_insnbuf insn) |
| 313 | { |
| 314 | unsigned tie_t = 0; |
| 315 | tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); |
| 316 | return tie_t; |
| 317 | } |
| 318 | |
| 319 | static void |
| 320 | Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 321 | { |
| 322 | uint32 tie_t; |
| 323 | tie_t = (val << 30) >> 30; |
| 324 | insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); |
| 325 | } |
| 326 | |
| 327 | static unsigned |
| 328 | Field_m_Slot_inst_get (const xtensa_insnbuf insn) |
| 329 | { |
| 330 | unsigned tie_t = 0; |
| 331 | tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); |
| 332 | return tie_t; |
| 333 | } |
| 334 | |
| 335 | static void |
| 336 | Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 337 | { |
| 338 | uint32 tie_t; |
| 339 | tie_t = (val << 30) >> 30; |
| 340 | insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); |
| 341 | } |
| 342 | |
| 343 | static unsigned |
| 344 | Field_sr_Slot_inst_get (const xtensa_insnbuf insn) |
| 345 | { |
| 346 | unsigned tie_t = 0; |
| 347 | tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); |
| 348 | tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); |
| 349 | return tie_t; |
| 350 | } |
| 351 | |
| 352 | static void |
| 353 | Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 354 | { |
| 355 | uint32 tie_t; |
| 356 | tie_t = (val << 28) >> 28; |
| 357 | insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); |
| 358 | tie_t = (val << 24) >> 28; |
| 359 | insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); |
| 360 | } |
| 361 | |
| 362 | static unsigned |
| 363 | Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) |
| 364 | { |
| 365 | unsigned tie_t = 0; |
| 366 | tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); |
| 367 | return tie_t; |
| 368 | } |
| 369 | |
| 370 | static void |
| 371 | Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 372 | { |
| 373 | uint32 tie_t; |
| 374 | tie_t = (val << 29) >> 29; |
| 375 | insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); |
| 376 | } |
| 377 | |
| 378 | static unsigned |
| 379 | Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) |
| 380 | { |
| 381 | unsigned tie_t = 0; |
| 382 | tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); |
| 383 | return tie_t; |
| 384 | } |
| 385 | |
| 386 | static void |
| 387 | Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) |
| 388 | { |
| 389 | uint32 tie_t; |
| 390 | tie_t = (val << 28) >> 28; |
| 391 | insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); |
| 392 | } |
| 393 | |
| 394 | static unsigned |
| 395 | Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) |
| 396 | { |
| 397 | unsigned tie_t = 0; |
| 398 | tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); |
| 399 | return tie_t; |
| 400 | } |
| 401 | |
| 402 | static void |
| 403 | Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) |
| 404 | { |
| 405 | uint32 tie_t; |
| 406 | tie_t = (val << 28) >> 28; |
| 407 | insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); |
| 408 | } |
| 409 | |
| 410 | static unsigned |
| 411 | Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) |
| 412 | { |
| 413 | unsigned tie_t = 0; |
| 414 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); |
| 415 | return tie_t; |
| 416 | } |
| 417 | |
| 418 | static void |
| 419 | Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) |
| 420 | { |
| 421 | uint32 tie_t; |
| 422 | tie_t = (val << 28) >> 28; |
| 423 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); |
| 424 | } |
| 425 | |
| 426 | static unsigned |
| 427 | Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) |
| 428 | { |
| 429 | unsigned tie_t = 0; |
| 430 | tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); |
| 431 | return tie_t; |
| 432 | } |
| 433 | |
| 434 | static void |
| 435 | Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) |
| 436 | { |
| 437 | uint32 tie_t; |
| 438 | tie_t = (val << 28) >> 28; |
| 439 | insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); |
| 440 | } |
| 441 | |
| 442 | static unsigned |
| 443 | Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) |
| 444 | { |
| 445 | unsigned tie_t = 0; |
| 446 | tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); |
| 447 | return tie_t; |
| 448 | } |
| 449 | |
| 450 | static void |
| 451 | Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) |
| 452 | { |
| 453 | uint32 tie_t; |
| 454 | tie_t = (val << 31) >> 31; |
| 455 | insn[0] = (insn[0] & ~0x400) | (tie_t << 10); |
| 456 | } |
| 457 | |
| 458 | static unsigned |
| 459 | Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) |
| 460 | { |
| 461 | unsigned tie_t = 0; |
| 462 | tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); |
| 463 | return tie_t; |
| 464 | } |
| 465 | |
| 466 | static void |
| 467 | Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) |
| 468 | { |
| 469 | uint32 tie_t; |
| 470 | tie_t = (val << 31) >> 31; |
| 471 | insn[0] = (insn[0] & ~0x800) | (tie_t << 11); |
| 472 | } |
| 473 | |
| 474 | static unsigned |
| 475 | Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) |
| 476 | { |
| 477 | unsigned tie_t = 0; |
| 478 | tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); |
| 479 | return tie_t; |
| 480 | } |
| 481 | |
| 482 | static void |
| 483 | Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) |
| 484 | { |
| 485 | uint32 tie_t; |
| 486 | tie_t = (val << 28) >> 28; |
| 487 | insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); |
| 488 | } |
| 489 | |
| 490 | static unsigned |
| 491 | Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) |
| 492 | { |
| 493 | unsigned tie_t = 0; |
| 494 | tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); |
| 495 | return tie_t; |
| 496 | } |
| 497 | |
| 498 | static void |
| 499 | Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) |
| 500 | { |
| 501 | uint32 tie_t; |
| 502 | tie_t = (val << 28) >> 28; |
| 503 | insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); |
| 504 | } |
| 505 | |
| 506 | static unsigned |
| 507 | Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) |
| 508 | { |
| 509 | unsigned tie_t = 0; |
| 510 | tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); |
| 511 | return tie_t; |
| 512 | } |
| 513 | |
| 514 | static void |
| 515 | Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 516 | { |
| 517 | uint32 tie_t; |
| 518 | tie_t = (val << 31) >> 31; |
| 519 | insn[0] = (insn[0] & ~0x100) | (tie_t << 8); |
| 520 | } |
| 521 | |
| 522 | static unsigned |
| 523 | Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) |
| 524 | { |
| 525 | unsigned tie_t = 0; |
| 526 | tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); |
| 527 | tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); |
| 528 | return tie_t; |
| 529 | } |
| 530 | |
| 531 | static void |
| 532 | Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 533 | { |
| 534 | uint32 tie_t; |
| 535 | tie_t = (val << 28) >> 28; |
| 536 | insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); |
| 537 | tie_t = (val << 27) >> 31; |
| 538 | insn[0] = (insn[0] & ~0x100) | (tie_t << 8); |
| 539 | } |
| 540 | |
| 541 | static unsigned |
| 542 | Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) |
| 543 | { |
| 544 | unsigned tie_t = 0; |
| 545 | tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20); |
| 546 | return tie_t; |
| 547 | } |
| 548 | |
| 549 | static void |
| 550 | Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 551 | { |
| 552 | uint32 tie_t; |
| 553 | tie_t = (val << 20) >> 20; |
| 554 | insn[0] = (insn[0] & ~0xfff) | (tie_t << 0); |
| 555 | } |
| 556 | |
| 557 | static unsigned |
| 558 | Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) |
| 559 | { |
| 560 | unsigned tie_t = 0; |
| 561 | tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); |
| 562 | return tie_t; |
| 563 | } |
| 564 | |
| 565 | static void |
| 566 | Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 567 | { |
| 568 | uint32 tie_t; |
| 569 | tie_t = (val << 24) >> 24; |
| 570 | insn[0] = (insn[0] & ~0xff) | (tie_t << 0); |
| 571 | } |
| 572 | |
| 573 | static unsigned |
| 574 | Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) |
| 575 | { |
| 576 | unsigned tie_t = 0; |
| 577 | tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); |
| 578 | return tie_t; |
| 579 | } |
| 580 | |
| 581 | static void |
| 582 | Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) |
| 583 | { |
| 584 | uint32 tie_t; |
| 585 | tie_t = (val << 28) >> 28; |
| 586 | insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); |
| 587 | } |
| 588 | |
| 589 | static unsigned |
| 590 | Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) |
| 591 | { |
| 592 | unsigned tie_t = 0; |
| 593 | tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); |
| 594 | tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); |
| 595 | return tie_t; |
| 596 | } |
| 597 | |
| 598 | static void |
| 599 | Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 600 | { |
| 601 | uint32 tie_t; |
| 602 | tie_t = (val << 24) >> 24; |
| 603 | insn[0] = (insn[0] & ~0xff) | (tie_t << 0); |
| 604 | tie_t = (val << 20) >> 28; |
| 605 | insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); |
| 606 | } |
| 607 | |
| 608 | static unsigned |
| 609 | Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) |
| 610 | { |
| 611 | unsigned tie_t = 0; |
| 612 | tie_t = (tie_t << 16) | ((insn[0] << 16) >> 16); |
| 613 | return tie_t; |
| 614 | } |
| 615 | |
| 616 | static void |
| 617 | Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 618 | { |
| 619 | uint32 tie_t; |
| 620 | tie_t = (val << 16) >> 16; |
| 621 | insn[0] = (insn[0] & ~0xffff) | (tie_t << 0); |
| 622 | } |
| 623 | |
| 624 | static unsigned |
| 625 | Field_offset_Slot_inst_get (const xtensa_insnbuf insn) |
| 626 | { |
| 627 | unsigned tie_t = 0; |
| 628 | tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); |
| 629 | return tie_t; |
| 630 | } |
| 631 | |
| 632 | static void |
| 633 | Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 634 | { |
| 635 | uint32 tie_t; |
| 636 | tie_t = (val << 14) >> 14; |
| 637 | insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); |
| 638 | } |
| 639 | |
| 640 | static unsigned |
| 641 | Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) |
| 642 | { |
| 643 | unsigned tie_t = 0; |
| 644 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); |
| 645 | return tie_t; |
| 646 | } |
| 647 | |
| 648 | static void |
| 649 | Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) |
| 650 | { |
| 651 | uint32 tie_t; |
| 652 | tie_t = (val << 28) >> 28; |
| 653 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); |
| 654 | } |
| 655 | |
| 656 | static unsigned |
| 657 | Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) |
| 658 | { |
| 659 | unsigned tie_t = 0; |
| 660 | tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); |
| 661 | return tie_t; |
| 662 | } |
| 663 | |
| 664 | static void |
| 665 | Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 666 | { |
| 667 | uint32 tie_t; |
| 668 | tie_t = (val << 31) >> 31; |
| 669 | insn[0] = (insn[0] & ~0x1) | (tie_t << 0); |
| 670 | } |
| 671 | |
| 672 | static unsigned |
| 673 | Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) |
| 674 | { |
| 675 | unsigned tie_t = 0; |
| 676 | tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); |
| 677 | return tie_t; |
| 678 | } |
| 679 | |
| 680 | static void |
| 681 | Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 682 | { |
| 683 | uint32 tie_t; |
| 684 | tie_t = (val << 31) >> 31; |
| 685 | insn[0] = (insn[0] & ~0x10) | (tie_t << 4); |
| 686 | } |
| 687 | |
| 688 | static unsigned |
| 689 | Field_sae_Slot_inst_get (const xtensa_insnbuf insn) |
| 690 | { |
| 691 | unsigned tie_t = 0; |
| 692 | tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); |
| 693 | tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); |
| 694 | return tie_t; |
| 695 | } |
| 696 | |
| 697 | static void |
| 698 | Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 699 | { |
| 700 | uint32 tie_t; |
| 701 | tie_t = (val << 28) >> 28; |
| 702 | insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); |
| 703 | tie_t = (val << 27) >> 31; |
| 704 | insn[0] = (insn[0] & ~0x10) | (tie_t << 4); |
| 705 | } |
| 706 | |
| 707 | static unsigned |
| 708 | Field_sal_Slot_inst_get (const xtensa_insnbuf insn) |
| 709 | { |
| 710 | unsigned tie_t = 0; |
| 711 | tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); |
| 712 | tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); |
| 713 | return tie_t; |
| 714 | } |
| 715 | |
| 716 | static void |
| 717 | Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 718 | { |
| 719 | uint32 tie_t; |
| 720 | tie_t = (val << 28) >> 28; |
| 721 | insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); |
| 722 | tie_t = (val << 27) >> 31; |
| 723 | insn[0] = (insn[0] & ~0x1) | (tie_t << 0); |
| 724 | } |
| 725 | |
| 726 | static unsigned |
| 727 | Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) |
| 728 | { |
| 729 | unsigned tie_t = 0; |
| 730 | tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); |
| 731 | tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); |
| 732 | return tie_t; |
| 733 | } |
| 734 | |
| 735 | static void |
| 736 | Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 737 | { |
| 738 | uint32 tie_t; |
| 739 | tie_t = (val << 28) >> 28; |
| 740 | insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); |
| 741 | tie_t = (val << 27) >> 31; |
| 742 | insn[0] = (insn[0] & ~0x1) | (tie_t << 0); |
| 743 | } |
| 744 | |
| 745 | static unsigned |
| 746 | Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) |
| 747 | { |
| 748 | unsigned tie_t = 0; |
| 749 | tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); |
| 750 | return tie_t; |
| 751 | } |
| 752 | |
| 753 | static void |
| 754 | Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 755 | { |
| 756 | uint32 tie_t; |
| 757 | tie_t = (val << 31) >> 31; |
| 758 | insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); |
| 759 | } |
| 760 | |
| 761 | static unsigned |
| 762 | Field_sas_Slot_inst_get (const xtensa_insnbuf insn) |
| 763 | { |
| 764 | unsigned tie_t = 0; |
| 765 | tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); |
| 766 | tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); |
| 767 | return tie_t; |
| 768 | } |
| 769 | |
| 770 | static void |
| 771 | Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 772 | { |
| 773 | uint32 tie_t; |
| 774 | tie_t = (val << 28) >> 28; |
| 775 | insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); |
| 776 | tie_t = (val << 27) >> 31; |
| 777 | insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); |
| 778 | } |
| 779 | |
| 780 | static unsigned |
| 781 | Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) |
| 782 | { |
| 783 | unsigned tie_t = 0; |
| 784 | tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); |
| 785 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); |
| 786 | return tie_t; |
| 787 | } |
| 788 | |
| 789 | static void |
| 790 | Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) |
| 791 | { |
| 792 | uint32 tie_t; |
| 793 | tie_t = (val << 28) >> 28; |
| 794 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); |
| 795 | tie_t = (val << 24) >> 28; |
| 796 | insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); |
| 797 | } |
| 798 | |
| 799 | static unsigned |
| 800 | Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) |
| 801 | { |
| 802 | unsigned tie_t = 0; |
| 803 | tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); |
| 804 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); |
| 805 | return tie_t; |
| 806 | } |
| 807 | |
| 808 | static void |
| 809 | Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) |
| 810 | { |
| 811 | uint32 tie_t; |
| 812 | tie_t = (val << 28) >> 28; |
| 813 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); |
| 814 | tie_t = (val << 24) >> 28; |
| 815 | insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); |
| 816 | } |
| 817 | |
| 818 | static unsigned |
| 819 | Field_st_Slot_inst_get (const xtensa_insnbuf insn) |
| 820 | { |
| 821 | unsigned tie_t = 0; |
| 822 | tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); |
| 823 | tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); |
| 824 | return tie_t; |
| 825 | } |
| 826 | |
| 827 | static void |
| 828 | Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 829 | { |
| 830 | uint32 tie_t; |
| 831 | tie_t = (val << 28) >> 28; |
| 832 | insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); |
| 833 | tie_t = (val << 24) >> 28; |
| 834 | insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); |
| 835 | } |
| 836 | |
| 837 | static unsigned |
| 838 | Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) |
| 839 | { |
| 840 | unsigned tie_t = 0; |
| 841 | tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); |
| 842 | tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); |
| 843 | return tie_t; |
| 844 | } |
| 845 | |
| 846 | static void |
| 847 | Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) |
| 848 | { |
| 849 | uint32 tie_t; |
| 850 | tie_t = (val << 28) >> 28; |
| 851 | insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); |
| 852 | tie_t = (val << 24) >> 28; |
| 853 | insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); |
| 854 | } |
| 855 | |
| 856 | static unsigned |
| 857 | Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) |
| 858 | { |
| 859 | unsigned tie_t = 0; |
| 860 | tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); |
| 861 | tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); |
| 862 | return tie_t; |
| 863 | } |
| 864 | |
| 865 | static void |
| 866 | Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) |
| 867 | { |
| 868 | uint32 tie_t; |
| 869 | tie_t = (val << 28) >> 28; |
| 870 | insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); |
| 871 | tie_t = (val << 24) >> 28; |
| 872 | insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); |
| 873 | } |
| 874 | |
| 875 | static unsigned |
| 876 | Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) |
| 877 | { |
| 878 | unsigned tie_t = 0; |
| 879 | tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); |
| 880 | return tie_t; |
| 881 | } |
| 882 | |
| 883 | static void |
| 884 | Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 885 | { |
| 886 | uint32 tie_t; |
| 887 | tie_t = (val << 28) >> 28; |
| 888 | insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); |
| 889 | } |
| 890 | |
| 891 | static unsigned |
| 892 | Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) |
| 893 | { |
| 894 | unsigned tie_t = 0; |
| 895 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); |
| 896 | return tie_t; |
| 897 | } |
| 898 | |
| 899 | static void |
| 900 | Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) |
| 901 | { |
| 902 | uint32 tie_t; |
| 903 | tie_t = (val << 28) >> 28; |
| 904 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); |
| 905 | } |
| 906 | |
| 907 | static unsigned |
| 908 | Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) |
| 909 | { |
| 910 | unsigned tie_t = 0; |
| 911 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); |
| 912 | return tie_t; |
| 913 | } |
| 914 | |
| 915 | static void |
| 916 | Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) |
| 917 | { |
| 918 | uint32 tie_t; |
| 919 | tie_t = (val << 28) >> 28; |
| 920 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); |
| 921 | } |
| 922 | |
| 923 | static unsigned |
| 924 | Field_mn_Slot_inst_get (const xtensa_insnbuf insn) |
| 925 | { |
| 926 | unsigned tie_t = 0; |
| 927 | tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); |
| 928 | tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); |
| 929 | return tie_t; |
| 930 | } |
| 931 | |
| 932 | static void |
| 933 | Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 934 | { |
| 935 | uint32 tie_t; |
| 936 | tie_t = (val << 30) >> 30; |
| 937 | insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); |
| 938 | tie_t = (val << 28) >> 30; |
| 939 | insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); |
| 940 | } |
| 941 | |
| 942 | static unsigned |
| 943 | Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) |
| 944 | { |
| 945 | unsigned tie_t = 0; |
| 946 | tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); |
| 947 | return tie_t; |
| 948 | } |
| 949 | |
| 950 | static void |
| 951 | Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) |
| 952 | { |
| 953 | uint32 tie_t; |
| 954 | tie_t = (val << 31) >> 31; |
| 955 | insn[0] = (insn[0] & ~0x800) | (tie_t << 11); |
| 956 | } |
| 957 | |
| 958 | static unsigned |
| 959 | Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) |
| 960 | { |
| 961 | unsigned tie_t = 0; |
| 962 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); |
| 963 | return tie_t; |
| 964 | } |
| 965 | |
| 966 | static void |
| 967 | Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) |
| 968 | { |
| 969 | uint32 tie_t; |
| 970 | tie_t = (val << 28) >> 28; |
| 971 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); |
| 972 | } |
| 973 | |
| 974 | static unsigned |
| 975 | Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) |
| 976 | { |
| 977 | unsigned tie_t = 0; |
| 978 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); |
| 979 | return tie_t; |
| 980 | } |
| 981 | |
| 982 | static void |
| 983 | Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) |
| 984 | { |
| 985 | uint32 tie_t; |
| 986 | tie_t = (val << 28) >> 28; |
| 987 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); |
| 988 | } |
| 989 | |
| 990 | static unsigned |
| 991 | Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) |
| 992 | { |
| 993 | unsigned tie_t = 0; |
| 994 | tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); |
| 995 | return tie_t; |
| 996 | } |
| 997 | |
| 998 | static void |
| 999 | Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) |
| 1000 | { |
| 1001 | uint32 tie_t; |
| 1002 | tie_t = (val << 30) >> 30; |
| 1003 | insn[0] = (insn[0] & ~0x300) | (tie_t << 8); |
| 1004 | } |
| 1005 | |
| 1006 | static unsigned |
| 1007 | Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) |
| 1008 | { |
| 1009 | unsigned tie_t = 0; |
| 1010 | tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); |
| 1011 | return tie_t; |
| 1012 | } |
| 1013 | |
| 1014 | static void |
| 1015 | Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) |
| 1016 | { |
| 1017 | uint32 tie_t; |
| 1018 | tie_t = (val << 30) >> 30; |
| 1019 | insn[0] = (insn[0] & ~0x300) | (tie_t << 8); |
| 1020 | } |
| 1021 | |
| 1022 | static unsigned |
| 1023 | Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) |
| 1024 | { |
| 1025 | unsigned tie_t = 0; |
| 1026 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); |
| 1027 | return tie_t; |
| 1028 | } |
| 1029 | |
| 1030 | static void |
| 1031 | Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) |
| 1032 | { |
| 1033 | uint32 tie_t; |
| 1034 | tie_t = (val << 28) >> 28; |
| 1035 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); |
| 1036 | } |
| 1037 | |
| 1038 | static unsigned |
| 1039 | Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) |
| 1040 | { |
| 1041 | unsigned tie_t = 0; |
| 1042 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); |
| 1043 | return tie_t; |
| 1044 | } |
| 1045 | |
| 1046 | static void |
| 1047 | Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) |
| 1048 | { |
| 1049 | uint32 tie_t; |
| 1050 | tie_t = (val << 28) >> 28; |
| 1051 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); |
| 1052 | } |
| 1053 | |
| 1054 | static unsigned |
| 1055 | Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) |
| 1056 | { |
| 1057 | unsigned tie_t = 0; |
| 1058 | tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); |
| 1059 | return tie_t; |
| 1060 | } |
| 1061 | |
| 1062 | static void |
| 1063 | Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) |
| 1064 | { |
| 1065 | uint32 tie_t; |
| 1066 | tie_t = (val << 29) >> 29; |
| 1067 | insn[0] = (insn[0] & ~0x700) | (tie_t << 8); |
| 1068 | } |
| 1069 | |
| 1070 | static unsigned |
| 1071 | Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) |
| 1072 | { |
| 1073 | unsigned tie_t = 0; |
| 1074 | tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); |
| 1075 | return tie_t; |
| 1076 | } |
| 1077 | |
| 1078 | static void |
| 1079 | Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) |
| 1080 | { |
| 1081 | uint32 tie_t; |
| 1082 | tie_t = (val << 29) >> 29; |
| 1083 | insn[0] = (insn[0] & ~0x700) | (tie_t << 8); |
| 1084 | } |
| 1085 | |
| 1086 | static unsigned |
| 1087 | Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) |
| 1088 | { |
| 1089 | unsigned tie_t = 0; |
| 1090 | tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); |
| 1091 | return tie_t; |
| 1092 | } |
| 1093 | |
| 1094 | static void |
| 1095 | Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) |
| 1096 | { |
| 1097 | uint32 tie_t; |
| 1098 | tie_t = (val << 31) >> 31; |
| 1099 | insn[0] = (insn[0] & ~0x400) | (tie_t << 10); |
| 1100 | } |
| 1101 | |
| 1102 | static unsigned |
| 1103 | Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) |
| 1104 | { |
| 1105 | unsigned tie_t = 0; |
| 1106 | tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); |
| 1107 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); |
| 1108 | return tie_t; |
| 1109 | } |
| 1110 | |
| 1111 | static void |
| 1112 | Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) |
| 1113 | { |
| 1114 | uint32 tie_t; |
| 1115 | tie_t = (val << 28) >> 28; |
| 1116 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); |
| 1117 | tie_t = (val << 26) >> 30; |
| 1118 | insn[0] = (insn[0] & ~0x300) | (tie_t << 8); |
| 1119 | } |
| 1120 | |
| 1121 | static unsigned |
| 1122 | Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) |
| 1123 | { |
| 1124 | unsigned tie_t = 0; |
| 1125 | tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); |
| 1126 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); |
| 1127 | return tie_t; |
| 1128 | } |
| 1129 | |
| 1130 | static void |
| 1131 | Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) |
| 1132 | { |
| 1133 | uint32 tie_t; |
| 1134 | tie_t = (val << 28) >> 28; |
| 1135 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); |
| 1136 | tie_t = (val << 26) >> 30; |
| 1137 | insn[0] = (insn[0] & ~0x300) | (tie_t << 8); |
| 1138 | } |
| 1139 | |
| 1140 | static unsigned |
| 1141 | Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) |
| 1142 | { |
| 1143 | unsigned tie_t = 0; |
| 1144 | tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); |
| 1145 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); |
| 1146 | return tie_t; |
| 1147 | } |
| 1148 | |
| 1149 | static void |
| 1150 | Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) |
| 1151 | { |
| 1152 | uint32 tie_t; |
| 1153 | tie_t = (val << 28) >> 28; |
| 1154 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); |
| 1155 | tie_t = (val << 25) >> 29; |
| 1156 | insn[0] = (insn[0] & ~0x700) | (tie_t << 8); |
| 1157 | } |
| 1158 | |
| 1159 | static unsigned |
| 1160 | Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) |
| 1161 | { |
| 1162 | unsigned tie_t = 0; |
| 1163 | tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); |
| 1164 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); |
| 1165 | return tie_t; |
| 1166 | } |
| 1167 | |
| 1168 | static void |
| 1169 | Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) |
| 1170 | { |
| 1171 | uint32 tie_t; |
| 1172 | tie_t = (val << 28) >> 28; |
| 1173 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); |
| 1174 | tie_t = (val << 25) >> 29; |
| 1175 | insn[0] = (insn[0] & ~0x700) | (tie_t << 8); |
| 1176 | } |
| 1177 | |
| 1178 | static void |
| 1179 | Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, |
| 1180 | uint32 val ATTRIBUTE_UNUSED) |
| 1181 | { |
| 1182 | /* Do nothing. */ |
| 1183 | } |
| 1184 | |
| 1185 | static unsigned |
| 1186 | Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) |
| 1187 | { |
| 1188 | return 0; |
| 1189 | } |
| 1190 | |
| 1191 | static unsigned |
| 1192 | Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) |
| 1193 | { |
| 1194 | return 4; |
| 1195 | } |
| 1196 | |
| 1197 | static unsigned |
| 1198 | Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) |
| 1199 | { |
| 1200 | return 8; |
| 1201 | } |
| 1202 | |
| 1203 | static unsigned |
| 1204 | Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) |
| 1205 | { |
| 1206 | return 12; |
| 1207 | } |
| 1208 | |
| 1209 | \f |
| 1210 | /* Functional units. */ |
| 1211 | |
| 1212 | static xtensa_funcUnit_internal funcUnits[] = { |
| 1213 | |
| 1214 | }; |
| 1215 | |
| 1216 | \f |
| 1217 | /* Register files. */ |
| 1218 | |
| 1219 | static xtensa_regfile_internal regfiles[] = { |
| 1220 | { "AR", "a", 0, 32, 64 } |
| 1221 | }; |
| 1222 | |
| 1223 | \f |
| 1224 | /* Interfaces. */ |
| 1225 | |
| 1226 | static xtensa_interface_internal interfaces[] = { |
| 1227 | |
| 1228 | }; |
| 1229 | |
| 1230 | \f |
| 1231 | /* Constant tables. */ |
| 1232 | |
| 1233 | /* constant table ai4c */ |
| 1234 | static const unsigned CONST_TBL_ai4c_0[] = { |
| 1235 | 0xffffffff, |
| 1236 | 0x1, |
| 1237 | 0x2, |
| 1238 | 0x3, |
| 1239 | 0x4, |
| 1240 | 0x5, |
| 1241 | 0x6, |
| 1242 | 0x7, |
| 1243 | 0x8, |
| 1244 | 0x9, |
| 1245 | 0xa, |
| 1246 | 0xb, |
| 1247 | 0xc, |
| 1248 | 0xd, |
| 1249 | 0xe, |
| 1250 | 0xf, |
| 1251 | 0 |
| 1252 | }; |
| 1253 | |
| 1254 | /* constant table b4c */ |
| 1255 | static const unsigned CONST_TBL_b4c_0[] = { |
| 1256 | 0xffffffff, |
| 1257 | 0x1, |
| 1258 | 0x2, |
| 1259 | 0x3, |
| 1260 | 0x4, |
| 1261 | 0x5, |
| 1262 | 0x6, |
| 1263 | 0x7, |
| 1264 | 0x8, |
| 1265 | 0xa, |
| 1266 | 0xc, |
| 1267 | 0x10, |
| 1268 | 0x20, |
| 1269 | 0x40, |
| 1270 | 0x80, |
| 1271 | 0x100, |
| 1272 | 0 |
| 1273 | }; |
| 1274 | |
| 1275 | /* constant table b4cu */ |
| 1276 | static const unsigned CONST_TBL_b4cu_0[] = { |
| 1277 | 0x8000, |
| 1278 | 0x10000, |
| 1279 | 0x2, |
| 1280 | 0x3, |
| 1281 | 0x4, |
| 1282 | 0x5, |
| 1283 | 0x6, |
| 1284 | 0x7, |
| 1285 | 0x8, |
| 1286 | 0xa, |
| 1287 | 0xc, |
| 1288 | 0x10, |
| 1289 | 0x20, |
| 1290 | 0x40, |
| 1291 | 0x80, |
| 1292 | 0x100, |
| 1293 | 0 |
| 1294 | }; |
| 1295 | |
| 1296 | \f |
| 1297 | /* Instruction operands. */ |
| 1298 | |
| 1299 | static int |
| 1300 | Operand_soffsetx4_decode (uint32 *valp) |
| 1301 | { |
| 1302 | unsigned soffsetx4_0, offset_0; |
| 1303 | offset_0 = *valp & 0x3ffff; |
| 1304 | soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2); |
| 1305 | *valp = soffsetx4_0; |
| 1306 | return 0; |
| 1307 | } |
| 1308 | |
| 1309 | static int |
| 1310 | Operand_soffsetx4_encode (uint32 *valp) |
| 1311 | { |
| 1312 | unsigned offset_0, soffsetx4_0; |
| 1313 | soffsetx4_0 = *valp; |
| 1314 | offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff; |
| 1315 | *valp = offset_0; |
| 1316 | return 0; |
| 1317 | } |
| 1318 | |
| 1319 | static int |
| 1320 | Operand_soffsetx4_ator (uint32 *valp, uint32 pc) |
| 1321 | { |
| 1322 | *valp -= (pc & ~0x3); |
| 1323 | return 0; |
| 1324 | } |
| 1325 | |
| 1326 | static int |
| 1327 | Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) |
| 1328 | { |
| 1329 | *valp += (pc & ~0x3); |
| 1330 | return 0; |
| 1331 | } |
| 1332 | |
| 1333 | static int |
| 1334 | Operand_uimm12x8_decode (uint32 *valp) |
| 1335 | { |
| 1336 | unsigned uimm12x8_0, imm12_0; |
| 1337 | imm12_0 = *valp & 0xfff; |
| 1338 | uimm12x8_0 = imm12_0 << 3; |
| 1339 | *valp = uimm12x8_0; |
| 1340 | return 0; |
| 1341 | } |
| 1342 | |
| 1343 | static int |
| 1344 | Operand_uimm12x8_encode (uint32 *valp) |
| 1345 | { |
| 1346 | unsigned imm12_0, uimm12x8_0; |
| 1347 | uimm12x8_0 = *valp; |
| 1348 | imm12_0 = ((uimm12x8_0 >> 3) & 0xfff); |
| 1349 | *valp = imm12_0; |
| 1350 | return 0; |
| 1351 | } |
| 1352 | |
| 1353 | static int |
| 1354 | Operand_simm4_decode (uint32 *valp) |
| 1355 | { |
| 1356 | unsigned simm4_0, mn_0; |
| 1357 | mn_0 = *valp & 0xf; |
| 1358 | simm4_0 = ((int) mn_0 << 28) >> 28; |
| 1359 | *valp = simm4_0; |
| 1360 | return 0; |
| 1361 | } |
| 1362 | |
| 1363 | static int |
| 1364 | Operand_simm4_encode (uint32 *valp) |
| 1365 | { |
| 1366 | unsigned mn_0, simm4_0; |
| 1367 | simm4_0 = *valp; |
| 1368 | mn_0 = (simm4_0 & 0xf); |
| 1369 | *valp = mn_0; |
| 1370 | return 0; |
| 1371 | } |
| 1372 | |
| 1373 | static int |
| 1374 | Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED) |
| 1375 | { |
| 1376 | return 0; |
| 1377 | } |
| 1378 | |
| 1379 | static int |
| 1380 | Operand_arr_encode (uint32 *valp) |
| 1381 | { |
| 1382 | int error; |
| 1383 | error = (*valp & ~0xf) != 0; |
| 1384 | return error; |
| 1385 | } |
| 1386 | |
| 1387 | static int |
| 1388 | Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED) |
| 1389 | { |
| 1390 | return 0; |
| 1391 | } |
| 1392 | |
| 1393 | static int |
| 1394 | Operand_ars_encode (uint32 *valp) |
| 1395 | { |
| 1396 | int error; |
| 1397 | error = (*valp & ~0xf) != 0; |
| 1398 | return error; |
| 1399 | } |
| 1400 | |
| 1401 | static int |
| 1402 | Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED) |
| 1403 | { |
| 1404 | return 0; |
| 1405 | } |
| 1406 | |
| 1407 | static int |
| 1408 | Operand_art_encode (uint32 *valp) |
| 1409 | { |
| 1410 | int error; |
| 1411 | error = (*valp & ~0xf) != 0; |
| 1412 | return error; |
| 1413 | } |
| 1414 | |
| 1415 | static int |
| 1416 | Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED) |
| 1417 | { |
| 1418 | return 0; |
| 1419 | } |
| 1420 | |
| 1421 | static int |
| 1422 | Operand_ar0_encode (uint32 *valp) |
| 1423 | { |
| 1424 | int error; |
| 1425 | error = (*valp & ~0x3f) != 0; |
| 1426 | return error; |
| 1427 | } |
| 1428 | |
| 1429 | static int |
| 1430 | Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED) |
| 1431 | { |
| 1432 | return 0; |
| 1433 | } |
| 1434 | |
| 1435 | static int |
| 1436 | Operand_ar4_encode (uint32 *valp) |
| 1437 | { |
| 1438 | int error; |
| 1439 | error = (*valp & ~0x3f) != 0; |
| 1440 | return error; |
| 1441 | } |
| 1442 | |
| 1443 | static int |
| 1444 | Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED) |
| 1445 | { |
| 1446 | return 0; |
| 1447 | } |
| 1448 | |
| 1449 | static int |
| 1450 | Operand_ar8_encode (uint32 *valp) |
| 1451 | { |
| 1452 | int error; |
| 1453 | error = (*valp & ~0x3f) != 0; |
| 1454 | return error; |
| 1455 | } |
| 1456 | |
| 1457 | static int |
| 1458 | Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED) |
| 1459 | { |
| 1460 | return 0; |
| 1461 | } |
| 1462 | |
| 1463 | static int |
| 1464 | Operand_ar12_encode (uint32 *valp) |
| 1465 | { |
| 1466 | int error; |
| 1467 | error = (*valp & ~0x3f) != 0; |
| 1468 | return error; |
| 1469 | } |
| 1470 | |
| 1471 | static int |
| 1472 | Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED) |
| 1473 | { |
| 1474 | return 0; |
| 1475 | } |
| 1476 | |
| 1477 | static int |
| 1478 | Operand_ars_entry_encode (uint32 *valp) |
| 1479 | { |
| 1480 | int error; |
| 1481 | error = (*valp & ~0x3f) != 0; |
| 1482 | return error; |
| 1483 | } |
| 1484 | |
| 1485 | static int |
| 1486 | Operand_immrx4_decode (uint32 *valp) |
| 1487 | { |
| 1488 | unsigned immrx4_0, r_0; |
| 1489 | r_0 = *valp & 0xf; |
| 1490 | immrx4_0 = ((((0xfffffff)) << 4) | r_0) << 2; |
| 1491 | *valp = immrx4_0; |
| 1492 | return 0; |
| 1493 | } |
| 1494 | |
| 1495 | static int |
| 1496 | Operand_immrx4_encode (uint32 *valp) |
| 1497 | { |
| 1498 | unsigned r_0, immrx4_0; |
| 1499 | immrx4_0 = *valp; |
| 1500 | r_0 = ((immrx4_0 >> 2) & 0xf); |
| 1501 | *valp = r_0; |
| 1502 | return 0; |
| 1503 | } |
| 1504 | |
| 1505 | static int |
| 1506 | Operand_lsi4x4_decode (uint32 *valp) |
| 1507 | { |
| 1508 | unsigned lsi4x4_0, r_0; |
| 1509 | r_0 = *valp & 0xf; |
| 1510 | lsi4x4_0 = r_0 << 2; |
| 1511 | *valp = lsi4x4_0; |
| 1512 | return 0; |
| 1513 | } |
| 1514 | |
| 1515 | static int |
| 1516 | Operand_lsi4x4_encode (uint32 *valp) |
| 1517 | { |
| 1518 | unsigned r_0, lsi4x4_0; |
| 1519 | lsi4x4_0 = *valp; |
| 1520 | r_0 = ((lsi4x4_0 >> 2) & 0xf); |
| 1521 | *valp = r_0; |
| 1522 | return 0; |
| 1523 | } |
| 1524 | |
| 1525 | static int |
| 1526 | Operand_simm7_decode (uint32 *valp) |
| 1527 | { |
| 1528 | unsigned simm7_0, imm7_0; |
| 1529 | imm7_0 = *valp & 0x7f; |
| 1530 | simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0; |
| 1531 | *valp = simm7_0; |
| 1532 | return 0; |
| 1533 | } |
| 1534 | |
| 1535 | static int |
| 1536 | Operand_simm7_encode (uint32 *valp) |
| 1537 | { |
| 1538 | unsigned imm7_0, simm7_0; |
| 1539 | simm7_0 = *valp; |
| 1540 | imm7_0 = (simm7_0 & 0x7f); |
| 1541 | *valp = imm7_0; |
| 1542 | return 0; |
| 1543 | } |
| 1544 | |
| 1545 | static int |
| 1546 | Operand_uimm6_decode (uint32 *valp) |
| 1547 | { |
| 1548 | unsigned uimm6_0, imm6_0; |
| 1549 | imm6_0 = *valp & 0x3f; |
| 1550 | uimm6_0 = 0x4 + ((((0)) << 6) | imm6_0); |
| 1551 | *valp = uimm6_0; |
| 1552 | return 0; |
| 1553 | } |
| 1554 | |
| 1555 | static int |
| 1556 | Operand_uimm6_encode (uint32 *valp) |
| 1557 | { |
| 1558 | unsigned imm6_0, uimm6_0; |
| 1559 | uimm6_0 = *valp; |
| 1560 | imm6_0 = (uimm6_0 - 0x4) & 0x3f; |
| 1561 | *valp = imm6_0; |
| 1562 | return 0; |
| 1563 | } |
| 1564 | |
| 1565 | static int |
| 1566 | Operand_uimm6_ator (uint32 *valp, uint32 pc) |
| 1567 | { |
| 1568 | *valp -= pc; |
| 1569 | return 0; |
| 1570 | } |
| 1571 | |
| 1572 | static int |
| 1573 | Operand_uimm6_rtoa (uint32 *valp, uint32 pc) |
| 1574 | { |
| 1575 | *valp += pc; |
| 1576 | return 0; |
| 1577 | } |
| 1578 | |
| 1579 | static int |
| 1580 | Operand_ai4const_decode (uint32 *valp) |
| 1581 | { |
| 1582 | unsigned ai4const_0, t_0; |
| 1583 | t_0 = *valp & 0xf; |
| 1584 | ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf]; |
| 1585 | *valp = ai4const_0; |
| 1586 | return 0; |
| 1587 | } |
| 1588 | |
| 1589 | static int |
| 1590 | Operand_ai4const_encode (uint32 *valp) |
| 1591 | { |
| 1592 | unsigned t_0, ai4const_0; |
| 1593 | ai4const_0 = *valp; |
| 1594 | switch (ai4const_0) |
| 1595 | { |
| 1596 | case 0xffffffff: t_0 = 0; break; |
| 1597 | case 0x1: t_0 = 0x1; break; |
| 1598 | case 0x2: t_0 = 0x2; break; |
| 1599 | case 0x3: t_0 = 0x3; break; |
| 1600 | case 0x4: t_0 = 0x4; break; |
| 1601 | case 0x5: t_0 = 0x5; break; |
| 1602 | case 0x6: t_0 = 0x6; break; |
| 1603 | case 0x7: t_0 = 0x7; break; |
| 1604 | case 0x8: t_0 = 0x8; break; |
| 1605 | case 0x9: t_0 = 0x9; break; |
| 1606 | case 0xa: t_0 = 0xa; break; |
| 1607 | case 0xb: t_0 = 0xb; break; |
| 1608 | case 0xc: t_0 = 0xc; break; |
| 1609 | case 0xd: t_0 = 0xd; break; |
| 1610 | case 0xe: t_0 = 0xe; break; |
| 1611 | default: t_0 = 0xf; break; |
| 1612 | } |
| 1613 | *valp = t_0; |
| 1614 | return 0; |
| 1615 | } |
| 1616 | |
| 1617 | static int |
| 1618 | Operand_b4const_decode (uint32 *valp) |
| 1619 | { |
| 1620 | unsigned b4const_0, r_0; |
| 1621 | r_0 = *valp & 0xf; |
| 1622 | b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf]; |
| 1623 | *valp = b4const_0; |
| 1624 | return 0; |
| 1625 | } |
| 1626 | |
| 1627 | static int |
| 1628 | Operand_b4const_encode (uint32 *valp) |
| 1629 | { |
| 1630 | unsigned r_0, b4const_0; |
| 1631 | b4const_0 = *valp; |
| 1632 | switch (b4const_0) |
| 1633 | { |
| 1634 | case 0xffffffff: r_0 = 0; break; |
| 1635 | case 0x1: r_0 = 0x1; break; |
| 1636 | case 0x2: r_0 = 0x2; break; |
| 1637 | case 0x3: r_0 = 0x3; break; |
| 1638 | case 0x4: r_0 = 0x4; break; |
| 1639 | case 0x5: r_0 = 0x5; break; |
| 1640 | case 0x6: r_0 = 0x6; break; |
| 1641 | case 0x7: r_0 = 0x7; break; |
| 1642 | case 0x8: r_0 = 0x8; break; |
| 1643 | case 0xa: r_0 = 0x9; break; |
| 1644 | case 0xc: r_0 = 0xa; break; |
| 1645 | case 0x10: r_0 = 0xb; break; |
| 1646 | case 0x20: r_0 = 0xc; break; |
| 1647 | case 0x40: r_0 = 0xd; break; |
| 1648 | case 0x80: r_0 = 0xe; break; |
| 1649 | default: r_0 = 0xf; break; |
| 1650 | } |
| 1651 | *valp = r_0; |
| 1652 | return 0; |
| 1653 | } |
| 1654 | |
| 1655 | static int |
| 1656 | Operand_b4constu_decode (uint32 *valp) |
| 1657 | { |
| 1658 | unsigned b4constu_0, r_0; |
| 1659 | r_0 = *valp & 0xf; |
| 1660 | b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf]; |
| 1661 | *valp = b4constu_0; |
| 1662 | return 0; |
| 1663 | } |
| 1664 | |
| 1665 | static int |
| 1666 | Operand_b4constu_encode (uint32 *valp) |
| 1667 | { |
| 1668 | unsigned r_0, b4constu_0; |
| 1669 | b4constu_0 = *valp; |
| 1670 | switch (b4constu_0) |
| 1671 | { |
| 1672 | case 0x8000: r_0 = 0; break; |
| 1673 | case 0x10000: r_0 = 0x1; break; |
| 1674 | case 0x2: r_0 = 0x2; break; |
| 1675 | case 0x3: r_0 = 0x3; break; |
| 1676 | case 0x4: r_0 = 0x4; break; |
| 1677 | case 0x5: r_0 = 0x5; break; |
| 1678 | case 0x6: r_0 = 0x6; break; |
| 1679 | case 0x7: r_0 = 0x7; break; |
| 1680 | case 0x8: r_0 = 0x8; break; |
| 1681 | case 0xa: r_0 = 0x9; break; |
| 1682 | case 0xc: r_0 = 0xa; break; |
| 1683 | case 0x10: r_0 = 0xb; break; |
| 1684 | case 0x20: r_0 = 0xc; break; |
| 1685 | case 0x40: r_0 = 0xd; break; |
| 1686 | case 0x80: r_0 = 0xe; break; |
| 1687 | default: r_0 = 0xf; break; |
| 1688 | } |
| 1689 | *valp = r_0; |
| 1690 | return 0; |
| 1691 | } |
| 1692 | |
| 1693 | static int |
| 1694 | Operand_uimm8_decode (uint32 *valp) |
| 1695 | { |
| 1696 | unsigned uimm8_0, imm8_0; |
| 1697 | imm8_0 = *valp & 0xff; |
| 1698 | uimm8_0 = imm8_0; |
| 1699 | *valp = uimm8_0; |
| 1700 | return 0; |
| 1701 | } |
| 1702 | |
| 1703 | static int |
| 1704 | Operand_uimm8_encode (uint32 *valp) |
| 1705 | { |
| 1706 | unsigned imm8_0, uimm8_0; |
| 1707 | uimm8_0 = *valp; |
| 1708 | imm8_0 = (uimm8_0 & 0xff); |
| 1709 | *valp = imm8_0; |
| 1710 | return 0; |
| 1711 | } |
| 1712 | |
| 1713 | static int |
| 1714 | Operand_uimm8x2_decode (uint32 *valp) |
| 1715 | { |
| 1716 | unsigned uimm8x2_0, imm8_0; |
| 1717 | imm8_0 = *valp & 0xff; |
| 1718 | uimm8x2_0 = imm8_0 << 1; |
| 1719 | *valp = uimm8x2_0; |
| 1720 | return 0; |
| 1721 | } |
| 1722 | |
| 1723 | static int |
| 1724 | Operand_uimm8x2_encode (uint32 *valp) |
| 1725 | { |
| 1726 | unsigned imm8_0, uimm8x2_0; |
| 1727 | uimm8x2_0 = *valp; |
| 1728 | imm8_0 = ((uimm8x2_0 >> 1) & 0xff); |
| 1729 | *valp = imm8_0; |
| 1730 | return 0; |
| 1731 | } |
| 1732 | |
| 1733 | static int |
| 1734 | Operand_uimm8x4_decode (uint32 *valp) |
| 1735 | { |
| 1736 | unsigned uimm8x4_0, imm8_0; |
| 1737 | imm8_0 = *valp & 0xff; |
| 1738 | uimm8x4_0 = imm8_0 << 2; |
| 1739 | *valp = uimm8x4_0; |
| 1740 | return 0; |
| 1741 | } |
| 1742 | |
| 1743 | static int |
| 1744 | Operand_uimm8x4_encode (uint32 *valp) |
| 1745 | { |
| 1746 | unsigned imm8_0, uimm8x4_0; |
| 1747 | uimm8x4_0 = *valp; |
| 1748 | imm8_0 = ((uimm8x4_0 >> 2) & 0xff); |
| 1749 | *valp = imm8_0; |
| 1750 | return 0; |
| 1751 | } |
| 1752 | |
| 1753 | static int |
| 1754 | Operand_uimm4x16_decode (uint32 *valp) |
| 1755 | { |
| 1756 | unsigned uimm4x16_0, op2_0; |
| 1757 | op2_0 = *valp & 0xf; |
| 1758 | uimm4x16_0 = op2_0 << 4; |
| 1759 | *valp = uimm4x16_0; |
| 1760 | return 0; |
| 1761 | } |
| 1762 | |
| 1763 | static int |
| 1764 | Operand_uimm4x16_encode (uint32 *valp) |
| 1765 | { |
| 1766 | unsigned op2_0, uimm4x16_0; |
| 1767 | uimm4x16_0 = *valp; |
| 1768 | op2_0 = ((uimm4x16_0 >> 4) & 0xf); |
| 1769 | *valp = op2_0; |
| 1770 | return 0; |
| 1771 | } |
| 1772 | |
| 1773 | static int |
| 1774 | Operand_simm8_decode (uint32 *valp) |
| 1775 | { |
| 1776 | unsigned simm8_0, imm8_0; |
| 1777 | imm8_0 = *valp & 0xff; |
| 1778 | simm8_0 = ((int) imm8_0 << 24) >> 24; |
| 1779 | *valp = simm8_0; |
| 1780 | return 0; |
| 1781 | } |
| 1782 | |
| 1783 | static int |
| 1784 | Operand_simm8_encode (uint32 *valp) |
| 1785 | { |
| 1786 | unsigned imm8_0, simm8_0; |
| 1787 | simm8_0 = *valp; |
| 1788 | imm8_0 = (simm8_0 & 0xff); |
| 1789 | *valp = imm8_0; |
| 1790 | return 0; |
| 1791 | } |
| 1792 | |
| 1793 | static int |
| 1794 | Operand_simm8x256_decode (uint32 *valp) |
| 1795 | { |
| 1796 | unsigned simm8x256_0, imm8_0; |
| 1797 | imm8_0 = *valp & 0xff; |
| 1798 | simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8; |
| 1799 | *valp = simm8x256_0; |
| 1800 | return 0; |
| 1801 | } |
| 1802 | |
| 1803 | static int |
| 1804 | Operand_simm8x256_encode (uint32 *valp) |
| 1805 | { |
| 1806 | unsigned imm8_0, simm8x256_0; |
| 1807 | simm8x256_0 = *valp; |
| 1808 | imm8_0 = ((simm8x256_0 >> 8) & 0xff); |
| 1809 | *valp = imm8_0; |
| 1810 | return 0; |
| 1811 | } |
| 1812 | |
| 1813 | static int |
| 1814 | Operand_simm12b_decode (uint32 *valp) |
| 1815 | { |
| 1816 | unsigned simm12b_0, imm12b_0; |
| 1817 | imm12b_0 = *valp & 0xfff; |
| 1818 | simm12b_0 = ((int) imm12b_0 << 20) >> 20; |
| 1819 | *valp = simm12b_0; |
| 1820 | return 0; |
| 1821 | } |
| 1822 | |
| 1823 | static int |
| 1824 | Operand_simm12b_encode (uint32 *valp) |
| 1825 | { |
| 1826 | unsigned imm12b_0, simm12b_0; |
| 1827 | simm12b_0 = *valp; |
| 1828 | imm12b_0 = (simm12b_0 & 0xfff); |
| 1829 | *valp = imm12b_0; |
| 1830 | return 0; |
| 1831 | } |
| 1832 | |
| 1833 | static int |
| 1834 | Operand_msalp32_decode (uint32 *valp) |
| 1835 | { |
| 1836 | unsigned msalp32_0, sal_0; |
| 1837 | sal_0 = *valp & 0x1f; |
| 1838 | msalp32_0 = 0x20 - sal_0; |
| 1839 | *valp = msalp32_0; |
| 1840 | return 0; |
| 1841 | } |
| 1842 | |
| 1843 | static int |
| 1844 | Operand_msalp32_encode (uint32 *valp) |
| 1845 | { |
| 1846 | unsigned sal_0, msalp32_0; |
| 1847 | msalp32_0 = *valp; |
| 1848 | sal_0 = (0x20 - msalp32_0) & 0x1f; |
| 1849 | *valp = sal_0; |
| 1850 | return 0; |
| 1851 | } |
| 1852 | |
| 1853 | static int |
| 1854 | Operand_op2p1_decode (uint32 *valp) |
| 1855 | { |
| 1856 | unsigned op2p1_0, op2_0; |
| 1857 | op2_0 = *valp & 0xf; |
| 1858 | op2p1_0 = op2_0 + 0x1; |
| 1859 | *valp = op2p1_0; |
| 1860 | return 0; |
| 1861 | } |
| 1862 | |
| 1863 | static int |
| 1864 | Operand_op2p1_encode (uint32 *valp) |
| 1865 | { |
| 1866 | unsigned op2_0, op2p1_0; |
| 1867 | op2p1_0 = *valp; |
| 1868 | op2_0 = (op2p1_0 - 0x1) & 0xf; |
| 1869 | *valp = op2_0; |
| 1870 | return 0; |
| 1871 | } |
| 1872 | |
| 1873 | static int |
| 1874 | Operand_label8_decode (uint32 *valp) |
| 1875 | { |
| 1876 | unsigned label8_0, imm8_0; |
| 1877 | imm8_0 = *valp & 0xff; |
| 1878 | label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24); |
| 1879 | *valp = label8_0; |
| 1880 | return 0; |
| 1881 | } |
| 1882 | |
| 1883 | static int |
| 1884 | Operand_label8_encode (uint32 *valp) |
| 1885 | { |
| 1886 | unsigned imm8_0, label8_0; |
| 1887 | label8_0 = *valp; |
| 1888 | imm8_0 = (label8_0 - 0x4) & 0xff; |
| 1889 | *valp = imm8_0; |
| 1890 | return 0; |
| 1891 | } |
| 1892 | |
| 1893 | static int |
| 1894 | Operand_label8_ator (uint32 *valp, uint32 pc) |
| 1895 | { |
| 1896 | *valp -= pc; |
| 1897 | return 0; |
| 1898 | } |
| 1899 | |
| 1900 | static int |
| 1901 | Operand_label8_rtoa (uint32 *valp, uint32 pc) |
| 1902 | { |
| 1903 | *valp += pc; |
| 1904 | return 0; |
| 1905 | } |
| 1906 | |
| 1907 | static int |
| 1908 | Operand_ulabel8_decode (uint32 *valp) |
| 1909 | { |
| 1910 | unsigned ulabel8_0, imm8_0; |
| 1911 | imm8_0 = *valp & 0xff; |
| 1912 | ulabel8_0 = 0x4 + ((((0)) << 8) | imm8_0); |
| 1913 | *valp = ulabel8_0; |
| 1914 | return 0; |
| 1915 | } |
| 1916 | |
| 1917 | static int |
| 1918 | Operand_ulabel8_encode (uint32 *valp) |
| 1919 | { |
| 1920 | unsigned imm8_0, ulabel8_0; |
| 1921 | ulabel8_0 = *valp; |
| 1922 | imm8_0 = (ulabel8_0 - 0x4) & 0xff; |
| 1923 | *valp = imm8_0; |
| 1924 | return 0; |
| 1925 | } |
| 1926 | |
| 1927 | static int |
| 1928 | Operand_ulabel8_ator (uint32 *valp, uint32 pc) |
| 1929 | { |
| 1930 | *valp -= pc; |
| 1931 | return 0; |
| 1932 | } |
| 1933 | |
| 1934 | static int |
| 1935 | Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) |
| 1936 | { |
| 1937 | *valp += pc; |
| 1938 | return 0; |
| 1939 | } |
| 1940 | |
| 1941 | static int |
| 1942 | Operand_label12_decode (uint32 *valp) |
| 1943 | { |
| 1944 | unsigned label12_0, imm12_0; |
| 1945 | imm12_0 = *valp & 0xfff; |
| 1946 | label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20); |
| 1947 | *valp = label12_0; |
| 1948 | return 0; |
| 1949 | } |
| 1950 | |
| 1951 | static int |
| 1952 | Operand_label12_encode (uint32 *valp) |
| 1953 | { |
| 1954 | unsigned imm12_0, label12_0; |
| 1955 | label12_0 = *valp; |
| 1956 | imm12_0 = (label12_0 - 0x4) & 0xfff; |
| 1957 | *valp = imm12_0; |
| 1958 | return 0; |
| 1959 | } |
| 1960 | |
| 1961 | static int |
| 1962 | Operand_label12_ator (uint32 *valp, uint32 pc) |
| 1963 | { |
| 1964 | *valp -= pc; |
| 1965 | return 0; |
| 1966 | } |
| 1967 | |
| 1968 | static int |
| 1969 | Operand_label12_rtoa (uint32 *valp, uint32 pc) |
| 1970 | { |
| 1971 | *valp += pc; |
| 1972 | return 0; |
| 1973 | } |
| 1974 | |
| 1975 | static int |
| 1976 | Operand_soffset_decode (uint32 *valp) |
| 1977 | { |
| 1978 | unsigned soffset_0, offset_0; |
| 1979 | offset_0 = *valp & 0x3ffff; |
| 1980 | soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14); |
| 1981 | *valp = soffset_0; |
| 1982 | return 0; |
| 1983 | } |
| 1984 | |
| 1985 | static int |
| 1986 | Operand_soffset_encode (uint32 *valp) |
| 1987 | { |
| 1988 | unsigned offset_0, soffset_0; |
| 1989 | soffset_0 = *valp; |
| 1990 | offset_0 = (soffset_0 - 0x4) & 0x3ffff; |
| 1991 | *valp = offset_0; |
| 1992 | return 0; |
| 1993 | } |
| 1994 | |
| 1995 | static int |
| 1996 | Operand_soffset_ator (uint32 *valp, uint32 pc) |
| 1997 | { |
| 1998 | *valp -= pc; |
| 1999 | return 0; |
| 2000 | } |
| 2001 | |
| 2002 | static int |
| 2003 | Operand_soffset_rtoa (uint32 *valp, uint32 pc) |
| 2004 | { |
| 2005 | *valp += pc; |
| 2006 | return 0; |
| 2007 | } |
| 2008 | |
| 2009 | static int |
| 2010 | Operand_uimm16x4_decode (uint32 *valp) |
| 2011 | { |
| 2012 | unsigned uimm16x4_0, imm16_0; |
| 2013 | imm16_0 = *valp & 0xffff; |
| 2014 | uimm16x4_0 = ((((0xffff)) << 16) | imm16_0) << 2; |
| 2015 | *valp = uimm16x4_0; |
| 2016 | return 0; |
| 2017 | } |
| 2018 | |
| 2019 | static int |
| 2020 | Operand_uimm16x4_encode (uint32 *valp) |
| 2021 | { |
| 2022 | unsigned imm16_0, uimm16x4_0; |
| 2023 | uimm16x4_0 = *valp; |
| 2024 | imm16_0 = (uimm16x4_0 >> 2) & 0xffff; |
| 2025 | *valp = imm16_0; |
| 2026 | return 0; |
| 2027 | } |
| 2028 | |
| 2029 | static int |
| 2030 | Operand_uimm16x4_ator (uint32 *valp, uint32 pc) |
| 2031 | { |
| 2032 | *valp -= ((pc + 3) & ~0x3); |
| 2033 | return 0; |
| 2034 | } |
| 2035 | |
| 2036 | static int |
| 2037 | Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) |
| 2038 | { |
| 2039 | *valp += ((pc + 3) & ~0x3); |
| 2040 | return 0; |
| 2041 | } |
| 2042 | |
| 2043 | static int |
| 2044 | Operand_immt_decode (uint32 *valp) |
| 2045 | { |
| 2046 | unsigned immt_0, t_0; |
| 2047 | t_0 = *valp & 0xf; |
| 2048 | immt_0 = t_0; |
| 2049 | *valp = immt_0; |
| 2050 | return 0; |
| 2051 | } |
| 2052 | |
| 2053 | static int |
| 2054 | Operand_immt_encode (uint32 *valp) |
| 2055 | { |
| 2056 | unsigned t_0, immt_0; |
| 2057 | immt_0 = *valp; |
| 2058 | t_0 = immt_0 & 0xf; |
| 2059 | *valp = t_0; |
| 2060 | return 0; |
| 2061 | } |
| 2062 | |
| 2063 | static int |
| 2064 | Operand_imms_decode (uint32 *valp) |
| 2065 | { |
| 2066 | unsigned imms_0, s_0; |
| 2067 | s_0 = *valp & 0xf; |
| 2068 | imms_0 = s_0; |
| 2069 | *valp = imms_0; |
| 2070 | return 0; |
| 2071 | } |
| 2072 | |
| 2073 | static int |
| 2074 | Operand_imms_encode (uint32 *valp) |
| 2075 | { |
| 2076 | unsigned s_0, imms_0; |
| 2077 | imms_0 = *valp; |
| 2078 | s_0 = imms_0 & 0xf; |
| 2079 | *valp = s_0; |
| 2080 | return 0; |
| 2081 | } |
| 2082 | |
| 2083 | static xtensa_operand_internal operands[] = { |
| 2084 | { "soffsetx4", 10, -1, 0, |
| 2085 | XTENSA_OPERAND_IS_PCRELATIVE, |
| 2086 | Operand_soffsetx4_encode, Operand_soffsetx4_decode, |
| 2087 | Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, |
| 2088 | { "uimm12x8", 3, -1, 0, |
| 2089 | 0, |
| 2090 | Operand_uimm12x8_encode, Operand_uimm12x8_decode, |
| 2091 | 0, 0 }, |
| 2092 | { "simm4", 26, -1, 0, |
| 2093 | 0, |
| 2094 | Operand_simm4_encode, Operand_simm4_decode, |
| 2095 | 0, 0 }, |
| 2096 | { "arr", 14, 0, 1, |
| 2097 | XTENSA_OPERAND_IS_REGISTER, |
| 2098 | Operand_arr_encode, Operand_arr_decode, |
| 2099 | 0, 0 }, |
| 2100 | { "ars", 5, 0, 1, |
| 2101 | XTENSA_OPERAND_IS_REGISTER, |
| 2102 | Operand_ars_encode, Operand_ars_decode, |
| 2103 | 0, 0 }, |
| 2104 | { "*ars_invisible", 5, 0, 1, |
| 2105 | XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, |
| 2106 | Operand_ars_encode, Operand_ars_decode, |
| 2107 | 0, 0 }, |
| 2108 | { "art", 0, 0, 1, |
| 2109 | XTENSA_OPERAND_IS_REGISTER, |
| 2110 | Operand_art_encode, Operand_art_decode, |
| 2111 | 0, 0 }, |
| 2112 | { "ar0", 35, 0, 1, |
| 2113 | XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, |
| 2114 | Operand_ar0_encode, Operand_ar0_decode, |
| 2115 | 0, 0 }, |
| 2116 | { "ar4", 36, 0, 1, |
| 2117 | XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, |
| 2118 | Operand_ar4_encode, Operand_ar4_decode, |
| 2119 | 0, 0 }, |
| 2120 | { "ar8", 37, 0, 1, |
| 2121 | XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, |
| 2122 | Operand_ar8_encode, Operand_ar8_decode, |
| 2123 | 0, 0 }, |
| 2124 | { "ar12", 38, 0, 1, |
| 2125 | XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, |
| 2126 | Operand_ar12_encode, Operand_ar12_decode, |
| 2127 | 0, 0 }, |
| 2128 | { "ars_entry", 5, 0, 1, |
| 2129 | XTENSA_OPERAND_IS_REGISTER, |
| 2130 | Operand_ars_entry_encode, Operand_ars_entry_decode, |
| 2131 | 0, 0 }, |
| 2132 | { "immrx4", 14, -1, 0, |
| 2133 | 0, |
| 2134 | Operand_immrx4_encode, Operand_immrx4_decode, |
| 2135 | 0, 0 }, |
| 2136 | { "lsi4x4", 14, -1, 0, |
| 2137 | 0, |
| 2138 | Operand_lsi4x4_encode, Operand_lsi4x4_decode, |
| 2139 | 0, 0 }, |
| 2140 | { "simm7", 34, -1, 0, |
| 2141 | 0, |
| 2142 | Operand_simm7_encode, Operand_simm7_decode, |
| 2143 | 0, 0 }, |
| 2144 | { "uimm6", 33, -1, 0, |
| 2145 | XTENSA_OPERAND_IS_PCRELATIVE, |
| 2146 | Operand_uimm6_encode, Operand_uimm6_decode, |
| 2147 | Operand_uimm6_ator, Operand_uimm6_rtoa }, |
| 2148 | { "ai4const", 0, -1, 0, |
| 2149 | 0, |
| 2150 | Operand_ai4const_encode, Operand_ai4const_decode, |
| 2151 | 0, 0 }, |
| 2152 | { "b4const", 14, -1, 0, |
| 2153 | 0, |
| 2154 | Operand_b4const_encode, Operand_b4const_decode, |
| 2155 | 0, 0 }, |
| 2156 | { "b4constu", 14, -1, 0, |
| 2157 | 0, |
| 2158 | Operand_b4constu_encode, Operand_b4constu_decode, |
| 2159 | 0, 0 }, |
| 2160 | { "uimm8", 4, -1, 0, |
| 2161 | 0, |
| 2162 | Operand_uimm8_encode, Operand_uimm8_decode, |
| 2163 | 0, 0 }, |
| 2164 | { "uimm8x2", 4, -1, 0, |
| 2165 | 0, |
| 2166 | Operand_uimm8x2_encode, Operand_uimm8x2_decode, |
| 2167 | 0, 0 }, |
| 2168 | { "uimm8x4", 4, -1, 0, |
| 2169 | 0, |
| 2170 | Operand_uimm8x4_encode, Operand_uimm8x4_decode, |
| 2171 | 0, 0 }, |
| 2172 | { "uimm4x16", 13, -1, 0, |
| 2173 | 0, |
| 2174 | Operand_uimm4x16_encode, Operand_uimm4x16_decode, |
| 2175 | 0, 0 }, |
| 2176 | { "simm8", 4, -1, 0, |
| 2177 | 0, |
| 2178 | Operand_simm8_encode, Operand_simm8_decode, |
| 2179 | 0, 0 }, |
| 2180 | { "simm8x256", 4, -1, 0, |
| 2181 | 0, |
| 2182 | Operand_simm8x256_encode, Operand_simm8x256_decode, |
| 2183 | 0, 0 }, |
| 2184 | { "simm12b", 6, -1, 0, |
| 2185 | 0, |
| 2186 | Operand_simm12b_encode, Operand_simm12b_decode, |
| 2187 | 0, 0 }, |
| 2188 | { "msalp32", 18, -1, 0, |
| 2189 | 0, |
| 2190 | Operand_msalp32_encode, Operand_msalp32_decode, |
| 2191 | 0, 0 }, |
| 2192 | { "op2p1", 13, -1, 0, |
| 2193 | 0, |
| 2194 | Operand_op2p1_encode, Operand_op2p1_decode, |
| 2195 | 0, 0 }, |
| 2196 | { "label8", 4, -1, 0, |
| 2197 | XTENSA_OPERAND_IS_PCRELATIVE, |
| 2198 | Operand_label8_encode, Operand_label8_decode, |
| 2199 | Operand_label8_ator, Operand_label8_rtoa }, |
| 2200 | { "ulabel8", 4, -1, 0, |
| 2201 | XTENSA_OPERAND_IS_PCRELATIVE, |
| 2202 | Operand_ulabel8_encode, Operand_ulabel8_decode, |
| 2203 | Operand_ulabel8_ator, Operand_ulabel8_rtoa }, |
| 2204 | { "label12", 3, -1, 0, |
| 2205 | XTENSA_OPERAND_IS_PCRELATIVE, |
| 2206 | Operand_label12_encode, Operand_label12_decode, |
| 2207 | Operand_label12_ator, Operand_label12_rtoa }, |
| 2208 | { "soffset", 10, -1, 0, |
| 2209 | XTENSA_OPERAND_IS_PCRELATIVE, |
| 2210 | Operand_soffset_encode, Operand_soffset_decode, |
| 2211 | Operand_soffset_ator, Operand_soffset_rtoa }, |
| 2212 | { "uimm16x4", 7, -1, 0, |
| 2213 | XTENSA_OPERAND_IS_PCRELATIVE, |
| 2214 | Operand_uimm16x4_encode, Operand_uimm16x4_decode, |
| 2215 | Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, |
| 2216 | { "immt", 0, -1, 0, |
| 2217 | 0, |
| 2218 | Operand_immt_encode, Operand_immt_decode, |
| 2219 | 0, 0 }, |
| 2220 | { "imms", 5, -1, 0, |
| 2221 | 0, |
| 2222 | Operand_imms_encode, Operand_imms_decode, |
| 2223 | 0, 0 }, |
| 2224 | { "t", 0, -1, 0, 0, 0, 0, 0, 0 }, |
| 2225 | { "bbi4", 1, -1, 0, 0, 0, 0, 0, 0 }, |
| 2226 | { "bbi", 2, -1, 0, 0, 0, 0, 0, 0 }, |
| 2227 | { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 }, |
| 2228 | { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 }, |
| 2229 | { "s", 5, -1, 0, 0, 0, 0, 0, 0 }, |
| 2230 | { "imm12b", 6, -1, 0, 0, 0, 0, 0, 0 }, |
| 2231 | { "imm16", 7, -1, 0, 0, 0, 0, 0, 0 }, |
| 2232 | { "m", 8, -1, 0, 0, 0, 0, 0, 0 }, |
| 2233 | { "n", 9, -1, 0, 0, 0, 0, 0, 0 }, |
| 2234 | { "offset", 10, -1, 0, 0, 0, 0, 0, 0 }, |
| 2235 | { "op0", 11, -1, 0, 0, 0, 0, 0, 0 }, |
| 2236 | { "op1", 12, -1, 0, 0, 0, 0, 0, 0 }, |
| 2237 | { "op2", 13, -1, 0, 0, 0, 0, 0, 0 }, |
| 2238 | { "r", 14, -1, 0, 0, 0, 0, 0, 0 }, |
| 2239 | { "sa4", 15, -1, 0, 0, 0, 0, 0, 0 }, |
| 2240 | { "sae4", 16, -1, 0, 0, 0, 0, 0, 0 }, |
| 2241 | { "sae", 17, -1, 0, 0, 0, 0, 0, 0 }, |
| 2242 | { "sal", 18, -1, 0, 0, 0, 0, 0, 0 }, |
| 2243 | { "sargt", 19, -1, 0, 0, 0, 0, 0, 0 }, |
| 2244 | { "sas4", 20, -1, 0, 0, 0, 0, 0, 0 }, |
| 2245 | { "sas", 21, -1, 0, 0, 0, 0, 0, 0 }, |
| 2246 | { "sr", 22, -1, 0, 0, 0, 0, 0, 0 }, |
| 2247 | { "st", 23, -1, 0, 0, 0, 0, 0, 0 }, |
| 2248 | { "thi3", 24, -1, 0, 0, 0, 0, 0, 0 }, |
| 2249 | { "imm4", 25, -1, 0, 0, 0, 0, 0, 0 }, |
| 2250 | { "mn", 26, -1, 0, 0, 0, 0, 0, 0 }, |
| 2251 | { "i", 27, -1, 0, 0, 0, 0, 0, 0 }, |
| 2252 | { "imm6lo", 28, -1, 0, 0, 0, 0, 0, 0 }, |
| 2253 | { "imm6hi", 29, -1, 0, 0, 0, 0, 0, 0 }, |
| 2254 | { "imm7lo", 30, -1, 0, 0, 0, 0, 0, 0 }, |
| 2255 | { "imm7hi", 31, -1, 0, 0, 0, 0, 0, 0 }, |
| 2256 | { "z", 32, -1, 0, 0, 0, 0, 0, 0 }, |
| 2257 | { "imm6", 33, -1, 0, 0, 0, 0, 0, 0 }, |
| 2258 | { "imm7", 34, -1, 0, 0, 0, 0, 0, 0 } |
| 2259 | }; |
| 2260 | |
| 2261 | \f |
| 2262 | /* Iclass table. */ |
| 2263 | |
| 2264 | static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { |
| 2265 | { { STATE_PSRING }, 'i' }, |
| 2266 | { { STATE_PSEXCM }, 'm' }, |
| 2267 | { { STATE_EPC1 }, 'i' } |
| 2268 | }; |
| 2269 | |
| 2270 | static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { |
| 2271 | { { STATE_PSEXCM }, 'i' }, |
| 2272 | { { STATE_PSRING }, 'i' }, |
| 2273 | { { STATE_DEPC }, 'i' } |
| 2274 | }; |
| 2275 | |
| 2276 | static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { |
| 2277 | { { 0 /* soffsetx4 */ }, 'i' }, |
| 2278 | { { 10 /* ar12 */ }, 'o' } |
| 2279 | }; |
| 2280 | |
| 2281 | static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { |
| 2282 | { { STATE_PSCALLINC }, 'o' } |
| 2283 | }; |
| 2284 | |
| 2285 | static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { |
| 2286 | { { 0 /* soffsetx4 */ }, 'i' }, |
| 2287 | { { 9 /* ar8 */ }, 'o' } |
| 2288 | }; |
| 2289 | |
| 2290 | static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { |
| 2291 | { { STATE_PSCALLINC }, 'o' } |
| 2292 | }; |
| 2293 | |
| 2294 | static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { |
| 2295 | { { 0 /* soffsetx4 */ }, 'i' }, |
| 2296 | { { 8 /* ar4 */ }, 'o' } |
| 2297 | }; |
| 2298 | |
| 2299 | static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { |
| 2300 | { { STATE_PSCALLINC }, 'o' } |
| 2301 | }; |
| 2302 | |
| 2303 | static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { |
| 2304 | { { 4 /* ars */ }, 'i' }, |
| 2305 | { { 10 /* ar12 */ }, 'o' } |
| 2306 | }; |
| 2307 | |
| 2308 | static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { |
| 2309 | { { STATE_PSCALLINC }, 'o' } |
| 2310 | }; |
| 2311 | |
| 2312 | static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { |
| 2313 | { { 4 /* ars */ }, 'i' }, |
| 2314 | { { 9 /* ar8 */ }, 'o' } |
| 2315 | }; |
| 2316 | |
| 2317 | static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { |
| 2318 | { { STATE_PSCALLINC }, 'o' } |
| 2319 | }; |
| 2320 | |
| 2321 | static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { |
| 2322 | { { 4 /* ars */ }, 'i' }, |
| 2323 | { { 8 /* ar4 */ }, 'o' } |
| 2324 | }; |
| 2325 | |
| 2326 | static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { |
| 2327 | { { STATE_PSCALLINC }, 'o' } |
| 2328 | }; |
| 2329 | |
| 2330 | static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { |
| 2331 | { { 11 /* ars_entry */ }, 's' }, |
| 2332 | { { 4 /* ars */ }, 'i' }, |
| 2333 | { { 1 /* uimm12x8 */ }, 'i' } |
| 2334 | }; |
| 2335 | |
| 2336 | static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { |
| 2337 | { { STATE_PSCALLINC }, 'i' }, |
| 2338 | { { STATE_PSEXCM }, 'i' }, |
| 2339 | { { STATE_PSWOE }, 'i' }, |
| 2340 | { { STATE_WindowBase }, 'm' }, |
| 2341 | { { STATE_WindowStart }, 'm' } |
| 2342 | }; |
| 2343 | |
| 2344 | static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { |
| 2345 | { { 6 /* art */ }, 'o' }, |
| 2346 | { { 4 /* ars */ }, 'i' } |
| 2347 | }; |
| 2348 | |
| 2349 | static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { |
| 2350 | { { STATE_WindowBase }, 'i' }, |
| 2351 | { { STATE_WindowStart }, 'i' } |
| 2352 | }; |
| 2353 | |
| 2354 | static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { |
| 2355 | { { 2 /* simm4 */ }, 'i' } |
| 2356 | }; |
| 2357 | |
| 2358 | static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { |
| 2359 | { { STATE_PSEXCM }, 'i' }, |
| 2360 | { { STATE_PSRING }, 'i' }, |
| 2361 | { { STATE_WindowBase }, 'm' } |
| 2362 | }; |
| 2363 | |
| 2364 | static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { |
| 2365 | { { 5 /* *ars_invisible */ }, 'i' } |
| 2366 | }; |
| 2367 | |
| 2368 | static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { |
| 2369 | { { STATE_WindowBase }, 'm' }, |
| 2370 | { { STATE_WindowStart }, 'm' }, |
| 2371 | { { STATE_PSEXCM }, 'i' }, |
| 2372 | { { STATE_PSWOE }, 'i' } |
| 2373 | }; |
| 2374 | |
| 2375 | static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { |
| 2376 | { { STATE_EPC1 }, 'i' }, |
| 2377 | { { STATE_PSEXCM }, 'm' }, |
| 2378 | { { STATE_PSRING }, 'i' }, |
| 2379 | { { STATE_WindowBase }, 'm' }, |
| 2380 | { { STATE_WindowStart }, 'm' }, |
| 2381 | { { STATE_PSOWB }, 'i' } |
| 2382 | }; |
| 2383 | |
| 2384 | static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { |
| 2385 | { { 6 /* art */ }, 'o' }, |
| 2386 | { { 4 /* ars */ }, 'i' }, |
| 2387 | { { 12 /* immrx4 */ }, 'i' } |
| 2388 | }; |
| 2389 | |
| 2390 | static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = { |
| 2391 | { { STATE_PSEXCM }, 'i' }, |
| 2392 | { { STATE_PSRING }, 'i' } |
| 2393 | }; |
| 2394 | |
| 2395 | static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { |
| 2396 | { { 6 /* art */ }, 'i' }, |
| 2397 | { { 4 /* ars */ }, 'i' }, |
| 2398 | { { 12 /* immrx4 */ }, 'i' } |
| 2399 | }; |
| 2400 | |
| 2401 | static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = { |
| 2402 | { { STATE_PSEXCM }, 'i' }, |
| 2403 | { { STATE_PSRING }, 'i' } |
| 2404 | }; |
| 2405 | |
| 2406 | static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { |
| 2407 | { { 6 /* art */ }, 'o' } |
| 2408 | }; |
| 2409 | |
| 2410 | static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { |
| 2411 | { { STATE_PSEXCM }, 'i' }, |
| 2412 | { { STATE_PSRING }, 'i' }, |
| 2413 | { { STATE_WindowBase }, 'i' } |
| 2414 | }; |
| 2415 | |
| 2416 | static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { |
| 2417 | { { 6 /* art */ }, 'i' } |
| 2418 | }; |
| 2419 | |
| 2420 | static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { |
| 2421 | { { STATE_PSEXCM }, 'i' }, |
| 2422 | { { STATE_PSRING }, 'i' }, |
| 2423 | { { STATE_WindowBase }, 'o' } |
| 2424 | }; |
| 2425 | |
| 2426 | static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { |
| 2427 | { { 6 /* art */ }, 'm' } |
| 2428 | }; |
| 2429 | |
| 2430 | static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { |
| 2431 | { { STATE_PSEXCM }, 'i' }, |
| 2432 | { { STATE_PSRING }, 'i' }, |
| 2433 | { { STATE_WindowBase }, 'm' } |
| 2434 | }; |
| 2435 | |
| 2436 | static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { |
| 2437 | { { 6 /* art */ }, 'o' } |
| 2438 | }; |
| 2439 | |
| 2440 | static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { |
| 2441 | { { STATE_PSEXCM }, 'i' }, |
| 2442 | { { STATE_PSRING }, 'i' }, |
| 2443 | { { STATE_WindowStart }, 'i' } |
| 2444 | }; |
| 2445 | |
| 2446 | static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { |
| 2447 | { { 6 /* art */ }, 'i' } |
| 2448 | }; |
| 2449 | |
| 2450 | static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { |
| 2451 | { { STATE_PSEXCM }, 'i' }, |
| 2452 | { { STATE_PSRING }, 'i' }, |
| 2453 | { { STATE_WindowStart }, 'o' } |
| 2454 | }; |
| 2455 | |
| 2456 | static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { |
| 2457 | { { 6 /* art */ }, 'm' } |
| 2458 | }; |
| 2459 | |
| 2460 | static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { |
| 2461 | { { STATE_PSEXCM }, 'i' }, |
| 2462 | { { STATE_PSRING }, 'i' }, |
| 2463 | { { STATE_WindowStart }, 'm' } |
| 2464 | }; |
| 2465 | |
| 2466 | static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { |
| 2467 | { { 3 /* arr */ }, 'o' }, |
| 2468 | { { 4 /* ars */ }, 'i' }, |
| 2469 | { { 6 /* art */ }, 'i' } |
| 2470 | }; |
| 2471 | |
| 2472 | static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { |
| 2473 | { { 3 /* arr */ }, 'o' }, |
| 2474 | { { 4 /* ars */ }, 'i' }, |
| 2475 | { { 16 /* ai4const */ }, 'i' } |
| 2476 | }; |
| 2477 | |
| 2478 | static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { |
| 2479 | { { 4 /* ars */ }, 'i' }, |
| 2480 | { { 15 /* uimm6 */ }, 'i' } |
| 2481 | }; |
| 2482 | |
| 2483 | static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { |
| 2484 | { { 6 /* art */ }, 'o' }, |
| 2485 | { { 4 /* ars */ }, 'i' }, |
| 2486 | { { 13 /* lsi4x4 */ }, 'i' } |
| 2487 | }; |
| 2488 | |
| 2489 | static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { |
| 2490 | { { 6 /* art */ }, 'o' }, |
| 2491 | { { 4 /* ars */ }, 'i' } |
| 2492 | }; |
| 2493 | |
| 2494 | static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { |
| 2495 | { { 4 /* ars */ }, 'o' }, |
| 2496 | { { 14 /* simm7 */ }, 'i' } |
| 2497 | }; |
| 2498 | |
| 2499 | static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { |
| 2500 | { { 5 /* *ars_invisible */ }, 'i' } |
| 2501 | }; |
| 2502 | |
| 2503 | static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { |
| 2504 | { { 6 /* art */ }, 'i' }, |
| 2505 | { { 4 /* ars */ }, 'i' }, |
| 2506 | { { 13 /* lsi4x4 */ }, 'i' } |
| 2507 | }; |
| 2508 | |
| 2509 | static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { |
| 2510 | { { 6 /* art */ }, 'o' }, |
| 2511 | { { 4 /* ars */ }, 'i' }, |
| 2512 | { { 23 /* simm8 */ }, 'i' } |
| 2513 | }; |
| 2514 | |
| 2515 | static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { |
| 2516 | { { 6 /* art */ }, 'o' }, |
| 2517 | { { 4 /* ars */ }, 'i' }, |
| 2518 | { { 24 /* simm8x256 */ }, 'i' } |
| 2519 | }; |
| 2520 | |
| 2521 | static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { |
| 2522 | { { 3 /* arr */ }, 'o' }, |
| 2523 | { { 4 /* ars */ }, 'i' }, |
| 2524 | { { 6 /* art */ }, 'i' } |
| 2525 | }; |
| 2526 | |
| 2527 | static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { |
| 2528 | { { 3 /* arr */ }, 'o' }, |
| 2529 | { { 4 /* ars */ }, 'i' }, |
| 2530 | { { 6 /* art */ }, 'i' } |
| 2531 | }; |
| 2532 | |
| 2533 | static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { |
| 2534 | { { 4 /* ars */ }, 'i' }, |
| 2535 | { { 17 /* b4const */ }, 'i' }, |
| 2536 | { { 28 /* label8 */ }, 'i' } |
| 2537 | }; |
| 2538 | |
| 2539 | static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { |
| 2540 | { { 4 /* ars */ }, 'i' }, |
| 2541 | { { 37 /* bbi */ }, 'i' }, |
| 2542 | { { 28 /* label8 */ }, 'i' } |
| 2543 | }; |
| 2544 | |
| 2545 | static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { |
| 2546 | { { 4 /* ars */ }, 'i' }, |
| 2547 | { { 18 /* b4constu */ }, 'i' }, |
| 2548 | { { 28 /* label8 */ }, 'i' } |
| 2549 | }; |
| 2550 | |
| 2551 | static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { |
| 2552 | { { 4 /* ars */ }, 'i' }, |
| 2553 | { { 6 /* art */ }, 'i' }, |
| 2554 | { { 28 /* label8 */ }, 'i' } |
| 2555 | }; |
| 2556 | |
| 2557 | static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { |
| 2558 | { { 4 /* ars */ }, 'i' }, |
| 2559 | { { 30 /* label12 */ }, 'i' } |
| 2560 | }; |
| 2561 | |
| 2562 | static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { |
| 2563 | { { 0 /* soffsetx4 */ }, 'i' }, |
| 2564 | { { 7 /* ar0 */ }, 'o' } |
| 2565 | }; |
| 2566 | |
| 2567 | static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { |
| 2568 | { { 4 /* ars */ }, 'i' }, |
| 2569 | { { 7 /* ar0 */ }, 'o' } |
| 2570 | }; |
| 2571 | |
| 2572 | static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { |
| 2573 | { { 3 /* arr */ }, 'o' }, |
| 2574 | { { 6 /* art */ }, 'i' }, |
| 2575 | { { 52 /* sae */ }, 'i' }, |
| 2576 | { { 27 /* op2p1 */ }, 'i' } |
| 2577 | }; |
| 2578 | |
| 2579 | static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { |
| 2580 | { { 31 /* soffset */ }, 'i' } |
| 2581 | }; |
| 2582 | |
| 2583 | static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { |
| 2584 | { { 4 /* ars */ }, 'i' } |
| 2585 | }; |
| 2586 | |
| 2587 | static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { |
| 2588 | { { 6 /* art */ }, 'o' }, |
| 2589 | { { 4 /* ars */ }, 'i' }, |
| 2590 | { { 20 /* uimm8x2 */ }, 'i' } |
| 2591 | }; |
| 2592 | |
| 2593 | static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { |
| 2594 | { { 6 /* art */ }, 'o' }, |
| 2595 | { { 4 /* ars */ }, 'i' }, |
| 2596 | { { 20 /* uimm8x2 */ }, 'i' } |
| 2597 | }; |
| 2598 | |
| 2599 | static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { |
| 2600 | { { 6 /* art */ }, 'o' }, |
| 2601 | { { 4 /* ars */ }, 'i' }, |
| 2602 | { { 21 /* uimm8x4 */ }, 'i' } |
| 2603 | }; |
| 2604 | |
| 2605 | static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { |
| 2606 | { { 6 /* art */ }, 'o' }, |
| 2607 | { { 32 /* uimm16x4 */ }, 'i' } |
| 2608 | }; |
| 2609 | |
| 2610 | static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = { |
| 2611 | { { STATE_LITBADDR }, 'i' }, |
| 2612 | { { STATE_LITBEN }, 'i' } |
| 2613 | }; |
| 2614 | |
| 2615 | static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { |
| 2616 | { { 6 /* art */ }, 'o' }, |
| 2617 | { { 4 /* ars */ }, 'i' }, |
| 2618 | { { 19 /* uimm8 */ }, 'i' } |
| 2619 | }; |
| 2620 | |
| 2621 | static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { |
| 2622 | { { 4 /* ars */ }, 'i' }, |
| 2623 | { { 29 /* ulabel8 */ }, 'i' } |
| 2624 | }; |
| 2625 | |
| 2626 | static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { |
| 2627 | { { STATE_LBEG }, 'o' }, |
| 2628 | { { STATE_LEND }, 'o' }, |
| 2629 | { { STATE_LCOUNT }, 'o' } |
| 2630 | }; |
| 2631 | |
| 2632 | static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { |
| 2633 | { { 4 /* ars */ }, 'i' }, |
| 2634 | { { 29 /* ulabel8 */ }, 'i' } |
| 2635 | }; |
| 2636 | |
| 2637 | static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { |
| 2638 | { { STATE_LBEG }, 'o' }, |
| 2639 | { { STATE_LEND }, 'o' }, |
| 2640 | { { STATE_LCOUNT }, 'o' } |
| 2641 | }; |
| 2642 | |
| 2643 | static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { |
| 2644 | { { 6 /* art */ }, 'o' }, |
| 2645 | { { 25 /* simm12b */ }, 'i' } |
| 2646 | }; |
| 2647 | |
| 2648 | static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { |
| 2649 | { { 3 /* arr */ }, 'm' }, |
| 2650 | { { 4 /* ars */ }, 'i' }, |
| 2651 | { { 6 /* art */ }, 'i' } |
| 2652 | }; |
| 2653 | |
| 2654 | static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { |
| 2655 | { { 3 /* arr */ }, 'o' }, |
| 2656 | { { 6 /* art */ }, 'i' } |
| 2657 | }; |
| 2658 | |
| 2659 | static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { |
| 2660 | { { 5 /* *ars_invisible */ }, 'i' } |
| 2661 | }; |
| 2662 | |
| 2663 | static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { |
| 2664 | { { 6 /* art */ }, 'i' }, |
| 2665 | { { 4 /* ars */ }, 'i' }, |
| 2666 | { { 20 /* uimm8x2 */ }, 'i' } |
| 2667 | }; |
| 2668 | |
| 2669 | static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { |
| 2670 | { { 6 /* art */ }, 'i' }, |
| 2671 | { { 4 /* ars */ }, 'i' }, |
| 2672 | { { 21 /* uimm8x4 */ }, 'i' } |
| 2673 | }; |
| 2674 | |
| 2675 | static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { |
| 2676 | { { 6 /* art */ }, 'i' }, |
| 2677 | { { 4 /* ars */ }, 'i' }, |
| 2678 | { { 19 /* uimm8 */ }, 'i' } |
| 2679 | }; |
| 2680 | |
| 2681 | static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { |
| 2682 | { { 4 /* ars */ }, 'i' } |
| 2683 | }; |
| 2684 | |
| 2685 | static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { |
| 2686 | { { STATE_SAR }, 'o' } |
| 2687 | }; |
| 2688 | |
| 2689 | static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { |
| 2690 | { { 56 /* sas */ }, 'i' } |
| 2691 | }; |
| 2692 | |
| 2693 | static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { |
| 2694 | { { STATE_SAR }, 'o' } |
| 2695 | }; |
| 2696 | |
| 2697 | static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { |
| 2698 | { { 3 /* arr */ }, 'o' }, |
| 2699 | { { 4 /* ars */ }, 'i' } |
| 2700 | }; |
| 2701 | |
| 2702 | static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { |
| 2703 | { { STATE_SAR }, 'i' } |
| 2704 | }; |
| 2705 | |
| 2706 | static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { |
| 2707 | { { 3 /* arr */ }, 'o' }, |
| 2708 | { { 4 /* ars */ }, 'i' }, |
| 2709 | { { 6 /* art */ }, 'i' } |
| 2710 | }; |
| 2711 | |
| 2712 | static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { |
| 2713 | { { STATE_SAR }, 'i' } |
| 2714 | }; |
| 2715 | |
| 2716 | static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { |
| 2717 | { { 3 /* arr */ }, 'o' }, |
| 2718 | { { 6 /* art */ }, 'i' } |
| 2719 | }; |
| 2720 | |
| 2721 | static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { |
| 2722 | { { STATE_SAR }, 'i' } |
| 2723 | }; |
| 2724 | |
| 2725 | static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { |
| 2726 | { { 3 /* arr */ }, 'o' }, |
| 2727 | { { 4 /* ars */ }, 'i' }, |
| 2728 | { { 26 /* msalp32 */ }, 'i' } |
| 2729 | }; |
| 2730 | |
| 2731 | static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { |
| 2732 | { { 3 /* arr */ }, 'o' }, |
| 2733 | { { 6 /* art */ }, 'i' }, |
| 2734 | { { 54 /* sargt */ }, 'i' } |
| 2735 | }; |
| 2736 | |
| 2737 | static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { |
| 2738 | { { 3 /* arr */ }, 'o' }, |
| 2739 | { { 6 /* art */ }, 'i' }, |
| 2740 | { { 40 /* s */ }, 'i' } |
| 2741 | }; |
| 2742 | |
| 2743 | static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { |
| 2744 | { { STATE_XTSYNC }, 'i' } |
| 2745 | }; |
| 2746 | |
| 2747 | static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { |
| 2748 | { { 6 /* art */ }, 'o' }, |
| 2749 | { { 40 /* s */ }, 'i' } |
| 2750 | }; |
| 2751 | |
| 2752 | static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { |
| 2753 | { { STATE_PSWOE }, 'i' }, |
| 2754 | { { STATE_PSCALLINC }, 'i' }, |
| 2755 | { { STATE_PSOWB }, 'i' }, |
| 2756 | { { STATE_PSRING }, 'i' }, |
| 2757 | { { STATE_PSUM }, 'i' }, |
| 2758 | { { STATE_PSEXCM }, 'i' }, |
| 2759 | { { STATE_PSINTLEVEL }, 'm' } |
| 2760 | }; |
| 2761 | |
| 2762 | static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { |
| 2763 | { { 6 /* art */ }, 'o' } |
| 2764 | }; |
| 2765 | |
| 2766 | static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { |
| 2767 | { { STATE_LEND }, 'i' } |
| 2768 | }; |
| 2769 | |
| 2770 | static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { |
| 2771 | { { 6 /* art */ }, 'i' } |
| 2772 | }; |
| 2773 | |
| 2774 | static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { |
| 2775 | { { STATE_LEND }, 'o' } |
| 2776 | }; |
| 2777 | |
| 2778 | static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { |
| 2779 | { { 6 /* art */ }, 'm' } |
| 2780 | }; |
| 2781 | |
| 2782 | static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { |
| 2783 | { { STATE_LEND }, 'm' } |
| 2784 | }; |
| 2785 | |
| 2786 | static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { |
| 2787 | { { 6 /* art */ }, 'o' } |
| 2788 | }; |
| 2789 | |
| 2790 | static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { |
| 2791 | { { STATE_LCOUNT }, 'i' } |
| 2792 | }; |
| 2793 | |
| 2794 | static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { |
| 2795 | { { 6 /* art */ }, 'i' } |
| 2796 | }; |
| 2797 | |
| 2798 | static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { |
| 2799 | { { STATE_XTSYNC }, 'o' }, |
| 2800 | { { STATE_LCOUNT }, 'o' } |
| 2801 | }; |
| 2802 | |
| 2803 | static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { |
| 2804 | { { 6 /* art */ }, 'm' } |
| 2805 | }; |
| 2806 | |
| 2807 | static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { |
| 2808 | { { STATE_XTSYNC }, 'o' }, |
| 2809 | { { STATE_LCOUNT }, 'm' } |
| 2810 | }; |
| 2811 | |
| 2812 | static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { |
| 2813 | { { 6 /* art */ }, 'o' } |
| 2814 | }; |
| 2815 | |
| 2816 | static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { |
| 2817 | { { STATE_LBEG }, 'i' } |
| 2818 | }; |
| 2819 | |
| 2820 | static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { |
| 2821 | { { 6 /* art */ }, 'i' } |
| 2822 | }; |
| 2823 | |
| 2824 | static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { |
| 2825 | { { STATE_LBEG }, 'o' } |
| 2826 | }; |
| 2827 | |
| 2828 | static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { |
| 2829 | { { 6 /* art */ }, 'm' } |
| 2830 | }; |
| 2831 | |
| 2832 | static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { |
| 2833 | { { STATE_LBEG }, 'm' } |
| 2834 | }; |
| 2835 | |
| 2836 | static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { |
| 2837 | { { 6 /* art */ }, 'o' } |
| 2838 | }; |
| 2839 | |
| 2840 | static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { |
| 2841 | { { STATE_SAR }, 'i' } |
| 2842 | }; |
| 2843 | |
| 2844 | static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { |
| 2845 | { { 6 /* art */ }, 'i' } |
| 2846 | }; |
| 2847 | |
| 2848 | static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { |
| 2849 | { { STATE_SAR }, 'o' }, |
| 2850 | { { STATE_XTSYNC }, 'o' } |
| 2851 | }; |
| 2852 | |
| 2853 | static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { |
| 2854 | { { 6 /* art */ }, 'm' } |
| 2855 | }; |
| 2856 | |
| 2857 | static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { |
| 2858 | { { STATE_SAR }, 'm' } |
| 2859 | }; |
| 2860 | |
| 2861 | static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { |
| 2862 | { { 6 /* art */ }, 'o' } |
| 2863 | }; |
| 2864 | |
| 2865 | static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = { |
| 2866 | { { STATE_LITBADDR }, 'i' }, |
| 2867 | { { STATE_LITBEN }, 'i' } |
| 2868 | }; |
| 2869 | |
| 2870 | static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { |
| 2871 | { { 6 /* art */ }, 'i' } |
| 2872 | }; |
| 2873 | |
| 2874 | static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = { |
| 2875 | { { STATE_LITBADDR }, 'o' }, |
| 2876 | { { STATE_LITBEN }, 'o' } |
| 2877 | }; |
| 2878 | |
| 2879 | static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { |
| 2880 | { { 6 /* art */ }, 'm' } |
| 2881 | }; |
| 2882 | |
| 2883 | static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = { |
| 2884 | { { STATE_LITBADDR }, 'm' }, |
| 2885 | { { STATE_LITBEN }, 'm' } |
| 2886 | }; |
| 2887 | |
| 2888 | static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = { |
| 2889 | { { 6 /* art */ }, 'o' } |
| 2890 | }; |
| 2891 | |
| 2892 | static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = { |
| 2893 | { { STATE_PSEXCM }, 'i' }, |
| 2894 | { { STATE_PSRING }, 'i' } |
| 2895 | }; |
| 2896 | |
| 2897 | static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = { |
| 2898 | { { 6 /* art */ }, 'o' } |
| 2899 | }; |
| 2900 | |
| 2901 | static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = { |
| 2902 | { { STATE_PSEXCM }, 'i' }, |
| 2903 | { { STATE_PSRING }, 'i' } |
| 2904 | }; |
| 2905 | |
| 2906 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { |
| 2907 | { { 6 /* art */ }, 'o' } |
| 2908 | }; |
| 2909 | |
| 2910 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { |
| 2911 | { { STATE_PSWOE }, 'i' }, |
| 2912 | { { STATE_PSCALLINC }, 'i' }, |
| 2913 | { { STATE_PSOWB }, 'i' }, |
| 2914 | { { STATE_PSRING }, 'i' }, |
| 2915 | { { STATE_PSUM }, 'i' }, |
| 2916 | { { STATE_PSEXCM }, 'i' }, |
| 2917 | { { STATE_PSINTLEVEL }, 'i' } |
| 2918 | }; |
| 2919 | |
| 2920 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { |
| 2921 | { { 6 /* art */ }, 'i' } |
| 2922 | }; |
| 2923 | |
| 2924 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { |
| 2925 | { { STATE_PSWOE }, 'o' }, |
| 2926 | { { STATE_PSCALLINC }, 'o' }, |
| 2927 | { { STATE_PSOWB }, 'o' }, |
| 2928 | { { STATE_PSRING }, 'm' }, |
| 2929 | { { STATE_PSUM }, 'o' }, |
| 2930 | { { STATE_PSEXCM }, 'm' }, |
| 2931 | { { STATE_PSINTLEVEL }, 'o' } |
| 2932 | }; |
| 2933 | |
| 2934 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { |
| 2935 | { { 6 /* art */ }, 'm' } |
| 2936 | }; |
| 2937 | |
| 2938 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { |
| 2939 | { { STATE_PSWOE }, 'm' }, |
| 2940 | { { STATE_PSCALLINC }, 'm' }, |
| 2941 | { { STATE_PSOWB }, 'm' }, |
| 2942 | { { STATE_PSRING }, 'm' }, |
| 2943 | { { STATE_PSUM }, 'm' }, |
| 2944 | { { STATE_PSEXCM }, 'm' }, |
| 2945 | { { STATE_PSINTLEVEL }, 'm' } |
| 2946 | }; |
| 2947 | |
| 2948 | static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { |
| 2949 | { { 6 /* art */ }, 'o' } |
| 2950 | }; |
| 2951 | |
| 2952 | static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { |
| 2953 | { { STATE_PSEXCM }, 'i' }, |
| 2954 | { { STATE_PSRING }, 'i' }, |
| 2955 | { { STATE_EPC1 }, 'i' } |
| 2956 | }; |
| 2957 | |
| 2958 | static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { |
| 2959 | { { 6 /* art */ }, 'i' } |
| 2960 | }; |
| 2961 | |
| 2962 | static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { |
| 2963 | { { STATE_PSEXCM }, 'i' }, |
| 2964 | { { STATE_PSRING }, 'i' }, |
| 2965 | { { STATE_EPC1 }, 'o' } |
| 2966 | }; |
| 2967 | |
| 2968 | static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { |
| 2969 | { { 6 /* art */ }, 'm' } |
| 2970 | }; |
| 2971 | |
| 2972 | static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { |
| 2973 | { { STATE_PSEXCM }, 'i' }, |
| 2974 | { { STATE_PSRING }, 'i' }, |
| 2975 | { { STATE_EPC1 }, 'm' } |
| 2976 | }; |
| 2977 | |
| 2978 | static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { |
| 2979 | { { 6 /* art */ }, 'o' } |
| 2980 | }; |
| 2981 | |
| 2982 | static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { |
| 2983 | { { STATE_PSEXCM }, 'i' }, |
| 2984 | { { STATE_PSRING }, 'i' }, |
| 2985 | { { STATE_EXCSAVE1 }, 'i' } |
| 2986 | }; |
| 2987 | |
| 2988 | static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { |
| 2989 | { { 6 /* art */ }, 'i' } |
| 2990 | }; |
| 2991 | |
| 2992 | static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { |
| 2993 | { { STATE_PSEXCM }, 'i' }, |
| 2994 | { { STATE_PSRING }, 'i' }, |
| 2995 | { { STATE_EXCSAVE1 }, 'o' } |
| 2996 | }; |
| 2997 | |
| 2998 | static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { |
| 2999 | { { 6 /* art */ }, 'm' } |
| 3000 | }; |
| 3001 | |
| 3002 | static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { |
| 3003 | { { STATE_PSEXCM }, 'i' }, |
| 3004 | { { STATE_PSRING }, 'i' }, |
| 3005 | { { STATE_EXCSAVE1 }, 'm' } |
| 3006 | }; |
| 3007 | |
| 3008 | static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { |
| 3009 | { { 6 /* art */ }, 'o' } |
| 3010 | }; |
| 3011 | |
| 3012 | static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { |
| 3013 | { { STATE_PSEXCM }, 'i' }, |
| 3014 | { { STATE_PSRING }, 'i' }, |
| 3015 | { { STATE_EPC2 }, 'i' } |
| 3016 | }; |
| 3017 | |
| 3018 | static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { |
| 3019 | { { 6 /* art */ }, 'i' } |
| 3020 | }; |
| 3021 | |
| 3022 | static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { |
| 3023 | { { STATE_PSEXCM }, 'i' }, |
| 3024 | { { STATE_PSRING }, 'i' }, |
| 3025 | { { STATE_EPC2 }, 'o' } |
| 3026 | }; |
| 3027 | |
| 3028 | static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { |
| 3029 | { { 6 /* art */ }, 'm' } |
| 3030 | }; |
| 3031 | |
| 3032 | static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { |
| 3033 | { { STATE_PSEXCM }, 'i' }, |
| 3034 | { { STATE_PSRING }, 'i' }, |
| 3035 | { { STATE_EPC2 }, 'm' } |
| 3036 | }; |
| 3037 | |
| 3038 | static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { |
| 3039 | { { 6 /* art */ }, 'o' } |
| 3040 | }; |
| 3041 | |
| 3042 | static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { |
| 3043 | { { STATE_PSEXCM }, 'i' }, |
| 3044 | { { STATE_PSRING }, 'i' }, |
| 3045 | { { STATE_EXCSAVE2 }, 'i' } |
| 3046 | }; |
| 3047 | |
| 3048 | static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { |
| 3049 | { { 6 /* art */ }, 'i' } |
| 3050 | }; |
| 3051 | |
| 3052 | static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { |
| 3053 | { { STATE_PSEXCM }, 'i' }, |
| 3054 | { { STATE_PSRING }, 'i' }, |
| 3055 | { { STATE_EXCSAVE2 }, 'o' } |
| 3056 | }; |
| 3057 | |
| 3058 | static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { |
| 3059 | { { 6 /* art */ }, 'm' } |
| 3060 | }; |
| 3061 | |
| 3062 | static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { |
| 3063 | { { STATE_PSEXCM }, 'i' }, |
| 3064 | { { STATE_PSRING }, 'i' }, |
| 3065 | { { STATE_EXCSAVE2 }, 'm' } |
| 3066 | }; |
| 3067 | |
| 3068 | static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { |
| 3069 | { { 6 /* art */ }, 'o' } |
| 3070 | }; |
| 3071 | |
| 3072 | static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { |
| 3073 | { { STATE_PSEXCM }, 'i' }, |
| 3074 | { { STATE_PSRING }, 'i' }, |
| 3075 | { { STATE_EPC3 }, 'i' } |
| 3076 | }; |
| 3077 | |
| 3078 | static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { |
| 3079 | { { 6 /* art */ }, 'i' } |
| 3080 | }; |
| 3081 | |
| 3082 | static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { |
| 3083 | { { STATE_PSEXCM }, 'i' }, |
| 3084 | { { STATE_PSRING }, 'i' }, |
| 3085 | { { STATE_EPC3 }, 'o' } |
| 3086 | }; |
| 3087 | |
| 3088 | static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { |
| 3089 | { { 6 /* art */ }, 'm' } |
| 3090 | }; |
| 3091 | |
| 3092 | static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { |
| 3093 | { { STATE_PSEXCM }, 'i' }, |
| 3094 | { { STATE_PSRING }, 'i' }, |
| 3095 | { { STATE_EPC3 }, 'm' } |
| 3096 | }; |
| 3097 | |
| 3098 | static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { |
| 3099 | { { 6 /* art */ }, 'o' } |
| 3100 | }; |
| 3101 | |
| 3102 | static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { |
| 3103 | { { STATE_PSEXCM }, 'i' }, |
| 3104 | { { STATE_PSRING }, 'i' }, |
| 3105 | { { STATE_EXCSAVE3 }, 'i' } |
| 3106 | }; |
| 3107 | |
| 3108 | static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { |
| 3109 | { { 6 /* art */ }, 'i' } |
| 3110 | }; |
| 3111 | |
| 3112 | static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { |
| 3113 | { { STATE_PSEXCM }, 'i' }, |
| 3114 | { { STATE_PSRING }, 'i' }, |
| 3115 | { { STATE_EXCSAVE3 }, 'o' } |
| 3116 | }; |
| 3117 | |
| 3118 | static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { |
| 3119 | { { 6 /* art */ }, 'm' } |
| 3120 | }; |
| 3121 | |
| 3122 | static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { |
| 3123 | { { STATE_PSEXCM }, 'i' }, |
| 3124 | { { STATE_PSRING }, 'i' }, |
| 3125 | { { STATE_EXCSAVE3 }, 'm' } |
| 3126 | }; |
| 3127 | |
| 3128 | static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { |
| 3129 | { { 6 /* art */ }, 'o' } |
| 3130 | }; |
| 3131 | |
| 3132 | static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { |
| 3133 | { { STATE_PSEXCM }, 'i' }, |
| 3134 | { { STATE_PSRING }, 'i' }, |
| 3135 | { { STATE_EPC4 }, 'i' } |
| 3136 | }; |
| 3137 | |
| 3138 | static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { |
| 3139 | { { 6 /* art */ }, 'i' } |
| 3140 | }; |
| 3141 | |
| 3142 | static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { |
| 3143 | { { STATE_PSEXCM }, 'i' }, |
| 3144 | { { STATE_PSRING }, 'i' }, |
| 3145 | { { STATE_EPC4 }, 'o' } |
| 3146 | }; |
| 3147 | |
| 3148 | static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { |
| 3149 | { { 6 /* art */ }, 'm' } |
| 3150 | }; |
| 3151 | |
| 3152 | static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { |
| 3153 | { { STATE_PSEXCM }, 'i' }, |
| 3154 | { { STATE_PSRING }, 'i' }, |
| 3155 | { { STATE_EPC4 }, 'm' } |
| 3156 | }; |
| 3157 | |
| 3158 | static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { |
| 3159 | { { 6 /* art */ }, 'o' } |
| 3160 | }; |
| 3161 | |
| 3162 | static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { |
| 3163 | { { STATE_PSEXCM }, 'i' }, |
| 3164 | { { STATE_PSRING }, 'i' }, |
| 3165 | { { STATE_EXCSAVE4 }, 'i' } |
| 3166 | }; |
| 3167 | |
| 3168 | static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { |
| 3169 | { { 6 /* art */ }, 'i' } |
| 3170 | }; |
| 3171 | |
| 3172 | static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { |
| 3173 | { { STATE_PSEXCM }, 'i' }, |
| 3174 | { { STATE_PSRING }, 'i' }, |
| 3175 | { { STATE_EXCSAVE4 }, 'o' } |
| 3176 | }; |
| 3177 | |
| 3178 | static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { |
| 3179 | { { 6 /* art */ }, 'm' } |
| 3180 | }; |
| 3181 | |
| 3182 | static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { |
| 3183 | { { STATE_PSEXCM }, 'i' }, |
| 3184 | { { STATE_PSRING }, 'i' }, |
| 3185 | { { STATE_EXCSAVE4 }, 'm' } |
| 3186 | }; |
| 3187 | |
| 3188 | static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { |
| 3189 | { { 6 /* art */ }, 'o' } |
| 3190 | }; |
| 3191 | |
| 3192 | static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { |
| 3193 | { { STATE_PSEXCM }, 'i' }, |
| 3194 | { { STATE_PSRING }, 'i' }, |
| 3195 | { { STATE_EPS2 }, 'i' } |
| 3196 | }; |
| 3197 | |
| 3198 | static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { |
| 3199 | { { 6 /* art */ }, 'i' } |
| 3200 | }; |
| 3201 | |
| 3202 | static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { |
| 3203 | { { STATE_PSEXCM }, 'i' }, |
| 3204 | { { STATE_PSRING }, 'i' }, |
| 3205 | { { STATE_EPS2 }, 'o' } |
| 3206 | }; |
| 3207 | |
| 3208 | static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { |
| 3209 | { { 6 /* art */ }, 'm' } |
| 3210 | }; |
| 3211 | |
| 3212 | static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { |
| 3213 | { { STATE_PSEXCM }, 'i' }, |
| 3214 | { { STATE_PSRING }, 'i' }, |
| 3215 | { { STATE_EPS2 }, 'm' } |
| 3216 | }; |
| 3217 | |
| 3218 | static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { |
| 3219 | { { 6 /* art */ }, 'o' } |
| 3220 | }; |
| 3221 | |
| 3222 | static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { |
| 3223 | { { STATE_PSEXCM }, 'i' }, |
| 3224 | { { STATE_PSRING }, 'i' }, |
| 3225 | { { STATE_EPS3 }, 'i' } |
| 3226 | }; |
| 3227 | |
| 3228 | static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { |
| 3229 | { { 6 /* art */ }, 'i' } |
| 3230 | }; |
| 3231 | |
| 3232 | static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { |
| 3233 | { { STATE_PSEXCM }, 'i' }, |
| 3234 | { { STATE_PSRING }, 'i' }, |
| 3235 | { { STATE_EPS3 }, 'o' } |
| 3236 | }; |
| 3237 | |
| 3238 | static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { |
| 3239 | { { 6 /* art */ }, 'm' } |
| 3240 | }; |
| 3241 | |
| 3242 | static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { |
| 3243 | { { STATE_PSEXCM }, 'i' }, |
| 3244 | { { STATE_PSRING }, 'i' }, |
| 3245 | { { STATE_EPS3 }, 'm' } |
| 3246 | }; |
| 3247 | |
| 3248 | static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { |
| 3249 | { { 6 /* art */ }, 'o' } |
| 3250 | }; |
| 3251 | |
| 3252 | static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { |
| 3253 | { { STATE_PSEXCM }, 'i' }, |
| 3254 | { { STATE_PSRING }, 'i' }, |
| 3255 | { { STATE_EPS4 }, 'i' } |
| 3256 | }; |
| 3257 | |
| 3258 | static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { |
| 3259 | { { 6 /* art */ }, 'i' } |
| 3260 | }; |
| 3261 | |
| 3262 | static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { |
| 3263 | { { STATE_PSEXCM }, 'i' }, |
| 3264 | { { STATE_PSRING }, 'i' }, |
| 3265 | { { STATE_EPS4 }, 'o' } |
| 3266 | }; |
| 3267 | |
| 3268 | static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { |
| 3269 | { { 6 /* art */ }, 'm' } |
| 3270 | }; |
| 3271 | |
| 3272 | static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { |
| 3273 | { { STATE_PSEXCM }, 'i' }, |
| 3274 | { { STATE_PSRING }, 'i' }, |
| 3275 | { { STATE_EPS4 }, 'm' } |
| 3276 | }; |
| 3277 | |
| 3278 | static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { |
| 3279 | { { 6 /* art */ }, 'o' } |
| 3280 | }; |
| 3281 | |
| 3282 | static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { |
| 3283 | { { STATE_PSEXCM }, 'i' }, |
| 3284 | { { STATE_PSRING }, 'i' }, |
| 3285 | { { STATE_EXCVADDR }, 'i' } |
| 3286 | }; |
| 3287 | |
| 3288 | static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { |
| 3289 | { { 6 /* art */ }, 'i' } |
| 3290 | }; |
| 3291 | |
| 3292 | static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { |
| 3293 | { { STATE_PSEXCM }, 'i' }, |
| 3294 | { { STATE_PSRING }, 'i' }, |
| 3295 | { { STATE_EXCVADDR }, 'o' } |
| 3296 | }; |
| 3297 | |
| 3298 | static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { |
| 3299 | { { 6 /* art */ }, 'm' } |
| 3300 | }; |
| 3301 | |
| 3302 | static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { |
| 3303 | { { STATE_PSEXCM }, 'i' }, |
| 3304 | { { STATE_PSRING }, 'i' }, |
| 3305 | { { STATE_EXCVADDR }, 'm' } |
| 3306 | }; |
| 3307 | |
| 3308 | static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { |
| 3309 | { { 6 /* art */ }, 'o' } |
| 3310 | }; |
| 3311 | |
| 3312 | static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { |
| 3313 | { { STATE_PSEXCM }, 'i' }, |
| 3314 | { { STATE_PSRING }, 'i' }, |
| 3315 | { { STATE_DEPC }, 'i' } |
| 3316 | }; |
| 3317 | |
| 3318 | static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { |
| 3319 | { { 6 /* art */ }, 'i' } |
| 3320 | }; |
| 3321 | |
| 3322 | static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { |
| 3323 | { { STATE_PSEXCM }, 'i' }, |
| 3324 | { { STATE_PSRING }, 'i' }, |
| 3325 | { { STATE_DEPC }, 'o' } |
| 3326 | }; |
| 3327 | |
| 3328 | static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { |
| 3329 | { { 6 /* art */ }, 'm' } |
| 3330 | }; |
| 3331 | |
| 3332 | static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { |
| 3333 | { { STATE_PSEXCM }, 'i' }, |
| 3334 | { { STATE_PSRING }, 'i' }, |
| 3335 | { { STATE_DEPC }, 'm' } |
| 3336 | }; |
| 3337 | |
| 3338 | static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { |
| 3339 | { { 6 /* art */ }, 'o' } |
| 3340 | }; |
| 3341 | |
| 3342 | static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { |
| 3343 | { { STATE_PSEXCM }, 'i' }, |
| 3344 | { { STATE_PSRING }, 'i' }, |
| 3345 | { { STATE_EXCCAUSE }, 'i' }, |
| 3346 | { { STATE_XTSYNC }, 'i' } |
| 3347 | }; |
| 3348 | |
| 3349 | static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { |
| 3350 | { { 6 /* art */ }, 'i' } |
| 3351 | }; |
| 3352 | |
| 3353 | static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { |
| 3354 | { { STATE_PSEXCM }, 'i' }, |
| 3355 | { { STATE_PSRING }, 'i' }, |
| 3356 | { { STATE_EXCCAUSE }, 'o' } |
| 3357 | }; |
| 3358 | |
| 3359 | static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { |
| 3360 | { { 6 /* art */ }, 'm' } |
| 3361 | }; |
| 3362 | |
| 3363 | static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { |
| 3364 | { { STATE_PSEXCM }, 'i' }, |
| 3365 | { { STATE_PSRING }, 'i' }, |
| 3366 | { { STATE_EXCCAUSE }, 'm' } |
| 3367 | }; |
| 3368 | |
| 3369 | static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { |
| 3370 | { { 6 /* art */ }, 'o' } |
| 3371 | }; |
| 3372 | |
| 3373 | static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { |
| 3374 | { { STATE_PSEXCM }, 'i' }, |
| 3375 | { { STATE_PSRING }, 'i' }, |
| 3376 | { { STATE_MISC0 }, 'i' } |
| 3377 | }; |
| 3378 | |
| 3379 | static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { |
| 3380 | { { 6 /* art */ }, 'i' } |
| 3381 | }; |
| 3382 | |
| 3383 | static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { |
| 3384 | { { STATE_PSEXCM }, 'i' }, |
| 3385 | { { STATE_PSRING }, 'i' }, |
| 3386 | { { STATE_MISC0 }, 'o' } |
| 3387 | }; |
| 3388 | |
| 3389 | static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { |
| 3390 | { { 6 /* art */ }, 'm' } |
| 3391 | }; |
| 3392 | |
| 3393 | static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { |
| 3394 | { { STATE_PSEXCM }, 'i' }, |
| 3395 | { { STATE_PSRING }, 'i' }, |
| 3396 | { { STATE_MISC0 }, 'm' } |
| 3397 | }; |
| 3398 | |
| 3399 | static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { |
| 3400 | { { 6 /* art */ }, 'o' } |
| 3401 | }; |
| 3402 | |
| 3403 | static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { |
| 3404 | { { STATE_PSEXCM }, 'i' }, |
| 3405 | { { STATE_PSRING }, 'i' }, |
| 3406 | { { STATE_MISC1 }, 'i' } |
| 3407 | }; |
| 3408 | |
| 3409 | static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { |
| 3410 | { { 6 /* art */ }, 'i' } |
| 3411 | }; |
| 3412 | |
| 3413 | static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { |
| 3414 | { { STATE_PSEXCM }, 'i' }, |
| 3415 | { { STATE_PSRING }, 'i' }, |
| 3416 | { { STATE_MISC1 }, 'o' } |
| 3417 | }; |
| 3418 | |
| 3419 | static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { |
| 3420 | { { 6 /* art */ }, 'm' } |
| 3421 | }; |
| 3422 | |
| 3423 | static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { |
| 3424 | { { STATE_PSEXCM }, 'i' }, |
| 3425 | { { STATE_PSRING }, 'i' }, |
| 3426 | { { STATE_MISC1 }, 'm' } |
| 3427 | }; |
| 3428 | |
| 3429 | static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { |
| 3430 | { { 6 /* art */ }, 'o' } |
| 3431 | }; |
| 3432 | |
| 3433 | static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = { |
| 3434 | { { STATE_PSEXCM }, 'i' }, |
| 3435 | { { STATE_PSRING }, 'i' } |
| 3436 | }; |
| 3437 | |
| 3438 | static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { |
| 3439 | { { 40 /* s */ }, 'i' } |
| 3440 | }; |
| 3441 | |
| 3442 | static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { |
| 3443 | { { STATE_PSWOE }, 'o' }, |
| 3444 | { { STATE_PSCALLINC }, 'o' }, |
| 3445 | { { STATE_PSOWB }, 'o' }, |
| 3446 | { { STATE_PSRING }, 'm' }, |
| 3447 | { { STATE_PSUM }, 'o' }, |
| 3448 | { { STATE_PSEXCM }, 'm' }, |
| 3449 | { { STATE_PSINTLEVEL }, 'o' }, |
| 3450 | { { STATE_EPC1 }, 'i' }, |
| 3451 | { { STATE_EPC2 }, 'i' }, |
| 3452 | { { STATE_EPC3 }, 'i' }, |
| 3453 | { { STATE_EPC4 }, 'i' }, |
| 3454 | { { STATE_EPS2 }, 'i' }, |
| 3455 | { { STATE_EPS3 }, 'i' }, |
| 3456 | { { STATE_EPS4 }, 'i' }, |
| 3457 | { { STATE_InOCDMode }, 'm' } |
| 3458 | }; |
| 3459 | |
| 3460 | static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { |
| 3461 | { { 40 /* s */ }, 'i' } |
| 3462 | }; |
| 3463 | |
| 3464 | static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { |
| 3465 | { { STATE_PSEXCM }, 'i' }, |
| 3466 | { { STATE_PSRING }, 'i' }, |
| 3467 | { { STATE_PSINTLEVEL }, 'o' } |
| 3468 | }; |
| 3469 | |
| 3470 | static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { |
| 3471 | { { 6 /* art */ }, 'o' } |
| 3472 | }; |
| 3473 | |
| 3474 | static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { |
| 3475 | { { STATE_PSEXCM }, 'i' }, |
| 3476 | { { STATE_PSRING }, 'i' }, |
| 3477 | { { STATE_INTERRUPT }, 'i' } |
| 3478 | }; |
| 3479 | |
| 3480 | static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { |
| 3481 | { { 6 /* art */ }, 'i' } |
| 3482 | }; |
| 3483 | |
| 3484 | static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { |
| 3485 | { { STATE_PSEXCM }, 'i' }, |
| 3486 | { { STATE_PSRING }, 'i' }, |
| 3487 | { { STATE_XTSYNC }, 'o' }, |
| 3488 | { { STATE_INTERRUPT }, 'm' } |
| 3489 | }; |
| 3490 | |
| 3491 | static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { |
| 3492 | { { 6 /* art */ }, 'i' } |
| 3493 | }; |
| 3494 | |
| 3495 | static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { |
| 3496 | { { STATE_PSEXCM }, 'i' }, |
| 3497 | { { STATE_PSRING }, 'i' }, |
| 3498 | { { STATE_XTSYNC }, 'o' }, |
| 3499 | { { STATE_INTERRUPT }, 'm' } |
| 3500 | }; |
| 3501 | |
| 3502 | static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { |
| 3503 | { { 6 /* art */ }, 'o' } |
| 3504 | }; |
| 3505 | |
| 3506 | static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { |
| 3507 | { { STATE_PSEXCM }, 'i' }, |
| 3508 | { { STATE_PSRING }, 'i' }, |
| 3509 | { { STATE_INTENABLE }, 'i' } |
| 3510 | }; |
| 3511 | |
| 3512 | static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { |
| 3513 | { { 6 /* art */ }, 'i' } |
| 3514 | }; |
| 3515 | |
| 3516 | static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { |
| 3517 | { { STATE_PSEXCM }, 'i' }, |
| 3518 | { { STATE_PSRING }, 'i' }, |
| 3519 | { { STATE_INTENABLE }, 'o' } |
| 3520 | }; |
| 3521 | |
| 3522 | static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { |
| 3523 | { { 6 /* art */ }, 'm' } |
| 3524 | }; |
| 3525 | |
| 3526 | static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { |
| 3527 | { { STATE_PSEXCM }, 'i' }, |
| 3528 | { { STATE_PSRING }, 'i' }, |
| 3529 | { { STATE_INTENABLE }, 'm' } |
| 3530 | }; |
| 3531 | |
| 3532 | static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { |
| 3533 | { { 34 /* imms */ }, 'i' }, |
| 3534 | { { 33 /* immt */ }, 'i' } |
| 3535 | }; |
| 3536 | |
| 3537 | static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { |
| 3538 | { { STATE_PSEXCM }, 'i' }, |
| 3539 | { { STATE_PSINTLEVEL }, 'i' } |
| 3540 | }; |
| 3541 | |
| 3542 | static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { |
| 3543 | { { 34 /* imms */ }, 'i' } |
| 3544 | }; |
| 3545 | |
| 3546 | static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { |
| 3547 | { { STATE_PSEXCM }, 'i' }, |
| 3548 | { { STATE_PSINTLEVEL }, 'i' } |
| 3549 | }; |
| 3550 | |
| 3551 | static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { |
| 3552 | { { 6 /* art */ }, 'o' } |
| 3553 | }; |
| 3554 | |
| 3555 | static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { |
| 3556 | { { STATE_PSEXCM }, 'i' }, |
| 3557 | { { STATE_PSRING }, 'i' }, |
| 3558 | { { STATE_DBREAKA0 }, 'i' } |
| 3559 | }; |
| 3560 | |
| 3561 | static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { |
| 3562 | { { 6 /* art */ }, 'i' } |
| 3563 | }; |
| 3564 | |
| 3565 | static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { |
| 3566 | { { STATE_PSEXCM }, 'i' }, |
| 3567 | { { STATE_PSRING }, 'i' }, |
| 3568 | { { STATE_DBREAKA0 }, 'o' }, |
| 3569 | { { STATE_XTSYNC }, 'o' } |
| 3570 | }; |
| 3571 | |
| 3572 | static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { |
| 3573 | { { 6 /* art */ }, 'm' } |
| 3574 | }; |
| 3575 | |
| 3576 | static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { |
| 3577 | { { STATE_PSEXCM }, 'i' }, |
| 3578 | { { STATE_PSRING }, 'i' }, |
| 3579 | { { STATE_DBREAKA0 }, 'm' }, |
| 3580 | { { STATE_XTSYNC }, 'o' } |
| 3581 | }; |
| 3582 | |
| 3583 | static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { |
| 3584 | { { 6 /* art */ }, 'o' } |
| 3585 | }; |
| 3586 | |
| 3587 | static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { |
| 3588 | { { STATE_PSEXCM }, 'i' }, |
| 3589 | { { STATE_PSRING }, 'i' }, |
| 3590 | { { STATE_DBREAKC0 }, 'i' } |
| 3591 | }; |
| 3592 | |
| 3593 | static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { |
| 3594 | { { 6 /* art */ }, 'i' } |
| 3595 | }; |
| 3596 | |
| 3597 | static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { |
| 3598 | { { STATE_PSEXCM }, 'i' }, |
| 3599 | { { STATE_PSRING }, 'i' }, |
| 3600 | { { STATE_DBREAKC0 }, 'o' }, |
| 3601 | { { STATE_XTSYNC }, 'o' } |
| 3602 | }; |
| 3603 | |
| 3604 | static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { |
| 3605 | { { 6 /* art */ }, 'm' } |
| 3606 | }; |
| 3607 | |
| 3608 | static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { |
| 3609 | { { STATE_PSEXCM }, 'i' }, |
| 3610 | { { STATE_PSRING }, 'i' }, |
| 3611 | { { STATE_DBREAKC0 }, 'm' }, |
| 3612 | { { STATE_XTSYNC }, 'o' } |
| 3613 | }; |
| 3614 | |
| 3615 | static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { |
| 3616 | { { 6 /* art */ }, 'o' } |
| 3617 | }; |
| 3618 | |
| 3619 | static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { |
| 3620 | { { STATE_PSEXCM }, 'i' }, |
| 3621 | { { STATE_PSRING }, 'i' }, |
| 3622 | { { STATE_DBREAKA1 }, 'i' } |
| 3623 | }; |
| 3624 | |
| 3625 | static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { |
| 3626 | { { 6 /* art */ }, 'i' } |
| 3627 | }; |
| 3628 | |
| 3629 | static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { |
| 3630 | { { STATE_PSEXCM }, 'i' }, |
| 3631 | { { STATE_PSRING }, 'i' }, |
| 3632 | { { STATE_DBREAKA1 }, 'o' }, |
| 3633 | { { STATE_XTSYNC }, 'o' } |
| 3634 | }; |
| 3635 | |
| 3636 | static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { |
| 3637 | { { 6 /* art */ }, 'm' } |
| 3638 | }; |
| 3639 | |
| 3640 | static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { |
| 3641 | { { STATE_PSEXCM }, 'i' }, |
| 3642 | { { STATE_PSRING }, 'i' }, |
| 3643 | { { STATE_DBREAKA1 }, 'm' }, |
| 3644 | { { STATE_XTSYNC }, 'o' } |
| 3645 | }; |
| 3646 | |
| 3647 | static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { |
| 3648 | { { 6 /* art */ }, 'o' } |
| 3649 | }; |
| 3650 | |
| 3651 | static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { |
| 3652 | { { STATE_PSEXCM }, 'i' }, |
| 3653 | { { STATE_PSRING }, 'i' }, |
| 3654 | { { STATE_DBREAKC1 }, 'i' } |
| 3655 | }; |
| 3656 | |
| 3657 | static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { |
| 3658 | { { 6 /* art */ }, 'i' } |
| 3659 | }; |
| 3660 | |
| 3661 | static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { |
| 3662 | { { STATE_PSEXCM }, 'i' }, |
| 3663 | { { STATE_PSRING }, 'i' }, |
| 3664 | { { STATE_DBREAKC1 }, 'o' }, |
| 3665 | { { STATE_XTSYNC }, 'o' } |
| 3666 | }; |
| 3667 | |
| 3668 | static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { |
| 3669 | { { 6 /* art */ }, 'm' } |
| 3670 | }; |
| 3671 | |
| 3672 | static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { |
| 3673 | { { STATE_PSEXCM }, 'i' }, |
| 3674 | { { STATE_PSRING }, 'i' }, |
| 3675 | { { STATE_DBREAKC1 }, 'm' }, |
| 3676 | { { STATE_XTSYNC }, 'o' } |
| 3677 | }; |
| 3678 | |
| 3679 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { |
| 3680 | { { 6 /* art */ }, 'o' } |
| 3681 | }; |
| 3682 | |
| 3683 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { |
| 3684 | { { STATE_PSEXCM }, 'i' }, |
| 3685 | { { STATE_PSRING }, 'i' }, |
| 3686 | { { STATE_IBREAKA0 }, 'i' } |
| 3687 | }; |
| 3688 | |
| 3689 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { |
| 3690 | { { 6 /* art */ }, 'i' } |
| 3691 | }; |
| 3692 | |
| 3693 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { |
| 3694 | { { STATE_PSEXCM }, 'i' }, |
| 3695 | { { STATE_PSRING }, 'i' }, |
| 3696 | { { STATE_IBREAKA0 }, 'o' } |
| 3697 | }; |
| 3698 | |
| 3699 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { |
| 3700 | { { 6 /* art */ }, 'm' } |
| 3701 | }; |
| 3702 | |
| 3703 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { |
| 3704 | { { STATE_PSEXCM }, 'i' }, |
| 3705 | { { STATE_PSRING }, 'i' }, |
| 3706 | { { STATE_IBREAKA0 }, 'm' } |
| 3707 | }; |
| 3708 | |
| 3709 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { |
| 3710 | { { 6 /* art */ }, 'o' } |
| 3711 | }; |
| 3712 | |
| 3713 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { |
| 3714 | { { STATE_PSEXCM }, 'i' }, |
| 3715 | { { STATE_PSRING }, 'i' }, |
| 3716 | { { STATE_IBREAKA1 }, 'i' } |
| 3717 | }; |
| 3718 | |
| 3719 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { |
| 3720 | { { 6 /* art */ }, 'i' } |
| 3721 | }; |
| 3722 | |
| 3723 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { |
| 3724 | { { STATE_PSEXCM }, 'i' }, |
| 3725 | { { STATE_PSRING }, 'i' }, |
| 3726 | { { STATE_IBREAKA1 }, 'o' } |
| 3727 | }; |
| 3728 | |
| 3729 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { |
| 3730 | { { 6 /* art */ }, 'm' } |
| 3731 | }; |
| 3732 | |
| 3733 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { |
| 3734 | { { STATE_PSEXCM }, 'i' }, |
| 3735 | { { STATE_PSRING }, 'i' }, |
| 3736 | { { STATE_IBREAKA1 }, 'm' } |
| 3737 | }; |
| 3738 | |
| 3739 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { |
| 3740 | { { 6 /* art */ }, 'o' } |
| 3741 | }; |
| 3742 | |
| 3743 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { |
| 3744 | { { STATE_PSEXCM }, 'i' }, |
| 3745 | { { STATE_PSRING }, 'i' }, |
| 3746 | { { STATE_IBREAKENABLE }, 'i' } |
| 3747 | }; |
| 3748 | |
| 3749 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { |
| 3750 | { { 6 /* art */ }, 'i' } |
| 3751 | }; |
| 3752 | |
| 3753 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { |
| 3754 | { { STATE_PSEXCM }, 'i' }, |
| 3755 | { { STATE_PSRING }, 'i' }, |
| 3756 | { { STATE_IBREAKENABLE }, 'o' } |
| 3757 | }; |
| 3758 | |
| 3759 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { |
| 3760 | { { 6 /* art */ }, 'm' } |
| 3761 | }; |
| 3762 | |
| 3763 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { |
| 3764 | { { STATE_PSEXCM }, 'i' }, |
| 3765 | { { STATE_PSRING }, 'i' }, |
| 3766 | { { STATE_IBREAKENABLE }, 'm' } |
| 3767 | }; |
| 3768 | |
| 3769 | static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { |
| 3770 | { { 6 /* art */ }, 'o' } |
| 3771 | }; |
| 3772 | |
| 3773 | static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { |
| 3774 | { { STATE_PSEXCM }, 'i' }, |
| 3775 | { { STATE_PSRING }, 'i' }, |
| 3776 | { { STATE_DEBUGCAUSE }, 'i' }, |
| 3777 | { { STATE_DBNUM }, 'i' } |
| 3778 | }; |
| 3779 | |
| 3780 | static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { |
| 3781 | { { 6 /* art */ }, 'i' } |
| 3782 | }; |
| 3783 | |
| 3784 | static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { |
| 3785 | { { STATE_PSEXCM }, 'i' }, |
| 3786 | { { STATE_PSRING }, 'i' }, |
| 3787 | { { STATE_DEBUGCAUSE }, 'o' }, |
| 3788 | { { STATE_DBNUM }, 'o' } |
| 3789 | }; |
| 3790 | |
| 3791 | static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { |
| 3792 | { { 6 /* art */ }, 'm' } |
| 3793 | }; |
| 3794 | |
| 3795 | static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { |
| 3796 | { { STATE_PSEXCM }, 'i' }, |
| 3797 | { { STATE_PSRING }, 'i' }, |
| 3798 | { { STATE_DEBUGCAUSE }, 'm' }, |
| 3799 | { { STATE_DBNUM }, 'm' } |
| 3800 | }; |
| 3801 | |
| 3802 | static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { |
| 3803 | { { 6 /* art */ }, 'o' } |
| 3804 | }; |
| 3805 | |
| 3806 | static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { |
| 3807 | { { STATE_PSEXCM }, 'i' }, |
| 3808 | { { STATE_PSRING }, 'i' }, |
| 3809 | { { STATE_ICOUNT }, 'i' } |
| 3810 | }; |
| 3811 | |
| 3812 | static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { |
| 3813 | { { 6 /* art */ }, 'i' } |
| 3814 | }; |
| 3815 | |
| 3816 | static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { |
| 3817 | { { STATE_PSEXCM }, 'i' }, |
| 3818 | { { STATE_PSRING }, 'i' }, |
| 3819 | { { STATE_XTSYNC }, 'o' }, |
| 3820 | { { STATE_ICOUNT }, 'o' } |
| 3821 | }; |
| 3822 | |
| 3823 | static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { |
| 3824 | { { 6 /* art */ }, 'm' } |
| 3825 | }; |
| 3826 | |
| 3827 | static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { |
| 3828 | { { STATE_PSEXCM }, 'i' }, |
| 3829 | { { STATE_PSRING }, 'i' }, |
| 3830 | { { STATE_XTSYNC }, 'o' }, |
| 3831 | { { STATE_ICOUNT }, 'm' } |
| 3832 | }; |
| 3833 | |
| 3834 | static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { |
| 3835 | { { 6 /* art */ }, 'o' } |
| 3836 | }; |
| 3837 | |
| 3838 | static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { |
| 3839 | { { STATE_PSEXCM }, 'i' }, |
| 3840 | { { STATE_PSRING }, 'i' }, |
| 3841 | { { STATE_ICOUNTLEVEL }, 'i' } |
| 3842 | }; |
| 3843 | |
| 3844 | static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { |
| 3845 | { { 6 /* art */ }, 'i' } |
| 3846 | }; |
| 3847 | |
| 3848 | static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { |
| 3849 | { { STATE_PSEXCM }, 'i' }, |
| 3850 | { { STATE_PSRING }, 'i' }, |
| 3851 | { { STATE_ICOUNTLEVEL }, 'o' } |
| 3852 | }; |
| 3853 | |
| 3854 | static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { |
| 3855 | { { 6 /* art */ }, 'm' } |
| 3856 | }; |
| 3857 | |
| 3858 | static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { |
| 3859 | { { STATE_PSEXCM }, 'i' }, |
| 3860 | { { STATE_PSRING }, 'i' }, |
| 3861 | { { STATE_ICOUNTLEVEL }, 'm' } |
| 3862 | }; |
| 3863 | |
| 3864 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { |
| 3865 | { { 6 /* art */ }, 'o' } |
| 3866 | }; |
| 3867 | |
| 3868 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { |
| 3869 | { { STATE_PSEXCM }, 'i' }, |
| 3870 | { { STATE_PSRING }, 'i' }, |
| 3871 | { { STATE_DDR }, 'i' } |
| 3872 | }; |
| 3873 | |
| 3874 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { |
| 3875 | { { 6 /* art */ }, 'i' } |
| 3876 | }; |
| 3877 | |
| 3878 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { |
| 3879 | { { STATE_PSEXCM }, 'i' }, |
| 3880 | { { STATE_PSRING }, 'i' }, |
| 3881 | { { STATE_XTSYNC }, 'o' }, |
| 3882 | { { STATE_DDR }, 'o' } |
| 3883 | }; |
| 3884 | |
| 3885 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { |
| 3886 | { { 6 /* art */ }, 'm' } |
| 3887 | }; |
| 3888 | |
| 3889 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { |
| 3890 | { { STATE_PSEXCM }, 'i' }, |
| 3891 | { { STATE_PSRING }, 'i' }, |
| 3892 | { { STATE_XTSYNC }, 'o' }, |
| 3893 | { { STATE_DDR }, 'm' } |
| 3894 | }; |
| 3895 | |
| 3896 | static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { |
| 3897 | { { STATE_InOCDMode }, 'm' }, |
| 3898 | { { STATE_EPC4 }, 'i' }, |
| 3899 | { { STATE_PSWOE }, 'o' }, |
| 3900 | { { STATE_PSCALLINC }, 'o' }, |
| 3901 | { { STATE_PSOWB }, 'o' }, |
| 3902 | { { STATE_PSRING }, 'o' }, |
| 3903 | { { STATE_PSUM }, 'o' }, |
| 3904 | { { STATE_PSEXCM }, 'o' }, |
| 3905 | { { STATE_PSINTLEVEL }, 'o' }, |
| 3906 | { { STATE_EPS4 }, 'i' } |
| 3907 | }; |
| 3908 | |
| 3909 | static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { |
| 3910 | { { STATE_InOCDMode }, 'm' } |
| 3911 | }; |
| 3912 | |
| 3913 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { |
| 3914 | { { 6 /* art */ }, 'o' } |
| 3915 | }; |
| 3916 | |
| 3917 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { |
| 3918 | { { STATE_PSEXCM }, 'i' }, |
| 3919 | { { STATE_PSRING }, 'i' }, |
| 3920 | { { STATE_CCOUNT }, 'i' } |
| 3921 | }; |
| 3922 | |
| 3923 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { |
| 3924 | { { 6 /* art */ }, 'i' } |
| 3925 | }; |
| 3926 | |
| 3927 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { |
| 3928 | { { STATE_PSEXCM }, 'i' }, |
| 3929 | { { STATE_PSRING }, 'i' }, |
| 3930 | { { STATE_XTSYNC }, 'o' }, |
| 3931 | { { STATE_CCOUNT }, 'o' } |
| 3932 | }; |
| 3933 | |
| 3934 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { |
| 3935 | { { 6 /* art */ }, 'm' } |
| 3936 | }; |
| 3937 | |
| 3938 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { |
| 3939 | { { STATE_PSEXCM }, 'i' }, |
| 3940 | { { STATE_PSRING }, 'i' }, |
| 3941 | { { STATE_XTSYNC }, 'o' }, |
| 3942 | { { STATE_CCOUNT }, 'm' } |
| 3943 | }; |
| 3944 | |
| 3945 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { |
| 3946 | { { 6 /* art */ }, 'o' } |
| 3947 | }; |
| 3948 | |
| 3949 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { |
| 3950 | { { STATE_PSEXCM }, 'i' }, |
| 3951 | { { STATE_PSRING }, 'i' }, |
| 3952 | { { STATE_CCOMPARE0 }, 'i' } |
| 3953 | }; |
| 3954 | |
| 3955 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { |
| 3956 | { { 6 /* art */ }, 'i' } |
| 3957 | }; |
| 3958 | |
| 3959 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { |
| 3960 | { { STATE_PSEXCM }, 'i' }, |
| 3961 | { { STATE_PSRING }, 'i' }, |
| 3962 | { { STATE_CCOMPARE0 }, 'o' }, |
| 3963 | { { STATE_INTERRUPT }, 'm' } |
| 3964 | }; |
| 3965 | |
| 3966 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { |
| 3967 | { { 6 /* art */ }, 'm' } |
| 3968 | }; |
| 3969 | |
| 3970 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { |
| 3971 | { { STATE_PSEXCM }, 'i' }, |
| 3972 | { { STATE_PSRING }, 'i' }, |
| 3973 | { { STATE_CCOMPARE0 }, 'm' }, |
| 3974 | { { STATE_INTERRUPT }, 'm' } |
| 3975 | }; |
| 3976 | |
| 3977 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { |
| 3978 | { { 6 /* art */ }, 'o' } |
| 3979 | }; |
| 3980 | |
| 3981 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { |
| 3982 | { { STATE_PSEXCM }, 'i' }, |
| 3983 | { { STATE_PSRING }, 'i' }, |
| 3984 | { { STATE_CCOMPARE1 }, 'i' } |
| 3985 | }; |
| 3986 | |
| 3987 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { |
| 3988 | { { 6 /* art */ }, 'i' } |
| 3989 | }; |
| 3990 | |
| 3991 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { |
| 3992 | { { STATE_PSEXCM }, 'i' }, |
| 3993 | { { STATE_PSRING }, 'i' }, |
| 3994 | { { STATE_CCOMPARE1 }, 'o' }, |
| 3995 | { { STATE_INTERRUPT }, 'm' } |
| 3996 | }; |
| 3997 | |
| 3998 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { |
| 3999 | { { 6 /* art */ }, 'm' } |
| 4000 | }; |
| 4001 | |
| 4002 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { |
| 4003 | { { STATE_PSEXCM }, 'i' }, |
| 4004 | { { STATE_PSRING }, 'i' }, |
| 4005 | { { STATE_CCOMPARE1 }, 'm' }, |
| 4006 | { { STATE_INTERRUPT }, 'm' } |
| 4007 | }; |
| 4008 | |
| 4009 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = { |
| 4010 | { { 6 /* art */ }, 'o' } |
| 4011 | }; |
| 4012 | |
| 4013 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = { |
| 4014 | { { STATE_PSEXCM }, 'i' }, |
| 4015 | { { STATE_PSRING }, 'i' }, |
| 4016 | { { STATE_CCOMPARE2 }, 'i' } |
| 4017 | }; |
| 4018 | |
| 4019 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = { |
| 4020 | { { 6 /* art */ }, 'i' } |
| 4021 | }; |
| 4022 | |
| 4023 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = { |
| 4024 | { { STATE_PSEXCM }, 'i' }, |
| 4025 | { { STATE_PSRING }, 'i' }, |
| 4026 | { { STATE_CCOMPARE2 }, 'o' }, |
| 4027 | { { STATE_INTERRUPT }, 'm' } |
| 4028 | }; |
| 4029 | |
| 4030 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = { |
| 4031 | { { 6 /* art */ }, 'm' } |
| 4032 | }; |
| 4033 | |
| 4034 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = { |
| 4035 | { { STATE_PSEXCM }, 'i' }, |
| 4036 | { { STATE_PSRING }, 'i' }, |
| 4037 | { { STATE_CCOMPARE2 }, 'm' }, |
| 4038 | { { STATE_INTERRUPT }, 'm' } |
| 4039 | }; |
| 4040 | |
| 4041 | static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { |
| 4042 | { { 4 /* ars */ }, 'i' }, |
| 4043 | { { 21 /* uimm8x4 */ }, 'i' } |
| 4044 | }; |
| 4045 | |
| 4046 | static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { |
| 4047 | { { 4 /* ars */ }, 'i' }, |
| 4048 | { { 21 /* uimm8x4 */ }, 'i' } |
| 4049 | }; |
| 4050 | |
| 4051 | static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = { |
| 4052 | { { STATE_PSEXCM }, 'i' }, |
| 4053 | { { STATE_PSRING }, 'i' } |
| 4054 | }; |
| 4055 | |
| 4056 | static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { |
| 4057 | { { 6 /* art */ }, 'o' }, |
| 4058 | { { 4 /* ars */ }, 'i' } |
| 4059 | }; |
| 4060 | |
| 4061 | static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = { |
| 4062 | { { STATE_PSEXCM }, 'i' }, |
| 4063 | { { STATE_PSRING }, 'i' } |
| 4064 | }; |
| 4065 | |
| 4066 | static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { |
| 4067 | { { 6 /* art */ }, 'i' }, |
| 4068 | { { 4 /* ars */ }, 'i' } |
| 4069 | }; |
| 4070 | |
| 4071 | static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = { |
| 4072 | { { STATE_PSEXCM }, 'i' }, |
| 4073 | { { STATE_PSRING }, 'i' } |
| 4074 | }; |
| 4075 | |
| 4076 | static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { |
| 4077 | { { 4 /* ars */ }, 'i' }, |
| 4078 | { { 21 /* uimm8x4 */ }, 'i' } |
| 4079 | }; |
| 4080 | |
| 4081 | static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = { |
| 4082 | { { 4 /* ars */ }, 'i' }, |
| 4083 | { { 22 /* uimm4x16 */ }, 'i' } |
| 4084 | }; |
| 4085 | |
| 4086 | static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = { |
| 4087 | { { STATE_PSEXCM }, 'i' }, |
| 4088 | { { STATE_PSRING }, 'i' } |
| 4089 | }; |
| 4090 | |
| 4091 | static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { |
| 4092 | { { 4 /* ars */ }, 'i' }, |
| 4093 | { { 21 /* uimm8x4 */ }, 'i' } |
| 4094 | }; |
| 4095 | |
| 4096 | static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = { |
| 4097 | { { STATE_PSEXCM }, 'i' }, |
| 4098 | { { STATE_PSRING }, 'i' } |
| 4099 | }; |
| 4100 | |
| 4101 | static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { |
| 4102 | { { 4 /* ars */ }, 'i' }, |
| 4103 | { { 21 /* uimm8x4 */ }, 'i' } |
| 4104 | }; |
| 4105 | |
| 4106 | static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = { |
| 4107 | { { 6 /* art */ }, 'i' }, |
| 4108 | { { 4 /* ars */ }, 'i' } |
| 4109 | }; |
| 4110 | |
| 4111 | static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = { |
| 4112 | { { STATE_PSEXCM }, 'i' }, |
| 4113 | { { STATE_PSRING }, 'i' } |
| 4114 | }; |
| 4115 | |
| 4116 | static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { |
| 4117 | { { 6 /* art */ }, 'o' }, |
| 4118 | { { 4 /* ars */ }, 'i' } |
| 4119 | }; |
| 4120 | |
| 4121 | static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = { |
| 4122 | { { STATE_PSEXCM }, 'i' }, |
| 4123 | { { STATE_PSRING }, 'i' } |
| 4124 | }; |
| 4125 | |
| 4126 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = { |
| 4127 | { { 6 /* art */ }, 'i' } |
| 4128 | }; |
| 4129 | |
| 4130 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = { |
| 4131 | { { STATE_PSEXCM }, 'i' }, |
| 4132 | { { STATE_PSRING }, 'i' }, |
| 4133 | { { STATE_PTBASE }, 'o' }, |
| 4134 | { { STATE_XTSYNC }, 'o' } |
| 4135 | }; |
| 4136 | |
| 4137 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = { |
| 4138 | { { 6 /* art */ }, 'o' } |
| 4139 | }; |
| 4140 | |
| 4141 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = { |
| 4142 | { { STATE_PSEXCM }, 'i' }, |
| 4143 | { { STATE_PSRING }, 'i' }, |
| 4144 | { { STATE_PTBASE }, 'i' }, |
| 4145 | { { STATE_EXCVADDR }, 'i' } |
| 4146 | }; |
| 4147 | |
| 4148 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = { |
| 4149 | { { 6 /* art */ }, 'm' } |
| 4150 | }; |
| 4151 | |
| 4152 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = { |
| 4153 | { { STATE_PSEXCM }, 'i' }, |
| 4154 | { { STATE_PSRING }, 'i' }, |
| 4155 | { { STATE_PTBASE }, 'm' }, |
| 4156 | { { STATE_EXCVADDR }, 'i' }, |
| 4157 | { { STATE_XTSYNC }, 'o' } |
| 4158 | }; |
| 4159 | |
| 4160 | static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = { |
| 4161 | { { 6 /* art */ }, 'o' } |
| 4162 | }; |
| 4163 | |
| 4164 | static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = { |
| 4165 | { { STATE_PSEXCM }, 'i' }, |
| 4166 | { { STATE_PSRING }, 'i' }, |
| 4167 | { { STATE_ASID3 }, 'i' }, |
| 4168 | { { STATE_ASID2 }, 'i' }, |
| 4169 | { { STATE_ASID1 }, 'i' } |
| 4170 | }; |
| 4171 | |
| 4172 | static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = { |
| 4173 | { { 6 /* art */ }, 'i' } |
| 4174 | }; |
| 4175 | |
| 4176 | static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = { |
| 4177 | { { STATE_XTSYNC }, 'o' }, |
| 4178 | { { STATE_PSEXCM }, 'i' }, |
| 4179 | { { STATE_PSRING }, 'i' }, |
| 4180 | { { STATE_ASID3 }, 'o' }, |
| 4181 | { { STATE_ASID2 }, 'o' }, |
| 4182 | { { STATE_ASID1 }, 'o' } |
| 4183 | }; |
| 4184 | |
| 4185 | static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = { |
| 4186 | { { 6 /* art */ }, 'm' } |
| 4187 | }; |
| 4188 | |
| 4189 | static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = { |
| 4190 | { { STATE_XTSYNC }, 'o' }, |
| 4191 | { { STATE_PSEXCM }, 'i' }, |
| 4192 | { { STATE_PSRING }, 'i' }, |
| 4193 | { { STATE_ASID3 }, 'm' }, |
| 4194 | { { STATE_ASID2 }, 'm' }, |
| 4195 | { { STATE_ASID1 }, 'm' } |
| 4196 | }; |
| 4197 | |
| 4198 | static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = { |
| 4199 | { { 6 /* art */ }, 'o' } |
| 4200 | }; |
| 4201 | |
| 4202 | static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = { |
| 4203 | { { STATE_PSEXCM }, 'i' }, |
| 4204 | { { STATE_PSRING }, 'i' }, |
| 4205 | { { STATE_INSTPGSZID4 }, 'i' } |
| 4206 | }; |
| 4207 | |
| 4208 | static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = { |
| 4209 | { { 6 /* art */ }, 'i' } |
| 4210 | }; |
| 4211 | |
| 4212 | static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = { |
| 4213 | { { STATE_XTSYNC }, 'o' }, |
| 4214 | { { STATE_PSEXCM }, 'i' }, |
| 4215 | { { STATE_PSRING }, 'i' }, |
| 4216 | { { STATE_INSTPGSZID4 }, 'o' } |
| 4217 | }; |
| 4218 | |
| 4219 | static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = { |
| 4220 | { { 6 /* art */ }, 'm' } |
| 4221 | }; |
| 4222 | |
| 4223 | static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = { |
| 4224 | { { STATE_XTSYNC }, 'o' }, |
| 4225 | { { STATE_PSEXCM }, 'i' }, |
| 4226 | { { STATE_PSRING }, 'i' }, |
| 4227 | { { STATE_INSTPGSZID4 }, 'm' } |
| 4228 | }; |
| 4229 | |
| 4230 | static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = { |
| 4231 | { { 6 /* art */ }, 'o' } |
| 4232 | }; |
| 4233 | |
| 4234 | static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = { |
| 4235 | { { STATE_PSEXCM }, 'i' }, |
| 4236 | { { STATE_PSRING }, 'i' }, |
| 4237 | { { STATE_DATAPGSZID4 }, 'i' } |
| 4238 | }; |
| 4239 | |
| 4240 | static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = { |
| 4241 | { { 6 /* art */ }, 'i' } |
| 4242 | }; |
| 4243 | |
| 4244 | static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = { |
| 4245 | { { STATE_XTSYNC }, 'o' }, |
| 4246 | { { STATE_PSEXCM }, 'i' }, |
| 4247 | { { STATE_PSRING }, 'i' }, |
| 4248 | { { STATE_DATAPGSZID4 }, 'o' } |
| 4249 | }; |
| 4250 | |
| 4251 | static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = { |
| 4252 | { { 6 /* art */ }, 'm' } |
| 4253 | }; |
| 4254 | |
| 4255 | static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = { |
| 4256 | { { STATE_XTSYNC }, 'o' }, |
| 4257 | { { STATE_PSEXCM }, 'i' }, |
| 4258 | { { STATE_PSRING }, 'i' }, |
| 4259 | { { STATE_DATAPGSZID4 }, 'm' } |
| 4260 | }; |
| 4261 | |
| 4262 | static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { |
| 4263 | { { 4 /* ars */ }, 'i' } |
| 4264 | }; |
| 4265 | |
| 4266 | static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { |
| 4267 | { { STATE_PSEXCM }, 'i' }, |
| 4268 | { { STATE_PSRING }, 'i' }, |
| 4269 | { { STATE_XTSYNC }, 'o' } |
| 4270 | }; |
| 4271 | |
| 4272 | static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { |
| 4273 | { { 6 /* art */ }, 'o' }, |
| 4274 | { { 4 /* ars */ }, 'i' } |
| 4275 | }; |
| 4276 | |
| 4277 | static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = { |
| 4278 | { { STATE_PSEXCM }, 'i' }, |
| 4279 | { { STATE_PSRING }, 'i' } |
| 4280 | }; |
| 4281 | |
| 4282 | static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { |
| 4283 | { { 6 /* art */ }, 'i' }, |
| 4284 | { { 4 /* ars */ }, 'i' } |
| 4285 | }; |
| 4286 | |
| 4287 | static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { |
| 4288 | { { STATE_PSEXCM }, 'i' }, |
| 4289 | { { STATE_PSRING }, 'i' }, |
| 4290 | { { STATE_XTSYNC }, 'o' } |
| 4291 | }; |
| 4292 | |
| 4293 | static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { |
| 4294 | { { 4 /* ars */ }, 'i' } |
| 4295 | }; |
| 4296 | |
| 4297 | static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = { |
| 4298 | { { STATE_PSEXCM }, 'i' }, |
| 4299 | { { STATE_PSRING }, 'i' } |
| 4300 | }; |
| 4301 | |
| 4302 | static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { |
| 4303 | { { 6 /* art */ }, 'o' }, |
| 4304 | { { 4 /* ars */ }, 'i' } |
| 4305 | }; |
| 4306 | |
| 4307 | static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = { |
| 4308 | { { STATE_PSEXCM }, 'i' }, |
| 4309 | { { STATE_PSRING }, 'i' } |
| 4310 | }; |
| 4311 | |
| 4312 | static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { |
| 4313 | { { 6 /* art */ }, 'i' }, |
| 4314 | { { 4 /* ars */ }, 'i' } |
| 4315 | }; |
| 4316 | |
| 4317 | static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = { |
| 4318 | { { STATE_PSEXCM }, 'i' }, |
| 4319 | { { STATE_PSRING }, 'i' } |
| 4320 | }; |
| 4321 | |
| 4322 | static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = { |
| 4323 | { { STATE_PTBASE }, 'i' }, |
| 4324 | { { STATE_EXCVADDR }, 'i' } |
| 4325 | }; |
| 4326 | |
| 4327 | static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = { |
| 4328 | { { STATE_EXCVADDR }, 'i' } |
| 4329 | }; |
| 4330 | |
| 4331 | static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = { |
| 4332 | { { STATE_EXCVADDR }, 'i' } |
| 4333 | }; |
| 4334 | |
| 4335 | static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { |
| 4336 | { { 6 /* art */ }, 'o' }, |
| 4337 | { { 4 /* ars */ }, 'i' } |
| 4338 | }; |
| 4339 | |
| 4340 | static xtensa_iclass_internal iclasses[] = { |
| 4341 | { 0, 0 /* xt_iclass_excw */, |
| 4342 | 0, 0, 0, 0 }, |
| 4343 | { 0, 0 /* xt_iclass_rfe */, |
| 4344 | 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, |
| 4345 | { 0, 0 /* xt_iclass_rfde */, |
| 4346 | 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, |
| 4347 | { 0, 0 /* xt_iclass_syscall */, |
| 4348 | 0, 0, 0, 0 }, |
| 4349 | { 0, 0 /* xt_iclass_simcall */, |
| 4350 | 0, 0, 0, 0 }, |
| 4351 | { 2, Iclass_xt_iclass_call12_args, |
| 4352 | 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, |
| 4353 | { 2, Iclass_xt_iclass_call8_args, |
| 4354 | 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, |
| 4355 | { 2, Iclass_xt_iclass_call4_args, |
| 4356 | 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, |
| 4357 | { 2, Iclass_xt_iclass_callx12_args, |
| 4358 | 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, |
| 4359 | { 2, Iclass_xt_iclass_callx8_args, |
| 4360 | 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, |
| 4361 | { 2, Iclass_xt_iclass_callx4_args, |
| 4362 | 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, |
| 4363 | { 3, Iclass_xt_iclass_entry_args, |
| 4364 | 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, |
| 4365 | { 2, Iclass_xt_iclass_movsp_args, |
| 4366 | 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, |
| 4367 | { 1, Iclass_xt_iclass_rotw_args, |
| 4368 | 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, |
| 4369 | { 1, Iclass_xt_iclass_retw_args, |
| 4370 | 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, |
| 4371 | { 0, 0 /* xt_iclass_rfwou */, |
| 4372 | 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, |
| 4373 | { 3, Iclass_xt_iclass_l32e_args, |
| 4374 | 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 }, |
| 4375 | { 3, Iclass_xt_iclass_s32e_args, |
| 4376 | 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 }, |
| 4377 | { 1, Iclass_xt_iclass_rsr_windowbase_args, |
| 4378 | 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, |
| 4379 | { 1, Iclass_xt_iclass_wsr_windowbase_args, |
| 4380 | 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, |
| 4381 | { 1, Iclass_xt_iclass_xsr_windowbase_args, |
| 4382 | 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, |
| 4383 | { 1, Iclass_xt_iclass_rsr_windowstart_args, |
| 4384 | 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, |
| 4385 | { 1, Iclass_xt_iclass_wsr_windowstart_args, |
| 4386 | 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, |
| 4387 | { 1, Iclass_xt_iclass_xsr_windowstart_args, |
| 4388 | 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, |
| 4389 | { 3, Iclass_xt_iclass_add_n_args, |
| 4390 | 0, 0, 0, 0 }, |
| 4391 | { 3, Iclass_xt_iclass_addi_n_args, |
| 4392 | 0, 0, 0, 0 }, |
| 4393 | { 2, Iclass_xt_iclass_bz6_args, |
| 4394 | 0, 0, 0, 0 }, |
| 4395 | { 0, 0 /* xt_iclass_ill_n */, |
| 4396 | 0, 0, 0, 0 }, |
| 4397 | { 3, Iclass_xt_iclass_loadi4_args, |
| 4398 | 0, 0, 0, 0 }, |
| 4399 | { 2, Iclass_xt_iclass_mov_n_args, |
| 4400 | 0, 0, 0, 0 }, |
| 4401 | { 2, Iclass_xt_iclass_movi_n_args, |
| 4402 | 0, 0, 0, 0 }, |
| 4403 | { 0, 0 /* xt_iclass_nopn */, |
| 4404 | 0, 0, 0, 0 }, |
| 4405 | { 1, Iclass_xt_iclass_retn_args, |
| 4406 | 0, 0, 0, 0 }, |
| 4407 | { 3, Iclass_xt_iclass_storei4_args, |
| 4408 | 0, 0, 0, 0 }, |
| 4409 | { 3, Iclass_xt_iclass_addi_args, |
| 4410 | 0, 0, 0, 0 }, |
| 4411 | { 3, Iclass_xt_iclass_addmi_args, |
| 4412 | 0, 0, 0, 0 }, |
| 4413 | { 3, Iclass_xt_iclass_addsub_args, |
| 4414 | 0, 0, 0, 0 }, |
| 4415 | { 3, Iclass_xt_iclass_bit_args, |
| 4416 | 0, 0, 0, 0 }, |
| 4417 | { 3, Iclass_xt_iclass_bsi8_args, |
| 4418 | 0, 0, 0, 0 }, |
| 4419 | { 3, Iclass_xt_iclass_bsi8b_args, |
| 4420 | 0, 0, 0, 0 }, |
| 4421 | { 3, Iclass_xt_iclass_bsi8u_args, |
| 4422 | 0, 0, 0, 0 }, |
| 4423 | { 3, Iclass_xt_iclass_bst8_args, |
| 4424 | 0, 0, 0, 0 }, |
| 4425 | { 2, Iclass_xt_iclass_bsz12_args, |
| 4426 | 0, 0, 0, 0 }, |
| 4427 | { 2, Iclass_xt_iclass_call0_args, |
| 4428 | 0, 0, 0, 0 }, |
| 4429 | { 2, Iclass_xt_iclass_callx0_args, |
| 4430 | 0, 0, 0, 0 }, |
| 4431 | { 4, Iclass_xt_iclass_exti_args, |
| 4432 | 0, 0, 0, 0 }, |
| 4433 | { 0, 0 /* xt_iclass_ill */, |
| 4434 | 0, 0, 0, 0 }, |
| 4435 | { 1, Iclass_xt_iclass_jump_args, |
| 4436 | 0, 0, 0, 0 }, |
| 4437 | { 1, Iclass_xt_iclass_jumpx_args, |
| 4438 | 0, 0, 0, 0 }, |
| 4439 | { 3, Iclass_xt_iclass_l16ui_args, |
| 4440 | 0, 0, 0, 0 }, |
| 4441 | { 3, Iclass_xt_iclass_l16si_args, |
| 4442 | 0, 0, 0, 0 }, |
| 4443 | { 3, Iclass_xt_iclass_l32i_args, |
| 4444 | 0, 0, 0, 0 }, |
| 4445 | { 2, Iclass_xt_iclass_l32r_args, |
| 4446 | 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 }, |
| 4447 | { 3, Iclass_xt_iclass_l8i_args, |
| 4448 | 0, 0, 0, 0 }, |
| 4449 | { 2, Iclass_xt_iclass_loop_args, |
| 4450 | 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, |
| 4451 | { 2, Iclass_xt_iclass_loopz_args, |
| 4452 | 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, |
| 4453 | { 2, Iclass_xt_iclass_movi_args, |
| 4454 | 0, 0, 0, 0 }, |
| 4455 | { 3, Iclass_xt_iclass_movz_args, |
| 4456 | 0, 0, 0, 0 }, |
| 4457 | { 2, Iclass_xt_iclass_neg_args, |
| 4458 | 0, 0, 0, 0 }, |
| 4459 | { 0, 0 /* xt_iclass_nop */, |
| 4460 | 0, 0, 0, 0 }, |
| 4461 | { 1, Iclass_xt_iclass_return_args, |
| 4462 | 0, 0, 0, 0 }, |
| 4463 | { 3, Iclass_xt_iclass_s16i_args, |
| 4464 | 0, 0, 0, 0 }, |
| 4465 | { 3, Iclass_xt_iclass_s32i_args, |
| 4466 | 0, 0, 0, 0 }, |
| 4467 | { 3, Iclass_xt_iclass_s8i_args, |
| 4468 | 0, 0, 0, 0 }, |
| 4469 | { 1, Iclass_xt_iclass_sar_args, |
| 4470 | 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, |
| 4471 | { 1, Iclass_xt_iclass_sari_args, |
| 4472 | 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, |
| 4473 | { 2, Iclass_xt_iclass_shifts_args, |
| 4474 | 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, |
| 4475 | { 3, Iclass_xt_iclass_shiftst_args, |
| 4476 | 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, |
| 4477 | { 2, Iclass_xt_iclass_shiftt_args, |
| 4478 | 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, |
| 4479 | { 3, Iclass_xt_iclass_slli_args, |
| 4480 | 0, 0, 0, 0 }, |
| 4481 | { 3, Iclass_xt_iclass_srai_args, |
| 4482 | 0, 0, 0, 0 }, |
| 4483 | { 3, Iclass_xt_iclass_srli_args, |
| 4484 | 0, 0, 0, 0 }, |
| 4485 | { 0, 0 /* xt_iclass_memw */, |
| 4486 | 0, 0, 0, 0 }, |
| 4487 | { 0, 0 /* xt_iclass_extw */, |
| 4488 | 0, 0, 0, 0 }, |
| 4489 | { 0, 0 /* xt_iclass_isync */, |
| 4490 | 0, 0, 0, 0 }, |
| 4491 | { 0, 0 /* xt_iclass_sync */, |
| 4492 | 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, |
| 4493 | { 2, Iclass_xt_iclass_rsil_args, |
| 4494 | 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, |
| 4495 | { 1, Iclass_xt_iclass_rsr_lend_args, |
| 4496 | 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, |
| 4497 | { 1, Iclass_xt_iclass_wsr_lend_args, |
| 4498 | 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, |
| 4499 | { 1, Iclass_xt_iclass_xsr_lend_args, |
| 4500 | 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, |
| 4501 | { 1, Iclass_xt_iclass_rsr_lcount_args, |
| 4502 | 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, |
| 4503 | { 1, Iclass_xt_iclass_wsr_lcount_args, |
| 4504 | 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, |
| 4505 | { 1, Iclass_xt_iclass_xsr_lcount_args, |
| 4506 | 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, |
| 4507 | { 1, Iclass_xt_iclass_rsr_lbeg_args, |
| 4508 | 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, |
| 4509 | { 1, Iclass_xt_iclass_wsr_lbeg_args, |
| 4510 | 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, |
| 4511 | { 1, Iclass_xt_iclass_xsr_lbeg_args, |
| 4512 | 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, |
| 4513 | { 1, Iclass_xt_iclass_rsr_sar_args, |
| 4514 | 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, |
| 4515 | { 1, Iclass_xt_iclass_wsr_sar_args, |
| 4516 | 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, |
| 4517 | { 1, Iclass_xt_iclass_xsr_sar_args, |
| 4518 | 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, |
| 4519 | { 1, Iclass_xt_iclass_rsr_litbase_args, |
| 4520 | 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 }, |
| 4521 | { 1, Iclass_xt_iclass_wsr_litbase_args, |
| 4522 | 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 }, |
| 4523 | { 1, Iclass_xt_iclass_xsr_litbase_args, |
| 4524 | 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 }, |
| 4525 | { 1, Iclass_xt_iclass_rsr_176_args, |
| 4526 | 2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 }, |
| 4527 | { 1, Iclass_xt_iclass_rsr_208_args, |
| 4528 | 2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 }, |
| 4529 | { 1, Iclass_xt_iclass_rsr_ps_args, |
| 4530 | 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, |
| 4531 | { 1, Iclass_xt_iclass_wsr_ps_args, |
| 4532 | 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, |
| 4533 | { 1, Iclass_xt_iclass_xsr_ps_args, |
| 4534 | 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, |
| 4535 | { 1, Iclass_xt_iclass_rsr_epc1_args, |
| 4536 | 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, |
| 4537 | { 1, Iclass_xt_iclass_wsr_epc1_args, |
| 4538 | 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, |
| 4539 | { 1, Iclass_xt_iclass_xsr_epc1_args, |
| 4540 | 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, |
| 4541 | { 1, Iclass_xt_iclass_rsr_excsave1_args, |
| 4542 | 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, |
| 4543 | { 1, Iclass_xt_iclass_wsr_excsave1_args, |
| 4544 | 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, |
| 4545 | { 1, Iclass_xt_iclass_xsr_excsave1_args, |
| 4546 | 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, |
| 4547 | { 1, Iclass_xt_iclass_rsr_epc2_args, |
| 4548 | 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, |
| 4549 | { 1, Iclass_xt_iclass_wsr_epc2_args, |
| 4550 | 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, |
| 4551 | { 1, Iclass_xt_iclass_xsr_epc2_args, |
| 4552 | 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, |
| 4553 | { 1, Iclass_xt_iclass_rsr_excsave2_args, |
| 4554 | 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, |
| 4555 | { 1, Iclass_xt_iclass_wsr_excsave2_args, |
| 4556 | 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, |
| 4557 | { 1, Iclass_xt_iclass_xsr_excsave2_args, |
| 4558 | 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, |
| 4559 | { 1, Iclass_xt_iclass_rsr_epc3_args, |
| 4560 | 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, |
| 4561 | { 1, Iclass_xt_iclass_wsr_epc3_args, |
| 4562 | 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, |
| 4563 | { 1, Iclass_xt_iclass_xsr_epc3_args, |
| 4564 | 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, |
| 4565 | { 1, Iclass_xt_iclass_rsr_excsave3_args, |
| 4566 | 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, |
| 4567 | { 1, Iclass_xt_iclass_wsr_excsave3_args, |
| 4568 | 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, |
| 4569 | { 1, Iclass_xt_iclass_xsr_excsave3_args, |
| 4570 | 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, |
| 4571 | { 1, Iclass_xt_iclass_rsr_epc4_args, |
| 4572 | 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, |
| 4573 | { 1, Iclass_xt_iclass_wsr_epc4_args, |
| 4574 | 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, |
| 4575 | { 1, Iclass_xt_iclass_xsr_epc4_args, |
| 4576 | 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, |
| 4577 | { 1, Iclass_xt_iclass_rsr_excsave4_args, |
| 4578 | 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, |
| 4579 | { 1, Iclass_xt_iclass_wsr_excsave4_args, |
| 4580 | 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, |
| 4581 | { 1, Iclass_xt_iclass_xsr_excsave4_args, |
| 4582 | 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, |
| 4583 | { 1, Iclass_xt_iclass_rsr_eps2_args, |
| 4584 | 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, |
| 4585 | { 1, Iclass_xt_iclass_wsr_eps2_args, |
| 4586 | 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, |
| 4587 | { 1, Iclass_xt_iclass_xsr_eps2_args, |
| 4588 | 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, |
| 4589 | { 1, Iclass_xt_iclass_rsr_eps3_args, |
| 4590 | 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, |
| 4591 | { 1, Iclass_xt_iclass_wsr_eps3_args, |
| 4592 | 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, |
| 4593 | { 1, Iclass_xt_iclass_xsr_eps3_args, |
| 4594 | 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, |
| 4595 | { 1, Iclass_xt_iclass_rsr_eps4_args, |
| 4596 | 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, |
| 4597 | { 1, Iclass_xt_iclass_wsr_eps4_args, |
| 4598 | 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, |
| 4599 | { 1, Iclass_xt_iclass_xsr_eps4_args, |
| 4600 | 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, |
| 4601 | { 1, Iclass_xt_iclass_rsr_excvaddr_args, |
| 4602 | 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, |
| 4603 | { 1, Iclass_xt_iclass_wsr_excvaddr_args, |
| 4604 | 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, |
| 4605 | { 1, Iclass_xt_iclass_xsr_excvaddr_args, |
| 4606 | 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, |
| 4607 | { 1, Iclass_xt_iclass_rsr_depc_args, |
| 4608 | 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, |
| 4609 | { 1, Iclass_xt_iclass_wsr_depc_args, |
| 4610 | 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, |
| 4611 | { 1, Iclass_xt_iclass_xsr_depc_args, |
| 4612 | 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, |
| 4613 | { 1, Iclass_xt_iclass_rsr_exccause_args, |
| 4614 | 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, |
| 4615 | { 1, Iclass_xt_iclass_wsr_exccause_args, |
| 4616 | 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, |
| 4617 | { 1, Iclass_xt_iclass_xsr_exccause_args, |
| 4618 | 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, |
| 4619 | { 1, Iclass_xt_iclass_rsr_misc0_args, |
| 4620 | 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, |
| 4621 | { 1, Iclass_xt_iclass_wsr_misc0_args, |
| 4622 | 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, |
| 4623 | { 1, Iclass_xt_iclass_xsr_misc0_args, |
| 4624 | 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, |
| 4625 | { 1, Iclass_xt_iclass_rsr_misc1_args, |
| 4626 | 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, |
| 4627 | { 1, Iclass_xt_iclass_wsr_misc1_args, |
| 4628 | 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, |
| 4629 | { 1, Iclass_xt_iclass_xsr_misc1_args, |
| 4630 | 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, |
| 4631 | { 1, Iclass_xt_iclass_rsr_prid_args, |
| 4632 | 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 }, |
| 4633 | { 1, Iclass_xt_iclass_rfi_args, |
| 4634 | 15, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, |
| 4635 | { 1, Iclass_xt_iclass_wait_args, |
| 4636 | 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, |
| 4637 | { 1, Iclass_xt_iclass_rsr_interrupt_args, |
| 4638 | 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, |
| 4639 | { 1, Iclass_xt_iclass_wsr_intset_args, |
| 4640 | 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, |
| 4641 | { 1, Iclass_xt_iclass_wsr_intclear_args, |
| 4642 | 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, |
| 4643 | { 1, Iclass_xt_iclass_rsr_intenable_args, |
| 4644 | 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, |
| 4645 | { 1, Iclass_xt_iclass_wsr_intenable_args, |
| 4646 | 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, |
| 4647 | { 1, Iclass_xt_iclass_xsr_intenable_args, |
| 4648 | 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, |
| 4649 | { 2, Iclass_xt_iclass_break_args, |
| 4650 | 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, |
| 4651 | { 1, Iclass_xt_iclass_break_n_args, |
| 4652 | 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, |
| 4653 | { 1, Iclass_xt_iclass_rsr_dbreaka0_args, |
| 4654 | 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, |
| 4655 | { 1, Iclass_xt_iclass_wsr_dbreaka0_args, |
| 4656 | 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, |
| 4657 | { 1, Iclass_xt_iclass_xsr_dbreaka0_args, |
| 4658 | 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, |
| 4659 | { 1, Iclass_xt_iclass_rsr_dbreakc0_args, |
| 4660 | 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, |
| 4661 | { 1, Iclass_xt_iclass_wsr_dbreakc0_args, |
| 4662 | 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, |
| 4663 | { 1, Iclass_xt_iclass_xsr_dbreakc0_args, |
| 4664 | 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, |
| 4665 | { 1, Iclass_xt_iclass_rsr_dbreaka1_args, |
| 4666 | 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, |
| 4667 | { 1, Iclass_xt_iclass_wsr_dbreaka1_args, |
| 4668 | 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, |
| 4669 | { 1, Iclass_xt_iclass_xsr_dbreaka1_args, |
| 4670 | 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, |
| 4671 | { 1, Iclass_xt_iclass_rsr_dbreakc1_args, |
| 4672 | 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, |
| 4673 | { 1, Iclass_xt_iclass_wsr_dbreakc1_args, |
| 4674 | 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, |
| 4675 | { 1, Iclass_xt_iclass_xsr_dbreakc1_args, |
| 4676 | 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, |
| 4677 | { 1, Iclass_xt_iclass_rsr_ibreaka0_args, |
| 4678 | 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, |
| 4679 | { 1, Iclass_xt_iclass_wsr_ibreaka0_args, |
| 4680 | 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, |
| 4681 | { 1, Iclass_xt_iclass_xsr_ibreaka0_args, |
| 4682 | 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, |
| 4683 | { 1, Iclass_xt_iclass_rsr_ibreaka1_args, |
| 4684 | 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, |
| 4685 | { 1, Iclass_xt_iclass_wsr_ibreaka1_args, |
| 4686 | 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, |
| 4687 | { 1, Iclass_xt_iclass_xsr_ibreaka1_args, |
| 4688 | 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, |
| 4689 | { 1, Iclass_xt_iclass_rsr_ibreakenable_args, |
| 4690 | 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, |
| 4691 | { 1, Iclass_xt_iclass_wsr_ibreakenable_args, |
| 4692 | 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, |
| 4693 | { 1, Iclass_xt_iclass_xsr_ibreakenable_args, |
| 4694 | 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, |
| 4695 | { 1, Iclass_xt_iclass_rsr_debugcause_args, |
| 4696 | 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, |
| 4697 | { 1, Iclass_xt_iclass_wsr_debugcause_args, |
| 4698 | 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, |
| 4699 | { 1, Iclass_xt_iclass_xsr_debugcause_args, |
| 4700 | 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, |
| 4701 | { 1, Iclass_xt_iclass_rsr_icount_args, |
| 4702 | 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, |
| 4703 | { 1, Iclass_xt_iclass_wsr_icount_args, |
| 4704 | 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, |
| 4705 | { 1, Iclass_xt_iclass_xsr_icount_args, |
| 4706 | 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, |
| 4707 | { 1, Iclass_xt_iclass_rsr_icountlevel_args, |
| 4708 | 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, |
| 4709 | { 1, Iclass_xt_iclass_wsr_icountlevel_args, |
| 4710 | 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, |
| 4711 | { 1, Iclass_xt_iclass_xsr_icountlevel_args, |
| 4712 | 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, |
| 4713 | { 1, Iclass_xt_iclass_rsr_ddr_args, |
| 4714 | 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, |
| 4715 | { 1, Iclass_xt_iclass_wsr_ddr_args, |
| 4716 | 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, |
| 4717 | { 1, Iclass_xt_iclass_xsr_ddr_args, |
| 4718 | 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, |
| 4719 | { 0, 0 /* xt_iclass_rfdo */, |
| 4720 | 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, |
| 4721 | { 0, 0 /* xt_iclass_rfdd */, |
| 4722 | 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, |
| 4723 | { 1, Iclass_xt_iclass_rsr_ccount_args, |
| 4724 | 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, |
| 4725 | { 1, Iclass_xt_iclass_wsr_ccount_args, |
| 4726 | 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, |
| 4727 | { 1, Iclass_xt_iclass_xsr_ccount_args, |
| 4728 | 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, |
| 4729 | { 1, Iclass_xt_iclass_rsr_ccompare0_args, |
| 4730 | 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, |
| 4731 | { 1, Iclass_xt_iclass_wsr_ccompare0_args, |
| 4732 | 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, |
| 4733 | { 1, Iclass_xt_iclass_xsr_ccompare0_args, |
| 4734 | 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, |
| 4735 | { 1, Iclass_xt_iclass_rsr_ccompare1_args, |
| 4736 | 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, |
| 4737 | { 1, Iclass_xt_iclass_wsr_ccompare1_args, |
| 4738 | 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, |
| 4739 | { 1, Iclass_xt_iclass_xsr_ccompare1_args, |
| 4740 | 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, |
| 4741 | { 1, Iclass_xt_iclass_rsr_ccompare2_args, |
| 4742 | 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, |
| 4743 | { 1, Iclass_xt_iclass_wsr_ccompare2_args, |
| 4744 | 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, |
| 4745 | { 1, Iclass_xt_iclass_xsr_ccompare2_args, |
| 4746 | 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, |
| 4747 | { 2, Iclass_xt_iclass_icache_args, |
| 4748 | 0, 0, 0, 0 }, |
| 4749 | { 2, Iclass_xt_iclass_icache_inv_args, |
| 4750 | 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 }, |
| 4751 | { 2, Iclass_xt_iclass_licx_args, |
| 4752 | 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 }, |
| 4753 | { 2, Iclass_xt_iclass_sicx_args, |
| 4754 | 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 }, |
| 4755 | { 2, Iclass_xt_iclass_dcache_args, |
| 4756 | 0, 0, 0, 0 }, |
| 4757 | { 2, Iclass_xt_iclass_dcache_ind_args, |
| 4758 | 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 }, |
| 4759 | { 2, Iclass_xt_iclass_dcache_inv_args, |
| 4760 | 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 }, |
| 4761 | { 2, Iclass_xt_iclass_dpf_args, |
| 4762 | 0, 0, 0, 0 }, |
| 4763 | { 2, Iclass_xt_iclass_sdct_args, |
| 4764 | 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 }, |
| 4765 | { 2, Iclass_xt_iclass_ldct_args, |
| 4766 | 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 }, |
| 4767 | { 1, Iclass_xt_iclass_wsr_ptevaddr_args, |
| 4768 | 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 }, |
| 4769 | { 1, Iclass_xt_iclass_rsr_ptevaddr_args, |
| 4770 | 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 }, |
| 4771 | { 1, Iclass_xt_iclass_xsr_ptevaddr_args, |
| 4772 | 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 }, |
| 4773 | { 1, Iclass_xt_iclass_rsr_rasid_args, |
| 4774 | 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 }, |
| 4775 | { 1, Iclass_xt_iclass_wsr_rasid_args, |
| 4776 | 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 }, |
| 4777 | { 1, Iclass_xt_iclass_xsr_rasid_args, |
| 4778 | 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 }, |
| 4779 | { 1, Iclass_xt_iclass_rsr_itlbcfg_args, |
| 4780 | 3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 }, |
| 4781 | { 1, Iclass_xt_iclass_wsr_itlbcfg_args, |
| 4782 | 4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 }, |
| 4783 | { 1, Iclass_xt_iclass_xsr_itlbcfg_args, |
| 4784 | 4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 }, |
| 4785 | { 1, Iclass_xt_iclass_rsr_dtlbcfg_args, |
| 4786 | 3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 }, |
| 4787 | { 1, Iclass_xt_iclass_wsr_dtlbcfg_args, |
| 4788 | 4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 }, |
| 4789 | { 1, Iclass_xt_iclass_xsr_dtlbcfg_args, |
| 4790 | 4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 }, |
| 4791 | { 1, Iclass_xt_iclass_idtlb_args, |
| 4792 | 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, |
| 4793 | { 2, Iclass_xt_iclass_rdtlb_args, |
| 4794 | 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 }, |
| 4795 | { 2, Iclass_xt_iclass_wdtlb_args, |
| 4796 | 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, |
| 4797 | { 1, Iclass_xt_iclass_iitlb_args, |
| 4798 | 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 }, |
| 4799 | { 2, Iclass_xt_iclass_ritlb_args, |
| 4800 | 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 }, |
| 4801 | { 2, Iclass_xt_iclass_witlb_args, |
| 4802 | 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 }, |
| 4803 | { 0, 0 /* xt_iclass_ldpte */, |
| 4804 | 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 }, |
| 4805 | { 0, 0 /* xt_iclass_hwwitlba */, |
| 4806 | 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 }, |
| 4807 | { 0, 0 /* xt_iclass_hwwdtlba */, |
| 4808 | 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 }, |
| 4809 | { 2, Iclass_xt_iclass_nsa_args, |
| 4810 | 0, 0, 0, 0 } |
| 4811 | }; |
| 4812 | |
| 4813 | \f |
| 4814 | /* Opcode encodings. */ |
| 4815 | |
| 4816 | static void |
| 4817 | Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 4818 | { |
| 4819 | slotbuf[0] = 0x80200; |
| 4820 | } |
| 4821 | |
| 4822 | static void |
| 4823 | Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 4824 | { |
| 4825 | slotbuf[0] = 0x300; |
| 4826 | } |
| 4827 | |
| 4828 | static void |
| 4829 | Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 4830 | { |
| 4831 | slotbuf[0] = 0x2300; |
| 4832 | } |
| 4833 | |
| 4834 | static void |
| 4835 | Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 4836 | { |
| 4837 | slotbuf[0] = 0x500; |
| 4838 | } |
| 4839 | |
| 4840 | static void |
| 4841 | Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 4842 | { |
| 4843 | slotbuf[0] = 0x1500; |
| 4844 | } |
| 4845 | |
| 4846 | static void |
| 4847 | Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 4848 | { |
| 4849 | slotbuf[0] = 0x5c0000; |
| 4850 | } |
| 4851 | |
| 4852 | static void |
| 4853 | Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 4854 | { |
| 4855 | slotbuf[0] = 0x580000; |
| 4856 | } |
| 4857 | |
| 4858 | static void |
| 4859 | Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 4860 | { |
| 4861 | slotbuf[0] = 0x540000; |
| 4862 | } |
| 4863 | |
| 4864 | static void |
| 4865 | Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 4866 | { |
| 4867 | slotbuf[0] = 0xf0000; |
| 4868 | } |
| 4869 | |
| 4870 | static void |
| 4871 | Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 4872 | { |
| 4873 | slotbuf[0] = 0xb0000; |
| 4874 | } |
| 4875 | |
| 4876 | static void |
| 4877 | Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 4878 | { |
| 4879 | slotbuf[0] = 0x70000; |
| 4880 | } |
| 4881 | |
| 4882 | static void |
| 4883 | Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 4884 | { |
| 4885 | slotbuf[0] = 0x6c0000; |
| 4886 | } |
| 4887 | |
| 4888 | static void |
| 4889 | Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 4890 | { |
| 4891 | slotbuf[0] = 0x100; |
| 4892 | } |
| 4893 | |
| 4894 | static void |
| 4895 | Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 4896 | { |
| 4897 | slotbuf[0] = 0x804; |
| 4898 | } |
| 4899 | |
| 4900 | static void |
| 4901 | Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 4902 | { |
| 4903 | slotbuf[0] = 0x60000; |
| 4904 | } |
| 4905 | |
| 4906 | static void |
| 4907 | Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) |
| 4908 | { |
| 4909 | slotbuf[0] = 0xd10f; |
| 4910 | } |
| 4911 | |
| 4912 | static void |
| 4913 | Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 4914 | { |
| 4915 | slotbuf[0] = 0x4300; |
| 4916 | } |
| 4917 | |
| 4918 | static void |
| 4919 | Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 4920 | { |
| 4921 | slotbuf[0] = 0x5300; |
| 4922 | } |
| 4923 | |
| 4924 | static void |
| 4925 | Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 4926 | { |
| 4927 | slotbuf[0] = 0x90; |
| 4928 | } |
| 4929 | |
| 4930 | static void |
| 4931 | Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 4932 | { |
| 4933 | slotbuf[0] = 0x94; |
| 4934 | } |
| 4935 | |
| 4936 | static void |
| 4937 | Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 4938 | { |
| 4939 | slotbuf[0] = 0x4830; |
| 4940 | } |
| 4941 | |
| 4942 | static void |
| 4943 | Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 4944 | { |
| 4945 | slotbuf[0] = 0x4831; |
| 4946 | } |
| 4947 | |
| 4948 | static void |
| 4949 | Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 4950 | { |
| 4951 | slotbuf[0] = 0x4816; |
| 4952 | } |
| 4953 | |
| 4954 | static void |
| 4955 | Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 4956 | { |
| 4957 | slotbuf[0] = 0x4930; |
| 4958 | } |
| 4959 | |
| 4960 | static void |
| 4961 | Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 4962 | { |
| 4963 | slotbuf[0] = 0x4931; |
| 4964 | } |
| 4965 | |
| 4966 | static void |
| 4967 | Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 4968 | { |
| 4969 | slotbuf[0] = 0x4916; |
| 4970 | } |
| 4971 | |
| 4972 | static void |
| 4973 | Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) |
| 4974 | { |
| 4975 | slotbuf[0] = 0xa000; |
| 4976 | } |
| 4977 | |
| 4978 | static void |
| 4979 | Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) |
| 4980 | { |
| 4981 | slotbuf[0] = 0xb000; |
| 4982 | } |
| 4983 | |
| 4984 | static void |
| 4985 | Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) |
| 4986 | { |
| 4987 | slotbuf[0] = 0xc800; |
| 4988 | } |
| 4989 | |
| 4990 | static void |
| 4991 | Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) |
| 4992 | { |
| 4993 | slotbuf[0] = 0xcc00; |
| 4994 | } |
| 4995 | |
| 4996 | static void |
| 4997 | Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) |
| 4998 | { |
| 4999 | slotbuf[0] = 0xd60f; |
| 5000 | } |
| 5001 | |
| 5002 | static void |
| 5003 | Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) |
| 5004 | { |
| 5005 | slotbuf[0] = 0x8000; |
| 5006 | } |
| 5007 | |
| 5008 | static void |
| 5009 | Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) |
| 5010 | { |
| 5011 | slotbuf[0] = 0xd000; |
| 5012 | } |
| 5013 | |
| 5014 | static void |
| 5015 | Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) |
| 5016 | { |
| 5017 | slotbuf[0] = 0xc000; |
| 5018 | } |
| 5019 | |
| 5020 | static void |
| 5021 | Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) |
| 5022 | { |
| 5023 | slotbuf[0] = 0xd30f; |
| 5024 | } |
| 5025 | |
| 5026 | static void |
| 5027 | Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) |
| 5028 | { |
| 5029 | slotbuf[0] = 0xd00f; |
| 5030 | } |
| 5031 | |
| 5032 | static void |
| 5033 | Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) |
| 5034 | { |
| 5035 | slotbuf[0] = 0x9000; |
| 5036 | } |
| 5037 | |
| 5038 | static void |
| 5039 | Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5040 | { |
| 5041 | slotbuf[0] = 0x200c00; |
| 5042 | } |
| 5043 | |
| 5044 | static void |
| 5045 | Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5046 | { |
| 5047 | slotbuf[0] = 0x200d00; |
| 5048 | } |
| 5049 | |
| 5050 | static void |
| 5051 | Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5052 | { |
| 5053 | slotbuf[0] = 0x8; |
| 5054 | } |
| 5055 | |
| 5056 | static void |
| 5057 | Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5058 | { |
| 5059 | slotbuf[0] = 0xc; |
| 5060 | } |
| 5061 | |
| 5062 | static void |
| 5063 | Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5064 | { |
| 5065 | slotbuf[0] = 0x9; |
| 5066 | } |
| 5067 | |
| 5068 | static void |
| 5069 | Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5070 | { |
| 5071 | slotbuf[0] = 0xa; |
| 5072 | } |
| 5073 | |
| 5074 | static void |
| 5075 | Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5076 | { |
| 5077 | slotbuf[0] = 0xb; |
| 5078 | } |
| 5079 | |
| 5080 | static void |
| 5081 | Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5082 | { |
| 5083 | slotbuf[0] = 0xd; |
| 5084 | } |
| 5085 | |
| 5086 | static void |
| 5087 | Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5088 | { |
| 5089 | slotbuf[0] = 0xe; |
| 5090 | } |
| 5091 | |
| 5092 | static void |
| 5093 | Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5094 | { |
| 5095 | slotbuf[0] = 0xf; |
| 5096 | } |
| 5097 | |
| 5098 | static void |
| 5099 | Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5100 | { |
| 5101 | slotbuf[0] = 0x1; |
| 5102 | } |
| 5103 | |
| 5104 | static void |
| 5105 | Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5106 | { |
| 5107 | slotbuf[0] = 0x2; |
| 5108 | } |
| 5109 | |
| 5110 | static void |
| 5111 | Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5112 | { |
| 5113 | slotbuf[0] = 0x3; |
| 5114 | } |
| 5115 | |
| 5116 | static void |
| 5117 | Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5118 | { |
| 5119 | slotbuf[0] = 0x680000; |
| 5120 | } |
| 5121 | |
| 5122 | static void |
| 5123 | Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5124 | { |
| 5125 | slotbuf[0] = 0x690000; |
| 5126 | } |
| 5127 | |
| 5128 | static void |
| 5129 | Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5130 | { |
| 5131 | slotbuf[0] = 0x6b0000; |
| 5132 | } |
| 5133 | |
| 5134 | static void |
| 5135 | Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5136 | { |
| 5137 | slotbuf[0] = 0x6a0000; |
| 5138 | } |
| 5139 | |
| 5140 | static void |
| 5141 | Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5142 | { |
| 5143 | slotbuf[0] = 0x700600; |
| 5144 | } |
| 5145 | |
| 5146 | static void |
| 5147 | Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5148 | { |
| 5149 | slotbuf[0] = 0x700e00; |
| 5150 | } |
| 5151 | |
| 5152 | static void |
| 5153 | Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5154 | { |
| 5155 | slotbuf[0] = 0x6f0000; |
| 5156 | } |
| 5157 | |
| 5158 | static void |
| 5159 | Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5160 | { |
| 5161 | slotbuf[0] = 0x6e0000; |
| 5162 | } |
| 5163 | |
| 5164 | static void |
| 5165 | Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5166 | { |
| 5167 | slotbuf[0] = 0x700100; |
| 5168 | } |
| 5169 | |
| 5170 | static void |
| 5171 | Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5172 | { |
| 5173 | slotbuf[0] = 0x700900; |
| 5174 | } |
| 5175 | |
| 5176 | static void |
| 5177 | Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5178 | { |
| 5179 | slotbuf[0] = 0x700a00; |
| 5180 | } |
| 5181 | |
| 5182 | static void |
| 5183 | Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5184 | { |
| 5185 | slotbuf[0] = 0x700200; |
| 5186 | } |
| 5187 | |
| 5188 | static void |
| 5189 | Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5190 | { |
| 5191 | slotbuf[0] = 0x700b00; |
| 5192 | } |
| 5193 | |
| 5194 | static void |
| 5195 | Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5196 | { |
| 5197 | slotbuf[0] = 0x700300; |
| 5198 | } |
| 5199 | |
| 5200 | static void |
| 5201 | Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5202 | { |
| 5203 | slotbuf[0] = 0x700800; |
| 5204 | } |
| 5205 | |
| 5206 | static void |
| 5207 | Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5208 | { |
| 5209 | slotbuf[0] = 0x700000; |
| 5210 | } |
| 5211 | |
| 5212 | static void |
| 5213 | Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5214 | { |
| 5215 | slotbuf[0] = 0x700400; |
| 5216 | } |
| 5217 | |
| 5218 | static void |
| 5219 | Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5220 | { |
| 5221 | slotbuf[0] = 0x700c00; |
| 5222 | } |
| 5223 | |
| 5224 | static void |
| 5225 | Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5226 | { |
| 5227 | slotbuf[0] = 0x700500; |
| 5228 | } |
| 5229 | |
| 5230 | static void |
| 5231 | Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5232 | { |
| 5233 | slotbuf[0] = 0x700d00; |
| 5234 | } |
| 5235 | |
| 5236 | static void |
| 5237 | Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5238 | { |
| 5239 | slotbuf[0] = 0x640000; |
| 5240 | } |
| 5241 | |
| 5242 | static void |
| 5243 | Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5244 | { |
| 5245 | slotbuf[0] = 0x650000; |
| 5246 | } |
| 5247 | |
| 5248 | static void |
| 5249 | Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5250 | { |
| 5251 | slotbuf[0] = 0x670000; |
| 5252 | } |
| 5253 | |
| 5254 | static void |
| 5255 | Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5256 | { |
| 5257 | slotbuf[0] = 0x660000; |
| 5258 | } |
| 5259 | |
| 5260 | static void |
| 5261 | Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5262 | { |
| 5263 | slotbuf[0] = 0x500000; |
| 5264 | } |
| 5265 | |
| 5266 | static void |
| 5267 | Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5268 | { |
| 5269 | slotbuf[0] = 0x30000; |
| 5270 | } |
| 5271 | |
| 5272 | static void |
| 5273 | Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5274 | { |
| 5275 | slotbuf[0] = 0x40; |
| 5276 | } |
| 5277 | |
| 5278 | static void |
| 5279 | Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5280 | { |
| 5281 | slotbuf[0] = 0; |
| 5282 | } |
| 5283 | |
| 5284 | static void |
| 5285 | Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5286 | { |
| 5287 | slotbuf[0] = 0x600000; |
| 5288 | } |
| 5289 | |
| 5290 | static void |
| 5291 | Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5292 | { |
| 5293 | slotbuf[0] = 0xa0000; |
| 5294 | } |
| 5295 | |
| 5296 | static void |
| 5297 | Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5298 | { |
| 5299 | slotbuf[0] = 0x200100; |
| 5300 | } |
| 5301 | |
| 5302 | static void |
| 5303 | Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5304 | { |
| 5305 | slotbuf[0] = 0x200900; |
| 5306 | } |
| 5307 | |
| 5308 | static void |
| 5309 | Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5310 | { |
| 5311 | slotbuf[0] = 0x200200; |
| 5312 | } |
| 5313 | |
| 5314 | static void |
| 5315 | Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5316 | { |
| 5317 | slotbuf[0] = 0x100000; |
| 5318 | } |
| 5319 | |
| 5320 | static void |
| 5321 | Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5322 | { |
| 5323 | slotbuf[0] = 0x200000; |
| 5324 | } |
| 5325 | |
| 5326 | static void |
| 5327 | Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5328 | { |
| 5329 | slotbuf[0] = 0x6d0800; |
| 5330 | } |
| 5331 | |
| 5332 | static void |
| 5333 | Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5334 | { |
| 5335 | slotbuf[0] = 0x6d0900; |
| 5336 | } |
| 5337 | |
| 5338 | static void |
| 5339 | Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5340 | { |
| 5341 | slotbuf[0] = 0x6d0a00; |
| 5342 | } |
| 5343 | |
| 5344 | static void |
| 5345 | Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5346 | { |
| 5347 | slotbuf[0] = 0x200a00; |
| 5348 | } |
| 5349 | |
| 5350 | static void |
| 5351 | Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5352 | { |
| 5353 | slotbuf[0] = 0x38; |
| 5354 | } |
| 5355 | |
| 5356 | static void |
| 5357 | Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5358 | { |
| 5359 | slotbuf[0] = 0x39; |
| 5360 | } |
| 5361 | |
| 5362 | static void |
| 5363 | Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5364 | { |
| 5365 | slotbuf[0] = 0x3a; |
| 5366 | } |
| 5367 | |
| 5368 | static void |
| 5369 | Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5370 | { |
| 5371 | slotbuf[0] = 0x3b; |
| 5372 | } |
| 5373 | |
| 5374 | static void |
| 5375 | Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5376 | { |
| 5377 | slotbuf[0] = 0x6; |
| 5378 | } |
| 5379 | |
| 5380 | static void |
| 5381 | Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5382 | { |
| 5383 | slotbuf[0] = 0x1006; |
| 5384 | } |
| 5385 | |
| 5386 | static void |
| 5387 | Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5388 | { |
| 5389 | slotbuf[0] = 0xf0200; |
| 5390 | } |
| 5391 | |
| 5392 | static void |
| 5393 | Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5394 | { |
| 5395 | slotbuf[0] = 0x20000; |
| 5396 | } |
| 5397 | |
| 5398 | static void |
| 5399 | Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5400 | { |
| 5401 | slotbuf[0] = 0x200500; |
| 5402 | } |
| 5403 | |
| 5404 | static void |
| 5405 | Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5406 | { |
| 5407 | slotbuf[0] = 0x200600; |
| 5408 | } |
| 5409 | |
| 5410 | static void |
| 5411 | Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5412 | { |
| 5413 | slotbuf[0] = 0x200400; |
| 5414 | } |
| 5415 | |
| 5416 | static void |
| 5417 | Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5418 | { |
| 5419 | slotbuf[0] = 0x4; |
| 5420 | } |
| 5421 | |
| 5422 | static void |
| 5423 | Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5424 | { |
| 5425 | slotbuf[0] = 0x104; |
| 5426 | } |
| 5427 | |
| 5428 | static void |
| 5429 | Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5430 | { |
| 5431 | slotbuf[0] = 0x204; |
| 5432 | } |
| 5433 | |
| 5434 | static void |
| 5435 | Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5436 | { |
| 5437 | slotbuf[0] = 0x304; |
| 5438 | } |
| 5439 | |
| 5440 | static void |
| 5441 | Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5442 | { |
| 5443 | slotbuf[0] = 0x404; |
| 5444 | } |
| 5445 | |
| 5446 | static void |
| 5447 | Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5448 | { |
| 5449 | slotbuf[0] = 0x1a; |
| 5450 | } |
| 5451 | |
| 5452 | static void |
| 5453 | Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5454 | { |
| 5455 | slotbuf[0] = 0x18; |
| 5456 | } |
| 5457 | |
| 5458 | static void |
| 5459 | Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5460 | { |
| 5461 | slotbuf[0] = 0x19; |
| 5462 | } |
| 5463 | |
| 5464 | static void |
| 5465 | Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5466 | { |
| 5467 | slotbuf[0] = 0x1b; |
| 5468 | } |
| 5469 | |
| 5470 | static void |
| 5471 | Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5472 | { |
| 5473 | slotbuf[0] = 0x10; |
| 5474 | } |
| 5475 | |
| 5476 | static void |
| 5477 | Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5478 | { |
| 5479 | slotbuf[0] = 0x12; |
| 5480 | } |
| 5481 | |
| 5482 | static void |
| 5483 | Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5484 | { |
| 5485 | slotbuf[0] = 0x14; |
| 5486 | } |
| 5487 | |
| 5488 | static void |
| 5489 | Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5490 | { |
| 5491 | slotbuf[0] = 0xc0200; |
| 5492 | } |
| 5493 | |
| 5494 | static void |
| 5495 | Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5496 | { |
| 5497 | slotbuf[0] = 0xd0200; |
| 5498 | } |
| 5499 | |
| 5500 | static void |
| 5501 | Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5502 | { |
| 5503 | slotbuf[0] = 0x200; |
| 5504 | } |
| 5505 | |
| 5506 | static void |
| 5507 | Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5508 | { |
| 5509 | slotbuf[0] = 0x10200; |
| 5510 | } |
| 5511 | |
| 5512 | static void |
| 5513 | Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5514 | { |
| 5515 | slotbuf[0] = 0x20200; |
| 5516 | } |
| 5517 | |
| 5518 | static void |
| 5519 | Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5520 | { |
| 5521 | slotbuf[0] = 0x30200; |
| 5522 | } |
| 5523 | |
| 5524 | static void |
| 5525 | Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5526 | { |
| 5527 | slotbuf[0] = 0x600; |
| 5528 | } |
| 5529 | |
| 5530 | static void |
| 5531 | Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5532 | { |
| 5533 | slotbuf[0] = 0x130; |
| 5534 | } |
| 5535 | |
| 5536 | static void |
| 5537 | Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5538 | { |
| 5539 | slotbuf[0] = 0x131; |
| 5540 | } |
| 5541 | |
| 5542 | static void |
| 5543 | Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5544 | { |
| 5545 | slotbuf[0] = 0x116; |
| 5546 | } |
| 5547 | |
| 5548 | static void |
| 5549 | Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5550 | { |
| 5551 | slotbuf[0] = 0x230; |
| 5552 | } |
| 5553 | |
| 5554 | static void |
| 5555 | Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5556 | { |
| 5557 | slotbuf[0] = 0x231; |
| 5558 | } |
| 5559 | |
| 5560 | static void |
| 5561 | Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5562 | { |
| 5563 | slotbuf[0] = 0x216; |
| 5564 | } |
| 5565 | |
| 5566 | static void |
| 5567 | Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5568 | { |
| 5569 | slotbuf[0] = 0x30; |
| 5570 | } |
| 5571 | |
| 5572 | static void |
| 5573 | Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5574 | { |
| 5575 | slotbuf[0] = 0x31; |
| 5576 | } |
| 5577 | |
| 5578 | static void |
| 5579 | Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5580 | { |
| 5581 | slotbuf[0] = 0x16; |
| 5582 | } |
| 5583 | |
| 5584 | static void |
| 5585 | Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5586 | { |
| 5587 | slotbuf[0] = 0x330; |
| 5588 | } |
| 5589 | |
| 5590 | static void |
| 5591 | Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5592 | { |
| 5593 | slotbuf[0] = 0x331; |
| 5594 | } |
| 5595 | |
| 5596 | static void |
| 5597 | Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5598 | { |
| 5599 | slotbuf[0] = 0x316; |
| 5600 | } |
| 5601 | |
| 5602 | static void |
| 5603 | Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5604 | { |
| 5605 | slotbuf[0] = 0x530; |
| 5606 | } |
| 5607 | |
| 5608 | static void |
| 5609 | Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5610 | { |
| 5611 | slotbuf[0] = 0x531; |
| 5612 | } |
| 5613 | |
| 5614 | static void |
| 5615 | Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5616 | { |
| 5617 | slotbuf[0] = 0x516; |
| 5618 | } |
| 5619 | |
| 5620 | static void |
| 5621 | Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5622 | { |
| 5623 | slotbuf[0] = 0xb030; |
| 5624 | } |
| 5625 | |
| 5626 | static void |
| 5627 | Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5628 | { |
| 5629 | slotbuf[0] = 0xd030; |
| 5630 | } |
| 5631 | |
| 5632 | static void |
| 5633 | Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5634 | { |
| 5635 | slotbuf[0] = 0xe630; |
| 5636 | } |
| 5637 | |
| 5638 | static void |
| 5639 | Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5640 | { |
| 5641 | slotbuf[0] = 0xe631; |
| 5642 | } |
| 5643 | |
| 5644 | static void |
| 5645 | Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5646 | { |
| 5647 | slotbuf[0] = 0xe616; |
| 5648 | } |
| 5649 | |
| 5650 | static void |
| 5651 | Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5652 | { |
| 5653 | slotbuf[0] = 0xb130; |
| 5654 | } |
| 5655 | |
| 5656 | static void |
| 5657 | Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5658 | { |
| 5659 | slotbuf[0] = 0xb131; |
| 5660 | } |
| 5661 | |
| 5662 | static void |
| 5663 | Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5664 | { |
| 5665 | slotbuf[0] = 0xb116; |
| 5666 | } |
| 5667 | |
| 5668 | static void |
| 5669 | Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5670 | { |
| 5671 | slotbuf[0] = 0xd130; |
| 5672 | } |
| 5673 | |
| 5674 | static void |
| 5675 | Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5676 | { |
| 5677 | slotbuf[0] = 0xd131; |
| 5678 | } |
| 5679 | |
| 5680 | static void |
| 5681 | Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5682 | { |
| 5683 | slotbuf[0] = 0xd116; |
| 5684 | } |
| 5685 | |
| 5686 | static void |
| 5687 | Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5688 | { |
| 5689 | slotbuf[0] = 0xb230; |
| 5690 | } |
| 5691 | |
| 5692 | static void |
| 5693 | Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5694 | { |
| 5695 | slotbuf[0] = 0xb231; |
| 5696 | } |
| 5697 | |
| 5698 | static void |
| 5699 | Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5700 | { |
| 5701 | slotbuf[0] = 0xb216; |
| 5702 | } |
| 5703 | |
| 5704 | static void |
| 5705 | Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5706 | { |
| 5707 | slotbuf[0] = 0xd230; |
| 5708 | } |
| 5709 | |
| 5710 | static void |
| 5711 | Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5712 | { |
| 5713 | slotbuf[0] = 0xd231; |
| 5714 | } |
| 5715 | |
| 5716 | static void |
| 5717 | Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5718 | { |
| 5719 | slotbuf[0] = 0xd216; |
| 5720 | } |
| 5721 | |
| 5722 | static void |
| 5723 | Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5724 | { |
| 5725 | slotbuf[0] = 0xb330; |
| 5726 | } |
| 5727 | |
| 5728 | static void |
| 5729 | Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5730 | { |
| 5731 | slotbuf[0] = 0xb331; |
| 5732 | } |
| 5733 | |
| 5734 | static void |
| 5735 | Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5736 | { |
| 5737 | slotbuf[0] = 0xb316; |
| 5738 | } |
| 5739 | |
| 5740 | static void |
| 5741 | Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5742 | { |
| 5743 | slotbuf[0] = 0xd330; |
| 5744 | } |
| 5745 | |
| 5746 | static void |
| 5747 | Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5748 | { |
| 5749 | slotbuf[0] = 0xd331; |
| 5750 | } |
| 5751 | |
| 5752 | static void |
| 5753 | Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5754 | { |
| 5755 | slotbuf[0] = 0xd316; |
| 5756 | } |
| 5757 | |
| 5758 | static void |
| 5759 | Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5760 | { |
| 5761 | slotbuf[0] = 0xb430; |
| 5762 | } |
| 5763 | |
| 5764 | static void |
| 5765 | Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5766 | { |
| 5767 | slotbuf[0] = 0xb431; |
| 5768 | } |
| 5769 | |
| 5770 | static void |
| 5771 | Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5772 | { |
| 5773 | slotbuf[0] = 0xb416; |
| 5774 | } |
| 5775 | |
| 5776 | static void |
| 5777 | Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5778 | { |
| 5779 | slotbuf[0] = 0xd430; |
| 5780 | } |
| 5781 | |
| 5782 | static void |
| 5783 | Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5784 | { |
| 5785 | slotbuf[0] = 0xd431; |
| 5786 | } |
| 5787 | |
| 5788 | static void |
| 5789 | Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5790 | { |
| 5791 | slotbuf[0] = 0xd416; |
| 5792 | } |
| 5793 | |
| 5794 | static void |
| 5795 | Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5796 | { |
| 5797 | slotbuf[0] = 0xc230; |
| 5798 | } |
| 5799 | |
| 5800 | static void |
| 5801 | Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5802 | { |
| 5803 | slotbuf[0] = 0xc231; |
| 5804 | } |
| 5805 | |
| 5806 | static void |
| 5807 | Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5808 | { |
| 5809 | slotbuf[0] = 0xc216; |
| 5810 | } |
| 5811 | |
| 5812 | static void |
| 5813 | Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5814 | { |
| 5815 | slotbuf[0] = 0xc330; |
| 5816 | } |
| 5817 | |
| 5818 | static void |
| 5819 | Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5820 | { |
| 5821 | slotbuf[0] = 0xc331; |
| 5822 | } |
| 5823 | |
| 5824 | static void |
| 5825 | Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5826 | { |
| 5827 | slotbuf[0] = 0xc316; |
| 5828 | } |
| 5829 | |
| 5830 | static void |
| 5831 | Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5832 | { |
| 5833 | slotbuf[0] = 0xc430; |
| 5834 | } |
| 5835 | |
| 5836 | static void |
| 5837 | Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5838 | { |
| 5839 | slotbuf[0] = 0xc431; |
| 5840 | } |
| 5841 | |
| 5842 | static void |
| 5843 | Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5844 | { |
| 5845 | slotbuf[0] = 0xc416; |
| 5846 | } |
| 5847 | |
| 5848 | static void |
| 5849 | Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5850 | { |
| 5851 | slotbuf[0] = 0xee30; |
| 5852 | } |
| 5853 | |
| 5854 | static void |
| 5855 | Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5856 | { |
| 5857 | slotbuf[0] = 0xee31; |
| 5858 | } |
| 5859 | |
| 5860 | static void |
| 5861 | Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5862 | { |
| 5863 | slotbuf[0] = 0xee16; |
| 5864 | } |
| 5865 | |
| 5866 | static void |
| 5867 | Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5868 | { |
| 5869 | slotbuf[0] = 0xc030; |
| 5870 | } |
| 5871 | |
| 5872 | static void |
| 5873 | Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5874 | { |
| 5875 | slotbuf[0] = 0xc031; |
| 5876 | } |
| 5877 | |
| 5878 | static void |
| 5879 | Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5880 | { |
| 5881 | slotbuf[0] = 0xc016; |
| 5882 | } |
| 5883 | |
| 5884 | static void |
| 5885 | Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5886 | { |
| 5887 | slotbuf[0] = 0xe830; |
| 5888 | } |
| 5889 | |
| 5890 | static void |
| 5891 | Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5892 | { |
| 5893 | slotbuf[0] = 0xe831; |
| 5894 | } |
| 5895 | |
| 5896 | static void |
| 5897 | Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5898 | { |
| 5899 | slotbuf[0] = 0xe816; |
| 5900 | } |
| 5901 | |
| 5902 | static void |
| 5903 | Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5904 | { |
| 5905 | slotbuf[0] = 0xf430; |
| 5906 | } |
| 5907 | |
| 5908 | static void |
| 5909 | Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5910 | { |
| 5911 | slotbuf[0] = 0xf431; |
| 5912 | } |
| 5913 | |
| 5914 | static void |
| 5915 | Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5916 | { |
| 5917 | slotbuf[0] = 0xf416; |
| 5918 | } |
| 5919 | |
| 5920 | static void |
| 5921 | Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5922 | { |
| 5923 | slotbuf[0] = 0xf530; |
| 5924 | } |
| 5925 | |
| 5926 | static void |
| 5927 | Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5928 | { |
| 5929 | slotbuf[0] = 0xf531; |
| 5930 | } |
| 5931 | |
| 5932 | static void |
| 5933 | Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5934 | { |
| 5935 | slotbuf[0] = 0xf516; |
| 5936 | } |
| 5937 | |
| 5938 | static void |
| 5939 | Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5940 | { |
| 5941 | slotbuf[0] = 0xeb30; |
| 5942 | } |
| 5943 | |
| 5944 | static void |
| 5945 | Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5946 | { |
| 5947 | slotbuf[0] = 0x10300; |
| 5948 | } |
| 5949 | |
| 5950 | static void |
| 5951 | Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5952 | { |
| 5953 | slotbuf[0] = 0x700; |
| 5954 | } |
| 5955 | |
| 5956 | static void |
| 5957 | Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5958 | { |
| 5959 | slotbuf[0] = 0xe230; |
| 5960 | } |
| 5961 | |
| 5962 | static void |
| 5963 | Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5964 | { |
| 5965 | slotbuf[0] = 0xe231; |
| 5966 | } |
| 5967 | |
| 5968 | static void |
| 5969 | Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5970 | { |
| 5971 | slotbuf[0] = 0xe331; |
| 5972 | } |
| 5973 | |
| 5974 | static void |
| 5975 | Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5976 | { |
| 5977 | slotbuf[0] = 0xe430; |
| 5978 | } |
| 5979 | |
| 5980 | static void |
| 5981 | Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5982 | { |
| 5983 | slotbuf[0] = 0xe431; |
| 5984 | } |
| 5985 | |
| 5986 | static void |
| 5987 | Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5988 | { |
| 5989 | slotbuf[0] = 0xe416; |
| 5990 | } |
| 5991 | |
| 5992 | static void |
| 5993 | Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5994 | { |
| 5995 | slotbuf[0] = 0x400; |
| 5996 | } |
| 5997 | |
| 5998 | static void |
| 5999 | Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) |
| 6000 | { |
| 6001 | slotbuf[0] = 0xd20f; |
| 6002 | } |
| 6003 | |
| 6004 | static void |
| 6005 | Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6006 | { |
| 6007 | slotbuf[0] = 0x9030; |
| 6008 | } |
| 6009 | |
| 6010 | static void |
| 6011 | Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6012 | { |
| 6013 | slotbuf[0] = 0x9031; |
| 6014 | } |
| 6015 | |
| 6016 | static void |
| 6017 | Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6018 | { |
| 6019 | slotbuf[0] = 0x9016; |
| 6020 | } |
| 6021 | |
| 6022 | static void |
| 6023 | Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6024 | { |
| 6025 | slotbuf[0] = 0xa030; |
| 6026 | } |
| 6027 | |
| 6028 | static void |
| 6029 | Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6030 | { |
| 6031 | slotbuf[0] = 0xa031; |
| 6032 | } |
| 6033 | |
| 6034 | static void |
| 6035 | Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6036 | { |
| 6037 | slotbuf[0] = 0xa016; |
| 6038 | } |
| 6039 | |
| 6040 | static void |
| 6041 | Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6042 | { |
| 6043 | slotbuf[0] = 0x9130; |
| 6044 | } |
| 6045 | |
| 6046 | static void |
| 6047 | Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6048 | { |
| 6049 | slotbuf[0] = 0x9131; |
| 6050 | } |
| 6051 | |
| 6052 | static void |
| 6053 | Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6054 | { |
| 6055 | slotbuf[0] = 0x9116; |
| 6056 | } |
| 6057 | |
| 6058 | static void |
| 6059 | Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6060 | { |
| 6061 | slotbuf[0] = 0xa130; |
| 6062 | } |
| 6063 | |
| 6064 | static void |
| 6065 | Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6066 | { |
| 6067 | slotbuf[0] = 0xa131; |
| 6068 | } |
| 6069 | |
| 6070 | static void |
| 6071 | Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6072 | { |
| 6073 | slotbuf[0] = 0xa116; |
| 6074 | } |
| 6075 | |
| 6076 | static void |
| 6077 | Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6078 | { |
| 6079 | slotbuf[0] = 0x8030; |
| 6080 | } |
| 6081 | |
| 6082 | static void |
| 6083 | Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6084 | { |
| 6085 | slotbuf[0] = 0x8031; |
| 6086 | } |
| 6087 | |
| 6088 | static void |
| 6089 | Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6090 | { |
| 6091 | slotbuf[0] = 0x8016; |
| 6092 | } |
| 6093 | |
| 6094 | static void |
| 6095 | Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6096 | { |
| 6097 | slotbuf[0] = 0x8130; |
| 6098 | } |
| 6099 | |
| 6100 | static void |
| 6101 | Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6102 | { |
| 6103 | slotbuf[0] = 0x8131; |
| 6104 | } |
| 6105 | |
| 6106 | static void |
| 6107 | Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6108 | { |
| 6109 | slotbuf[0] = 0x8116; |
| 6110 | } |
| 6111 | |
| 6112 | static void |
| 6113 | Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6114 | { |
| 6115 | slotbuf[0] = 0x6030; |
| 6116 | } |
| 6117 | |
| 6118 | static void |
| 6119 | Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6120 | { |
| 6121 | slotbuf[0] = 0x6031; |
| 6122 | } |
| 6123 | |
| 6124 | static void |
| 6125 | Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6126 | { |
| 6127 | slotbuf[0] = 0x6016; |
| 6128 | } |
| 6129 | |
| 6130 | static void |
| 6131 | Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6132 | { |
| 6133 | slotbuf[0] = 0xe930; |
| 6134 | } |
| 6135 | |
| 6136 | static void |
| 6137 | Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6138 | { |
| 6139 | slotbuf[0] = 0xe931; |
| 6140 | } |
| 6141 | |
| 6142 | static void |
| 6143 | Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6144 | { |
| 6145 | slotbuf[0] = 0xe916; |
| 6146 | } |
| 6147 | |
| 6148 | static void |
| 6149 | Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6150 | { |
| 6151 | slotbuf[0] = 0xec30; |
| 6152 | } |
| 6153 | |
| 6154 | static void |
| 6155 | Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6156 | { |
| 6157 | slotbuf[0] = 0xec31; |
| 6158 | } |
| 6159 | |
| 6160 | static void |
| 6161 | Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6162 | { |
| 6163 | slotbuf[0] = 0xec16; |
| 6164 | } |
| 6165 | |
| 6166 | static void |
| 6167 | Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6168 | { |
| 6169 | slotbuf[0] = 0xed30; |
| 6170 | } |
| 6171 | |
| 6172 | static void |
| 6173 | Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6174 | { |
| 6175 | slotbuf[0] = 0xed31; |
| 6176 | } |
| 6177 | |
| 6178 | static void |
| 6179 | Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6180 | { |
| 6181 | slotbuf[0] = 0xed16; |
| 6182 | } |
| 6183 | |
| 6184 | static void |
| 6185 | Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6186 | { |
| 6187 | slotbuf[0] = 0x6830; |
| 6188 | } |
| 6189 | |
| 6190 | static void |
| 6191 | Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6192 | { |
| 6193 | slotbuf[0] = 0x6831; |
| 6194 | } |
| 6195 | |
| 6196 | static void |
| 6197 | Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6198 | { |
| 6199 | slotbuf[0] = 0x6816; |
| 6200 | } |
| 6201 | |
| 6202 | static void |
| 6203 | Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6204 | { |
| 6205 | slotbuf[0] = 0xe1f; |
| 6206 | } |
| 6207 | |
| 6208 | static void |
| 6209 | Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6210 | { |
| 6211 | slotbuf[0] = 0x10e1f; |
| 6212 | } |
| 6213 | |
| 6214 | static void |
| 6215 | Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6216 | { |
| 6217 | slotbuf[0] = 0xea30; |
| 6218 | } |
| 6219 | |
| 6220 | static void |
| 6221 | Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6222 | { |
| 6223 | slotbuf[0] = 0xea31; |
| 6224 | } |
| 6225 | |
| 6226 | static void |
| 6227 | Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6228 | { |
| 6229 | slotbuf[0] = 0xea16; |
| 6230 | } |
| 6231 | |
| 6232 | static void |
| 6233 | Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6234 | { |
| 6235 | slotbuf[0] = 0xf030; |
| 6236 | } |
| 6237 | |
| 6238 | static void |
| 6239 | Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6240 | { |
| 6241 | slotbuf[0] = 0xf031; |
| 6242 | } |
| 6243 | |
| 6244 | static void |
| 6245 | Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6246 | { |
| 6247 | slotbuf[0] = 0xf016; |
| 6248 | } |
| 6249 | |
| 6250 | static void |
| 6251 | Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6252 | { |
| 6253 | slotbuf[0] = 0xf130; |
| 6254 | } |
| 6255 | |
| 6256 | static void |
| 6257 | Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6258 | { |
| 6259 | slotbuf[0] = 0xf131; |
| 6260 | } |
| 6261 | |
| 6262 | static void |
| 6263 | Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6264 | { |
| 6265 | slotbuf[0] = 0xf116; |
| 6266 | } |
| 6267 | |
| 6268 | static void |
| 6269 | Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6270 | { |
| 6271 | slotbuf[0] = 0xf230; |
| 6272 | } |
| 6273 | |
| 6274 | static void |
| 6275 | Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6276 | { |
| 6277 | slotbuf[0] = 0xf231; |
| 6278 | } |
| 6279 | |
| 6280 | static void |
| 6281 | Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6282 | { |
| 6283 | slotbuf[0] = 0xf216; |
| 6284 | } |
| 6285 | |
| 6286 | static void |
| 6287 | Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6288 | { |
| 6289 | slotbuf[0] = 0x2c0700; |
| 6290 | } |
| 6291 | |
| 6292 | static void |
| 6293 | Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6294 | { |
| 6295 | slotbuf[0] = 0x2e0700; |
| 6296 | } |
| 6297 | |
| 6298 | static void |
| 6299 | Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6300 | { |
| 6301 | slotbuf[0] = 0x2f0700; |
| 6302 | } |
| 6303 | |
| 6304 | static void |
| 6305 | Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6306 | { |
| 6307 | slotbuf[0] = 0x1f; |
| 6308 | } |
| 6309 | |
| 6310 | static void |
| 6311 | Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6312 | { |
| 6313 | slotbuf[0] = 0x21f; |
| 6314 | } |
| 6315 | |
| 6316 | static void |
| 6317 | Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6318 | { |
| 6319 | slotbuf[0] = 0x11f; |
| 6320 | } |
| 6321 | |
| 6322 | static void |
| 6323 | Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6324 | { |
| 6325 | slotbuf[0] = 0x31f; |
| 6326 | } |
| 6327 | |
| 6328 | static void |
| 6329 | Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6330 | { |
| 6331 | slotbuf[0] = 0x240700; |
| 6332 | } |
| 6333 | |
| 6334 | static void |
| 6335 | Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6336 | { |
| 6337 | slotbuf[0] = 0x250700; |
| 6338 | } |
| 6339 | |
| 6340 | static void |
| 6341 | Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6342 | { |
| 6343 | slotbuf[0] = 0x280740; |
| 6344 | } |
| 6345 | |
| 6346 | static void |
| 6347 | Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6348 | { |
| 6349 | slotbuf[0] = 0x280750; |
| 6350 | } |
| 6351 | |
| 6352 | static void |
| 6353 | Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6354 | { |
| 6355 | slotbuf[0] = 0x260700; |
| 6356 | } |
| 6357 | |
| 6358 | static void |
| 6359 | Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6360 | { |
| 6361 | slotbuf[0] = 0x270700; |
| 6362 | } |
| 6363 | |
| 6364 | static void |
| 6365 | Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6366 | { |
| 6367 | slotbuf[0] = 0x200700; |
| 6368 | } |
| 6369 | |
| 6370 | static void |
| 6371 | Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6372 | { |
| 6373 | slotbuf[0] = 0x210700; |
| 6374 | } |
| 6375 | |
| 6376 | static void |
| 6377 | Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6378 | { |
| 6379 | slotbuf[0] = 0x220700; |
| 6380 | } |
| 6381 | |
| 6382 | static void |
| 6383 | Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6384 | { |
| 6385 | slotbuf[0] = 0x230700; |
| 6386 | } |
| 6387 | |
| 6388 | static void |
| 6389 | Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6390 | { |
| 6391 | slotbuf[0] = 0x91f; |
| 6392 | } |
| 6393 | |
| 6394 | static void |
| 6395 | Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6396 | { |
| 6397 | slotbuf[0] = 0x81f; |
| 6398 | } |
| 6399 | |
| 6400 | static void |
| 6401 | Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6402 | { |
| 6403 | slotbuf[0] = 0x5331; |
| 6404 | } |
| 6405 | |
| 6406 | static void |
| 6407 | Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6408 | { |
| 6409 | slotbuf[0] = 0x5330; |
| 6410 | } |
| 6411 | |
| 6412 | static void |
| 6413 | Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6414 | { |
| 6415 | slotbuf[0] = 0x5316; |
| 6416 | } |
| 6417 | |
| 6418 | static void |
| 6419 | Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6420 | { |
| 6421 | slotbuf[0] = 0x5a30; |
| 6422 | } |
| 6423 | |
| 6424 | static void |
| 6425 | Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6426 | { |
| 6427 | slotbuf[0] = 0x5a31; |
| 6428 | } |
| 6429 | |
| 6430 | static void |
| 6431 | Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6432 | { |
| 6433 | slotbuf[0] = 0x5a16; |
| 6434 | } |
| 6435 | |
| 6436 | static void |
| 6437 | Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6438 | { |
| 6439 | slotbuf[0] = 0x5b30; |
| 6440 | } |
| 6441 | |
| 6442 | static void |
| 6443 | Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6444 | { |
| 6445 | slotbuf[0] = 0x5b31; |
| 6446 | } |
| 6447 | |
| 6448 | static void |
| 6449 | Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6450 | { |
| 6451 | slotbuf[0] = 0x5b16; |
| 6452 | } |
| 6453 | |
| 6454 | static void |
| 6455 | Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6456 | { |
| 6457 | slotbuf[0] = 0x5c30; |
| 6458 | } |
| 6459 | |
| 6460 | static void |
| 6461 | Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6462 | { |
| 6463 | slotbuf[0] = 0x5c31; |
| 6464 | } |
| 6465 | |
| 6466 | static void |
| 6467 | Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6468 | { |
| 6469 | slotbuf[0] = 0x5c16; |
| 6470 | } |
| 6471 | |
| 6472 | static void |
| 6473 | Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6474 | { |
| 6475 | slotbuf[0] = 0xc05; |
| 6476 | } |
| 6477 | |
| 6478 | static void |
| 6479 | Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6480 | { |
| 6481 | slotbuf[0] = 0xd05; |
| 6482 | } |
| 6483 | |
| 6484 | static void |
| 6485 | Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6486 | { |
| 6487 | slotbuf[0] = 0xb05; |
| 6488 | } |
| 6489 | |
| 6490 | static void |
| 6491 | Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6492 | { |
| 6493 | slotbuf[0] = 0xf05; |
| 6494 | } |
| 6495 | |
| 6496 | static void |
| 6497 | Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6498 | { |
| 6499 | slotbuf[0] = 0xe05; |
| 6500 | } |
| 6501 | |
| 6502 | static void |
| 6503 | Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6504 | { |
| 6505 | slotbuf[0] = 0x405; |
| 6506 | } |
| 6507 | |
| 6508 | static void |
| 6509 | Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6510 | { |
| 6511 | slotbuf[0] = 0x505; |
| 6512 | } |
| 6513 | |
| 6514 | static void |
| 6515 | Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6516 | { |
| 6517 | slotbuf[0] = 0x305; |
| 6518 | } |
| 6519 | |
| 6520 | static void |
| 6521 | Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6522 | { |
| 6523 | slotbuf[0] = 0x705; |
| 6524 | } |
| 6525 | |
| 6526 | static void |
| 6527 | Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6528 | { |
| 6529 | slotbuf[0] = 0x605; |
| 6530 | } |
| 6531 | |
| 6532 | static void |
| 6533 | Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6534 | { |
| 6535 | slotbuf[0] = 0xf1f; |
| 6536 | } |
| 6537 | |
| 6538 | static void |
| 6539 | Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6540 | { |
| 6541 | slotbuf[0] = 0x105; |
| 6542 | } |
| 6543 | |
| 6544 | static void |
| 6545 | Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6546 | { |
| 6547 | slotbuf[0] = 0x905; |
| 6548 | } |
| 6549 | |
| 6550 | static void |
| 6551 | Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6552 | { |
| 6553 | slotbuf[0] = 0xe04; |
| 6554 | } |
| 6555 | |
| 6556 | static void |
| 6557 | Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6558 | { |
| 6559 | slotbuf[0] = 0xf04; |
| 6560 | } |
| 6561 | |
| 6562 | xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { |
| 6563 | Opcode_excw_Slot_inst_encode, 0, 0 |
| 6564 | }; |
| 6565 | |
| 6566 | xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { |
| 6567 | Opcode_rfe_Slot_inst_encode, 0, 0 |
| 6568 | }; |
| 6569 | |
| 6570 | xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { |
| 6571 | Opcode_rfde_Slot_inst_encode, 0, 0 |
| 6572 | }; |
| 6573 | |
| 6574 | xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { |
| 6575 | Opcode_syscall_Slot_inst_encode, 0, 0 |
| 6576 | }; |
| 6577 | |
| 6578 | xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { |
| 6579 | Opcode_simcall_Slot_inst_encode, 0, 0 |
| 6580 | }; |
| 6581 | |
| 6582 | xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { |
| 6583 | Opcode_call12_Slot_inst_encode, 0, 0 |
| 6584 | }; |
| 6585 | |
| 6586 | xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { |
| 6587 | Opcode_call8_Slot_inst_encode, 0, 0 |
| 6588 | }; |
| 6589 | |
| 6590 | xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { |
| 6591 | Opcode_call4_Slot_inst_encode, 0, 0 |
| 6592 | }; |
| 6593 | |
| 6594 | xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { |
| 6595 | Opcode_callx12_Slot_inst_encode, 0, 0 |
| 6596 | }; |
| 6597 | |
| 6598 | xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { |
| 6599 | Opcode_callx8_Slot_inst_encode, 0, 0 |
| 6600 | }; |
| 6601 | |
| 6602 | xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { |
| 6603 | Opcode_callx4_Slot_inst_encode, 0, 0 |
| 6604 | }; |
| 6605 | |
| 6606 | xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { |
| 6607 | Opcode_entry_Slot_inst_encode, 0, 0 |
| 6608 | }; |
| 6609 | |
| 6610 | xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { |
| 6611 | Opcode_movsp_Slot_inst_encode, 0, 0 |
| 6612 | }; |
| 6613 | |
| 6614 | xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { |
| 6615 | Opcode_rotw_Slot_inst_encode, 0, 0 |
| 6616 | }; |
| 6617 | |
| 6618 | xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { |
| 6619 | Opcode_retw_Slot_inst_encode, 0, 0 |
| 6620 | }; |
| 6621 | |
| 6622 | xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { |
| 6623 | 0, 0, Opcode_retw_n_Slot_inst16b_encode |
| 6624 | }; |
| 6625 | |
| 6626 | xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { |
| 6627 | Opcode_rfwo_Slot_inst_encode, 0, 0 |
| 6628 | }; |
| 6629 | |
| 6630 | xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { |
| 6631 | Opcode_rfwu_Slot_inst_encode, 0, 0 |
| 6632 | }; |
| 6633 | |
| 6634 | xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { |
| 6635 | Opcode_l32e_Slot_inst_encode, 0, 0 |
| 6636 | }; |
| 6637 | |
| 6638 | xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { |
| 6639 | Opcode_s32e_Slot_inst_encode, 0, 0 |
| 6640 | }; |
| 6641 | |
| 6642 | xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { |
| 6643 | Opcode_rsr_windowbase_Slot_inst_encode, 0, 0 |
| 6644 | }; |
| 6645 | |
| 6646 | xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { |
| 6647 | Opcode_wsr_windowbase_Slot_inst_encode, 0, 0 |
| 6648 | }; |
| 6649 | |
| 6650 | xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { |
| 6651 | Opcode_xsr_windowbase_Slot_inst_encode, 0, 0 |
| 6652 | }; |
| 6653 | |
| 6654 | xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { |
| 6655 | Opcode_rsr_windowstart_Slot_inst_encode, 0, 0 |
| 6656 | }; |
| 6657 | |
| 6658 | xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { |
| 6659 | Opcode_wsr_windowstart_Slot_inst_encode, 0, 0 |
| 6660 | }; |
| 6661 | |
| 6662 | xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { |
| 6663 | Opcode_xsr_windowstart_Slot_inst_encode, 0, 0 |
| 6664 | }; |
| 6665 | |
| 6666 | xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { |
| 6667 | 0, Opcode_add_n_Slot_inst16a_encode, 0 |
| 6668 | }; |
| 6669 | |
| 6670 | xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { |
| 6671 | 0, Opcode_addi_n_Slot_inst16a_encode, 0 |
| 6672 | }; |
| 6673 | |
| 6674 | xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { |
| 6675 | 0, 0, Opcode_beqz_n_Slot_inst16b_encode |
| 6676 | }; |
| 6677 | |
| 6678 | xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { |
| 6679 | 0, 0, Opcode_bnez_n_Slot_inst16b_encode |
| 6680 | }; |
| 6681 | |
| 6682 | xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { |
| 6683 | 0, 0, Opcode_ill_n_Slot_inst16b_encode |
| 6684 | }; |
| 6685 | |
| 6686 | xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { |
| 6687 | 0, Opcode_l32i_n_Slot_inst16a_encode, 0 |
| 6688 | }; |
| 6689 | |
| 6690 | xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { |
| 6691 | 0, 0, Opcode_mov_n_Slot_inst16b_encode |
| 6692 | }; |
| 6693 | |
| 6694 | xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { |
| 6695 | 0, 0, Opcode_movi_n_Slot_inst16b_encode |
| 6696 | }; |
| 6697 | |
| 6698 | xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { |
| 6699 | 0, 0, Opcode_nop_n_Slot_inst16b_encode |
| 6700 | }; |
| 6701 | |
| 6702 | xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { |
| 6703 | 0, 0, Opcode_ret_n_Slot_inst16b_encode |
| 6704 | }; |
| 6705 | |
| 6706 | xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { |
| 6707 | 0, Opcode_s32i_n_Slot_inst16a_encode, 0 |
| 6708 | }; |
| 6709 | |
| 6710 | xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { |
| 6711 | Opcode_addi_Slot_inst_encode, 0, 0 |
| 6712 | }; |
| 6713 | |
| 6714 | xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { |
| 6715 | Opcode_addmi_Slot_inst_encode, 0, 0 |
| 6716 | }; |
| 6717 | |
| 6718 | xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { |
| 6719 | Opcode_add_Slot_inst_encode, 0, 0 |
| 6720 | }; |
| 6721 | |
| 6722 | xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { |
| 6723 | Opcode_sub_Slot_inst_encode, 0, 0 |
| 6724 | }; |
| 6725 | |
| 6726 | xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { |
| 6727 | Opcode_addx2_Slot_inst_encode, 0, 0 |
| 6728 | }; |
| 6729 | |
| 6730 | xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { |
| 6731 | Opcode_addx4_Slot_inst_encode, 0, 0 |
| 6732 | }; |
| 6733 | |
| 6734 | xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { |
| 6735 | Opcode_addx8_Slot_inst_encode, 0, 0 |
| 6736 | }; |
| 6737 | |
| 6738 | xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { |
| 6739 | Opcode_subx2_Slot_inst_encode, 0, 0 |
| 6740 | }; |
| 6741 | |
| 6742 | xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { |
| 6743 | Opcode_subx4_Slot_inst_encode, 0, 0 |
| 6744 | }; |
| 6745 | |
| 6746 | xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { |
| 6747 | Opcode_subx8_Slot_inst_encode, 0, 0 |
| 6748 | }; |
| 6749 | |
| 6750 | xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { |
| 6751 | Opcode_and_Slot_inst_encode, 0, 0 |
| 6752 | }; |
| 6753 | |
| 6754 | xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { |
| 6755 | Opcode_or_Slot_inst_encode, 0, 0 |
| 6756 | }; |
| 6757 | |
| 6758 | xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { |
| 6759 | Opcode_xor_Slot_inst_encode, 0, 0 |
| 6760 | }; |
| 6761 | |
| 6762 | xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { |
| 6763 | Opcode_beqi_Slot_inst_encode, 0, 0 |
| 6764 | }; |
| 6765 | |
| 6766 | xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { |
| 6767 | Opcode_bnei_Slot_inst_encode, 0, 0 |
| 6768 | }; |
| 6769 | |
| 6770 | xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { |
| 6771 | Opcode_bgei_Slot_inst_encode, 0, 0 |
| 6772 | }; |
| 6773 | |
| 6774 | xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { |
| 6775 | Opcode_blti_Slot_inst_encode, 0, 0 |
| 6776 | }; |
| 6777 | |
| 6778 | xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { |
| 6779 | Opcode_bbci_Slot_inst_encode, 0, 0 |
| 6780 | }; |
| 6781 | |
| 6782 | xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { |
| 6783 | Opcode_bbsi_Slot_inst_encode, 0, 0 |
| 6784 | }; |
| 6785 | |
| 6786 | xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { |
| 6787 | Opcode_bgeui_Slot_inst_encode, 0, 0 |
| 6788 | }; |
| 6789 | |
| 6790 | xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { |
| 6791 | Opcode_bltui_Slot_inst_encode, 0, 0 |
| 6792 | }; |
| 6793 | |
| 6794 | xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { |
| 6795 | Opcode_beq_Slot_inst_encode, 0, 0 |
| 6796 | }; |
| 6797 | |
| 6798 | xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { |
| 6799 | Opcode_bne_Slot_inst_encode, 0, 0 |
| 6800 | }; |
| 6801 | |
| 6802 | xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { |
| 6803 | Opcode_bge_Slot_inst_encode, 0, 0 |
| 6804 | }; |
| 6805 | |
| 6806 | xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { |
| 6807 | Opcode_blt_Slot_inst_encode, 0, 0 |
| 6808 | }; |
| 6809 | |
| 6810 | xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { |
| 6811 | Opcode_bgeu_Slot_inst_encode, 0, 0 |
| 6812 | }; |
| 6813 | |
| 6814 | xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { |
| 6815 | Opcode_bltu_Slot_inst_encode, 0, 0 |
| 6816 | }; |
| 6817 | |
| 6818 | xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { |
| 6819 | Opcode_bany_Slot_inst_encode, 0, 0 |
| 6820 | }; |
| 6821 | |
| 6822 | xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { |
| 6823 | Opcode_bnone_Slot_inst_encode, 0, 0 |
| 6824 | }; |
| 6825 | |
| 6826 | xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { |
| 6827 | Opcode_ball_Slot_inst_encode, 0, 0 |
| 6828 | }; |
| 6829 | |
| 6830 | xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { |
| 6831 | Opcode_bnall_Slot_inst_encode, 0, 0 |
| 6832 | }; |
| 6833 | |
| 6834 | xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { |
| 6835 | Opcode_bbc_Slot_inst_encode, 0, 0 |
| 6836 | }; |
| 6837 | |
| 6838 | xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { |
| 6839 | Opcode_bbs_Slot_inst_encode, 0, 0 |
| 6840 | }; |
| 6841 | |
| 6842 | xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { |
| 6843 | Opcode_beqz_Slot_inst_encode, 0, 0 |
| 6844 | }; |
| 6845 | |
| 6846 | xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { |
| 6847 | Opcode_bnez_Slot_inst_encode, 0, 0 |
| 6848 | }; |
| 6849 | |
| 6850 | xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { |
| 6851 | Opcode_bgez_Slot_inst_encode, 0, 0 |
| 6852 | }; |
| 6853 | |
| 6854 | xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { |
| 6855 | Opcode_bltz_Slot_inst_encode, 0, 0 |
| 6856 | }; |
| 6857 | |
| 6858 | xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { |
| 6859 | Opcode_call0_Slot_inst_encode, 0, 0 |
| 6860 | }; |
| 6861 | |
| 6862 | xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { |
| 6863 | Opcode_callx0_Slot_inst_encode, 0, 0 |
| 6864 | }; |
| 6865 | |
| 6866 | xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { |
| 6867 | Opcode_extui_Slot_inst_encode, 0, 0 |
| 6868 | }; |
| 6869 | |
| 6870 | xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { |
| 6871 | Opcode_ill_Slot_inst_encode, 0, 0 |
| 6872 | }; |
| 6873 | |
| 6874 | xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { |
| 6875 | Opcode_j_Slot_inst_encode, 0, 0 |
| 6876 | }; |
| 6877 | |
| 6878 | xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { |
| 6879 | Opcode_jx_Slot_inst_encode, 0, 0 |
| 6880 | }; |
| 6881 | |
| 6882 | xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { |
| 6883 | Opcode_l16ui_Slot_inst_encode, 0, 0 |
| 6884 | }; |
| 6885 | |
| 6886 | xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { |
| 6887 | Opcode_l16si_Slot_inst_encode, 0, 0 |
| 6888 | }; |
| 6889 | |
| 6890 | xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { |
| 6891 | Opcode_l32i_Slot_inst_encode, 0, 0 |
| 6892 | }; |
| 6893 | |
| 6894 | xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { |
| 6895 | Opcode_l32r_Slot_inst_encode, 0, 0 |
| 6896 | }; |
| 6897 | |
| 6898 | xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { |
| 6899 | Opcode_l8ui_Slot_inst_encode, 0, 0 |
| 6900 | }; |
| 6901 | |
| 6902 | xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { |
| 6903 | Opcode_loop_Slot_inst_encode, 0, 0 |
| 6904 | }; |
| 6905 | |
| 6906 | xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { |
| 6907 | Opcode_loopnez_Slot_inst_encode, 0, 0 |
| 6908 | }; |
| 6909 | |
| 6910 | xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { |
| 6911 | Opcode_loopgtz_Slot_inst_encode, 0, 0 |
| 6912 | }; |
| 6913 | |
| 6914 | xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { |
| 6915 | Opcode_movi_Slot_inst_encode, 0, 0 |
| 6916 | }; |
| 6917 | |
| 6918 | xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { |
| 6919 | Opcode_moveqz_Slot_inst_encode, 0, 0 |
| 6920 | }; |
| 6921 | |
| 6922 | xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { |
| 6923 | Opcode_movnez_Slot_inst_encode, 0, 0 |
| 6924 | }; |
| 6925 | |
| 6926 | xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { |
| 6927 | Opcode_movltz_Slot_inst_encode, 0, 0 |
| 6928 | }; |
| 6929 | |
| 6930 | xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { |
| 6931 | Opcode_movgez_Slot_inst_encode, 0, 0 |
| 6932 | }; |
| 6933 | |
| 6934 | xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { |
| 6935 | Opcode_neg_Slot_inst_encode, 0, 0 |
| 6936 | }; |
| 6937 | |
| 6938 | xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { |
| 6939 | Opcode_abs_Slot_inst_encode, 0, 0 |
| 6940 | }; |
| 6941 | |
| 6942 | xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { |
| 6943 | Opcode_nop_Slot_inst_encode, 0, 0 |
| 6944 | }; |
| 6945 | |
| 6946 | xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { |
| 6947 | Opcode_ret_Slot_inst_encode, 0, 0 |
| 6948 | }; |
| 6949 | |
| 6950 | xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { |
| 6951 | Opcode_s16i_Slot_inst_encode, 0, 0 |
| 6952 | }; |
| 6953 | |
| 6954 | xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { |
| 6955 | Opcode_s32i_Slot_inst_encode, 0, 0 |
| 6956 | }; |
| 6957 | |
| 6958 | xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { |
| 6959 | Opcode_s8i_Slot_inst_encode, 0, 0 |
| 6960 | }; |
| 6961 | |
| 6962 | xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { |
| 6963 | Opcode_ssr_Slot_inst_encode, 0, 0 |
| 6964 | }; |
| 6965 | |
| 6966 | xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { |
| 6967 | Opcode_ssl_Slot_inst_encode, 0, 0 |
| 6968 | }; |
| 6969 | |
| 6970 | xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { |
| 6971 | Opcode_ssa8l_Slot_inst_encode, 0, 0 |
| 6972 | }; |
| 6973 | |
| 6974 | xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { |
| 6975 | Opcode_ssa8b_Slot_inst_encode, 0, 0 |
| 6976 | }; |
| 6977 | |
| 6978 | xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { |
| 6979 | Opcode_ssai_Slot_inst_encode, 0, 0 |
| 6980 | }; |
| 6981 | |
| 6982 | xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { |
| 6983 | Opcode_sll_Slot_inst_encode, 0, 0 |
| 6984 | }; |
| 6985 | |
| 6986 | xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { |
| 6987 | Opcode_src_Slot_inst_encode, 0, 0 |
| 6988 | }; |
| 6989 | |
| 6990 | xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { |
| 6991 | Opcode_srl_Slot_inst_encode, 0, 0 |
| 6992 | }; |
| 6993 | |
| 6994 | xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { |
| 6995 | Opcode_sra_Slot_inst_encode, 0, 0 |
| 6996 | }; |
| 6997 | |
| 6998 | xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { |
| 6999 | Opcode_slli_Slot_inst_encode, 0, 0 |
| 7000 | }; |
| 7001 | |
| 7002 | xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { |
| 7003 | Opcode_srai_Slot_inst_encode, 0, 0 |
| 7004 | }; |
| 7005 | |
| 7006 | xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { |
| 7007 | Opcode_srli_Slot_inst_encode, 0, 0 |
| 7008 | }; |
| 7009 | |
| 7010 | xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { |
| 7011 | Opcode_memw_Slot_inst_encode, 0, 0 |
| 7012 | }; |
| 7013 | |
| 7014 | xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { |
| 7015 | Opcode_extw_Slot_inst_encode, 0, 0 |
| 7016 | }; |
| 7017 | |
| 7018 | xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { |
| 7019 | Opcode_isync_Slot_inst_encode, 0, 0 |
| 7020 | }; |
| 7021 | |
| 7022 | xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { |
| 7023 | Opcode_rsync_Slot_inst_encode, 0, 0 |
| 7024 | }; |
| 7025 | |
| 7026 | xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { |
| 7027 | Opcode_esync_Slot_inst_encode, 0, 0 |
| 7028 | }; |
| 7029 | |
| 7030 | xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { |
| 7031 | Opcode_dsync_Slot_inst_encode, 0, 0 |
| 7032 | }; |
| 7033 | |
| 7034 | xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { |
| 7035 | Opcode_rsil_Slot_inst_encode, 0, 0 |
| 7036 | }; |
| 7037 | |
| 7038 | xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { |
| 7039 | Opcode_rsr_lend_Slot_inst_encode, 0, 0 |
| 7040 | }; |
| 7041 | |
| 7042 | xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { |
| 7043 | Opcode_wsr_lend_Slot_inst_encode, 0, 0 |
| 7044 | }; |
| 7045 | |
| 7046 | xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { |
| 7047 | Opcode_xsr_lend_Slot_inst_encode, 0, 0 |
| 7048 | }; |
| 7049 | |
| 7050 | xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { |
| 7051 | Opcode_rsr_lcount_Slot_inst_encode, 0, 0 |
| 7052 | }; |
| 7053 | |
| 7054 | xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { |
| 7055 | Opcode_wsr_lcount_Slot_inst_encode, 0, 0 |
| 7056 | }; |
| 7057 | |
| 7058 | xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { |
| 7059 | Opcode_xsr_lcount_Slot_inst_encode, 0, 0 |
| 7060 | }; |
| 7061 | |
| 7062 | xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { |
| 7063 | Opcode_rsr_lbeg_Slot_inst_encode, 0, 0 |
| 7064 | }; |
| 7065 | |
| 7066 | xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { |
| 7067 | Opcode_wsr_lbeg_Slot_inst_encode, 0, 0 |
| 7068 | }; |
| 7069 | |
| 7070 | xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { |
| 7071 | Opcode_xsr_lbeg_Slot_inst_encode, 0, 0 |
| 7072 | }; |
| 7073 | |
| 7074 | xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { |
| 7075 | Opcode_rsr_sar_Slot_inst_encode, 0, 0 |
| 7076 | }; |
| 7077 | |
| 7078 | xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { |
| 7079 | Opcode_wsr_sar_Slot_inst_encode, 0, 0 |
| 7080 | }; |
| 7081 | |
| 7082 | xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { |
| 7083 | Opcode_xsr_sar_Slot_inst_encode, 0, 0 |
| 7084 | }; |
| 7085 | |
| 7086 | xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { |
| 7087 | Opcode_rsr_litbase_Slot_inst_encode, 0, 0 |
| 7088 | }; |
| 7089 | |
| 7090 | xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { |
| 7091 | Opcode_wsr_litbase_Slot_inst_encode, 0, 0 |
| 7092 | }; |
| 7093 | |
| 7094 | xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { |
| 7095 | Opcode_xsr_litbase_Slot_inst_encode, 0, 0 |
| 7096 | }; |
| 7097 | |
| 7098 | xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = { |
| 7099 | Opcode_rsr_176_Slot_inst_encode, 0, 0 |
| 7100 | }; |
| 7101 | |
| 7102 | xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = { |
| 7103 | Opcode_rsr_208_Slot_inst_encode, 0, 0 |
| 7104 | }; |
| 7105 | |
| 7106 | xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { |
| 7107 | Opcode_rsr_ps_Slot_inst_encode, 0, 0 |
| 7108 | }; |
| 7109 | |
| 7110 | xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { |
| 7111 | Opcode_wsr_ps_Slot_inst_encode, 0, 0 |
| 7112 | }; |
| 7113 | |
| 7114 | xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { |
| 7115 | Opcode_xsr_ps_Slot_inst_encode, 0, 0 |
| 7116 | }; |
| 7117 | |
| 7118 | xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { |
| 7119 | Opcode_rsr_epc1_Slot_inst_encode, 0, 0 |
| 7120 | }; |
| 7121 | |
| 7122 | xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { |
| 7123 | Opcode_wsr_epc1_Slot_inst_encode, 0, 0 |
| 7124 | }; |
| 7125 | |
| 7126 | xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { |
| 7127 | Opcode_xsr_epc1_Slot_inst_encode, 0, 0 |
| 7128 | }; |
| 7129 | |
| 7130 | xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { |
| 7131 | Opcode_rsr_excsave1_Slot_inst_encode, 0, 0 |
| 7132 | }; |
| 7133 | |
| 7134 | xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { |
| 7135 | Opcode_wsr_excsave1_Slot_inst_encode, 0, 0 |
| 7136 | }; |
| 7137 | |
| 7138 | xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { |
| 7139 | Opcode_xsr_excsave1_Slot_inst_encode, 0, 0 |
| 7140 | }; |
| 7141 | |
| 7142 | xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { |
| 7143 | Opcode_rsr_epc2_Slot_inst_encode, 0, 0 |
| 7144 | }; |
| 7145 | |
| 7146 | xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { |
| 7147 | Opcode_wsr_epc2_Slot_inst_encode, 0, 0 |
| 7148 | }; |
| 7149 | |
| 7150 | xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { |
| 7151 | Opcode_xsr_epc2_Slot_inst_encode, 0, 0 |
| 7152 | }; |
| 7153 | |
| 7154 | xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { |
| 7155 | Opcode_rsr_excsave2_Slot_inst_encode, 0, 0 |
| 7156 | }; |
| 7157 | |
| 7158 | xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { |
| 7159 | Opcode_wsr_excsave2_Slot_inst_encode, 0, 0 |
| 7160 | }; |
| 7161 | |
| 7162 | xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { |
| 7163 | Opcode_xsr_excsave2_Slot_inst_encode, 0, 0 |
| 7164 | }; |
| 7165 | |
| 7166 | xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { |
| 7167 | Opcode_rsr_epc3_Slot_inst_encode, 0, 0 |
| 7168 | }; |
| 7169 | |
| 7170 | xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { |
| 7171 | Opcode_wsr_epc3_Slot_inst_encode, 0, 0 |
| 7172 | }; |
| 7173 | |
| 7174 | xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { |
| 7175 | Opcode_xsr_epc3_Slot_inst_encode, 0, 0 |
| 7176 | }; |
| 7177 | |
| 7178 | xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { |
| 7179 | Opcode_rsr_excsave3_Slot_inst_encode, 0, 0 |
| 7180 | }; |
| 7181 | |
| 7182 | xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { |
| 7183 | Opcode_wsr_excsave3_Slot_inst_encode, 0, 0 |
| 7184 | }; |
| 7185 | |
| 7186 | xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { |
| 7187 | Opcode_xsr_excsave3_Slot_inst_encode, 0, 0 |
| 7188 | }; |
| 7189 | |
| 7190 | xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { |
| 7191 | Opcode_rsr_epc4_Slot_inst_encode, 0, 0 |
| 7192 | }; |
| 7193 | |
| 7194 | xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { |
| 7195 | Opcode_wsr_epc4_Slot_inst_encode, 0, 0 |
| 7196 | }; |
| 7197 | |
| 7198 | xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { |
| 7199 | Opcode_xsr_epc4_Slot_inst_encode, 0, 0 |
| 7200 | }; |
| 7201 | |
| 7202 | xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { |
| 7203 | Opcode_rsr_excsave4_Slot_inst_encode, 0, 0 |
| 7204 | }; |
| 7205 | |
| 7206 | xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { |
| 7207 | Opcode_wsr_excsave4_Slot_inst_encode, 0, 0 |
| 7208 | }; |
| 7209 | |
| 7210 | xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { |
| 7211 | Opcode_xsr_excsave4_Slot_inst_encode, 0, 0 |
| 7212 | }; |
| 7213 | |
| 7214 | xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { |
| 7215 | Opcode_rsr_eps2_Slot_inst_encode, 0, 0 |
| 7216 | }; |
| 7217 | |
| 7218 | xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { |
| 7219 | Opcode_wsr_eps2_Slot_inst_encode, 0, 0 |
| 7220 | }; |
| 7221 | |
| 7222 | xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { |
| 7223 | Opcode_xsr_eps2_Slot_inst_encode, 0, 0 |
| 7224 | }; |
| 7225 | |
| 7226 | xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { |
| 7227 | Opcode_rsr_eps3_Slot_inst_encode, 0, 0 |
| 7228 | }; |
| 7229 | |
| 7230 | xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { |
| 7231 | Opcode_wsr_eps3_Slot_inst_encode, 0, 0 |
| 7232 | }; |
| 7233 | |
| 7234 | xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { |
| 7235 | Opcode_xsr_eps3_Slot_inst_encode, 0, 0 |
| 7236 | }; |
| 7237 | |
| 7238 | xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { |
| 7239 | Opcode_rsr_eps4_Slot_inst_encode, 0, 0 |
| 7240 | }; |
| 7241 | |
| 7242 | xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { |
| 7243 | Opcode_wsr_eps4_Slot_inst_encode, 0, 0 |
| 7244 | }; |
| 7245 | |
| 7246 | xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { |
| 7247 | Opcode_xsr_eps4_Slot_inst_encode, 0, 0 |
| 7248 | }; |
| 7249 | |
| 7250 | xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { |
| 7251 | Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0 |
| 7252 | }; |
| 7253 | |
| 7254 | xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { |
| 7255 | Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0 |
| 7256 | }; |
| 7257 | |
| 7258 | xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { |
| 7259 | Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0 |
| 7260 | }; |
| 7261 | |
| 7262 | xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { |
| 7263 | Opcode_rsr_depc_Slot_inst_encode, 0, 0 |
| 7264 | }; |
| 7265 | |
| 7266 | xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { |
| 7267 | Opcode_wsr_depc_Slot_inst_encode, 0, 0 |
| 7268 | }; |
| 7269 | |
| 7270 | xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { |
| 7271 | Opcode_xsr_depc_Slot_inst_encode, 0, 0 |
| 7272 | }; |
| 7273 | |
| 7274 | xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { |
| 7275 | Opcode_rsr_exccause_Slot_inst_encode, 0, 0 |
| 7276 | }; |
| 7277 | |
| 7278 | xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { |
| 7279 | Opcode_wsr_exccause_Slot_inst_encode, 0, 0 |
| 7280 | }; |
| 7281 | |
| 7282 | xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { |
| 7283 | Opcode_xsr_exccause_Slot_inst_encode, 0, 0 |
| 7284 | }; |
| 7285 | |
| 7286 | xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { |
| 7287 | Opcode_rsr_misc0_Slot_inst_encode, 0, 0 |
| 7288 | }; |
| 7289 | |
| 7290 | xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { |
| 7291 | Opcode_wsr_misc0_Slot_inst_encode, 0, 0 |
| 7292 | }; |
| 7293 | |
| 7294 | xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { |
| 7295 | Opcode_xsr_misc0_Slot_inst_encode, 0, 0 |
| 7296 | }; |
| 7297 | |
| 7298 | xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { |
| 7299 | Opcode_rsr_misc1_Slot_inst_encode, 0, 0 |
| 7300 | }; |
| 7301 | |
| 7302 | xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { |
| 7303 | Opcode_wsr_misc1_Slot_inst_encode, 0, 0 |
| 7304 | }; |
| 7305 | |
| 7306 | xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { |
| 7307 | Opcode_xsr_misc1_Slot_inst_encode, 0, 0 |
| 7308 | }; |
| 7309 | |
| 7310 | xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { |
| 7311 | Opcode_rsr_prid_Slot_inst_encode, 0, 0 |
| 7312 | }; |
| 7313 | |
| 7314 | xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { |
| 7315 | Opcode_rfi_Slot_inst_encode, 0, 0 |
| 7316 | }; |
| 7317 | |
| 7318 | xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { |
| 7319 | Opcode_waiti_Slot_inst_encode, 0, 0 |
| 7320 | }; |
| 7321 | |
| 7322 | xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { |
| 7323 | Opcode_rsr_interrupt_Slot_inst_encode, 0, 0 |
| 7324 | }; |
| 7325 | |
| 7326 | xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { |
| 7327 | Opcode_wsr_intset_Slot_inst_encode, 0, 0 |
| 7328 | }; |
| 7329 | |
| 7330 | xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { |
| 7331 | Opcode_wsr_intclear_Slot_inst_encode, 0, 0 |
| 7332 | }; |
| 7333 | |
| 7334 | xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { |
| 7335 | Opcode_rsr_intenable_Slot_inst_encode, 0, 0 |
| 7336 | }; |
| 7337 | |
| 7338 | xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { |
| 7339 | Opcode_wsr_intenable_Slot_inst_encode, 0, 0 |
| 7340 | }; |
| 7341 | |
| 7342 | xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { |
| 7343 | Opcode_xsr_intenable_Slot_inst_encode, 0, 0 |
| 7344 | }; |
| 7345 | |
| 7346 | xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { |
| 7347 | Opcode_break_Slot_inst_encode, 0, 0 |
| 7348 | }; |
| 7349 | |
| 7350 | xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { |
| 7351 | 0, 0, Opcode_break_n_Slot_inst16b_encode |
| 7352 | }; |
| 7353 | |
| 7354 | xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { |
| 7355 | Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0 |
| 7356 | }; |
| 7357 | |
| 7358 | xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { |
| 7359 | Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0 |
| 7360 | }; |
| 7361 | |
| 7362 | xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { |
| 7363 | Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0 |
| 7364 | }; |
| 7365 | |
| 7366 | xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { |
| 7367 | Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0 |
| 7368 | }; |
| 7369 | |
| 7370 | xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { |
| 7371 | Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0 |
| 7372 | }; |
| 7373 | |
| 7374 | xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { |
| 7375 | Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0 |
| 7376 | }; |
| 7377 | |
| 7378 | xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { |
| 7379 | Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0 |
| 7380 | }; |
| 7381 | |
| 7382 | xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { |
| 7383 | Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0 |
| 7384 | }; |
| 7385 | |
| 7386 | xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { |
| 7387 | Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0 |
| 7388 | }; |
| 7389 | |
| 7390 | xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { |
| 7391 | Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0 |
| 7392 | }; |
| 7393 | |
| 7394 | xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { |
| 7395 | Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0 |
| 7396 | }; |
| 7397 | |
| 7398 | xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { |
| 7399 | Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0 |
| 7400 | }; |
| 7401 | |
| 7402 | xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { |
| 7403 | Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0 |
| 7404 | }; |
| 7405 | |
| 7406 | xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { |
| 7407 | Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0 |
| 7408 | }; |
| 7409 | |
| 7410 | xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { |
| 7411 | Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0 |
| 7412 | }; |
| 7413 | |
| 7414 | xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { |
| 7415 | Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0 |
| 7416 | }; |
| 7417 | |
| 7418 | xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { |
| 7419 | Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0 |
| 7420 | }; |
| 7421 | |
| 7422 | xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { |
| 7423 | Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0 |
| 7424 | }; |
| 7425 | |
| 7426 | xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { |
| 7427 | Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0 |
| 7428 | }; |
| 7429 | |
| 7430 | xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { |
| 7431 | Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0 |
| 7432 | }; |
| 7433 | |
| 7434 | xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { |
| 7435 | Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0 |
| 7436 | }; |
| 7437 | |
| 7438 | xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { |
| 7439 | Opcode_rsr_debugcause_Slot_inst_encode, 0, 0 |
| 7440 | }; |
| 7441 | |
| 7442 | xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { |
| 7443 | Opcode_wsr_debugcause_Slot_inst_encode, 0, 0 |
| 7444 | }; |
| 7445 | |
| 7446 | xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { |
| 7447 | Opcode_xsr_debugcause_Slot_inst_encode, 0, 0 |
| 7448 | }; |
| 7449 | |
| 7450 | xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { |
| 7451 | Opcode_rsr_icount_Slot_inst_encode, 0, 0 |
| 7452 | }; |
| 7453 | |
| 7454 | xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { |
| 7455 | Opcode_wsr_icount_Slot_inst_encode, 0, 0 |
| 7456 | }; |
| 7457 | |
| 7458 | xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { |
| 7459 | Opcode_xsr_icount_Slot_inst_encode, 0, 0 |
| 7460 | }; |
| 7461 | |
| 7462 | xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { |
| 7463 | Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0 |
| 7464 | }; |
| 7465 | |
| 7466 | xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { |
| 7467 | Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0 |
| 7468 | }; |
| 7469 | |
| 7470 | xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { |
| 7471 | Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0 |
| 7472 | }; |
| 7473 | |
| 7474 | xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { |
| 7475 | Opcode_rsr_ddr_Slot_inst_encode, 0, 0 |
| 7476 | }; |
| 7477 | |
| 7478 | xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { |
| 7479 | Opcode_wsr_ddr_Slot_inst_encode, 0, 0 |
| 7480 | }; |
| 7481 | |
| 7482 | xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { |
| 7483 | Opcode_xsr_ddr_Slot_inst_encode, 0, 0 |
| 7484 | }; |
| 7485 | |
| 7486 | xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { |
| 7487 | Opcode_rfdo_Slot_inst_encode, 0, 0 |
| 7488 | }; |
| 7489 | |
| 7490 | xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { |
| 7491 | Opcode_rfdd_Slot_inst_encode, 0, 0 |
| 7492 | }; |
| 7493 | |
| 7494 | xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { |
| 7495 | Opcode_rsr_ccount_Slot_inst_encode, 0, 0 |
| 7496 | }; |
| 7497 | |
| 7498 | xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { |
| 7499 | Opcode_wsr_ccount_Slot_inst_encode, 0, 0 |
| 7500 | }; |
| 7501 | |
| 7502 | xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { |
| 7503 | Opcode_xsr_ccount_Slot_inst_encode, 0, 0 |
| 7504 | }; |
| 7505 | |
| 7506 | xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { |
| 7507 | Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0 |
| 7508 | }; |
| 7509 | |
| 7510 | xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { |
| 7511 | Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0 |
| 7512 | }; |
| 7513 | |
| 7514 | xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { |
| 7515 | Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0 |
| 7516 | }; |
| 7517 | |
| 7518 | xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { |
| 7519 | Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0 |
| 7520 | }; |
| 7521 | |
| 7522 | xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { |
| 7523 | Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0 |
| 7524 | }; |
| 7525 | |
| 7526 | xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { |
| 7527 | Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0 |
| 7528 | }; |
| 7529 | |
| 7530 | xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = { |
| 7531 | Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0 |
| 7532 | }; |
| 7533 | |
| 7534 | xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = { |
| 7535 | Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0 |
| 7536 | }; |
| 7537 | |
| 7538 | xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = { |
| 7539 | Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0 |
| 7540 | }; |
| 7541 | |
| 7542 | xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { |
| 7543 | Opcode_ipf_Slot_inst_encode, 0, 0 |
| 7544 | }; |
| 7545 | |
| 7546 | xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { |
| 7547 | Opcode_ihi_Slot_inst_encode, 0, 0 |
| 7548 | }; |
| 7549 | |
| 7550 | xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { |
| 7551 | Opcode_iii_Slot_inst_encode, 0, 0 |
| 7552 | }; |
| 7553 | |
| 7554 | xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { |
| 7555 | Opcode_lict_Slot_inst_encode, 0, 0 |
| 7556 | }; |
| 7557 | |
| 7558 | xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { |
| 7559 | Opcode_licw_Slot_inst_encode, 0, 0 |
| 7560 | }; |
| 7561 | |
| 7562 | xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { |
| 7563 | Opcode_sict_Slot_inst_encode, 0, 0 |
| 7564 | }; |
| 7565 | |
| 7566 | xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { |
| 7567 | Opcode_sicw_Slot_inst_encode, 0, 0 |
| 7568 | }; |
| 7569 | |
| 7570 | xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { |
| 7571 | Opcode_dhwb_Slot_inst_encode, 0, 0 |
| 7572 | }; |
| 7573 | |
| 7574 | xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { |
| 7575 | Opcode_dhwbi_Slot_inst_encode, 0, 0 |
| 7576 | }; |
| 7577 | |
| 7578 | xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { |
| 7579 | Opcode_diwb_Slot_inst_encode, 0, 0 |
| 7580 | }; |
| 7581 | |
| 7582 | xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { |
| 7583 | Opcode_diwbi_Slot_inst_encode, 0, 0 |
| 7584 | }; |
| 7585 | |
| 7586 | xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { |
| 7587 | Opcode_dhi_Slot_inst_encode, 0, 0 |
| 7588 | }; |
| 7589 | |
| 7590 | xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { |
| 7591 | Opcode_dii_Slot_inst_encode, 0, 0 |
| 7592 | }; |
| 7593 | |
| 7594 | xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { |
| 7595 | Opcode_dpfr_Slot_inst_encode, 0, 0 |
| 7596 | }; |
| 7597 | |
| 7598 | xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { |
| 7599 | Opcode_dpfw_Slot_inst_encode, 0, 0 |
| 7600 | }; |
| 7601 | |
| 7602 | xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { |
| 7603 | Opcode_dpfro_Slot_inst_encode, 0, 0 |
| 7604 | }; |
| 7605 | |
| 7606 | xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { |
| 7607 | Opcode_dpfwo_Slot_inst_encode, 0, 0 |
| 7608 | }; |
| 7609 | |
| 7610 | xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { |
| 7611 | Opcode_sdct_Slot_inst_encode, 0, 0 |
| 7612 | }; |
| 7613 | |
| 7614 | xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { |
| 7615 | Opcode_ldct_Slot_inst_encode, 0, 0 |
| 7616 | }; |
| 7617 | |
| 7618 | xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = { |
| 7619 | Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0 |
| 7620 | }; |
| 7621 | |
| 7622 | xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = { |
| 7623 | Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0 |
| 7624 | }; |
| 7625 | |
| 7626 | xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = { |
| 7627 | Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0 |
| 7628 | }; |
| 7629 | |
| 7630 | xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = { |
| 7631 | Opcode_rsr_rasid_Slot_inst_encode, 0, 0 |
| 7632 | }; |
| 7633 | |
| 7634 | xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = { |
| 7635 | Opcode_wsr_rasid_Slot_inst_encode, 0, 0 |
| 7636 | }; |
| 7637 | |
| 7638 | xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = { |
| 7639 | Opcode_xsr_rasid_Slot_inst_encode, 0, 0 |
| 7640 | }; |
| 7641 | |
| 7642 | xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = { |
| 7643 | Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0 |
| 7644 | }; |
| 7645 | |
| 7646 | xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = { |
| 7647 | Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0 |
| 7648 | }; |
| 7649 | |
| 7650 | xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = { |
| 7651 | Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0 |
| 7652 | }; |
| 7653 | |
| 7654 | xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = { |
| 7655 | Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0 |
| 7656 | }; |
| 7657 | |
| 7658 | xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = { |
| 7659 | Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0 |
| 7660 | }; |
| 7661 | |
| 7662 | xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = { |
| 7663 | Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0 |
| 7664 | }; |
| 7665 | |
| 7666 | xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { |
| 7667 | Opcode_idtlb_Slot_inst_encode, 0, 0 |
| 7668 | }; |
| 7669 | |
| 7670 | xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { |
| 7671 | Opcode_pdtlb_Slot_inst_encode, 0, 0 |
| 7672 | }; |
| 7673 | |
| 7674 | xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { |
| 7675 | Opcode_rdtlb0_Slot_inst_encode, 0, 0 |
| 7676 | }; |
| 7677 | |
| 7678 | xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { |
| 7679 | Opcode_rdtlb1_Slot_inst_encode, 0, 0 |
| 7680 | }; |
| 7681 | |
| 7682 | xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { |
| 7683 | Opcode_wdtlb_Slot_inst_encode, 0, 0 |
| 7684 | }; |
| 7685 | |
| 7686 | xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { |
| 7687 | Opcode_iitlb_Slot_inst_encode, 0, 0 |
| 7688 | }; |
| 7689 | |
| 7690 | xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { |
| 7691 | Opcode_pitlb_Slot_inst_encode, 0, 0 |
| 7692 | }; |
| 7693 | |
| 7694 | xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { |
| 7695 | Opcode_ritlb0_Slot_inst_encode, 0, 0 |
| 7696 | }; |
| 7697 | |
| 7698 | xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { |
| 7699 | Opcode_ritlb1_Slot_inst_encode, 0, 0 |
| 7700 | }; |
| 7701 | |
| 7702 | xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { |
| 7703 | Opcode_witlb_Slot_inst_encode, 0, 0 |
| 7704 | }; |
| 7705 | |
| 7706 | xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = { |
| 7707 | Opcode_ldpte_Slot_inst_encode, 0, 0 |
| 7708 | }; |
| 7709 | |
| 7710 | xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = { |
| 7711 | Opcode_hwwitlba_Slot_inst_encode, 0, 0 |
| 7712 | }; |
| 7713 | |
| 7714 | xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = { |
| 7715 | Opcode_hwwdtlba_Slot_inst_encode, 0, 0 |
| 7716 | }; |
| 7717 | |
| 7718 | xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { |
| 7719 | Opcode_nsa_Slot_inst_encode, 0, 0 |
| 7720 | }; |
| 7721 | |
| 7722 | xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { |
| 7723 | Opcode_nsau_Slot_inst_encode, 0, 0 |
| 7724 | }; |
| 7725 | |
| 7726 | \f |
| 7727 | /* Opcode table. */ |
| 7728 | |
| 7729 | static xtensa_opcode_internal opcodes[] = { |
| 7730 | { "excw", 0 /* xt_iclass_excw */, |
| 7731 | 0, |
| 7732 | Opcode_excw_encode_fns, 0, 0 }, |
| 7733 | { "rfe", 1 /* xt_iclass_rfe */, |
| 7734 | XTENSA_OPCODE_IS_JUMP, |
| 7735 | Opcode_rfe_encode_fns, 0, 0 }, |
| 7736 | { "rfde", 2 /* xt_iclass_rfde */, |
| 7737 | XTENSA_OPCODE_IS_JUMP, |
| 7738 | Opcode_rfde_encode_fns, 0, 0 }, |
| 7739 | { "syscall", 3 /* xt_iclass_syscall */, |
| 7740 | 0, |
| 7741 | Opcode_syscall_encode_fns, 0, 0 }, |
| 7742 | { "simcall", 4 /* xt_iclass_simcall */, |
| 7743 | 0, |
| 7744 | Opcode_simcall_encode_fns, 0, 0 }, |
| 7745 | { "call12", 5 /* xt_iclass_call12 */, |
| 7746 | XTENSA_OPCODE_IS_CALL, |
| 7747 | Opcode_call12_encode_fns, 0, 0 }, |
| 7748 | { "call8", 6 /* xt_iclass_call8 */, |
| 7749 | XTENSA_OPCODE_IS_CALL, |
| 7750 | Opcode_call8_encode_fns, 0, 0 }, |
| 7751 | { "call4", 7 /* xt_iclass_call4 */, |
| 7752 | XTENSA_OPCODE_IS_CALL, |
| 7753 | Opcode_call4_encode_fns, 0, 0 }, |
| 7754 | { "callx12", 8 /* xt_iclass_callx12 */, |
| 7755 | XTENSA_OPCODE_IS_CALL, |
| 7756 | Opcode_callx12_encode_fns, 0, 0 }, |
| 7757 | { "callx8", 9 /* xt_iclass_callx8 */, |
| 7758 | XTENSA_OPCODE_IS_CALL, |
| 7759 | Opcode_callx8_encode_fns, 0, 0 }, |
| 7760 | { "callx4", 10 /* xt_iclass_callx4 */, |
| 7761 | XTENSA_OPCODE_IS_CALL, |
| 7762 | Opcode_callx4_encode_fns, 0, 0 }, |
| 7763 | { "entry", 11 /* xt_iclass_entry */, |
| 7764 | 0, |
| 7765 | Opcode_entry_encode_fns, 0, 0 }, |
| 7766 | { "movsp", 12 /* xt_iclass_movsp */, |
| 7767 | 0, |
| 7768 | Opcode_movsp_encode_fns, 0, 0 }, |
| 7769 | { "rotw", 13 /* xt_iclass_rotw */, |
| 7770 | 0, |
| 7771 | Opcode_rotw_encode_fns, 0, 0 }, |
| 7772 | { "retw", 14 /* xt_iclass_retw */, |
| 7773 | XTENSA_OPCODE_IS_JUMP, |
| 7774 | Opcode_retw_encode_fns, 0, 0 }, |
| 7775 | { "retw.n", 14 /* xt_iclass_retw */, |
| 7776 | XTENSA_OPCODE_IS_JUMP, |
| 7777 | Opcode_retw_n_encode_fns, 0, 0 }, |
| 7778 | { "rfwo", 15 /* xt_iclass_rfwou */, |
| 7779 | XTENSA_OPCODE_IS_JUMP, |
| 7780 | Opcode_rfwo_encode_fns, 0, 0 }, |
| 7781 | { "rfwu", 15 /* xt_iclass_rfwou */, |
| 7782 | XTENSA_OPCODE_IS_JUMP, |
| 7783 | Opcode_rfwu_encode_fns, 0, 0 }, |
| 7784 | { "l32e", 16 /* xt_iclass_l32e */, |
| 7785 | 0, |
| 7786 | Opcode_l32e_encode_fns, 0, 0 }, |
| 7787 | { "s32e", 17 /* xt_iclass_s32e */, |
| 7788 | 0, |
| 7789 | Opcode_s32e_encode_fns, 0, 0 }, |
| 7790 | { "rsr.windowbase", 18 /* xt_iclass_rsr.windowbase */, |
| 7791 | 0, |
| 7792 | Opcode_rsr_windowbase_encode_fns, 0, 0 }, |
| 7793 | { "wsr.windowbase", 19 /* xt_iclass_wsr.windowbase */, |
| 7794 | 0, |
| 7795 | Opcode_wsr_windowbase_encode_fns, 0, 0 }, |
| 7796 | { "xsr.windowbase", 20 /* xt_iclass_xsr.windowbase */, |
| 7797 | 0, |
| 7798 | Opcode_xsr_windowbase_encode_fns, 0, 0 }, |
| 7799 | { "rsr.windowstart", 21 /* xt_iclass_rsr.windowstart */, |
| 7800 | 0, |
| 7801 | Opcode_rsr_windowstart_encode_fns, 0, 0 }, |
| 7802 | { "wsr.windowstart", 22 /* xt_iclass_wsr.windowstart */, |
| 7803 | 0, |
| 7804 | Opcode_wsr_windowstart_encode_fns, 0, 0 }, |
| 7805 | { "xsr.windowstart", 23 /* xt_iclass_xsr.windowstart */, |
| 7806 | 0, |
| 7807 | Opcode_xsr_windowstart_encode_fns, 0, 0 }, |
| 7808 | { "add.n", 24 /* xt_iclass_add.n */, |
| 7809 | 0, |
| 7810 | Opcode_add_n_encode_fns, 0, 0 }, |
| 7811 | { "addi.n", 25 /* xt_iclass_addi.n */, |
| 7812 | 0, |
| 7813 | Opcode_addi_n_encode_fns, 0, 0 }, |
| 7814 | { "beqz.n", 26 /* xt_iclass_bz6 */, |
| 7815 | XTENSA_OPCODE_IS_BRANCH, |
| 7816 | Opcode_beqz_n_encode_fns, 0, 0 }, |
| 7817 | { "bnez.n", 26 /* xt_iclass_bz6 */, |
| 7818 | XTENSA_OPCODE_IS_BRANCH, |
| 7819 | Opcode_bnez_n_encode_fns, 0, 0 }, |
| 7820 | { "ill.n", 27 /* xt_iclass_ill.n */, |
| 7821 | 0, |
| 7822 | Opcode_ill_n_encode_fns, 0, 0 }, |
| 7823 | { "l32i.n", 28 /* xt_iclass_loadi4 */, |
| 7824 | 0, |
| 7825 | Opcode_l32i_n_encode_fns, 0, 0 }, |
| 7826 | { "mov.n", 29 /* xt_iclass_mov.n */, |
| 7827 | 0, |
| 7828 | Opcode_mov_n_encode_fns, 0, 0 }, |
| 7829 | { "movi.n", 30 /* xt_iclass_movi.n */, |
| 7830 | 0, |
| 7831 | Opcode_movi_n_encode_fns, 0, 0 }, |
| 7832 | { "nop.n", 31 /* xt_iclass_nopn */, |
| 7833 | 0, |
| 7834 | Opcode_nop_n_encode_fns, 0, 0 }, |
| 7835 | { "ret.n", 32 /* xt_iclass_retn */, |
| 7836 | XTENSA_OPCODE_IS_JUMP, |
| 7837 | Opcode_ret_n_encode_fns, 0, 0 }, |
| 7838 | { "s32i.n", 33 /* xt_iclass_storei4 */, |
| 7839 | 0, |
| 7840 | Opcode_s32i_n_encode_fns, 0, 0 }, |
| 7841 | { "addi", 34 /* xt_iclass_addi */, |
| 7842 | 0, |
| 7843 | Opcode_addi_encode_fns, 0, 0 }, |
| 7844 | { "addmi", 35 /* xt_iclass_addmi */, |
| 7845 | 0, |
| 7846 | Opcode_addmi_encode_fns, 0, 0 }, |
| 7847 | { "add", 36 /* xt_iclass_addsub */, |
| 7848 | 0, |
| 7849 | Opcode_add_encode_fns, 0, 0 }, |
| 7850 | { "sub", 36 /* xt_iclass_addsub */, |
| 7851 | 0, |
| 7852 | Opcode_sub_encode_fns, 0, 0 }, |
| 7853 | { "addx2", 36 /* xt_iclass_addsub */, |
| 7854 | 0, |
| 7855 | Opcode_addx2_encode_fns, 0, 0 }, |
| 7856 | { "addx4", 36 /* xt_iclass_addsub */, |
| 7857 | 0, |
| 7858 | Opcode_addx4_encode_fns, 0, 0 }, |
| 7859 | { "addx8", 36 /* xt_iclass_addsub */, |
| 7860 | 0, |
| 7861 | Opcode_addx8_encode_fns, 0, 0 }, |
| 7862 | { "subx2", 36 /* xt_iclass_addsub */, |
| 7863 | 0, |
| 7864 | Opcode_subx2_encode_fns, 0, 0 }, |
| 7865 | { "subx4", 36 /* xt_iclass_addsub */, |
| 7866 | 0, |
| 7867 | Opcode_subx4_encode_fns, 0, 0 }, |
| 7868 | { "subx8", 36 /* xt_iclass_addsub */, |
| 7869 | 0, |
| 7870 | Opcode_subx8_encode_fns, 0, 0 }, |
| 7871 | { "and", 37 /* xt_iclass_bit */, |
| 7872 | 0, |
| 7873 | Opcode_and_encode_fns, 0, 0 }, |
| 7874 | { "or", 37 /* xt_iclass_bit */, |
| 7875 | 0, |
| 7876 | Opcode_or_encode_fns, 0, 0 }, |
| 7877 | { "xor", 37 /* xt_iclass_bit */, |
| 7878 | 0, |
| 7879 | Opcode_xor_encode_fns, 0, 0 }, |
| 7880 | { "beqi", 38 /* xt_iclass_bsi8 */, |
| 7881 | XTENSA_OPCODE_IS_BRANCH, |
| 7882 | Opcode_beqi_encode_fns, 0, 0 }, |
| 7883 | { "bnei", 38 /* xt_iclass_bsi8 */, |
| 7884 | XTENSA_OPCODE_IS_BRANCH, |
| 7885 | Opcode_bnei_encode_fns, 0, 0 }, |
| 7886 | { "bgei", 38 /* xt_iclass_bsi8 */, |
| 7887 | XTENSA_OPCODE_IS_BRANCH, |
| 7888 | Opcode_bgei_encode_fns, 0, 0 }, |
| 7889 | { "blti", 38 /* xt_iclass_bsi8 */, |
| 7890 | XTENSA_OPCODE_IS_BRANCH, |
| 7891 | Opcode_blti_encode_fns, 0, 0 }, |
| 7892 | { "bbci", 39 /* xt_iclass_bsi8b */, |
| 7893 | XTENSA_OPCODE_IS_BRANCH, |
| 7894 | Opcode_bbci_encode_fns, 0, 0 }, |
| 7895 | { "bbsi", 39 /* xt_iclass_bsi8b */, |
| 7896 | XTENSA_OPCODE_IS_BRANCH, |
| 7897 | Opcode_bbsi_encode_fns, 0, 0 }, |
| 7898 | { "bgeui", 40 /* xt_iclass_bsi8u */, |
| 7899 | XTENSA_OPCODE_IS_BRANCH, |
| 7900 | Opcode_bgeui_encode_fns, 0, 0 }, |
| 7901 | { "bltui", 40 /* xt_iclass_bsi8u */, |
| 7902 | XTENSA_OPCODE_IS_BRANCH, |
| 7903 | Opcode_bltui_encode_fns, 0, 0 }, |
| 7904 | { "beq", 41 /* xt_iclass_bst8 */, |
| 7905 | XTENSA_OPCODE_IS_BRANCH, |
| 7906 | Opcode_beq_encode_fns, 0, 0 }, |
| 7907 | { "bne", 41 /* xt_iclass_bst8 */, |
| 7908 | XTENSA_OPCODE_IS_BRANCH, |
| 7909 | Opcode_bne_encode_fns, 0, 0 }, |
| 7910 | { "bge", 41 /* xt_iclass_bst8 */, |
| 7911 | XTENSA_OPCODE_IS_BRANCH, |
| 7912 | Opcode_bge_encode_fns, 0, 0 }, |
| 7913 | { "blt", 41 /* xt_iclass_bst8 */, |
| 7914 | XTENSA_OPCODE_IS_BRANCH, |
| 7915 | Opcode_blt_encode_fns, 0, 0 }, |
| 7916 | { "bgeu", 41 /* xt_iclass_bst8 */, |
| 7917 | XTENSA_OPCODE_IS_BRANCH, |
| 7918 | Opcode_bgeu_encode_fns, 0, 0 }, |
| 7919 | { "bltu", 41 /* xt_iclass_bst8 */, |
| 7920 | XTENSA_OPCODE_IS_BRANCH, |
| 7921 | Opcode_bltu_encode_fns, 0, 0 }, |
| 7922 | { "bany", 41 /* xt_iclass_bst8 */, |
| 7923 | XTENSA_OPCODE_IS_BRANCH, |
| 7924 | Opcode_bany_encode_fns, 0, 0 }, |
| 7925 | { "bnone", 41 /* xt_iclass_bst8 */, |
| 7926 | XTENSA_OPCODE_IS_BRANCH, |
| 7927 | Opcode_bnone_encode_fns, 0, 0 }, |
| 7928 | { "ball", 41 /* xt_iclass_bst8 */, |
| 7929 | XTENSA_OPCODE_IS_BRANCH, |
| 7930 | Opcode_ball_encode_fns, 0, 0 }, |
| 7931 | { "bnall", 41 /* xt_iclass_bst8 */, |
| 7932 | XTENSA_OPCODE_IS_BRANCH, |
| 7933 | Opcode_bnall_encode_fns, 0, 0 }, |
| 7934 | { "bbc", 41 /* xt_iclass_bst8 */, |
| 7935 | XTENSA_OPCODE_IS_BRANCH, |
| 7936 | Opcode_bbc_encode_fns, 0, 0 }, |
| 7937 | { "bbs", 41 /* xt_iclass_bst8 */, |
| 7938 | XTENSA_OPCODE_IS_BRANCH, |
| 7939 | Opcode_bbs_encode_fns, 0, 0 }, |
| 7940 | { "beqz", 42 /* xt_iclass_bsz12 */, |
| 7941 | XTENSA_OPCODE_IS_BRANCH, |
| 7942 | Opcode_beqz_encode_fns, 0, 0 }, |
| 7943 | { "bnez", 42 /* xt_iclass_bsz12 */, |
| 7944 | XTENSA_OPCODE_IS_BRANCH, |
| 7945 | Opcode_bnez_encode_fns, 0, 0 }, |
| 7946 | { "bgez", 42 /* xt_iclass_bsz12 */, |
| 7947 | XTENSA_OPCODE_IS_BRANCH, |
| 7948 | Opcode_bgez_encode_fns, 0, 0 }, |
| 7949 | { "bltz", 42 /* xt_iclass_bsz12 */, |
| 7950 | XTENSA_OPCODE_IS_BRANCH, |
| 7951 | Opcode_bltz_encode_fns, 0, 0 }, |
| 7952 | { "call0", 43 /* xt_iclass_call0 */, |
| 7953 | XTENSA_OPCODE_IS_CALL, |
| 7954 | Opcode_call0_encode_fns, 0, 0 }, |
| 7955 | { "callx0", 44 /* xt_iclass_callx0 */, |
| 7956 | XTENSA_OPCODE_IS_CALL, |
| 7957 | Opcode_callx0_encode_fns, 0, 0 }, |
| 7958 | { "extui", 45 /* xt_iclass_exti */, |
| 7959 | 0, |
| 7960 | Opcode_extui_encode_fns, 0, 0 }, |
| 7961 | { "ill", 46 /* xt_iclass_ill */, |
| 7962 | 0, |
| 7963 | Opcode_ill_encode_fns, 0, 0 }, |
| 7964 | { "j", 47 /* xt_iclass_jump */, |
| 7965 | XTENSA_OPCODE_IS_JUMP, |
| 7966 | Opcode_j_encode_fns, 0, 0 }, |
| 7967 | { "jx", 48 /* xt_iclass_jumpx */, |
| 7968 | XTENSA_OPCODE_IS_JUMP, |
| 7969 | Opcode_jx_encode_fns, 0, 0 }, |
| 7970 | { "l16ui", 49 /* xt_iclass_l16ui */, |
| 7971 | 0, |
| 7972 | Opcode_l16ui_encode_fns, 0, 0 }, |
| 7973 | { "l16si", 50 /* xt_iclass_l16si */, |
| 7974 | 0, |
| 7975 | Opcode_l16si_encode_fns, 0, 0 }, |
| 7976 | { "l32i", 51 /* xt_iclass_l32i */, |
| 7977 | 0, |
| 7978 | Opcode_l32i_encode_fns, 0, 0 }, |
| 7979 | { "l32r", 52 /* xt_iclass_l32r */, |
| 7980 | 0, |
| 7981 | Opcode_l32r_encode_fns, 0, 0 }, |
| 7982 | { "l8ui", 53 /* xt_iclass_l8i */, |
| 7983 | 0, |
| 7984 | Opcode_l8ui_encode_fns, 0, 0 }, |
| 7985 | { "loop", 54 /* xt_iclass_loop */, |
| 7986 | XTENSA_OPCODE_IS_LOOP, |
| 7987 | Opcode_loop_encode_fns, 0, 0 }, |
| 7988 | { "loopnez", 55 /* xt_iclass_loopz */, |
| 7989 | XTENSA_OPCODE_IS_LOOP, |
| 7990 | Opcode_loopnez_encode_fns, 0, 0 }, |
| 7991 | { "loopgtz", 55 /* xt_iclass_loopz */, |
| 7992 | XTENSA_OPCODE_IS_LOOP, |
| 7993 | Opcode_loopgtz_encode_fns, 0, 0 }, |
| 7994 | { "movi", 56 /* xt_iclass_movi */, |
| 7995 | 0, |
| 7996 | Opcode_movi_encode_fns, 0, 0 }, |
| 7997 | { "moveqz", 57 /* xt_iclass_movz */, |
| 7998 | 0, |
| 7999 | Opcode_moveqz_encode_fns, 0, 0 }, |
| 8000 | { "movnez", 57 /* xt_iclass_movz */, |
| 8001 | 0, |
| 8002 | Opcode_movnez_encode_fns, 0, 0 }, |
| 8003 | { "movltz", 57 /* xt_iclass_movz */, |
| 8004 | 0, |
| 8005 | Opcode_movltz_encode_fns, 0, 0 }, |
| 8006 | { "movgez", 57 /* xt_iclass_movz */, |
| 8007 | 0, |
| 8008 | Opcode_movgez_encode_fns, 0, 0 }, |
| 8009 | { "neg", 58 /* xt_iclass_neg */, |
| 8010 | 0, |
| 8011 | Opcode_neg_encode_fns, 0, 0 }, |
| 8012 | { "abs", 58 /* xt_iclass_neg */, |
| 8013 | 0, |
| 8014 | Opcode_abs_encode_fns, 0, 0 }, |
| 8015 | { "nop", 59 /* xt_iclass_nop */, |
| 8016 | 0, |
| 8017 | Opcode_nop_encode_fns, 0, 0 }, |
| 8018 | { "ret", 60 /* xt_iclass_return */, |
| 8019 | XTENSA_OPCODE_IS_JUMP, |
| 8020 | Opcode_ret_encode_fns, 0, 0 }, |
| 8021 | { "s16i", 61 /* xt_iclass_s16i */, |
| 8022 | 0, |
| 8023 | Opcode_s16i_encode_fns, 0, 0 }, |
| 8024 | { "s32i", 62 /* xt_iclass_s32i */, |
| 8025 | 0, |
| 8026 | Opcode_s32i_encode_fns, 0, 0 }, |
| 8027 | { "s8i", 63 /* xt_iclass_s8i */, |
| 8028 | 0, |
| 8029 | Opcode_s8i_encode_fns, 0, 0 }, |
| 8030 | { "ssr", 64 /* xt_iclass_sar */, |
| 8031 | 0, |
| 8032 | Opcode_ssr_encode_fns, 0, 0 }, |
| 8033 | { "ssl", 64 /* xt_iclass_sar */, |
| 8034 | 0, |
| 8035 | Opcode_ssl_encode_fns, 0, 0 }, |
| 8036 | { "ssa8l", 64 /* xt_iclass_sar */, |
| 8037 | 0, |
| 8038 | Opcode_ssa8l_encode_fns, 0, 0 }, |
| 8039 | { "ssa8b", 64 /* xt_iclass_sar */, |
| 8040 | 0, |
| 8041 | Opcode_ssa8b_encode_fns, 0, 0 }, |
| 8042 | { "ssai", 65 /* xt_iclass_sari */, |
| 8043 | 0, |
| 8044 | Opcode_ssai_encode_fns, 0, 0 }, |
| 8045 | { "sll", 66 /* xt_iclass_shifts */, |
| 8046 | 0, |
| 8047 | Opcode_sll_encode_fns, 0, 0 }, |
| 8048 | { "src", 67 /* xt_iclass_shiftst */, |
| 8049 | 0, |
| 8050 | Opcode_src_encode_fns, 0, 0 }, |
| 8051 | { "srl", 68 /* xt_iclass_shiftt */, |
| 8052 | 0, |
| 8053 | Opcode_srl_encode_fns, 0, 0 }, |
| 8054 | { "sra", 68 /* xt_iclass_shiftt */, |
| 8055 | 0, |
| 8056 | Opcode_sra_encode_fns, 0, 0 }, |
| 8057 | { "slli", 69 /* xt_iclass_slli */, |
| 8058 | 0, |
| 8059 | Opcode_slli_encode_fns, 0, 0 }, |
| 8060 | { "srai", 70 /* xt_iclass_srai */, |
| 8061 | 0, |
| 8062 | Opcode_srai_encode_fns, 0, 0 }, |
| 8063 | { "srli", 71 /* xt_iclass_srli */, |
| 8064 | 0, |
| 8065 | Opcode_srli_encode_fns, 0, 0 }, |
| 8066 | { "memw", 72 /* xt_iclass_memw */, |
| 8067 | 0, |
| 8068 | Opcode_memw_encode_fns, 0, 0 }, |
| 8069 | { "extw", 73 /* xt_iclass_extw */, |
| 8070 | 0, |
| 8071 | Opcode_extw_encode_fns, 0, 0 }, |
| 8072 | { "isync", 74 /* xt_iclass_isync */, |
| 8073 | 0, |
| 8074 | Opcode_isync_encode_fns, 0, 0 }, |
| 8075 | { "rsync", 75 /* xt_iclass_sync */, |
| 8076 | 0, |
| 8077 | Opcode_rsync_encode_fns, 0, 0 }, |
| 8078 | { "esync", 75 /* xt_iclass_sync */, |
| 8079 | 0, |
| 8080 | Opcode_esync_encode_fns, 0, 0 }, |
| 8081 | { "dsync", 75 /* xt_iclass_sync */, |
| 8082 | 0, |
| 8083 | Opcode_dsync_encode_fns, 0, 0 }, |
| 8084 | { "rsil", 76 /* xt_iclass_rsil */, |
| 8085 | 0, |
| 8086 | Opcode_rsil_encode_fns, 0, 0 }, |
| 8087 | { "rsr.lend", 77 /* xt_iclass_rsr.lend */, |
| 8088 | 0, |
| 8089 | Opcode_rsr_lend_encode_fns, 0, 0 }, |
| 8090 | { "wsr.lend", 78 /* xt_iclass_wsr.lend */, |
| 8091 | 0, |
| 8092 | Opcode_wsr_lend_encode_fns, 0, 0 }, |
| 8093 | { "xsr.lend", 79 /* xt_iclass_xsr.lend */, |
| 8094 | 0, |
| 8095 | Opcode_xsr_lend_encode_fns, 0, 0 }, |
| 8096 | { "rsr.lcount", 80 /* xt_iclass_rsr.lcount */, |
| 8097 | 0, |
| 8098 | Opcode_rsr_lcount_encode_fns, 0, 0 }, |
| 8099 | { "wsr.lcount", 81 /* xt_iclass_wsr.lcount */, |
| 8100 | 0, |
| 8101 | Opcode_wsr_lcount_encode_fns, 0, 0 }, |
| 8102 | { "xsr.lcount", 82 /* xt_iclass_xsr.lcount */, |
| 8103 | 0, |
| 8104 | Opcode_xsr_lcount_encode_fns, 0, 0 }, |
| 8105 | { "rsr.lbeg", 83 /* xt_iclass_rsr.lbeg */, |
| 8106 | 0, |
| 8107 | Opcode_rsr_lbeg_encode_fns, 0, 0 }, |
| 8108 | { "wsr.lbeg", 84 /* xt_iclass_wsr.lbeg */, |
| 8109 | 0, |
| 8110 | Opcode_wsr_lbeg_encode_fns, 0, 0 }, |
| 8111 | { "xsr.lbeg", 85 /* xt_iclass_xsr.lbeg */, |
| 8112 | 0, |
| 8113 | Opcode_xsr_lbeg_encode_fns, 0, 0 }, |
| 8114 | { "rsr.sar", 86 /* xt_iclass_rsr.sar */, |
| 8115 | 0, |
| 8116 | Opcode_rsr_sar_encode_fns, 0, 0 }, |
| 8117 | { "wsr.sar", 87 /* xt_iclass_wsr.sar */, |
| 8118 | 0, |
| 8119 | Opcode_wsr_sar_encode_fns, 0, 0 }, |
| 8120 | { "xsr.sar", 88 /* xt_iclass_xsr.sar */, |
| 8121 | 0, |
| 8122 | Opcode_xsr_sar_encode_fns, 0, 0 }, |
| 8123 | { "rsr.litbase", 89 /* xt_iclass_rsr.litbase */, |
| 8124 | 0, |
| 8125 | Opcode_rsr_litbase_encode_fns, 0, 0 }, |
| 8126 | { "wsr.litbase", 90 /* xt_iclass_wsr.litbase */, |
| 8127 | 0, |
| 8128 | Opcode_wsr_litbase_encode_fns, 0, 0 }, |
| 8129 | { "xsr.litbase", 91 /* xt_iclass_xsr.litbase */, |
| 8130 | 0, |
| 8131 | Opcode_xsr_litbase_encode_fns, 0, 0 }, |
| 8132 | { "rsr.176", 92 /* xt_iclass_rsr.176 */, |
| 8133 | 0, |
| 8134 | Opcode_rsr_176_encode_fns, 0, 0 }, |
| 8135 | { "rsr.208", 93 /* xt_iclass_rsr.208 */, |
| 8136 | 0, |
| 8137 | Opcode_rsr_208_encode_fns, 0, 0 }, |
| 8138 | { "rsr.ps", 94 /* xt_iclass_rsr.ps */, |
| 8139 | 0, |
| 8140 | Opcode_rsr_ps_encode_fns, 0, 0 }, |
| 8141 | { "wsr.ps", 95 /* xt_iclass_wsr.ps */, |
| 8142 | 0, |
| 8143 | Opcode_wsr_ps_encode_fns, 0, 0 }, |
| 8144 | { "xsr.ps", 96 /* xt_iclass_xsr.ps */, |
| 8145 | 0, |
| 8146 | Opcode_xsr_ps_encode_fns, 0, 0 }, |
| 8147 | { "rsr.epc1", 97 /* xt_iclass_rsr.epc1 */, |
| 8148 | 0, |
| 8149 | Opcode_rsr_epc1_encode_fns, 0, 0 }, |
| 8150 | { "wsr.epc1", 98 /* xt_iclass_wsr.epc1 */, |
| 8151 | 0, |
| 8152 | Opcode_wsr_epc1_encode_fns, 0, 0 }, |
| 8153 | { "xsr.epc1", 99 /* xt_iclass_xsr.epc1 */, |
| 8154 | 0, |
| 8155 | Opcode_xsr_epc1_encode_fns, 0, 0 }, |
| 8156 | { "rsr.excsave1", 100 /* xt_iclass_rsr.excsave1 */, |
| 8157 | 0, |
| 8158 | Opcode_rsr_excsave1_encode_fns, 0, 0 }, |
| 8159 | { "wsr.excsave1", 101 /* xt_iclass_wsr.excsave1 */, |
| 8160 | 0, |
| 8161 | Opcode_wsr_excsave1_encode_fns, 0, 0 }, |
| 8162 | { "xsr.excsave1", 102 /* xt_iclass_xsr.excsave1 */, |
| 8163 | 0, |
| 8164 | Opcode_xsr_excsave1_encode_fns, 0, 0 }, |
| 8165 | { "rsr.epc2", 103 /* xt_iclass_rsr.epc2 */, |
| 8166 | 0, |
| 8167 | Opcode_rsr_epc2_encode_fns, 0, 0 }, |
| 8168 | { "wsr.epc2", 104 /* xt_iclass_wsr.epc2 */, |
| 8169 | 0, |
| 8170 | Opcode_wsr_epc2_encode_fns, 0, 0 }, |
| 8171 | { "xsr.epc2", 105 /* xt_iclass_xsr.epc2 */, |
| 8172 | 0, |
| 8173 | Opcode_xsr_epc2_encode_fns, 0, 0 }, |
| 8174 | { "rsr.excsave2", 106 /* xt_iclass_rsr.excsave2 */, |
| 8175 | 0, |
| 8176 | Opcode_rsr_excsave2_encode_fns, 0, 0 }, |
| 8177 | { "wsr.excsave2", 107 /* xt_iclass_wsr.excsave2 */, |
| 8178 | 0, |
| 8179 | Opcode_wsr_excsave2_encode_fns, 0, 0 }, |
| 8180 | { "xsr.excsave2", 108 /* xt_iclass_xsr.excsave2 */, |
| 8181 | 0, |
| 8182 | Opcode_xsr_excsave2_encode_fns, 0, 0 }, |
| 8183 | { "rsr.epc3", 109 /* xt_iclass_rsr.epc3 */, |
| 8184 | 0, |
| 8185 | Opcode_rsr_epc3_encode_fns, 0, 0 }, |
| 8186 | { "wsr.epc3", 110 /* xt_iclass_wsr.epc3 */, |
| 8187 | 0, |
| 8188 | Opcode_wsr_epc3_encode_fns, 0, 0 }, |
| 8189 | { "xsr.epc3", 111 /* xt_iclass_xsr.epc3 */, |
| 8190 | 0, |
| 8191 | Opcode_xsr_epc3_encode_fns, 0, 0 }, |
| 8192 | { "rsr.excsave3", 112 /* xt_iclass_rsr.excsave3 */, |
| 8193 | 0, |
| 8194 | Opcode_rsr_excsave3_encode_fns, 0, 0 }, |
| 8195 | { "wsr.excsave3", 113 /* xt_iclass_wsr.excsave3 */, |
| 8196 | 0, |
| 8197 | Opcode_wsr_excsave3_encode_fns, 0, 0 }, |
| 8198 | { "xsr.excsave3", 114 /* xt_iclass_xsr.excsave3 */, |
| 8199 | 0, |
| 8200 | Opcode_xsr_excsave3_encode_fns, 0, 0 }, |
| 8201 | { "rsr.epc4", 115 /* xt_iclass_rsr.epc4 */, |
| 8202 | 0, |
| 8203 | Opcode_rsr_epc4_encode_fns, 0, 0 }, |
| 8204 | { "wsr.epc4", 116 /* xt_iclass_wsr.epc4 */, |
| 8205 | 0, |
| 8206 | Opcode_wsr_epc4_encode_fns, 0, 0 }, |
| 8207 | { "xsr.epc4", 117 /* xt_iclass_xsr.epc4 */, |
| 8208 | 0, |
| 8209 | Opcode_xsr_epc4_encode_fns, 0, 0 }, |
| 8210 | { "rsr.excsave4", 118 /* xt_iclass_rsr.excsave4 */, |
| 8211 | 0, |
| 8212 | Opcode_rsr_excsave4_encode_fns, 0, 0 }, |
| 8213 | { "wsr.excsave4", 119 /* xt_iclass_wsr.excsave4 */, |
| 8214 | 0, |
| 8215 | Opcode_wsr_excsave4_encode_fns, 0, 0 }, |
| 8216 | { "xsr.excsave4", 120 /* xt_iclass_xsr.excsave4 */, |
| 8217 | 0, |
| 8218 | Opcode_xsr_excsave4_encode_fns, 0, 0 }, |
| 8219 | { "rsr.eps2", 121 /* xt_iclass_rsr.eps2 */, |
| 8220 | 0, |
| 8221 | Opcode_rsr_eps2_encode_fns, 0, 0 }, |
| 8222 | { "wsr.eps2", 122 /* xt_iclass_wsr.eps2 */, |
| 8223 | 0, |
| 8224 | Opcode_wsr_eps2_encode_fns, 0, 0 }, |
| 8225 | { "xsr.eps2", 123 /* xt_iclass_xsr.eps2 */, |
| 8226 | 0, |
| 8227 | Opcode_xsr_eps2_encode_fns, 0, 0 }, |
| 8228 | { "rsr.eps3", 124 /* xt_iclass_rsr.eps3 */, |
| 8229 | 0, |
| 8230 | Opcode_rsr_eps3_encode_fns, 0, 0 }, |
| 8231 | { "wsr.eps3", 125 /* xt_iclass_wsr.eps3 */, |
| 8232 | 0, |
| 8233 | Opcode_wsr_eps3_encode_fns, 0, 0 }, |
| 8234 | { "xsr.eps3", 126 /* xt_iclass_xsr.eps3 */, |
| 8235 | 0, |
| 8236 | Opcode_xsr_eps3_encode_fns, 0, 0 }, |
| 8237 | { "rsr.eps4", 127 /* xt_iclass_rsr.eps4 */, |
| 8238 | 0, |
| 8239 | Opcode_rsr_eps4_encode_fns, 0, 0 }, |
| 8240 | { "wsr.eps4", 128 /* xt_iclass_wsr.eps4 */, |
| 8241 | 0, |
| 8242 | Opcode_wsr_eps4_encode_fns, 0, 0 }, |
| 8243 | { "xsr.eps4", 129 /* xt_iclass_xsr.eps4 */, |
| 8244 | 0, |
| 8245 | Opcode_xsr_eps4_encode_fns, 0, 0 }, |
| 8246 | { "rsr.excvaddr", 130 /* xt_iclass_rsr.excvaddr */, |
| 8247 | 0, |
| 8248 | Opcode_rsr_excvaddr_encode_fns, 0, 0 }, |
| 8249 | { "wsr.excvaddr", 131 /* xt_iclass_wsr.excvaddr */, |
| 8250 | 0, |
| 8251 | Opcode_wsr_excvaddr_encode_fns, 0, 0 }, |
| 8252 | { "xsr.excvaddr", 132 /* xt_iclass_xsr.excvaddr */, |
| 8253 | 0, |
| 8254 | Opcode_xsr_excvaddr_encode_fns, 0, 0 }, |
| 8255 | { "rsr.depc", 133 /* xt_iclass_rsr.depc */, |
| 8256 | 0, |
| 8257 | Opcode_rsr_depc_encode_fns, 0, 0 }, |
| 8258 | { "wsr.depc", 134 /* xt_iclass_wsr.depc */, |
| 8259 | 0, |
| 8260 | Opcode_wsr_depc_encode_fns, 0, 0 }, |
| 8261 | { "xsr.depc", 135 /* xt_iclass_xsr.depc */, |
| 8262 | 0, |
| 8263 | Opcode_xsr_depc_encode_fns, 0, 0 }, |
| 8264 | { "rsr.exccause", 136 /* xt_iclass_rsr.exccause */, |
| 8265 | 0, |
| 8266 | Opcode_rsr_exccause_encode_fns, 0, 0 }, |
| 8267 | { "wsr.exccause", 137 /* xt_iclass_wsr.exccause */, |
| 8268 | 0, |
| 8269 | Opcode_wsr_exccause_encode_fns, 0, 0 }, |
| 8270 | { "xsr.exccause", 138 /* xt_iclass_xsr.exccause */, |
| 8271 | 0, |
| 8272 | Opcode_xsr_exccause_encode_fns, 0, 0 }, |
| 8273 | { "rsr.misc0", 139 /* xt_iclass_rsr.misc0 */, |
| 8274 | 0, |
| 8275 | Opcode_rsr_misc0_encode_fns, 0, 0 }, |
| 8276 | { "wsr.misc0", 140 /* xt_iclass_wsr.misc0 */, |
| 8277 | 0, |
| 8278 | Opcode_wsr_misc0_encode_fns, 0, 0 }, |
| 8279 | { "xsr.misc0", 141 /* xt_iclass_xsr.misc0 */, |
| 8280 | 0, |
| 8281 | Opcode_xsr_misc0_encode_fns, 0, 0 }, |
| 8282 | { "rsr.misc1", 142 /* xt_iclass_rsr.misc1 */, |
| 8283 | 0, |
| 8284 | Opcode_rsr_misc1_encode_fns, 0, 0 }, |
| 8285 | { "wsr.misc1", 143 /* xt_iclass_wsr.misc1 */, |
| 8286 | 0, |
| 8287 | Opcode_wsr_misc1_encode_fns, 0, 0 }, |
| 8288 | { "xsr.misc1", 144 /* xt_iclass_xsr.misc1 */, |
| 8289 | 0, |
| 8290 | Opcode_xsr_misc1_encode_fns, 0, 0 }, |
| 8291 | { "rsr.prid", 145 /* xt_iclass_rsr.prid */, |
| 8292 | 0, |
| 8293 | Opcode_rsr_prid_encode_fns, 0, 0 }, |
| 8294 | { "rfi", 146 /* xt_iclass_rfi */, |
| 8295 | XTENSA_OPCODE_IS_JUMP, |
| 8296 | Opcode_rfi_encode_fns, 0, 0 }, |
| 8297 | { "waiti", 147 /* xt_iclass_wait */, |
| 8298 | 0, |
| 8299 | Opcode_waiti_encode_fns, 0, 0 }, |
| 8300 | { "rsr.interrupt", 148 /* xt_iclass_rsr.interrupt */, |
| 8301 | 0, |
| 8302 | Opcode_rsr_interrupt_encode_fns, 0, 0 }, |
| 8303 | { "wsr.intset", 149 /* xt_iclass_wsr.intset */, |
| 8304 | 0, |
| 8305 | Opcode_wsr_intset_encode_fns, 0, 0 }, |
| 8306 | { "wsr.intclear", 150 /* xt_iclass_wsr.intclear */, |
| 8307 | 0, |
| 8308 | Opcode_wsr_intclear_encode_fns, 0, 0 }, |
| 8309 | { "rsr.intenable", 151 /* xt_iclass_rsr.intenable */, |
| 8310 | 0, |
| 8311 | Opcode_rsr_intenable_encode_fns, 0, 0 }, |
| 8312 | { "wsr.intenable", 152 /* xt_iclass_wsr.intenable */, |
| 8313 | 0, |
| 8314 | Opcode_wsr_intenable_encode_fns, 0, 0 }, |
| 8315 | { "xsr.intenable", 153 /* xt_iclass_xsr.intenable */, |
| 8316 | 0, |
| 8317 | Opcode_xsr_intenable_encode_fns, 0, 0 }, |
| 8318 | { "break", 154 /* xt_iclass_break */, |
| 8319 | 0, |
| 8320 | Opcode_break_encode_fns, 0, 0 }, |
| 8321 | { "break.n", 155 /* xt_iclass_break.n */, |
| 8322 | 0, |
| 8323 | Opcode_break_n_encode_fns, 0, 0 }, |
| 8324 | { "rsr.dbreaka0", 156 /* xt_iclass_rsr.dbreaka0 */, |
| 8325 | 0, |
| 8326 | Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, |
| 8327 | { "wsr.dbreaka0", 157 /* xt_iclass_wsr.dbreaka0 */, |
| 8328 | 0, |
| 8329 | Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, |
| 8330 | { "xsr.dbreaka0", 158 /* xt_iclass_xsr.dbreaka0 */, |
| 8331 | 0, |
| 8332 | Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, |
| 8333 | { "rsr.dbreakc0", 159 /* xt_iclass_rsr.dbreakc0 */, |
| 8334 | 0, |
| 8335 | Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, |
| 8336 | { "wsr.dbreakc0", 160 /* xt_iclass_wsr.dbreakc0 */, |
| 8337 | 0, |
| 8338 | Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, |
| 8339 | { "xsr.dbreakc0", 161 /* xt_iclass_xsr.dbreakc0 */, |
| 8340 | 0, |
| 8341 | Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, |
| 8342 | { "rsr.dbreaka1", 162 /* xt_iclass_rsr.dbreaka1 */, |
| 8343 | 0, |
| 8344 | Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, |
| 8345 | { "wsr.dbreaka1", 163 /* xt_iclass_wsr.dbreaka1 */, |
| 8346 | 0, |
| 8347 | Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, |
| 8348 | { "xsr.dbreaka1", 164 /* xt_iclass_xsr.dbreaka1 */, |
| 8349 | 0, |
| 8350 | Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, |
| 8351 | { "rsr.dbreakc1", 165 /* xt_iclass_rsr.dbreakc1 */, |
| 8352 | 0, |
| 8353 | Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, |
| 8354 | { "wsr.dbreakc1", 166 /* xt_iclass_wsr.dbreakc1 */, |
| 8355 | 0, |
| 8356 | Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, |
| 8357 | { "xsr.dbreakc1", 167 /* xt_iclass_xsr.dbreakc1 */, |
| 8358 | 0, |
| 8359 | Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, |
| 8360 | { "rsr.ibreaka0", 168 /* xt_iclass_rsr.ibreaka0 */, |
| 8361 | 0, |
| 8362 | Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, |
| 8363 | { "wsr.ibreaka0", 169 /* xt_iclass_wsr.ibreaka0 */, |
| 8364 | 0, |
| 8365 | Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, |
| 8366 | { "xsr.ibreaka0", 170 /* xt_iclass_xsr.ibreaka0 */, |
| 8367 | 0, |
| 8368 | Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, |
| 8369 | { "rsr.ibreaka1", 171 /* xt_iclass_rsr.ibreaka1 */, |
| 8370 | 0, |
| 8371 | Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, |
| 8372 | { "wsr.ibreaka1", 172 /* xt_iclass_wsr.ibreaka1 */, |
| 8373 | 0, |
| 8374 | Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, |
| 8375 | { "xsr.ibreaka1", 173 /* xt_iclass_xsr.ibreaka1 */, |
| 8376 | 0, |
| 8377 | Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, |
| 8378 | { "rsr.ibreakenable", 174 /* xt_iclass_rsr.ibreakenable */, |
| 8379 | 0, |
| 8380 | Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, |
| 8381 | { "wsr.ibreakenable", 175 /* xt_iclass_wsr.ibreakenable */, |
| 8382 | 0, |
| 8383 | Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, |
| 8384 | { "xsr.ibreakenable", 176 /* xt_iclass_xsr.ibreakenable */, |
| 8385 | 0, |
| 8386 | Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, |
| 8387 | { "rsr.debugcause", 177 /* xt_iclass_rsr.debugcause */, |
| 8388 | 0, |
| 8389 | Opcode_rsr_debugcause_encode_fns, 0, 0 }, |
| 8390 | { "wsr.debugcause", 178 /* xt_iclass_wsr.debugcause */, |
| 8391 | 0, |
| 8392 | Opcode_wsr_debugcause_encode_fns, 0, 0 }, |
| 8393 | { "xsr.debugcause", 179 /* xt_iclass_xsr.debugcause */, |
| 8394 | 0, |
| 8395 | Opcode_xsr_debugcause_encode_fns, 0, 0 }, |
| 8396 | { "rsr.icount", 180 /* xt_iclass_rsr.icount */, |
| 8397 | 0, |
| 8398 | Opcode_rsr_icount_encode_fns, 0, 0 }, |
| 8399 | { "wsr.icount", 181 /* xt_iclass_wsr.icount */, |
| 8400 | 0, |
| 8401 | Opcode_wsr_icount_encode_fns, 0, 0 }, |
| 8402 | { "xsr.icount", 182 /* xt_iclass_xsr.icount */, |
| 8403 | 0, |
| 8404 | Opcode_xsr_icount_encode_fns, 0, 0 }, |
| 8405 | { "rsr.icountlevel", 183 /* xt_iclass_rsr.icountlevel */, |
| 8406 | 0, |
| 8407 | Opcode_rsr_icountlevel_encode_fns, 0, 0 }, |
| 8408 | { "wsr.icountlevel", 184 /* xt_iclass_wsr.icountlevel */, |
| 8409 | 0, |
| 8410 | Opcode_wsr_icountlevel_encode_fns, 0, 0 }, |
| 8411 | { "xsr.icountlevel", 185 /* xt_iclass_xsr.icountlevel */, |
| 8412 | 0, |
| 8413 | Opcode_xsr_icountlevel_encode_fns, 0, 0 }, |
| 8414 | { "rsr.ddr", 186 /* xt_iclass_rsr.ddr */, |
| 8415 | 0, |
| 8416 | Opcode_rsr_ddr_encode_fns, 0, 0 }, |
| 8417 | { "wsr.ddr", 187 /* xt_iclass_wsr.ddr */, |
| 8418 | 0, |
| 8419 | Opcode_wsr_ddr_encode_fns, 0, 0 }, |
| 8420 | { "xsr.ddr", 188 /* xt_iclass_xsr.ddr */, |
| 8421 | 0, |
| 8422 | Opcode_xsr_ddr_encode_fns, 0, 0 }, |
| 8423 | { "rfdo", 189 /* xt_iclass_rfdo */, |
| 8424 | XTENSA_OPCODE_IS_JUMP, |
| 8425 | Opcode_rfdo_encode_fns, 0, 0 }, |
| 8426 | { "rfdd", 190 /* xt_iclass_rfdd */, |
| 8427 | XTENSA_OPCODE_IS_JUMP, |
| 8428 | Opcode_rfdd_encode_fns, 0, 0 }, |
| 8429 | { "rsr.ccount", 191 /* xt_iclass_rsr.ccount */, |
| 8430 | 0, |
| 8431 | Opcode_rsr_ccount_encode_fns, 0, 0 }, |
| 8432 | { "wsr.ccount", 192 /* xt_iclass_wsr.ccount */, |
| 8433 | 0, |
| 8434 | Opcode_wsr_ccount_encode_fns, 0, 0 }, |
| 8435 | { "xsr.ccount", 193 /* xt_iclass_xsr.ccount */, |
| 8436 | 0, |
| 8437 | Opcode_xsr_ccount_encode_fns, 0, 0 }, |
| 8438 | { "rsr.ccompare0", 194 /* xt_iclass_rsr.ccompare0 */, |
| 8439 | 0, |
| 8440 | Opcode_rsr_ccompare0_encode_fns, 0, 0 }, |
| 8441 | { "wsr.ccompare0", 195 /* xt_iclass_wsr.ccompare0 */, |
| 8442 | 0, |
| 8443 | Opcode_wsr_ccompare0_encode_fns, 0, 0 }, |
| 8444 | { "xsr.ccompare0", 196 /* xt_iclass_xsr.ccompare0 */, |
| 8445 | 0, |
| 8446 | Opcode_xsr_ccompare0_encode_fns, 0, 0 }, |
| 8447 | { "rsr.ccompare1", 197 /* xt_iclass_rsr.ccompare1 */, |
| 8448 | 0, |
| 8449 | Opcode_rsr_ccompare1_encode_fns, 0, 0 }, |
| 8450 | { "wsr.ccompare1", 198 /* xt_iclass_wsr.ccompare1 */, |
| 8451 | 0, |
| 8452 | Opcode_wsr_ccompare1_encode_fns, 0, 0 }, |
| 8453 | { "xsr.ccompare1", 199 /* xt_iclass_xsr.ccompare1 */, |
| 8454 | 0, |
| 8455 | Opcode_xsr_ccompare1_encode_fns, 0, 0 }, |
| 8456 | { "rsr.ccompare2", 200 /* xt_iclass_rsr.ccompare2 */, |
| 8457 | 0, |
| 8458 | Opcode_rsr_ccompare2_encode_fns, 0, 0 }, |
| 8459 | { "wsr.ccompare2", 201 /* xt_iclass_wsr.ccompare2 */, |
| 8460 | 0, |
| 8461 | Opcode_wsr_ccompare2_encode_fns, 0, 0 }, |
| 8462 | { "xsr.ccompare2", 202 /* xt_iclass_xsr.ccompare2 */, |
| 8463 | 0, |
| 8464 | Opcode_xsr_ccompare2_encode_fns, 0, 0 }, |
| 8465 | { "ipf", 203 /* xt_iclass_icache */, |
| 8466 | 0, |
| 8467 | Opcode_ipf_encode_fns, 0, 0 }, |
| 8468 | { "ihi", 203 /* xt_iclass_icache */, |
| 8469 | 0, |
| 8470 | Opcode_ihi_encode_fns, 0, 0 }, |
| 8471 | { "iii", 204 /* xt_iclass_icache_inv */, |
| 8472 | 0, |
| 8473 | Opcode_iii_encode_fns, 0, 0 }, |
| 8474 | { "lict", 205 /* xt_iclass_licx */, |
| 8475 | 0, |
| 8476 | Opcode_lict_encode_fns, 0, 0 }, |
| 8477 | { "licw", 205 /* xt_iclass_licx */, |
| 8478 | 0, |
| 8479 | Opcode_licw_encode_fns, 0, 0 }, |
| 8480 | { "sict", 206 /* xt_iclass_sicx */, |
| 8481 | 0, |
| 8482 | Opcode_sict_encode_fns, 0, 0 }, |
| 8483 | { "sicw", 206 /* xt_iclass_sicx */, |
| 8484 | 0, |
| 8485 | Opcode_sicw_encode_fns, 0, 0 }, |
| 8486 | { "dhwb", 207 /* xt_iclass_dcache */, |
| 8487 | 0, |
| 8488 | Opcode_dhwb_encode_fns, 0, 0 }, |
| 8489 | { "dhwbi", 207 /* xt_iclass_dcache */, |
| 8490 | 0, |
| 8491 | Opcode_dhwbi_encode_fns, 0, 0 }, |
| 8492 | { "diwb", 208 /* xt_iclass_dcache_ind */, |
| 8493 | 0, |
| 8494 | Opcode_diwb_encode_fns, 0, 0 }, |
| 8495 | { "diwbi", 208 /* xt_iclass_dcache_ind */, |
| 8496 | 0, |
| 8497 | Opcode_diwbi_encode_fns, 0, 0 }, |
| 8498 | { "dhi", 209 /* xt_iclass_dcache_inv */, |
| 8499 | 0, |
| 8500 | Opcode_dhi_encode_fns, 0, 0 }, |
| 8501 | { "dii", 209 /* xt_iclass_dcache_inv */, |
| 8502 | 0, |
| 8503 | Opcode_dii_encode_fns, 0, 0 }, |
| 8504 | { "dpfr", 210 /* xt_iclass_dpf */, |
| 8505 | 0, |
| 8506 | Opcode_dpfr_encode_fns, 0, 0 }, |
| 8507 | { "dpfw", 210 /* xt_iclass_dpf */, |
| 8508 | 0, |
| 8509 | Opcode_dpfw_encode_fns, 0, 0 }, |
| 8510 | { "dpfro", 210 /* xt_iclass_dpf */, |
| 8511 | 0, |
| 8512 | Opcode_dpfro_encode_fns, 0, 0 }, |
| 8513 | { "dpfwo", 210 /* xt_iclass_dpf */, |
| 8514 | 0, |
| 8515 | Opcode_dpfwo_encode_fns, 0, 0 }, |
| 8516 | { "sdct", 211 /* xt_iclass_sdct */, |
| 8517 | 0, |
| 8518 | Opcode_sdct_encode_fns, 0, 0 }, |
| 8519 | { "ldct", 212 /* xt_iclass_ldct */, |
| 8520 | 0, |
| 8521 | Opcode_ldct_encode_fns, 0, 0 }, |
| 8522 | { "wsr.ptevaddr", 213 /* xt_iclass_wsr.ptevaddr */, |
| 8523 | 0, |
| 8524 | Opcode_wsr_ptevaddr_encode_fns, 0, 0 }, |
| 8525 | { "rsr.ptevaddr", 214 /* xt_iclass_rsr.ptevaddr */, |
| 8526 | 0, |
| 8527 | Opcode_rsr_ptevaddr_encode_fns, 0, 0 }, |
| 8528 | { "xsr.ptevaddr", 215 /* xt_iclass_xsr.ptevaddr */, |
| 8529 | 0, |
| 8530 | Opcode_xsr_ptevaddr_encode_fns, 0, 0 }, |
| 8531 | { "rsr.rasid", 216 /* xt_iclass_rsr.rasid */, |
| 8532 | 0, |
| 8533 | Opcode_rsr_rasid_encode_fns, 0, 0 }, |
| 8534 | { "wsr.rasid", 217 /* xt_iclass_wsr.rasid */, |
| 8535 | 0, |
| 8536 | Opcode_wsr_rasid_encode_fns, 0, 0 }, |
| 8537 | { "xsr.rasid", 218 /* xt_iclass_xsr.rasid */, |
| 8538 | 0, |
| 8539 | Opcode_xsr_rasid_encode_fns, 0, 0 }, |
| 8540 | { "rsr.itlbcfg", 219 /* xt_iclass_rsr.itlbcfg */, |
| 8541 | 0, |
| 8542 | Opcode_rsr_itlbcfg_encode_fns, 0, 0 }, |
| 8543 | { "wsr.itlbcfg", 220 /* xt_iclass_wsr.itlbcfg */, |
| 8544 | 0, |
| 8545 | Opcode_wsr_itlbcfg_encode_fns, 0, 0 }, |
| 8546 | { "xsr.itlbcfg", 221 /* xt_iclass_xsr.itlbcfg */, |
| 8547 | 0, |
| 8548 | Opcode_xsr_itlbcfg_encode_fns, 0, 0 }, |
| 8549 | { "rsr.dtlbcfg", 222 /* xt_iclass_rsr.dtlbcfg */, |
| 8550 | 0, |
| 8551 | Opcode_rsr_dtlbcfg_encode_fns, 0, 0 }, |
| 8552 | { "wsr.dtlbcfg", 223 /* xt_iclass_wsr.dtlbcfg */, |
| 8553 | 0, |
| 8554 | Opcode_wsr_dtlbcfg_encode_fns, 0, 0 }, |
| 8555 | { "xsr.dtlbcfg", 224 /* xt_iclass_xsr.dtlbcfg */, |
| 8556 | 0, |
| 8557 | Opcode_xsr_dtlbcfg_encode_fns, 0, 0 }, |
| 8558 | { "idtlb", 225 /* xt_iclass_idtlb */, |
| 8559 | 0, |
| 8560 | Opcode_idtlb_encode_fns, 0, 0 }, |
| 8561 | { "pdtlb", 226 /* xt_iclass_rdtlb */, |
| 8562 | 0, |
| 8563 | Opcode_pdtlb_encode_fns, 0, 0 }, |
| 8564 | { "rdtlb0", 226 /* xt_iclass_rdtlb */, |
| 8565 | 0, |
| 8566 | Opcode_rdtlb0_encode_fns, 0, 0 }, |
| 8567 | { "rdtlb1", 226 /* xt_iclass_rdtlb */, |
| 8568 | 0, |
| 8569 | Opcode_rdtlb1_encode_fns, 0, 0 }, |
| 8570 | { "wdtlb", 227 /* xt_iclass_wdtlb */, |
| 8571 | 0, |
| 8572 | Opcode_wdtlb_encode_fns, 0, 0 }, |
| 8573 | { "iitlb", 228 /* xt_iclass_iitlb */, |
| 8574 | 0, |
| 8575 | Opcode_iitlb_encode_fns, 0, 0 }, |
| 8576 | { "pitlb", 229 /* xt_iclass_ritlb */, |
| 8577 | 0, |
| 8578 | Opcode_pitlb_encode_fns, 0, 0 }, |
| 8579 | { "ritlb0", 229 /* xt_iclass_ritlb */, |
| 8580 | 0, |
| 8581 | Opcode_ritlb0_encode_fns, 0, 0 }, |
| 8582 | { "ritlb1", 229 /* xt_iclass_ritlb */, |
| 8583 | 0, |
| 8584 | Opcode_ritlb1_encode_fns, 0, 0 }, |
| 8585 | { "witlb", 230 /* xt_iclass_witlb */, |
| 8586 | 0, |
| 8587 | Opcode_witlb_encode_fns, 0, 0 }, |
| 8588 | { "ldpte", 231 /* xt_iclass_ldpte */, |
| 8589 | 0, |
| 8590 | Opcode_ldpte_encode_fns, 0, 0 }, |
| 8591 | { "hwwitlba", 232 /* xt_iclass_hwwitlba */, |
| 8592 | XTENSA_OPCODE_IS_BRANCH, |
| 8593 | Opcode_hwwitlba_encode_fns, 0, 0 }, |
| 8594 | { "hwwdtlba", 233 /* xt_iclass_hwwdtlba */, |
| 8595 | 0, |
| 8596 | Opcode_hwwdtlba_encode_fns, 0, 0 }, |
| 8597 | { "nsa", 234 /* xt_iclass_nsa */, |
| 8598 | 0, |
| 8599 | Opcode_nsa_encode_fns, 0, 0 }, |
| 8600 | { "nsau", 234 /* xt_iclass_nsa */, |
| 8601 | 0, |
| 8602 | Opcode_nsau_encode_fns, 0, 0 } |
| 8603 | }; |
| 8604 | |
| 8605 | \f |
| 8606 | /* Slot-specific opcode decode functions. */ |
| 8607 | |
| 8608 | static int |
| 8609 | Slot_inst_decode (const xtensa_insnbuf insn) |
| 8610 | { |
| 8611 | switch (Field_op0_Slot_inst_get (insn)) |
| 8612 | { |
| 8613 | case 0: |
| 8614 | switch (Field_op1_Slot_inst_get (insn)) |
| 8615 | { |
| 8616 | case 0: |
| 8617 | switch (Field_op2_Slot_inst_get (insn)) |
| 8618 | { |
| 8619 | case 0: |
| 8620 | switch (Field_r_Slot_inst_get (insn)) |
| 8621 | { |
| 8622 | case 0: |
| 8623 | switch (Field_m_Slot_inst_get (insn)) |
| 8624 | { |
| 8625 | case 0: |
| 8626 | if (Field_s_Slot_inst_get (insn) == 0 && |
| 8627 | Field_n_Slot_inst_get (insn) == 0) |
| 8628 | return 77; /* ill */ |
| 8629 | break; |
| 8630 | case 2: |
| 8631 | switch (Field_n_Slot_inst_get (insn)) |
| 8632 | { |
| 8633 | case 0: |
| 8634 | return 96; /* ret */ |
| 8635 | case 1: |
| 8636 | return 14; /* retw */ |
| 8637 | case 2: |
| 8638 | return 79; /* jx */ |
| 8639 | } |
| 8640 | break; |
| 8641 | case 3: |
| 8642 | switch (Field_n_Slot_inst_get (insn)) |
| 8643 | { |
| 8644 | case 0: |
| 8645 | return 75; /* callx0 */ |
| 8646 | case 1: |
| 8647 | return 10; /* callx4 */ |
| 8648 | case 2: |
| 8649 | return 9; /* callx8 */ |
| 8650 | case 3: |
| 8651 | return 8; /* callx12 */ |
| 8652 | } |
| 8653 | break; |
| 8654 | } |
| 8655 | break; |
| 8656 | case 1: |
| 8657 | return 12; /* movsp */ |
| 8658 | case 2: |
| 8659 | if (Field_s_Slot_inst_get (insn) == 0) |
| 8660 | { |
| 8661 | switch (Field_t_Slot_inst_get (insn)) |
| 8662 | { |
| 8663 | case 0: |
| 8664 | return 114; /* isync */ |
| 8665 | case 1: |
| 8666 | return 115; /* rsync */ |
| 8667 | case 2: |
| 8668 | return 116; /* esync */ |
| 8669 | case 3: |
| 8670 | return 117; /* dsync */ |
| 8671 | case 8: |
| 8672 | return 0; /* excw */ |
| 8673 | case 12: |
| 8674 | return 112; /* memw */ |
| 8675 | case 13: |
| 8676 | return 113; /* extw */ |
| 8677 | case 15: |
| 8678 | return 95; /* nop */ |
| 8679 | } |
| 8680 | } |
| 8681 | break; |
| 8682 | case 3: |
| 8683 | switch (Field_t_Slot_inst_get (insn)) |
| 8684 | { |
| 8685 | case 0: |
| 8686 | switch (Field_s_Slot_inst_get (insn)) |
| 8687 | { |
| 8688 | case 0: |
| 8689 | return 1; /* rfe */ |
| 8690 | case 2: |
| 8691 | return 2; /* rfde */ |
| 8692 | case 4: |
| 8693 | return 16; /* rfwo */ |
| 8694 | case 5: |
| 8695 | return 17; /* rfwu */ |
| 8696 | } |
| 8697 | break; |
| 8698 | case 1: |
| 8699 | return 188; /* rfi */ |
| 8700 | } |
| 8701 | break; |
| 8702 | case 4: |
| 8703 | return 196; /* break */ |
| 8704 | case 5: |
| 8705 | switch (Field_s_Slot_inst_get (insn)) |
| 8706 | { |
| 8707 | case 0: |
| 8708 | if (Field_t_Slot_inst_get (insn) == 0) |
| 8709 | return 3; /* syscall */ |
| 8710 | break; |
| 8711 | case 1: |
| 8712 | if (Field_t_Slot_inst_get (insn) == 0) |
| 8713 | return 4; /* simcall */ |
| 8714 | break; |
| 8715 | } |
| 8716 | break; |
| 8717 | case 6: |
| 8718 | return 118; /* rsil */ |
| 8719 | case 7: |
| 8720 | if (Field_t_Slot_inst_get (insn) == 0) |
| 8721 | return 189; /* waiti */ |
| 8722 | break; |
| 8723 | } |
| 8724 | break; |
| 8725 | case 1: |
| 8726 | return 47; /* and */ |
| 8727 | case 2: |
| 8728 | return 48; /* or */ |
| 8729 | case 3: |
| 8730 | return 49; /* xor */ |
| 8731 | case 4: |
| 8732 | switch (Field_r_Slot_inst_get (insn)) |
| 8733 | { |
| 8734 | case 0: |
| 8735 | if (Field_t_Slot_inst_get (insn) == 0) |
| 8736 | return 100; /* ssr */ |
| 8737 | break; |
| 8738 | case 1: |
| 8739 | if (Field_t_Slot_inst_get (insn) == 0) |
| 8740 | return 101; /* ssl */ |
| 8741 | break; |
| 8742 | case 2: |
| 8743 | if (Field_t_Slot_inst_get (insn) == 0) |
| 8744 | return 102; /* ssa8l */ |
| 8745 | break; |
| 8746 | case 3: |
| 8747 | if (Field_t_Slot_inst_get (insn) == 0) |
| 8748 | return 103; /* ssa8b */ |
| 8749 | break; |
| 8750 | case 4: |
| 8751 | if (Field_thi3_Slot_inst_get (insn) == 0) |
| 8752 | return 104; /* ssai */ |
| 8753 | break; |
| 8754 | case 8: |
| 8755 | if (Field_s_Slot_inst_get (insn) == 0) |
| 8756 | return 13; /* rotw */ |
| 8757 | break; |
| 8758 | case 14: |
| 8759 | return 289; /* nsa */ |
| 8760 | case 15: |
| 8761 | return 290; /* nsau */ |
| 8762 | } |
| 8763 | break; |
| 8764 | case 5: |
| 8765 | switch (Field_r_Slot_inst_get (insn)) |
| 8766 | { |
| 8767 | case 1: |
| 8768 | return 287; /* hwwitlba */ |
| 8769 | case 3: |
| 8770 | return 283; /* ritlb0 */ |
| 8771 | case 4: |
| 8772 | if (Field_t_Slot_inst_get (insn) == 0) |
| 8773 | return 281; /* iitlb */ |
| 8774 | break; |
| 8775 | case 5: |
| 8776 | return 282; /* pitlb */ |
| 8777 | case 6: |
| 8778 | return 285; /* witlb */ |
| 8779 | case 7: |
| 8780 | return 284; /* ritlb1 */ |
| 8781 | case 9: |
| 8782 | return 288; /* hwwdtlba */ |
| 8783 | case 11: |
| 8784 | return 278; /* rdtlb0 */ |
| 8785 | case 12: |
| 8786 | if (Field_t_Slot_inst_get (insn) == 0) |
| 8787 | return 276; /* idtlb */ |
| 8788 | break; |
| 8789 | case 13: |
| 8790 | return 277; /* pdtlb */ |
| 8791 | case 14: |
| 8792 | return 280; /* wdtlb */ |
| 8793 | case 15: |
| 8794 | return 279; /* rdtlb1 */ |
| 8795 | } |
| 8796 | break; |
| 8797 | case 6: |
| 8798 | switch (Field_s_Slot_inst_get (insn)) |
| 8799 | { |
| 8800 | case 0: |
| 8801 | return 93; /* neg */ |
| 8802 | case 1: |
| 8803 | return 94; /* abs */ |
| 8804 | } |
| 8805 | break; |
| 8806 | case 8: |
| 8807 | return 39; /* add */ |
| 8808 | case 9: |
| 8809 | return 41; /* addx2 */ |
| 8810 | case 10: |
| 8811 | return 42; /* addx4 */ |
| 8812 | case 11: |
| 8813 | return 43; /* addx8 */ |
| 8814 | case 12: |
| 8815 | return 40; /* sub */ |
| 8816 | case 13: |
| 8817 | return 44; /* subx2 */ |
| 8818 | case 14: |
| 8819 | return 45; /* subx4 */ |
| 8820 | case 15: |
| 8821 | return 46; /* subx8 */ |
| 8822 | } |
| 8823 | break; |
| 8824 | case 1: |
| 8825 | switch (Field_op2_Slot_inst_get (insn)) |
| 8826 | { |
| 8827 | case 0: |
| 8828 | case 1: |
| 8829 | return 109; /* slli */ |
| 8830 | case 2: |
| 8831 | case 3: |
| 8832 | return 110; /* srai */ |
| 8833 | case 4: |
| 8834 | return 111; /* srli */ |
| 8835 | case 6: |
| 8836 | switch (Field_sr_Slot_inst_get (insn)) |
| 8837 | { |
| 8838 | case 0: |
| 8839 | return 127; /* xsr.lbeg */ |
| 8840 | case 1: |
| 8841 | return 121; /* xsr.lend */ |
| 8842 | case 2: |
| 8843 | return 124; /* xsr.lcount */ |
| 8844 | case 3: |
| 8845 | return 130; /* xsr.sar */ |
| 8846 | case 5: |
| 8847 | return 133; /* xsr.litbase */ |
| 8848 | case 72: |
| 8849 | return 22; /* xsr.windowbase */ |
| 8850 | case 73: |
| 8851 | return 25; /* xsr.windowstart */ |
| 8852 | case 83: |
| 8853 | return 266; /* xsr.ptevaddr */ |
| 8854 | case 90: |
| 8855 | return 269; /* xsr.rasid */ |
| 8856 | case 91: |
| 8857 | return 272; /* xsr.itlbcfg */ |
| 8858 | case 92: |
| 8859 | return 275; /* xsr.dtlbcfg */ |
| 8860 | case 96: |
| 8861 | return 218; /* xsr.ibreakenable */ |
| 8862 | case 104: |
| 8863 | return 230; /* xsr.ddr */ |
| 8864 | case 128: |
| 8865 | return 212; /* xsr.ibreaka0 */ |
| 8866 | case 129: |
| 8867 | return 215; /* xsr.ibreaka1 */ |
| 8868 | case 144: |
| 8869 | return 200; /* xsr.dbreaka0 */ |
| 8870 | case 145: |
| 8871 | return 206; /* xsr.dbreaka1 */ |
| 8872 | case 160: |
| 8873 | return 203; /* xsr.dbreakc0 */ |
| 8874 | case 161: |
| 8875 | return 209; /* xsr.dbreakc1 */ |
| 8876 | case 177: |
| 8877 | return 141; /* xsr.epc1 */ |
| 8878 | case 178: |
| 8879 | return 147; /* xsr.epc2 */ |
| 8880 | case 179: |
| 8881 | return 153; /* xsr.epc3 */ |
| 8882 | case 180: |
| 8883 | return 159; /* xsr.epc4 */ |
| 8884 | case 192: |
| 8885 | return 177; /* xsr.depc */ |
| 8886 | case 194: |
| 8887 | return 165; /* xsr.eps2 */ |
| 8888 | case 195: |
| 8889 | return 168; /* xsr.eps3 */ |
| 8890 | case 196: |
| 8891 | return 171; /* xsr.eps4 */ |
| 8892 | case 209: |
| 8893 | return 144; /* xsr.excsave1 */ |
| 8894 | case 210: |
| 8895 | return 150; /* xsr.excsave2 */ |
| 8896 | case 211: |
| 8897 | return 156; /* xsr.excsave3 */ |
| 8898 | case 212: |
| 8899 | return 162; /* xsr.excsave4 */ |
| 8900 | case 228: |
| 8901 | return 195; /* xsr.intenable */ |
| 8902 | case 230: |
| 8903 | return 138; /* xsr.ps */ |
| 8904 | case 232: |
| 8905 | return 180; /* xsr.exccause */ |
| 8906 | case 233: |
| 8907 | return 221; /* xsr.debugcause */ |
| 8908 | case 234: |
| 8909 | return 235; /* xsr.ccount */ |
| 8910 | case 236: |
| 8911 | return 224; /* xsr.icount */ |
| 8912 | case 237: |
| 8913 | return 227; /* xsr.icountlevel */ |
| 8914 | case 238: |
| 8915 | return 174; /* xsr.excvaddr */ |
| 8916 | case 240: |
| 8917 | return 238; /* xsr.ccompare0 */ |
| 8918 | case 241: |
| 8919 | return 241; /* xsr.ccompare1 */ |
| 8920 | case 242: |
| 8921 | return 244; /* xsr.ccompare2 */ |
| 8922 | case 244: |
| 8923 | return 183; /* xsr.misc0 */ |
| 8924 | case 245: |
| 8925 | return 186; /* xsr.misc1 */ |
| 8926 | } |
| 8927 | break; |
| 8928 | case 8: |
| 8929 | return 106; /* src */ |
| 8930 | case 9: |
| 8931 | if (Field_s_Slot_inst_get (insn) == 0) |
| 8932 | return 107; /* srl */ |
| 8933 | break; |
| 8934 | case 10: |
| 8935 | if (Field_t_Slot_inst_get (insn) == 0) |
| 8936 | return 105; /* sll */ |
| 8937 | break; |
| 8938 | case 11: |
| 8939 | if (Field_s_Slot_inst_get (insn) == 0) |
| 8940 | return 108; /* sra */ |
| 8941 | break; |
| 8942 | case 15: |
| 8943 | switch (Field_r_Slot_inst_get (insn)) |
| 8944 | { |
| 8945 | case 0: |
| 8946 | return 248; /* lict */ |
| 8947 | case 1: |
| 8948 | return 250; /* sict */ |
| 8949 | case 2: |
| 8950 | return 249; /* licw */ |
| 8951 | case 3: |
| 8952 | return 251; /* sicw */ |
| 8953 | case 8: |
| 8954 | return 263; /* ldct */ |
| 8955 | case 9: |
| 8956 | return 262; /* sdct */ |
| 8957 | case 14: |
| 8958 | if (Field_t_Slot_inst_get (insn) == 0 && |
| 8959 | Field_s_Slot_inst_get (insn) == 0) |
| 8960 | return 231; /* rfdo */ |
| 8961 | if (Field_t_Slot_inst_get (insn) == 1 && |
| 8962 | Field_s_Slot_inst_get (insn) == 0) |
| 8963 | return 232; /* rfdd */ |
| 8964 | break; |
| 8965 | case 15: |
| 8966 | return 286; /* ldpte */ |
| 8967 | } |
| 8968 | break; |
| 8969 | } |
| 8970 | break; |
| 8971 | case 3: |
| 8972 | switch (Field_op2_Slot_inst_get (insn)) |
| 8973 | { |
| 8974 | case 0: |
| 8975 | switch (Field_sr_Slot_inst_get (insn)) |
| 8976 | { |
| 8977 | case 0: |
| 8978 | return 125; /* rsr.lbeg */ |
| 8979 | case 1: |
| 8980 | return 119; /* rsr.lend */ |
| 8981 | case 2: |
| 8982 | return 122; /* rsr.lcount */ |
| 8983 | case 3: |
| 8984 | return 128; /* rsr.sar */ |
| 8985 | case 5: |
| 8986 | return 131; /* rsr.litbase */ |
| 8987 | case 72: |
| 8988 | return 20; /* rsr.windowbase */ |
| 8989 | case 73: |
| 8990 | return 23; /* rsr.windowstart */ |
| 8991 | case 83: |
| 8992 | return 265; /* rsr.ptevaddr */ |
| 8993 | case 90: |
| 8994 | return 267; /* rsr.rasid */ |
| 8995 | case 91: |
| 8996 | return 270; /* rsr.itlbcfg */ |
| 8997 | case 92: |
| 8998 | return 273; /* rsr.dtlbcfg */ |
| 8999 | case 96: |
| 9000 | return 216; /* rsr.ibreakenable */ |
| 9001 | case 104: |
| 9002 | return 228; /* rsr.ddr */ |
| 9003 | case 128: |
| 9004 | return 210; /* rsr.ibreaka0 */ |
| 9005 | case 129: |
| 9006 | return 213; /* rsr.ibreaka1 */ |
| 9007 | case 144: |
| 9008 | return 198; /* rsr.dbreaka0 */ |
| 9009 | case 145: |
| 9010 | return 204; /* rsr.dbreaka1 */ |
| 9011 | case 160: |
| 9012 | return 201; /* rsr.dbreakc0 */ |
| 9013 | case 161: |
| 9014 | return 207; /* rsr.dbreakc1 */ |
| 9015 | case 176: |
| 9016 | return 134; /* rsr.176 */ |
| 9017 | case 177: |
| 9018 | return 139; /* rsr.epc1 */ |
| 9019 | case 178: |
| 9020 | return 145; /* rsr.epc2 */ |
| 9021 | case 179: |
| 9022 | return 151; /* rsr.epc3 */ |
| 9023 | case 180: |
| 9024 | return 157; /* rsr.epc4 */ |
| 9025 | case 192: |
| 9026 | return 175; /* rsr.depc */ |
| 9027 | case 194: |
| 9028 | return 163; /* rsr.eps2 */ |
| 9029 | case 195: |
| 9030 | return 166; /* rsr.eps3 */ |
| 9031 | case 196: |
| 9032 | return 169; /* rsr.eps4 */ |
| 9033 | case 208: |
| 9034 | return 135; /* rsr.208 */ |
| 9035 | case 209: |
| 9036 | return 142; /* rsr.excsave1 */ |
| 9037 | case 210: |
| 9038 | return 148; /* rsr.excsave2 */ |
| 9039 | case 211: |
| 9040 | return 154; /* rsr.excsave3 */ |
| 9041 | case 212: |
| 9042 | return 160; /* rsr.excsave4 */ |
| 9043 | case 226: |
| 9044 | return 190; /* rsr.interrupt */ |
| 9045 | case 228: |
| 9046 | return 193; /* rsr.intenable */ |
| 9047 | case 230: |
| 9048 | return 136; /* rsr.ps */ |
| 9049 | case 232: |
| 9050 | return 178; /* rsr.exccause */ |
| 9051 | case 233: |
| 9052 | return 219; /* rsr.debugcause */ |
| 9053 | case 234: |
| 9054 | return 233; /* rsr.ccount */ |
| 9055 | case 235: |
| 9056 | return 187; /* rsr.prid */ |
| 9057 | case 236: |
| 9058 | return 222; /* rsr.icount */ |
| 9059 | case 237: |
| 9060 | return 225; /* rsr.icountlevel */ |
| 9061 | case 238: |
| 9062 | return 172; /* rsr.excvaddr */ |
| 9063 | case 240: |
| 9064 | return 236; /* rsr.ccompare0 */ |
| 9065 | case 241: |
| 9066 | return 239; /* rsr.ccompare1 */ |
| 9067 | case 242: |
| 9068 | return 242; /* rsr.ccompare2 */ |
| 9069 | case 244: |
| 9070 | return 181; /* rsr.misc0 */ |
| 9071 | case 245: |
| 9072 | return 184; /* rsr.misc1 */ |
| 9073 | } |
| 9074 | break; |
| 9075 | case 1: |
| 9076 | switch (Field_sr_Slot_inst_get (insn)) |
| 9077 | { |
| 9078 | case 0: |
| 9079 | return 126; /* wsr.lbeg */ |
| 9080 | case 1: |
| 9081 | return 120; /* wsr.lend */ |
| 9082 | case 2: |
| 9083 | return 123; /* wsr.lcount */ |
| 9084 | case 3: |
| 9085 | return 129; /* wsr.sar */ |
| 9086 | case 5: |
| 9087 | return 132; /* wsr.litbase */ |
| 9088 | case 72: |
| 9089 | return 21; /* wsr.windowbase */ |
| 9090 | case 73: |
| 9091 | return 24; /* wsr.windowstart */ |
| 9092 | case 83: |
| 9093 | return 264; /* wsr.ptevaddr */ |
| 9094 | case 90: |
| 9095 | return 268; /* wsr.rasid */ |
| 9096 | case 91: |
| 9097 | return 271; /* wsr.itlbcfg */ |
| 9098 | case 92: |
| 9099 | return 274; /* wsr.dtlbcfg */ |
| 9100 | case 96: |
| 9101 | return 217; /* wsr.ibreakenable */ |
| 9102 | case 104: |
| 9103 | return 229; /* wsr.ddr */ |
| 9104 | case 128: |
| 9105 | return 211; /* wsr.ibreaka0 */ |
| 9106 | case 129: |
| 9107 | return 214; /* wsr.ibreaka1 */ |
| 9108 | case 144: |
| 9109 | return 199; /* wsr.dbreaka0 */ |
| 9110 | case 145: |
| 9111 | return 205; /* wsr.dbreaka1 */ |
| 9112 | case 160: |
| 9113 | return 202; /* wsr.dbreakc0 */ |
| 9114 | case 161: |
| 9115 | return 208; /* wsr.dbreakc1 */ |
| 9116 | case 177: |
| 9117 | return 140; /* wsr.epc1 */ |
| 9118 | case 178: |
| 9119 | return 146; /* wsr.epc2 */ |
| 9120 | case 179: |
| 9121 | return 152; /* wsr.epc3 */ |
| 9122 | case 180: |
| 9123 | return 158; /* wsr.epc4 */ |
| 9124 | case 192: |
| 9125 | return 176; /* wsr.depc */ |
| 9126 | case 194: |
| 9127 | return 164; /* wsr.eps2 */ |
| 9128 | case 195: |
| 9129 | return 167; /* wsr.eps3 */ |
| 9130 | case 196: |
| 9131 | return 170; /* wsr.eps4 */ |
| 9132 | case 209: |
| 9133 | return 143; /* wsr.excsave1 */ |
| 9134 | case 210: |
| 9135 | return 149; /* wsr.excsave2 */ |
| 9136 | case 211: |
| 9137 | return 155; /* wsr.excsave3 */ |
| 9138 | case 212: |
| 9139 | return 161; /* wsr.excsave4 */ |
| 9140 | case 226: |
| 9141 | return 191; /* wsr.intset */ |
| 9142 | case 227: |
| 9143 | return 192; /* wsr.intclear */ |
| 9144 | case 228: |
| 9145 | return 194; /* wsr.intenable */ |
| 9146 | case 230: |
| 9147 | return 137; /* wsr.ps */ |
| 9148 | case 232: |
| 9149 | return 179; /* wsr.exccause */ |
| 9150 | case 233: |
| 9151 | return 220; /* wsr.debugcause */ |
| 9152 | case 234: |
| 9153 | return 234; /* wsr.ccount */ |
| 9154 | case 236: |
| 9155 | return 223; /* wsr.icount */ |
| 9156 | case 237: |
| 9157 | return 226; /* wsr.icountlevel */ |
| 9158 | case 238: |
| 9159 | return 173; /* wsr.excvaddr */ |
| 9160 | case 240: |
| 9161 | return 237; /* wsr.ccompare0 */ |
| 9162 | case 241: |
| 9163 | return 240; /* wsr.ccompare1 */ |
| 9164 | case 242: |
| 9165 | return 243; /* wsr.ccompare2 */ |
| 9166 | case 244: |
| 9167 | return 182; /* wsr.misc0 */ |
| 9168 | case 245: |
| 9169 | return 185; /* wsr.misc1 */ |
| 9170 | } |
| 9171 | break; |
| 9172 | case 8: |
| 9173 | return 89; /* moveqz */ |
| 9174 | case 9: |
| 9175 | return 90; /* movnez */ |
| 9176 | case 10: |
| 9177 | return 91; /* movltz */ |
| 9178 | case 11: |
| 9179 | return 92; /* movgez */ |
| 9180 | } |
| 9181 | break; |
| 9182 | case 4: |
| 9183 | case 5: |
| 9184 | return 76; /* extui */ |
| 9185 | case 9: |
| 9186 | switch (Field_op2_Slot_inst_get (insn)) |
| 9187 | { |
| 9188 | case 0: |
| 9189 | return 18; /* l32e */ |
| 9190 | case 4: |
| 9191 | return 19; /* s32e */ |
| 9192 | } |
| 9193 | break; |
| 9194 | } |
| 9195 | break; |
| 9196 | case 1: |
| 9197 | return 83; /* l32r */ |
| 9198 | case 2: |
| 9199 | switch (Field_r_Slot_inst_get (insn)) |
| 9200 | { |
| 9201 | case 0: |
| 9202 | return 84; /* l8ui */ |
| 9203 | case 1: |
| 9204 | return 80; /* l16ui */ |
| 9205 | case 2: |
| 9206 | return 82; /* l32i */ |
| 9207 | case 4: |
| 9208 | return 99; /* s8i */ |
| 9209 | case 5: |
| 9210 | return 97; /* s16i */ |
| 9211 | case 6: |
| 9212 | return 98; /* s32i */ |
| 9213 | case 7: |
| 9214 | switch (Field_t_Slot_inst_get (insn)) |
| 9215 | { |
| 9216 | case 0: |
| 9217 | return 258; /* dpfr */ |
| 9218 | case 1: |
| 9219 | return 259; /* dpfw */ |
| 9220 | case 2: |
| 9221 | return 260; /* dpfro */ |
| 9222 | case 3: |
| 9223 | return 261; /* dpfwo */ |
| 9224 | case 4: |
| 9225 | return 252; /* dhwb */ |
| 9226 | case 5: |
| 9227 | return 253; /* dhwbi */ |
| 9228 | case 6: |
| 9229 | return 256; /* dhi */ |
| 9230 | case 7: |
| 9231 | return 257; /* dii */ |
| 9232 | case 8: |
| 9233 | switch (Field_op1_Slot_inst_get (insn)) |
| 9234 | { |
| 9235 | case 4: |
| 9236 | return 254; /* diwb */ |
| 9237 | case 5: |
| 9238 | return 255; /* diwbi */ |
| 9239 | } |
| 9240 | break; |
| 9241 | case 12: |
| 9242 | return 245; /* ipf */ |
| 9243 | case 14: |
| 9244 | return 246; /* ihi */ |
| 9245 | case 15: |
| 9246 | return 247; /* iii */ |
| 9247 | } |
| 9248 | break; |
| 9249 | case 9: |
| 9250 | return 81; /* l16si */ |
| 9251 | case 10: |
| 9252 | return 88; /* movi */ |
| 9253 | case 12: |
| 9254 | return 37; /* addi */ |
| 9255 | case 13: |
| 9256 | return 38; /* addmi */ |
| 9257 | } |
| 9258 | break; |
| 9259 | case 5: |
| 9260 | switch (Field_n_Slot_inst_get (insn)) |
| 9261 | { |
| 9262 | case 0: |
| 9263 | return 74; /* call0 */ |
| 9264 | case 1: |
| 9265 | return 7; /* call4 */ |
| 9266 | case 2: |
| 9267 | return 6; /* call8 */ |
| 9268 | case 3: |
| 9269 | return 5; /* call12 */ |
| 9270 | } |
| 9271 | break; |
| 9272 | case 6: |
| 9273 | switch (Field_n_Slot_inst_get (insn)) |
| 9274 | { |
| 9275 | case 0: |
| 9276 | return 78; /* j */ |
| 9277 | case 1: |
| 9278 | switch (Field_m_Slot_inst_get (insn)) |
| 9279 | { |
| 9280 | case 0: |
| 9281 | return 70; /* beqz */ |
| 9282 | case 1: |
| 9283 | return 71; /* bnez */ |
| 9284 | case 2: |
| 9285 | return 73; /* bltz */ |
| 9286 | case 3: |
| 9287 | return 72; /* bgez */ |
| 9288 | } |
| 9289 | break; |
| 9290 | case 2: |
| 9291 | switch (Field_m_Slot_inst_get (insn)) |
| 9292 | { |
| 9293 | case 0: |
| 9294 | return 50; /* beqi */ |
| 9295 | case 1: |
| 9296 | return 51; /* bnei */ |
| 9297 | case 2: |
| 9298 | return 53; /* blti */ |
| 9299 | case 3: |
| 9300 | return 52; /* bgei */ |
| 9301 | } |
| 9302 | break; |
| 9303 | case 3: |
| 9304 | switch (Field_m_Slot_inst_get (insn)) |
| 9305 | { |
| 9306 | case 0: |
| 9307 | return 11; /* entry */ |
| 9308 | case 1: |
| 9309 | switch (Field_r_Slot_inst_get (insn)) |
| 9310 | { |
| 9311 | case 8: |
| 9312 | return 85; /* loop */ |
| 9313 | case 9: |
| 9314 | return 86; /* loopnez */ |
| 9315 | case 10: |
| 9316 | return 87; /* loopgtz */ |
| 9317 | } |
| 9318 | break; |
| 9319 | case 2: |
| 9320 | return 57; /* bltui */ |
| 9321 | case 3: |
| 9322 | return 56; /* bgeui */ |
| 9323 | } |
| 9324 | break; |
| 9325 | } |
| 9326 | break; |
| 9327 | case 7: |
| 9328 | switch (Field_r_Slot_inst_get (insn)) |
| 9329 | { |
| 9330 | case 0: |
| 9331 | return 65; /* bnone */ |
| 9332 | case 1: |
| 9333 | return 58; /* beq */ |
| 9334 | case 2: |
| 9335 | return 61; /* blt */ |
| 9336 | case 3: |
| 9337 | return 63; /* bltu */ |
| 9338 | case 4: |
| 9339 | return 66; /* ball */ |
| 9340 | case 5: |
| 9341 | return 68; /* bbc */ |
| 9342 | case 6: |
| 9343 | case 7: |
| 9344 | return 54; /* bbci */ |
| 9345 | case 8: |
| 9346 | return 64; /* bany */ |
| 9347 | case 9: |
| 9348 | return 59; /* bne */ |
| 9349 | case 10: |
| 9350 | return 60; /* bge */ |
| 9351 | case 11: |
| 9352 | return 62; /* bgeu */ |
| 9353 | case 12: |
| 9354 | return 67; /* bnall */ |
| 9355 | case 13: |
| 9356 | return 69; /* bbs */ |
| 9357 | case 14: |
| 9358 | case 15: |
| 9359 | return 55; /* bbsi */ |
| 9360 | } |
| 9361 | break; |
| 9362 | } |
| 9363 | return 0; |
| 9364 | } |
| 9365 | |
| 9366 | static int |
| 9367 | Slot_inst16b_decode (const xtensa_insnbuf insn) |
| 9368 | { |
| 9369 | switch (Field_op0_Slot_inst16b_get (insn)) |
| 9370 | { |
| 9371 | case 12: |
| 9372 | switch (Field_i_Slot_inst16b_get (insn)) |
| 9373 | { |
| 9374 | case 0: |
| 9375 | return 33; /* movi.n */ |
| 9376 | case 1: |
| 9377 | switch (Field_z_Slot_inst16b_get (insn)) |
| 9378 | { |
| 9379 | case 0: |
| 9380 | return 28; /* beqz.n */ |
| 9381 | case 1: |
| 9382 | return 29; /* bnez.n */ |
| 9383 | } |
| 9384 | break; |
| 9385 | } |
| 9386 | break; |
| 9387 | case 13: |
| 9388 | switch (Field_r_Slot_inst16b_get (insn)) |
| 9389 | { |
| 9390 | case 0: |
| 9391 | return 32; /* mov.n */ |
| 9392 | case 15: |
| 9393 | switch (Field_t_Slot_inst16b_get (insn)) |
| 9394 | { |
| 9395 | case 0: |
| 9396 | return 35; /* ret.n */ |
| 9397 | case 1: |
| 9398 | return 15; /* retw.n */ |
| 9399 | case 2: |
| 9400 | return 197; /* break.n */ |
| 9401 | case 3: |
| 9402 | if (Field_s_Slot_inst16b_get (insn) == 0) |
| 9403 | return 34; /* nop.n */ |
| 9404 | break; |
| 9405 | case 6: |
| 9406 | if (Field_s_Slot_inst16b_get (insn) == 0) |
| 9407 | return 30; /* ill.n */ |
| 9408 | break; |
| 9409 | } |
| 9410 | break; |
| 9411 | } |
| 9412 | break; |
| 9413 | } |
| 9414 | return 0; |
| 9415 | } |
| 9416 | |
| 9417 | static int |
| 9418 | Slot_inst16a_decode (const xtensa_insnbuf insn) |
| 9419 | { |
| 9420 | switch (Field_op0_Slot_inst16a_get (insn)) |
| 9421 | { |
| 9422 | case 8: |
| 9423 | return 31; /* l32i.n */ |
| 9424 | case 9: |
| 9425 | return 36; /* s32i.n */ |
| 9426 | case 10: |
| 9427 | return 26; /* add.n */ |
| 9428 | case 11: |
| 9429 | return 27; /* addi.n */ |
| 9430 | } |
| 9431 | return 0; |
| 9432 | } |
| 9433 | |
| 9434 | \f |
| 9435 | /* Instruction slots. */ |
| 9436 | |
| 9437 | static void |
| 9438 | Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, |
| 9439 | xtensa_insnbuf slotbuf) |
| 9440 | { |
| 9441 | slotbuf[0] = (insn[0] & 0xffffff); |
| 9442 | } |
| 9443 | |
| 9444 | static void |
| 9445 | Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, |
| 9446 | const xtensa_insnbuf slotbuf) |
| 9447 | { |
| 9448 | insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); |
| 9449 | } |
| 9450 | |
| 9451 | static void |
| 9452 | Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, |
| 9453 | xtensa_insnbuf slotbuf) |
| 9454 | { |
| 9455 | slotbuf[0] = ((insn[0] & 0xffff00) >> 8); |
| 9456 | } |
| 9457 | |
| 9458 | static void |
| 9459 | Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, |
| 9460 | const xtensa_insnbuf slotbuf) |
| 9461 | { |
| 9462 | insn[0] = (insn[0] & ~0xffff00) | ((slotbuf[0] & 0xffff) << 8); |
| 9463 | } |
| 9464 | |
| 9465 | static void |
| 9466 | Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, |
| 9467 | xtensa_insnbuf slotbuf) |
| 9468 | { |
| 9469 | slotbuf[0] = ((insn[0] & 0xffff00) >> 8); |
| 9470 | } |
| 9471 | |
| 9472 | static void |
| 9473 | Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, |
| 9474 | const xtensa_insnbuf slotbuf) |
| 9475 | { |
| 9476 | insn[0] = (insn[0] & ~0xffff00) | ((slotbuf[0] & 0xffff) << 8); |
| 9477 | } |
| 9478 | |
| 9479 | static xtensa_get_field_fn |
| 9480 | Slot_inst_get_field_fns[] = { |
| 9481 | Field_t_Slot_inst_get, |
| 9482 | Field_bbi4_Slot_inst_get, |
| 9483 | Field_bbi_Slot_inst_get, |
| 9484 | Field_imm12_Slot_inst_get, |
| 9485 | Field_imm8_Slot_inst_get, |
| 9486 | Field_s_Slot_inst_get, |
| 9487 | Field_imm12b_Slot_inst_get, |
| 9488 | Field_imm16_Slot_inst_get, |
| 9489 | Field_m_Slot_inst_get, |
| 9490 | Field_n_Slot_inst_get, |
| 9491 | Field_offset_Slot_inst_get, |
| 9492 | Field_op0_Slot_inst_get, |
| 9493 | Field_op1_Slot_inst_get, |
| 9494 | Field_op2_Slot_inst_get, |
| 9495 | Field_r_Slot_inst_get, |
| 9496 | Field_sa4_Slot_inst_get, |
| 9497 | Field_sae4_Slot_inst_get, |
| 9498 | Field_sae_Slot_inst_get, |
| 9499 | Field_sal_Slot_inst_get, |
| 9500 | Field_sargt_Slot_inst_get, |
| 9501 | Field_sas4_Slot_inst_get, |
| 9502 | Field_sas_Slot_inst_get, |
| 9503 | Field_sr_Slot_inst_get, |
| 9504 | Field_st_Slot_inst_get, |
| 9505 | Field_thi3_Slot_inst_get, |
| 9506 | Field_imm4_Slot_inst_get, |
| 9507 | Field_mn_Slot_inst_get, |
| 9508 | 0, |
| 9509 | 0, |
| 9510 | 0, |
| 9511 | 0, |
| 9512 | 0, |
| 9513 | 0, |
| 9514 | 0, |
| 9515 | 0, |
| 9516 | Implicit_Field_ar0_get, |
| 9517 | Implicit_Field_ar4_get, |
| 9518 | Implicit_Field_ar8_get, |
| 9519 | Implicit_Field_ar12_get |
| 9520 | }; |
| 9521 | |
| 9522 | static xtensa_set_field_fn |
| 9523 | Slot_inst_set_field_fns[] = { |
| 9524 | Field_t_Slot_inst_set, |
| 9525 | Field_bbi4_Slot_inst_set, |
| 9526 | Field_bbi_Slot_inst_set, |
| 9527 | Field_imm12_Slot_inst_set, |
| 9528 | Field_imm8_Slot_inst_set, |
| 9529 | Field_s_Slot_inst_set, |
| 9530 | Field_imm12b_Slot_inst_set, |
| 9531 | Field_imm16_Slot_inst_set, |
| 9532 | Field_m_Slot_inst_set, |
| 9533 | Field_n_Slot_inst_set, |
| 9534 | Field_offset_Slot_inst_set, |
| 9535 | Field_op0_Slot_inst_set, |
| 9536 | Field_op1_Slot_inst_set, |
| 9537 | Field_op2_Slot_inst_set, |
| 9538 | Field_r_Slot_inst_set, |
| 9539 | Field_sa4_Slot_inst_set, |
| 9540 | Field_sae4_Slot_inst_set, |
| 9541 | Field_sae_Slot_inst_set, |
| 9542 | Field_sal_Slot_inst_set, |
| 9543 | Field_sargt_Slot_inst_set, |
| 9544 | Field_sas4_Slot_inst_set, |
| 9545 | Field_sas_Slot_inst_set, |
| 9546 | Field_sr_Slot_inst_set, |
| 9547 | Field_st_Slot_inst_set, |
| 9548 | Field_thi3_Slot_inst_set, |
| 9549 | Field_imm4_Slot_inst_set, |
| 9550 | Field_mn_Slot_inst_set, |
| 9551 | 0, |
| 9552 | 0, |
| 9553 | 0, |
| 9554 | 0, |
| 9555 | 0, |
| 9556 | 0, |
| 9557 | 0, |
| 9558 | 0, |
| 9559 | Implicit_Field_set, |
| 9560 | Implicit_Field_set, |
| 9561 | Implicit_Field_set, |
| 9562 | Implicit_Field_set |
| 9563 | }; |
| 9564 | |
| 9565 | static xtensa_get_field_fn |
| 9566 | Slot_inst16a_get_field_fns[] = { |
| 9567 | Field_t_Slot_inst16a_get, |
| 9568 | 0, |
| 9569 | 0, |
| 9570 | 0, |
| 9571 | 0, |
| 9572 | Field_s_Slot_inst16a_get, |
| 9573 | 0, |
| 9574 | 0, |
| 9575 | 0, |
| 9576 | 0, |
| 9577 | 0, |
| 9578 | Field_op0_Slot_inst16a_get, |
| 9579 | 0, |
| 9580 | 0, |
| 9581 | Field_r_Slot_inst16a_get, |
| 9582 | 0, |
| 9583 | 0, |
| 9584 | 0, |
| 9585 | 0, |
| 9586 | 0, |
| 9587 | 0, |
| 9588 | 0, |
| 9589 | Field_sr_Slot_inst16a_get, |
| 9590 | Field_st_Slot_inst16a_get, |
| 9591 | 0, |
| 9592 | Field_imm4_Slot_inst16a_get, |
| 9593 | 0, |
| 9594 | Field_i_Slot_inst16a_get, |
| 9595 | Field_imm6lo_Slot_inst16a_get, |
| 9596 | Field_imm6hi_Slot_inst16a_get, |
| 9597 | Field_imm7lo_Slot_inst16a_get, |
| 9598 | Field_imm7hi_Slot_inst16a_get, |
| 9599 | Field_z_Slot_inst16a_get, |
| 9600 | Field_imm6_Slot_inst16a_get, |
| 9601 | Field_imm7_Slot_inst16a_get, |
| 9602 | Implicit_Field_ar0_get, |
| 9603 | Implicit_Field_ar4_get, |
| 9604 | Implicit_Field_ar8_get, |
| 9605 | Implicit_Field_ar12_get |
| 9606 | }; |
| 9607 | |
| 9608 | static xtensa_set_field_fn |
| 9609 | Slot_inst16a_set_field_fns[] = { |
| 9610 | Field_t_Slot_inst16a_set, |
| 9611 | 0, |
| 9612 | 0, |
| 9613 | 0, |
| 9614 | 0, |
| 9615 | Field_s_Slot_inst16a_set, |
| 9616 | 0, |
| 9617 | 0, |
| 9618 | 0, |
| 9619 | 0, |
| 9620 | 0, |
| 9621 | Field_op0_Slot_inst16a_set, |
| 9622 | 0, |
| 9623 | 0, |
| 9624 | Field_r_Slot_inst16a_set, |
| 9625 | 0, |
| 9626 | 0, |
| 9627 | 0, |
| 9628 | 0, |
| 9629 | 0, |
| 9630 | 0, |
| 9631 | 0, |
| 9632 | Field_sr_Slot_inst16a_set, |
| 9633 | Field_st_Slot_inst16a_set, |
| 9634 | 0, |
| 9635 | Field_imm4_Slot_inst16a_set, |
| 9636 | 0, |
| 9637 | Field_i_Slot_inst16a_set, |
| 9638 | Field_imm6lo_Slot_inst16a_set, |
| 9639 | Field_imm6hi_Slot_inst16a_set, |
| 9640 | Field_imm7lo_Slot_inst16a_set, |
| 9641 | Field_imm7hi_Slot_inst16a_set, |
| 9642 | Field_z_Slot_inst16a_set, |
| 9643 | Field_imm6_Slot_inst16a_set, |
| 9644 | Field_imm7_Slot_inst16a_set, |
| 9645 | Implicit_Field_set, |
| 9646 | Implicit_Field_set, |
| 9647 | Implicit_Field_set, |
| 9648 | Implicit_Field_set |
| 9649 | }; |
| 9650 | |
| 9651 | static xtensa_get_field_fn |
| 9652 | Slot_inst16b_get_field_fns[] = { |
| 9653 | Field_t_Slot_inst16b_get, |
| 9654 | 0, |
| 9655 | 0, |
| 9656 | 0, |
| 9657 | 0, |
| 9658 | Field_s_Slot_inst16b_get, |
| 9659 | 0, |
| 9660 | 0, |
| 9661 | 0, |
| 9662 | 0, |
| 9663 | 0, |
| 9664 | Field_op0_Slot_inst16b_get, |
| 9665 | 0, |
| 9666 | 0, |
| 9667 | Field_r_Slot_inst16b_get, |
| 9668 | 0, |
| 9669 | 0, |
| 9670 | 0, |
| 9671 | 0, |
| 9672 | 0, |
| 9673 | 0, |
| 9674 | 0, |
| 9675 | Field_sr_Slot_inst16b_get, |
| 9676 | Field_st_Slot_inst16b_get, |
| 9677 | 0, |
| 9678 | Field_imm4_Slot_inst16b_get, |
| 9679 | 0, |
| 9680 | Field_i_Slot_inst16b_get, |
| 9681 | Field_imm6lo_Slot_inst16b_get, |
| 9682 | Field_imm6hi_Slot_inst16b_get, |
| 9683 | Field_imm7lo_Slot_inst16b_get, |
| 9684 | Field_imm7hi_Slot_inst16b_get, |
| 9685 | Field_z_Slot_inst16b_get, |
| 9686 | Field_imm6_Slot_inst16b_get, |
| 9687 | Field_imm7_Slot_inst16b_get, |
| 9688 | Implicit_Field_ar0_get, |
| 9689 | Implicit_Field_ar4_get, |
| 9690 | Implicit_Field_ar8_get, |
| 9691 | Implicit_Field_ar12_get |
| 9692 | }; |
| 9693 | |
| 9694 | static xtensa_set_field_fn |
| 9695 | Slot_inst16b_set_field_fns[] = { |
| 9696 | Field_t_Slot_inst16b_set, |
| 9697 | 0, |
| 9698 | 0, |
| 9699 | 0, |
| 9700 | 0, |
| 9701 | Field_s_Slot_inst16b_set, |
| 9702 | 0, |
| 9703 | 0, |
| 9704 | 0, |
| 9705 | 0, |
| 9706 | 0, |
| 9707 | Field_op0_Slot_inst16b_set, |
| 9708 | 0, |
| 9709 | 0, |
| 9710 | Field_r_Slot_inst16b_set, |
| 9711 | 0, |
| 9712 | 0, |
| 9713 | 0, |
| 9714 | 0, |
| 9715 | 0, |
| 9716 | 0, |
| 9717 | 0, |
| 9718 | Field_sr_Slot_inst16b_set, |
| 9719 | Field_st_Slot_inst16b_set, |
| 9720 | 0, |
| 9721 | Field_imm4_Slot_inst16b_set, |
| 9722 | 0, |
| 9723 | Field_i_Slot_inst16b_set, |
| 9724 | Field_imm6lo_Slot_inst16b_set, |
| 9725 | Field_imm6hi_Slot_inst16b_set, |
| 9726 | Field_imm7lo_Slot_inst16b_set, |
| 9727 | Field_imm7hi_Slot_inst16b_set, |
| 9728 | Field_z_Slot_inst16b_set, |
| 9729 | Field_imm6_Slot_inst16b_set, |
| 9730 | Field_imm7_Slot_inst16b_set, |
| 9731 | Implicit_Field_set, |
| 9732 | Implicit_Field_set, |
| 9733 | Implicit_Field_set, |
| 9734 | Implicit_Field_set |
| 9735 | }; |
| 9736 | |
| 9737 | static xtensa_slot_internal slots[] = { |
| 9738 | { "Inst", "x24", 0, |
| 9739 | Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, |
| 9740 | Slot_inst_get_field_fns, Slot_inst_set_field_fns, |
| 9741 | Slot_inst_decode, "nop" }, |
| 9742 | { "Inst16a", "x16a", 0, |
| 9743 | Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, |
| 9744 | Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, |
| 9745 | Slot_inst16a_decode, "" }, |
| 9746 | { "Inst16b", "x16b", 0, |
| 9747 | Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, |
| 9748 | Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, |
| 9749 | Slot_inst16b_decode, "nop.n" } |
| 9750 | }; |
| 9751 | |
| 9752 | \f |
| 9753 | /* Instruction formats. */ |
| 9754 | |
| 9755 | static void |
| 9756 | Format_x24_encode (xtensa_insnbuf insn) |
| 9757 | { |
| 9758 | insn[0] = 0; |
| 9759 | } |
| 9760 | |
| 9761 | static void |
| 9762 | Format_x16a_encode (xtensa_insnbuf insn) |
| 9763 | { |
| 9764 | insn[0] = 0x800000; |
| 9765 | } |
| 9766 | |
| 9767 | static void |
| 9768 | Format_x16b_encode (xtensa_insnbuf insn) |
| 9769 | { |
| 9770 | insn[0] = 0xc00000; |
| 9771 | } |
| 9772 | |
| 9773 | static int Format_x24_slots[] = { 0 }; |
| 9774 | |
| 9775 | static int Format_x16a_slots[] = { 1 }; |
| 9776 | |
| 9777 | static int Format_x16b_slots[] = { 2 }; |
| 9778 | |
| 9779 | static xtensa_format_internal formats[] = { |
| 9780 | { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, |
| 9781 | { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, |
| 9782 | { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots } |
| 9783 | }; |
| 9784 | |
| 9785 | |
| 9786 | static int |
| 9787 | format_decoder (const xtensa_insnbuf insn) |
| 9788 | { |
| 9789 | if ((insn[0] & 0x800000) == 0) |
| 9790 | return 0; /* x24 */ |
| 9791 | if ((insn[0] & 0xc00000) == 0x800000) |
| 9792 | return 1; /* x16a */ |
| 9793 | if ((insn[0] & 0xe00000) == 0xc00000) |
| 9794 | return 2; /* x16b */ |
| 9795 | return -1; |
| 9796 | } |
| 9797 | |
| 9798 | static int length_table[16] = { |
| 9799 | 3, |
| 9800 | 3, |
| 9801 | 3, |
| 9802 | 3, |
| 9803 | 3, |
| 9804 | 3, |
| 9805 | 3, |
| 9806 | 3, |
| 9807 | 2, |
| 9808 | 2, |
| 9809 | 2, |
| 9810 | 2, |
| 9811 | 2, |
| 9812 | 2, |
| 9813 | -1, |
| 9814 | -1 |
| 9815 | }; |
| 9816 | |
| 9817 | static int |
| 9818 | length_decoder (const unsigned char *insn) |
| 9819 | { |
| 9820 | int op0 = (insn[0] >> 4) & 0xf; |
| 9821 | return length_table[op0]; |
| 9822 | } |
| 9823 | |
| 9824 | \f |
| 9825 | /* Top-level ISA structure. */ |
| 9826 | |
| 9827 | xtensa_isa_internal xtensa_modules = { |
| 9828 | 1 /* big-endian */, |
| 9829 | 3 /* insn_size */, 0, |
| 9830 | 3, formats, format_decoder, length_decoder, |
| 9831 | 3, slots, |
| 9832 | 39 /* num_fields */, |
| 9833 | 70, operands, |
| 9834 | 235, iclasses, |
| 9835 | 291, opcodes, 0, |
| 9836 | 1, regfiles, |
| 9837 | NUM_STATES, states, 0, |
| 9838 | NUM_SYSREGS, sysregs, 0, |
| 9839 | { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, |
| 9840 | 0, interfaces, 0, |
| 9841 | 0, funcUnits, 0 |
| 9842 | }; |