| 1 | ; OpenRISC 1000 32-bit CPU hardware description. -*- Scheme -*- |
| 2 | ; Copyright 2000-2019 Free Software Foundation, Inc. |
| 3 | ; Contributed for OR32 by Johan Rydberg, jrydberg@opencores.org |
| 4 | ; Modified by Julius Baxter, juliusbaxter@gmail.com |
| 5 | ; Modified by Andrey Bacherov, avbacherov@opencores.org |
| 6 | ; |
| 7 | ; This program is free software; you can redistribute it and/or modify |
| 8 | ; it under the terms of the GNU General Public License as published by |
| 9 | ; the Free Software Foundation; either version 3 of the License, or |
| 10 | ; (at your option) any later version. |
| 11 | ; |
| 12 | ; This program is distributed in the hope that it will be useful, |
| 13 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | ; GNU General Public License for more details. |
| 16 | ; |
| 17 | ; You should have received a copy of the GNU General Public License |
| 18 | ; along with this program; if not, see <http://www.gnu.org/licenses/> |
| 19 | |
| 20 | ; Hardware pieces. |
| 21 | ; These entries list the elements of the raw hardware. |
| 22 | ; They're also used to provide tables and other elements of the assembly |
| 23 | ; language. |
| 24 | |
| 25 | (define-hardware |
| 26 | (name h-pc) |
| 27 | (comment "program counter") |
| 28 | (attrs PC (MACH ORBIS-MACHS)) |
| 29 | (type pc UWI) |
| 30 | (get () (raw-reg h-pc)) |
| 31 | (set (newval) (sequence () |
| 32 | (set (reg h-sys-ppc) (raw-reg h-pc)) |
| 33 | (set (raw-reg h-pc) newval) |
| 34 | )) |
| 35 | ) |
| 36 | |
| 37 | (define-pmacro REG-INDICES |
| 38 | ((r0 0) |
| 39 | (r1 1) |
| 40 | (r2 2) |
| 41 | (r3 3) |
| 42 | (r4 4) |
| 43 | (r5 5) |
| 44 | (r6 6) |
| 45 | (r7 7) |
| 46 | (r8 8) |
| 47 | (r9 9) |
| 48 | (r10 10) |
| 49 | (r11 11) |
| 50 | (r12 12) |
| 51 | (r13 13) |
| 52 | (r14 14) |
| 53 | (r15 15) |
| 54 | (r16 16) |
| 55 | (r17 17) |
| 56 | (r18 18) |
| 57 | (r19 19) |
| 58 | (r20 20) |
| 59 | (r21 21) |
| 60 | (r22 22) |
| 61 | (r23 23) |
| 62 | (r24 24) |
| 63 | (r25 25) |
| 64 | (r26 26) |
| 65 | (r27 27) |
| 66 | (r28 28) |
| 67 | (r29 29) |
| 68 | (r30 30) |
| 69 | (r31 31) |
| 70 | (lr 9) |
| 71 | (sp 1) |
| 72 | (fp 2)) |
| 73 | ) |
| 74 | |
| 75 | ; |
| 76 | ; Hardware: [S]pecial [P]urpose [R]egisters |
| 77 | ; |
| 78 | (define-hardware |
| 79 | (name h-spr) (comment "special purpose registers") |
| 80 | (attrs VIRTUAL (MACH ORBIS-MACHS)) |
| 81 | (type register UWI (#x20000)) |
| 82 | (get (index) (c-call UWI "@cpu@_h_spr_get_raw" index)) |
| 83 | (set (index newval) (c-call VOID "@cpu@_h_spr_set_raw" index newval)) |
| 84 | ) |
| 85 | |
| 86 | (define-pmacro spr-shift 11) |
| 87 | (define-pmacro (spr-address spr-group spr-index) |
| 88 | (or (sll UWI (enum UWI (.sym "SPR-GROUP-" spr-group)) spr-shift) |
| 89 | (enum UWI (.sym "SPR-INDEX-" spr-group "-" spr-index)))) |
| 90 | |
| 91 | ; |
| 92 | ; Hardware: [G]enepral [P]urpose [R]egisters |
| 93 | ; |
| 94 | (define-hardware |
| 95 | (name h-gpr) (comment "general registers") |
| 96 | (attrs (MACH ORBIS-MACHS)) |
| 97 | (type register UWI (32)) |
| 98 | (indices keyword "" REG-INDICES) |
| 99 | (get (index) (reg UWI h-spr (add index (spr-address SYS GPR0)))) |
| 100 | (set (index newval) (set UWI (reg UWI h-spr (add index (spr-address SYS GPR0))) newval)) |
| 101 | ) |
| 102 | |
| 103 | ; |
| 104 | ; Hardware: virtual registerts for FPU (single precision) |
| 105 | ; mapped to GPRs |
| 106 | ; |
| 107 | (define-hardware |
| 108 | (name h-fsr) |
| 109 | (comment "floating point registers (single, virtual)") |
| 110 | (attrs VIRTUAL (MACH ORFPX32-MACHS)) |
| 111 | (type register SF (32)) |
| 112 | (indices keyword "" REG-INDICES) |
| 113 | (get (index) (subword SF (trunc SI (reg h-gpr index)) 0)) |
| 114 | (set (index newval) (set UWI (reg h-gpr index) (zext UWI (subword SI newval 0)))) |
| 115 | ) |
| 116 | |
| 117 | ; |
| 118 | ; Hardware: virtual registerts for FPU (double precision) |
| 119 | ; mapped to GPRs |
| 120 | ; |
| 121 | (define-hardware |
| 122 | (name h-fdr) |
| 123 | (comment "or64 floating point registers (double, virtual)") |
| 124 | (attrs VIRTUAL (MACH ORFPX64-MACHS)) |
| 125 | (type register DF (32)) |
| 126 | (indices keyword "" REG-INDICES) |
| 127 | (get (index) (subword DF (trunc DI (reg h-gpr index)) 0)) |
| 128 | (set (index newval) (set UDI (reg h-gpr index) (zext UDI (subword DI newval 0)))) |
| 129 | ) |
| 130 | |
| 131 | ; |
| 132 | ; Register pairs are offset by 2 for registers r16 and above. This is to |
| 133 | ; be able to allow registers to be call saved in GCC across function calls. |
| 134 | ; |
| 135 | (define-pmacro (reg-pair-reg-lo index) |
| 136 | (and index (const #x1f)) |
| 137 | ) |
| 138 | |
| 139 | (define-pmacro (reg-pair-reg-hi index) |
| 140 | (add (and index (const #x1f)) |
| 141 | (if (eq (sra index (const 5)) |
| 142 | (const 1)) |
| 143 | (const 2) |
| 144 | (const 1) |
| 145 | ) |
| 146 | ) |
| 147 | ) |
| 148 | |
| 149 | ; |
| 150 | ; Hardware: vrtual registers for double precision floating point |
| 151 | ; operands on 32-bit machines |
| 152 | ; mapped to GPRs |
| 153 | ; |
| 154 | (define-hardware |
| 155 | (name h-fd32r) |
| 156 | (comment "or32 floating point registers (double, virtual)") |
| 157 | (attrs VIRTUAL (MACH ORFPX64A32-MACHS)) |
| 158 | (type register DF (32)) |
| 159 | (get (index) (join DF SI |
| 160 | (reg h-gpr (reg-pair-reg-lo index)) |
| 161 | (reg h-gpr (reg-pair-reg-hi index)))) |
| 162 | (set (index newval) |
| 163 | (sequence () |
| 164 | (set (reg h-gpr (reg-pair-reg-lo index)) (subword SI newval 0)) |
| 165 | (set (reg h-gpr (reg-pair-reg-hi index)) |
| 166 | (subword SI newval 1)))) |
| 167 | ) |
| 168 | |
| 169 | ; |
| 170 | ; Hardware: vrtual 64-bit integer registers for conversions |
| 171 | ; float64 <-> int64 on 32-bit machines |
| 172 | ; mapped to GPRs |
| 173 | ; |
| 174 | (define-hardware |
| 175 | (name h-i64r) |
| 176 | (comment "or32 double word registers (int64, virtual)") |
| 177 | (attrs VIRTUAL (MACH ORFPX64A32-MACHS)) |
| 178 | (type register DI (32)) |
| 179 | (get (index) (join DI SI |
| 180 | (reg h-gpr (reg-pair-reg-lo index)) |
| 181 | (reg h-gpr (reg-pair-reg-hi index)))) |
| 182 | (set (index newval) |
| 183 | (sequence () |
| 184 | (set (reg h-gpr (reg-pair-reg-lo index)) (subword SI newval 0)) |
| 185 | (set (reg h-gpr (reg-pair-reg-hi index)) |
| 186 | (subword SI newval 1)))) |
| 187 | ) |
| 188 | |
| 189 | |
| 190 | (define-normal-enum |
| 191 | except-number |
| 192 | "Exception numbers" |
| 193 | () |
| 194 | EXCEPT- |
| 195 | (("NONE" #x00) |
| 196 | ("RESET" #x01) |
| 197 | ("BUSERR" #x02) |
| 198 | ("DPF" #x03) |
| 199 | ("IPF" #x04) |
| 200 | ("TICK" #x05) |
| 201 | ("ALIGN" #x06) |
| 202 | ("ILLEGAL" #x07) |
| 203 | ("INT" #x08) |
| 204 | ("DTLBMISS" #x09) |
| 205 | ("ITLBMISS" #x0a) |
| 206 | ("RANGE" #x0b) |
| 207 | ("SYSCALL" #x0c) |
| 208 | ("FPE" #x0d) |
| 209 | ("TRAP" #x0e) |
| 210 | ) |
| 211 | ) |
| 212 | |
| 213 | (define-pmacro (raise-exception exnum) |
| 214 | (c-call VOID "@cpu@_exception" pc exnum)) |
| 215 | |
| 216 | (define-normal-enum |
| 217 | spr-groups |
| 218 | "special purpose register groups" |
| 219 | () |
| 220 | SPR-GROUP- |
| 221 | (("SYS" #x0) |
| 222 | ("DMMU" #x1) |
| 223 | ("IMMU" #x2) |
| 224 | ("DCACHE" #x3) |
| 225 | ("ICACHE" #x4) |
| 226 | ("MAC" #x5) |
| 227 | ("DEBUG" #x6) |
| 228 | ("PERF" #x7) |
| 229 | ("POWER" #x8) |
| 230 | ("PIC" #x9) |
| 231 | ("TICK" #xa) |
| 232 | ("FPU" #xb) |
| 233 | ) |
| 234 | ) |
| 235 | |
| 236 | (define-pmacro (spr-reg-info) |
| 237 | (.splice |
| 238 | (SYS VR #x000 "version register") |
| 239 | (SYS UPR #x001 "unit present register") |
| 240 | (SYS CPUCFGR #x002 "cpu configuration register") |
| 241 | (SYS DMMUCFGR #x003 "Data MMU configuration register") |
| 242 | (SYS IMMUCFGR #x004 "Insn MMU configuration register") |
| 243 | (SYS DCCFGR #x005 "Data cache configuration register") |
| 244 | (SYS ICCFGR #x006 "Insn cache configuration register") |
| 245 | (SYS DCFGR #x007 "Debug configuration register") |
| 246 | (SYS PCCFGR #x008 "Performance counters configuration register") |
| 247 | (SYS NPC #x010 "Next program counter") |
| 248 | (SYS SR #x011 "Supervision Register") |
| 249 | (SYS PPC #x012 "Previous program counter") |
| 250 | (SYS FPCSR #x014 "Floating point control status register") |
| 251 | (.unsplice |
| 252 | (.map (.pmacro (n) (.splice SYS (.sym "EPCR" n) (.add n #x20) (.str "Exception PC register " n))) |
| 253 | (.iota #x10))) |
| 254 | (.unsplice |
| 255 | (.map (.pmacro (n) (.splice SYS (.sym "EEAR" n) (.add n #x30) (.str "Exception effective address register " n))) |
| 256 | (.iota #x10))) |
| 257 | (.unsplice |
| 258 | (.map (.pmacro (n) (.splice SYS (.sym "ESR" n) (.add n #x40) (.str "Exception supervision register " n))) |
| 259 | (.iota #x10))) |
| 260 | (.unsplice |
| 261 | (.map (.pmacro (n) (.splice SYS (.sym "GPR" n) (.add n #x400) (.str "General purpose register " n))) |
| 262 | (.iota #x200))) |
| 263 | |
| 264 | (MAC MACLO #x001 "Multiply and accumulate result (low)") |
| 265 | (MAC MACHI #x002 "Multiply and accumulate result (high)") |
| 266 | (TICK TTMR #x000 "Tick timer mode register") |
| 267 | ) |
| 268 | ) |
| 269 | |
| 270 | (define-normal-enum |
| 271 | spr-reg-indices |
| 272 | "special purpose register indices" |
| 273 | () |
| 274 | SPR-INDEX- |
| 275 | (.map (.pmacro (args) |
| 276 | (.apply (.pmacro (group index n comment) |
| 277 | ((.sym group "-" index) n)) |
| 278 | args) |
| 279 | ) |
| 280 | (spr-reg-info) |
| 281 | ) |
| 282 | ) |
| 283 | |
| 284 | (define-pmacro (define-h-spr-reg spr-group spr-index n spr-comment) |
| 285 | (define-hardware |
| 286 | (name (.sym "h-" (.downcase spr-group) "-" (.downcase spr-index))) |
| 287 | (comment spr-comment) |
| 288 | (attrs VIRTUAL (MACH ORBIS-MACHS)) |
| 289 | (type register UWI) |
| 290 | (get () (reg UWI h-spr (spr-address spr-group spr-index))) |
| 291 | (set (newval) (set (reg UWI h-spr (spr-address spr-group spr-index)) newval)) |
| 292 | ) |
| 293 | ) |
| 294 | (.splice begin (.unsplice (.map (.pmacro (args) (.apply define-h-spr-reg args)) (spr-reg-info)))) |
| 295 | |
| 296 | (define-pmacro (spr-field-info) |
| 297 | ((SYS VR REV 5 0 "revision field") |
| 298 | (SYS VR CFG 23 16 "configuration template field") |
| 299 | (SYS VR VER 31 24 "version field") |
| 300 | (SYS UPR UP 0 0 "UPR present bit") |
| 301 | (SYS UPR DCP 1 1 "data cache present bit") |
| 302 | (SYS UPR ICP 2 2 "insn cache present bit") |
| 303 | (SYS UPR DMP 3 3 "data MMU present bit") |
| 304 | (SYS UPR MP 4 4 "MAC unit present bit") |
| 305 | (SYS UPR IMP 5 5 "insn MMU present bit") |
| 306 | (SYS UPR DUP 6 6 "debug unit present bit") |
| 307 | (SYS UPR PCUP 7 7 "performance counters unit present bit") |
| 308 | (SYS UPR PICP 8 8 "programmable interrupt controller present bit") |
| 309 | (SYS UPR PMP 9 9 "power management present bit") |
| 310 | (SYS UPR TTP 10 10 "tick timer present bit") |
| 311 | (SYS UPR CUP 31 24 "custom units present field") |
| 312 | (SYS CPUCFGR NSGR 3 0 "number of shadow GPR files field") |
| 313 | (SYS CPUCFGR CGF 4 4 "custom GPR file bit") |
| 314 | (SYS CPUCFGR OB32S 5 5 "ORBIS32 supported bit") |
| 315 | (SYS CPUCFGR OB64S 6 6 "ORBIS64 supported bit") |
| 316 | (SYS CPUCFGR OF32S 7 7 "ORFPX32 supported bit") |
| 317 | (SYS CPUCFGR OF64S 8 8 "ORFPX64 supported bit") |
| 318 | (SYS CPUCFGR OV64S 9 9 "ORVDX64 supported bit") |
| 319 | (SYS CPUCFGR ND 10 10 "no transfer delay bit") |
| 320 | (SYS SR SM 0 0 "supervisor mode bit") |
| 321 | (SYS SR TEE 1 1 "tick timer exception enabled bit") |
| 322 | (SYS SR IEE 2 2 "interrupt exception enabled bit") |
| 323 | (SYS SR DCE 3 3 "data cache enabled bit") |
| 324 | (SYS SR ICE 4 4 "insn cache enabled bit") |
| 325 | (SYS SR DME 5 5 "data MMU enabled bit") |
| 326 | (SYS SR IME 6 6 "insn MMU enabled bit") |
| 327 | (SYS SR LEE 7 7 "little endian enabled bit") |
| 328 | (SYS SR CE 8 8 "CID enable bit") |
| 329 | (SYS SR F 9 9 "flag bit") |
| 330 | (SYS SR CY 10 10 "carry bit") |
| 331 | (SYS SR OV 11 11 "overflow bit") |
| 332 | (SYS SR OVE 12 12 "overflow exception enabled bit") |
| 333 | (SYS SR DSX 13 13 "delay slot exception bit") |
| 334 | (SYS SR EPH 14 14 "exception prefix high bit") |
| 335 | (SYS SR FO 15 15 "fixed one bit") |
| 336 | (SYS SR SUMRA 16 16 "SPRs user mode read access bit") |
| 337 | (SYS SR CID 31 28 "context ID field") |
| 338 | (SYS FPCSR FPEE 0 0 "floating point exceptions enabled bit") |
| 339 | (SYS FPCSR RM 2 1 "floating point rounding mode field") |
| 340 | (SYS FPCSR OVF 3 3 "floating point overflow flag bit") |
| 341 | (SYS FPCSR UNF 4 4 "floating point underflow bit") |
| 342 | (SYS FPCSR SNF 5 5 "floating point SNAN flag bit") |
| 343 | (SYS FPCSR QNF 6 6 "floating point QNAN flag bit") |
| 344 | (SYS FPCSR ZF 7 7 "floating point zero flag bit") |
| 345 | (SYS FPCSR IXF 8 8 "floating point inexact flag bit") |
| 346 | (SYS FPCSR IVF 9 9 "floating point invalid flag bit") |
| 347 | (SYS FPCSR INF 10 10 "floating point infinity flag bit") |
| 348 | (SYS FPCSR DZF 11 11 "floating point divide by zero flag bit") |
| 349 | ) |
| 350 | ) |
| 351 | |
| 352 | (define-normal-enum |
| 353 | spr-field-msbs |
| 354 | "SPR field msb positions" |
| 355 | () |
| 356 | SPR-FIELD-MSB- |
| 357 | (.map (.pmacro (args) |
| 358 | (.apply (.pmacro (group index field msb lsb comment) |
| 359 | ((.sym group "-" index "-" field) msb) |
| 360 | ) |
| 361 | args |
| 362 | ) |
| 363 | ) |
| 364 | (spr-field-info) |
| 365 | ) |
| 366 | ) |
| 367 | |
| 368 | (define-normal-enum |
| 369 | spr-field-lsbs |
| 370 | "SPR field lsb positions" |
| 371 | () |
| 372 | SPR-FIELD-SIZE- |
| 373 | (.map (.pmacro (args) |
| 374 | (.apply (.pmacro (group index field msb lsb comment) |
| 375 | ((.sym group "-" index "-" field) lsb) |
| 376 | ) |
| 377 | args |
| 378 | ) |
| 379 | ) |
| 380 | (spr-field-info) |
| 381 | ) |
| 382 | ) |
| 383 | |
| 384 | (define-normal-enum |
| 385 | spr-field-masks |
| 386 | "SPR field masks" |
| 387 | () |
| 388 | SPR-FIELD-MASK- |
| 389 | (.map (.pmacro (args) |
| 390 | (.apply (.pmacro (group index field msb lsb comment) |
| 391 | (.splice (.str group "-" index "-" field) (.sll (.inv (.sll (.inv 0) (.add (.sub msb lsb) 1))) lsb)) |
| 392 | ) |
| 393 | args |
| 394 | ) |
| 395 | ) |
| 396 | (spr-field-info) |
| 397 | ) |
| 398 | ) |
| 399 | |
| 400 | (define-pmacro (define-h-spr-field spr-group spr-index spr-field spr-field-msb spr-field-lsb spr-field-comment) |
| 401 | (.let ((spr-field-name (.sym "h-" (.downcase spr-group) "-" (.downcase spr-index) "-" (.downcase spr-field))) |
| 402 | ) |
| 403 | (begin |
| 404 | (define-hardware |
| 405 | (name spr-field-name) |
| 406 | (comment spr-field-comment) |
| 407 | (attrs VIRTUAL (MACH ORBIS-MACHS)) |
| 408 | (type register UWI) |
| 409 | (get () (c-call UWI "@cpu@_h_spr_field_get_raw" (spr-address spr-group spr-index) spr-field-msb spr-field-lsb)) |
| 410 | (set (value) (c-call VOID "@cpu@_h_spr_field_set_raw" (spr-address spr-group spr-index) spr-field-msb spr-field-lsb value)) |
| 411 | ) |
| 412 | ) |
| 413 | ) |
| 414 | ) |
| 415 | (.splice begin (.unsplice (.map (.pmacro (args) (.apply define-h-spr-field args)) (spr-field-info)))) |
| 416 | |
| 417 | (define-attr |
| 418 | (type boolean) |
| 419 | (for insn) |
| 420 | (name DELAYED-CTI) |
| 421 | (comment "delayed control transfer instruction") |
| 422 | (values #f #t) |
| 423 | (default #f) |
| 424 | ) |
| 425 | |
| 426 | (define-attr |
| 427 | (for insn) |
| 428 | (type boolean) |
| 429 | (name NOT-IN-DELAY-SLOT) |
| 430 | (comment "instruction cannot be in delay slot") |
| 431 | (values #f #t) |
| 432 | (default #f) |
| 433 | ) |
| 434 | |
| 435 | (define-attr |
| 436 | (for insn) |
| 437 | (type boolean) |
| 438 | (name FORCED-CTI) |
| 439 | (comment "instruction may forcefully transfer control (e.g., rfe)") |
| 440 | ) |