| 1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
| 2 | */ |
| 3 | /* |
| 4 | * |
| 5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 6 | * All Rights Reserved. |
| 7 | * |
| 8 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 9 | * copy of this software and associated documentation files (the |
| 10 | * "Software"), to deal in the Software without restriction, including |
| 11 | * without limitation the rights to use, copy, modify, merge, publish, |
| 12 | * distribute, sub license, and/or sell copies of the Software, and to |
| 13 | * permit persons to whom the Software is furnished to do so, subject to |
| 14 | * the following conditions: |
| 15 | * |
| 16 | * The above copyright notice and this permission notice (including the |
| 17 | * next paragraph) shall be included in all copies or substantial portions |
| 18 | * of the Software. |
| 19 | * |
| 20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #include <linux/device.h> |
| 31 | #include <linux/acpi.h> |
| 32 | #include <drm/drmP.h> |
| 33 | #include <drm/i915_drm.h> |
| 34 | #include "i915_drv.h" |
| 35 | #include "i915_trace.h" |
| 36 | #include "intel_drv.h" |
| 37 | |
| 38 | #include <linux/console.h> |
| 39 | #include <linux/module.h> |
| 40 | #include <linux/pm_runtime.h> |
| 41 | #include <drm/drm_crtc_helper.h> |
| 42 | |
| 43 | static struct drm_driver driver; |
| 44 | |
| 45 | #define GEN_DEFAULT_PIPEOFFSETS \ |
| 46 | .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ |
| 47 | PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \ |
| 48 | .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ |
| 49 | TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \ |
| 50 | .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET } |
| 51 | |
| 52 | #define GEN_CHV_PIPEOFFSETS \ |
| 53 | .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ |
| 54 | CHV_PIPE_C_OFFSET }, \ |
| 55 | .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ |
| 56 | CHV_TRANSCODER_C_OFFSET, }, \ |
| 57 | .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \ |
| 58 | CHV_PALETTE_C_OFFSET } |
| 59 | |
| 60 | #define CURSOR_OFFSETS \ |
| 61 | .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET } |
| 62 | |
| 63 | #define IVB_CURSOR_OFFSETS \ |
| 64 | .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET } |
| 65 | |
| 66 | static const struct intel_device_info intel_i830_info = { |
| 67 | .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
| 68 | .has_overlay = 1, .overlay_needs_physical = 1, |
| 69 | .ring_mask = RENDER_RING, |
| 70 | GEN_DEFAULT_PIPEOFFSETS, |
| 71 | CURSOR_OFFSETS, |
| 72 | }; |
| 73 | |
| 74 | static const struct intel_device_info intel_845g_info = { |
| 75 | .gen = 2, .num_pipes = 1, |
| 76 | .has_overlay = 1, .overlay_needs_physical = 1, |
| 77 | .ring_mask = RENDER_RING, |
| 78 | GEN_DEFAULT_PIPEOFFSETS, |
| 79 | CURSOR_OFFSETS, |
| 80 | }; |
| 81 | |
| 82 | static const struct intel_device_info intel_i85x_info = { |
| 83 | .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2, |
| 84 | .cursor_needs_physical = 1, |
| 85 | .has_overlay = 1, .overlay_needs_physical = 1, |
| 86 | .has_fbc = 1, |
| 87 | .ring_mask = RENDER_RING, |
| 88 | GEN_DEFAULT_PIPEOFFSETS, |
| 89 | CURSOR_OFFSETS, |
| 90 | }; |
| 91 | |
| 92 | static const struct intel_device_info intel_i865g_info = { |
| 93 | .gen = 2, .num_pipes = 1, |
| 94 | .has_overlay = 1, .overlay_needs_physical = 1, |
| 95 | .ring_mask = RENDER_RING, |
| 96 | GEN_DEFAULT_PIPEOFFSETS, |
| 97 | CURSOR_OFFSETS, |
| 98 | }; |
| 99 | |
| 100 | static const struct intel_device_info intel_i915g_info = { |
| 101 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
| 102 | .has_overlay = 1, .overlay_needs_physical = 1, |
| 103 | .ring_mask = RENDER_RING, |
| 104 | GEN_DEFAULT_PIPEOFFSETS, |
| 105 | CURSOR_OFFSETS, |
| 106 | }; |
| 107 | static const struct intel_device_info intel_i915gm_info = { |
| 108 | .gen = 3, .is_mobile = 1, .num_pipes = 2, |
| 109 | .cursor_needs_physical = 1, |
| 110 | .has_overlay = 1, .overlay_needs_physical = 1, |
| 111 | .supports_tv = 1, |
| 112 | .has_fbc = 1, |
| 113 | .ring_mask = RENDER_RING, |
| 114 | GEN_DEFAULT_PIPEOFFSETS, |
| 115 | CURSOR_OFFSETS, |
| 116 | }; |
| 117 | static const struct intel_device_info intel_i945g_info = { |
| 118 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
| 119 | .has_overlay = 1, .overlay_needs_physical = 1, |
| 120 | .ring_mask = RENDER_RING, |
| 121 | GEN_DEFAULT_PIPEOFFSETS, |
| 122 | CURSOR_OFFSETS, |
| 123 | }; |
| 124 | static const struct intel_device_info intel_i945gm_info = { |
| 125 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2, |
| 126 | .has_hotplug = 1, .cursor_needs_physical = 1, |
| 127 | .has_overlay = 1, .overlay_needs_physical = 1, |
| 128 | .supports_tv = 1, |
| 129 | .has_fbc = 1, |
| 130 | .ring_mask = RENDER_RING, |
| 131 | GEN_DEFAULT_PIPEOFFSETS, |
| 132 | CURSOR_OFFSETS, |
| 133 | }; |
| 134 | |
| 135 | static const struct intel_device_info intel_i965g_info = { |
| 136 | .gen = 4, .is_broadwater = 1, .num_pipes = 2, |
| 137 | .has_hotplug = 1, |
| 138 | .has_overlay = 1, |
| 139 | .ring_mask = RENDER_RING, |
| 140 | GEN_DEFAULT_PIPEOFFSETS, |
| 141 | CURSOR_OFFSETS, |
| 142 | }; |
| 143 | |
| 144 | static const struct intel_device_info intel_i965gm_info = { |
| 145 | .gen = 4, .is_crestline = 1, .num_pipes = 2, |
| 146 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, |
| 147 | .has_overlay = 1, |
| 148 | .supports_tv = 1, |
| 149 | .ring_mask = RENDER_RING, |
| 150 | GEN_DEFAULT_PIPEOFFSETS, |
| 151 | CURSOR_OFFSETS, |
| 152 | }; |
| 153 | |
| 154 | static const struct intel_device_info intel_g33_info = { |
| 155 | .gen = 3, .is_g33 = 1, .num_pipes = 2, |
| 156 | .need_gfx_hws = 1, .has_hotplug = 1, |
| 157 | .has_overlay = 1, |
| 158 | .ring_mask = RENDER_RING, |
| 159 | GEN_DEFAULT_PIPEOFFSETS, |
| 160 | CURSOR_OFFSETS, |
| 161 | }; |
| 162 | |
| 163 | static const struct intel_device_info intel_g45_info = { |
| 164 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2, |
| 165 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
| 166 | .ring_mask = RENDER_RING | BSD_RING, |
| 167 | GEN_DEFAULT_PIPEOFFSETS, |
| 168 | CURSOR_OFFSETS, |
| 169 | }; |
| 170 | |
| 171 | static const struct intel_device_info intel_gm45_info = { |
| 172 | .gen = 4, .is_g4x = 1, .num_pipes = 2, |
| 173 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, |
| 174 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
| 175 | .supports_tv = 1, |
| 176 | .ring_mask = RENDER_RING | BSD_RING, |
| 177 | GEN_DEFAULT_PIPEOFFSETS, |
| 178 | CURSOR_OFFSETS, |
| 179 | }; |
| 180 | |
| 181 | static const struct intel_device_info intel_pineview_info = { |
| 182 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2, |
| 183 | .need_gfx_hws = 1, .has_hotplug = 1, |
| 184 | .has_overlay = 1, |
| 185 | GEN_DEFAULT_PIPEOFFSETS, |
| 186 | CURSOR_OFFSETS, |
| 187 | }; |
| 188 | |
| 189 | static const struct intel_device_info intel_ironlake_d_info = { |
| 190 | .gen = 5, .num_pipes = 2, |
| 191 | .need_gfx_hws = 1, .has_hotplug = 1, |
| 192 | .ring_mask = RENDER_RING | BSD_RING, |
| 193 | GEN_DEFAULT_PIPEOFFSETS, |
| 194 | CURSOR_OFFSETS, |
| 195 | }; |
| 196 | |
| 197 | static const struct intel_device_info intel_ironlake_m_info = { |
| 198 | .gen = 5, .is_mobile = 1, .num_pipes = 2, |
| 199 | .need_gfx_hws = 1, .has_hotplug = 1, |
| 200 | .has_fbc = 1, |
| 201 | .ring_mask = RENDER_RING | BSD_RING, |
| 202 | GEN_DEFAULT_PIPEOFFSETS, |
| 203 | CURSOR_OFFSETS, |
| 204 | }; |
| 205 | |
| 206 | static const struct intel_device_info intel_sandybridge_d_info = { |
| 207 | .gen = 6, .num_pipes = 2, |
| 208 | .need_gfx_hws = 1, .has_hotplug = 1, |
| 209 | .has_fbc = 1, |
| 210 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, |
| 211 | .has_llc = 1, |
| 212 | GEN_DEFAULT_PIPEOFFSETS, |
| 213 | CURSOR_OFFSETS, |
| 214 | }; |
| 215 | |
| 216 | static const struct intel_device_info intel_sandybridge_m_info = { |
| 217 | .gen = 6, .is_mobile = 1, .num_pipes = 2, |
| 218 | .need_gfx_hws = 1, .has_hotplug = 1, |
| 219 | .has_fbc = 1, |
| 220 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, |
| 221 | .has_llc = 1, |
| 222 | GEN_DEFAULT_PIPEOFFSETS, |
| 223 | CURSOR_OFFSETS, |
| 224 | }; |
| 225 | |
| 226 | #define GEN7_FEATURES \ |
| 227 | .gen = 7, .num_pipes = 3, \ |
| 228 | .need_gfx_hws = 1, .has_hotplug = 1, \ |
| 229 | .has_fbc = 1, \ |
| 230 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ |
| 231 | .has_llc = 1 |
| 232 | |
| 233 | static const struct intel_device_info intel_ivybridge_d_info = { |
| 234 | GEN7_FEATURES, |
| 235 | .is_ivybridge = 1, |
| 236 | GEN_DEFAULT_PIPEOFFSETS, |
| 237 | IVB_CURSOR_OFFSETS, |
| 238 | }; |
| 239 | |
| 240 | static const struct intel_device_info intel_ivybridge_m_info = { |
| 241 | GEN7_FEATURES, |
| 242 | .is_ivybridge = 1, |
| 243 | .is_mobile = 1, |
| 244 | GEN_DEFAULT_PIPEOFFSETS, |
| 245 | IVB_CURSOR_OFFSETS, |
| 246 | }; |
| 247 | |
| 248 | static const struct intel_device_info intel_ivybridge_q_info = { |
| 249 | GEN7_FEATURES, |
| 250 | .is_ivybridge = 1, |
| 251 | .num_pipes = 0, /* legal, last one wins */ |
| 252 | GEN_DEFAULT_PIPEOFFSETS, |
| 253 | IVB_CURSOR_OFFSETS, |
| 254 | }; |
| 255 | |
| 256 | static const struct intel_device_info intel_valleyview_m_info = { |
| 257 | GEN7_FEATURES, |
| 258 | .is_mobile = 1, |
| 259 | .num_pipes = 2, |
| 260 | .is_valleyview = 1, |
| 261 | .display_mmio_offset = VLV_DISPLAY_BASE, |
| 262 | .has_fbc = 0, /* legal, last one wins */ |
| 263 | .has_llc = 0, /* legal, last one wins */ |
| 264 | GEN_DEFAULT_PIPEOFFSETS, |
| 265 | CURSOR_OFFSETS, |
| 266 | }; |
| 267 | |
| 268 | static const struct intel_device_info intel_valleyview_d_info = { |
| 269 | GEN7_FEATURES, |
| 270 | .num_pipes = 2, |
| 271 | .is_valleyview = 1, |
| 272 | .display_mmio_offset = VLV_DISPLAY_BASE, |
| 273 | .has_fbc = 0, /* legal, last one wins */ |
| 274 | .has_llc = 0, /* legal, last one wins */ |
| 275 | GEN_DEFAULT_PIPEOFFSETS, |
| 276 | CURSOR_OFFSETS, |
| 277 | }; |
| 278 | |
| 279 | static const struct intel_device_info intel_haswell_d_info = { |
| 280 | GEN7_FEATURES, |
| 281 | .is_haswell = 1, |
| 282 | .has_ddi = 1, |
| 283 | .has_fpga_dbg = 1, |
| 284 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, |
| 285 | GEN_DEFAULT_PIPEOFFSETS, |
| 286 | IVB_CURSOR_OFFSETS, |
| 287 | }; |
| 288 | |
| 289 | static const struct intel_device_info intel_haswell_m_info = { |
| 290 | GEN7_FEATURES, |
| 291 | .is_haswell = 1, |
| 292 | .is_mobile = 1, |
| 293 | .has_ddi = 1, |
| 294 | .has_fpga_dbg = 1, |
| 295 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, |
| 296 | GEN_DEFAULT_PIPEOFFSETS, |
| 297 | IVB_CURSOR_OFFSETS, |
| 298 | }; |
| 299 | |
| 300 | static const struct intel_device_info intel_broadwell_d_info = { |
| 301 | .gen = 8, .num_pipes = 3, |
| 302 | .need_gfx_hws = 1, .has_hotplug = 1, |
| 303 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, |
| 304 | .has_llc = 1, |
| 305 | .has_ddi = 1, |
| 306 | .has_fpga_dbg = 1, |
| 307 | .has_fbc = 1, |
| 308 | GEN_DEFAULT_PIPEOFFSETS, |
| 309 | IVB_CURSOR_OFFSETS, |
| 310 | }; |
| 311 | |
| 312 | static const struct intel_device_info intel_broadwell_m_info = { |
| 313 | .gen = 8, .is_mobile = 1, .num_pipes = 3, |
| 314 | .need_gfx_hws = 1, .has_hotplug = 1, |
| 315 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, |
| 316 | .has_llc = 1, |
| 317 | .has_ddi = 1, |
| 318 | .has_fpga_dbg = 1, |
| 319 | .has_fbc = 1, |
| 320 | GEN_DEFAULT_PIPEOFFSETS, |
| 321 | IVB_CURSOR_OFFSETS, |
| 322 | }; |
| 323 | |
| 324 | static const struct intel_device_info intel_broadwell_gt3d_info = { |
| 325 | .gen = 8, .num_pipes = 3, |
| 326 | .need_gfx_hws = 1, .has_hotplug = 1, |
| 327 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
| 328 | .has_llc = 1, |
| 329 | .has_ddi = 1, |
| 330 | .has_fpga_dbg = 1, |
| 331 | .has_fbc = 1, |
| 332 | GEN_DEFAULT_PIPEOFFSETS, |
| 333 | IVB_CURSOR_OFFSETS, |
| 334 | }; |
| 335 | |
| 336 | static const struct intel_device_info intel_broadwell_gt3m_info = { |
| 337 | .gen = 8, .is_mobile = 1, .num_pipes = 3, |
| 338 | .need_gfx_hws = 1, .has_hotplug = 1, |
| 339 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
| 340 | .has_llc = 1, |
| 341 | .has_ddi = 1, |
| 342 | .has_fpga_dbg = 1, |
| 343 | .has_fbc = 1, |
| 344 | GEN_DEFAULT_PIPEOFFSETS, |
| 345 | IVB_CURSOR_OFFSETS, |
| 346 | }; |
| 347 | |
| 348 | static const struct intel_device_info intel_cherryview_info = { |
| 349 | .gen = 8, .num_pipes = 3, |
| 350 | .need_gfx_hws = 1, .has_hotplug = 1, |
| 351 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, |
| 352 | .is_valleyview = 1, |
| 353 | .display_mmio_offset = VLV_DISPLAY_BASE, |
| 354 | GEN_CHV_PIPEOFFSETS, |
| 355 | CURSOR_OFFSETS, |
| 356 | }; |
| 357 | |
| 358 | static const struct intel_device_info intel_skylake_info = { |
| 359 | .is_skylake = 1, |
| 360 | .gen = 9, .num_pipes = 3, |
| 361 | .need_gfx_hws = 1, .has_hotplug = 1, |
| 362 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, |
| 363 | .has_llc = 1, |
| 364 | .has_ddi = 1, |
| 365 | .has_fpga_dbg = 1, |
| 366 | .has_fbc = 1, |
| 367 | GEN_DEFAULT_PIPEOFFSETS, |
| 368 | IVB_CURSOR_OFFSETS, |
| 369 | }; |
| 370 | |
| 371 | static const struct intel_device_info intel_skylake_gt3_info = { |
| 372 | .is_skylake = 1, |
| 373 | .gen = 9, .num_pipes = 3, |
| 374 | .need_gfx_hws = 1, .has_hotplug = 1, |
| 375 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
| 376 | .has_llc = 1, |
| 377 | .has_ddi = 1, |
| 378 | .has_fpga_dbg = 1, |
| 379 | .has_fbc = 1, |
| 380 | GEN_DEFAULT_PIPEOFFSETS, |
| 381 | IVB_CURSOR_OFFSETS, |
| 382 | }; |
| 383 | |
| 384 | static const struct intel_device_info intel_broxton_info = { |
| 385 | .is_preliminary = 1, |
| 386 | .is_broxton = 1, |
| 387 | .gen = 9, |
| 388 | .need_gfx_hws = 1, .has_hotplug = 1, |
| 389 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, |
| 390 | .num_pipes = 3, |
| 391 | .has_ddi = 1, |
| 392 | .has_fpga_dbg = 1, |
| 393 | .has_fbc = 1, |
| 394 | GEN_DEFAULT_PIPEOFFSETS, |
| 395 | IVB_CURSOR_OFFSETS, |
| 396 | }; |
| 397 | |
| 398 | /* |
| 399 | * Make sure any device matches here are from most specific to most |
| 400 | * general. For example, since the Quanta match is based on the subsystem |
| 401 | * and subvendor IDs, we need it to come before the more general IVB |
| 402 | * PCI ID matches, otherwise we'll use the wrong info struct above. |
| 403 | */ |
| 404 | static const struct pci_device_id pciidlist[] = { |
| 405 | INTEL_I830_IDS(&intel_i830_info), |
| 406 | INTEL_I845G_IDS(&intel_845g_info), |
| 407 | INTEL_I85X_IDS(&intel_i85x_info), |
| 408 | INTEL_I865G_IDS(&intel_i865g_info), |
| 409 | INTEL_I915G_IDS(&intel_i915g_info), |
| 410 | INTEL_I915GM_IDS(&intel_i915gm_info), |
| 411 | INTEL_I945G_IDS(&intel_i945g_info), |
| 412 | INTEL_I945GM_IDS(&intel_i945gm_info), |
| 413 | INTEL_I965G_IDS(&intel_i965g_info), |
| 414 | INTEL_G33_IDS(&intel_g33_info), |
| 415 | INTEL_I965GM_IDS(&intel_i965gm_info), |
| 416 | INTEL_GM45_IDS(&intel_gm45_info), |
| 417 | INTEL_G45_IDS(&intel_g45_info), |
| 418 | INTEL_PINEVIEW_IDS(&intel_pineview_info), |
| 419 | INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), |
| 420 | INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), |
| 421 | INTEL_SNB_D_IDS(&intel_sandybridge_d_info), |
| 422 | INTEL_SNB_M_IDS(&intel_sandybridge_m_info), |
| 423 | INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ |
| 424 | INTEL_IVB_M_IDS(&intel_ivybridge_m_info), |
| 425 | INTEL_IVB_D_IDS(&intel_ivybridge_d_info), |
| 426 | INTEL_HSW_D_IDS(&intel_haswell_d_info), |
| 427 | INTEL_HSW_M_IDS(&intel_haswell_m_info), |
| 428 | INTEL_VLV_M_IDS(&intel_valleyview_m_info), |
| 429 | INTEL_VLV_D_IDS(&intel_valleyview_d_info), |
| 430 | INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), |
| 431 | INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), |
| 432 | INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), |
| 433 | INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), |
| 434 | INTEL_CHV_IDS(&intel_cherryview_info), |
| 435 | INTEL_SKL_GT1_IDS(&intel_skylake_info), |
| 436 | INTEL_SKL_GT2_IDS(&intel_skylake_info), |
| 437 | INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), |
| 438 | INTEL_BXT_IDS(&intel_broxton_info), |
| 439 | {0, 0, 0} |
| 440 | }; |
| 441 | |
| 442 | MODULE_DEVICE_TABLE(pci, pciidlist); |
| 443 | |
| 444 | static enum intel_pch intel_virt_detect_pch(struct drm_device *dev) |
| 445 | { |
| 446 | enum intel_pch ret = PCH_NOP; |
| 447 | |
| 448 | /* |
| 449 | * In a virtualized passthrough environment we can be in a |
| 450 | * setup where the ISA bridge is not able to be passed through. |
| 451 | * In this case, a south bridge can be emulated and we have to |
| 452 | * make an educated guess as to which PCH is really there. |
| 453 | */ |
| 454 | |
| 455 | if (IS_GEN5(dev)) { |
| 456 | ret = PCH_IBX; |
| 457 | DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n"); |
| 458 | } else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) { |
| 459 | ret = PCH_CPT; |
| 460 | DRM_DEBUG_KMS("Assuming CouarPoint PCH\n"); |
| 461 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
| 462 | ret = PCH_LPT; |
| 463 | DRM_DEBUG_KMS("Assuming LynxPoint PCH\n"); |
| 464 | } else if (IS_SKYLAKE(dev)) { |
| 465 | ret = PCH_SPT; |
| 466 | DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n"); |
| 467 | } |
| 468 | |
| 469 | return ret; |
| 470 | } |
| 471 | |
| 472 | void intel_detect_pch(struct drm_device *dev) |
| 473 | { |
| 474 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 475 | struct pci_dev *pch = NULL; |
| 476 | |
| 477 | /* In all current cases, num_pipes is equivalent to the PCH_NOP setting |
| 478 | * (which really amounts to a PCH but no South Display). |
| 479 | */ |
| 480 | if (INTEL_INFO(dev)->num_pipes == 0) { |
| 481 | dev_priv->pch_type = PCH_NOP; |
| 482 | return; |
| 483 | } |
| 484 | |
| 485 | /* |
| 486 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to |
| 487 | * make graphics device passthrough work easy for VMM, that only |
| 488 | * need to expose ISA bridge to let driver know the real hardware |
| 489 | * underneath. This is a requirement from virtualization team. |
| 490 | * |
| 491 | * In some virtualized environments (e.g. XEN), there is irrelevant |
| 492 | * ISA bridge in the system. To work reliably, we should scan trhough |
| 493 | * all the ISA bridge devices and check for the first match, instead |
| 494 | * of only checking the first one. |
| 495 | */ |
| 496 | while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) { |
| 497 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { |
| 498 | unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK; |
| 499 | dev_priv->pch_id = id; |
| 500 | |
| 501 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { |
| 502 | dev_priv->pch_type = PCH_IBX; |
| 503 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); |
| 504 | WARN_ON(!IS_GEN5(dev)); |
| 505 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { |
| 506 | dev_priv->pch_type = PCH_CPT; |
| 507 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); |
| 508 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
| 509 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { |
| 510 | /* PantherPoint is CPT compatible */ |
| 511 | dev_priv->pch_type = PCH_CPT; |
| 512 | DRM_DEBUG_KMS("Found PantherPoint PCH\n"); |
| 513 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
| 514 | } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
| 515 | dev_priv->pch_type = PCH_LPT; |
| 516 | DRM_DEBUG_KMS("Found LynxPoint PCH\n"); |
| 517 | WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev)); |
| 518 | WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev)); |
| 519 | } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
| 520 | dev_priv->pch_type = PCH_LPT; |
| 521 | DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); |
| 522 | WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev)); |
| 523 | WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev)); |
| 524 | } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) { |
| 525 | dev_priv->pch_type = PCH_SPT; |
| 526 | DRM_DEBUG_KMS("Found SunrisePoint PCH\n"); |
| 527 | WARN_ON(!IS_SKYLAKE(dev)); |
| 528 | } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) { |
| 529 | dev_priv->pch_type = PCH_SPT; |
| 530 | DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n"); |
| 531 | WARN_ON(!IS_SKYLAKE(dev)); |
| 532 | } else if (id == INTEL_PCH_P2X_DEVICE_ID_TYPE) { |
| 533 | dev_priv->pch_type = intel_virt_detect_pch(dev); |
| 534 | } else |
| 535 | continue; |
| 536 | |
| 537 | break; |
| 538 | } |
| 539 | } |
| 540 | if (!pch) |
| 541 | DRM_DEBUG_KMS("No PCH found.\n"); |
| 542 | |
| 543 | pci_dev_put(pch); |
| 544 | } |
| 545 | |
| 546 | bool i915_semaphore_is_enabled(struct drm_device *dev) |
| 547 | { |
| 548 | if (INTEL_INFO(dev)->gen < 6) |
| 549 | return false; |
| 550 | |
| 551 | if (i915.semaphores >= 0) |
| 552 | return i915.semaphores; |
| 553 | |
| 554 | /* TODO: make semaphores and Execlists play nicely together */ |
| 555 | if (i915.enable_execlists) |
| 556 | return false; |
| 557 | |
| 558 | /* Until we get further testing... */ |
| 559 | if (IS_GEN8(dev)) |
| 560 | return false; |
| 561 | |
| 562 | #ifdef CONFIG_INTEL_IOMMU |
| 563 | /* Enable semaphores on SNB when IO remapping is off */ |
| 564 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) |
| 565 | return false; |
| 566 | #endif |
| 567 | |
| 568 | return true; |
| 569 | } |
| 570 | |
| 571 | void i915_firmware_load_error_print(const char *fw_path, int err) |
| 572 | { |
| 573 | DRM_ERROR("failed to load firmware %s (%d)\n", fw_path, err); |
| 574 | |
| 575 | /* |
| 576 | * If the reason is not known assume -ENOENT since that's the most |
| 577 | * usual failure mode. |
| 578 | */ |
| 579 | if (!err) |
| 580 | err = -ENOENT; |
| 581 | |
| 582 | if (!(IS_BUILTIN(CONFIG_DRM_I915) && err == -ENOENT)) |
| 583 | return; |
| 584 | |
| 585 | DRM_ERROR( |
| 586 | "The driver is built-in, so to load the firmware you need to\n" |
| 587 | "include it either in the kernel (see CONFIG_EXTRA_FIRMWARE) or\n" |
| 588 | "in your initrd/initramfs image.\n"); |
| 589 | } |
| 590 | |
| 591 | static void intel_suspend_encoders(struct drm_i915_private *dev_priv) |
| 592 | { |
| 593 | struct drm_device *dev = dev_priv->dev; |
| 594 | struct drm_encoder *encoder; |
| 595 | |
| 596 | drm_modeset_lock_all(dev); |
| 597 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 598 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
| 599 | |
| 600 | if (intel_encoder->suspend) |
| 601 | intel_encoder->suspend(intel_encoder); |
| 602 | } |
| 603 | drm_modeset_unlock_all(dev); |
| 604 | } |
| 605 | |
| 606 | static int intel_suspend_complete(struct drm_i915_private *dev_priv); |
| 607 | static int vlv_resume_prepare(struct drm_i915_private *dev_priv, |
| 608 | bool rpm_resume); |
| 609 | static int skl_resume_prepare(struct drm_i915_private *dev_priv); |
| 610 | static int bxt_resume_prepare(struct drm_i915_private *dev_priv); |
| 611 | |
| 612 | |
| 613 | static int i915_drm_suspend(struct drm_device *dev) |
| 614 | { |
| 615 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 616 | pci_power_t opregion_target_state; |
| 617 | int error; |
| 618 | |
| 619 | /* ignore lid events during suspend */ |
| 620 | mutex_lock(&dev_priv->modeset_restore_lock); |
| 621 | dev_priv->modeset_restore = MODESET_SUSPENDED; |
| 622 | mutex_unlock(&dev_priv->modeset_restore_lock); |
| 623 | |
| 624 | /* We do a lot of poking in a lot of registers, make sure they work |
| 625 | * properly. */ |
| 626 | intel_display_set_init_power(dev_priv, true); |
| 627 | |
| 628 | drm_kms_helper_poll_disable(dev); |
| 629 | |
| 630 | pci_save_state(dev->pdev); |
| 631 | |
| 632 | error = i915_gem_suspend(dev); |
| 633 | if (error) { |
| 634 | dev_err(&dev->pdev->dev, |
| 635 | "GEM idle failed, resume might fail\n"); |
| 636 | return error; |
| 637 | } |
| 638 | |
| 639 | intel_guc_suspend(dev); |
| 640 | |
| 641 | intel_suspend_gt_powersave(dev); |
| 642 | |
| 643 | /* |
| 644 | * Disable CRTCs directly since we want to preserve sw state |
| 645 | * for _thaw. Also, power gate the CRTC power wells. |
| 646 | */ |
| 647 | drm_modeset_lock_all(dev); |
| 648 | intel_display_suspend(dev); |
| 649 | drm_modeset_unlock_all(dev); |
| 650 | |
| 651 | intel_dp_mst_suspend(dev); |
| 652 | |
| 653 | intel_runtime_pm_disable_interrupts(dev_priv); |
| 654 | intel_hpd_cancel_work(dev_priv); |
| 655 | |
| 656 | intel_suspend_encoders(dev_priv); |
| 657 | |
| 658 | intel_suspend_hw(dev); |
| 659 | |
| 660 | i915_gem_suspend_gtt_mappings(dev); |
| 661 | |
| 662 | i915_save_state(dev); |
| 663 | |
| 664 | opregion_target_state = PCI_D3cold; |
| 665 | #if IS_ENABLED(CONFIG_ACPI_SLEEP) |
| 666 | if (acpi_target_system_state() < ACPI_STATE_S3) |
| 667 | opregion_target_state = PCI_D1; |
| 668 | #endif |
| 669 | intel_opregion_notify_adapter(dev, opregion_target_state); |
| 670 | |
| 671 | intel_uncore_forcewake_reset(dev, false); |
| 672 | intel_opregion_fini(dev); |
| 673 | |
| 674 | intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true); |
| 675 | |
| 676 | dev_priv->suspend_count++; |
| 677 | |
| 678 | intel_display_set_init_power(dev_priv, false); |
| 679 | |
| 680 | return 0; |
| 681 | } |
| 682 | |
| 683 | static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation) |
| 684 | { |
| 685 | struct drm_i915_private *dev_priv = drm_dev->dev_private; |
| 686 | int ret; |
| 687 | |
| 688 | ret = intel_suspend_complete(dev_priv); |
| 689 | |
| 690 | if (ret) { |
| 691 | DRM_ERROR("Suspend complete failed: %d\n", ret); |
| 692 | |
| 693 | return ret; |
| 694 | } |
| 695 | |
| 696 | pci_disable_device(drm_dev->pdev); |
| 697 | /* |
| 698 | * During hibernation on some platforms the BIOS may try to access |
| 699 | * the device even though it's already in D3 and hang the machine. So |
| 700 | * leave the device in D0 on those platforms and hope the BIOS will |
| 701 | * power down the device properly. The issue was seen on multiple old |
| 702 | * GENs with different BIOS vendors, so having an explicit blacklist |
| 703 | * is inpractical; apply the workaround on everything pre GEN6. The |
| 704 | * platforms where the issue was seen: |
| 705 | * Lenovo Thinkpad X301, X61s, X60, T60, X41 |
| 706 | * Fujitsu FSC S7110 |
| 707 | * Acer Aspire 1830T |
| 708 | */ |
| 709 | if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6)) |
| 710 | pci_set_power_state(drm_dev->pdev, PCI_D3hot); |
| 711 | |
| 712 | return 0; |
| 713 | } |
| 714 | |
| 715 | int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state) |
| 716 | { |
| 717 | int error; |
| 718 | |
| 719 | if (!dev || !dev->dev_private) { |
| 720 | DRM_ERROR("dev: %p\n", dev); |
| 721 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); |
| 722 | return -ENODEV; |
| 723 | } |
| 724 | |
| 725 | if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND && |
| 726 | state.event != PM_EVENT_FREEZE)) |
| 727 | return -EINVAL; |
| 728 | |
| 729 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
| 730 | return 0; |
| 731 | |
| 732 | error = i915_drm_suspend(dev); |
| 733 | if (error) |
| 734 | return error; |
| 735 | |
| 736 | return i915_drm_suspend_late(dev, false); |
| 737 | } |
| 738 | |
| 739 | static int i915_drm_resume(struct drm_device *dev) |
| 740 | { |
| 741 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 742 | |
| 743 | mutex_lock(&dev->struct_mutex); |
| 744 | i915_gem_restore_gtt_mappings(dev); |
| 745 | mutex_unlock(&dev->struct_mutex); |
| 746 | |
| 747 | i915_restore_state(dev); |
| 748 | intel_opregion_setup(dev); |
| 749 | |
| 750 | intel_init_pch_refclk(dev); |
| 751 | drm_mode_config_reset(dev); |
| 752 | |
| 753 | /* |
| 754 | * Interrupts have to be enabled before any batches are run. If not the |
| 755 | * GPU will hang. i915_gem_init_hw() will initiate batches to |
| 756 | * update/restore the context. |
| 757 | * |
| 758 | * Modeset enabling in intel_modeset_init_hw() also needs working |
| 759 | * interrupts. |
| 760 | */ |
| 761 | intel_runtime_pm_enable_interrupts(dev_priv); |
| 762 | |
| 763 | mutex_lock(&dev->struct_mutex); |
| 764 | if (i915_gem_init_hw(dev)) { |
| 765 | DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n"); |
| 766 | atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter); |
| 767 | } |
| 768 | mutex_unlock(&dev->struct_mutex); |
| 769 | |
| 770 | intel_guc_resume(dev); |
| 771 | |
| 772 | intel_modeset_init_hw(dev); |
| 773 | |
| 774 | spin_lock_irq(&dev_priv->irq_lock); |
| 775 | if (dev_priv->display.hpd_irq_setup) |
| 776 | dev_priv->display.hpd_irq_setup(dev); |
| 777 | spin_unlock_irq(&dev_priv->irq_lock); |
| 778 | |
| 779 | drm_modeset_lock_all(dev); |
| 780 | intel_display_resume(dev); |
| 781 | drm_modeset_unlock_all(dev); |
| 782 | |
| 783 | intel_dp_mst_resume(dev); |
| 784 | |
| 785 | /* |
| 786 | * ... but also need to make sure that hotplug processing |
| 787 | * doesn't cause havoc. Like in the driver load code we don't |
| 788 | * bother with the tiny race here where we might loose hotplug |
| 789 | * notifications. |
| 790 | * */ |
| 791 | intel_hpd_init(dev_priv); |
| 792 | /* Config may have changed between suspend and resume */ |
| 793 | drm_helper_hpd_irq_event(dev); |
| 794 | |
| 795 | intel_opregion_init(dev); |
| 796 | |
| 797 | intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false); |
| 798 | |
| 799 | mutex_lock(&dev_priv->modeset_restore_lock); |
| 800 | dev_priv->modeset_restore = MODESET_DONE; |
| 801 | mutex_unlock(&dev_priv->modeset_restore_lock); |
| 802 | |
| 803 | intel_opregion_notify_adapter(dev, PCI_D0); |
| 804 | |
| 805 | drm_kms_helper_poll_enable(dev); |
| 806 | |
| 807 | return 0; |
| 808 | } |
| 809 | |
| 810 | static int i915_drm_resume_early(struct drm_device *dev) |
| 811 | { |
| 812 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 813 | int ret = 0; |
| 814 | |
| 815 | /* |
| 816 | * We have a resume ordering issue with the snd-hda driver also |
| 817 | * requiring our device to be power up. Due to the lack of a |
| 818 | * parent/child relationship we currently solve this with an early |
| 819 | * resume hook. |
| 820 | * |
| 821 | * FIXME: This should be solved with a special hdmi sink device or |
| 822 | * similar so that power domains can be employed. |
| 823 | */ |
| 824 | if (pci_enable_device(dev->pdev)) |
| 825 | return -EIO; |
| 826 | |
| 827 | pci_set_master(dev->pdev); |
| 828 | |
| 829 | if (IS_VALLEYVIEW(dev_priv)) |
| 830 | ret = vlv_resume_prepare(dev_priv, false); |
| 831 | if (ret) |
| 832 | DRM_ERROR("Resume prepare failed: %d, continuing anyway\n", |
| 833 | ret); |
| 834 | |
| 835 | intel_uncore_early_sanitize(dev, true); |
| 836 | |
| 837 | if (IS_BROXTON(dev)) |
| 838 | ret = bxt_resume_prepare(dev_priv); |
| 839 | else if (IS_SKYLAKE(dev_priv)) |
| 840 | ret = skl_resume_prepare(dev_priv); |
| 841 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
| 842 | hsw_disable_pc8(dev_priv); |
| 843 | |
| 844 | intel_uncore_sanitize(dev); |
| 845 | intel_power_domains_init_hw(dev_priv); |
| 846 | |
| 847 | return ret; |
| 848 | } |
| 849 | |
| 850 | int i915_resume_switcheroo(struct drm_device *dev) |
| 851 | { |
| 852 | int ret; |
| 853 | |
| 854 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
| 855 | return 0; |
| 856 | |
| 857 | ret = i915_drm_resume_early(dev); |
| 858 | if (ret) |
| 859 | return ret; |
| 860 | |
| 861 | return i915_drm_resume(dev); |
| 862 | } |
| 863 | |
| 864 | /** |
| 865 | * i915_reset - reset chip after a hang |
| 866 | * @dev: drm device to reset |
| 867 | * |
| 868 | * Reset the chip. Useful if a hang is detected. Returns zero on successful |
| 869 | * reset or otherwise an error code. |
| 870 | * |
| 871 | * Procedure is fairly simple: |
| 872 | * - reset the chip using the reset reg |
| 873 | * - re-init context state |
| 874 | * - re-init hardware status page |
| 875 | * - re-init ring buffer |
| 876 | * - re-init interrupt state |
| 877 | * - re-init display |
| 878 | */ |
| 879 | int i915_reset(struct drm_device *dev) |
| 880 | { |
| 881 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 882 | bool simulated; |
| 883 | int ret; |
| 884 | |
| 885 | intel_reset_gt_powersave(dev); |
| 886 | |
| 887 | mutex_lock(&dev->struct_mutex); |
| 888 | |
| 889 | i915_gem_reset(dev); |
| 890 | |
| 891 | simulated = dev_priv->gpu_error.stop_rings != 0; |
| 892 | |
| 893 | ret = intel_gpu_reset(dev); |
| 894 | |
| 895 | /* Also reset the gpu hangman. */ |
| 896 | if (simulated) { |
| 897 | DRM_INFO("Simulated gpu hang, resetting stop_rings\n"); |
| 898 | dev_priv->gpu_error.stop_rings = 0; |
| 899 | if (ret == -ENODEV) { |
| 900 | DRM_INFO("Reset not implemented, but ignoring " |
| 901 | "error for simulated gpu hangs\n"); |
| 902 | ret = 0; |
| 903 | } |
| 904 | } |
| 905 | |
| 906 | if (i915_stop_ring_allow_warn(dev_priv)) |
| 907 | pr_notice("drm/i915: Resetting chip after gpu hang\n"); |
| 908 | |
| 909 | if (ret) { |
| 910 | DRM_ERROR("Failed to reset chip: %i\n", ret); |
| 911 | mutex_unlock(&dev->struct_mutex); |
| 912 | return ret; |
| 913 | } |
| 914 | |
| 915 | intel_overlay_reset(dev_priv); |
| 916 | |
| 917 | /* Ok, now get things going again... */ |
| 918 | |
| 919 | /* |
| 920 | * Everything depends on having the GTT running, so we need to start |
| 921 | * there. Fortunately we don't need to do this unless we reset the |
| 922 | * chip at a PCI level. |
| 923 | * |
| 924 | * Next we need to restore the context, but we don't use those |
| 925 | * yet either... |
| 926 | * |
| 927 | * Ring buffer needs to be re-initialized in the KMS case, or if X |
| 928 | * was running at the time of the reset (i.e. we weren't VT |
| 929 | * switched away). |
| 930 | */ |
| 931 | |
| 932 | /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */ |
| 933 | dev_priv->gpu_error.reload_in_reset = true; |
| 934 | |
| 935 | ret = i915_gem_init_hw(dev); |
| 936 | |
| 937 | dev_priv->gpu_error.reload_in_reset = false; |
| 938 | |
| 939 | mutex_unlock(&dev->struct_mutex); |
| 940 | if (ret) { |
| 941 | DRM_ERROR("Failed hw init on reset %d\n", ret); |
| 942 | return ret; |
| 943 | } |
| 944 | |
| 945 | /* |
| 946 | * rps/rc6 re-init is necessary to restore state lost after the |
| 947 | * reset and the re-install of gt irqs. Skip for ironlake per |
| 948 | * previous concerns that it doesn't respond well to some forms |
| 949 | * of re-init after reset. |
| 950 | */ |
| 951 | if (INTEL_INFO(dev)->gen > 5) |
| 952 | intel_enable_gt_powersave(dev); |
| 953 | |
| 954 | return 0; |
| 955 | } |
| 956 | |
| 957 | static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
| 958 | { |
| 959 | struct intel_device_info *intel_info = |
| 960 | (struct intel_device_info *) ent->driver_data; |
| 961 | |
| 962 | if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) { |
| 963 | DRM_INFO("This hardware requires preliminary hardware support.\n" |
| 964 | "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n"); |
| 965 | return -ENODEV; |
| 966 | } |
| 967 | |
| 968 | /* Only bind to function 0 of the device. Early generations |
| 969 | * used function 1 as a placeholder for multi-head. This causes |
| 970 | * us confusion instead, especially on the systems where both |
| 971 | * functions have the same PCI-ID! |
| 972 | */ |
| 973 | if (PCI_FUNC(pdev->devfn)) |
| 974 | return -ENODEV; |
| 975 | |
| 976 | return drm_get_pci_dev(pdev, ent, &driver); |
| 977 | } |
| 978 | |
| 979 | static void |
| 980 | i915_pci_remove(struct pci_dev *pdev) |
| 981 | { |
| 982 | struct drm_device *dev = pci_get_drvdata(pdev); |
| 983 | |
| 984 | drm_put_dev(dev); |
| 985 | } |
| 986 | |
| 987 | static int i915_pm_suspend(struct device *dev) |
| 988 | { |
| 989 | struct pci_dev *pdev = to_pci_dev(dev); |
| 990 | struct drm_device *drm_dev = pci_get_drvdata(pdev); |
| 991 | |
| 992 | if (!drm_dev || !drm_dev->dev_private) { |
| 993 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); |
| 994 | return -ENODEV; |
| 995 | } |
| 996 | |
| 997 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
| 998 | return 0; |
| 999 | |
| 1000 | return i915_drm_suspend(drm_dev); |
| 1001 | } |
| 1002 | |
| 1003 | static int i915_pm_suspend_late(struct device *dev) |
| 1004 | { |
| 1005 | struct drm_device *drm_dev = dev_to_i915(dev)->dev; |
| 1006 | |
| 1007 | /* |
| 1008 | * We have a suspend ordering issue with the snd-hda driver also |
| 1009 | * requiring our device to be power up. Due to the lack of a |
| 1010 | * parent/child relationship we currently solve this with an late |
| 1011 | * suspend hook. |
| 1012 | * |
| 1013 | * FIXME: This should be solved with a special hdmi sink device or |
| 1014 | * similar so that power domains can be employed. |
| 1015 | */ |
| 1016 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
| 1017 | return 0; |
| 1018 | |
| 1019 | return i915_drm_suspend_late(drm_dev, false); |
| 1020 | } |
| 1021 | |
| 1022 | static int i915_pm_poweroff_late(struct device *dev) |
| 1023 | { |
| 1024 | struct drm_device *drm_dev = dev_to_i915(dev)->dev; |
| 1025 | |
| 1026 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
| 1027 | return 0; |
| 1028 | |
| 1029 | return i915_drm_suspend_late(drm_dev, true); |
| 1030 | } |
| 1031 | |
| 1032 | static int i915_pm_resume_early(struct device *dev) |
| 1033 | { |
| 1034 | struct drm_device *drm_dev = dev_to_i915(dev)->dev; |
| 1035 | |
| 1036 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
| 1037 | return 0; |
| 1038 | |
| 1039 | return i915_drm_resume_early(drm_dev); |
| 1040 | } |
| 1041 | |
| 1042 | static int i915_pm_resume(struct device *dev) |
| 1043 | { |
| 1044 | struct drm_device *drm_dev = dev_to_i915(dev)->dev; |
| 1045 | |
| 1046 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
| 1047 | return 0; |
| 1048 | |
| 1049 | return i915_drm_resume(drm_dev); |
| 1050 | } |
| 1051 | |
| 1052 | static int skl_suspend_complete(struct drm_i915_private *dev_priv) |
| 1053 | { |
| 1054 | enum csr_state state; |
| 1055 | /* Enabling DC6 is not a hard requirement to enter runtime D3 */ |
| 1056 | |
| 1057 | skl_uninit_cdclk(dev_priv); |
| 1058 | |
| 1059 | /* TODO: wait for a completion event or |
| 1060 | * similar here instead of busy |
| 1061 | * waiting using wait_for function. |
| 1062 | */ |
| 1063 | wait_for((state = intel_csr_load_status_get(dev_priv)) != |
| 1064 | FW_UNINITIALIZED, 1000); |
| 1065 | if (state == FW_LOADED) |
| 1066 | skl_enable_dc6(dev_priv); |
| 1067 | |
| 1068 | return 0; |
| 1069 | } |
| 1070 | |
| 1071 | static int hsw_suspend_complete(struct drm_i915_private *dev_priv) |
| 1072 | { |
| 1073 | hsw_enable_pc8(dev_priv); |
| 1074 | |
| 1075 | return 0; |
| 1076 | } |
| 1077 | |
| 1078 | static int bxt_suspend_complete(struct drm_i915_private *dev_priv) |
| 1079 | { |
| 1080 | struct drm_device *dev = dev_priv->dev; |
| 1081 | |
| 1082 | /* TODO: when DC5 support is added disable DC5 here. */ |
| 1083 | |
| 1084 | broxton_ddi_phy_uninit(dev); |
| 1085 | broxton_uninit_cdclk(dev); |
| 1086 | bxt_enable_dc9(dev_priv); |
| 1087 | |
| 1088 | return 0; |
| 1089 | } |
| 1090 | |
| 1091 | static int bxt_resume_prepare(struct drm_i915_private *dev_priv) |
| 1092 | { |
| 1093 | struct drm_device *dev = dev_priv->dev; |
| 1094 | |
| 1095 | /* TODO: when CSR FW support is added make sure the FW is loaded */ |
| 1096 | |
| 1097 | bxt_disable_dc9(dev_priv); |
| 1098 | |
| 1099 | /* |
| 1100 | * TODO: when DC5 support is added enable DC5 here if the CSR FW |
| 1101 | * is available. |
| 1102 | */ |
| 1103 | broxton_init_cdclk(dev); |
| 1104 | broxton_ddi_phy_init(dev); |
| 1105 | intel_prepare_ddi(dev); |
| 1106 | |
| 1107 | return 0; |
| 1108 | } |
| 1109 | |
| 1110 | static int skl_resume_prepare(struct drm_i915_private *dev_priv) |
| 1111 | { |
| 1112 | struct drm_device *dev = dev_priv->dev; |
| 1113 | |
| 1114 | if (intel_csr_load_status_get(dev_priv) == FW_LOADED) |
| 1115 | skl_disable_dc6(dev_priv); |
| 1116 | |
| 1117 | skl_init_cdclk(dev_priv); |
| 1118 | intel_csr_load_program(dev); |
| 1119 | |
| 1120 | return 0; |
| 1121 | } |
| 1122 | |
| 1123 | /* |
| 1124 | * Save all Gunit registers that may be lost after a D3 and a subsequent |
| 1125 | * S0i[R123] transition. The list of registers needing a save/restore is |
| 1126 | * defined in the VLV2_S0IXRegs document. This documents marks all Gunit |
| 1127 | * registers in the following way: |
| 1128 | * - Driver: saved/restored by the driver |
| 1129 | * - Punit : saved/restored by the Punit firmware |
| 1130 | * - No, w/o marking: no need to save/restore, since the register is R/O or |
| 1131 | * used internally by the HW in a way that doesn't depend |
| 1132 | * keeping the content across a suspend/resume. |
| 1133 | * - Debug : used for debugging |
| 1134 | * |
| 1135 | * We save/restore all registers marked with 'Driver', with the following |
| 1136 | * exceptions: |
| 1137 | * - Registers out of use, including also registers marked with 'Debug'. |
| 1138 | * These have no effect on the driver's operation, so we don't save/restore |
| 1139 | * them to reduce the overhead. |
| 1140 | * - Registers that are fully setup by an initialization function called from |
| 1141 | * the resume path. For example many clock gating and RPS/RC6 registers. |
| 1142 | * - Registers that provide the right functionality with their reset defaults. |
| 1143 | * |
| 1144 | * TODO: Except for registers that based on the above 3 criteria can be safely |
| 1145 | * ignored, we save/restore all others, practically treating the HW context as |
| 1146 | * a black-box for the driver. Further investigation is needed to reduce the |
| 1147 | * saved/restored registers even further, by following the same 3 criteria. |
| 1148 | */ |
| 1149 | static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv) |
| 1150 | { |
| 1151 | struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; |
| 1152 | int i; |
| 1153 | |
| 1154 | /* GAM 0x4000-0x4770 */ |
| 1155 | s->wr_watermark = I915_READ(GEN7_WR_WATERMARK); |
| 1156 | s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL); |
| 1157 | s->arb_mode = I915_READ(ARB_MODE); |
| 1158 | s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0); |
| 1159 | s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1); |
| 1160 | |
| 1161 | for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) |
| 1162 | s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i)); |
| 1163 | |
| 1164 | s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT); |
| 1165 | s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT); |
| 1166 | |
| 1167 | s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7); |
| 1168 | s->ecochk = I915_READ(GAM_ECOCHK); |
| 1169 | s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7); |
| 1170 | s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7); |
| 1171 | |
| 1172 | s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR); |
| 1173 | |
| 1174 | /* MBC 0x9024-0x91D0, 0x8500 */ |
| 1175 | s->g3dctl = I915_READ(VLV_G3DCTL); |
| 1176 | s->gsckgctl = I915_READ(VLV_GSCKGCTL); |
| 1177 | s->mbctl = I915_READ(GEN6_MBCTL); |
| 1178 | |
| 1179 | /* GCP 0x9400-0x9424, 0x8100-0x810C */ |
| 1180 | s->ucgctl1 = I915_READ(GEN6_UCGCTL1); |
| 1181 | s->ucgctl3 = I915_READ(GEN6_UCGCTL3); |
| 1182 | s->rcgctl1 = I915_READ(GEN6_RCGCTL1); |
| 1183 | s->rcgctl2 = I915_READ(GEN6_RCGCTL2); |
| 1184 | s->rstctl = I915_READ(GEN6_RSTCTL); |
| 1185 | s->misccpctl = I915_READ(GEN7_MISCCPCTL); |
| 1186 | |
| 1187 | /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ |
| 1188 | s->gfxpause = I915_READ(GEN6_GFXPAUSE); |
| 1189 | s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC); |
| 1190 | s->rpdeuc = I915_READ(GEN6_RPDEUC); |
| 1191 | s->ecobus = I915_READ(ECOBUS); |
| 1192 | s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL); |
| 1193 | s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT); |
| 1194 | s->rp_deucsw = I915_READ(GEN6_RPDEUCSW); |
| 1195 | s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR); |
| 1196 | s->rcedata = I915_READ(VLV_RCEDATA); |
| 1197 | s->spare2gh = I915_READ(VLV_SPAREG2H); |
| 1198 | |
| 1199 | /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ |
| 1200 | s->gt_imr = I915_READ(GTIMR); |
| 1201 | s->gt_ier = I915_READ(GTIER); |
| 1202 | s->pm_imr = I915_READ(GEN6_PMIMR); |
| 1203 | s->pm_ier = I915_READ(GEN6_PMIER); |
| 1204 | |
| 1205 | for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) |
| 1206 | s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i)); |
| 1207 | |
| 1208 | /* GT SA CZ domain, 0x100000-0x138124 */ |
| 1209 | s->tilectl = I915_READ(TILECTL); |
| 1210 | s->gt_fifoctl = I915_READ(GTFIFOCTL); |
| 1211 | s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL); |
| 1212 | s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG); |
| 1213 | s->pmwgicz = I915_READ(VLV_PMWGICZ); |
| 1214 | |
| 1215 | /* Gunit-Display CZ domain, 0x182028-0x1821CF */ |
| 1216 | s->gu_ctl0 = I915_READ(VLV_GU_CTL0); |
| 1217 | s->gu_ctl1 = I915_READ(VLV_GU_CTL1); |
| 1218 | s->pcbr = I915_READ(VLV_PCBR); |
| 1219 | s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2); |
| 1220 | |
| 1221 | /* |
| 1222 | * Not saving any of: |
| 1223 | * DFT, 0x9800-0x9EC0 |
| 1224 | * SARB, 0xB000-0xB1FC |
| 1225 | * GAC, 0x5208-0x524C, 0x14000-0x14C000 |
| 1226 | * PCI CFG |
| 1227 | */ |
| 1228 | } |
| 1229 | |
| 1230 | static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv) |
| 1231 | { |
| 1232 | struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; |
| 1233 | u32 val; |
| 1234 | int i; |
| 1235 | |
| 1236 | /* GAM 0x4000-0x4770 */ |
| 1237 | I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark); |
| 1238 | I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl); |
| 1239 | I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16)); |
| 1240 | I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0); |
| 1241 | I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1); |
| 1242 | |
| 1243 | for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) |
| 1244 | I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]); |
| 1245 | |
| 1246 | I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count); |
| 1247 | I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count); |
| 1248 | |
| 1249 | I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp); |
| 1250 | I915_WRITE(GAM_ECOCHK, s->ecochk); |
| 1251 | I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp); |
| 1252 | I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp); |
| 1253 | |
| 1254 | I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr); |
| 1255 | |
| 1256 | /* MBC 0x9024-0x91D0, 0x8500 */ |
| 1257 | I915_WRITE(VLV_G3DCTL, s->g3dctl); |
| 1258 | I915_WRITE(VLV_GSCKGCTL, s->gsckgctl); |
| 1259 | I915_WRITE(GEN6_MBCTL, s->mbctl); |
| 1260 | |
| 1261 | /* GCP 0x9400-0x9424, 0x8100-0x810C */ |
| 1262 | I915_WRITE(GEN6_UCGCTL1, s->ucgctl1); |
| 1263 | I915_WRITE(GEN6_UCGCTL3, s->ucgctl3); |
| 1264 | I915_WRITE(GEN6_RCGCTL1, s->rcgctl1); |
| 1265 | I915_WRITE(GEN6_RCGCTL2, s->rcgctl2); |
| 1266 | I915_WRITE(GEN6_RSTCTL, s->rstctl); |
| 1267 | I915_WRITE(GEN7_MISCCPCTL, s->misccpctl); |
| 1268 | |
| 1269 | /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ |
| 1270 | I915_WRITE(GEN6_GFXPAUSE, s->gfxpause); |
| 1271 | I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc); |
| 1272 | I915_WRITE(GEN6_RPDEUC, s->rpdeuc); |
| 1273 | I915_WRITE(ECOBUS, s->ecobus); |
| 1274 | I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl); |
| 1275 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout); |
| 1276 | I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw); |
| 1277 | I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr); |
| 1278 | I915_WRITE(VLV_RCEDATA, s->rcedata); |
| 1279 | I915_WRITE(VLV_SPAREG2H, s->spare2gh); |
| 1280 | |
| 1281 | /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ |
| 1282 | I915_WRITE(GTIMR, s->gt_imr); |
| 1283 | I915_WRITE(GTIER, s->gt_ier); |
| 1284 | I915_WRITE(GEN6_PMIMR, s->pm_imr); |
| 1285 | I915_WRITE(GEN6_PMIER, s->pm_ier); |
| 1286 | |
| 1287 | for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) |
| 1288 | I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]); |
| 1289 | |
| 1290 | /* GT SA CZ domain, 0x100000-0x138124 */ |
| 1291 | I915_WRITE(TILECTL, s->tilectl); |
| 1292 | I915_WRITE(GTFIFOCTL, s->gt_fifoctl); |
| 1293 | /* |
| 1294 | * Preserve the GT allow wake and GFX force clock bit, they are not |
| 1295 | * be restored, as they are used to control the s0ix suspend/resume |
| 1296 | * sequence by the caller. |
| 1297 | */ |
| 1298 | val = I915_READ(VLV_GTLC_WAKE_CTRL); |
| 1299 | val &= VLV_GTLC_ALLOWWAKEREQ; |
| 1300 | val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ; |
| 1301 | I915_WRITE(VLV_GTLC_WAKE_CTRL, val); |
| 1302 | |
| 1303 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); |
| 1304 | val &= VLV_GFX_CLK_FORCE_ON_BIT; |
| 1305 | val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT; |
| 1306 | I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); |
| 1307 | |
| 1308 | I915_WRITE(VLV_PMWGICZ, s->pmwgicz); |
| 1309 | |
| 1310 | /* Gunit-Display CZ domain, 0x182028-0x1821CF */ |
| 1311 | I915_WRITE(VLV_GU_CTL0, s->gu_ctl0); |
| 1312 | I915_WRITE(VLV_GU_CTL1, s->gu_ctl1); |
| 1313 | I915_WRITE(VLV_PCBR, s->pcbr); |
| 1314 | I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2); |
| 1315 | } |
| 1316 | |
| 1317 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on) |
| 1318 | { |
| 1319 | u32 val; |
| 1320 | int err; |
| 1321 | |
| 1322 | #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT) |
| 1323 | |
| 1324 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); |
| 1325 | val &= ~VLV_GFX_CLK_FORCE_ON_BIT; |
| 1326 | if (force_on) |
| 1327 | val |= VLV_GFX_CLK_FORCE_ON_BIT; |
| 1328 | I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); |
| 1329 | |
| 1330 | if (!force_on) |
| 1331 | return 0; |
| 1332 | |
| 1333 | err = wait_for(COND, 20); |
| 1334 | if (err) |
| 1335 | DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n", |
| 1336 | I915_READ(VLV_GTLC_SURVIVABILITY_REG)); |
| 1337 | |
| 1338 | return err; |
| 1339 | #undef COND |
| 1340 | } |
| 1341 | |
| 1342 | static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow) |
| 1343 | { |
| 1344 | u32 val; |
| 1345 | int err = 0; |
| 1346 | |
| 1347 | val = I915_READ(VLV_GTLC_WAKE_CTRL); |
| 1348 | val &= ~VLV_GTLC_ALLOWWAKEREQ; |
| 1349 | if (allow) |
| 1350 | val |= VLV_GTLC_ALLOWWAKEREQ; |
| 1351 | I915_WRITE(VLV_GTLC_WAKE_CTRL, val); |
| 1352 | POSTING_READ(VLV_GTLC_WAKE_CTRL); |
| 1353 | |
| 1354 | #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \ |
| 1355 | allow) |
| 1356 | err = wait_for(COND, 1); |
| 1357 | if (err) |
| 1358 | DRM_ERROR("timeout disabling GT waking\n"); |
| 1359 | return err; |
| 1360 | #undef COND |
| 1361 | } |
| 1362 | |
| 1363 | static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv, |
| 1364 | bool wait_for_on) |
| 1365 | { |
| 1366 | u32 mask; |
| 1367 | u32 val; |
| 1368 | int err; |
| 1369 | |
| 1370 | mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK; |
| 1371 | val = wait_for_on ? mask : 0; |
| 1372 | #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val) |
| 1373 | if (COND) |
| 1374 | return 0; |
| 1375 | |
| 1376 | DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n", |
| 1377 | wait_for_on ? "on" : "off", |
| 1378 | I915_READ(VLV_GTLC_PW_STATUS)); |
| 1379 | |
| 1380 | /* |
| 1381 | * RC6 transitioning can be delayed up to 2 msec (see |
| 1382 | * valleyview_enable_rps), use 3 msec for safety. |
| 1383 | */ |
| 1384 | err = wait_for(COND, 3); |
| 1385 | if (err) |
| 1386 | DRM_ERROR("timeout waiting for GT wells to go %s\n", |
| 1387 | wait_for_on ? "on" : "off"); |
| 1388 | |
| 1389 | return err; |
| 1390 | #undef COND |
| 1391 | } |
| 1392 | |
| 1393 | static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv) |
| 1394 | { |
| 1395 | if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR)) |
| 1396 | return; |
| 1397 | |
| 1398 | DRM_ERROR("GT register access while GT waking disabled\n"); |
| 1399 | I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR); |
| 1400 | } |
| 1401 | |
| 1402 | static int vlv_suspend_complete(struct drm_i915_private *dev_priv) |
| 1403 | { |
| 1404 | u32 mask; |
| 1405 | int err; |
| 1406 | |
| 1407 | /* |
| 1408 | * Bspec defines the following GT well on flags as debug only, so |
| 1409 | * don't treat them as hard failures. |
| 1410 | */ |
| 1411 | (void)vlv_wait_for_gt_wells(dev_priv, false); |
| 1412 | |
| 1413 | mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS; |
| 1414 | WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask); |
| 1415 | |
| 1416 | vlv_check_no_gt_access(dev_priv); |
| 1417 | |
| 1418 | err = vlv_force_gfx_clock(dev_priv, true); |
| 1419 | if (err) |
| 1420 | goto err1; |
| 1421 | |
| 1422 | err = vlv_allow_gt_wake(dev_priv, false); |
| 1423 | if (err) |
| 1424 | goto err2; |
| 1425 | |
| 1426 | if (!IS_CHERRYVIEW(dev_priv->dev)) |
| 1427 | vlv_save_gunit_s0ix_state(dev_priv); |
| 1428 | |
| 1429 | err = vlv_force_gfx_clock(dev_priv, false); |
| 1430 | if (err) |
| 1431 | goto err2; |
| 1432 | |
| 1433 | return 0; |
| 1434 | |
| 1435 | err2: |
| 1436 | /* For safety always re-enable waking and disable gfx clock forcing */ |
| 1437 | vlv_allow_gt_wake(dev_priv, true); |
| 1438 | err1: |
| 1439 | vlv_force_gfx_clock(dev_priv, false); |
| 1440 | |
| 1441 | return err; |
| 1442 | } |
| 1443 | |
| 1444 | static int vlv_resume_prepare(struct drm_i915_private *dev_priv, |
| 1445 | bool rpm_resume) |
| 1446 | { |
| 1447 | struct drm_device *dev = dev_priv->dev; |
| 1448 | int err; |
| 1449 | int ret; |
| 1450 | |
| 1451 | /* |
| 1452 | * If any of the steps fail just try to continue, that's the best we |
| 1453 | * can do at this point. Return the first error code (which will also |
| 1454 | * leave RPM permanently disabled). |
| 1455 | */ |
| 1456 | ret = vlv_force_gfx_clock(dev_priv, true); |
| 1457 | |
| 1458 | if (!IS_CHERRYVIEW(dev_priv->dev)) |
| 1459 | vlv_restore_gunit_s0ix_state(dev_priv); |
| 1460 | |
| 1461 | err = vlv_allow_gt_wake(dev_priv, true); |
| 1462 | if (!ret) |
| 1463 | ret = err; |
| 1464 | |
| 1465 | err = vlv_force_gfx_clock(dev_priv, false); |
| 1466 | if (!ret) |
| 1467 | ret = err; |
| 1468 | |
| 1469 | vlv_check_no_gt_access(dev_priv); |
| 1470 | |
| 1471 | if (rpm_resume) { |
| 1472 | intel_init_clock_gating(dev); |
| 1473 | i915_gem_restore_fences(dev); |
| 1474 | } |
| 1475 | |
| 1476 | return ret; |
| 1477 | } |
| 1478 | |
| 1479 | static int intel_runtime_suspend(struct device *device) |
| 1480 | { |
| 1481 | struct pci_dev *pdev = to_pci_dev(device); |
| 1482 | struct drm_device *dev = pci_get_drvdata(pdev); |
| 1483 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1484 | int ret; |
| 1485 | |
| 1486 | if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev)))) |
| 1487 | return -ENODEV; |
| 1488 | |
| 1489 | if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev))) |
| 1490 | return -ENODEV; |
| 1491 | |
| 1492 | DRM_DEBUG_KMS("Suspending device\n"); |
| 1493 | |
| 1494 | /* |
| 1495 | * We could deadlock here in case another thread holding struct_mutex |
| 1496 | * calls RPM suspend concurrently, since the RPM suspend will wait |
| 1497 | * first for this RPM suspend to finish. In this case the concurrent |
| 1498 | * RPM resume will be followed by its RPM suspend counterpart. Still |
| 1499 | * for consistency return -EAGAIN, which will reschedule this suspend. |
| 1500 | */ |
| 1501 | if (!mutex_trylock(&dev->struct_mutex)) { |
| 1502 | DRM_DEBUG_KMS("device lock contention, deffering suspend\n"); |
| 1503 | /* |
| 1504 | * Bump the expiration timestamp, otherwise the suspend won't |
| 1505 | * be rescheduled. |
| 1506 | */ |
| 1507 | pm_runtime_mark_last_busy(device); |
| 1508 | |
| 1509 | return -EAGAIN; |
| 1510 | } |
| 1511 | /* |
| 1512 | * We are safe here against re-faults, since the fault handler takes |
| 1513 | * an RPM reference. |
| 1514 | */ |
| 1515 | i915_gem_release_all_mmaps(dev_priv); |
| 1516 | mutex_unlock(&dev->struct_mutex); |
| 1517 | |
| 1518 | intel_guc_suspend(dev); |
| 1519 | |
| 1520 | intel_suspend_gt_powersave(dev); |
| 1521 | intel_runtime_pm_disable_interrupts(dev_priv); |
| 1522 | |
| 1523 | ret = intel_suspend_complete(dev_priv); |
| 1524 | if (ret) { |
| 1525 | DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret); |
| 1526 | intel_runtime_pm_enable_interrupts(dev_priv); |
| 1527 | |
| 1528 | return ret; |
| 1529 | } |
| 1530 | |
| 1531 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
| 1532 | intel_uncore_forcewake_reset(dev, false); |
| 1533 | dev_priv->pm.suspended = true; |
| 1534 | |
| 1535 | /* |
| 1536 | * FIXME: We really should find a document that references the arguments |
| 1537 | * used below! |
| 1538 | */ |
| 1539 | if (IS_BROADWELL(dev)) { |
| 1540 | /* |
| 1541 | * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop |
| 1542 | * being detected, and the call we do at intel_runtime_resume() |
| 1543 | * won't be able to restore them. Since PCI_D3hot matches the |
| 1544 | * actual specification and appears to be working, use it. |
| 1545 | */ |
| 1546 | intel_opregion_notify_adapter(dev, PCI_D3hot); |
| 1547 | } else { |
| 1548 | /* |
| 1549 | * current versions of firmware which depend on this opregion |
| 1550 | * notification have repurposed the D1 definition to mean |
| 1551 | * "runtime suspended" vs. what you would normally expect (D3) |
| 1552 | * to distinguish it from notifications that might be sent via |
| 1553 | * the suspend path. |
| 1554 | */ |
| 1555 | intel_opregion_notify_adapter(dev, PCI_D1); |
| 1556 | } |
| 1557 | |
| 1558 | assert_forcewakes_inactive(dev_priv); |
| 1559 | |
| 1560 | DRM_DEBUG_KMS("Device suspended\n"); |
| 1561 | return 0; |
| 1562 | } |
| 1563 | |
| 1564 | static int intel_runtime_resume(struct device *device) |
| 1565 | { |
| 1566 | struct pci_dev *pdev = to_pci_dev(device); |
| 1567 | struct drm_device *dev = pci_get_drvdata(pdev); |
| 1568 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1569 | int ret = 0; |
| 1570 | |
| 1571 | if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev))) |
| 1572 | return -ENODEV; |
| 1573 | |
| 1574 | DRM_DEBUG_KMS("Resuming device\n"); |
| 1575 | |
| 1576 | intel_opregion_notify_adapter(dev, PCI_D0); |
| 1577 | dev_priv->pm.suspended = false; |
| 1578 | |
| 1579 | intel_guc_resume(dev); |
| 1580 | |
| 1581 | if (IS_GEN6(dev_priv)) |
| 1582 | intel_init_pch_refclk(dev); |
| 1583 | |
| 1584 | if (IS_BROXTON(dev)) |
| 1585 | ret = bxt_resume_prepare(dev_priv); |
| 1586 | else if (IS_SKYLAKE(dev)) |
| 1587 | ret = skl_resume_prepare(dev_priv); |
| 1588 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
| 1589 | hsw_disable_pc8(dev_priv); |
| 1590 | else if (IS_VALLEYVIEW(dev_priv)) |
| 1591 | ret = vlv_resume_prepare(dev_priv, true); |
| 1592 | |
| 1593 | /* |
| 1594 | * No point of rolling back things in case of an error, as the best |
| 1595 | * we can do is to hope that things will still work (and disable RPM). |
| 1596 | */ |
| 1597 | i915_gem_init_swizzling(dev); |
| 1598 | gen6_update_ring_freq(dev); |
| 1599 | |
| 1600 | intel_runtime_pm_enable_interrupts(dev_priv); |
| 1601 | |
| 1602 | /* |
| 1603 | * On VLV/CHV display interrupts are part of the display |
| 1604 | * power well, so hpd is reinitialized from there. For |
| 1605 | * everyone else do it here. |
| 1606 | */ |
| 1607 | if (!IS_VALLEYVIEW(dev_priv)) |
| 1608 | intel_hpd_init(dev_priv); |
| 1609 | |
| 1610 | intel_enable_gt_powersave(dev); |
| 1611 | |
| 1612 | if (ret) |
| 1613 | DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret); |
| 1614 | else |
| 1615 | DRM_DEBUG_KMS("Device resumed\n"); |
| 1616 | |
| 1617 | return ret; |
| 1618 | } |
| 1619 | |
| 1620 | /* |
| 1621 | * This function implements common functionality of runtime and system |
| 1622 | * suspend sequence. |
| 1623 | */ |
| 1624 | static int intel_suspend_complete(struct drm_i915_private *dev_priv) |
| 1625 | { |
| 1626 | int ret; |
| 1627 | |
| 1628 | if (IS_BROXTON(dev_priv)) |
| 1629 | ret = bxt_suspend_complete(dev_priv); |
| 1630 | else if (IS_SKYLAKE(dev_priv)) |
| 1631 | ret = skl_suspend_complete(dev_priv); |
| 1632 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
| 1633 | ret = hsw_suspend_complete(dev_priv); |
| 1634 | else if (IS_VALLEYVIEW(dev_priv)) |
| 1635 | ret = vlv_suspend_complete(dev_priv); |
| 1636 | else |
| 1637 | ret = 0; |
| 1638 | |
| 1639 | return ret; |
| 1640 | } |
| 1641 | |
| 1642 | static const struct dev_pm_ops i915_pm_ops = { |
| 1643 | /* |
| 1644 | * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND, |
| 1645 | * PMSG_RESUME] |
| 1646 | */ |
| 1647 | .suspend = i915_pm_suspend, |
| 1648 | .suspend_late = i915_pm_suspend_late, |
| 1649 | .resume_early = i915_pm_resume_early, |
| 1650 | .resume = i915_pm_resume, |
| 1651 | |
| 1652 | /* |
| 1653 | * S4 event handlers |
| 1654 | * @freeze, @freeze_late : called (1) before creating the |
| 1655 | * hibernation image [PMSG_FREEZE] and |
| 1656 | * (2) after rebooting, before restoring |
| 1657 | * the image [PMSG_QUIESCE] |
| 1658 | * @thaw, @thaw_early : called (1) after creating the hibernation |
| 1659 | * image, before writing it [PMSG_THAW] |
| 1660 | * and (2) after failing to create or |
| 1661 | * restore the image [PMSG_RECOVER] |
| 1662 | * @poweroff, @poweroff_late: called after writing the hibernation |
| 1663 | * image, before rebooting [PMSG_HIBERNATE] |
| 1664 | * @restore, @restore_early : called after rebooting and restoring the |
| 1665 | * hibernation image [PMSG_RESTORE] |
| 1666 | */ |
| 1667 | .freeze = i915_pm_suspend, |
| 1668 | .freeze_late = i915_pm_suspend_late, |
| 1669 | .thaw_early = i915_pm_resume_early, |
| 1670 | .thaw = i915_pm_resume, |
| 1671 | .poweroff = i915_pm_suspend, |
| 1672 | .poweroff_late = i915_pm_poweroff_late, |
| 1673 | .restore_early = i915_pm_resume_early, |
| 1674 | .restore = i915_pm_resume, |
| 1675 | |
| 1676 | /* S0ix (via runtime suspend) event handlers */ |
| 1677 | .runtime_suspend = intel_runtime_suspend, |
| 1678 | .runtime_resume = intel_runtime_resume, |
| 1679 | }; |
| 1680 | |
| 1681 | static const struct vm_operations_struct i915_gem_vm_ops = { |
| 1682 | .fault = i915_gem_fault, |
| 1683 | .open = drm_gem_vm_open, |
| 1684 | .close = drm_gem_vm_close, |
| 1685 | }; |
| 1686 | |
| 1687 | static const struct file_operations i915_driver_fops = { |
| 1688 | .owner = THIS_MODULE, |
| 1689 | .open = drm_open, |
| 1690 | .release = drm_release, |
| 1691 | .unlocked_ioctl = drm_ioctl, |
| 1692 | .mmap = drm_gem_mmap, |
| 1693 | .poll = drm_poll, |
| 1694 | .read = drm_read, |
| 1695 | #ifdef CONFIG_COMPAT |
| 1696 | .compat_ioctl = i915_compat_ioctl, |
| 1697 | #endif |
| 1698 | .llseek = noop_llseek, |
| 1699 | }; |
| 1700 | |
| 1701 | static struct drm_driver driver = { |
| 1702 | /* Don't use MTRRs here; the Xserver or userspace app should |
| 1703 | * deal with them for Intel hardware. |
| 1704 | */ |
| 1705 | .driver_features = |
| 1706 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME | |
| 1707 | DRIVER_RENDER | DRIVER_MODESET, |
| 1708 | .load = i915_driver_load, |
| 1709 | .unload = i915_driver_unload, |
| 1710 | .open = i915_driver_open, |
| 1711 | .lastclose = i915_driver_lastclose, |
| 1712 | .preclose = i915_driver_preclose, |
| 1713 | .postclose = i915_driver_postclose, |
| 1714 | .set_busid = drm_pci_set_busid, |
| 1715 | |
| 1716 | #if defined(CONFIG_DEBUG_FS) |
| 1717 | .debugfs_init = i915_debugfs_init, |
| 1718 | .debugfs_cleanup = i915_debugfs_cleanup, |
| 1719 | #endif |
| 1720 | .gem_free_object = i915_gem_free_object, |
| 1721 | .gem_vm_ops = &i915_gem_vm_ops, |
| 1722 | |
| 1723 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, |
| 1724 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, |
| 1725 | .gem_prime_export = i915_gem_prime_export, |
| 1726 | .gem_prime_import = i915_gem_prime_import, |
| 1727 | |
| 1728 | .dumb_create = i915_gem_dumb_create, |
| 1729 | .dumb_map_offset = i915_gem_mmap_gtt, |
| 1730 | .dumb_destroy = drm_gem_dumb_destroy, |
| 1731 | .ioctls = i915_ioctls, |
| 1732 | .fops = &i915_driver_fops, |
| 1733 | .name = DRIVER_NAME, |
| 1734 | .desc = DRIVER_DESC, |
| 1735 | .date = DRIVER_DATE, |
| 1736 | .major = DRIVER_MAJOR, |
| 1737 | .minor = DRIVER_MINOR, |
| 1738 | .patchlevel = DRIVER_PATCHLEVEL, |
| 1739 | }; |
| 1740 | |
| 1741 | static struct pci_driver i915_pci_driver = { |
| 1742 | .name = DRIVER_NAME, |
| 1743 | .id_table = pciidlist, |
| 1744 | .probe = i915_pci_probe, |
| 1745 | .remove = i915_pci_remove, |
| 1746 | .driver.pm = &i915_pm_ops, |
| 1747 | }; |
| 1748 | |
| 1749 | static int __init i915_init(void) |
| 1750 | { |
| 1751 | driver.num_ioctls = i915_max_ioctl; |
| 1752 | |
| 1753 | /* |
| 1754 | * Enable KMS by default, unless explicitly overriden by |
| 1755 | * either the i915.modeset prarameter or by the |
| 1756 | * vga_text_mode_force boot option. |
| 1757 | */ |
| 1758 | |
| 1759 | if (i915.modeset == 0) |
| 1760 | driver.driver_features &= ~DRIVER_MODESET; |
| 1761 | |
| 1762 | #ifdef CONFIG_VGA_CONSOLE |
| 1763 | if (vgacon_text_force() && i915.modeset == -1) |
| 1764 | driver.driver_features &= ~DRIVER_MODESET; |
| 1765 | #endif |
| 1766 | |
| 1767 | if (!(driver.driver_features & DRIVER_MODESET)) { |
| 1768 | /* Silently fail loading to not upset userspace. */ |
| 1769 | DRM_DEBUG_DRIVER("KMS and UMS disabled.\n"); |
| 1770 | return 0; |
| 1771 | } |
| 1772 | |
| 1773 | if (i915.nuclear_pageflip) |
| 1774 | driver.driver_features |= DRIVER_ATOMIC; |
| 1775 | |
| 1776 | return drm_pci_init(&driver, &i915_pci_driver); |
| 1777 | } |
| 1778 | |
| 1779 | static void __exit i915_exit(void) |
| 1780 | { |
| 1781 | if (!(driver.driver_features & DRIVER_MODESET)) |
| 1782 | return; /* Never loaded a driver. */ |
| 1783 | |
| 1784 | drm_pci_exit(&driver, &i915_pci_driver); |
| 1785 | } |
| 1786 | |
| 1787 | module_init(i915_init); |
| 1788 | module_exit(i915_exit); |
| 1789 | |
| 1790 | MODULE_AUTHOR("Tungsten Graphics, Inc."); |
| 1791 | MODULE_AUTHOR("Intel Corporation"); |
| 1792 | |
| 1793 | MODULE_DESCRIPTION(DRIVER_DESC); |
| 1794 | MODULE_LICENSE("GPL and additional rights"); |