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drm/i915: Segregate memory domains in the GTT using coloring
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gem.c
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1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include "drmP.h"
29#include "drm.h"
30#include "i915_drm.h"
31#include "i915_drv.h"
32#include "i915_trace.h"
33#include "intel_drv.h"
34#include <linux/shmem_fs.h>
35#include <linux/slab.h>
36#include <linux/swap.h>
37#include <linux/pci.h>
38#include <linux/dma-buf.h>
39
40static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
41static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
42static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
43 unsigned alignment,
44 bool map_and_fenceable);
45static int i915_gem_phys_pwrite(struct drm_device *dev,
46 struct drm_i915_gem_object *obj,
47 struct drm_i915_gem_pwrite *args,
48 struct drm_file *file);
49
50static void i915_gem_write_fence(struct drm_device *dev, int reg,
51 struct drm_i915_gem_object *obj);
52static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
53 struct drm_i915_fence_reg *fence,
54 bool enable);
55
56static int i915_gem_inactive_shrink(struct shrinker *shrinker,
57 struct shrink_control *sc);
58static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
59
60static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
61{
62 if (obj->tiling_mode)
63 i915_gem_release_mmap(obj);
64
65 /* As we do not have an associated fence register, we will force
66 * a tiling change if we ever need to acquire one.
67 */
68 obj->fence_dirty = false;
69 obj->fence_reg = I915_FENCE_REG_NONE;
70}
71
72/* some bookkeeping */
73static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
74 size_t size)
75{
76 dev_priv->mm.object_count++;
77 dev_priv->mm.object_memory += size;
78}
79
80static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
81 size_t size)
82{
83 dev_priv->mm.object_count--;
84 dev_priv->mm.object_memory -= size;
85}
86
87static int
88i915_gem_wait_for_error(struct drm_device *dev)
89{
90 struct drm_i915_private *dev_priv = dev->dev_private;
91 struct completion *x = &dev_priv->error_completion;
92 unsigned long flags;
93 int ret;
94
95 if (!atomic_read(&dev_priv->mm.wedged))
96 return 0;
97
98 /*
99 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
100 * userspace. If it takes that long something really bad is going on and
101 * we should simply try to bail out and fail as gracefully as possible.
102 */
103 ret = wait_for_completion_interruptible_timeout(x, 10*HZ);
104 if (ret == 0) {
105 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
106 return -EIO;
107 } else if (ret < 0) {
108 return ret;
109 }
110
111 if (atomic_read(&dev_priv->mm.wedged)) {
112 /* GPU is hung, bump the completion count to account for
113 * the token we just consumed so that we never hit zero and
114 * end up waiting upon a subsequent completion event that
115 * will never happen.
116 */
117 spin_lock_irqsave(&x->wait.lock, flags);
118 x->done++;
119 spin_unlock_irqrestore(&x->wait.lock, flags);
120 }
121 return 0;
122}
123
124int i915_mutex_lock_interruptible(struct drm_device *dev)
125{
126 int ret;
127
128 ret = i915_gem_wait_for_error(dev);
129 if (ret)
130 return ret;
131
132 ret = mutex_lock_interruptible(&dev->struct_mutex);
133 if (ret)
134 return ret;
135
136 WARN_ON(i915_verify_lists(dev));
137 return 0;
138}
139
140static inline bool
141i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
142{
143 return !obj->active;
144}
145
146int
147i915_gem_init_ioctl(struct drm_device *dev, void *data,
148 struct drm_file *file)
149{
150 struct drm_i915_gem_init *args = data;
151
152 if (drm_core_check_feature(dev, DRIVER_MODESET))
153 return -ENODEV;
154
155 if (args->gtt_start >= args->gtt_end ||
156 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
157 return -EINVAL;
158
159 /* GEM with user mode setting was never supported on ilk and later. */
160 if (INTEL_INFO(dev)->gen >= 5)
161 return -ENODEV;
162
163 mutex_lock(&dev->struct_mutex);
164 i915_gem_init_global_gtt(dev, args->gtt_start,
165 args->gtt_end, args->gtt_end);
166 mutex_unlock(&dev->struct_mutex);
167
168 return 0;
169}
170
171int
172i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
173 struct drm_file *file)
174{
175 struct drm_i915_private *dev_priv = dev->dev_private;
176 struct drm_i915_gem_get_aperture *args = data;
177 struct drm_i915_gem_object *obj;
178 size_t pinned;
179
180 pinned = 0;
181 mutex_lock(&dev->struct_mutex);
182 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list)
183 if (obj->pin_count)
184 pinned += obj->gtt_space->size;
185 mutex_unlock(&dev->struct_mutex);
186
187 args->aper_size = dev_priv->mm.gtt_total;
188 args->aper_available_size = args->aper_size - pinned;
189
190 return 0;
191}
192
193static int
194i915_gem_create(struct drm_file *file,
195 struct drm_device *dev,
196 uint64_t size,
197 uint32_t *handle_p)
198{
199 struct drm_i915_gem_object *obj;
200 int ret;
201 u32 handle;
202
203 size = roundup(size, PAGE_SIZE);
204 if (size == 0)
205 return -EINVAL;
206
207 /* Allocate the new object */
208 obj = i915_gem_alloc_object(dev, size);
209 if (obj == NULL)
210 return -ENOMEM;
211
212 ret = drm_gem_handle_create(file, &obj->base, &handle);
213 if (ret) {
214 drm_gem_object_release(&obj->base);
215 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
216 kfree(obj);
217 return ret;
218 }
219
220 /* drop reference from allocate - handle holds it now */
221 drm_gem_object_unreference(&obj->base);
222 trace_i915_gem_object_create(obj);
223
224 *handle_p = handle;
225 return 0;
226}
227
228int
229i915_gem_dumb_create(struct drm_file *file,
230 struct drm_device *dev,
231 struct drm_mode_create_dumb *args)
232{
233 /* have to work out size/pitch and return them */
234 args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
235 args->size = args->pitch * args->height;
236 return i915_gem_create(file, dev,
237 args->size, &args->handle);
238}
239
240int i915_gem_dumb_destroy(struct drm_file *file,
241 struct drm_device *dev,
242 uint32_t handle)
243{
244 return drm_gem_handle_delete(file, handle);
245}
246
247/**
248 * Creates a new mm object and returns a handle to it.
249 */
250int
251i915_gem_create_ioctl(struct drm_device *dev, void *data,
252 struct drm_file *file)
253{
254 struct drm_i915_gem_create *args = data;
255
256 return i915_gem_create(file, dev,
257 args->size, &args->handle);
258}
259
260static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
261{
262 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
263
264 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
265 obj->tiling_mode != I915_TILING_NONE;
266}
267
268static inline int
269__copy_to_user_swizzled(char __user *cpu_vaddr,
270 const char *gpu_vaddr, int gpu_offset,
271 int length)
272{
273 int ret, cpu_offset = 0;
274
275 while (length > 0) {
276 int cacheline_end = ALIGN(gpu_offset + 1, 64);
277 int this_length = min(cacheline_end - gpu_offset, length);
278 int swizzled_gpu_offset = gpu_offset ^ 64;
279
280 ret = __copy_to_user(cpu_vaddr + cpu_offset,
281 gpu_vaddr + swizzled_gpu_offset,
282 this_length);
283 if (ret)
284 return ret + length;
285
286 cpu_offset += this_length;
287 gpu_offset += this_length;
288 length -= this_length;
289 }
290
291 return 0;
292}
293
294static inline int
295__copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
296 const char __user *cpu_vaddr,
297 int length)
298{
299 int ret, cpu_offset = 0;
300
301 while (length > 0) {
302 int cacheline_end = ALIGN(gpu_offset + 1, 64);
303 int this_length = min(cacheline_end - gpu_offset, length);
304 int swizzled_gpu_offset = gpu_offset ^ 64;
305
306 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
307 cpu_vaddr + cpu_offset,
308 this_length);
309 if (ret)
310 return ret + length;
311
312 cpu_offset += this_length;
313 gpu_offset += this_length;
314 length -= this_length;
315 }
316
317 return 0;
318}
319
320/* Per-page copy function for the shmem pread fastpath.
321 * Flushes invalid cachelines before reading the target if
322 * needs_clflush is set. */
323static int
324shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
325 char __user *user_data,
326 bool page_do_bit17_swizzling, bool needs_clflush)
327{
328 char *vaddr;
329 int ret;
330
331 if (unlikely(page_do_bit17_swizzling))
332 return -EINVAL;
333
334 vaddr = kmap_atomic(page);
335 if (needs_clflush)
336 drm_clflush_virt_range(vaddr + shmem_page_offset,
337 page_length);
338 ret = __copy_to_user_inatomic(user_data,
339 vaddr + shmem_page_offset,
340 page_length);
341 kunmap_atomic(vaddr);
342
343 return ret;
344}
345
346static void
347shmem_clflush_swizzled_range(char *addr, unsigned long length,
348 bool swizzled)
349{
350 if (unlikely(swizzled)) {
351 unsigned long start = (unsigned long) addr;
352 unsigned long end = (unsigned long) addr + length;
353
354 /* For swizzling simply ensure that we always flush both
355 * channels. Lame, but simple and it works. Swizzled
356 * pwrite/pread is far from a hotpath - current userspace
357 * doesn't use it at all. */
358 start = round_down(start, 128);
359 end = round_up(end, 128);
360
361 drm_clflush_virt_range((void *)start, end - start);
362 } else {
363 drm_clflush_virt_range(addr, length);
364 }
365
366}
367
368/* Only difference to the fast-path function is that this can handle bit17
369 * and uses non-atomic copy and kmap functions. */
370static int
371shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
372 char __user *user_data,
373 bool page_do_bit17_swizzling, bool needs_clflush)
374{
375 char *vaddr;
376 int ret;
377
378 vaddr = kmap(page);
379 if (needs_clflush)
380 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
381 page_length,
382 page_do_bit17_swizzling);
383
384 if (page_do_bit17_swizzling)
385 ret = __copy_to_user_swizzled(user_data,
386 vaddr, shmem_page_offset,
387 page_length);
388 else
389 ret = __copy_to_user(user_data,
390 vaddr + shmem_page_offset,
391 page_length);
392 kunmap(page);
393
394 return ret;
395}
396
397static int
398i915_gem_shmem_pread(struct drm_device *dev,
399 struct drm_i915_gem_object *obj,
400 struct drm_i915_gem_pread *args,
401 struct drm_file *file)
402{
403 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
404 char __user *user_data;
405 ssize_t remain;
406 loff_t offset;
407 int shmem_page_offset, page_length, ret = 0;
408 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
409 int hit_slowpath = 0;
410 int prefaulted = 0;
411 int needs_clflush = 0;
412 int release_page;
413
414 user_data = (char __user *) (uintptr_t) args->data_ptr;
415 remain = args->size;
416
417 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
418
419 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
420 /* If we're not in the cpu read domain, set ourself into the gtt
421 * read domain and manually flush cachelines (if required). This
422 * optimizes for the case when the gpu will dirty the data
423 * anyway again before the next pread happens. */
424 if (obj->cache_level == I915_CACHE_NONE)
425 needs_clflush = 1;
426 ret = i915_gem_object_set_to_gtt_domain(obj, false);
427 if (ret)
428 return ret;
429 }
430
431 offset = args->offset;
432
433 while (remain > 0) {
434 struct page *page;
435
436 /* Operation in this page
437 *
438 * shmem_page_offset = offset within page in shmem file
439 * page_length = bytes to copy for this page
440 */
441 shmem_page_offset = offset_in_page(offset);
442 page_length = remain;
443 if ((shmem_page_offset + page_length) > PAGE_SIZE)
444 page_length = PAGE_SIZE - shmem_page_offset;
445
446 if (obj->pages) {
447 page = obj->pages[offset >> PAGE_SHIFT];
448 release_page = 0;
449 } else {
450 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
451 if (IS_ERR(page)) {
452 ret = PTR_ERR(page);
453 goto out;
454 }
455 release_page = 1;
456 }
457
458 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
459 (page_to_phys(page) & (1 << 17)) != 0;
460
461 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
462 user_data, page_do_bit17_swizzling,
463 needs_clflush);
464 if (ret == 0)
465 goto next_page;
466
467 hit_slowpath = 1;
468 page_cache_get(page);
469 mutex_unlock(&dev->struct_mutex);
470
471 if (!prefaulted) {
472 ret = fault_in_multipages_writeable(user_data, remain);
473 /* Userspace is tricking us, but we've already clobbered
474 * its pages with the prefault and promised to write the
475 * data up to the first fault. Hence ignore any errors
476 * and just continue. */
477 (void)ret;
478 prefaulted = 1;
479 }
480
481 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
482 user_data, page_do_bit17_swizzling,
483 needs_clflush);
484
485 mutex_lock(&dev->struct_mutex);
486 page_cache_release(page);
487next_page:
488 mark_page_accessed(page);
489 if (release_page)
490 page_cache_release(page);
491
492 if (ret) {
493 ret = -EFAULT;
494 goto out;
495 }
496
497 remain -= page_length;
498 user_data += page_length;
499 offset += page_length;
500 }
501
502out:
503 if (hit_slowpath) {
504 /* Fixup: Kill any reinstated backing storage pages */
505 if (obj->madv == __I915_MADV_PURGED)
506 i915_gem_object_truncate(obj);
507 }
508
509 return ret;
510}
511
512/**
513 * Reads data from the object referenced by handle.
514 *
515 * On error, the contents of *data are undefined.
516 */
517int
518i915_gem_pread_ioctl(struct drm_device *dev, void *data,
519 struct drm_file *file)
520{
521 struct drm_i915_gem_pread *args = data;
522 struct drm_i915_gem_object *obj;
523 int ret = 0;
524
525 if (args->size == 0)
526 return 0;
527
528 if (!access_ok(VERIFY_WRITE,
529 (char __user *)(uintptr_t)args->data_ptr,
530 args->size))
531 return -EFAULT;
532
533 ret = i915_mutex_lock_interruptible(dev);
534 if (ret)
535 return ret;
536
537 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
538 if (&obj->base == NULL) {
539 ret = -ENOENT;
540 goto unlock;
541 }
542
543 /* Bounds check source. */
544 if (args->offset > obj->base.size ||
545 args->size > obj->base.size - args->offset) {
546 ret = -EINVAL;
547 goto out;
548 }
549
550 /* prime objects have no backing filp to GEM pread/pwrite
551 * pages from.
552 */
553 if (!obj->base.filp) {
554 ret = -EINVAL;
555 goto out;
556 }
557
558 trace_i915_gem_object_pread(obj, args->offset, args->size);
559
560 ret = i915_gem_shmem_pread(dev, obj, args, file);
561
562out:
563 drm_gem_object_unreference(&obj->base);
564unlock:
565 mutex_unlock(&dev->struct_mutex);
566 return ret;
567}
568
569/* This is the fast write path which cannot handle
570 * page faults in the source data
571 */
572
573static inline int
574fast_user_write(struct io_mapping *mapping,
575 loff_t page_base, int page_offset,
576 char __user *user_data,
577 int length)
578{
579 void __iomem *vaddr_atomic;
580 void *vaddr;
581 unsigned long unwritten;
582
583 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
584 /* We can use the cpu mem copy function because this is X86. */
585 vaddr = (void __force*)vaddr_atomic + page_offset;
586 unwritten = __copy_from_user_inatomic_nocache(vaddr,
587 user_data, length);
588 io_mapping_unmap_atomic(vaddr_atomic);
589 return unwritten;
590}
591
592/**
593 * This is the fast pwrite path, where we copy the data directly from the
594 * user into the GTT, uncached.
595 */
596static int
597i915_gem_gtt_pwrite_fast(struct drm_device *dev,
598 struct drm_i915_gem_object *obj,
599 struct drm_i915_gem_pwrite *args,
600 struct drm_file *file)
601{
602 drm_i915_private_t *dev_priv = dev->dev_private;
603 ssize_t remain;
604 loff_t offset, page_base;
605 char __user *user_data;
606 int page_offset, page_length, ret;
607
608 ret = i915_gem_object_pin(obj, 0, true);
609 if (ret)
610 goto out;
611
612 ret = i915_gem_object_set_to_gtt_domain(obj, true);
613 if (ret)
614 goto out_unpin;
615
616 ret = i915_gem_object_put_fence(obj);
617 if (ret)
618 goto out_unpin;
619
620 user_data = (char __user *) (uintptr_t) args->data_ptr;
621 remain = args->size;
622
623 offset = obj->gtt_offset + args->offset;
624
625 while (remain > 0) {
626 /* Operation in this page
627 *
628 * page_base = page offset within aperture
629 * page_offset = offset within page
630 * page_length = bytes to copy for this page
631 */
632 page_base = offset & PAGE_MASK;
633 page_offset = offset_in_page(offset);
634 page_length = remain;
635 if ((page_offset + remain) > PAGE_SIZE)
636 page_length = PAGE_SIZE - page_offset;
637
638 /* If we get a fault while copying data, then (presumably) our
639 * source page isn't available. Return the error and we'll
640 * retry in the slow path.
641 */
642 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
643 page_offset, user_data, page_length)) {
644 ret = -EFAULT;
645 goto out_unpin;
646 }
647
648 remain -= page_length;
649 user_data += page_length;
650 offset += page_length;
651 }
652
653out_unpin:
654 i915_gem_object_unpin(obj);
655out:
656 return ret;
657}
658
659/* Per-page copy function for the shmem pwrite fastpath.
660 * Flushes invalid cachelines before writing to the target if
661 * needs_clflush_before is set and flushes out any written cachelines after
662 * writing if needs_clflush is set. */
663static int
664shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
665 char __user *user_data,
666 bool page_do_bit17_swizzling,
667 bool needs_clflush_before,
668 bool needs_clflush_after)
669{
670 char *vaddr;
671 int ret;
672
673 if (unlikely(page_do_bit17_swizzling))
674 return -EINVAL;
675
676 vaddr = kmap_atomic(page);
677 if (needs_clflush_before)
678 drm_clflush_virt_range(vaddr + shmem_page_offset,
679 page_length);
680 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
681 user_data,
682 page_length);
683 if (needs_clflush_after)
684 drm_clflush_virt_range(vaddr + shmem_page_offset,
685 page_length);
686 kunmap_atomic(vaddr);
687
688 return ret;
689}
690
691/* Only difference to the fast-path function is that this can handle bit17
692 * and uses non-atomic copy and kmap functions. */
693static int
694shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
695 char __user *user_data,
696 bool page_do_bit17_swizzling,
697 bool needs_clflush_before,
698 bool needs_clflush_after)
699{
700 char *vaddr;
701 int ret;
702
703 vaddr = kmap(page);
704 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
705 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
706 page_length,
707 page_do_bit17_swizzling);
708 if (page_do_bit17_swizzling)
709 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
710 user_data,
711 page_length);
712 else
713 ret = __copy_from_user(vaddr + shmem_page_offset,
714 user_data,
715 page_length);
716 if (needs_clflush_after)
717 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
718 page_length,
719 page_do_bit17_swizzling);
720 kunmap(page);
721
722 return ret;
723}
724
725static int
726i915_gem_shmem_pwrite(struct drm_device *dev,
727 struct drm_i915_gem_object *obj,
728 struct drm_i915_gem_pwrite *args,
729 struct drm_file *file)
730{
731 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
732 ssize_t remain;
733 loff_t offset;
734 char __user *user_data;
735 int shmem_page_offset, page_length, ret = 0;
736 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
737 int hit_slowpath = 0;
738 int needs_clflush_after = 0;
739 int needs_clflush_before = 0;
740 int release_page;
741
742 user_data = (char __user *) (uintptr_t) args->data_ptr;
743 remain = args->size;
744
745 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
746
747 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
748 /* If we're not in the cpu write domain, set ourself into the gtt
749 * write domain and manually flush cachelines (if required). This
750 * optimizes for the case when the gpu will use the data
751 * right away and we therefore have to clflush anyway. */
752 if (obj->cache_level == I915_CACHE_NONE)
753 needs_clflush_after = 1;
754 ret = i915_gem_object_set_to_gtt_domain(obj, true);
755 if (ret)
756 return ret;
757 }
758 /* Same trick applies for invalidate partially written cachelines before
759 * writing. */
760 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
761 && obj->cache_level == I915_CACHE_NONE)
762 needs_clflush_before = 1;
763
764 offset = args->offset;
765 obj->dirty = 1;
766
767 while (remain > 0) {
768 struct page *page;
769 int partial_cacheline_write;
770
771 /* Operation in this page
772 *
773 * shmem_page_offset = offset within page in shmem file
774 * page_length = bytes to copy for this page
775 */
776 shmem_page_offset = offset_in_page(offset);
777
778 page_length = remain;
779 if ((shmem_page_offset + page_length) > PAGE_SIZE)
780 page_length = PAGE_SIZE - shmem_page_offset;
781
782 /* If we don't overwrite a cacheline completely we need to be
783 * careful to have up-to-date data by first clflushing. Don't
784 * overcomplicate things and flush the entire patch. */
785 partial_cacheline_write = needs_clflush_before &&
786 ((shmem_page_offset | page_length)
787 & (boot_cpu_data.x86_clflush_size - 1));
788
789 if (obj->pages) {
790 page = obj->pages[offset >> PAGE_SHIFT];
791 release_page = 0;
792 } else {
793 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
794 if (IS_ERR(page)) {
795 ret = PTR_ERR(page);
796 goto out;
797 }
798 release_page = 1;
799 }
800
801 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
802 (page_to_phys(page) & (1 << 17)) != 0;
803
804 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
805 user_data, page_do_bit17_swizzling,
806 partial_cacheline_write,
807 needs_clflush_after);
808 if (ret == 0)
809 goto next_page;
810
811 hit_slowpath = 1;
812 page_cache_get(page);
813 mutex_unlock(&dev->struct_mutex);
814
815 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
816 user_data, page_do_bit17_swizzling,
817 partial_cacheline_write,
818 needs_clflush_after);
819
820 mutex_lock(&dev->struct_mutex);
821 page_cache_release(page);
822next_page:
823 set_page_dirty(page);
824 mark_page_accessed(page);
825 if (release_page)
826 page_cache_release(page);
827
828 if (ret) {
829 ret = -EFAULT;
830 goto out;
831 }
832
833 remain -= page_length;
834 user_data += page_length;
835 offset += page_length;
836 }
837
838out:
839 if (hit_slowpath) {
840 /* Fixup: Kill any reinstated backing storage pages */
841 if (obj->madv == __I915_MADV_PURGED)
842 i915_gem_object_truncate(obj);
843 /* and flush dirty cachelines in case the object isn't in the cpu write
844 * domain anymore. */
845 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
846 i915_gem_clflush_object(obj);
847 intel_gtt_chipset_flush();
848 }
849 }
850
851 if (needs_clflush_after)
852 intel_gtt_chipset_flush();
853
854 return ret;
855}
856
857/**
858 * Writes data to the object referenced by handle.
859 *
860 * On error, the contents of the buffer that were to be modified are undefined.
861 */
862int
863i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
864 struct drm_file *file)
865{
866 struct drm_i915_gem_pwrite *args = data;
867 struct drm_i915_gem_object *obj;
868 int ret;
869
870 if (args->size == 0)
871 return 0;
872
873 if (!access_ok(VERIFY_READ,
874 (char __user *)(uintptr_t)args->data_ptr,
875 args->size))
876 return -EFAULT;
877
878 ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr,
879 args->size);
880 if (ret)
881 return -EFAULT;
882
883 ret = i915_mutex_lock_interruptible(dev);
884 if (ret)
885 return ret;
886
887 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
888 if (&obj->base == NULL) {
889 ret = -ENOENT;
890 goto unlock;
891 }
892
893 /* Bounds check destination. */
894 if (args->offset > obj->base.size ||
895 args->size > obj->base.size - args->offset) {
896 ret = -EINVAL;
897 goto out;
898 }
899
900 /* prime objects have no backing filp to GEM pread/pwrite
901 * pages from.
902 */
903 if (!obj->base.filp) {
904 ret = -EINVAL;
905 goto out;
906 }
907
908 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
909
910 ret = -EFAULT;
911 /* We can only do the GTT pwrite on untiled buffers, as otherwise
912 * it would end up going through the fenced access, and we'll get
913 * different detiling behavior between reading and writing.
914 * pread/pwrite currently are reading and writing from the CPU
915 * perspective, requiring manual detiling by the client.
916 */
917 if (obj->phys_obj) {
918 ret = i915_gem_phys_pwrite(dev, obj, args, file);
919 goto out;
920 }
921
922 if (obj->gtt_space &&
923 obj->cache_level == I915_CACHE_NONE &&
924 obj->tiling_mode == I915_TILING_NONE &&
925 obj->map_and_fenceable &&
926 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
927 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
928 /* Note that the gtt paths might fail with non-page-backed user
929 * pointers (e.g. gtt mappings when moving data between
930 * textures). Fallback to the shmem path in that case. */
931 }
932
933 if (ret == -EFAULT)
934 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
935
936out:
937 drm_gem_object_unreference(&obj->base);
938unlock:
939 mutex_unlock(&dev->struct_mutex);
940 return ret;
941}
942
943/**
944 * Called when user space prepares to use an object with the CPU, either
945 * through the mmap ioctl's mapping or a GTT mapping.
946 */
947int
948i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
949 struct drm_file *file)
950{
951 struct drm_i915_gem_set_domain *args = data;
952 struct drm_i915_gem_object *obj;
953 uint32_t read_domains = args->read_domains;
954 uint32_t write_domain = args->write_domain;
955 int ret;
956
957 /* Only handle setting domains to types used by the CPU. */
958 if (write_domain & I915_GEM_GPU_DOMAINS)
959 return -EINVAL;
960
961 if (read_domains & I915_GEM_GPU_DOMAINS)
962 return -EINVAL;
963
964 /* Having something in the write domain implies it's in the read
965 * domain, and only that read domain. Enforce that in the request.
966 */
967 if (write_domain != 0 && read_domains != write_domain)
968 return -EINVAL;
969
970 ret = i915_mutex_lock_interruptible(dev);
971 if (ret)
972 return ret;
973
974 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
975 if (&obj->base == NULL) {
976 ret = -ENOENT;
977 goto unlock;
978 }
979
980 if (read_domains & I915_GEM_DOMAIN_GTT) {
981 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
982
983 /* Silently promote "you're not bound, there was nothing to do"
984 * to success, since the client was just asking us to
985 * make sure everything was done.
986 */
987 if (ret == -EINVAL)
988 ret = 0;
989 } else {
990 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
991 }
992
993 drm_gem_object_unreference(&obj->base);
994unlock:
995 mutex_unlock(&dev->struct_mutex);
996 return ret;
997}
998
999/**
1000 * Called when user space has done writes to this buffer
1001 */
1002int
1003i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1004 struct drm_file *file)
1005{
1006 struct drm_i915_gem_sw_finish *args = data;
1007 struct drm_i915_gem_object *obj;
1008 int ret = 0;
1009
1010 ret = i915_mutex_lock_interruptible(dev);
1011 if (ret)
1012 return ret;
1013
1014 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1015 if (&obj->base == NULL) {
1016 ret = -ENOENT;
1017 goto unlock;
1018 }
1019
1020 /* Pinned buffers may be scanout, so flush the cache */
1021 if (obj->pin_count)
1022 i915_gem_object_flush_cpu_write_domain(obj);
1023
1024 drm_gem_object_unreference(&obj->base);
1025unlock:
1026 mutex_unlock(&dev->struct_mutex);
1027 return ret;
1028}
1029
1030/**
1031 * Maps the contents of an object, returning the address it is mapped
1032 * into.
1033 *
1034 * While the mapping holds a reference on the contents of the object, it doesn't
1035 * imply a ref on the object itself.
1036 */
1037int
1038i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1039 struct drm_file *file)
1040{
1041 struct drm_i915_gem_mmap *args = data;
1042 struct drm_gem_object *obj;
1043 unsigned long addr;
1044
1045 obj = drm_gem_object_lookup(dev, file, args->handle);
1046 if (obj == NULL)
1047 return -ENOENT;
1048
1049 /* prime objects have no backing filp to GEM mmap
1050 * pages from.
1051 */
1052 if (!obj->filp) {
1053 drm_gem_object_unreference_unlocked(obj);
1054 return -EINVAL;
1055 }
1056
1057 addr = vm_mmap(obj->filp, 0, args->size,
1058 PROT_READ | PROT_WRITE, MAP_SHARED,
1059 args->offset);
1060 drm_gem_object_unreference_unlocked(obj);
1061 if (IS_ERR((void *)addr))
1062 return addr;
1063
1064 args->addr_ptr = (uint64_t) addr;
1065
1066 return 0;
1067}
1068
1069/**
1070 * i915_gem_fault - fault a page into the GTT
1071 * vma: VMA in question
1072 * vmf: fault info
1073 *
1074 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1075 * from userspace. The fault handler takes care of binding the object to
1076 * the GTT (if needed), allocating and programming a fence register (again,
1077 * only if needed based on whether the old reg is still valid or the object
1078 * is tiled) and inserting a new PTE into the faulting process.
1079 *
1080 * Note that the faulting process may involve evicting existing objects
1081 * from the GTT and/or fence registers to make room. So performance may
1082 * suffer if the GTT working set is large or there are few fence registers
1083 * left.
1084 */
1085int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1086{
1087 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1088 struct drm_device *dev = obj->base.dev;
1089 drm_i915_private_t *dev_priv = dev->dev_private;
1090 pgoff_t page_offset;
1091 unsigned long pfn;
1092 int ret = 0;
1093 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1094
1095 /* We don't use vmf->pgoff since that has the fake offset */
1096 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1097 PAGE_SHIFT;
1098
1099 ret = i915_mutex_lock_interruptible(dev);
1100 if (ret)
1101 goto out;
1102
1103 trace_i915_gem_object_fault(obj, page_offset, true, write);
1104
1105 /* Now bind it into the GTT if needed */
1106 if (!obj->map_and_fenceable) {
1107 ret = i915_gem_object_unbind(obj);
1108 if (ret)
1109 goto unlock;
1110 }
1111 if (!obj->gtt_space) {
1112 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
1113 if (ret)
1114 goto unlock;
1115
1116 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1117 if (ret)
1118 goto unlock;
1119 }
1120
1121 if (!obj->has_global_gtt_mapping)
1122 i915_gem_gtt_bind_object(obj, obj->cache_level);
1123
1124 ret = i915_gem_object_get_fence(obj);
1125 if (ret)
1126 goto unlock;
1127
1128 if (i915_gem_object_is_inactive(obj))
1129 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1130
1131 obj->fault_mappable = true;
1132
1133 pfn = ((dev_priv->mm.gtt_base_addr + obj->gtt_offset) >> PAGE_SHIFT) +
1134 page_offset;
1135
1136 /* Finally, remap it using the new GTT offset */
1137 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1138unlock:
1139 mutex_unlock(&dev->struct_mutex);
1140out:
1141 switch (ret) {
1142 case -EIO:
1143 /* If this -EIO is due to a gpu hang, give the reset code a
1144 * chance to clean up the mess. Otherwise return the proper
1145 * SIGBUS. */
1146 if (!atomic_read(&dev_priv->mm.wedged))
1147 return VM_FAULT_SIGBUS;
1148 case -EAGAIN:
1149 /* Give the error handler a chance to run and move the
1150 * objects off the GPU active list. Next time we service the
1151 * fault, we should be able to transition the page into the
1152 * GTT without touching the GPU (and so avoid further
1153 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1154 * with coherency, just lost writes.
1155 */
1156 set_need_resched();
1157 case 0:
1158 case -ERESTARTSYS:
1159 case -EINTR:
1160 return VM_FAULT_NOPAGE;
1161 case -ENOMEM:
1162 return VM_FAULT_OOM;
1163 default:
1164 return VM_FAULT_SIGBUS;
1165 }
1166}
1167
1168/**
1169 * i915_gem_release_mmap - remove physical page mappings
1170 * @obj: obj in question
1171 *
1172 * Preserve the reservation of the mmapping with the DRM core code, but
1173 * relinquish ownership of the pages back to the system.
1174 *
1175 * It is vital that we remove the page mapping if we have mapped a tiled
1176 * object through the GTT and then lose the fence register due to
1177 * resource pressure. Similarly if the object has been moved out of the
1178 * aperture, than pages mapped into userspace must be revoked. Removing the
1179 * mapping will then trigger a page fault on the next user access, allowing
1180 * fixup by i915_gem_fault().
1181 */
1182void
1183i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1184{
1185 if (!obj->fault_mappable)
1186 return;
1187
1188 if (obj->base.dev->dev_mapping)
1189 unmap_mapping_range(obj->base.dev->dev_mapping,
1190 (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1191 obj->base.size, 1);
1192
1193 obj->fault_mappable = false;
1194}
1195
1196static uint32_t
1197i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1198{
1199 uint32_t gtt_size;
1200
1201 if (INTEL_INFO(dev)->gen >= 4 ||
1202 tiling_mode == I915_TILING_NONE)
1203 return size;
1204
1205 /* Previous chips need a power-of-two fence region when tiling */
1206 if (INTEL_INFO(dev)->gen == 3)
1207 gtt_size = 1024*1024;
1208 else
1209 gtt_size = 512*1024;
1210
1211 while (gtt_size < size)
1212 gtt_size <<= 1;
1213
1214 return gtt_size;
1215}
1216
1217/**
1218 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1219 * @obj: object to check
1220 *
1221 * Return the required GTT alignment for an object, taking into account
1222 * potential fence register mapping.
1223 */
1224static uint32_t
1225i915_gem_get_gtt_alignment(struct drm_device *dev,
1226 uint32_t size,
1227 int tiling_mode)
1228{
1229 /*
1230 * Minimum alignment is 4k (GTT page size), but might be greater
1231 * if a fence register is needed for the object.
1232 */
1233 if (INTEL_INFO(dev)->gen >= 4 ||
1234 tiling_mode == I915_TILING_NONE)
1235 return 4096;
1236
1237 /*
1238 * Previous chips need to be aligned to the size of the smallest
1239 * fence register that can contain the object.
1240 */
1241 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1242}
1243
1244/**
1245 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1246 * unfenced object
1247 * @dev: the device
1248 * @size: size of the object
1249 * @tiling_mode: tiling mode of the object
1250 *
1251 * Return the required GTT alignment for an object, only taking into account
1252 * unfenced tiled surface requirements.
1253 */
1254uint32_t
1255i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1256 uint32_t size,
1257 int tiling_mode)
1258{
1259 /*
1260 * Minimum alignment is 4k (GTT page size) for sane hw.
1261 */
1262 if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1263 tiling_mode == I915_TILING_NONE)
1264 return 4096;
1265
1266 /* Previous hardware however needs to be aligned to a power-of-two
1267 * tile height. The simplest method for determining this is to reuse
1268 * the power-of-tile object size.
1269 */
1270 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1271}
1272
1273int
1274i915_gem_mmap_gtt(struct drm_file *file,
1275 struct drm_device *dev,
1276 uint32_t handle,
1277 uint64_t *offset)
1278{
1279 struct drm_i915_private *dev_priv = dev->dev_private;
1280 struct drm_i915_gem_object *obj;
1281 int ret;
1282
1283 ret = i915_mutex_lock_interruptible(dev);
1284 if (ret)
1285 return ret;
1286
1287 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1288 if (&obj->base == NULL) {
1289 ret = -ENOENT;
1290 goto unlock;
1291 }
1292
1293 if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1294 ret = -E2BIG;
1295 goto out;
1296 }
1297
1298 if (obj->madv != I915_MADV_WILLNEED) {
1299 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1300 ret = -EINVAL;
1301 goto out;
1302 }
1303
1304 if (!obj->base.map_list.map) {
1305 ret = drm_gem_create_mmap_offset(&obj->base);
1306 if (ret)
1307 goto out;
1308 }
1309
1310 *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1311
1312out:
1313 drm_gem_object_unreference(&obj->base);
1314unlock:
1315 mutex_unlock(&dev->struct_mutex);
1316 return ret;
1317}
1318
1319/**
1320 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1321 * @dev: DRM device
1322 * @data: GTT mapping ioctl data
1323 * @file: GEM object info
1324 *
1325 * Simply returns the fake offset to userspace so it can mmap it.
1326 * The mmap call will end up in drm_gem_mmap(), which will set things
1327 * up so we can get faults in the handler above.
1328 *
1329 * The fault handler will take care of binding the object into the GTT
1330 * (since it may have been evicted to make room for something), allocating
1331 * a fence register, and mapping the appropriate aperture address into
1332 * userspace.
1333 */
1334int
1335i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1336 struct drm_file *file)
1337{
1338 struct drm_i915_gem_mmap_gtt *args = data;
1339
1340 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1341}
1342
1343int
1344i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
1345 gfp_t gfpmask)
1346{
1347 int page_count, i;
1348 struct address_space *mapping;
1349 struct inode *inode;
1350 struct page *page;
1351
1352 if (obj->pages || obj->sg_table)
1353 return 0;
1354
1355 /* Get the list of pages out of our struct file. They'll be pinned
1356 * at this point until we release them.
1357 */
1358 page_count = obj->base.size / PAGE_SIZE;
1359 BUG_ON(obj->pages != NULL);
1360 obj->pages = drm_malloc_ab(page_count, sizeof(struct page *));
1361 if (obj->pages == NULL)
1362 return -ENOMEM;
1363
1364 inode = obj->base.filp->f_path.dentry->d_inode;
1365 mapping = inode->i_mapping;
1366 gfpmask |= mapping_gfp_mask(mapping);
1367
1368 for (i = 0; i < page_count; i++) {
1369 page = shmem_read_mapping_page_gfp(mapping, i, gfpmask);
1370 if (IS_ERR(page))
1371 goto err_pages;
1372
1373 obj->pages[i] = page;
1374 }
1375
1376 if (i915_gem_object_needs_bit17_swizzle(obj))
1377 i915_gem_object_do_bit_17_swizzle(obj);
1378
1379 return 0;
1380
1381err_pages:
1382 while (i--)
1383 page_cache_release(obj->pages[i]);
1384
1385 drm_free_large(obj->pages);
1386 obj->pages = NULL;
1387 return PTR_ERR(page);
1388}
1389
1390static void
1391i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1392{
1393 int page_count = obj->base.size / PAGE_SIZE;
1394 int i;
1395
1396 if (!obj->pages)
1397 return;
1398
1399 BUG_ON(obj->madv == __I915_MADV_PURGED);
1400
1401 if (i915_gem_object_needs_bit17_swizzle(obj))
1402 i915_gem_object_save_bit_17_swizzle(obj);
1403
1404 if (obj->madv == I915_MADV_DONTNEED)
1405 obj->dirty = 0;
1406
1407 for (i = 0; i < page_count; i++) {
1408 if (obj->dirty)
1409 set_page_dirty(obj->pages[i]);
1410
1411 if (obj->madv == I915_MADV_WILLNEED)
1412 mark_page_accessed(obj->pages[i]);
1413
1414 page_cache_release(obj->pages[i]);
1415 }
1416 obj->dirty = 0;
1417
1418 drm_free_large(obj->pages);
1419 obj->pages = NULL;
1420}
1421
1422void
1423i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1424 struct intel_ring_buffer *ring,
1425 u32 seqno)
1426{
1427 struct drm_device *dev = obj->base.dev;
1428 struct drm_i915_private *dev_priv = dev->dev_private;
1429
1430 BUG_ON(ring == NULL);
1431 obj->ring = ring;
1432
1433 /* Add a reference if we're newly entering the active list. */
1434 if (!obj->active) {
1435 drm_gem_object_reference(&obj->base);
1436 obj->active = 1;
1437 }
1438
1439 /* Move from whatever list we were on to the tail of execution. */
1440 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1441 list_move_tail(&obj->ring_list, &ring->active_list);
1442
1443 obj->last_read_seqno = seqno;
1444
1445 if (obj->fenced_gpu_access) {
1446 obj->last_fenced_seqno = seqno;
1447
1448 /* Bump MRU to take account of the delayed flush */
1449 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1450 struct drm_i915_fence_reg *reg;
1451
1452 reg = &dev_priv->fence_regs[obj->fence_reg];
1453 list_move_tail(&reg->lru_list,
1454 &dev_priv->mm.fence_list);
1455 }
1456 }
1457}
1458
1459static void
1460i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1461{
1462 struct drm_device *dev = obj->base.dev;
1463 struct drm_i915_private *dev_priv = dev->dev_private;
1464
1465 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1466 BUG_ON(!obj->active);
1467
1468 if (obj->pin_count) /* are we a framebuffer? */
1469 intel_mark_fb_idle(obj);
1470
1471 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1472
1473 list_del_init(&obj->ring_list);
1474 obj->ring = NULL;
1475
1476 obj->last_read_seqno = 0;
1477 obj->last_write_seqno = 0;
1478 obj->base.write_domain = 0;
1479
1480 obj->last_fenced_seqno = 0;
1481 obj->fenced_gpu_access = false;
1482
1483 obj->active = 0;
1484 drm_gem_object_unreference(&obj->base);
1485
1486 WARN_ON(i915_verify_lists(dev));
1487}
1488
1489/* Immediately discard the backing storage */
1490static void
1491i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1492{
1493 struct inode *inode;
1494
1495 /* Our goal here is to return as much of the memory as
1496 * is possible back to the system as we are called from OOM.
1497 * To do this we must instruct the shmfs to drop all of its
1498 * backing pages, *now*.
1499 */
1500 inode = obj->base.filp->f_path.dentry->d_inode;
1501 shmem_truncate_range(inode, 0, (loff_t)-1);
1502
1503 if (obj->base.map_list.map)
1504 drm_gem_free_mmap_offset(&obj->base);
1505
1506 obj->madv = __I915_MADV_PURGED;
1507}
1508
1509static inline int
1510i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1511{
1512 return obj->madv == I915_MADV_DONTNEED;
1513}
1514
1515static u32
1516i915_gem_get_seqno(struct drm_device *dev)
1517{
1518 drm_i915_private_t *dev_priv = dev->dev_private;
1519 u32 seqno = dev_priv->next_seqno;
1520
1521 /* reserve 0 for non-seqno */
1522 if (++dev_priv->next_seqno == 0)
1523 dev_priv->next_seqno = 1;
1524
1525 return seqno;
1526}
1527
1528u32
1529i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
1530{
1531 if (ring->outstanding_lazy_request == 0)
1532 ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev);
1533
1534 return ring->outstanding_lazy_request;
1535}
1536
1537int
1538i915_add_request(struct intel_ring_buffer *ring,
1539 struct drm_file *file,
1540 struct drm_i915_gem_request *request)
1541{
1542 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1543 uint32_t seqno;
1544 u32 request_ring_position;
1545 int was_empty;
1546 int ret;
1547
1548 /*
1549 * Emit any outstanding flushes - execbuf can fail to emit the flush
1550 * after having emitted the batchbuffer command. Hence we need to fix
1551 * things up similar to emitting the lazy request. The difference here
1552 * is that the flush _must_ happen before the next request, no matter
1553 * what.
1554 */
1555 ret = intel_ring_flush_all_caches(ring);
1556 if (ret)
1557 return ret;
1558
1559 if (request == NULL) {
1560 request = kmalloc(sizeof(*request), GFP_KERNEL);
1561 if (request == NULL)
1562 return -ENOMEM;
1563 }
1564
1565 seqno = i915_gem_next_request_seqno(ring);
1566
1567 /* Record the position of the start of the request so that
1568 * should we detect the updated seqno part-way through the
1569 * GPU processing the request, we never over-estimate the
1570 * position of the head.
1571 */
1572 request_ring_position = intel_ring_get_tail(ring);
1573
1574 ret = ring->add_request(ring, &seqno);
1575 if (ret) {
1576 kfree(request);
1577 return ret;
1578 }
1579
1580 trace_i915_gem_request_add(ring, seqno);
1581
1582 request->seqno = seqno;
1583 request->ring = ring;
1584 request->tail = request_ring_position;
1585 request->emitted_jiffies = jiffies;
1586 was_empty = list_empty(&ring->request_list);
1587 list_add_tail(&request->list, &ring->request_list);
1588 request->file_priv = NULL;
1589
1590 if (file) {
1591 struct drm_i915_file_private *file_priv = file->driver_priv;
1592
1593 spin_lock(&file_priv->mm.lock);
1594 request->file_priv = file_priv;
1595 list_add_tail(&request->client_list,
1596 &file_priv->mm.request_list);
1597 spin_unlock(&file_priv->mm.lock);
1598 }
1599
1600 ring->outstanding_lazy_request = 0;
1601
1602 if (!dev_priv->mm.suspended) {
1603 if (i915_enable_hangcheck) {
1604 mod_timer(&dev_priv->hangcheck_timer,
1605 jiffies +
1606 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1607 }
1608 if (was_empty) {
1609 queue_delayed_work(dev_priv->wq,
1610 &dev_priv->mm.retire_work, HZ);
1611 intel_mark_busy(dev_priv->dev);
1612 }
1613 }
1614
1615 return 0;
1616}
1617
1618static inline void
1619i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1620{
1621 struct drm_i915_file_private *file_priv = request->file_priv;
1622
1623 if (!file_priv)
1624 return;
1625
1626 spin_lock(&file_priv->mm.lock);
1627 if (request->file_priv) {
1628 list_del(&request->client_list);
1629 request->file_priv = NULL;
1630 }
1631 spin_unlock(&file_priv->mm.lock);
1632}
1633
1634static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1635 struct intel_ring_buffer *ring)
1636{
1637 while (!list_empty(&ring->request_list)) {
1638 struct drm_i915_gem_request *request;
1639
1640 request = list_first_entry(&ring->request_list,
1641 struct drm_i915_gem_request,
1642 list);
1643
1644 list_del(&request->list);
1645 i915_gem_request_remove_from_client(request);
1646 kfree(request);
1647 }
1648
1649 while (!list_empty(&ring->active_list)) {
1650 struct drm_i915_gem_object *obj;
1651
1652 obj = list_first_entry(&ring->active_list,
1653 struct drm_i915_gem_object,
1654 ring_list);
1655
1656 i915_gem_object_move_to_inactive(obj);
1657 }
1658}
1659
1660static void i915_gem_reset_fences(struct drm_device *dev)
1661{
1662 struct drm_i915_private *dev_priv = dev->dev_private;
1663 int i;
1664
1665 for (i = 0; i < dev_priv->num_fence_regs; i++) {
1666 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
1667
1668 i915_gem_write_fence(dev, i, NULL);
1669
1670 if (reg->obj)
1671 i915_gem_object_fence_lost(reg->obj);
1672
1673 reg->pin_count = 0;
1674 reg->obj = NULL;
1675 INIT_LIST_HEAD(&reg->lru_list);
1676 }
1677
1678 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
1679}
1680
1681void i915_gem_reset(struct drm_device *dev)
1682{
1683 struct drm_i915_private *dev_priv = dev->dev_private;
1684 struct drm_i915_gem_object *obj;
1685 struct intel_ring_buffer *ring;
1686 int i;
1687
1688 for_each_ring(ring, dev_priv, i)
1689 i915_gem_reset_ring_lists(dev_priv, ring);
1690
1691 /* Move everything out of the GPU domains to ensure we do any
1692 * necessary invalidation upon reuse.
1693 */
1694 list_for_each_entry(obj,
1695 &dev_priv->mm.inactive_list,
1696 mm_list)
1697 {
1698 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1699 }
1700
1701 /* The fence registers are invalidated so clear them out */
1702 i915_gem_reset_fences(dev);
1703}
1704
1705/**
1706 * This function clears the request list as sequence numbers are passed.
1707 */
1708void
1709i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
1710{
1711 uint32_t seqno;
1712 int i;
1713
1714 if (list_empty(&ring->request_list))
1715 return;
1716
1717 WARN_ON(i915_verify_lists(ring->dev));
1718
1719 seqno = ring->get_seqno(ring);
1720
1721 for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++)
1722 if (seqno >= ring->sync_seqno[i])
1723 ring->sync_seqno[i] = 0;
1724
1725 while (!list_empty(&ring->request_list)) {
1726 struct drm_i915_gem_request *request;
1727
1728 request = list_first_entry(&ring->request_list,
1729 struct drm_i915_gem_request,
1730 list);
1731
1732 if (!i915_seqno_passed(seqno, request->seqno))
1733 break;
1734
1735 trace_i915_gem_request_retire(ring, request->seqno);
1736 /* We know the GPU must have read the request to have
1737 * sent us the seqno + interrupt, so use the position
1738 * of tail of the request to update the last known position
1739 * of the GPU head.
1740 */
1741 ring->last_retired_head = request->tail;
1742
1743 list_del(&request->list);
1744 i915_gem_request_remove_from_client(request);
1745 kfree(request);
1746 }
1747
1748 /* Move any buffers on the active list that are no longer referenced
1749 * by the ringbuffer to the flushing/inactive lists as appropriate.
1750 */
1751 while (!list_empty(&ring->active_list)) {
1752 struct drm_i915_gem_object *obj;
1753
1754 obj = list_first_entry(&ring->active_list,
1755 struct drm_i915_gem_object,
1756 ring_list);
1757
1758 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
1759 break;
1760
1761 i915_gem_object_move_to_inactive(obj);
1762 }
1763
1764 if (unlikely(ring->trace_irq_seqno &&
1765 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
1766 ring->irq_put(ring);
1767 ring->trace_irq_seqno = 0;
1768 }
1769
1770 WARN_ON(i915_verify_lists(ring->dev));
1771}
1772
1773void
1774i915_gem_retire_requests(struct drm_device *dev)
1775{
1776 drm_i915_private_t *dev_priv = dev->dev_private;
1777 struct intel_ring_buffer *ring;
1778 int i;
1779
1780 for_each_ring(ring, dev_priv, i)
1781 i915_gem_retire_requests_ring(ring);
1782}
1783
1784static void
1785i915_gem_retire_work_handler(struct work_struct *work)
1786{
1787 drm_i915_private_t *dev_priv;
1788 struct drm_device *dev;
1789 struct intel_ring_buffer *ring;
1790 bool idle;
1791 int i;
1792
1793 dev_priv = container_of(work, drm_i915_private_t,
1794 mm.retire_work.work);
1795 dev = dev_priv->dev;
1796
1797 /* Come back later if the device is busy... */
1798 if (!mutex_trylock(&dev->struct_mutex)) {
1799 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1800 return;
1801 }
1802
1803 i915_gem_retire_requests(dev);
1804
1805 /* Send a periodic flush down the ring so we don't hold onto GEM
1806 * objects indefinitely.
1807 */
1808 idle = true;
1809 for_each_ring(ring, dev_priv, i) {
1810 if (ring->gpu_caches_dirty)
1811 i915_add_request(ring, NULL, NULL);
1812
1813 idle &= list_empty(&ring->request_list);
1814 }
1815
1816 if (!dev_priv->mm.suspended && !idle)
1817 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1818 if (idle)
1819 intel_mark_idle(dev);
1820
1821 mutex_unlock(&dev->struct_mutex);
1822}
1823
1824int
1825i915_gem_check_wedge(struct drm_i915_private *dev_priv,
1826 bool interruptible)
1827{
1828 if (atomic_read(&dev_priv->mm.wedged)) {
1829 struct completion *x = &dev_priv->error_completion;
1830 bool recovery_complete;
1831 unsigned long flags;
1832
1833 /* Give the error handler a chance to run. */
1834 spin_lock_irqsave(&x->wait.lock, flags);
1835 recovery_complete = x->done > 0;
1836 spin_unlock_irqrestore(&x->wait.lock, flags);
1837
1838 /* Non-interruptible callers can't handle -EAGAIN, hence return
1839 * -EIO unconditionally for these. */
1840 if (!interruptible)
1841 return -EIO;
1842
1843 /* Recovery complete, but still wedged means reset failure. */
1844 if (recovery_complete)
1845 return -EIO;
1846
1847 return -EAGAIN;
1848 }
1849
1850 return 0;
1851}
1852
1853/*
1854 * Compare seqno against outstanding lazy request. Emit a request if they are
1855 * equal.
1856 */
1857static int
1858i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
1859{
1860 int ret;
1861
1862 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1863
1864 ret = 0;
1865 if (seqno == ring->outstanding_lazy_request)
1866 ret = i915_add_request(ring, NULL, NULL);
1867
1868 return ret;
1869}
1870
1871/**
1872 * __wait_seqno - wait until execution of seqno has finished
1873 * @ring: the ring expected to report seqno
1874 * @seqno: duh!
1875 * @interruptible: do an interruptible wait (normally yes)
1876 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1877 *
1878 * Returns 0 if the seqno was found within the alloted time. Else returns the
1879 * errno with remaining time filled in timeout argument.
1880 */
1881static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
1882 bool interruptible, struct timespec *timeout)
1883{
1884 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1885 struct timespec before, now, wait_time={1,0};
1886 unsigned long timeout_jiffies;
1887 long end;
1888 bool wait_forever = true;
1889 int ret;
1890
1891 if (i915_seqno_passed(ring->get_seqno(ring), seqno))
1892 return 0;
1893
1894 trace_i915_gem_request_wait_begin(ring, seqno);
1895
1896 if (timeout != NULL) {
1897 wait_time = *timeout;
1898 wait_forever = false;
1899 }
1900
1901 timeout_jiffies = timespec_to_jiffies(&wait_time);
1902
1903 if (WARN_ON(!ring->irq_get(ring)))
1904 return -ENODEV;
1905
1906 /* Record current time in case interrupted by signal, or wedged * */
1907 getrawmonotonic(&before);
1908
1909#define EXIT_COND \
1910 (i915_seqno_passed(ring->get_seqno(ring), seqno) || \
1911 atomic_read(&dev_priv->mm.wedged))
1912 do {
1913 if (interruptible)
1914 end = wait_event_interruptible_timeout(ring->irq_queue,
1915 EXIT_COND,
1916 timeout_jiffies);
1917 else
1918 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1919 timeout_jiffies);
1920
1921 ret = i915_gem_check_wedge(dev_priv, interruptible);
1922 if (ret)
1923 end = ret;
1924 } while (end == 0 && wait_forever);
1925
1926 getrawmonotonic(&now);
1927
1928 ring->irq_put(ring);
1929 trace_i915_gem_request_wait_end(ring, seqno);
1930#undef EXIT_COND
1931
1932 if (timeout) {
1933 struct timespec sleep_time = timespec_sub(now, before);
1934 *timeout = timespec_sub(*timeout, sleep_time);
1935 }
1936
1937 switch (end) {
1938 case -EIO:
1939 case -EAGAIN: /* Wedged */
1940 case -ERESTARTSYS: /* Signal */
1941 return (int)end;
1942 case 0: /* Timeout */
1943 if (timeout)
1944 set_normalized_timespec(timeout, 0, 0);
1945 return -ETIME;
1946 default: /* Completed */
1947 WARN_ON(end < 0); /* We're not aware of other errors */
1948 return 0;
1949 }
1950}
1951
1952/**
1953 * Waits for a sequence number to be signaled, and cleans up the
1954 * request and object lists appropriately for that event.
1955 */
1956int
1957i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1958{
1959 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1960 int ret = 0;
1961
1962 BUG_ON(seqno == 0);
1963
1964 ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
1965 if (ret)
1966 return ret;
1967
1968 ret = i915_gem_check_olr(ring, seqno);
1969 if (ret)
1970 return ret;
1971
1972 ret = __wait_seqno(ring, seqno, dev_priv->mm.interruptible, NULL);
1973
1974 return ret;
1975}
1976
1977/**
1978 * Ensures that all rendering to the object has completed and the object is
1979 * safe to unbind from the GTT or access from the CPU.
1980 */
1981static __must_check int
1982i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1983 bool readonly)
1984{
1985 u32 seqno;
1986 int ret;
1987
1988 /* If there is rendering queued on the buffer being evicted, wait for
1989 * it.
1990 */
1991 if (readonly)
1992 seqno = obj->last_write_seqno;
1993 else
1994 seqno = obj->last_read_seqno;
1995 if (seqno == 0)
1996 return 0;
1997
1998 ret = i915_wait_seqno(obj->ring, seqno);
1999 if (ret)
2000 return ret;
2001
2002 /* Manually manage the write flush as we may have not yet retired
2003 * the buffer.
2004 */
2005 if (obj->last_write_seqno &&
2006 i915_seqno_passed(seqno, obj->last_write_seqno)) {
2007 obj->last_write_seqno = 0;
2008 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
2009 }
2010
2011 i915_gem_retire_requests_ring(obj->ring);
2012 return 0;
2013}
2014
2015/**
2016 * Ensures that an object will eventually get non-busy by flushing any required
2017 * write domains, emitting any outstanding lazy request and retiring and
2018 * completed requests.
2019 */
2020static int
2021i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2022{
2023 int ret;
2024
2025 if (obj->active) {
2026 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2027 if (ret)
2028 return ret;
2029
2030 i915_gem_retire_requests_ring(obj->ring);
2031 }
2032
2033 return 0;
2034}
2035
2036/**
2037 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2038 * @DRM_IOCTL_ARGS: standard ioctl arguments
2039 *
2040 * Returns 0 if successful, else an error is returned with the remaining time in
2041 * the timeout parameter.
2042 * -ETIME: object is still busy after timeout
2043 * -ERESTARTSYS: signal interrupted the wait
2044 * -ENONENT: object doesn't exist
2045 * Also possible, but rare:
2046 * -EAGAIN: GPU wedged
2047 * -ENOMEM: damn
2048 * -ENODEV: Internal IRQ fail
2049 * -E?: The add request failed
2050 *
2051 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2052 * non-zero timeout parameter the wait ioctl will wait for the given number of
2053 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2054 * without holding struct_mutex the object may become re-busied before this
2055 * function completes. A similar but shorter * race condition exists in the busy
2056 * ioctl
2057 */
2058int
2059i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2060{
2061 struct drm_i915_gem_wait *args = data;
2062 struct drm_i915_gem_object *obj;
2063 struct intel_ring_buffer *ring = NULL;
2064 struct timespec timeout_stack, *timeout = NULL;
2065 u32 seqno = 0;
2066 int ret = 0;
2067
2068 if (args->timeout_ns >= 0) {
2069 timeout_stack = ns_to_timespec(args->timeout_ns);
2070 timeout = &timeout_stack;
2071 }
2072
2073 ret = i915_mutex_lock_interruptible(dev);
2074 if (ret)
2075 return ret;
2076
2077 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2078 if (&obj->base == NULL) {
2079 mutex_unlock(&dev->struct_mutex);
2080 return -ENOENT;
2081 }
2082
2083 /* Need to make sure the object gets inactive eventually. */
2084 ret = i915_gem_object_flush_active(obj);
2085 if (ret)
2086 goto out;
2087
2088 if (obj->active) {
2089 seqno = obj->last_read_seqno;
2090 ring = obj->ring;
2091 }
2092
2093 if (seqno == 0)
2094 goto out;
2095
2096 /* Do this after OLR check to make sure we make forward progress polling
2097 * on this IOCTL with a 0 timeout (like busy ioctl)
2098 */
2099 if (!args->timeout_ns) {
2100 ret = -ETIME;
2101 goto out;
2102 }
2103
2104 drm_gem_object_unreference(&obj->base);
2105 mutex_unlock(&dev->struct_mutex);
2106
2107 ret = __wait_seqno(ring, seqno, true, timeout);
2108 if (timeout) {
2109 WARN_ON(!timespec_valid(timeout));
2110 args->timeout_ns = timespec_to_ns(timeout);
2111 }
2112 return ret;
2113
2114out:
2115 drm_gem_object_unreference(&obj->base);
2116 mutex_unlock(&dev->struct_mutex);
2117 return ret;
2118}
2119
2120/**
2121 * i915_gem_object_sync - sync an object to a ring.
2122 *
2123 * @obj: object which may be in use on another ring.
2124 * @to: ring we wish to use the object on. May be NULL.
2125 *
2126 * This code is meant to abstract object synchronization with the GPU.
2127 * Calling with NULL implies synchronizing the object with the CPU
2128 * rather than a particular GPU ring.
2129 *
2130 * Returns 0 if successful, else propagates up the lower layer error.
2131 */
2132int
2133i915_gem_object_sync(struct drm_i915_gem_object *obj,
2134 struct intel_ring_buffer *to)
2135{
2136 struct intel_ring_buffer *from = obj->ring;
2137 u32 seqno;
2138 int ret, idx;
2139
2140 if (from == NULL || to == from)
2141 return 0;
2142
2143 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2144 return i915_gem_object_wait_rendering(obj, false);
2145
2146 idx = intel_ring_sync_index(from, to);
2147
2148 seqno = obj->last_read_seqno;
2149 if (seqno <= from->sync_seqno[idx])
2150 return 0;
2151
2152 ret = i915_gem_check_olr(obj->ring, seqno);
2153 if (ret)
2154 return ret;
2155
2156 ret = to->sync_to(to, from, seqno);
2157 if (!ret)
2158 from->sync_seqno[idx] = seqno;
2159
2160 return ret;
2161}
2162
2163static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2164{
2165 u32 old_write_domain, old_read_domains;
2166
2167 /* Act a barrier for all accesses through the GTT */
2168 mb();
2169
2170 /* Force a pagefault for domain tracking on next user access */
2171 i915_gem_release_mmap(obj);
2172
2173 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2174 return;
2175
2176 old_read_domains = obj->base.read_domains;
2177 old_write_domain = obj->base.write_domain;
2178
2179 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2180 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2181
2182 trace_i915_gem_object_change_domain(obj,
2183 old_read_domains,
2184 old_write_domain);
2185}
2186
2187/**
2188 * Unbinds an object from the GTT aperture.
2189 */
2190int
2191i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2192{
2193 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2194 int ret = 0;
2195
2196 if (obj->gtt_space == NULL)
2197 return 0;
2198
2199 if (obj->pin_count)
2200 return -EBUSY;
2201
2202 ret = i915_gem_object_finish_gpu(obj);
2203 if (ret)
2204 return ret;
2205 /* Continue on if we fail due to EIO, the GPU is hung so we
2206 * should be safe and we need to cleanup or else we might
2207 * cause memory corruption through use-after-free.
2208 */
2209
2210 i915_gem_object_finish_gtt(obj);
2211
2212 /* Move the object to the CPU domain to ensure that
2213 * any possible CPU writes while it's not in the GTT
2214 * are flushed when we go to remap it.
2215 */
2216 if (ret == 0)
2217 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2218 if (ret == -ERESTARTSYS)
2219 return ret;
2220 if (ret) {
2221 /* In the event of a disaster, abandon all caches and
2222 * hope for the best.
2223 */
2224 i915_gem_clflush_object(obj);
2225 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2226 }
2227
2228 /* release the fence reg _after_ flushing */
2229 ret = i915_gem_object_put_fence(obj);
2230 if (ret)
2231 return ret;
2232
2233 trace_i915_gem_object_unbind(obj);
2234
2235 if (obj->has_global_gtt_mapping)
2236 i915_gem_gtt_unbind_object(obj);
2237 if (obj->has_aliasing_ppgtt_mapping) {
2238 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2239 obj->has_aliasing_ppgtt_mapping = 0;
2240 }
2241 i915_gem_gtt_finish_object(obj);
2242
2243 i915_gem_object_put_pages_gtt(obj);
2244
2245 list_del_init(&obj->gtt_list);
2246 list_del_init(&obj->mm_list);
2247 /* Avoid an unnecessary call to unbind on rebind. */
2248 obj->map_and_fenceable = true;
2249
2250 drm_mm_put_block(obj->gtt_space);
2251 obj->gtt_space = NULL;
2252 obj->gtt_offset = 0;
2253
2254 if (i915_gem_object_is_purgeable(obj))
2255 i915_gem_object_truncate(obj);
2256
2257 return ret;
2258}
2259
2260static int i915_ring_idle(struct intel_ring_buffer *ring)
2261{
2262 if (list_empty(&ring->active_list))
2263 return 0;
2264
2265 return i915_wait_seqno(ring, i915_gem_next_request_seqno(ring));
2266}
2267
2268int i915_gpu_idle(struct drm_device *dev)
2269{
2270 drm_i915_private_t *dev_priv = dev->dev_private;
2271 struct intel_ring_buffer *ring;
2272 int ret, i;
2273
2274 /* Flush everything onto the inactive list. */
2275 for_each_ring(ring, dev_priv, i) {
2276 ret = i915_ring_idle(ring);
2277 if (ret)
2278 return ret;
2279
2280 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2281 if (ret)
2282 return ret;
2283 }
2284
2285 return 0;
2286}
2287
2288static void sandybridge_write_fence_reg(struct drm_device *dev, int reg,
2289 struct drm_i915_gem_object *obj)
2290{
2291 drm_i915_private_t *dev_priv = dev->dev_private;
2292 uint64_t val;
2293
2294 if (obj) {
2295 u32 size = obj->gtt_space->size;
2296
2297 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2298 0xfffff000) << 32;
2299 val |= obj->gtt_offset & 0xfffff000;
2300 val |= (uint64_t)((obj->stride / 128) - 1) <<
2301 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2302
2303 if (obj->tiling_mode == I915_TILING_Y)
2304 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2305 val |= I965_FENCE_REG_VALID;
2306 } else
2307 val = 0;
2308
2309 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val);
2310 POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8);
2311}
2312
2313static void i965_write_fence_reg(struct drm_device *dev, int reg,
2314 struct drm_i915_gem_object *obj)
2315{
2316 drm_i915_private_t *dev_priv = dev->dev_private;
2317 uint64_t val;
2318
2319 if (obj) {
2320 u32 size = obj->gtt_space->size;
2321
2322 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2323 0xfffff000) << 32;
2324 val |= obj->gtt_offset & 0xfffff000;
2325 val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2326 if (obj->tiling_mode == I915_TILING_Y)
2327 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2328 val |= I965_FENCE_REG_VALID;
2329 } else
2330 val = 0;
2331
2332 I915_WRITE64(FENCE_REG_965_0 + reg * 8, val);
2333 POSTING_READ(FENCE_REG_965_0 + reg * 8);
2334}
2335
2336static void i915_write_fence_reg(struct drm_device *dev, int reg,
2337 struct drm_i915_gem_object *obj)
2338{
2339 drm_i915_private_t *dev_priv = dev->dev_private;
2340 u32 val;
2341
2342 if (obj) {
2343 u32 size = obj->gtt_space->size;
2344 int pitch_val;
2345 int tile_width;
2346
2347 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2348 (size & -size) != size ||
2349 (obj->gtt_offset & (size - 1)),
2350 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2351 obj->gtt_offset, obj->map_and_fenceable, size);
2352
2353 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2354 tile_width = 128;
2355 else
2356 tile_width = 512;
2357
2358 /* Note: pitch better be a power of two tile widths */
2359 pitch_val = obj->stride / tile_width;
2360 pitch_val = ffs(pitch_val) - 1;
2361
2362 val = obj->gtt_offset;
2363 if (obj->tiling_mode == I915_TILING_Y)
2364 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2365 val |= I915_FENCE_SIZE_BITS(size);
2366 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2367 val |= I830_FENCE_REG_VALID;
2368 } else
2369 val = 0;
2370
2371 if (reg < 8)
2372 reg = FENCE_REG_830_0 + reg * 4;
2373 else
2374 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2375
2376 I915_WRITE(reg, val);
2377 POSTING_READ(reg);
2378}
2379
2380static void i830_write_fence_reg(struct drm_device *dev, int reg,
2381 struct drm_i915_gem_object *obj)
2382{
2383 drm_i915_private_t *dev_priv = dev->dev_private;
2384 uint32_t val;
2385
2386 if (obj) {
2387 u32 size = obj->gtt_space->size;
2388 uint32_t pitch_val;
2389
2390 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2391 (size & -size) != size ||
2392 (obj->gtt_offset & (size - 1)),
2393 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2394 obj->gtt_offset, size);
2395
2396 pitch_val = obj->stride / 128;
2397 pitch_val = ffs(pitch_val) - 1;
2398
2399 val = obj->gtt_offset;
2400 if (obj->tiling_mode == I915_TILING_Y)
2401 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2402 val |= I830_FENCE_SIZE_BITS(size);
2403 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2404 val |= I830_FENCE_REG_VALID;
2405 } else
2406 val = 0;
2407
2408 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2409 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2410}
2411
2412static void i915_gem_write_fence(struct drm_device *dev, int reg,
2413 struct drm_i915_gem_object *obj)
2414{
2415 switch (INTEL_INFO(dev)->gen) {
2416 case 7:
2417 case 6: sandybridge_write_fence_reg(dev, reg, obj); break;
2418 case 5:
2419 case 4: i965_write_fence_reg(dev, reg, obj); break;
2420 case 3: i915_write_fence_reg(dev, reg, obj); break;
2421 case 2: i830_write_fence_reg(dev, reg, obj); break;
2422 default: break;
2423 }
2424}
2425
2426static inline int fence_number(struct drm_i915_private *dev_priv,
2427 struct drm_i915_fence_reg *fence)
2428{
2429 return fence - dev_priv->fence_regs;
2430}
2431
2432static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2433 struct drm_i915_fence_reg *fence,
2434 bool enable)
2435{
2436 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2437 int reg = fence_number(dev_priv, fence);
2438
2439 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2440
2441 if (enable) {
2442 obj->fence_reg = reg;
2443 fence->obj = obj;
2444 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2445 } else {
2446 obj->fence_reg = I915_FENCE_REG_NONE;
2447 fence->obj = NULL;
2448 list_del_init(&fence->lru_list);
2449 }
2450}
2451
2452static int
2453i915_gem_object_flush_fence(struct drm_i915_gem_object *obj)
2454{
2455 if (obj->last_fenced_seqno) {
2456 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2457 if (ret)
2458 return ret;
2459
2460 obj->last_fenced_seqno = 0;
2461 }
2462
2463 /* Ensure that all CPU reads are completed before installing a fence
2464 * and all writes before removing the fence.
2465 */
2466 if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
2467 mb();
2468
2469 obj->fenced_gpu_access = false;
2470 return 0;
2471}
2472
2473int
2474i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2475{
2476 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2477 int ret;
2478
2479 ret = i915_gem_object_flush_fence(obj);
2480 if (ret)
2481 return ret;
2482
2483 if (obj->fence_reg == I915_FENCE_REG_NONE)
2484 return 0;
2485
2486 i915_gem_object_update_fence(obj,
2487 &dev_priv->fence_regs[obj->fence_reg],
2488 false);
2489 i915_gem_object_fence_lost(obj);
2490
2491 return 0;
2492}
2493
2494static struct drm_i915_fence_reg *
2495i915_find_fence_reg(struct drm_device *dev)
2496{
2497 struct drm_i915_private *dev_priv = dev->dev_private;
2498 struct drm_i915_fence_reg *reg, *avail;
2499 int i;
2500
2501 /* First try to find a free reg */
2502 avail = NULL;
2503 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2504 reg = &dev_priv->fence_regs[i];
2505 if (!reg->obj)
2506 return reg;
2507
2508 if (!reg->pin_count)
2509 avail = reg;
2510 }
2511
2512 if (avail == NULL)
2513 return NULL;
2514
2515 /* None available, try to steal one or wait for a user to finish */
2516 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2517 if (reg->pin_count)
2518 continue;
2519
2520 return reg;
2521 }
2522
2523 return NULL;
2524}
2525
2526/**
2527 * i915_gem_object_get_fence - set up fencing for an object
2528 * @obj: object to map through a fence reg
2529 *
2530 * When mapping objects through the GTT, userspace wants to be able to write
2531 * to them without having to worry about swizzling if the object is tiled.
2532 * This function walks the fence regs looking for a free one for @obj,
2533 * stealing one if it can't find any.
2534 *
2535 * It then sets up the reg based on the object's properties: address, pitch
2536 * and tiling format.
2537 *
2538 * For an untiled surface, this removes any existing fence.
2539 */
2540int
2541i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2542{
2543 struct drm_device *dev = obj->base.dev;
2544 struct drm_i915_private *dev_priv = dev->dev_private;
2545 bool enable = obj->tiling_mode != I915_TILING_NONE;
2546 struct drm_i915_fence_reg *reg;
2547 int ret;
2548
2549 /* Have we updated the tiling parameters upon the object and so
2550 * will need to serialise the write to the associated fence register?
2551 */
2552 if (obj->fence_dirty) {
2553 ret = i915_gem_object_flush_fence(obj);
2554 if (ret)
2555 return ret;
2556 }
2557
2558 /* Just update our place in the LRU if our fence is getting reused. */
2559 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2560 reg = &dev_priv->fence_regs[obj->fence_reg];
2561 if (!obj->fence_dirty) {
2562 list_move_tail(&reg->lru_list,
2563 &dev_priv->mm.fence_list);
2564 return 0;
2565 }
2566 } else if (enable) {
2567 reg = i915_find_fence_reg(dev);
2568 if (reg == NULL)
2569 return -EDEADLK;
2570
2571 if (reg->obj) {
2572 struct drm_i915_gem_object *old = reg->obj;
2573
2574 ret = i915_gem_object_flush_fence(old);
2575 if (ret)
2576 return ret;
2577
2578 i915_gem_object_fence_lost(old);
2579 }
2580 } else
2581 return 0;
2582
2583 i915_gem_object_update_fence(obj, reg, enable);
2584 obj->fence_dirty = false;
2585
2586 return 0;
2587}
2588
2589static bool i915_gem_valid_gtt_space(struct drm_device *dev,
2590 struct drm_mm_node *gtt_space,
2591 unsigned long cache_level)
2592{
2593 struct drm_mm_node *other;
2594
2595 /* On non-LLC machines we have to be careful when putting differing
2596 * types of snoopable memory together to avoid the prefetcher
2597 * crossing memory domains and dieing.
2598 */
2599 if (HAS_LLC(dev))
2600 return true;
2601
2602 if (gtt_space == NULL)
2603 return true;
2604
2605 if (list_empty(&gtt_space->node_list))
2606 return true;
2607
2608 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
2609 if (other->allocated && !other->hole_follows && other->color != cache_level)
2610 return false;
2611
2612 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
2613 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
2614 return false;
2615
2616 return true;
2617}
2618
2619static void i915_gem_verify_gtt(struct drm_device *dev)
2620{
2621#if WATCH_GTT
2622 struct drm_i915_private *dev_priv = dev->dev_private;
2623 struct drm_i915_gem_object *obj;
2624 int err = 0;
2625
2626 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
2627 if (obj->gtt_space == NULL) {
2628 printk(KERN_ERR "object found on GTT list with no space reserved\n");
2629 err++;
2630 continue;
2631 }
2632
2633 if (obj->cache_level != obj->gtt_space->color) {
2634 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
2635 obj->gtt_space->start,
2636 obj->gtt_space->start + obj->gtt_space->size,
2637 obj->cache_level,
2638 obj->gtt_space->color);
2639 err++;
2640 continue;
2641 }
2642
2643 if (!i915_gem_valid_gtt_space(dev,
2644 obj->gtt_space,
2645 obj->cache_level)) {
2646 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
2647 obj->gtt_space->start,
2648 obj->gtt_space->start + obj->gtt_space->size,
2649 obj->cache_level);
2650 err++;
2651 continue;
2652 }
2653 }
2654
2655 WARN_ON(err);
2656#endif
2657}
2658
2659/**
2660 * Finds free space in the GTT aperture and binds the object there.
2661 */
2662static int
2663i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2664 unsigned alignment,
2665 bool map_and_fenceable)
2666{
2667 struct drm_device *dev = obj->base.dev;
2668 drm_i915_private_t *dev_priv = dev->dev_private;
2669 struct drm_mm_node *free_space;
2670 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2671 u32 size, fence_size, fence_alignment, unfenced_alignment;
2672 bool mappable, fenceable;
2673 int ret;
2674
2675 if (obj->madv != I915_MADV_WILLNEED) {
2676 DRM_ERROR("Attempting to bind a purgeable object\n");
2677 return -EINVAL;
2678 }
2679
2680 fence_size = i915_gem_get_gtt_size(dev,
2681 obj->base.size,
2682 obj->tiling_mode);
2683 fence_alignment = i915_gem_get_gtt_alignment(dev,
2684 obj->base.size,
2685 obj->tiling_mode);
2686 unfenced_alignment =
2687 i915_gem_get_unfenced_gtt_alignment(dev,
2688 obj->base.size,
2689 obj->tiling_mode);
2690
2691 if (alignment == 0)
2692 alignment = map_and_fenceable ? fence_alignment :
2693 unfenced_alignment;
2694 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2695 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2696 return -EINVAL;
2697 }
2698
2699 size = map_and_fenceable ? fence_size : obj->base.size;
2700
2701 /* If the object is bigger than the entire aperture, reject it early
2702 * before evicting everything in a vain attempt to find space.
2703 */
2704 if (obj->base.size >
2705 (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2706 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2707 return -E2BIG;
2708 }
2709
2710 search_free:
2711 if (map_and_fenceable)
2712 free_space =
2713 drm_mm_search_free_in_range_color(&dev_priv->mm.gtt_space,
2714 size, alignment, obj->cache_level,
2715 0, dev_priv->mm.gtt_mappable_end,
2716 false);
2717 else
2718 free_space = drm_mm_search_free_color(&dev_priv->mm.gtt_space,
2719 size, alignment, obj->cache_level,
2720 false);
2721
2722 if (free_space != NULL) {
2723 if (map_and_fenceable)
2724 obj->gtt_space =
2725 drm_mm_get_block_range_generic(free_space,
2726 size, alignment, obj->cache_level,
2727 0, dev_priv->mm.gtt_mappable_end,
2728 false);
2729 else
2730 obj->gtt_space =
2731 drm_mm_get_block_generic(free_space,
2732 size, alignment, obj->cache_level,
2733 false);
2734 }
2735 if (obj->gtt_space == NULL) {
2736 /* If the gtt is empty and we're still having trouble
2737 * fitting our object in, we're out of memory.
2738 */
2739 ret = i915_gem_evict_something(dev, size, alignment,
2740 obj->cache_level,
2741 map_and_fenceable);
2742 if (ret)
2743 return ret;
2744
2745 goto search_free;
2746 }
2747 if (WARN_ON(!i915_gem_valid_gtt_space(dev,
2748 obj->gtt_space,
2749 obj->cache_level))) {
2750 drm_mm_put_block(obj->gtt_space);
2751 obj->gtt_space = NULL;
2752 return -EINVAL;
2753 }
2754
2755 ret = i915_gem_object_get_pages_gtt(obj, gfpmask);
2756 if (ret) {
2757 drm_mm_put_block(obj->gtt_space);
2758 obj->gtt_space = NULL;
2759
2760 if (ret == -ENOMEM) {
2761 /* first try to reclaim some memory by clearing the GTT */
2762 ret = i915_gem_evict_everything(dev, false);
2763 if (ret) {
2764 /* now try to shrink everyone else */
2765 if (gfpmask) {
2766 gfpmask = 0;
2767 goto search_free;
2768 }
2769
2770 return -ENOMEM;
2771 }
2772
2773 goto search_free;
2774 }
2775
2776 return ret;
2777 }
2778
2779 ret = i915_gem_gtt_prepare_object(obj);
2780 if (ret) {
2781 i915_gem_object_put_pages_gtt(obj);
2782 drm_mm_put_block(obj->gtt_space);
2783 obj->gtt_space = NULL;
2784
2785 if (i915_gem_evict_everything(dev, false))
2786 return ret;
2787
2788 goto search_free;
2789 }
2790
2791 if (!dev_priv->mm.aliasing_ppgtt)
2792 i915_gem_gtt_bind_object(obj, obj->cache_level);
2793
2794 list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
2795 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2796
2797 /* Assert that the object is not currently in any GPU domain. As it
2798 * wasn't in the GTT, there shouldn't be any way it could have been in
2799 * a GPU cache
2800 */
2801 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2802 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2803
2804 obj->gtt_offset = obj->gtt_space->start;
2805
2806 fenceable =
2807 obj->gtt_space->size == fence_size &&
2808 (obj->gtt_space->start & (fence_alignment - 1)) == 0;
2809
2810 mappable =
2811 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2812
2813 obj->map_and_fenceable = mappable && fenceable;
2814
2815 trace_i915_gem_object_bind(obj, map_and_fenceable);
2816 i915_gem_verify_gtt(dev);
2817 return 0;
2818}
2819
2820void
2821i915_gem_clflush_object(struct drm_i915_gem_object *obj)
2822{
2823 /* If we don't have a page list set up, then we're not pinned
2824 * to GPU, and we can ignore the cache flush because it'll happen
2825 * again at bind time.
2826 */
2827 if (obj->pages == NULL)
2828 return;
2829
2830 /* If the GPU is snooping the contents of the CPU cache,
2831 * we do not need to manually clear the CPU cache lines. However,
2832 * the caches are only snooped when the render cache is
2833 * flushed/invalidated. As we always have to emit invalidations
2834 * and flushes when moving into and out of the RENDER domain, correct
2835 * snooping behaviour occurs naturally as the result of our domain
2836 * tracking.
2837 */
2838 if (obj->cache_level != I915_CACHE_NONE)
2839 return;
2840
2841 trace_i915_gem_object_clflush(obj);
2842
2843 drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
2844}
2845
2846/** Flushes the GTT write domain for the object if it's dirty. */
2847static void
2848i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
2849{
2850 uint32_t old_write_domain;
2851
2852 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
2853 return;
2854
2855 /* No actual flushing is required for the GTT write domain. Writes
2856 * to it immediately go to main memory as far as we know, so there's
2857 * no chipset flush. It also doesn't land in render cache.
2858 *
2859 * However, we do have to enforce the order so that all writes through
2860 * the GTT land before any writes to the device, such as updates to
2861 * the GATT itself.
2862 */
2863 wmb();
2864
2865 old_write_domain = obj->base.write_domain;
2866 obj->base.write_domain = 0;
2867
2868 trace_i915_gem_object_change_domain(obj,
2869 obj->base.read_domains,
2870 old_write_domain);
2871}
2872
2873/** Flushes the CPU write domain for the object if it's dirty. */
2874static void
2875i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
2876{
2877 uint32_t old_write_domain;
2878
2879 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
2880 return;
2881
2882 i915_gem_clflush_object(obj);
2883 intel_gtt_chipset_flush();
2884 old_write_domain = obj->base.write_domain;
2885 obj->base.write_domain = 0;
2886
2887 trace_i915_gem_object_change_domain(obj,
2888 obj->base.read_domains,
2889 old_write_domain);
2890}
2891
2892/**
2893 * Moves a single object to the GTT read, and possibly write domain.
2894 *
2895 * This function returns when the move is complete, including waiting on
2896 * flushes to occur.
2897 */
2898int
2899i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
2900{
2901 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2902 uint32_t old_write_domain, old_read_domains;
2903 int ret;
2904
2905 /* Not valid to be called on unbound objects. */
2906 if (obj->gtt_space == NULL)
2907 return -EINVAL;
2908
2909 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
2910 return 0;
2911
2912 ret = i915_gem_object_wait_rendering(obj, !write);
2913 if (ret)
2914 return ret;
2915
2916 i915_gem_object_flush_cpu_write_domain(obj);
2917
2918 old_write_domain = obj->base.write_domain;
2919 old_read_domains = obj->base.read_domains;
2920
2921 /* It should now be out of any other write domains, and we can update
2922 * the domain values for our changes.
2923 */
2924 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2925 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2926 if (write) {
2927 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
2928 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
2929 obj->dirty = 1;
2930 }
2931
2932 trace_i915_gem_object_change_domain(obj,
2933 old_read_domains,
2934 old_write_domain);
2935
2936 /* And bump the LRU for this access */
2937 if (i915_gem_object_is_inactive(obj))
2938 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2939
2940 return 0;
2941}
2942
2943int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2944 enum i915_cache_level cache_level)
2945{
2946 struct drm_device *dev = obj->base.dev;
2947 drm_i915_private_t *dev_priv = dev->dev_private;
2948 int ret;
2949
2950 if (obj->cache_level == cache_level)
2951 return 0;
2952
2953 if (obj->pin_count) {
2954 DRM_DEBUG("can not change the cache level of pinned objects\n");
2955 return -EBUSY;
2956 }
2957
2958 if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) {
2959 ret = i915_gem_object_unbind(obj);
2960 if (ret)
2961 return ret;
2962 }
2963
2964 if (obj->gtt_space) {
2965 ret = i915_gem_object_finish_gpu(obj);
2966 if (ret)
2967 return ret;
2968
2969 i915_gem_object_finish_gtt(obj);
2970
2971 /* Before SandyBridge, you could not use tiling or fence
2972 * registers with snooped memory, so relinquish any fences
2973 * currently pointing to our region in the aperture.
2974 */
2975 if (INTEL_INFO(dev)->gen < 6) {
2976 ret = i915_gem_object_put_fence(obj);
2977 if (ret)
2978 return ret;
2979 }
2980
2981 if (obj->has_global_gtt_mapping)
2982 i915_gem_gtt_bind_object(obj, cache_level);
2983 if (obj->has_aliasing_ppgtt_mapping)
2984 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
2985 obj, cache_level);
2986
2987 obj->gtt_space->color = cache_level;
2988 }
2989
2990 if (cache_level == I915_CACHE_NONE) {
2991 u32 old_read_domains, old_write_domain;
2992
2993 /* If we're coming from LLC cached, then we haven't
2994 * actually been tracking whether the data is in the
2995 * CPU cache or not, since we only allow one bit set
2996 * in obj->write_domain and have been skipping the clflushes.
2997 * Just set it to the CPU cache for now.
2998 */
2999 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3000 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3001
3002 old_read_domains = obj->base.read_domains;
3003 old_write_domain = obj->base.write_domain;
3004
3005 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3006 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3007
3008 trace_i915_gem_object_change_domain(obj,
3009 old_read_domains,
3010 old_write_domain);
3011 }
3012
3013 obj->cache_level = cache_level;
3014 i915_gem_verify_gtt(dev);
3015 return 0;
3016}
3017
3018/*
3019 * Prepare buffer for display plane (scanout, cursors, etc).
3020 * Can be called from an uninterruptible phase (modesetting) and allows
3021 * any flushes to be pipelined (for pageflips).
3022 */
3023int
3024i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3025 u32 alignment,
3026 struct intel_ring_buffer *pipelined)
3027{
3028 u32 old_read_domains, old_write_domain;
3029 int ret;
3030
3031 if (pipelined != obj->ring) {
3032 ret = i915_gem_object_sync(obj, pipelined);
3033 if (ret)
3034 return ret;
3035 }
3036
3037 /* The display engine is not coherent with the LLC cache on gen6. As
3038 * a result, we make sure that the pinning that is about to occur is
3039 * done with uncached PTEs. This is lowest common denominator for all
3040 * chipsets.
3041 *
3042 * However for gen6+, we could do better by using the GFDT bit instead
3043 * of uncaching, which would allow us to flush all the LLC-cached data
3044 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3045 */
3046 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3047 if (ret)
3048 return ret;
3049
3050 /* As the user may map the buffer once pinned in the display plane
3051 * (e.g. libkms for the bootup splash), we have to ensure that we
3052 * always use map_and_fenceable for all scanout buffers.
3053 */
3054 ret = i915_gem_object_pin(obj, alignment, true);
3055 if (ret)
3056 return ret;
3057
3058 i915_gem_object_flush_cpu_write_domain(obj);
3059
3060 old_write_domain = obj->base.write_domain;
3061 old_read_domains = obj->base.read_domains;
3062
3063 /* It should now be out of any other write domains, and we can update
3064 * the domain values for our changes.
3065 */
3066 obj->base.write_domain = 0;
3067 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3068
3069 trace_i915_gem_object_change_domain(obj,
3070 old_read_domains,
3071 old_write_domain);
3072
3073 return 0;
3074}
3075
3076int
3077i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3078{
3079 int ret;
3080
3081 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3082 return 0;
3083
3084 ret = i915_gem_object_wait_rendering(obj, false);
3085 if (ret)
3086 return ret;
3087
3088 /* Ensure that we invalidate the GPU's caches and TLBs. */
3089 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3090 return 0;
3091}
3092
3093/**
3094 * Moves a single object to the CPU read, and possibly write domain.
3095 *
3096 * This function returns when the move is complete, including waiting on
3097 * flushes to occur.
3098 */
3099int
3100i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3101{
3102 uint32_t old_write_domain, old_read_domains;
3103 int ret;
3104
3105 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3106 return 0;
3107
3108 ret = i915_gem_object_wait_rendering(obj, !write);
3109 if (ret)
3110 return ret;
3111
3112 i915_gem_object_flush_gtt_write_domain(obj);
3113
3114 old_write_domain = obj->base.write_domain;
3115 old_read_domains = obj->base.read_domains;
3116
3117 /* Flush the CPU cache if it's still invalid. */
3118 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3119 i915_gem_clflush_object(obj);
3120
3121 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3122 }
3123
3124 /* It should now be out of any other write domains, and we can update
3125 * the domain values for our changes.
3126 */
3127 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3128
3129 /* If we're writing through the CPU, then the GPU read domains will
3130 * need to be invalidated at next use.
3131 */
3132 if (write) {
3133 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3134 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3135 }
3136
3137 trace_i915_gem_object_change_domain(obj,
3138 old_read_domains,
3139 old_write_domain);
3140
3141 return 0;
3142}
3143
3144/* Throttle our rendering by waiting until the ring has completed our requests
3145 * emitted over 20 msec ago.
3146 *
3147 * Note that if we were to use the current jiffies each time around the loop,
3148 * we wouldn't escape the function with any frames outstanding if the time to
3149 * render a frame was over 20ms.
3150 *
3151 * This should get us reasonable parallelism between CPU and GPU but also
3152 * relatively low latency when blocking on a particular request to finish.
3153 */
3154static int
3155i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3156{
3157 struct drm_i915_private *dev_priv = dev->dev_private;
3158 struct drm_i915_file_private *file_priv = file->driver_priv;
3159 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3160 struct drm_i915_gem_request *request;
3161 struct intel_ring_buffer *ring = NULL;
3162 u32 seqno = 0;
3163 int ret;
3164
3165 if (atomic_read(&dev_priv->mm.wedged))
3166 return -EIO;
3167
3168 spin_lock(&file_priv->mm.lock);
3169 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3170 if (time_after_eq(request->emitted_jiffies, recent_enough))
3171 break;
3172
3173 ring = request->ring;
3174 seqno = request->seqno;
3175 }
3176 spin_unlock(&file_priv->mm.lock);
3177
3178 if (seqno == 0)
3179 return 0;
3180
3181 ret = __wait_seqno(ring, seqno, true, NULL);
3182 if (ret == 0)
3183 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3184
3185 return ret;
3186}
3187
3188int
3189i915_gem_object_pin(struct drm_i915_gem_object *obj,
3190 uint32_t alignment,
3191 bool map_and_fenceable)
3192{
3193 int ret;
3194
3195 BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
3196
3197 if (obj->gtt_space != NULL) {
3198 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3199 (map_and_fenceable && !obj->map_and_fenceable)) {
3200 WARN(obj->pin_count,
3201 "bo is already pinned with incorrect alignment:"
3202 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3203 " obj->map_and_fenceable=%d\n",
3204 obj->gtt_offset, alignment,
3205 map_and_fenceable,
3206 obj->map_and_fenceable);
3207 ret = i915_gem_object_unbind(obj);
3208 if (ret)
3209 return ret;
3210 }
3211 }
3212
3213 if (obj->gtt_space == NULL) {
3214 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3215 map_and_fenceable);
3216 if (ret)
3217 return ret;
3218 }
3219
3220 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3221 i915_gem_gtt_bind_object(obj, obj->cache_level);
3222
3223 obj->pin_count++;
3224 obj->pin_mappable |= map_and_fenceable;
3225
3226 return 0;
3227}
3228
3229void
3230i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3231{
3232 BUG_ON(obj->pin_count == 0);
3233 BUG_ON(obj->gtt_space == NULL);
3234
3235 if (--obj->pin_count == 0)
3236 obj->pin_mappable = false;
3237}
3238
3239int
3240i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3241 struct drm_file *file)
3242{
3243 struct drm_i915_gem_pin *args = data;
3244 struct drm_i915_gem_object *obj;
3245 int ret;
3246
3247 ret = i915_mutex_lock_interruptible(dev);
3248 if (ret)
3249 return ret;
3250
3251 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3252 if (&obj->base == NULL) {
3253 ret = -ENOENT;
3254 goto unlock;
3255 }
3256
3257 if (obj->madv != I915_MADV_WILLNEED) {
3258 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3259 ret = -EINVAL;
3260 goto out;
3261 }
3262
3263 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3264 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3265 args->handle);
3266 ret = -EINVAL;
3267 goto out;
3268 }
3269
3270 obj->user_pin_count++;
3271 obj->pin_filp = file;
3272 if (obj->user_pin_count == 1) {
3273 ret = i915_gem_object_pin(obj, args->alignment, true);
3274 if (ret)
3275 goto out;
3276 }
3277
3278 /* XXX - flush the CPU caches for pinned objects
3279 * as the X server doesn't manage domains yet
3280 */
3281 i915_gem_object_flush_cpu_write_domain(obj);
3282 args->offset = obj->gtt_offset;
3283out:
3284 drm_gem_object_unreference(&obj->base);
3285unlock:
3286 mutex_unlock(&dev->struct_mutex);
3287 return ret;
3288}
3289
3290int
3291i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3292 struct drm_file *file)
3293{
3294 struct drm_i915_gem_pin *args = data;
3295 struct drm_i915_gem_object *obj;
3296 int ret;
3297
3298 ret = i915_mutex_lock_interruptible(dev);
3299 if (ret)
3300 return ret;
3301
3302 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3303 if (&obj->base == NULL) {
3304 ret = -ENOENT;
3305 goto unlock;
3306 }
3307
3308 if (obj->pin_filp != file) {
3309 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3310 args->handle);
3311 ret = -EINVAL;
3312 goto out;
3313 }
3314 obj->user_pin_count--;
3315 if (obj->user_pin_count == 0) {
3316 obj->pin_filp = NULL;
3317 i915_gem_object_unpin(obj);
3318 }
3319
3320out:
3321 drm_gem_object_unreference(&obj->base);
3322unlock:
3323 mutex_unlock(&dev->struct_mutex);
3324 return ret;
3325}
3326
3327int
3328i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3329 struct drm_file *file)
3330{
3331 struct drm_i915_gem_busy *args = data;
3332 struct drm_i915_gem_object *obj;
3333 int ret;
3334
3335 ret = i915_mutex_lock_interruptible(dev);
3336 if (ret)
3337 return ret;
3338
3339 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3340 if (&obj->base == NULL) {
3341 ret = -ENOENT;
3342 goto unlock;
3343 }
3344
3345 /* Count all active objects as busy, even if they are currently not used
3346 * by the gpu. Users of this interface expect objects to eventually
3347 * become non-busy without any further actions, therefore emit any
3348 * necessary flushes here.
3349 */
3350 ret = i915_gem_object_flush_active(obj);
3351
3352 args->busy = obj->active;
3353 if (obj->ring) {
3354 BUILD_BUG_ON(I915_NUM_RINGS > 16);
3355 args->busy |= intel_ring_flag(obj->ring) << 16;
3356 }
3357
3358 drm_gem_object_unreference(&obj->base);
3359unlock:
3360 mutex_unlock(&dev->struct_mutex);
3361 return ret;
3362}
3363
3364int
3365i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3366 struct drm_file *file_priv)
3367{
3368 return i915_gem_ring_throttle(dev, file_priv);
3369}
3370
3371int
3372i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3373 struct drm_file *file_priv)
3374{
3375 struct drm_i915_gem_madvise *args = data;
3376 struct drm_i915_gem_object *obj;
3377 int ret;
3378
3379 switch (args->madv) {
3380 case I915_MADV_DONTNEED:
3381 case I915_MADV_WILLNEED:
3382 break;
3383 default:
3384 return -EINVAL;
3385 }
3386
3387 ret = i915_mutex_lock_interruptible(dev);
3388 if (ret)
3389 return ret;
3390
3391 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3392 if (&obj->base == NULL) {
3393 ret = -ENOENT;
3394 goto unlock;
3395 }
3396
3397 if (obj->pin_count) {
3398 ret = -EINVAL;
3399 goto out;
3400 }
3401
3402 if (obj->madv != __I915_MADV_PURGED)
3403 obj->madv = args->madv;
3404
3405 /* if the object is no longer bound, discard its backing storage */
3406 if (i915_gem_object_is_purgeable(obj) &&
3407 obj->gtt_space == NULL)
3408 i915_gem_object_truncate(obj);
3409
3410 args->retained = obj->madv != __I915_MADV_PURGED;
3411
3412out:
3413 drm_gem_object_unreference(&obj->base);
3414unlock:
3415 mutex_unlock(&dev->struct_mutex);
3416 return ret;
3417}
3418
3419struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3420 size_t size)
3421{
3422 struct drm_i915_private *dev_priv = dev->dev_private;
3423 struct drm_i915_gem_object *obj;
3424 struct address_space *mapping;
3425 u32 mask;
3426
3427 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
3428 if (obj == NULL)
3429 return NULL;
3430
3431 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3432 kfree(obj);
3433 return NULL;
3434 }
3435
3436 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3437 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
3438 /* 965gm cannot relocate objects above 4GiB. */
3439 mask &= ~__GFP_HIGHMEM;
3440 mask |= __GFP_DMA32;
3441 }
3442
3443 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3444 mapping_set_gfp_mask(mapping, mask);
3445
3446 i915_gem_info_add_obj(dev_priv, size);
3447
3448 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3449 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3450
3451 if (HAS_LLC(dev)) {
3452 /* On some devices, we can have the GPU use the LLC (the CPU
3453 * cache) for about a 10% performance improvement
3454 * compared to uncached. Graphics requests other than
3455 * display scanout are coherent with the CPU in
3456 * accessing this cache. This means in this mode we
3457 * don't need to clflush on the CPU side, and on the
3458 * GPU side we only need to flush internal caches to
3459 * get data visible to the CPU.
3460 *
3461 * However, we maintain the display planes as UC, and so
3462 * need to rebind when first used as such.
3463 */
3464 obj->cache_level = I915_CACHE_LLC;
3465 } else
3466 obj->cache_level = I915_CACHE_NONE;
3467
3468 obj->base.driver_private = NULL;
3469 obj->fence_reg = I915_FENCE_REG_NONE;
3470 INIT_LIST_HEAD(&obj->mm_list);
3471 INIT_LIST_HEAD(&obj->gtt_list);
3472 INIT_LIST_HEAD(&obj->ring_list);
3473 INIT_LIST_HEAD(&obj->exec_list);
3474 obj->madv = I915_MADV_WILLNEED;
3475 /* Avoid an unnecessary call to unbind on the first bind. */
3476 obj->map_and_fenceable = true;
3477
3478 return obj;
3479}
3480
3481int i915_gem_init_object(struct drm_gem_object *obj)
3482{
3483 BUG();
3484
3485 return 0;
3486}
3487
3488void i915_gem_free_object(struct drm_gem_object *gem_obj)
3489{
3490 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3491 struct drm_device *dev = obj->base.dev;
3492 drm_i915_private_t *dev_priv = dev->dev_private;
3493
3494 trace_i915_gem_object_destroy(obj);
3495
3496 if (gem_obj->import_attach)
3497 drm_prime_gem_destroy(gem_obj, obj->sg_table);
3498
3499 if (obj->phys_obj)
3500 i915_gem_detach_phys_object(dev, obj);
3501
3502 obj->pin_count = 0;
3503 if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
3504 bool was_interruptible;
3505
3506 was_interruptible = dev_priv->mm.interruptible;
3507 dev_priv->mm.interruptible = false;
3508
3509 WARN_ON(i915_gem_object_unbind(obj));
3510
3511 dev_priv->mm.interruptible = was_interruptible;
3512 }
3513
3514 if (obj->base.map_list.map)
3515 drm_gem_free_mmap_offset(&obj->base);
3516
3517 drm_gem_object_release(&obj->base);
3518 i915_gem_info_remove_obj(dev_priv, obj->base.size);
3519
3520 kfree(obj->bit_17);
3521 kfree(obj);
3522}
3523
3524int
3525i915_gem_idle(struct drm_device *dev)
3526{
3527 drm_i915_private_t *dev_priv = dev->dev_private;
3528 int ret;
3529
3530 mutex_lock(&dev->struct_mutex);
3531
3532 if (dev_priv->mm.suspended) {
3533 mutex_unlock(&dev->struct_mutex);
3534 return 0;
3535 }
3536
3537 ret = i915_gpu_idle(dev);
3538 if (ret) {
3539 mutex_unlock(&dev->struct_mutex);
3540 return ret;
3541 }
3542 i915_gem_retire_requests(dev);
3543
3544 /* Under UMS, be paranoid and evict. */
3545 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3546 i915_gem_evict_everything(dev, false);
3547
3548 i915_gem_reset_fences(dev);
3549
3550 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3551 * We need to replace this with a semaphore, or something.
3552 * And not confound mm.suspended!
3553 */
3554 dev_priv->mm.suspended = 1;
3555 del_timer_sync(&dev_priv->hangcheck_timer);
3556
3557 i915_kernel_lost_context(dev);
3558 i915_gem_cleanup_ringbuffer(dev);
3559
3560 mutex_unlock(&dev->struct_mutex);
3561
3562 /* Cancel the retire work handler, which should be idle now. */
3563 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3564
3565 return 0;
3566}
3567
3568void i915_gem_l3_remap(struct drm_device *dev)
3569{
3570 drm_i915_private_t *dev_priv = dev->dev_private;
3571 u32 misccpctl;
3572 int i;
3573
3574 if (!IS_IVYBRIDGE(dev))
3575 return;
3576
3577 if (!dev_priv->mm.l3_remap_info)
3578 return;
3579
3580 misccpctl = I915_READ(GEN7_MISCCPCTL);
3581 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
3582 POSTING_READ(GEN7_MISCCPCTL);
3583
3584 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
3585 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
3586 if (remap && remap != dev_priv->mm.l3_remap_info[i/4])
3587 DRM_DEBUG("0x%x was already programmed to %x\n",
3588 GEN7_L3LOG_BASE + i, remap);
3589 if (remap && !dev_priv->mm.l3_remap_info[i/4])
3590 DRM_DEBUG_DRIVER("Clearing remapped register\n");
3591 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->mm.l3_remap_info[i/4]);
3592 }
3593
3594 /* Make sure all the writes land before disabling dop clock gating */
3595 POSTING_READ(GEN7_L3LOG_BASE);
3596
3597 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
3598}
3599
3600void i915_gem_init_swizzling(struct drm_device *dev)
3601{
3602 drm_i915_private_t *dev_priv = dev->dev_private;
3603
3604 if (INTEL_INFO(dev)->gen < 5 ||
3605 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
3606 return;
3607
3608 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
3609 DISP_TILE_SURFACE_SWIZZLING);
3610
3611 if (IS_GEN5(dev))
3612 return;
3613
3614 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
3615 if (IS_GEN6(dev))
3616 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
3617 else
3618 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
3619}
3620
3621void i915_gem_init_ppgtt(struct drm_device *dev)
3622{
3623 drm_i915_private_t *dev_priv = dev->dev_private;
3624 uint32_t pd_offset;
3625 struct intel_ring_buffer *ring;
3626 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
3627 uint32_t __iomem *pd_addr;
3628 uint32_t pd_entry;
3629 int i;
3630
3631 if (!dev_priv->mm.aliasing_ppgtt)
3632 return;
3633
3634
3635 pd_addr = dev_priv->mm.gtt->gtt + ppgtt->pd_offset/sizeof(uint32_t);
3636 for (i = 0; i < ppgtt->num_pd_entries; i++) {
3637 dma_addr_t pt_addr;
3638
3639 if (dev_priv->mm.gtt->needs_dmar)
3640 pt_addr = ppgtt->pt_dma_addr[i];
3641 else
3642 pt_addr = page_to_phys(ppgtt->pt_pages[i]);
3643
3644 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
3645 pd_entry |= GEN6_PDE_VALID;
3646
3647 writel(pd_entry, pd_addr + i);
3648 }
3649 readl(pd_addr);
3650
3651 pd_offset = ppgtt->pd_offset;
3652 pd_offset /= 64; /* in cachelines, */
3653 pd_offset <<= 16;
3654
3655 if (INTEL_INFO(dev)->gen == 6) {
3656 uint32_t ecochk, gab_ctl, ecobits;
3657
3658 ecobits = I915_READ(GAC_ECO_BITS);
3659 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
3660
3661 gab_ctl = I915_READ(GAB_CTL);
3662 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
3663
3664 ecochk = I915_READ(GAM_ECOCHK);
3665 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
3666 ECOCHK_PPGTT_CACHE64B);
3667 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
3668 } else if (INTEL_INFO(dev)->gen >= 7) {
3669 I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
3670 /* GFX_MODE is per-ring on gen7+ */
3671 }
3672
3673 for_each_ring(ring, dev_priv, i) {
3674 if (INTEL_INFO(dev)->gen >= 7)
3675 I915_WRITE(RING_MODE_GEN7(ring),
3676 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
3677
3678 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
3679 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
3680 }
3681}
3682
3683static bool
3684intel_enable_blt(struct drm_device *dev)
3685{
3686 if (!HAS_BLT(dev))
3687 return false;
3688
3689 /* The blitter was dysfunctional on early prototypes */
3690 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
3691 DRM_INFO("BLT not supported on this pre-production hardware;"
3692 " graphics performance will be degraded.\n");
3693 return false;
3694 }
3695
3696 return true;
3697}
3698
3699int
3700i915_gem_init_hw(struct drm_device *dev)
3701{
3702 drm_i915_private_t *dev_priv = dev->dev_private;
3703 int ret;
3704
3705 if (!intel_enable_gtt())
3706 return -EIO;
3707
3708 i915_gem_l3_remap(dev);
3709
3710 i915_gem_init_swizzling(dev);
3711
3712 ret = intel_init_render_ring_buffer(dev);
3713 if (ret)
3714 return ret;
3715
3716 if (HAS_BSD(dev)) {
3717 ret = intel_init_bsd_ring_buffer(dev);
3718 if (ret)
3719 goto cleanup_render_ring;
3720 }
3721
3722 if (intel_enable_blt(dev)) {
3723 ret = intel_init_blt_ring_buffer(dev);
3724 if (ret)
3725 goto cleanup_bsd_ring;
3726 }
3727
3728 dev_priv->next_seqno = 1;
3729
3730 /*
3731 * XXX: There was some w/a described somewhere suggesting loading
3732 * contexts before PPGTT.
3733 */
3734 i915_gem_context_init(dev);
3735 i915_gem_init_ppgtt(dev);
3736
3737 return 0;
3738
3739cleanup_bsd_ring:
3740 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
3741cleanup_render_ring:
3742 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
3743 return ret;
3744}
3745
3746static bool
3747intel_enable_ppgtt(struct drm_device *dev)
3748{
3749 if (i915_enable_ppgtt >= 0)
3750 return i915_enable_ppgtt;
3751
3752#ifdef CONFIG_INTEL_IOMMU
3753 /* Disable ppgtt on SNB if VT-d is on. */
3754 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
3755 return false;
3756#endif
3757
3758 return true;
3759}
3760
3761int i915_gem_init(struct drm_device *dev)
3762{
3763 struct drm_i915_private *dev_priv = dev->dev_private;
3764 unsigned long gtt_size, mappable_size;
3765 int ret;
3766
3767 gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
3768 mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
3769
3770 mutex_lock(&dev->struct_mutex);
3771 if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
3772 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
3773 * aperture accordingly when using aliasing ppgtt. */
3774 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
3775
3776 i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size);
3777
3778 ret = i915_gem_init_aliasing_ppgtt(dev);
3779 if (ret) {
3780 mutex_unlock(&dev->struct_mutex);
3781 return ret;
3782 }
3783 } else {
3784 /* Let GEM Manage all of the aperture.
3785 *
3786 * However, leave one page at the end still bound to the scratch
3787 * page. There are a number of places where the hardware
3788 * apparently prefetches past the end of the object, and we've
3789 * seen multiple hangs with the GPU head pointer stuck in a
3790 * batchbuffer bound at the last page of the aperture. One page
3791 * should be enough to keep any prefetching inside of the
3792 * aperture.
3793 */
3794 i915_gem_init_global_gtt(dev, 0, mappable_size,
3795 gtt_size);
3796 }
3797
3798 ret = i915_gem_init_hw(dev);
3799 mutex_unlock(&dev->struct_mutex);
3800 if (ret) {
3801 i915_gem_cleanup_aliasing_ppgtt(dev);
3802 return ret;
3803 }
3804
3805 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
3806 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3807 dev_priv->dri1.allow_batchbuffer = 1;
3808 return 0;
3809}
3810
3811void
3812i915_gem_cleanup_ringbuffer(struct drm_device *dev)
3813{
3814 drm_i915_private_t *dev_priv = dev->dev_private;
3815 struct intel_ring_buffer *ring;
3816 int i;
3817
3818 for_each_ring(ring, dev_priv, i)
3819 intel_cleanup_ring_buffer(ring);
3820}
3821
3822int
3823i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
3824 struct drm_file *file_priv)
3825{
3826 drm_i915_private_t *dev_priv = dev->dev_private;
3827 int ret;
3828
3829 if (drm_core_check_feature(dev, DRIVER_MODESET))
3830 return 0;
3831
3832 if (atomic_read(&dev_priv->mm.wedged)) {
3833 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3834 atomic_set(&dev_priv->mm.wedged, 0);
3835 }
3836
3837 mutex_lock(&dev->struct_mutex);
3838 dev_priv->mm.suspended = 0;
3839
3840 ret = i915_gem_init_hw(dev);
3841 if (ret != 0) {
3842 mutex_unlock(&dev->struct_mutex);
3843 return ret;
3844 }
3845
3846 BUG_ON(!list_empty(&dev_priv->mm.active_list));
3847 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
3848 mutex_unlock(&dev->struct_mutex);
3849
3850 ret = drm_irq_install(dev);
3851 if (ret)
3852 goto cleanup_ringbuffer;
3853
3854 return 0;
3855
3856cleanup_ringbuffer:
3857 mutex_lock(&dev->struct_mutex);
3858 i915_gem_cleanup_ringbuffer(dev);
3859 dev_priv->mm.suspended = 1;
3860 mutex_unlock(&dev->struct_mutex);
3861
3862 return ret;
3863}
3864
3865int
3866i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
3867 struct drm_file *file_priv)
3868{
3869 if (drm_core_check_feature(dev, DRIVER_MODESET))
3870 return 0;
3871
3872 drm_irq_uninstall(dev);
3873 return i915_gem_idle(dev);
3874}
3875
3876void
3877i915_gem_lastclose(struct drm_device *dev)
3878{
3879 int ret;
3880
3881 if (drm_core_check_feature(dev, DRIVER_MODESET))
3882 return;
3883
3884 ret = i915_gem_idle(dev);
3885 if (ret)
3886 DRM_ERROR("failed to idle hardware: %d\n", ret);
3887}
3888
3889static void
3890init_ring_lists(struct intel_ring_buffer *ring)
3891{
3892 INIT_LIST_HEAD(&ring->active_list);
3893 INIT_LIST_HEAD(&ring->request_list);
3894}
3895
3896void
3897i915_gem_load(struct drm_device *dev)
3898{
3899 int i;
3900 drm_i915_private_t *dev_priv = dev->dev_private;
3901
3902 INIT_LIST_HEAD(&dev_priv->mm.active_list);
3903 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
3904 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
3905 INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
3906 for (i = 0; i < I915_NUM_RINGS; i++)
3907 init_ring_lists(&dev_priv->ring[i]);
3908 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
3909 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
3910 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
3911 i915_gem_retire_work_handler);
3912 init_completion(&dev_priv->error_completion);
3913
3914 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3915 if (IS_GEN3(dev)) {
3916 I915_WRITE(MI_ARB_STATE,
3917 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
3918 }
3919
3920 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
3921
3922 /* Old X drivers will take 0-2 for front, back, depth buffers */
3923 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3924 dev_priv->fence_reg_start = 3;
3925
3926 if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3927 dev_priv->num_fence_regs = 16;
3928 else
3929 dev_priv->num_fence_regs = 8;
3930
3931 /* Initialize fence registers to zero */
3932 i915_gem_reset_fences(dev);
3933
3934 i915_gem_detect_bit_6_swizzle(dev);
3935 init_waitqueue_head(&dev_priv->pending_flip_queue);
3936
3937 dev_priv->mm.interruptible = true;
3938
3939 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
3940 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
3941 register_shrinker(&dev_priv->mm.inactive_shrinker);
3942}
3943
3944/*
3945 * Create a physically contiguous memory object for this object
3946 * e.g. for cursor + overlay regs
3947 */
3948static int i915_gem_init_phys_object(struct drm_device *dev,
3949 int id, int size, int align)
3950{
3951 drm_i915_private_t *dev_priv = dev->dev_private;
3952 struct drm_i915_gem_phys_object *phys_obj;
3953 int ret;
3954
3955 if (dev_priv->mm.phys_objs[id - 1] || !size)
3956 return 0;
3957
3958 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
3959 if (!phys_obj)
3960 return -ENOMEM;
3961
3962 phys_obj->id = id;
3963
3964 phys_obj->handle = drm_pci_alloc(dev, size, align);
3965 if (!phys_obj->handle) {
3966 ret = -ENOMEM;
3967 goto kfree_obj;
3968 }
3969#ifdef CONFIG_X86
3970 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3971#endif
3972
3973 dev_priv->mm.phys_objs[id - 1] = phys_obj;
3974
3975 return 0;
3976kfree_obj:
3977 kfree(phys_obj);
3978 return ret;
3979}
3980
3981static void i915_gem_free_phys_object(struct drm_device *dev, int id)
3982{
3983 drm_i915_private_t *dev_priv = dev->dev_private;
3984 struct drm_i915_gem_phys_object *phys_obj;
3985
3986 if (!dev_priv->mm.phys_objs[id - 1])
3987 return;
3988
3989 phys_obj = dev_priv->mm.phys_objs[id - 1];
3990 if (phys_obj->cur_obj) {
3991 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
3992 }
3993
3994#ifdef CONFIG_X86
3995 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3996#endif
3997 drm_pci_free(dev, phys_obj->handle);
3998 kfree(phys_obj);
3999 dev_priv->mm.phys_objs[id - 1] = NULL;
4000}
4001
4002void i915_gem_free_all_phys_object(struct drm_device *dev)
4003{
4004 int i;
4005
4006 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4007 i915_gem_free_phys_object(dev, i);
4008}
4009
4010void i915_gem_detach_phys_object(struct drm_device *dev,
4011 struct drm_i915_gem_object *obj)
4012{
4013 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4014 char *vaddr;
4015 int i;
4016 int page_count;
4017
4018 if (!obj->phys_obj)
4019 return;
4020 vaddr = obj->phys_obj->handle->vaddr;
4021
4022 page_count = obj->base.size / PAGE_SIZE;
4023 for (i = 0; i < page_count; i++) {
4024 struct page *page = shmem_read_mapping_page(mapping, i);
4025 if (!IS_ERR(page)) {
4026 char *dst = kmap_atomic(page);
4027 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4028 kunmap_atomic(dst);
4029
4030 drm_clflush_pages(&page, 1);
4031
4032 set_page_dirty(page);
4033 mark_page_accessed(page);
4034 page_cache_release(page);
4035 }
4036 }
4037 intel_gtt_chipset_flush();
4038
4039 obj->phys_obj->cur_obj = NULL;
4040 obj->phys_obj = NULL;
4041}
4042
4043int
4044i915_gem_attach_phys_object(struct drm_device *dev,
4045 struct drm_i915_gem_object *obj,
4046 int id,
4047 int align)
4048{
4049 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4050 drm_i915_private_t *dev_priv = dev->dev_private;
4051 int ret = 0;
4052 int page_count;
4053 int i;
4054
4055 if (id > I915_MAX_PHYS_OBJECT)
4056 return -EINVAL;
4057
4058 if (obj->phys_obj) {
4059 if (obj->phys_obj->id == id)
4060 return 0;
4061 i915_gem_detach_phys_object(dev, obj);
4062 }
4063
4064 /* create a new object */
4065 if (!dev_priv->mm.phys_objs[id - 1]) {
4066 ret = i915_gem_init_phys_object(dev, id,
4067 obj->base.size, align);
4068 if (ret) {
4069 DRM_ERROR("failed to init phys object %d size: %zu\n",
4070 id, obj->base.size);
4071 return ret;
4072 }
4073 }
4074
4075 /* bind to the object */
4076 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4077 obj->phys_obj->cur_obj = obj;
4078
4079 page_count = obj->base.size / PAGE_SIZE;
4080
4081 for (i = 0; i < page_count; i++) {
4082 struct page *page;
4083 char *dst, *src;
4084
4085 page = shmem_read_mapping_page(mapping, i);
4086 if (IS_ERR(page))
4087 return PTR_ERR(page);
4088
4089 src = kmap_atomic(page);
4090 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4091 memcpy(dst, src, PAGE_SIZE);
4092 kunmap_atomic(src);
4093
4094 mark_page_accessed(page);
4095 page_cache_release(page);
4096 }
4097
4098 return 0;
4099}
4100
4101static int
4102i915_gem_phys_pwrite(struct drm_device *dev,
4103 struct drm_i915_gem_object *obj,
4104 struct drm_i915_gem_pwrite *args,
4105 struct drm_file *file_priv)
4106{
4107 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4108 char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
4109
4110 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4111 unsigned long unwritten;
4112
4113 /* The physical object once assigned is fixed for the lifetime
4114 * of the obj, so we can safely drop the lock and continue
4115 * to access vaddr.
4116 */
4117 mutex_unlock(&dev->struct_mutex);
4118 unwritten = copy_from_user(vaddr, user_data, args->size);
4119 mutex_lock(&dev->struct_mutex);
4120 if (unwritten)
4121 return -EFAULT;
4122 }
4123
4124 intel_gtt_chipset_flush();
4125 return 0;
4126}
4127
4128void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4129{
4130 struct drm_i915_file_private *file_priv = file->driver_priv;
4131
4132 /* Clean up our request list when the client is going away, so that
4133 * later retire_requests won't dereference our soon-to-be-gone
4134 * file_priv.
4135 */
4136 spin_lock(&file_priv->mm.lock);
4137 while (!list_empty(&file_priv->mm.request_list)) {
4138 struct drm_i915_gem_request *request;
4139
4140 request = list_first_entry(&file_priv->mm.request_list,
4141 struct drm_i915_gem_request,
4142 client_list);
4143 list_del(&request->client_list);
4144 request->file_priv = NULL;
4145 }
4146 spin_unlock(&file_priv->mm.lock);
4147}
4148
4149static int
4150i915_gpu_is_active(struct drm_device *dev)
4151{
4152 drm_i915_private_t *dev_priv = dev->dev_private;
4153 return !list_empty(&dev_priv->mm.active_list);
4154}
4155
4156static int
4157i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4158{
4159 struct drm_i915_private *dev_priv =
4160 container_of(shrinker,
4161 struct drm_i915_private,
4162 mm.inactive_shrinker);
4163 struct drm_device *dev = dev_priv->dev;
4164 struct drm_i915_gem_object *obj, *next;
4165 int nr_to_scan = sc->nr_to_scan;
4166 int cnt;
4167
4168 if (!mutex_trylock(&dev->struct_mutex))
4169 return 0;
4170
4171 /* "fast-path" to count number of available objects */
4172 if (nr_to_scan == 0) {
4173 cnt = 0;
4174 list_for_each_entry(obj,
4175 &dev_priv->mm.inactive_list,
4176 mm_list)
4177 cnt++;
4178 mutex_unlock(&dev->struct_mutex);
4179 return cnt / 100 * sysctl_vfs_cache_pressure;
4180 }
4181
4182rescan:
4183 /* first scan for clean buffers */
4184 i915_gem_retire_requests(dev);
4185
4186 list_for_each_entry_safe(obj, next,
4187 &dev_priv->mm.inactive_list,
4188 mm_list) {
4189 if (i915_gem_object_is_purgeable(obj)) {
4190 if (i915_gem_object_unbind(obj) == 0 &&
4191 --nr_to_scan == 0)
4192 break;
4193 }
4194 }
4195
4196 /* second pass, evict/count anything still on the inactive list */
4197 cnt = 0;
4198 list_for_each_entry_safe(obj, next,
4199 &dev_priv->mm.inactive_list,
4200 mm_list) {
4201 if (nr_to_scan &&
4202 i915_gem_object_unbind(obj) == 0)
4203 nr_to_scan--;
4204 else
4205 cnt++;
4206 }
4207
4208 if (nr_to_scan && i915_gpu_is_active(dev)) {
4209 /*
4210 * We are desperate for pages, so as a last resort, wait
4211 * for the GPU to finish and discard whatever we can.
4212 * This has a dramatic impact to reduce the number of
4213 * OOM-killer events whilst running the GPU aggressively.
4214 */
4215 if (i915_gpu_idle(dev) == 0)
4216 goto rescan;
4217 }
4218 mutex_unlock(&dev->struct_mutex);
4219 return cnt / 100 * sysctl_vfs_cache_pressure;
4220}
Linux kernel - Deliverables
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