| 1 | /* |
| 2 | * Copyright © 2008-2015 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include <drm/drmP.h> |
| 29 | #include <drm/drm_vma_manager.h> |
| 30 | #include <drm/i915_drm.h> |
| 31 | #include "i915_drv.h" |
| 32 | #include "i915_vgpu.h" |
| 33 | #include "i915_trace.h" |
| 34 | #include "intel_drv.h" |
| 35 | #include "intel_mocs.h" |
| 36 | #include <linux/shmem_fs.h> |
| 37 | #include <linux/slab.h> |
| 38 | #include <linux/swap.h> |
| 39 | #include <linux/pci.h> |
| 40 | #include <linux/dma-buf.h> |
| 41 | |
| 42 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
| 43 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
| 44 | static void |
| 45 | i915_gem_object_retire__write(struct drm_i915_gem_object *obj); |
| 46 | static void |
| 47 | i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring); |
| 48 | |
| 49 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
| 50 | enum i915_cache_level level) |
| 51 | { |
| 52 | return HAS_LLC(dev) || level != I915_CACHE_NONE; |
| 53 | } |
| 54 | |
| 55 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
| 56 | { |
| 57 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
| 58 | return true; |
| 59 | |
| 60 | return obj->pin_display; |
| 61 | } |
| 62 | |
| 63 | /* some bookkeeping */ |
| 64 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, |
| 65 | size_t size) |
| 66 | { |
| 67 | spin_lock(&dev_priv->mm.object_stat_lock); |
| 68 | dev_priv->mm.object_count++; |
| 69 | dev_priv->mm.object_memory += size; |
| 70 | spin_unlock(&dev_priv->mm.object_stat_lock); |
| 71 | } |
| 72 | |
| 73 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, |
| 74 | size_t size) |
| 75 | { |
| 76 | spin_lock(&dev_priv->mm.object_stat_lock); |
| 77 | dev_priv->mm.object_count--; |
| 78 | dev_priv->mm.object_memory -= size; |
| 79 | spin_unlock(&dev_priv->mm.object_stat_lock); |
| 80 | } |
| 81 | |
| 82 | static int |
| 83 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
| 84 | { |
| 85 | int ret; |
| 86 | |
| 87 | if (!i915_reset_in_progress(error)) |
| 88 | return 0; |
| 89 | |
| 90 | /* |
| 91 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging |
| 92 | * userspace. If it takes that long something really bad is going on and |
| 93 | * we should simply try to bail out and fail as gracefully as possible. |
| 94 | */ |
| 95 | ret = wait_event_interruptible_timeout(error->reset_queue, |
| 96 | !i915_reset_in_progress(error), |
| 97 | 10*HZ); |
| 98 | if (ret == 0) { |
| 99 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); |
| 100 | return -EIO; |
| 101 | } else if (ret < 0) { |
| 102 | return ret; |
| 103 | } else { |
| 104 | return 0; |
| 105 | } |
| 106 | } |
| 107 | |
| 108 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
| 109 | { |
| 110 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 111 | int ret; |
| 112 | |
| 113 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
| 114 | if (ret) |
| 115 | return ret; |
| 116 | |
| 117 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 118 | if (ret) |
| 119 | return ret; |
| 120 | |
| 121 | WARN_ON(i915_verify_lists(dev)); |
| 122 | return 0; |
| 123 | } |
| 124 | |
| 125 | int |
| 126 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
| 127 | struct drm_file *file) |
| 128 | { |
| 129 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 130 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
| 131 | struct drm_i915_gem_get_aperture *args = data; |
| 132 | struct i915_vma *vma; |
| 133 | size_t pinned; |
| 134 | |
| 135 | pinned = 0; |
| 136 | mutex_lock(&dev->struct_mutex); |
| 137 | list_for_each_entry(vma, &ggtt->base.active_list, vm_link) |
| 138 | if (vma->pin_count) |
| 139 | pinned += vma->node.size; |
| 140 | list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link) |
| 141 | if (vma->pin_count) |
| 142 | pinned += vma->node.size; |
| 143 | mutex_unlock(&dev->struct_mutex); |
| 144 | |
| 145 | args->aper_size = ggtt->base.total; |
| 146 | args->aper_available_size = args->aper_size - pinned; |
| 147 | |
| 148 | return 0; |
| 149 | } |
| 150 | |
| 151 | static int |
| 152 | i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) |
| 153 | { |
| 154 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
| 155 | char *vaddr = obj->phys_handle->vaddr; |
| 156 | struct sg_table *st; |
| 157 | struct scatterlist *sg; |
| 158 | int i; |
| 159 | |
| 160 | if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))) |
| 161 | return -EINVAL; |
| 162 | |
| 163 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { |
| 164 | struct page *page; |
| 165 | char *src; |
| 166 | |
| 167 | page = shmem_read_mapping_page(mapping, i); |
| 168 | if (IS_ERR(page)) |
| 169 | return PTR_ERR(page); |
| 170 | |
| 171 | src = kmap_atomic(page); |
| 172 | memcpy(vaddr, src, PAGE_SIZE); |
| 173 | drm_clflush_virt_range(vaddr, PAGE_SIZE); |
| 174 | kunmap_atomic(src); |
| 175 | |
| 176 | put_page(page); |
| 177 | vaddr += PAGE_SIZE; |
| 178 | } |
| 179 | |
| 180 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
| 181 | |
| 182 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
| 183 | if (st == NULL) |
| 184 | return -ENOMEM; |
| 185 | |
| 186 | if (sg_alloc_table(st, 1, GFP_KERNEL)) { |
| 187 | kfree(st); |
| 188 | return -ENOMEM; |
| 189 | } |
| 190 | |
| 191 | sg = st->sgl; |
| 192 | sg->offset = 0; |
| 193 | sg->length = obj->base.size; |
| 194 | |
| 195 | sg_dma_address(sg) = obj->phys_handle->busaddr; |
| 196 | sg_dma_len(sg) = obj->base.size; |
| 197 | |
| 198 | obj->pages = st; |
| 199 | return 0; |
| 200 | } |
| 201 | |
| 202 | static void |
| 203 | i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj) |
| 204 | { |
| 205 | int ret; |
| 206 | |
| 207 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
| 208 | |
| 209 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
| 210 | if (WARN_ON(ret)) { |
| 211 | /* In the event of a disaster, abandon all caches and |
| 212 | * hope for the best. |
| 213 | */ |
| 214 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 215 | } |
| 216 | |
| 217 | if (obj->madv == I915_MADV_DONTNEED) |
| 218 | obj->dirty = 0; |
| 219 | |
| 220 | if (obj->dirty) { |
| 221 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
| 222 | char *vaddr = obj->phys_handle->vaddr; |
| 223 | int i; |
| 224 | |
| 225 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { |
| 226 | struct page *page; |
| 227 | char *dst; |
| 228 | |
| 229 | page = shmem_read_mapping_page(mapping, i); |
| 230 | if (IS_ERR(page)) |
| 231 | continue; |
| 232 | |
| 233 | dst = kmap_atomic(page); |
| 234 | drm_clflush_virt_range(vaddr, PAGE_SIZE); |
| 235 | memcpy(dst, vaddr, PAGE_SIZE); |
| 236 | kunmap_atomic(dst); |
| 237 | |
| 238 | set_page_dirty(page); |
| 239 | if (obj->madv == I915_MADV_WILLNEED) |
| 240 | mark_page_accessed(page); |
| 241 | put_page(page); |
| 242 | vaddr += PAGE_SIZE; |
| 243 | } |
| 244 | obj->dirty = 0; |
| 245 | } |
| 246 | |
| 247 | sg_free_table(obj->pages); |
| 248 | kfree(obj->pages); |
| 249 | } |
| 250 | |
| 251 | static void |
| 252 | i915_gem_object_release_phys(struct drm_i915_gem_object *obj) |
| 253 | { |
| 254 | drm_pci_free(obj->base.dev, obj->phys_handle); |
| 255 | } |
| 256 | |
| 257 | static const struct drm_i915_gem_object_ops i915_gem_phys_ops = { |
| 258 | .get_pages = i915_gem_object_get_pages_phys, |
| 259 | .put_pages = i915_gem_object_put_pages_phys, |
| 260 | .release = i915_gem_object_release_phys, |
| 261 | }; |
| 262 | |
| 263 | static int |
| 264 | drop_pages(struct drm_i915_gem_object *obj) |
| 265 | { |
| 266 | struct i915_vma *vma, *next; |
| 267 | int ret; |
| 268 | |
| 269 | drm_gem_object_reference(&obj->base); |
| 270 | list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) |
| 271 | if (i915_vma_unbind(vma)) |
| 272 | break; |
| 273 | |
| 274 | ret = i915_gem_object_put_pages(obj); |
| 275 | drm_gem_object_unreference(&obj->base); |
| 276 | |
| 277 | return ret; |
| 278 | } |
| 279 | |
| 280 | int |
| 281 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, |
| 282 | int align) |
| 283 | { |
| 284 | drm_dma_handle_t *phys; |
| 285 | int ret; |
| 286 | |
| 287 | if (obj->phys_handle) { |
| 288 | if ((unsigned long)obj->phys_handle->vaddr & (align -1)) |
| 289 | return -EBUSY; |
| 290 | |
| 291 | return 0; |
| 292 | } |
| 293 | |
| 294 | if (obj->madv != I915_MADV_WILLNEED) |
| 295 | return -EFAULT; |
| 296 | |
| 297 | if (obj->base.filp == NULL) |
| 298 | return -EINVAL; |
| 299 | |
| 300 | ret = drop_pages(obj); |
| 301 | if (ret) |
| 302 | return ret; |
| 303 | |
| 304 | /* create a new object */ |
| 305 | phys = drm_pci_alloc(obj->base.dev, obj->base.size, align); |
| 306 | if (!phys) |
| 307 | return -ENOMEM; |
| 308 | |
| 309 | obj->phys_handle = phys; |
| 310 | obj->ops = &i915_gem_phys_ops; |
| 311 | |
| 312 | return i915_gem_object_get_pages(obj); |
| 313 | } |
| 314 | |
| 315 | static int |
| 316 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, |
| 317 | struct drm_i915_gem_pwrite *args, |
| 318 | struct drm_file *file_priv) |
| 319 | { |
| 320 | struct drm_device *dev = obj->base.dev; |
| 321 | void *vaddr = obj->phys_handle->vaddr + args->offset; |
| 322 | char __user *user_data = to_user_ptr(args->data_ptr); |
| 323 | int ret = 0; |
| 324 | |
| 325 | /* We manually control the domain here and pretend that it |
| 326 | * remains coherent i.e. in the GTT domain, like shmem_pwrite. |
| 327 | */ |
| 328 | ret = i915_gem_object_wait_rendering(obj, false); |
| 329 | if (ret) |
| 330 | return ret; |
| 331 | |
| 332 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
| 333 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
| 334 | unsigned long unwritten; |
| 335 | |
| 336 | /* The physical object once assigned is fixed for the lifetime |
| 337 | * of the obj, so we can safely drop the lock and continue |
| 338 | * to access vaddr. |
| 339 | */ |
| 340 | mutex_unlock(&dev->struct_mutex); |
| 341 | unwritten = copy_from_user(vaddr, user_data, args->size); |
| 342 | mutex_lock(&dev->struct_mutex); |
| 343 | if (unwritten) { |
| 344 | ret = -EFAULT; |
| 345 | goto out; |
| 346 | } |
| 347 | } |
| 348 | |
| 349 | drm_clflush_virt_range(vaddr, args->size); |
| 350 | i915_gem_chipset_flush(to_i915(dev)); |
| 351 | |
| 352 | out: |
| 353 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
| 354 | return ret; |
| 355 | } |
| 356 | |
| 357 | void *i915_gem_object_alloc(struct drm_device *dev) |
| 358 | { |
| 359 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 360 | return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL); |
| 361 | } |
| 362 | |
| 363 | void i915_gem_object_free(struct drm_i915_gem_object *obj) |
| 364 | { |
| 365 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 366 | kmem_cache_free(dev_priv->objects, obj); |
| 367 | } |
| 368 | |
| 369 | static int |
| 370 | i915_gem_create(struct drm_file *file, |
| 371 | struct drm_device *dev, |
| 372 | uint64_t size, |
| 373 | uint32_t *handle_p) |
| 374 | { |
| 375 | struct drm_i915_gem_object *obj; |
| 376 | int ret; |
| 377 | u32 handle; |
| 378 | |
| 379 | size = roundup(size, PAGE_SIZE); |
| 380 | if (size == 0) |
| 381 | return -EINVAL; |
| 382 | |
| 383 | /* Allocate the new object */ |
| 384 | obj = i915_gem_object_create(dev, size); |
| 385 | if (IS_ERR(obj)) |
| 386 | return PTR_ERR(obj); |
| 387 | |
| 388 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
| 389 | /* drop reference from allocate - handle holds it now */ |
| 390 | drm_gem_object_unreference_unlocked(&obj->base); |
| 391 | if (ret) |
| 392 | return ret; |
| 393 | |
| 394 | *handle_p = handle; |
| 395 | return 0; |
| 396 | } |
| 397 | |
| 398 | int |
| 399 | i915_gem_dumb_create(struct drm_file *file, |
| 400 | struct drm_device *dev, |
| 401 | struct drm_mode_create_dumb *args) |
| 402 | { |
| 403 | /* have to work out size/pitch and return them */ |
| 404 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
| 405 | args->size = args->pitch * args->height; |
| 406 | return i915_gem_create(file, dev, |
| 407 | args->size, &args->handle); |
| 408 | } |
| 409 | |
| 410 | /** |
| 411 | * Creates a new mm object and returns a handle to it. |
| 412 | */ |
| 413 | int |
| 414 | i915_gem_create_ioctl(struct drm_device *dev, void *data, |
| 415 | struct drm_file *file) |
| 416 | { |
| 417 | struct drm_i915_gem_create *args = data; |
| 418 | |
| 419 | return i915_gem_create(file, dev, |
| 420 | args->size, &args->handle); |
| 421 | } |
| 422 | |
| 423 | static inline int |
| 424 | __copy_to_user_swizzled(char __user *cpu_vaddr, |
| 425 | const char *gpu_vaddr, int gpu_offset, |
| 426 | int length) |
| 427 | { |
| 428 | int ret, cpu_offset = 0; |
| 429 | |
| 430 | while (length > 0) { |
| 431 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 432 | int this_length = min(cacheline_end - gpu_offset, length); |
| 433 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 434 | |
| 435 | ret = __copy_to_user(cpu_vaddr + cpu_offset, |
| 436 | gpu_vaddr + swizzled_gpu_offset, |
| 437 | this_length); |
| 438 | if (ret) |
| 439 | return ret + length; |
| 440 | |
| 441 | cpu_offset += this_length; |
| 442 | gpu_offset += this_length; |
| 443 | length -= this_length; |
| 444 | } |
| 445 | |
| 446 | return 0; |
| 447 | } |
| 448 | |
| 449 | static inline int |
| 450 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
| 451 | const char __user *cpu_vaddr, |
| 452 | int length) |
| 453 | { |
| 454 | int ret, cpu_offset = 0; |
| 455 | |
| 456 | while (length > 0) { |
| 457 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 458 | int this_length = min(cacheline_end - gpu_offset, length); |
| 459 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 460 | |
| 461 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, |
| 462 | cpu_vaddr + cpu_offset, |
| 463 | this_length); |
| 464 | if (ret) |
| 465 | return ret + length; |
| 466 | |
| 467 | cpu_offset += this_length; |
| 468 | gpu_offset += this_length; |
| 469 | length -= this_length; |
| 470 | } |
| 471 | |
| 472 | return 0; |
| 473 | } |
| 474 | |
| 475 | /* |
| 476 | * Pins the specified object's pages and synchronizes the object with |
| 477 | * GPU accesses. Sets needs_clflush to non-zero if the caller should |
| 478 | * flush the object from the CPU cache. |
| 479 | */ |
| 480 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, |
| 481 | int *needs_clflush) |
| 482 | { |
| 483 | int ret; |
| 484 | |
| 485 | *needs_clflush = 0; |
| 486 | |
| 487 | if (WARN_ON((obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE) == 0)) |
| 488 | return -EINVAL; |
| 489 | |
| 490 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
| 491 | /* If we're not in the cpu read domain, set ourself into the gtt |
| 492 | * read domain and manually flush cachelines (if required). This |
| 493 | * optimizes for the case when the gpu will dirty the data |
| 494 | * anyway again before the next pread happens. */ |
| 495 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, |
| 496 | obj->cache_level); |
| 497 | ret = i915_gem_object_wait_rendering(obj, true); |
| 498 | if (ret) |
| 499 | return ret; |
| 500 | } |
| 501 | |
| 502 | ret = i915_gem_object_get_pages(obj); |
| 503 | if (ret) |
| 504 | return ret; |
| 505 | |
| 506 | i915_gem_object_pin_pages(obj); |
| 507 | |
| 508 | return ret; |
| 509 | } |
| 510 | |
| 511 | /* Per-page copy function for the shmem pread fastpath. |
| 512 | * Flushes invalid cachelines before reading the target if |
| 513 | * needs_clflush is set. */ |
| 514 | static int |
| 515 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
| 516 | char __user *user_data, |
| 517 | bool page_do_bit17_swizzling, bool needs_clflush) |
| 518 | { |
| 519 | char *vaddr; |
| 520 | int ret; |
| 521 | |
| 522 | if (unlikely(page_do_bit17_swizzling)) |
| 523 | return -EINVAL; |
| 524 | |
| 525 | vaddr = kmap_atomic(page); |
| 526 | if (needs_clflush) |
| 527 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 528 | page_length); |
| 529 | ret = __copy_to_user_inatomic(user_data, |
| 530 | vaddr + shmem_page_offset, |
| 531 | page_length); |
| 532 | kunmap_atomic(vaddr); |
| 533 | |
| 534 | return ret ? -EFAULT : 0; |
| 535 | } |
| 536 | |
| 537 | static void |
| 538 | shmem_clflush_swizzled_range(char *addr, unsigned long length, |
| 539 | bool swizzled) |
| 540 | { |
| 541 | if (unlikely(swizzled)) { |
| 542 | unsigned long start = (unsigned long) addr; |
| 543 | unsigned long end = (unsigned long) addr + length; |
| 544 | |
| 545 | /* For swizzling simply ensure that we always flush both |
| 546 | * channels. Lame, but simple and it works. Swizzled |
| 547 | * pwrite/pread is far from a hotpath - current userspace |
| 548 | * doesn't use it at all. */ |
| 549 | start = round_down(start, 128); |
| 550 | end = round_up(end, 128); |
| 551 | |
| 552 | drm_clflush_virt_range((void *)start, end - start); |
| 553 | } else { |
| 554 | drm_clflush_virt_range(addr, length); |
| 555 | } |
| 556 | |
| 557 | } |
| 558 | |
| 559 | /* Only difference to the fast-path function is that this can handle bit17 |
| 560 | * and uses non-atomic copy and kmap functions. */ |
| 561 | static int |
| 562 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, |
| 563 | char __user *user_data, |
| 564 | bool page_do_bit17_swizzling, bool needs_clflush) |
| 565 | { |
| 566 | char *vaddr; |
| 567 | int ret; |
| 568 | |
| 569 | vaddr = kmap(page); |
| 570 | if (needs_clflush) |
| 571 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 572 | page_length, |
| 573 | page_do_bit17_swizzling); |
| 574 | |
| 575 | if (page_do_bit17_swizzling) |
| 576 | ret = __copy_to_user_swizzled(user_data, |
| 577 | vaddr, shmem_page_offset, |
| 578 | page_length); |
| 579 | else |
| 580 | ret = __copy_to_user(user_data, |
| 581 | vaddr + shmem_page_offset, |
| 582 | page_length); |
| 583 | kunmap(page); |
| 584 | |
| 585 | return ret ? - EFAULT : 0; |
| 586 | } |
| 587 | |
| 588 | static int |
| 589 | i915_gem_shmem_pread(struct drm_device *dev, |
| 590 | struct drm_i915_gem_object *obj, |
| 591 | struct drm_i915_gem_pread *args, |
| 592 | struct drm_file *file) |
| 593 | { |
| 594 | char __user *user_data; |
| 595 | ssize_t remain; |
| 596 | loff_t offset; |
| 597 | int shmem_page_offset, page_length, ret = 0; |
| 598 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
| 599 | int prefaulted = 0; |
| 600 | int needs_clflush = 0; |
| 601 | struct sg_page_iter sg_iter; |
| 602 | |
| 603 | user_data = to_user_ptr(args->data_ptr); |
| 604 | remain = args->size; |
| 605 | |
| 606 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
| 607 | |
| 608 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); |
| 609 | if (ret) |
| 610 | return ret; |
| 611 | |
| 612 | offset = args->offset; |
| 613 | |
| 614 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
| 615 | offset >> PAGE_SHIFT) { |
| 616 | struct page *page = sg_page_iter_page(&sg_iter); |
| 617 | |
| 618 | if (remain <= 0) |
| 619 | break; |
| 620 | |
| 621 | /* Operation in this page |
| 622 | * |
| 623 | * shmem_page_offset = offset within page in shmem file |
| 624 | * page_length = bytes to copy for this page |
| 625 | */ |
| 626 | shmem_page_offset = offset_in_page(offset); |
| 627 | page_length = remain; |
| 628 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 629 | page_length = PAGE_SIZE - shmem_page_offset; |
| 630 | |
| 631 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
| 632 | (page_to_phys(page) & (1 << 17)) != 0; |
| 633 | |
| 634 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
| 635 | user_data, page_do_bit17_swizzling, |
| 636 | needs_clflush); |
| 637 | if (ret == 0) |
| 638 | goto next_page; |
| 639 | |
| 640 | mutex_unlock(&dev->struct_mutex); |
| 641 | |
| 642 | if (likely(!i915.prefault_disable) && !prefaulted) { |
| 643 | ret = fault_in_multipages_writeable(user_data, remain); |
| 644 | /* Userspace is tricking us, but we've already clobbered |
| 645 | * its pages with the prefault and promised to write the |
| 646 | * data up to the first fault. Hence ignore any errors |
| 647 | * and just continue. */ |
| 648 | (void)ret; |
| 649 | prefaulted = 1; |
| 650 | } |
| 651 | |
| 652 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
| 653 | user_data, page_do_bit17_swizzling, |
| 654 | needs_clflush); |
| 655 | |
| 656 | mutex_lock(&dev->struct_mutex); |
| 657 | |
| 658 | if (ret) |
| 659 | goto out; |
| 660 | |
| 661 | next_page: |
| 662 | remain -= page_length; |
| 663 | user_data += page_length; |
| 664 | offset += page_length; |
| 665 | } |
| 666 | |
| 667 | out: |
| 668 | i915_gem_object_unpin_pages(obj); |
| 669 | |
| 670 | return ret; |
| 671 | } |
| 672 | |
| 673 | /** |
| 674 | * Reads data from the object referenced by handle. |
| 675 | * |
| 676 | * On error, the contents of *data are undefined. |
| 677 | */ |
| 678 | int |
| 679 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
| 680 | struct drm_file *file) |
| 681 | { |
| 682 | struct drm_i915_gem_pread *args = data; |
| 683 | struct drm_i915_gem_object *obj; |
| 684 | int ret = 0; |
| 685 | |
| 686 | if (args->size == 0) |
| 687 | return 0; |
| 688 | |
| 689 | if (!access_ok(VERIFY_WRITE, |
| 690 | to_user_ptr(args->data_ptr), |
| 691 | args->size)) |
| 692 | return -EFAULT; |
| 693 | |
| 694 | ret = i915_mutex_lock_interruptible(dev); |
| 695 | if (ret) |
| 696 | return ret; |
| 697 | |
| 698 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
| 699 | if (&obj->base == NULL) { |
| 700 | ret = -ENOENT; |
| 701 | goto unlock; |
| 702 | } |
| 703 | |
| 704 | /* Bounds check source. */ |
| 705 | if (args->offset > obj->base.size || |
| 706 | args->size > obj->base.size - args->offset) { |
| 707 | ret = -EINVAL; |
| 708 | goto out; |
| 709 | } |
| 710 | |
| 711 | /* prime objects have no backing filp to GEM pread/pwrite |
| 712 | * pages from. |
| 713 | */ |
| 714 | if (!obj->base.filp) { |
| 715 | ret = -EINVAL; |
| 716 | goto out; |
| 717 | } |
| 718 | |
| 719 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
| 720 | |
| 721 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
| 722 | |
| 723 | out: |
| 724 | drm_gem_object_unreference(&obj->base); |
| 725 | unlock: |
| 726 | mutex_unlock(&dev->struct_mutex); |
| 727 | return ret; |
| 728 | } |
| 729 | |
| 730 | /* This is the fast write path which cannot handle |
| 731 | * page faults in the source data |
| 732 | */ |
| 733 | |
| 734 | static inline int |
| 735 | fast_user_write(struct io_mapping *mapping, |
| 736 | loff_t page_base, int page_offset, |
| 737 | char __user *user_data, |
| 738 | int length) |
| 739 | { |
| 740 | void __iomem *vaddr_atomic; |
| 741 | void *vaddr; |
| 742 | unsigned long unwritten; |
| 743 | |
| 744 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
| 745 | /* We can use the cpu mem copy function because this is X86. */ |
| 746 | vaddr = (void __force*)vaddr_atomic + page_offset; |
| 747 | unwritten = __copy_from_user_inatomic_nocache(vaddr, |
| 748 | user_data, length); |
| 749 | io_mapping_unmap_atomic(vaddr_atomic); |
| 750 | return unwritten; |
| 751 | } |
| 752 | |
| 753 | /** |
| 754 | * This is the fast pwrite path, where we copy the data directly from the |
| 755 | * user into the GTT, uncached. |
| 756 | */ |
| 757 | static int |
| 758 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
| 759 | struct drm_i915_gem_object *obj, |
| 760 | struct drm_i915_gem_pwrite *args, |
| 761 | struct drm_file *file) |
| 762 | { |
| 763 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 764 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
| 765 | ssize_t remain; |
| 766 | loff_t offset, page_base; |
| 767 | char __user *user_data; |
| 768 | int page_offset, page_length, ret; |
| 769 | |
| 770 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK); |
| 771 | if (ret) |
| 772 | goto out; |
| 773 | |
| 774 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| 775 | if (ret) |
| 776 | goto out_unpin; |
| 777 | |
| 778 | ret = i915_gem_object_put_fence(obj); |
| 779 | if (ret) |
| 780 | goto out_unpin; |
| 781 | |
| 782 | user_data = to_user_ptr(args->data_ptr); |
| 783 | remain = args->size; |
| 784 | |
| 785 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
| 786 | |
| 787 | intel_fb_obj_invalidate(obj, ORIGIN_GTT); |
| 788 | |
| 789 | while (remain > 0) { |
| 790 | /* Operation in this page |
| 791 | * |
| 792 | * page_base = page offset within aperture |
| 793 | * page_offset = offset within page |
| 794 | * page_length = bytes to copy for this page |
| 795 | */ |
| 796 | page_base = offset & PAGE_MASK; |
| 797 | page_offset = offset_in_page(offset); |
| 798 | page_length = remain; |
| 799 | if ((page_offset + remain) > PAGE_SIZE) |
| 800 | page_length = PAGE_SIZE - page_offset; |
| 801 | |
| 802 | /* If we get a fault while copying data, then (presumably) our |
| 803 | * source page isn't available. Return the error and we'll |
| 804 | * retry in the slow path. |
| 805 | */ |
| 806 | if (fast_user_write(ggtt->mappable, page_base, |
| 807 | page_offset, user_data, page_length)) { |
| 808 | ret = -EFAULT; |
| 809 | goto out_flush; |
| 810 | } |
| 811 | |
| 812 | remain -= page_length; |
| 813 | user_data += page_length; |
| 814 | offset += page_length; |
| 815 | } |
| 816 | |
| 817 | out_flush: |
| 818 | intel_fb_obj_flush(obj, false, ORIGIN_GTT); |
| 819 | out_unpin: |
| 820 | i915_gem_object_ggtt_unpin(obj); |
| 821 | out: |
| 822 | return ret; |
| 823 | } |
| 824 | |
| 825 | /* Per-page copy function for the shmem pwrite fastpath. |
| 826 | * Flushes invalid cachelines before writing to the target if |
| 827 | * needs_clflush_before is set and flushes out any written cachelines after |
| 828 | * writing if needs_clflush is set. */ |
| 829 | static int |
| 830 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
| 831 | char __user *user_data, |
| 832 | bool page_do_bit17_swizzling, |
| 833 | bool needs_clflush_before, |
| 834 | bool needs_clflush_after) |
| 835 | { |
| 836 | char *vaddr; |
| 837 | int ret; |
| 838 | |
| 839 | if (unlikely(page_do_bit17_swizzling)) |
| 840 | return -EINVAL; |
| 841 | |
| 842 | vaddr = kmap_atomic(page); |
| 843 | if (needs_clflush_before) |
| 844 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 845 | page_length); |
| 846 | ret = __copy_from_user_inatomic(vaddr + shmem_page_offset, |
| 847 | user_data, page_length); |
| 848 | if (needs_clflush_after) |
| 849 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 850 | page_length); |
| 851 | kunmap_atomic(vaddr); |
| 852 | |
| 853 | return ret ? -EFAULT : 0; |
| 854 | } |
| 855 | |
| 856 | /* Only difference to the fast-path function is that this can handle bit17 |
| 857 | * and uses non-atomic copy and kmap functions. */ |
| 858 | static int |
| 859 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
| 860 | char __user *user_data, |
| 861 | bool page_do_bit17_swizzling, |
| 862 | bool needs_clflush_before, |
| 863 | bool needs_clflush_after) |
| 864 | { |
| 865 | char *vaddr; |
| 866 | int ret; |
| 867 | |
| 868 | vaddr = kmap(page); |
| 869 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
| 870 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 871 | page_length, |
| 872 | page_do_bit17_swizzling); |
| 873 | if (page_do_bit17_swizzling) |
| 874 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, |
| 875 | user_data, |
| 876 | page_length); |
| 877 | else |
| 878 | ret = __copy_from_user(vaddr + shmem_page_offset, |
| 879 | user_data, |
| 880 | page_length); |
| 881 | if (needs_clflush_after) |
| 882 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 883 | page_length, |
| 884 | page_do_bit17_swizzling); |
| 885 | kunmap(page); |
| 886 | |
| 887 | return ret ? -EFAULT : 0; |
| 888 | } |
| 889 | |
| 890 | static int |
| 891 | i915_gem_shmem_pwrite(struct drm_device *dev, |
| 892 | struct drm_i915_gem_object *obj, |
| 893 | struct drm_i915_gem_pwrite *args, |
| 894 | struct drm_file *file) |
| 895 | { |
| 896 | ssize_t remain; |
| 897 | loff_t offset; |
| 898 | char __user *user_data; |
| 899 | int shmem_page_offset, page_length, ret = 0; |
| 900 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
| 901 | int hit_slowpath = 0; |
| 902 | int needs_clflush_after = 0; |
| 903 | int needs_clflush_before = 0; |
| 904 | struct sg_page_iter sg_iter; |
| 905 | |
| 906 | user_data = to_user_ptr(args->data_ptr); |
| 907 | remain = args->size; |
| 908 | |
| 909 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
| 910 | |
| 911 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
| 912 | /* If we're not in the cpu write domain, set ourself into the gtt |
| 913 | * write domain and manually flush cachelines (if required). This |
| 914 | * optimizes for the case when the gpu will use the data |
| 915 | * right away and we therefore have to clflush anyway. */ |
| 916 | needs_clflush_after = cpu_write_needs_clflush(obj); |
| 917 | ret = i915_gem_object_wait_rendering(obj, false); |
| 918 | if (ret) |
| 919 | return ret; |
| 920 | } |
| 921 | /* Same trick applies to invalidate partially written cachelines read |
| 922 | * before writing. */ |
| 923 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) |
| 924 | needs_clflush_before = |
| 925 | !cpu_cache_is_coherent(dev, obj->cache_level); |
| 926 | |
| 927 | ret = i915_gem_object_get_pages(obj); |
| 928 | if (ret) |
| 929 | return ret; |
| 930 | |
| 931 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
| 932 | |
| 933 | i915_gem_object_pin_pages(obj); |
| 934 | |
| 935 | offset = args->offset; |
| 936 | obj->dirty = 1; |
| 937 | |
| 938 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
| 939 | offset >> PAGE_SHIFT) { |
| 940 | struct page *page = sg_page_iter_page(&sg_iter); |
| 941 | int partial_cacheline_write; |
| 942 | |
| 943 | if (remain <= 0) |
| 944 | break; |
| 945 | |
| 946 | /* Operation in this page |
| 947 | * |
| 948 | * shmem_page_offset = offset within page in shmem file |
| 949 | * page_length = bytes to copy for this page |
| 950 | */ |
| 951 | shmem_page_offset = offset_in_page(offset); |
| 952 | |
| 953 | page_length = remain; |
| 954 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 955 | page_length = PAGE_SIZE - shmem_page_offset; |
| 956 | |
| 957 | /* If we don't overwrite a cacheline completely we need to be |
| 958 | * careful to have up-to-date data by first clflushing. Don't |
| 959 | * overcomplicate things and flush the entire patch. */ |
| 960 | partial_cacheline_write = needs_clflush_before && |
| 961 | ((shmem_page_offset | page_length) |
| 962 | & (boot_cpu_data.x86_clflush_size - 1)); |
| 963 | |
| 964 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
| 965 | (page_to_phys(page) & (1 << 17)) != 0; |
| 966 | |
| 967 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
| 968 | user_data, page_do_bit17_swizzling, |
| 969 | partial_cacheline_write, |
| 970 | needs_clflush_after); |
| 971 | if (ret == 0) |
| 972 | goto next_page; |
| 973 | |
| 974 | hit_slowpath = 1; |
| 975 | mutex_unlock(&dev->struct_mutex); |
| 976 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
| 977 | user_data, page_do_bit17_swizzling, |
| 978 | partial_cacheline_write, |
| 979 | needs_clflush_after); |
| 980 | |
| 981 | mutex_lock(&dev->struct_mutex); |
| 982 | |
| 983 | if (ret) |
| 984 | goto out; |
| 985 | |
| 986 | next_page: |
| 987 | remain -= page_length; |
| 988 | user_data += page_length; |
| 989 | offset += page_length; |
| 990 | } |
| 991 | |
| 992 | out: |
| 993 | i915_gem_object_unpin_pages(obj); |
| 994 | |
| 995 | if (hit_slowpath) { |
| 996 | /* |
| 997 | * Fixup: Flush cpu caches in case we didn't flush the dirty |
| 998 | * cachelines in-line while writing and the object moved |
| 999 | * out of the cpu write domain while we've dropped the lock. |
| 1000 | */ |
| 1001 | if (!needs_clflush_after && |
| 1002 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
| 1003 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
| 1004 | needs_clflush_after = true; |
| 1005 | } |
| 1006 | } |
| 1007 | |
| 1008 | if (needs_clflush_after) |
| 1009 | i915_gem_chipset_flush(to_i915(dev)); |
| 1010 | else |
| 1011 | obj->cache_dirty = true; |
| 1012 | |
| 1013 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
| 1014 | return ret; |
| 1015 | } |
| 1016 | |
| 1017 | /** |
| 1018 | * Writes data to the object referenced by handle. |
| 1019 | * |
| 1020 | * On error, the contents of the buffer that were to be modified are undefined. |
| 1021 | */ |
| 1022 | int |
| 1023 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
| 1024 | struct drm_file *file) |
| 1025 | { |
| 1026 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1027 | struct drm_i915_gem_pwrite *args = data; |
| 1028 | struct drm_i915_gem_object *obj; |
| 1029 | int ret; |
| 1030 | |
| 1031 | if (args->size == 0) |
| 1032 | return 0; |
| 1033 | |
| 1034 | if (!access_ok(VERIFY_READ, |
| 1035 | to_user_ptr(args->data_ptr), |
| 1036 | args->size)) |
| 1037 | return -EFAULT; |
| 1038 | |
| 1039 | if (likely(!i915.prefault_disable)) { |
| 1040 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), |
| 1041 | args->size); |
| 1042 | if (ret) |
| 1043 | return -EFAULT; |
| 1044 | } |
| 1045 | |
| 1046 | intel_runtime_pm_get(dev_priv); |
| 1047 | |
| 1048 | ret = i915_mutex_lock_interruptible(dev); |
| 1049 | if (ret) |
| 1050 | goto put_rpm; |
| 1051 | |
| 1052 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
| 1053 | if (&obj->base == NULL) { |
| 1054 | ret = -ENOENT; |
| 1055 | goto unlock; |
| 1056 | } |
| 1057 | |
| 1058 | /* Bounds check destination. */ |
| 1059 | if (args->offset > obj->base.size || |
| 1060 | args->size > obj->base.size - args->offset) { |
| 1061 | ret = -EINVAL; |
| 1062 | goto out; |
| 1063 | } |
| 1064 | |
| 1065 | /* prime objects have no backing filp to GEM pread/pwrite |
| 1066 | * pages from. |
| 1067 | */ |
| 1068 | if (!obj->base.filp) { |
| 1069 | ret = -EINVAL; |
| 1070 | goto out; |
| 1071 | } |
| 1072 | |
| 1073 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
| 1074 | |
| 1075 | ret = -EFAULT; |
| 1076 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
| 1077 | * it would end up going through the fenced access, and we'll get |
| 1078 | * different detiling behavior between reading and writing. |
| 1079 | * pread/pwrite currently are reading and writing from the CPU |
| 1080 | * perspective, requiring manual detiling by the client. |
| 1081 | */ |
| 1082 | if (obj->tiling_mode == I915_TILING_NONE && |
| 1083 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && |
| 1084 | cpu_write_needs_clflush(obj)) { |
| 1085 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
| 1086 | /* Note that the gtt paths might fail with non-page-backed user |
| 1087 | * pointers (e.g. gtt mappings when moving data between |
| 1088 | * textures). Fallback to the shmem path in that case. */ |
| 1089 | } |
| 1090 | |
| 1091 | if (ret == -EFAULT || ret == -ENOSPC) { |
| 1092 | if (obj->phys_handle) |
| 1093 | ret = i915_gem_phys_pwrite(obj, args, file); |
| 1094 | else |
| 1095 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
| 1096 | } |
| 1097 | |
| 1098 | out: |
| 1099 | drm_gem_object_unreference(&obj->base); |
| 1100 | unlock: |
| 1101 | mutex_unlock(&dev->struct_mutex); |
| 1102 | put_rpm: |
| 1103 | intel_runtime_pm_put(dev_priv); |
| 1104 | |
| 1105 | return ret; |
| 1106 | } |
| 1107 | |
| 1108 | static int |
| 1109 | i915_gem_check_wedge(unsigned reset_counter, bool interruptible) |
| 1110 | { |
| 1111 | if (__i915_terminally_wedged(reset_counter)) |
| 1112 | return -EIO; |
| 1113 | |
| 1114 | if (__i915_reset_in_progress(reset_counter)) { |
| 1115 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
| 1116 | * -EIO unconditionally for these. */ |
| 1117 | if (!interruptible) |
| 1118 | return -EIO; |
| 1119 | |
| 1120 | return -EAGAIN; |
| 1121 | } |
| 1122 | |
| 1123 | return 0; |
| 1124 | } |
| 1125 | |
| 1126 | static void fake_irq(unsigned long data) |
| 1127 | { |
| 1128 | wake_up_process((struct task_struct *)data); |
| 1129 | } |
| 1130 | |
| 1131 | static bool missed_irq(struct drm_i915_private *dev_priv, |
| 1132 | struct intel_engine_cs *engine) |
| 1133 | { |
| 1134 | return test_bit(engine->id, &dev_priv->gpu_error.missed_irq_rings); |
| 1135 | } |
| 1136 | |
| 1137 | static unsigned long local_clock_us(unsigned *cpu) |
| 1138 | { |
| 1139 | unsigned long t; |
| 1140 | |
| 1141 | /* Cheaply and approximately convert from nanoseconds to microseconds. |
| 1142 | * The result and subsequent calculations are also defined in the same |
| 1143 | * approximate microseconds units. The principal source of timing |
| 1144 | * error here is from the simple truncation. |
| 1145 | * |
| 1146 | * Note that local_clock() is only defined wrt to the current CPU; |
| 1147 | * the comparisons are no longer valid if we switch CPUs. Instead of |
| 1148 | * blocking preemption for the entire busywait, we can detect the CPU |
| 1149 | * switch and use that as indicator of system load and a reason to |
| 1150 | * stop busywaiting, see busywait_stop(). |
| 1151 | */ |
| 1152 | *cpu = get_cpu(); |
| 1153 | t = local_clock() >> 10; |
| 1154 | put_cpu(); |
| 1155 | |
| 1156 | return t; |
| 1157 | } |
| 1158 | |
| 1159 | static bool busywait_stop(unsigned long timeout, unsigned cpu) |
| 1160 | { |
| 1161 | unsigned this_cpu; |
| 1162 | |
| 1163 | if (time_after(local_clock_us(&this_cpu), timeout)) |
| 1164 | return true; |
| 1165 | |
| 1166 | return this_cpu != cpu; |
| 1167 | } |
| 1168 | |
| 1169 | static int __i915_spin_request(struct drm_i915_gem_request *req, int state) |
| 1170 | { |
| 1171 | unsigned long timeout; |
| 1172 | unsigned cpu; |
| 1173 | |
| 1174 | /* When waiting for high frequency requests, e.g. during synchronous |
| 1175 | * rendering split between the CPU and GPU, the finite amount of time |
| 1176 | * required to set up the irq and wait upon it limits the response |
| 1177 | * rate. By busywaiting on the request completion for a short while we |
| 1178 | * can service the high frequency waits as quick as possible. However, |
| 1179 | * if it is a slow request, we want to sleep as quickly as possible. |
| 1180 | * The tradeoff between waiting and sleeping is roughly the time it |
| 1181 | * takes to sleep on a request, on the order of a microsecond. |
| 1182 | */ |
| 1183 | |
| 1184 | if (req->engine->irq_refcount) |
| 1185 | return -EBUSY; |
| 1186 | |
| 1187 | /* Only spin if we know the GPU is processing this request */ |
| 1188 | if (!i915_gem_request_started(req, true)) |
| 1189 | return -EAGAIN; |
| 1190 | |
| 1191 | timeout = local_clock_us(&cpu) + 5; |
| 1192 | while (!need_resched()) { |
| 1193 | if (i915_gem_request_completed(req, true)) |
| 1194 | return 0; |
| 1195 | |
| 1196 | if (signal_pending_state(state, current)) |
| 1197 | break; |
| 1198 | |
| 1199 | if (busywait_stop(timeout, cpu)) |
| 1200 | break; |
| 1201 | |
| 1202 | cpu_relax_lowlatency(); |
| 1203 | } |
| 1204 | |
| 1205 | if (i915_gem_request_completed(req, false)) |
| 1206 | return 0; |
| 1207 | |
| 1208 | return -EAGAIN; |
| 1209 | } |
| 1210 | |
| 1211 | /** |
| 1212 | * __i915_wait_request - wait until execution of request has finished |
| 1213 | * @req: duh! |
| 1214 | * @interruptible: do an interruptible wait (normally yes) |
| 1215 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining |
| 1216 | * |
| 1217 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
| 1218 | * values have been read by the caller in an smp safe manner. Where read-side |
| 1219 | * locks are involved, it is sufficient to read the reset_counter before |
| 1220 | * unlocking the lock that protects the seqno. For lockless tricks, the |
| 1221 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be |
| 1222 | * inserted. |
| 1223 | * |
| 1224 | * Returns 0 if the request was found within the alloted time. Else returns the |
| 1225 | * errno with remaining time filled in timeout argument. |
| 1226 | */ |
| 1227 | int __i915_wait_request(struct drm_i915_gem_request *req, |
| 1228 | bool interruptible, |
| 1229 | s64 *timeout, |
| 1230 | struct intel_rps_client *rps) |
| 1231 | { |
| 1232 | struct intel_engine_cs *engine = i915_gem_request_get_engine(req); |
| 1233 | struct drm_i915_private *dev_priv = req->i915; |
| 1234 | const bool irq_test_in_progress = |
| 1235 | ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_engine_flag(engine); |
| 1236 | int state = interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE; |
| 1237 | DEFINE_WAIT(wait); |
| 1238 | unsigned long timeout_expire; |
| 1239 | s64 before = 0; /* Only to silence a compiler warning. */ |
| 1240 | int ret; |
| 1241 | |
| 1242 | WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled"); |
| 1243 | |
| 1244 | if (list_empty(&req->list)) |
| 1245 | return 0; |
| 1246 | |
| 1247 | if (i915_gem_request_completed(req, true)) |
| 1248 | return 0; |
| 1249 | |
| 1250 | timeout_expire = 0; |
| 1251 | if (timeout) { |
| 1252 | if (WARN_ON(*timeout < 0)) |
| 1253 | return -EINVAL; |
| 1254 | |
| 1255 | if (*timeout == 0) |
| 1256 | return -ETIME; |
| 1257 | |
| 1258 | timeout_expire = jiffies + nsecs_to_jiffies_timeout(*timeout); |
| 1259 | |
| 1260 | /* |
| 1261 | * Record current time in case interrupted by signal, or wedged. |
| 1262 | */ |
| 1263 | before = ktime_get_raw_ns(); |
| 1264 | } |
| 1265 | |
| 1266 | if (INTEL_INFO(dev_priv)->gen >= 6) |
| 1267 | gen6_rps_boost(dev_priv, rps, req->emitted_jiffies); |
| 1268 | |
| 1269 | trace_i915_gem_request_wait_begin(req); |
| 1270 | |
| 1271 | /* Optimistic spin for the next jiffie before touching IRQs */ |
| 1272 | ret = __i915_spin_request(req, state); |
| 1273 | if (ret == 0) |
| 1274 | goto out; |
| 1275 | |
| 1276 | if (!irq_test_in_progress && WARN_ON(!engine->irq_get(engine))) { |
| 1277 | ret = -ENODEV; |
| 1278 | goto out; |
| 1279 | } |
| 1280 | |
| 1281 | for (;;) { |
| 1282 | struct timer_list timer; |
| 1283 | |
| 1284 | prepare_to_wait(&engine->irq_queue, &wait, state); |
| 1285 | |
| 1286 | /* We need to check whether any gpu reset happened in between |
| 1287 | * the request being submitted and now. If a reset has occurred, |
| 1288 | * the request is effectively complete (we either are in the |
| 1289 | * process of or have discarded the rendering and completely |
| 1290 | * reset the GPU. The results of the request are lost and we |
| 1291 | * are free to continue on with the original operation. |
| 1292 | */ |
| 1293 | if (req->reset_counter != i915_reset_counter(&dev_priv->gpu_error)) { |
| 1294 | ret = 0; |
| 1295 | break; |
| 1296 | } |
| 1297 | |
| 1298 | if (i915_gem_request_completed(req, false)) { |
| 1299 | ret = 0; |
| 1300 | break; |
| 1301 | } |
| 1302 | |
| 1303 | if (signal_pending_state(state, current)) { |
| 1304 | ret = -ERESTARTSYS; |
| 1305 | break; |
| 1306 | } |
| 1307 | |
| 1308 | if (timeout && time_after_eq(jiffies, timeout_expire)) { |
| 1309 | ret = -ETIME; |
| 1310 | break; |
| 1311 | } |
| 1312 | |
| 1313 | timer.function = NULL; |
| 1314 | if (timeout || missed_irq(dev_priv, engine)) { |
| 1315 | unsigned long expire; |
| 1316 | |
| 1317 | setup_timer_on_stack(&timer, fake_irq, (unsigned long)current); |
| 1318 | expire = missed_irq(dev_priv, engine) ? jiffies + 1 : timeout_expire; |
| 1319 | mod_timer(&timer, expire); |
| 1320 | } |
| 1321 | |
| 1322 | io_schedule(); |
| 1323 | |
| 1324 | if (timer.function) { |
| 1325 | del_singleshot_timer_sync(&timer); |
| 1326 | destroy_timer_on_stack(&timer); |
| 1327 | } |
| 1328 | } |
| 1329 | if (!irq_test_in_progress) |
| 1330 | engine->irq_put(engine); |
| 1331 | |
| 1332 | finish_wait(&engine->irq_queue, &wait); |
| 1333 | |
| 1334 | out: |
| 1335 | trace_i915_gem_request_wait_end(req); |
| 1336 | |
| 1337 | if (timeout) { |
| 1338 | s64 tres = *timeout - (ktime_get_raw_ns() - before); |
| 1339 | |
| 1340 | *timeout = tres < 0 ? 0 : tres; |
| 1341 | |
| 1342 | /* |
| 1343 | * Apparently ktime isn't accurate enough and occasionally has a |
| 1344 | * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch |
| 1345 | * things up to make the test happy. We allow up to 1 jiffy. |
| 1346 | * |
| 1347 | * This is a regrssion from the timespec->ktime conversion. |
| 1348 | */ |
| 1349 | if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000) |
| 1350 | *timeout = 0; |
| 1351 | } |
| 1352 | |
| 1353 | return ret; |
| 1354 | } |
| 1355 | |
| 1356 | int i915_gem_request_add_to_client(struct drm_i915_gem_request *req, |
| 1357 | struct drm_file *file) |
| 1358 | { |
| 1359 | struct drm_i915_file_private *file_priv; |
| 1360 | |
| 1361 | WARN_ON(!req || !file || req->file_priv); |
| 1362 | |
| 1363 | if (!req || !file) |
| 1364 | return -EINVAL; |
| 1365 | |
| 1366 | if (req->file_priv) |
| 1367 | return -EINVAL; |
| 1368 | |
| 1369 | file_priv = file->driver_priv; |
| 1370 | |
| 1371 | spin_lock(&file_priv->mm.lock); |
| 1372 | req->file_priv = file_priv; |
| 1373 | list_add_tail(&req->client_list, &file_priv->mm.request_list); |
| 1374 | spin_unlock(&file_priv->mm.lock); |
| 1375 | |
| 1376 | req->pid = get_pid(task_pid(current)); |
| 1377 | |
| 1378 | return 0; |
| 1379 | } |
| 1380 | |
| 1381 | static inline void |
| 1382 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) |
| 1383 | { |
| 1384 | struct drm_i915_file_private *file_priv = request->file_priv; |
| 1385 | |
| 1386 | if (!file_priv) |
| 1387 | return; |
| 1388 | |
| 1389 | spin_lock(&file_priv->mm.lock); |
| 1390 | list_del(&request->client_list); |
| 1391 | request->file_priv = NULL; |
| 1392 | spin_unlock(&file_priv->mm.lock); |
| 1393 | |
| 1394 | put_pid(request->pid); |
| 1395 | request->pid = NULL; |
| 1396 | } |
| 1397 | |
| 1398 | static void i915_gem_request_retire(struct drm_i915_gem_request *request) |
| 1399 | { |
| 1400 | trace_i915_gem_request_retire(request); |
| 1401 | |
| 1402 | /* We know the GPU must have read the request to have |
| 1403 | * sent us the seqno + interrupt, so use the position |
| 1404 | * of tail of the request to update the last known position |
| 1405 | * of the GPU head. |
| 1406 | * |
| 1407 | * Note this requires that we are always called in request |
| 1408 | * completion order. |
| 1409 | */ |
| 1410 | request->ringbuf->last_retired_head = request->postfix; |
| 1411 | |
| 1412 | list_del_init(&request->list); |
| 1413 | i915_gem_request_remove_from_client(request); |
| 1414 | |
| 1415 | if (request->previous_context) { |
| 1416 | if (i915.enable_execlists) |
| 1417 | intel_lr_context_unpin(request->previous_context, |
| 1418 | request->engine); |
| 1419 | } |
| 1420 | |
| 1421 | i915_gem_context_unreference(request->ctx); |
| 1422 | i915_gem_request_unreference(request); |
| 1423 | } |
| 1424 | |
| 1425 | static void |
| 1426 | __i915_gem_request_retire__upto(struct drm_i915_gem_request *req) |
| 1427 | { |
| 1428 | struct intel_engine_cs *engine = req->engine; |
| 1429 | struct drm_i915_gem_request *tmp; |
| 1430 | |
| 1431 | lockdep_assert_held(&engine->i915->dev->struct_mutex); |
| 1432 | |
| 1433 | if (list_empty(&req->list)) |
| 1434 | return; |
| 1435 | |
| 1436 | do { |
| 1437 | tmp = list_first_entry(&engine->request_list, |
| 1438 | typeof(*tmp), list); |
| 1439 | |
| 1440 | i915_gem_request_retire(tmp); |
| 1441 | } while (tmp != req); |
| 1442 | |
| 1443 | WARN_ON(i915_verify_lists(engine->dev)); |
| 1444 | } |
| 1445 | |
| 1446 | /** |
| 1447 | * Waits for a request to be signaled, and cleans up the |
| 1448 | * request and object lists appropriately for that event. |
| 1449 | */ |
| 1450 | int |
| 1451 | i915_wait_request(struct drm_i915_gem_request *req) |
| 1452 | { |
| 1453 | struct drm_i915_private *dev_priv = req->i915; |
| 1454 | bool interruptible; |
| 1455 | int ret; |
| 1456 | |
| 1457 | interruptible = dev_priv->mm.interruptible; |
| 1458 | |
| 1459 | BUG_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); |
| 1460 | |
| 1461 | ret = __i915_wait_request(req, interruptible, NULL, NULL); |
| 1462 | if (ret) |
| 1463 | return ret; |
| 1464 | |
| 1465 | __i915_gem_request_retire__upto(req); |
| 1466 | return 0; |
| 1467 | } |
| 1468 | |
| 1469 | /** |
| 1470 | * Ensures that all rendering to the object has completed and the object is |
| 1471 | * safe to unbind from the GTT or access from the CPU. |
| 1472 | */ |
| 1473 | int |
| 1474 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
| 1475 | bool readonly) |
| 1476 | { |
| 1477 | int ret, i; |
| 1478 | |
| 1479 | if (!obj->active) |
| 1480 | return 0; |
| 1481 | |
| 1482 | if (readonly) { |
| 1483 | if (obj->last_write_req != NULL) { |
| 1484 | ret = i915_wait_request(obj->last_write_req); |
| 1485 | if (ret) |
| 1486 | return ret; |
| 1487 | |
| 1488 | i = obj->last_write_req->engine->id; |
| 1489 | if (obj->last_read_req[i] == obj->last_write_req) |
| 1490 | i915_gem_object_retire__read(obj, i); |
| 1491 | else |
| 1492 | i915_gem_object_retire__write(obj); |
| 1493 | } |
| 1494 | } else { |
| 1495 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
| 1496 | if (obj->last_read_req[i] == NULL) |
| 1497 | continue; |
| 1498 | |
| 1499 | ret = i915_wait_request(obj->last_read_req[i]); |
| 1500 | if (ret) |
| 1501 | return ret; |
| 1502 | |
| 1503 | i915_gem_object_retire__read(obj, i); |
| 1504 | } |
| 1505 | GEM_BUG_ON(obj->active); |
| 1506 | } |
| 1507 | |
| 1508 | return 0; |
| 1509 | } |
| 1510 | |
| 1511 | static void |
| 1512 | i915_gem_object_retire_request(struct drm_i915_gem_object *obj, |
| 1513 | struct drm_i915_gem_request *req) |
| 1514 | { |
| 1515 | int ring = req->engine->id; |
| 1516 | |
| 1517 | if (obj->last_read_req[ring] == req) |
| 1518 | i915_gem_object_retire__read(obj, ring); |
| 1519 | else if (obj->last_write_req == req) |
| 1520 | i915_gem_object_retire__write(obj); |
| 1521 | |
| 1522 | __i915_gem_request_retire__upto(req); |
| 1523 | } |
| 1524 | |
| 1525 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
| 1526 | * as the object state may change during this call. |
| 1527 | */ |
| 1528 | static __must_check int |
| 1529 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, |
| 1530 | struct intel_rps_client *rps, |
| 1531 | bool readonly) |
| 1532 | { |
| 1533 | struct drm_device *dev = obj->base.dev; |
| 1534 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1535 | struct drm_i915_gem_request *requests[I915_NUM_ENGINES]; |
| 1536 | int ret, i, n = 0; |
| 1537 | |
| 1538 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 1539 | BUG_ON(!dev_priv->mm.interruptible); |
| 1540 | |
| 1541 | if (!obj->active) |
| 1542 | return 0; |
| 1543 | |
| 1544 | if (readonly) { |
| 1545 | struct drm_i915_gem_request *req; |
| 1546 | |
| 1547 | req = obj->last_write_req; |
| 1548 | if (req == NULL) |
| 1549 | return 0; |
| 1550 | |
| 1551 | requests[n++] = i915_gem_request_reference(req); |
| 1552 | } else { |
| 1553 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
| 1554 | struct drm_i915_gem_request *req; |
| 1555 | |
| 1556 | req = obj->last_read_req[i]; |
| 1557 | if (req == NULL) |
| 1558 | continue; |
| 1559 | |
| 1560 | requests[n++] = i915_gem_request_reference(req); |
| 1561 | } |
| 1562 | } |
| 1563 | |
| 1564 | mutex_unlock(&dev->struct_mutex); |
| 1565 | ret = 0; |
| 1566 | for (i = 0; ret == 0 && i < n; i++) |
| 1567 | ret = __i915_wait_request(requests[i], true, NULL, rps); |
| 1568 | mutex_lock(&dev->struct_mutex); |
| 1569 | |
| 1570 | for (i = 0; i < n; i++) { |
| 1571 | if (ret == 0) |
| 1572 | i915_gem_object_retire_request(obj, requests[i]); |
| 1573 | i915_gem_request_unreference(requests[i]); |
| 1574 | } |
| 1575 | |
| 1576 | return ret; |
| 1577 | } |
| 1578 | |
| 1579 | static struct intel_rps_client *to_rps_client(struct drm_file *file) |
| 1580 | { |
| 1581 | struct drm_i915_file_private *fpriv = file->driver_priv; |
| 1582 | return &fpriv->rps; |
| 1583 | } |
| 1584 | |
| 1585 | /** |
| 1586 | * Called when user space prepares to use an object with the CPU, either |
| 1587 | * through the mmap ioctl's mapping or a GTT mapping. |
| 1588 | */ |
| 1589 | int |
| 1590 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
| 1591 | struct drm_file *file) |
| 1592 | { |
| 1593 | struct drm_i915_gem_set_domain *args = data; |
| 1594 | struct drm_i915_gem_object *obj; |
| 1595 | uint32_t read_domains = args->read_domains; |
| 1596 | uint32_t write_domain = args->write_domain; |
| 1597 | int ret; |
| 1598 | |
| 1599 | /* Only handle setting domains to types used by the CPU. */ |
| 1600 | if (write_domain & I915_GEM_GPU_DOMAINS) |
| 1601 | return -EINVAL; |
| 1602 | |
| 1603 | if (read_domains & I915_GEM_GPU_DOMAINS) |
| 1604 | return -EINVAL; |
| 1605 | |
| 1606 | /* Having something in the write domain implies it's in the read |
| 1607 | * domain, and only that read domain. Enforce that in the request. |
| 1608 | */ |
| 1609 | if (write_domain != 0 && read_domains != write_domain) |
| 1610 | return -EINVAL; |
| 1611 | |
| 1612 | ret = i915_mutex_lock_interruptible(dev); |
| 1613 | if (ret) |
| 1614 | return ret; |
| 1615 | |
| 1616 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
| 1617 | if (&obj->base == NULL) { |
| 1618 | ret = -ENOENT; |
| 1619 | goto unlock; |
| 1620 | } |
| 1621 | |
| 1622 | /* Try to flush the object off the GPU without holding the lock. |
| 1623 | * We will repeat the flush holding the lock in the normal manner |
| 1624 | * to catch cases where we are gazumped. |
| 1625 | */ |
| 1626 | ret = i915_gem_object_wait_rendering__nonblocking(obj, |
| 1627 | to_rps_client(file), |
| 1628 | !write_domain); |
| 1629 | if (ret) |
| 1630 | goto unref; |
| 1631 | |
| 1632 | if (read_domains & I915_GEM_DOMAIN_GTT) |
| 1633 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
| 1634 | else |
| 1635 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
| 1636 | |
| 1637 | if (write_domain != 0) |
| 1638 | intel_fb_obj_invalidate(obj, |
| 1639 | write_domain == I915_GEM_DOMAIN_GTT ? |
| 1640 | ORIGIN_GTT : ORIGIN_CPU); |
| 1641 | |
| 1642 | unref: |
| 1643 | drm_gem_object_unreference(&obj->base); |
| 1644 | unlock: |
| 1645 | mutex_unlock(&dev->struct_mutex); |
| 1646 | return ret; |
| 1647 | } |
| 1648 | |
| 1649 | /** |
| 1650 | * Called when user space has done writes to this buffer |
| 1651 | */ |
| 1652 | int |
| 1653 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
| 1654 | struct drm_file *file) |
| 1655 | { |
| 1656 | struct drm_i915_gem_sw_finish *args = data; |
| 1657 | struct drm_i915_gem_object *obj; |
| 1658 | int ret = 0; |
| 1659 | |
| 1660 | ret = i915_mutex_lock_interruptible(dev); |
| 1661 | if (ret) |
| 1662 | return ret; |
| 1663 | |
| 1664 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
| 1665 | if (&obj->base == NULL) { |
| 1666 | ret = -ENOENT; |
| 1667 | goto unlock; |
| 1668 | } |
| 1669 | |
| 1670 | /* Pinned buffers may be scanout, so flush the cache */ |
| 1671 | if (obj->pin_display) |
| 1672 | i915_gem_object_flush_cpu_write_domain(obj); |
| 1673 | |
| 1674 | drm_gem_object_unreference(&obj->base); |
| 1675 | unlock: |
| 1676 | mutex_unlock(&dev->struct_mutex); |
| 1677 | return ret; |
| 1678 | } |
| 1679 | |
| 1680 | /** |
| 1681 | * Maps the contents of an object, returning the address it is mapped |
| 1682 | * into. |
| 1683 | * |
| 1684 | * While the mapping holds a reference on the contents of the object, it doesn't |
| 1685 | * imply a ref on the object itself. |
| 1686 | * |
| 1687 | * IMPORTANT: |
| 1688 | * |
| 1689 | * DRM driver writers who look a this function as an example for how to do GEM |
| 1690 | * mmap support, please don't implement mmap support like here. The modern way |
| 1691 | * to implement DRM mmap support is with an mmap offset ioctl (like |
| 1692 | * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly. |
| 1693 | * That way debug tooling like valgrind will understand what's going on, hiding |
| 1694 | * the mmap call in a driver private ioctl will break that. The i915 driver only |
| 1695 | * does cpu mmaps this way because we didn't know better. |
| 1696 | */ |
| 1697 | int |
| 1698 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
| 1699 | struct drm_file *file) |
| 1700 | { |
| 1701 | struct drm_i915_gem_mmap *args = data; |
| 1702 | struct drm_gem_object *obj; |
| 1703 | unsigned long addr; |
| 1704 | |
| 1705 | if (args->flags & ~(I915_MMAP_WC)) |
| 1706 | return -EINVAL; |
| 1707 | |
| 1708 | if (args->flags & I915_MMAP_WC && !cpu_has_pat) |
| 1709 | return -ENODEV; |
| 1710 | |
| 1711 | obj = drm_gem_object_lookup(dev, file, args->handle); |
| 1712 | if (obj == NULL) |
| 1713 | return -ENOENT; |
| 1714 | |
| 1715 | /* prime objects have no backing filp to GEM mmap |
| 1716 | * pages from. |
| 1717 | */ |
| 1718 | if (!obj->filp) { |
| 1719 | drm_gem_object_unreference_unlocked(obj); |
| 1720 | return -EINVAL; |
| 1721 | } |
| 1722 | |
| 1723 | addr = vm_mmap(obj->filp, 0, args->size, |
| 1724 | PROT_READ | PROT_WRITE, MAP_SHARED, |
| 1725 | args->offset); |
| 1726 | if (args->flags & I915_MMAP_WC) { |
| 1727 | struct mm_struct *mm = current->mm; |
| 1728 | struct vm_area_struct *vma; |
| 1729 | |
| 1730 | down_write(&mm->mmap_sem); |
| 1731 | vma = find_vma(mm, addr); |
| 1732 | if (vma) |
| 1733 | vma->vm_page_prot = |
| 1734 | pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); |
| 1735 | else |
| 1736 | addr = -ENOMEM; |
| 1737 | up_write(&mm->mmap_sem); |
| 1738 | } |
| 1739 | drm_gem_object_unreference_unlocked(obj); |
| 1740 | if (IS_ERR((void *)addr)) |
| 1741 | return addr; |
| 1742 | |
| 1743 | args->addr_ptr = (uint64_t) addr; |
| 1744 | |
| 1745 | return 0; |
| 1746 | } |
| 1747 | |
| 1748 | /** |
| 1749 | * i915_gem_fault - fault a page into the GTT |
| 1750 | * @vma: VMA in question |
| 1751 | * @vmf: fault info |
| 1752 | * |
| 1753 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped |
| 1754 | * from userspace. The fault handler takes care of binding the object to |
| 1755 | * the GTT (if needed), allocating and programming a fence register (again, |
| 1756 | * only if needed based on whether the old reg is still valid or the object |
| 1757 | * is tiled) and inserting a new PTE into the faulting process. |
| 1758 | * |
| 1759 | * Note that the faulting process may involve evicting existing objects |
| 1760 | * from the GTT and/or fence registers to make room. So performance may |
| 1761 | * suffer if the GTT working set is large or there are few fence registers |
| 1762 | * left. |
| 1763 | */ |
| 1764 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) |
| 1765 | { |
| 1766 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
| 1767 | struct drm_device *dev = obj->base.dev; |
| 1768 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 1769 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
| 1770 | struct i915_ggtt_view view = i915_ggtt_view_normal; |
| 1771 | pgoff_t page_offset; |
| 1772 | unsigned long pfn; |
| 1773 | int ret = 0; |
| 1774 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
| 1775 | |
| 1776 | intel_runtime_pm_get(dev_priv); |
| 1777 | |
| 1778 | /* We don't use vmf->pgoff since that has the fake offset */ |
| 1779 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> |
| 1780 | PAGE_SHIFT; |
| 1781 | |
| 1782 | ret = i915_mutex_lock_interruptible(dev); |
| 1783 | if (ret) |
| 1784 | goto out; |
| 1785 | |
| 1786 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
| 1787 | |
| 1788 | /* Try to flush the object off the GPU first without holding the lock. |
| 1789 | * Upon reacquiring the lock, we will perform our sanity checks and then |
| 1790 | * repeat the flush holding the lock in the normal manner to catch cases |
| 1791 | * where we are gazumped. |
| 1792 | */ |
| 1793 | ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write); |
| 1794 | if (ret) |
| 1795 | goto unlock; |
| 1796 | |
| 1797 | /* Access to snoopable pages through the GTT is incoherent. */ |
| 1798 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { |
| 1799 | ret = -EFAULT; |
| 1800 | goto unlock; |
| 1801 | } |
| 1802 | |
| 1803 | /* Use a partial view if the object is bigger than the aperture. */ |
| 1804 | if (obj->base.size >= ggtt->mappable_end && |
| 1805 | obj->tiling_mode == I915_TILING_NONE) { |
| 1806 | static const unsigned int chunk_size = 256; // 1 MiB |
| 1807 | |
| 1808 | memset(&view, 0, sizeof(view)); |
| 1809 | view.type = I915_GGTT_VIEW_PARTIAL; |
| 1810 | view.params.partial.offset = rounddown(page_offset, chunk_size); |
| 1811 | view.params.partial.size = |
| 1812 | min_t(unsigned int, |
| 1813 | chunk_size, |
| 1814 | (vma->vm_end - vma->vm_start)/PAGE_SIZE - |
| 1815 | view.params.partial.offset); |
| 1816 | } |
| 1817 | |
| 1818 | /* Now pin it into the GTT if needed */ |
| 1819 | ret = i915_gem_object_ggtt_pin(obj, &view, 0, PIN_MAPPABLE); |
| 1820 | if (ret) |
| 1821 | goto unlock; |
| 1822 | |
| 1823 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
| 1824 | if (ret) |
| 1825 | goto unpin; |
| 1826 | |
| 1827 | ret = i915_gem_object_get_fence(obj); |
| 1828 | if (ret) |
| 1829 | goto unpin; |
| 1830 | |
| 1831 | /* Finally, remap it using the new GTT offset */ |
| 1832 | pfn = ggtt->mappable_base + |
| 1833 | i915_gem_obj_ggtt_offset_view(obj, &view); |
| 1834 | pfn >>= PAGE_SHIFT; |
| 1835 | |
| 1836 | if (unlikely(view.type == I915_GGTT_VIEW_PARTIAL)) { |
| 1837 | /* Overriding existing pages in partial view does not cause |
| 1838 | * us any trouble as TLBs are still valid because the fault |
| 1839 | * is due to userspace losing part of the mapping or never |
| 1840 | * having accessed it before (at this partials' range). |
| 1841 | */ |
| 1842 | unsigned long base = vma->vm_start + |
| 1843 | (view.params.partial.offset << PAGE_SHIFT); |
| 1844 | unsigned int i; |
| 1845 | |
| 1846 | for (i = 0; i < view.params.partial.size; i++) { |
| 1847 | ret = vm_insert_pfn(vma, base + i * PAGE_SIZE, pfn + i); |
| 1848 | if (ret) |
| 1849 | break; |
| 1850 | } |
| 1851 | |
| 1852 | obj->fault_mappable = true; |
| 1853 | } else { |
| 1854 | if (!obj->fault_mappable) { |
| 1855 | unsigned long size = min_t(unsigned long, |
| 1856 | vma->vm_end - vma->vm_start, |
| 1857 | obj->base.size); |
| 1858 | int i; |
| 1859 | |
| 1860 | for (i = 0; i < size >> PAGE_SHIFT; i++) { |
| 1861 | ret = vm_insert_pfn(vma, |
| 1862 | (unsigned long)vma->vm_start + i * PAGE_SIZE, |
| 1863 | pfn + i); |
| 1864 | if (ret) |
| 1865 | break; |
| 1866 | } |
| 1867 | |
| 1868 | obj->fault_mappable = true; |
| 1869 | } else |
| 1870 | ret = vm_insert_pfn(vma, |
| 1871 | (unsigned long)vmf->virtual_address, |
| 1872 | pfn + page_offset); |
| 1873 | } |
| 1874 | unpin: |
| 1875 | i915_gem_object_ggtt_unpin_view(obj, &view); |
| 1876 | unlock: |
| 1877 | mutex_unlock(&dev->struct_mutex); |
| 1878 | out: |
| 1879 | switch (ret) { |
| 1880 | case -EIO: |
| 1881 | /* |
| 1882 | * We eat errors when the gpu is terminally wedged to avoid |
| 1883 | * userspace unduly crashing (gl has no provisions for mmaps to |
| 1884 | * fail). But any other -EIO isn't ours (e.g. swap in failure) |
| 1885 | * and so needs to be reported. |
| 1886 | */ |
| 1887 | if (!i915_terminally_wedged(&dev_priv->gpu_error)) { |
| 1888 | ret = VM_FAULT_SIGBUS; |
| 1889 | break; |
| 1890 | } |
| 1891 | case -EAGAIN: |
| 1892 | /* |
| 1893 | * EAGAIN means the gpu is hung and we'll wait for the error |
| 1894 | * handler to reset everything when re-faulting in |
| 1895 | * i915_mutex_lock_interruptible. |
| 1896 | */ |
| 1897 | case 0: |
| 1898 | case -ERESTARTSYS: |
| 1899 | case -EINTR: |
| 1900 | case -EBUSY: |
| 1901 | /* |
| 1902 | * EBUSY is ok: this just means that another thread |
| 1903 | * already did the job. |
| 1904 | */ |
| 1905 | ret = VM_FAULT_NOPAGE; |
| 1906 | break; |
| 1907 | case -ENOMEM: |
| 1908 | ret = VM_FAULT_OOM; |
| 1909 | break; |
| 1910 | case -ENOSPC: |
| 1911 | case -EFAULT: |
| 1912 | ret = VM_FAULT_SIGBUS; |
| 1913 | break; |
| 1914 | default: |
| 1915 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
| 1916 | ret = VM_FAULT_SIGBUS; |
| 1917 | break; |
| 1918 | } |
| 1919 | |
| 1920 | intel_runtime_pm_put(dev_priv); |
| 1921 | return ret; |
| 1922 | } |
| 1923 | |
| 1924 | /** |
| 1925 | * i915_gem_release_mmap - remove physical page mappings |
| 1926 | * @obj: obj in question |
| 1927 | * |
| 1928 | * Preserve the reservation of the mmapping with the DRM core code, but |
| 1929 | * relinquish ownership of the pages back to the system. |
| 1930 | * |
| 1931 | * It is vital that we remove the page mapping if we have mapped a tiled |
| 1932 | * object through the GTT and then lose the fence register due to |
| 1933 | * resource pressure. Similarly if the object has been moved out of the |
| 1934 | * aperture, than pages mapped into userspace must be revoked. Removing the |
| 1935 | * mapping will then trigger a page fault on the next user access, allowing |
| 1936 | * fixup by i915_gem_fault(). |
| 1937 | */ |
| 1938 | void |
| 1939 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
| 1940 | { |
| 1941 | /* Serialisation between user GTT access and our code depends upon |
| 1942 | * revoking the CPU's PTE whilst the mutex is held. The next user |
| 1943 | * pagefault then has to wait until we release the mutex. |
| 1944 | */ |
| 1945 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
| 1946 | |
| 1947 | if (!obj->fault_mappable) |
| 1948 | return; |
| 1949 | |
| 1950 | drm_vma_node_unmap(&obj->base.vma_node, |
| 1951 | obj->base.dev->anon_inode->i_mapping); |
| 1952 | |
| 1953 | /* Ensure that the CPU's PTE are revoked and there are not outstanding |
| 1954 | * memory transactions from userspace before we return. The TLB |
| 1955 | * flushing implied above by changing the PTE above *should* be |
| 1956 | * sufficient, an extra barrier here just provides us with a bit |
| 1957 | * of paranoid documentation about our requirement to serialise |
| 1958 | * memory writes before touching registers / GSM. |
| 1959 | */ |
| 1960 | wmb(); |
| 1961 | |
| 1962 | obj->fault_mappable = false; |
| 1963 | } |
| 1964 | |
| 1965 | void |
| 1966 | i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) |
| 1967 | { |
| 1968 | struct drm_i915_gem_object *obj; |
| 1969 | |
| 1970 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
| 1971 | i915_gem_release_mmap(obj); |
| 1972 | } |
| 1973 | |
| 1974 | uint32_t |
| 1975 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
| 1976 | { |
| 1977 | uint32_t gtt_size; |
| 1978 | |
| 1979 | if (INTEL_INFO(dev)->gen >= 4 || |
| 1980 | tiling_mode == I915_TILING_NONE) |
| 1981 | return size; |
| 1982 | |
| 1983 | /* Previous chips need a power-of-two fence region when tiling */ |
| 1984 | if (INTEL_INFO(dev)->gen == 3) |
| 1985 | gtt_size = 1024*1024; |
| 1986 | else |
| 1987 | gtt_size = 512*1024; |
| 1988 | |
| 1989 | while (gtt_size < size) |
| 1990 | gtt_size <<= 1; |
| 1991 | |
| 1992 | return gtt_size; |
| 1993 | } |
| 1994 | |
| 1995 | /** |
| 1996 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object |
| 1997 | * @obj: object to check |
| 1998 | * |
| 1999 | * Return the required GTT alignment for an object, taking into account |
| 2000 | * potential fence register mapping. |
| 2001 | */ |
| 2002 | uint32_t |
| 2003 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
| 2004 | int tiling_mode, bool fenced) |
| 2005 | { |
| 2006 | /* |
| 2007 | * Minimum alignment is 4k (GTT page size), but might be greater |
| 2008 | * if a fence register is needed for the object. |
| 2009 | */ |
| 2010 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
| 2011 | tiling_mode == I915_TILING_NONE) |
| 2012 | return 4096; |
| 2013 | |
| 2014 | /* |
| 2015 | * Previous chips need to be aligned to the size of the smallest |
| 2016 | * fence register that can contain the object. |
| 2017 | */ |
| 2018 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
| 2019 | } |
| 2020 | |
| 2021 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
| 2022 | { |
| 2023 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 2024 | int ret; |
| 2025 | |
| 2026 | if (drm_vma_node_has_offset(&obj->base.vma_node)) |
| 2027 | return 0; |
| 2028 | |
| 2029 | dev_priv->mm.shrinker_no_lock_stealing = true; |
| 2030 | |
| 2031 | ret = drm_gem_create_mmap_offset(&obj->base); |
| 2032 | if (ret != -ENOSPC) |
| 2033 | goto out; |
| 2034 | |
| 2035 | /* Badly fragmented mmap space? The only way we can recover |
| 2036 | * space is by destroying unwanted objects. We can't randomly release |
| 2037 | * mmap_offsets as userspace expects them to be persistent for the |
| 2038 | * lifetime of the objects. The closest we can is to release the |
| 2039 | * offsets on purgeable objects by truncating it and marking it purged, |
| 2040 | * which prevents userspace from ever using that object again. |
| 2041 | */ |
| 2042 | i915_gem_shrink(dev_priv, |
| 2043 | obj->base.size >> PAGE_SHIFT, |
| 2044 | I915_SHRINK_BOUND | |
| 2045 | I915_SHRINK_UNBOUND | |
| 2046 | I915_SHRINK_PURGEABLE); |
| 2047 | ret = drm_gem_create_mmap_offset(&obj->base); |
| 2048 | if (ret != -ENOSPC) |
| 2049 | goto out; |
| 2050 | |
| 2051 | i915_gem_shrink_all(dev_priv); |
| 2052 | ret = drm_gem_create_mmap_offset(&obj->base); |
| 2053 | out: |
| 2054 | dev_priv->mm.shrinker_no_lock_stealing = false; |
| 2055 | |
| 2056 | return ret; |
| 2057 | } |
| 2058 | |
| 2059 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) |
| 2060 | { |
| 2061 | drm_gem_free_mmap_offset(&obj->base); |
| 2062 | } |
| 2063 | |
| 2064 | int |
| 2065 | i915_gem_mmap_gtt(struct drm_file *file, |
| 2066 | struct drm_device *dev, |
| 2067 | uint32_t handle, |
| 2068 | uint64_t *offset) |
| 2069 | { |
| 2070 | struct drm_i915_gem_object *obj; |
| 2071 | int ret; |
| 2072 | |
| 2073 | ret = i915_mutex_lock_interruptible(dev); |
| 2074 | if (ret) |
| 2075 | return ret; |
| 2076 | |
| 2077 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
| 2078 | if (&obj->base == NULL) { |
| 2079 | ret = -ENOENT; |
| 2080 | goto unlock; |
| 2081 | } |
| 2082 | |
| 2083 | if (obj->madv != I915_MADV_WILLNEED) { |
| 2084 | DRM_DEBUG("Attempting to mmap a purgeable buffer\n"); |
| 2085 | ret = -EFAULT; |
| 2086 | goto out; |
| 2087 | } |
| 2088 | |
| 2089 | ret = i915_gem_object_create_mmap_offset(obj); |
| 2090 | if (ret) |
| 2091 | goto out; |
| 2092 | |
| 2093 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); |
| 2094 | |
| 2095 | out: |
| 2096 | drm_gem_object_unreference(&obj->base); |
| 2097 | unlock: |
| 2098 | mutex_unlock(&dev->struct_mutex); |
| 2099 | return ret; |
| 2100 | } |
| 2101 | |
| 2102 | /** |
| 2103 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing |
| 2104 | * @dev: DRM device |
| 2105 | * @data: GTT mapping ioctl data |
| 2106 | * @file: GEM object info |
| 2107 | * |
| 2108 | * Simply returns the fake offset to userspace so it can mmap it. |
| 2109 | * The mmap call will end up in drm_gem_mmap(), which will set things |
| 2110 | * up so we can get faults in the handler above. |
| 2111 | * |
| 2112 | * The fault handler will take care of binding the object into the GTT |
| 2113 | * (since it may have been evicted to make room for something), allocating |
| 2114 | * a fence register, and mapping the appropriate aperture address into |
| 2115 | * userspace. |
| 2116 | */ |
| 2117 | int |
| 2118 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
| 2119 | struct drm_file *file) |
| 2120 | { |
| 2121 | struct drm_i915_gem_mmap_gtt *args = data; |
| 2122 | |
| 2123 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
| 2124 | } |
| 2125 | |
| 2126 | /* Immediately discard the backing storage */ |
| 2127 | static void |
| 2128 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
| 2129 | { |
| 2130 | i915_gem_object_free_mmap_offset(obj); |
| 2131 | |
| 2132 | if (obj->base.filp == NULL) |
| 2133 | return; |
| 2134 | |
| 2135 | /* Our goal here is to return as much of the memory as |
| 2136 | * is possible back to the system as we are called from OOM. |
| 2137 | * To do this we must instruct the shmfs to drop all of its |
| 2138 | * backing pages, *now*. |
| 2139 | */ |
| 2140 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
| 2141 | obj->madv = __I915_MADV_PURGED; |
| 2142 | } |
| 2143 | |
| 2144 | /* Try to discard unwanted pages */ |
| 2145 | static void |
| 2146 | i915_gem_object_invalidate(struct drm_i915_gem_object *obj) |
| 2147 | { |
| 2148 | struct address_space *mapping; |
| 2149 | |
| 2150 | switch (obj->madv) { |
| 2151 | case I915_MADV_DONTNEED: |
| 2152 | i915_gem_object_truncate(obj); |
| 2153 | case __I915_MADV_PURGED: |
| 2154 | return; |
| 2155 | } |
| 2156 | |
| 2157 | if (obj->base.filp == NULL) |
| 2158 | return; |
| 2159 | |
| 2160 | mapping = file_inode(obj->base.filp)->i_mapping, |
| 2161 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); |
| 2162 | } |
| 2163 | |
| 2164 | static void |
| 2165 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
| 2166 | { |
| 2167 | struct sg_page_iter sg_iter; |
| 2168 | int ret; |
| 2169 | |
| 2170 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
| 2171 | |
| 2172 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
| 2173 | if (WARN_ON(ret)) { |
| 2174 | /* In the event of a disaster, abandon all caches and |
| 2175 | * hope for the best. |
| 2176 | */ |
| 2177 | i915_gem_clflush_object(obj, true); |
| 2178 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 2179 | } |
| 2180 | |
| 2181 | i915_gem_gtt_finish_object(obj); |
| 2182 | |
| 2183 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
| 2184 | i915_gem_object_save_bit_17_swizzle(obj); |
| 2185 | |
| 2186 | if (obj->madv == I915_MADV_DONTNEED) |
| 2187 | obj->dirty = 0; |
| 2188 | |
| 2189 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
| 2190 | struct page *page = sg_page_iter_page(&sg_iter); |
| 2191 | |
| 2192 | if (obj->dirty) |
| 2193 | set_page_dirty(page); |
| 2194 | |
| 2195 | if (obj->madv == I915_MADV_WILLNEED) |
| 2196 | mark_page_accessed(page); |
| 2197 | |
| 2198 | put_page(page); |
| 2199 | } |
| 2200 | obj->dirty = 0; |
| 2201 | |
| 2202 | sg_free_table(obj->pages); |
| 2203 | kfree(obj->pages); |
| 2204 | } |
| 2205 | |
| 2206 | int |
| 2207 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
| 2208 | { |
| 2209 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
| 2210 | |
| 2211 | if (obj->pages == NULL) |
| 2212 | return 0; |
| 2213 | |
| 2214 | if (obj->pages_pin_count) |
| 2215 | return -EBUSY; |
| 2216 | |
| 2217 | BUG_ON(i915_gem_obj_bound_any(obj)); |
| 2218 | |
| 2219 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
| 2220 | * array, hence protect them from being reaped by removing them from gtt |
| 2221 | * lists early. */ |
| 2222 | list_del(&obj->global_list); |
| 2223 | |
| 2224 | if (obj->mapping) { |
| 2225 | if (is_vmalloc_addr(obj->mapping)) |
| 2226 | vunmap(obj->mapping); |
| 2227 | else |
| 2228 | kunmap(kmap_to_page(obj->mapping)); |
| 2229 | obj->mapping = NULL; |
| 2230 | } |
| 2231 | |
| 2232 | ops->put_pages(obj); |
| 2233 | obj->pages = NULL; |
| 2234 | |
| 2235 | i915_gem_object_invalidate(obj); |
| 2236 | |
| 2237 | return 0; |
| 2238 | } |
| 2239 | |
| 2240 | static int |
| 2241 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
| 2242 | { |
| 2243 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 2244 | int page_count, i; |
| 2245 | struct address_space *mapping; |
| 2246 | struct sg_table *st; |
| 2247 | struct scatterlist *sg; |
| 2248 | struct sg_page_iter sg_iter; |
| 2249 | struct page *page; |
| 2250 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
| 2251 | int ret; |
| 2252 | gfp_t gfp; |
| 2253 | |
| 2254 | /* Assert that the object is not currently in any GPU domain. As it |
| 2255 | * wasn't in the GTT, there shouldn't be any way it could have been in |
| 2256 | * a GPU cache |
| 2257 | */ |
| 2258 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
| 2259 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); |
| 2260 | |
| 2261 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
| 2262 | if (st == NULL) |
| 2263 | return -ENOMEM; |
| 2264 | |
| 2265 | page_count = obj->base.size / PAGE_SIZE; |
| 2266 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
| 2267 | kfree(st); |
| 2268 | return -ENOMEM; |
| 2269 | } |
| 2270 | |
| 2271 | /* Get the list of pages out of our struct file. They'll be pinned |
| 2272 | * at this point until we release them. |
| 2273 | * |
| 2274 | * Fail silently without starting the shrinker |
| 2275 | */ |
| 2276 | mapping = file_inode(obj->base.filp)->i_mapping; |
| 2277 | gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM)); |
| 2278 | gfp |= __GFP_NORETRY | __GFP_NOWARN; |
| 2279 | sg = st->sgl; |
| 2280 | st->nents = 0; |
| 2281 | for (i = 0; i < page_count; i++) { |
| 2282 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
| 2283 | if (IS_ERR(page)) { |
| 2284 | i915_gem_shrink(dev_priv, |
| 2285 | page_count, |
| 2286 | I915_SHRINK_BOUND | |
| 2287 | I915_SHRINK_UNBOUND | |
| 2288 | I915_SHRINK_PURGEABLE); |
| 2289 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
| 2290 | } |
| 2291 | if (IS_ERR(page)) { |
| 2292 | /* We've tried hard to allocate the memory by reaping |
| 2293 | * our own buffer, now let the real VM do its job and |
| 2294 | * go down in flames if truly OOM. |
| 2295 | */ |
| 2296 | i915_gem_shrink_all(dev_priv); |
| 2297 | page = shmem_read_mapping_page(mapping, i); |
| 2298 | if (IS_ERR(page)) { |
| 2299 | ret = PTR_ERR(page); |
| 2300 | goto err_pages; |
| 2301 | } |
| 2302 | } |
| 2303 | #ifdef CONFIG_SWIOTLB |
| 2304 | if (swiotlb_nr_tbl()) { |
| 2305 | st->nents++; |
| 2306 | sg_set_page(sg, page, PAGE_SIZE, 0); |
| 2307 | sg = sg_next(sg); |
| 2308 | continue; |
| 2309 | } |
| 2310 | #endif |
| 2311 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
| 2312 | if (i) |
| 2313 | sg = sg_next(sg); |
| 2314 | st->nents++; |
| 2315 | sg_set_page(sg, page, PAGE_SIZE, 0); |
| 2316 | } else { |
| 2317 | sg->length += PAGE_SIZE; |
| 2318 | } |
| 2319 | last_pfn = page_to_pfn(page); |
| 2320 | |
| 2321 | /* Check that the i965g/gm workaround works. */ |
| 2322 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); |
| 2323 | } |
| 2324 | #ifdef CONFIG_SWIOTLB |
| 2325 | if (!swiotlb_nr_tbl()) |
| 2326 | #endif |
| 2327 | sg_mark_end(sg); |
| 2328 | obj->pages = st; |
| 2329 | |
| 2330 | ret = i915_gem_gtt_prepare_object(obj); |
| 2331 | if (ret) |
| 2332 | goto err_pages; |
| 2333 | |
| 2334 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
| 2335 | i915_gem_object_do_bit_17_swizzle(obj); |
| 2336 | |
| 2337 | if (obj->tiling_mode != I915_TILING_NONE && |
| 2338 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) |
| 2339 | i915_gem_object_pin_pages(obj); |
| 2340 | |
| 2341 | return 0; |
| 2342 | |
| 2343 | err_pages: |
| 2344 | sg_mark_end(sg); |
| 2345 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) |
| 2346 | put_page(sg_page_iter_page(&sg_iter)); |
| 2347 | sg_free_table(st); |
| 2348 | kfree(st); |
| 2349 | |
| 2350 | /* shmemfs first checks if there is enough memory to allocate the page |
| 2351 | * and reports ENOSPC should there be insufficient, along with the usual |
| 2352 | * ENOMEM for a genuine allocation failure. |
| 2353 | * |
| 2354 | * We use ENOSPC in our driver to mean that we have run out of aperture |
| 2355 | * space and so want to translate the error from shmemfs back to our |
| 2356 | * usual understanding of ENOMEM. |
| 2357 | */ |
| 2358 | if (ret == -ENOSPC) |
| 2359 | ret = -ENOMEM; |
| 2360 | |
| 2361 | return ret; |
| 2362 | } |
| 2363 | |
| 2364 | /* Ensure that the associated pages are gathered from the backing storage |
| 2365 | * and pinned into our object. i915_gem_object_get_pages() may be called |
| 2366 | * multiple times before they are released by a single call to |
| 2367 | * i915_gem_object_put_pages() - once the pages are no longer referenced |
| 2368 | * either as a result of memory pressure (reaping pages under the shrinker) |
| 2369 | * or as the object is itself released. |
| 2370 | */ |
| 2371 | int |
| 2372 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) |
| 2373 | { |
| 2374 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 2375 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
| 2376 | int ret; |
| 2377 | |
| 2378 | if (obj->pages) |
| 2379 | return 0; |
| 2380 | |
| 2381 | if (obj->madv != I915_MADV_WILLNEED) { |
| 2382 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); |
| 2383 | return -EFAULT; |
| 2384 | } |
| 2385 | |
| 2386 | BUG_ON(obj->pages_pin_count); |
| 2387 | |
| 2388 | ret = ops->get_pages(obj); |
| 2389 | if (ret) |
| 2390 | return ret; |
| 2391 | |
| 2392 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
| 2393 | |
| 2394 | obj->get_page.sg = obj->pages->sgl; |
| 2395 | obj->get_page.last = 0; |
| 2396 | |
| 2397 | return 0; |
| 2398 | } |
| 2399 | |
| 2400 | void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj) |
| 2401 | { |
| 2402 | int ret; |
| 2403 | |
| 2404 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
| 2405 | |
| 2406 | ret = i915_gem_object_get_pages(obj); |
| 2407 | if (ret) |
| 2408 | return ERR_PTR(ret); |
| 2409 | |
| 2410 | i915_gem_object_pin_pages(obj); |
| 2411 | |
| 2412 | if (obj->mapping == NULL) { |
| 2413 | struct page **pages; |
| 2414 | |
| 2415 | pages = NULL; |
| 2416 | if (obj->base.size == PAGE_SIZE) |
| 2417 | obj->mapping = kmap(sg_page(obj->pages->sgl)); |
| 2418 | else |
| 2419 | pages = drm_malloc_gfp(obj->base.size >> PAGE_SHIFT, |
| 2420 | sizeof(*pages), |
| 2421 | GFP_TEMPORARY); |
| 2422 | if (pages != NULL) { |
| 2423 | struct sg_page_iter sg_iter; |
| 2424 | int n; |
| 2425 | |
| 2426 | n = 0; |
| 2427 | for_each_sg_page(obj->pages->sgl, &sg_iter, |
| 2428 | obj->pages->nents, 0) |
| 2429 | pages[n++] = sg_page_iter_page(&sg_iter); |
| 2430 | |
| 2431 | obj->mapping = vmap(pages, n, 0, PAGE_KERNEL); |
| 2432 | drm_free_large(pages); |
| 2433 | } |
| 2434 | if (obj->mapping == NULL) { |
| 2435 | i915_gem_object_unpin_pages(obj); |
| 2436 | return ERR_PTR(-ENOMEM); |
| 2437 | } |
| 2438 | } |
| 2439 | |
| 2440 | return obj->mapping; |
| 2441 | } |
| 2442 | |
| 2443 | void i915_vma_move_to_active(struct i915_vma *vma, |
| 2444 | struct drm_i915_gem_request *req) |
| 2445 | { |
| 2446 | struct drm_i915_gem_object *obj = vma->obj; |
| 2447 | struct intel_engine_cs *engine; |
| 2448 | |
| 2449 | engine = i915_gem_request_get_engine(req); |
| 2450 | |
| 2451 | /* Add a reference if we're newly entering the active list. */ |
| 2452 | if (obj->active == 0) |
| 2453 | drm_gem_object_reference(&obj->base); |
| 2454 | obj->active |= intel_engine_flag(engine); |
| 2455 | |
| 2456 | list_move_tail(&obj->engine_list[engine->id], &engine->active_list); |
| 2457 | i915_gem_request_assign(&obj->last_read_req[engine->id], req); |
| 2458 | |
| 2459 | list_move_tail(&vma->vm_link, &vma->vm->active_list); |
| 2460 | } |
| 2461 | |
| 2462 | static void |
| 2463 | i915_gem_object_retire__write(struct drm_i915_gem_object *obj) |
| 2464 | { |
| 2465 | GEM_BUG_ON(obj->last_write_req == NULL); |
| 2466 | GEM_BUG_ON(!(obj->active & intel_engine_flag(obj->last_write_req->engine))); |
| 2467 | |
| 2468 | i915_gem_request_assign(&obj->last_write_req, NULL); |
| 2469 | intel_fb_obj_flush(obj, true, ORIGIN_CS); |
| 2470 | } |
| 2471 | |
| 2472 | static void |
| 2473 | i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring) |
| 2474 | { |
| 2475 | struct i915_vma *vma; |
| 2476 | |
| 2477 | GEM_BUG_ON(obj->last_read_req[ring] == NULL); |
| 2478 | GEM_BUG_ON(!(obj->active & (1 << ring))); |
| 2479 | |
| 2480 | list_del_init(&obj->engine_list[ring]); |
| 2481 | i915_gem_request_assign(&obj->last_read_req[ring], NULL); |
| 2482 | |
| 2483 | if (obj->last_write_req && obj->last_write_req->engine->id == ring) |
| 2484 | i915_gem_object_retire__write(obj); |
| 2485 | |
| 2486 | obj->active &= ~(1 << ring); |
| 2487 | if (obj->active) |
| 2488 | return; |
| 2489 | |
| 2490 | /* Bump our place on the bound list to keep it roughly in LRU order |
| 2491 | * so that we don't steal from recently used but inactive objects |
| 2492 | * (unless we are forced to ofc!) |
| 2493 | */ |
| 2494 | list_move_tail(&obj->global_list, |
| 2495 | &to_i915(obj->base.dev)->mm.bound_list); |
| 2496 | |
| 2497 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
| 2498 | if (!list_empty(&vma->vm_link)) |
| 2499 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); |
| 2500 | } |
| 2501 | |
| 2502 | i915_gem_request_assign(&obj->last_fenced_req, NULL); |
| 2503 | drm_gem_object_unreference(&obj->base); |
| 2504 | } |
| 2505 | |
| 2506 | static int |
| 2507 | i915_gem_init_seqno(struct drm_i915_private *dev_priv, u32 seqno) |
| 2508 | { |
| 2509 | struct intel_engine_cs *engine; |
| 2510 | int ret; |
| 2511 | |
| 2512 | /* Carefully retire all requests without writing to the rings */ |
| 2513 | for_each_engine(engine, dev_priv) { |
| 2514 | ret = intel_engine_idle(engine); |
| 2515 | if (ret) |
| 2516 | return ret; |
| 2517 | } |
| 2518 | i915_gem_retire_requests(dev_priv); |
| 2519 | |
| 2520 | /* Finally reset hw state */ |
| 2521 | for_each_engine(engine, dev_priv) |
| 2522 | intel_ring_init_seqno(engine, seqno); |
| 2523 | |
| 2524 | return 0; |
| 2525 | } |
| 2526 | |
| 2527 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
| 2528 | { |
| 2529 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2530 | int ret; |
| 2531 | |
| 2532 | if (seqno == 0) |
| 2533 | return -EINVAL; |
| 2534 | |
| 2535 | /* HWS page needs to be set less than what we |
| 2536 | * will inject to ring |
| 2537 | */ |
| 2538 | ret = i915_gem_init_seqno(dev_priv, seqno - 1); |
| 2539 | if (ret) |
| 2540 | return ret; |
| 2541 | |
| 2542 | /* Carefully set the last_seqno value so that wrap |
| 2543 | * detection still works |
| 2544 | */ |
| 2545 | dev_priv->next_seqno = seqno; |
| 2546 | dev_priv->last_seqno = seqno - 1; |
| 2547 | if (dev_priv->last_seqno == 0) |
| 2548 | dev_priv->last_seqno--; |
| 2549 | |
| 2550 | return 0; |
| 2551 | } |
| 2552 | |
| 2553 | int |
| 2554 | i915_gem_get_seqno(struct drm_i915_private *dev_priv, u32 *seqno) |
| 2555 | { |
| 2556 | /* reserve 0 for non-seqno */ |
| 2557 | if (dev_priv->next_seqno == 0) { |
| 2558 | int ret = i915_gem_init_seqno(dev_priv, 0); |
| 2559 | if (ret) |
| 2560 | return ret; |
| 2561 | |
| 2562 | dev_priv->next_seqno = 1; |
| 2563 | } |
| 2564 | |
| 2565 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
| 2566 | return 0; |
| 2567 | } |
| 2568 | |
| 2569 | /* |
| 2570 | * NB: This function is not allowed to fail. Doing so would mean the the |
| 2571 | * request is not being tracked for completion but the work itself is |
| 2572 | * going to happen on the hardware. This would be a Bad Thing(tm). |
| 2573 | */ |
| 2574 | void __i915_add_request(struct drm_i915_gem_request *request, |
| 2575 | struct drm_i915_gem_object *obj, |
| 2576 | bool flush_caches) |
| 2577 | { |
| 2578 | struct intel_engine_cs *engine; |
| 2579 | struct drm_i915_private *dev_priv; |
| 2580 | struct intel_ringbuffer *ringbuf; |
| 2581 | u32 request_start; |
| 2582 | u32 reserved_tail; |
| 2583 | int ret; |
| 2584 | |
| 2585 | if (WARN_ON(request == NULL)) |
| 2586 | return; |
| 2587 | |
| 2588 | engine = request->engine; |
| 2589 | dev_priv = request->i915; |
| 2590 | ringbuf = request->ringbuf; |
| 2591 | |
| 2592 | /* |
| 2593 | * To ensure that this call will not fail, space for its emissions |
| 2594 | * should already have been reserved in the ring buffer. Let the ring |
| 2595 | * know that it is time to use that space up. |
| 2596 | */ |
| 2597 | request_start = intel_ring_get_tail(ringbuf); |
| 2598 | reserved_tail = request->reserved_space; |
| 2599 | request->reserved_space = 0; |
| 2600 | |
| 2601 | /* |
| 2602 | * Emit any outstanding flushes - execbuf can fail to emit the flush |
| 2603 | * after having emitted the batchbuffer command. Hence we need to fix |
| 2604 | * things up similar to emitting the lazy request. The difference here |
| 2605 | * is that the flush _must_ happen before the next request, no matter |
| 2606 | * what. |
| 2607 | */ |
| 2608 | if (flush_caches) { |
| 2609 | if (i915.enable_execlists) |
| 2610 | ret = logical_ring_flush_all_caches(request); |
| 2611 | else |
| 2612 | ret = intel_ring_flush_all_caches(request); |
| 2613 | /* Not allowed to fail! */ |
| 2614 | WARN(ret, "*_ring_flush_all_caches failed: %d!\n", ret); |
| 2615 | } |
| 2616 | |
| 2617 | trace_i915_gem_request_add(request); |
| 2618 | |
| 2619 | request->head = request_start; |
| 2620 | |
| 2621 | /* Whilst this request exists, batch_obj will be on the |
| 2622 | * active_list, and so will hold the active reference. Only when this |
| 2623 | * request is retired will the the batch_obj be moved onto the |
| 2624 | * inactive_list and lose its active reference. Hence we do not need |
| 2625 | * to explicitly hold another reference here. |
| 2626 | */ |
| 2627 | request->batch_obj = obj; |
| 2628 | |
| 2629 | /* Seal the request and mark it as pending execution. Note that |
| 2630 | * we may inspect this state, without holding any locks, during |
| 2631 | * hangcheck. Hence we apply the barrier to ensure that we do not |
| 2632 | * see a more recent value in the hws than we are tracking. |
| 2633 | */ |
| 2634 | request->emitted_jiffies = jiffies; |
| 2635 | request->previous_seqno = engine->last_submitted_seqno; |
| 2636 | smp_store_mb(engine->last_submitted_seqno, request->seqno); |
| 2637 | list_add_tail(&request->list, &engine->request_list); |
| 2638 | |
| 2639 | /* Record the position of the start of the request so that |
| 2640 | * should we detect the updated seqno part-way through the |
| 2641 | * GPU processing the request, we never over-estimate the |
| 2642 | * position of the head. |
| 2643 | */ |
| 2644 | request->postfix = intel_ring_get_tail(ringbuf); |
| 2645 | |
| 2646 | if (i915.enable_execlists) |
| 2647 | ret = engine->emit_request(request); |
| 2648 | else { |
| 2649 | ret = engine->add_request(request); |
| 2650 | |
| 2651 | request->tail = intel_ring_get_tail(ringbuf); |
| 2652 | } |
| 2653 | /* Not allowed to fail! */ |
| 2654 | WARN(ret, "emit|add_request failed: %d!\n", ret); |
| 2655 | |
| 2656 | i915_queue_hangcheck(engine->i915); |
| 2657 | |
| 2658 | queue_delayed_work(dev_priv->wq, |
| 2659 | &dev_priv->mm.retire_work, |
| 2660 | round_jiffies_up_relative(HZ)); |
| 2661 | intel_mark_busy(dev_priv); |
| 2662 | |
| 2663 | /* Sanity check that the reserved size was large enough. */ |
| 2664 | ret = intel_ring_get_tail(ringbuf) - request_start; |
| 2665 | if (ret < 0) |
| 2666 | ret += ringbuf->size; |
| 2667 | WARN_ONCE(ret > reserved_tail, |
| 2668 | "Not enough space reserved (%d bytes) " |
| 2669 | "for adding the request (%d bytes)\n", |
| 2670 | reserved_tail, ret); |
| 2671 | } |
| 2672 | |
| 2673 | static bool i915_context_is_banned(struct drm_i915_private *dev_priv, |
| 2674 | const struct intel_context *ctx) |
| 2675 | { |
| 2676 | unsigned long elapsed; |
| 2677 | |
| 2678 | elapsed = get_seconds() - ctx->hang_stats.guilty_ts; |
| 2679 | |
| 2680 | if (ctx->hang_stats.banned) |
| 2681 | return true; |
| 2682 | |
| 2683 | if (ctx->hang_stats.ban_period_seconds && |
| 2684 | elapsed <= ctx->hang_stats.ban_period_seconds) { |
| 2685 | if (!i915_gem_context_is_default(ctx)) { |
| 2686 | DRM_DEBUG("context hanging too fast, banning!\n"); |
| 2687 | return true; |
| 2688 | } else if (i915_stop_ring_allow_ban(dev_priv)) { |
| 2689 | if (i915_stop_ring_allow_warn(dev_priv)) |
| 2690 | DRM_ERROR("gpu hanging too fast, banning!\n"); |
| 2691 | return true; |
| 2692 | } |
| 2693 | } |
| 2694 | |
| 2695 | return false; |
| 2696 | } |
| 2697 | |
| 2698 | static void i915_set_reset_status(struct drm_i915_private *dev_priv, |
| 2699 | struct intel_context *ctx, |
| 2700 | const bool guilty) |
| 2701 | { |
| 2702 | struct i915_ctx_hang_stats *hs; |
| 2703 | |
| 2704 | if (WARN_ON(!ctx)) |
| 2705 | return; |
| 2706 | |
| 2707 | hs = &ctx->hang_stats; |
| 2708 | |
| 2709 | if (guilty) { |
| 2710 | hs->banned = i915_context_is_banned(dev_priv, ctx); |
| 2711 | hs->batch_active++; |
| 2712 | hs->guilty_ts = get_seconds(); |
| 2713 | } else { |
| 2714 | hs->batch_pending++; |
| 2715 | } |
| 2716 | } |
| 2717 | |
| 2718 | void i915_gem_request_free(struct kref *req_ref) |
| 2719 | { |
| 2720 | struct drm_i915_gem_request *req = container_of(req_ref, |
| 2721 | typeof(*req), ref); |
| 2722 | kmem_cache_free(req->i915->requests, req); |
| 2723 | } |
| 2724 | |
| 2725 | static inline int |
| 2726 | __i915_gem_request_alloc(struct intel_engine_cs *engine, |
| 2727 | struct intel_context *ctx, |
| 2728 | struct drm_i915_gem_request **req_out) |
| 2729 | { |
| 2730 | struct drm_i915_private *dev_priv = engine->i915; |
| 2731 | unsigned reset_counter = i915_reset_counter(&dev_priv->gpu_error); |
| 2732 | struct drm_i915_gem_request *req; |
| 2733 | int ret; |
| 2734 | |
| 2735 | if (!req_out) |
| 2736 | return -EINVAL; |
| 2737 | |
| 2738 | *req_out = NULL; |
| 2739 | |
| 2740 | /* ABI: Before userspace accesses the GPU (e.g. execbuffer), report |
| 2741 | * EIO if the GPU is already wedged, or EAGAIN to drop the struct_mutex |
| 2742 | * and restart. |
| 2743 | */ |
| 2744 | ret = i915_gem_check_wedge(reset_counter, dev_priv->mm.interruptible); |
| 2745 | if (ret) |
| 2746 | return ret; |
| 2747 | |
| 2748 | req = kmem_cache_zalloc(dev_priv->requests, GFP_KERNEL); |
| 2749 | if (req == NULL) |
| 2750 | return -ENOMEM; |
| 2751 | |
| 2752 | ret = i915_gem_get_seqno(engine->i915, &req->seqno); |
| 2753 | if (ret) |
| 2754 | goto err; |
| 2755 | |
| 2756 | kref_init(&req->ref); |
| 2757 | req->i915 = dev_priv; |
| 2758 | req->engine = engine; |
| 2759 | req->reset_counter = reset_counter; |
| 2760 | req->ctx = ctx; |
| 2761 | i915_gem_context_reference(req->ctx); |
| 2762 | |
| 2763 | /* |
| 2764 | * Reserve space in the ring buffer for all the commands required to |
| 2765 | * eventually emit this request. This is to guarantee that the |
| 2766 | * i915_add_request() call can't fail. Note that the reserve may need |
| 2767 | * to be redone if the request is not actually submitted straight |
| 2768 | * away, e.g. because a GPU scheduler has deferred it. |
| 2769 | */ |
| 2770 | req->reserved_space = MIN_SPACE_FOR_ADD_REQUEST; |
| 2771 | |
| 2772 | if (i915.enable_execlists) |
| 2773 | ret = intel_logical_ring_alloc_request_extras(req); |
| 2774 | else |
| 2775 | ret = intel_ring_alloc_request_extras(req); |
| 2776 | if (ret) |
| 2777 | goto err_ctx; |
| 2778 | |
| 2779 | *req_out = req; |
| 2780 | return 0; |
| 2781 | |
| 2782 | err_ctx: |
| 2783 | i915_gem_context_unreference(ctx); |
| 2784 | err: |
| 2785 | kmem_cache_free(dev_priv->requests, req); |
| 2786 | return ret; |
| 2787 | } |
| 2788 | |
| 2789 | /** |
| 2790 | * i915_gem_request_alloc - allocate a request structure |
| 2791 | * |
| 2792 | * @engine: engine that we wish to issue the request on. |
| 2793 | * @ctx: context that the request will be associated with. |
| 2794 | * This can be NULL if the request is not directly related to |
| 2795 | * any specific user context, in which case this function will |
| 2796 | * choose an appropriate context to use. |
| 2797 | * |
| 2798 | * Returns a pointer to the allocated request if successful, |
| 2799 | * or an error code if not. |
| 2800 | */ |
| 2801 | struct drm_i915_gem_request * |
| 2802 | i915_gem_request_alloc(struct intel_engine_cs *engine, |
| 2803 | struct intel_context *ctx) |
| 2804 | { |
| 2805 | struct drm_i915_gem_request *req; |
| 2806 | int err; |
| 2807 | |
| 2808 | if (ctx == NULL) |
| 2809 | ctx = engine->i915->kernel_context; |
| 2810 | err = __i915_gem_request_alloc(engine, ctx, &req); |
| 2811 | return err ? ERR_PTR(err) : req; |
| 2812 | } |
| 2813 | |
| 2814 | struct drm_i915_gem_request * |
| 2815 | i915_gem_find_active_request(struct intel_engine_cs *engine) |
| 2816 | { |
| 2817 | struct drm_i915_gem_request *request; |
| 2818 | |
| 2819 | list_for_each_entry(request, &engine->request_list, list) { |
| 2820 | if (i915_gem_request_completed(request, false)) |
| 2821 | continue; |
| 2822 | |
| 2823 | return request; |
| 2824 | } |
| 2825 | |
| 2826 | return NULL; |
| 2827 | } |
| 2828 | |
| 2829 | static void i915_gem_reset_engine_status(struct drm_i915_private *dev_priv, |
| 2830 | struct intel_engine_cs *engine) |
| 2831 | { |
| 2832 | struct drm_i915_gem_request *request; |
| 2833 | bool ring_hung; |
| 2834 | |
| 2835 | request = i915_gem_find_active_request(engine); |
| 2836 | |
| 2837 | if (request == NULL) |
| 2838 | return; |
| 2839 | |
| 2840 | ring_hung = engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; |
| 2841 | |
| 2842 | i915_set_reset_status(dev_priv, request->ctx, ring_hung); |
| 2843 | |
| 2844 | list_for_each_entry_continue(request, &engine->request_list, list) |
| 2845 | i915_set_reset_status(dev_priv, request->ctx, false); |
| 2846 | } |
| 2847 | |
| 2848 | static void i915_gem_reset_engine_cleanup(struct drm_i915_private *dev_priv, |
| 2849 | struct intel_engine_cs *engine) |
| 2850 | { |
| 2851 | struct intel_ringbuffer *buffer; |
| 2852 | |
| 2853 | while (!list_empty(&engine->active_list)) { |
| 2854 | struct drm_i915_gem_object *obj; |
| 2855 | |
| 2856 | obj = list_first_entry(&engine->active_list, |
| 2857 | struct drm_i915_gem_object, |
| 2858 | engine_list[engine->id]); |
| 2859 | |
| 2860 | i915_gem_object_retire__read(obj, engine->id); |
| 2861 | } |
| 2862 | |
| 2863 | /* |
| 2864 | * Clear the execlists queue up before freeing the requests, as those |
| 2865 | * are the ones that keep the context and ringbuffer backing objects |
| 2866 | * pinned in place. |
| 2867 | */ |
| 2868 | |
| 2869 | if (i915.enable_execlists) { |
| 2870 | /* Ensure irq handler finishes or is cancelled. */ |
| 2871 | tasklet_kill(&engine->irq_tasklet); |
| 2872 | |
| 2873 | intel_execlists_cancel_requests(engine); |
| 2874 | } |
| 2875 | |
| 2876 | /* |
| 2877 | * We must free the requests after all the corresponding objects have |
| 2878 | * been moved off active lists. Which is the same order as the normal |
| 2879 | * retire_requests function does. This is important if object hold |
| 2880 | * implicit references on things like e.g. ppgtt address spaces through |
| 2881 | * the request. |
| 2882 | */ |
| 2883 | while (!list_empty(&engine->request_list)) { |
| 2884 | struct drm_i915_gem_request *request; |
| 2885 | |
| 2886 | request = list_first_entry(&engine->request_list, |
| 2887 | struct drm_i915_gem_request, |
| 2888 | list); |
| 2889 | |
| 2890 | i915_gem_request_retire(request); |
| 2891 | } |
| 2892 | |
| 2893 | /* Having flushed all requests from all queues, we know that all |
| 2894 | * ringbuffers must now be empty. However, since we do not reclaim |
| 2895 | * all space when retiring the request (to prevent HEADs colliding |
| 2896 | * with rapid ringbuffer wraparound) the amount of available space |
| 2897 | * upon reset is less than when we start. Do one more pass over |
| 2898 | * all the ringbuffers to reset last_retired_head. |
| 2899 | */ |
| 2900 | list_for_each_entry(buffer, &engine->buffers, link) { |
| 2901 | buffer->last_retired_head = buffer->tail; |
| 2902 | intel_ring_update_space(buffer); |
| 2903 | } |
| 2904 | |
| 2905 | intel_ring_init_seqno(engine, engine->last_submitted_seqno); |
| 2906 | } |
| 2907 | |
| 2908 | void i915_gem_reset(struct drm_device *dev) |
| 2909 | { |
| 2910 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2911 | struct intel_engine_cs *engine; |
| 2912 | |
| 2913 | /* |
| 2914 | * Before we free the objects from the requests, we need to inspect |
| 2915 | * them for finding the guilty party. As the requests only borrow |
| 2916 | * their reference to the objects, the inspection must be done first. |
| 2917 | */ |
| 2918 | for_each_engine(engine, dev_priv) |
| 2919 | i915_gem_reset_engine_status(dev_priv, engine); |
| 2920 | |
| 2921 | for_each_engine(engine, dev_priv) |
| 2922 | i915_gem_reset_engine_cleanup(dev_priv, engine); |
| 2923 | |
| 2924 | i915_gem_context_reset(dev); |
| 2925 | |
| 2926 | i915_gem_restore_fences(dev); |
| 2927 | |
| 2928 | WARN_ON(i915_verify_lists(dev)); |
| 2929 | } |
| 2930 | |
| 2931 | /** |
| 2932 | * This function clears the request list as sequence numbers are passed. |
| 2933 | */ |
| 2934 | void |
| 2935 | i915_gem_retire_requests_ring(struct intel_engine_cs *engine) |
| 2936 | { |
| 2937 | WARN_ON(i915_verify_lists(engine->dev)); |
| 2938 | |
| 2939 | /* Retire requests first as we use it above for the early return. |
| 2940 | * If we retire requests last, we may use a later seqno and so clear |
| 2941 | * the requests lists without clearing the active list, leading to |
| 2942 | * confusion. |
| 2943 | */ |
| 2944 | while (!list_empty(&engine->request_list)) { |
| 2945 | struct drm_i915_gem_request *request; |
| 2946 | |
| 2947 | request = list_first_entry(&engine->request_list, |
| 2948 | struct drm_i915_gem_request, |
| 2949 | list); |
| 2950 | |
| 2951 | if (!i915_gem_request_completed(request, true)) |
| 2952 | break; |
| 2953 | |
| 2954 | i915_gem_request_retire(request); |
| 2955 | } |
| 2956 | |
| 2957 | /* Move any buffers on the active list that are no longer referenced |
| 2958 | * by the ringbuffer to the flushing/inactive lists as appropriate, |
| 2959 | * before we free the context associated with the requests. |
| 2960 | */ |
| 2961 | while (!list_empty(&engine->active_list)) { |
| 2962 | struct drm_i915_gem_object *obj; |
| 2963 | |
| 2964 | obj = list_first_entry(&engine->active_list, |
| 2965 | struct drm_i915_gem_object, |
| 2966 | engine_list[engine->id]); |
| 2967 | |
| 2968 | if (!list_empty(&obj->last_read_req[engine->id]->list)) |
| 2969 | break; |
| 2970 | |
| 2971 | i915_gem_object_retire__read(obj, engine->id); |
| 2972 | } |
| 2973 | |
| 2974 | if (unlikely(engine->trace_irq_req && |
| 2975 | i915_gem_request_completed(engine->trace_irq_req, true))) { |
| 2976 | engine->irq_put(engine); |
| 2977 | i915_gem_request_assign(&engine->trace_irq_req, NULL); |
| 2978 | } |
| 2979 | |
| 2980 | WARN_ON(i915_verify_lists(engine->dev)); |
| 2981 | } |
| 2982 | |
| 2983 | bool |
| 2984 | i915_gem_retire_requests(struct drm_i915_private *dev_priv) |
| 2985 | { |
| 2986 | struct intel_engine_cs *engine; |
| 2987 | bool idle = true; |
| 2988 | |
| 2989 | for_each_engine(engine, dev_priv) { |
| 2990 | i915_gem_retire_requests_ring(engine); |
| 2991 | idle &= list_empty(&engine->request_list); |
| 2992 | if (i915.enable_execlists) { |
| 2993 | spin_lock_bh(&engine->execlist_lock); |
| 2994 | idle &= list_empty(&engine->execlist_queue); |
| 2995 | spin_unlock_bh(&engine->execlist_lock); |
| 2996 | } |
| 2997 | } |
| 2998 | |
| 2999 | if (idle) |
| 3000 | mod_delayed_work(dev_priv->wq, |
| 3001 | &dev_priv->mm.idle_work, |
| 3002 | msecs_to_jiffies(100)); |
| 3003 | |
| 3004 | return idle; |
| 3005 | } |
| 3006 | |
| 3007 | static void |
| 3008 | i915_gem_retire_work_handler(struct work_struct *work) |
| 3009 | { |
| 3010 | struct drm_i915_private *dev_priv = |
| 3011 | container_of(work, typeof(*dev_priv), mm.retire_work.work); |
| 3012 | struct drm_device *dev = dev_priv->dev; |
| 3013 | bool idle; |
| 3014 | |
| 3015 | /* Come back later if the device is busy... */ |
| 3016 | idle = false; |
| 3017 | if (mutex_trylock(&dev->struct_mutex)) { |
| 3018 | idle = i915_gem_retire_requests(dev_priv); |
| 3019 | mutex_unlock(&dev->struct_mutex); |
| 3020 | } |
| 3021 | if (!idle) |
| 3022 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
| 3023 | round_jiffies_up_relative(HZ)); |
| 3024 | } |
| 3025 | |
| 3026 | static void |
| 3027 | i915_gem_idle_work_handler(struct work_struct *work) |
| 3028 | { |
| 3029 | struct drm_i915_private *dev_priv = |
| 3030 | container_of(work, typeof(*dev_priv), mm.idle_work.work); |
| 3031 | struct drm_device *dev = dev_priv->dev; |
| 3032 | struct intel_engine_cs *engine; |
| 3033 | |
| 3034 | for_each_engine(engine, dev_priv) |
| 3035 | if (!list_empty(&engine->request_list)) |
| 3036 | return; |
| 3037 | |
| 3038 | /* we probably should sync with hangcheck here, using cancel_work_sync. |
| 3039 | * Also locking seems to be fubar here, engine->request_list is protected |
| 3040 | * by dev->struct_mutex. */ |
| 3041 | |
| 3042 | intel_mark_idle(dev_priv); |
| 3043 | |
| 3044 | if (mutex_trylock(&dev->struct_mutex)) { |
| 3045 | for_each_engine(engine, dev_priv) |
| 3046 | i915_gem_batch_pool_fini(&engine->batch_pool); |
| 3047 | |
| 3048 | mutex_unlock(&dev->struct_mutex); |
| 3049 | } |
| 3050 | } |
| 3051 | |
| 3052 | /** |
| 3053 | * Ensures that an object will eventually get non-busy by flushing any required |
| 3054 | * write domains, emitting any outstanding lazy request and retiring and |
| 3055 | * completed requests. |
| 3056 | */ |
| 3057 | static int |
| 3058 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) |
| 3059 | { |
| 3060 | int i; |
| 3061 | |
| 3062 | if (!obj->active) |
| 3063 | return 0; |
| 3064 | |
| 3065 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
| 3066 | struct drm_i915_gem_request *req; |
| 3067 | |
| 3068 | req = obj->last_read_req[i]; |
| 3069 | if (req == NULL) |
| 3070 | continue; |
| 3071 | |
| 3072 | if (list_empty(&req->list)) |
| 3073 | goto retire; |
| 3074 | |
| 3075 | if (i915_gem_request_completed(req, true)) { |
| 3076 | __i915_gem_request_retire__upto(req); |
| 3077 | retire: |
| 3078 | i915_gem_object_retire__read(obj, i); |
| 3079 | } |
| 3080 | } |
| 3081 | |
| 3082 | return 0; |
| 3083 | } |
| 3084 | |
| 3085 | /** |
| 3086 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT |
| 3087 | * @DRM_IOCTL_ARGS: standard ioctl arguments |
| 3088 | * |
| 3089 | * Returns 0 if successful, else an error is returned with the remaining time in |
| 3090 | * the timeout parameter. |
| 3091 | * -ETIME: object is still busy after timeout |
| 3092 | * -ERESTARTSYS: signal interrupted the wait |
| 3093 | * -ENONENT: object doesn't exist |
| 3094 | * Also possible, but rare: |
| 3095 | * -EAGAIN: GPU wedged |
| 3096 | * -ENOMEM: damn |
| 3097 | * -ENODEV: Internal IRQ fail |
| 3098 | * -E?: The add request failed |
| 3099 | * |
| 3100 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any |
| 3101 | * non-zero timeout parameter the wait ioctl will wait for the given number of |
| 3102 | * nanoseconds on an object becoming unbusy. Since the wait itself does so |
| 3103 | * without holding struct_mutex the object may become re-busied before this |
| 3104 | * function completes. A similar but shorter * race condition exists in the busy |
| 3105 | * ioctl |
| 3106 | */ |
| 3107 | int |
| 3108 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) |
| 3109 | { |
| 3110 | struct drm_i915_gem_wait *args = data; |
| 3111 | struct drm_i915_gem_object *obj; |
| 3112 | struct drm_i915_gem_request *req[I915_NUM_ENGINES]; |
| 3113 | int i, n = 0; |
| 3114 | int ret; |
| 3115 | |
| 3116 | if (args->flags != 0) |
| 3117 | return -EINVAL; |
| 3118 | |
| 3119 | ret = i915_mutex_lock_interruptible(dev); |
| 3120 | if (ret) |
| 3121 | return ret; |
| 3122 | |
| 3123 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); |
| 3124 | if (&obj->base == NULL) { |
| 3125 | mutex_unlock(&dev->struct_mutex); |
| 3126 | return -ENOENT; |
| 3127 | } |
| 3128 | |
| 3129 | /* Need to make sure the object gets inactive eventually. */ |
| 3130 | ret = i915_gem_object_flush_active(obj); |
| 3131 | if (ret) |
| 3132 | goto out; |
| 3133 | |
| 3134 | if (!obj->active) |
| 3135 | goto out; |
| 3136 | |
| 3137 | /* Do this after OLR check to make sure we make forward progress polling |
| 3138 | * on this IOCTL with a timeout == 0 (like busy ioctl) |
| 3139 | */ |
| 3140 | if (args->timeout_ns == 0) { |
| 3141 | ret = -ETIME; |
| 3142 | goto out; |
| 3143 | } |
| 3144 | |
| 3145 | drm_gem_object_unreference(&obj->base); |
| 3146 | |
| 3147 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
| 3148 | if (obj->last_read_req[i] == NULL) |
| 3149 | continue; |
| 3150 | |
| 3151 | req[n++] = i915_gem_request_reference(obj->last_read_req[i]); |
| 3152 | } |
| 3153 | |
| 3154 | mutex_unlock(&dev->struct_mutex); |
| 3155 | |
| 3156 | for (i = 0; i < n; i++) { |
| 3157 | if (ret == 0) |
| 3158 | ret = __i915_wait_request(req[i], true, |
| 3159 | args->timeout_ns > 0 ? &args->timeout_ns : NULL, |
| 3160 | to_rps_client(file)); |
| 3161 | i915_gem_request_unreference(req[i]); |
| 3162 | } |
| 3163 | return ret; |
| 3164 | |
| 3165 | out: |
| 3166 | drm_gem_object_unreference(&obj->base); |
| 3167 | mutex_unlock(&dev->struct_mutex); |
| 3168 | return ret; |
| 3169 | } |
| 3170 | |
| 3171 | static int |
| 3172 | __i915_gem_object_sync(struct drm_i915_gem_object *obj, |
| 3173 | struct intel_engine_cs *to, |
| 3174 | struct drm_i915_gem_request *from_req, |
| 3175 | struct drm_i915_gem_request **to_req) |
| 3176 | { |
| 3177 | struct intel_engine_cs *from; |
| 3178 | int ret; |
| 3179 | |
| 3180 | from = i915_gem_request_get_engine(from_req); |
| 3181 | if (to == from) |
| 3182 | return 0; |
| 3183 | |
| 3184 | if (i915_gem_request_completed(from_req, true)) |
| 3185 | return 0; |
| 3186 | |
| 3187 | if (!i915_semaphore_is_enabled(to_i915(obj->base.dev))) { |
| 3188 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
| 3189 | ret = __i915_wait_request(from_req, |
| 3190 | i915->mm.interruptible, |
| 3191 | NULL, |
| 3192 | &i915->rps.semaphores); |
| 3193 | if (ret) |
| 3194 | return ret; |
| 3195 | |
| 3196 | i915_gem_object_retire_request(obj, from_req); |
| 3197 | } else { |
| 3198 | int idx = intel_ring_sync_index(from, to); |
| 3199 | u32 seqno = i915_gem_request_get_seqno(from_req); |
| 3200 | |
| 3201 | WARN_ON(!to_req); |
| 3202 | |
| 3203 | if (seqno <= from->semaphore.sync_seqno[idx]) |
| 3204 | return 0; |
| 3205 | |
| 3206 | if (*to_req == NULL) { |
| 3207 | struct drm_i915_gem_request *req; |
| 3208 | |
| 3209 | req = i915_gem_request_alloc(to, NULL); |
| 3210 | if (IS_ERR(req)) |
| 3211 | return PTR_ERR(req); |
| 3212 | |
| 3213 | *to_req = req; |
| 3214 | } |
| 3215 | |
| 3216 | trace_i915_gem_ring_sync_to(*to_req, from, from_req); |
| 3217 | ret = to->semaphore.sync_to(*to_req, from, seqno); |
| 3218 | if (ret) |
| 3219 | return ret; |
| 3220 | |
| 3221 | /* We use last_read_req because sync_to() |
| 3222 | * might have just caused seqno wrap under |
| 3223 | * the radar. |
| 3224 | */ |
| 3225 | from->semaphore.sync_seqno[idx] = |
| 3226 | i915_gem_request_get_seqno(obj->last_read_req[from->id]); |
| 3227 | } |
| 3228 | |
| 3229 | return 0; |
| 3230 | } |
| 3231 | |
| 3232 | /** |
| 3233 | * i915_gem_object_sync - sync an object to a ring. |
| 3234 | * |
| 3235 | * @obj: object which may be in use on another ring. |
| 3236 | * @to: ring we wish to use the object on. May be NULL. |
| 3237 | * @to_req: request we wish to use the object for. See below. |
| 3238 | * This will be allocated and returned if a request is |
| 3239 | * required but not passed in. |
| 3240 | * |
| 3241 | * This code is meant to abstract object synchronization with the GPU. |
| 3242 | * Calling with NULL implies synchronizing the object with the CPU |
| 3243 | * rather than a particular GPU ring. Conceptually we serialise writes |
| 3244 | * between engines inside the GPU. We only allow one engine to write |
| 3245 | * into a buffer at any time, but multiple readers. To ensure each has |
| 3246 | * a coherent view of memory, we must: |
| 3247 | * |
| 3248 | * - If there is an outstanding write request to the object, the new |
| 3249 | * request must wait for it to complete (either CPU or in hw, requests |
| 3250 | * on the same ring will be naturally ordered). |
| 3251 | * |
| 3252 | * - If we are a write request (pending_write_domain is set), the new |
| 3253 | * request must wait for outstanding read requests to complete. |
| 3254 | * |
| 3255 | * For CPU synchronisation (NULL to) no request is required. For syncing with |
| 3256 | * rings to_req must be non-NULL. However, a request does not have to be |
| 3257 | * pre-allocated. If *to_req is NULL and sync commands will be emitted then a |
| 3258 | * request will be allocated automatically and returned through *to_req. Note |
| 3259 | * that it is not guaranteed that commands will be emitted (because the system |
| 3260 | * might already be idle). Hence there is no need to create a request that |
| 3261 | * might never have any work submitted. Note further that if a request is |
| 3262 | * returned in *to_req, it is the responsibility of the caller to submit |
| 3263 | * that request (after potentially adding more work to it). |
| 3264 | * |
| 3265 | * Returns 0 if successful, else propagates up the lower layer error. |
| 3266 | */ |
| 3267 | int |
| 3268 | i915_gem_object_sync(struct drm_i915_gem_object *obj, |
| 3269 | struct intel_engine_cs *to, |
| 3270 | struct drm_i915_gem_request **to_req) |
| 3271 | { |
| 3272 | const bool readonly = obj->base.pending_write_domain == 0; |
| 3273 | struct drm_i915_gem_request *req[I915_NUM_ENGINES]; |
| 3274 | int ret, i, n; |
| 3275 | |
| 3276 | if (!obj->active) |
| 3277 | return 0; |
| 3278 | |
| 3279 | if (to == NULL) |
| 3280 | return i915_gem_object_wait_rendering(obj, readonly); |
| 3281 | |
| 3282 | n = 0; |
| 3283 | if (readonly) { |
| 3284 | if (obj->last_write_req) |
| 3285 | req[n++] = obj->last_write_req; |
| 3286 | } else { |
| 3287 | for (i = 0; i < I915_NUM_ENGINES; i++) |
| 3288 | if (obj->last_read_req[i]) |
| 3289 | req[n++] = obj->last_read_req[i]; |
| 3290 | } |
| 3291 | for (i = 0; i < n; i++) { |
| 3292 | ret = __i915_gem_object_sync(obj, to, req[i], to_req); |
| 3293 | if (ret) |
| 3294 | return ret; |
| 3295 | } |
| 3296 | |
| 3297 | return 0; |
| 3298 | } |
| 3299 | |
| 3300 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
| 3301 | { |
| 3302 | u32 old_write_domain, old_read_domains; |
| 3303 | |
| 3304 | /* Force a pagefault for domain tracking on next user access */ |
| 3305 | i915_gem_release_mmap(obj); |
| 3306 | |
| 3307 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
| 3308 | return; |
| 3309 | |
| 3310 | old_read_domains = obj->base.read_domains; |
| 3311 | old_write_domain = obj->base.write_domain; |
| 3312 | |
| 3313 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; |
| 3314 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; |
| 3315 | |
| 3316 | trace_i915_gem_object_change_domain(obj, |
| 3317 | old_read_domains, |
| 3318 | old_write_domain); |
| 3319 | } |
| 3320 | |
| 3321 | static void __i915_vma_iounmap(struct i915_vma *vma) |
| 3322 | { |
| 3323 | GEM_BUG_ON(vma->pin_count); |
| 3324 | |
| 3325 | if (vma->iomap == NULL) |
| 3326 | return; |
| 3327 | |
| 3328 | io_mapping_unmap(vma->iomap); |
| 3329 | vma->iomap = NULL; |
| 3330 | } |
| 3331 | |
| 3332 | static int __i915_vma_unbind(struct i915_vma *vma, bool wait) |
| 3333 | { |
| 3334 | struct drm_i915_gem_object *obj = vma->obj; |
| 3335 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 3336 | int ret; |
| 3337 | |
| 3338 | if (list_empty(&vma->obj_link)) |
| 3339 | return 0; |
| 3340 | |
| 3341 | if (!drm_mm_node_allocated(&vma->node)) { |
| 3342 | i915_gem_vma_destroy(vma); |
| 3343 | return 0; |
| 3344 | } |
| 3345 | |
| 3346 | if (vma->pin_count) |
| 3347 | return -EBUSY; |
| 3348 | |
| 3349 | BUG_ON(obj->pages == NULL); |
| 3350 | |
| 3351 | if (wait) { |
| 3352 | ret = i915_gem_object_wait_rendering(obj, false); |
| 3353 | if (ret) |
| 3354 | return ret; |
| 3355 | } |
| 3356 | |
| 3357 | if (vma->is_ggtt && vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { |
| 3358 | i915_gem_object_finish_gtt(obj); |
| 3359 | |
| 3360 | /* release the fence reg _after_ flushing */ |
| 3361 | ret = i915_gem_object_put_fence(obj); |
| 3362 | if (ret) |
| 3363 | return ret; |
| 3364 | |
| 3365 | __i915_vma_iounmap(vma); |
| 3366 | } |
| 3367 | |
| 3368 | trace_i915_vma_unbind(vma); |
| 3369 | |
| 3370 | vma->vm->unbind_vma(vma); |
| 3371 | vma->bound = 0; |
| 3372 | |
| 3373 | list_del_init(&vma->vm_link); |
| 3374 | if (vma->is_ggtt) { |
| 3375 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { |
| 3376 | obj->map_and_fenceable = false; |
| 3377 | } else if (vma->ggtt_view.pages) { |
| 3378 | sg_free_table(vma->ggtt_view.pages); |
| 3379 | kfree(vma->ggtt_view.pages); |
| 3380 | } |
| 3381 | vma->ggtt_view.pages = NULL; |
| 3382 | } |
| 3383 | |
| 3384 | drm_mm_remove_node(&vma->node); |
| 3385 | i915_gem_vma_destroy(vma); |
| 3386 | |
| 3387 | /* Since the unbound list is global, only move to that list if |
| 3388 | * no more VMAs exist. */ |
| 3389 | if (list_empty(&obj->vma_list)) |
| 3390 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
| 3391 | |
| 3392 | /* And finally now the object is completely decoupled from this vma, |
| 3393 | * we can drop its hold on the backing storage and allow it to be |
| 3394 | * reaped by the shrinker. |
| 3395 | */ |
| 3396 | i915_gem_object_unpin_pages(obj); |
| 3397 | |
| 3398 | return 0; |
| 3399 | } |
| 3400 | |
| 3401 | int i915_vma_unbind(struct i915_vma *vma) |
| 3402 | { |
| 3403 | return __i915_vma_unbind(vma, true); |
| 3404 | } |
| 3405 | |
| 3406 | int __i915_vma_unbind_no_wait(struct i915_vma *vma) |
| 3407 | { |
| 3408 | return __i915_vma_unbind(vma, false); |
| 3409 | } |
| 3410 | |
| 3411 | int i915_gpu_idle(struct drm_device *dev) |
| 3412 | { |
| 3413 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3414 | struct intel_engine_cs *engine; |
| 3415 | int ret; |
| 3416 | |
| 3417 | /* Flush everything onto the inactive list. */ |
| 3418 | for_each_engine(engine, dev_priv) { |
| 3419 | if (!i915.enable_execlists) { |
| 3420 | struct drm_i915_gem_request *req; |
| 3421 | |
| 3422 | req = i915_gem_request_alloc(engine, NULL); |
| 3423 | if (IS_ERR(req)) |
| 3424 | return PTR_ERR(req); |
| 3425 | |
| 3426 | ret = i915_switch_context(req); |
| 3427 | i915_add_request_no_flush(req); |
| 3428 | if (ret) |
| 3429 | return ret; |
| 3430 | } |
| 3431 | |
| 3432 | ret = intel_engine_idle(engine); |
| 3433 | if (ret) |
| 3434 | return ret; |
| 3435 | } |
| 3436 | |
| 3437 | WARN_ON(i915_verify_lists(dev)); |
| 3438 | return 0; |
| 3439 | } |
| 3440 | |
| 3441 | static bool i915_gem_valid_gtt_space(struct i915_vma *vma, |
| 3442 | unsigned long cache_level) |
| 3443 | { |
| 3444 | struct drm_mm_node *gtt_space = &vma->node; |
| 3445 | struct drm_mm_node *other; |
| 3446 | |
| 3447 | /* |
| 3448 | * On some machines we have to be careful when putting differing types |
| 3449 | * of snoopable memory together to avoid the prefetcher crossing memory |
| 3450 | * domains and dying. During vm initialisation, we decide whether or not |
| 3451 | * these constraints apply and set the drm_mm.color_adjust |
| 3452 | * appropriately. |
| 3453 | */ |
| 3454 | if (vma->vm->mm.color_adjust == NULL) |
| 3455 | return true; |
| 3456 | |
| 3457 | if (!drm_mm_node_allocated(gtt_space)) |
| 3458 | return true; |
| 3459 | |
| 3460 | if (list_empty(>t_space->node_list)) |
| 3461 | return true; |
| 3462 | |
| 3463 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); |
| 3464 | if (other->allocated && !other->hole_follows && other->color != cache_level) |
| 3465 | return false; |
| 3466 | |
| 3467 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); |
| 3468 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) |
| 3469 | return false; |
| 3470 | |
| 3471 | return true; |
| 3472 | } |
| 3473 | |
| 3474 | /** |
| 3475 | * Finds free space in the GTT aperture and binds the object or a view of it |
| 3476 | * there. |
| 3477 | */ |
| 3478 | static struct i915_vma * |
| 3479 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
| 3480 | struct i915_address_space *vm, |
| 3481 | const struct i915_ggtt_view *ggtt_view, |
| 3482 | unsigned alignment, |
| 3483 | uint64_t flags) |
| 3484 | { |
| 3485 | struct drm_device *dev = obj->base.dev; |
| 3486 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 3487 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
| 3488 | u32 fence_alignment, unfenced_alignment; |
| 3489 | u32 search_flag, alloc_flag; |
| 3490 | u64 start, end; |
| 3491 | u64 size, fence_size; |
| 3492 | struct i915_vma *vma; |
| 3493 | int ret; |
| 3494 | |
| 3495 | if (i915_is_ggtt(vm)) { |
| 3496 | u32 view_size; |
| 3497 | |
| 3498 | if (WARN_ON(!ggtt_view)) |
| 3499 | return ERR_PTR(-EINVAL); |
| 3500 | |
| 3501 | view_size = i915_ggtt_view_size(obj, ggtt_view); |
| 3502 | |
| 3503 | fence_size = i915_gem_get_gtt_size(dev, |
| 3504 | view_size, |
| 3505 | obj->tiling_mode); |
| 3506 | fence_alignment = i915_gem_get_gtt_alignment(dev, |
| 3507 | view_size, |
| 3508 | obj->tiling_mode, |
| 3509 | true); |
| 3510 | unfenced_alignment = i915_gem_get_gtt_alignment(dev, |
| 3511 | view_size, |
| 3512 | obj->tiling_mode, |
| 3513 | false); |
| 3514 | size = flags & PIN_MAPPABLE ? fence_size : view_size; |
| 3515 | } else { |
| 3516 | fence_size = i915_gem_get_gtt_size(dev, |
| 3517 | obj->base.size, |
| 3518 | obj->tiling_mode); |
| 3519 | fence_alignment = i915_gem_get_gtt_alignment(dev, |
| 3520 | obj->base.size, |
| 3521 | obj->tiling_mode, |
| 3522 | true); |
| 3523 | unfenced_alignment = |
| 3524 | i915_gem_get_gtt_alignment(dev, |
| 3525 | obj->base.size, |
| 3526 | obj->tiling_mode, |
| 3527 | false); |
| 3528 | size = flags & PIN_MAPPABLE ? fence_size : obj->base.size; |
| 3529 | } |
| 3530 | |
| 3531 | start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; |
| 3532 | end = vm->total; |
| 3533 | if (flags & PIN_MAPPABLE) |
| 3534 | end = min_t(u64, end, ggtt->mappable_end); |
| 3535 | if (flags & PIN_ZONE_4G) |
| 3536 | end = min_t(u64, end, (1ULL << 32) - PAGE_SIZE); |
| 3537 | |
| 3538 | if (alignment == 0) |
| 3539 | alignment = flags & PIN_MAPPABLE ? fence_alignment : |
| 3540 | unfenced_alignment; |
| 3541 | if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) { |
| 3542 | DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n", |
| 3543 | ggtt_view ? ggtt_view->type : 0, |
| 3544 | alignment); |
| 3545 | return ERR_PTR(-EINVAL); |
| 3546 | } |
| 3547 | |
| 3548 | /* If binding the object/GGTT view requires more space than the entire |
| 3549 | * aperture has, reject it early before evicting everything in a vain |
| 3550 | * attempt to find space. |
| 3551 | */ |
| 3552 | if (size > end) { |
| 3553 | DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%llu > %s aperture=%llu\n", |
| 3554 | ggtt_view ? ggtt_view->type : 0, |
| 3555 | size, |
| 3556 | flags & PIN_MAPPABLE ? "mappable" : "total", |
| 3557 | end); |
| 3558 | return ERR_PTR(-E2BIG); |
| 3559 | } |
| 3560 | |
| 3561 | ret = i915_gem_object_get_pages(obj); |
| 3562 | if (ret) |
| 3563 | return ERR_PTR(ret); |
| 3564 | |
| 3565 | i915_gem_object_pin_pages(obj); |
| 3566 | |
| 3567 | vma = ggtt_view ? i915_gem_obj_lookup_or_create_ggtt_vma(obj, ggtt_view) : |
| 3568 | i915_gem_obj_lookup_or_create_vma(obj, vm); |
| 3569 | |
| 3570 | if (IS_ERR(vma)) |
| 3571 | goto err_unpin; |
| 3572 | |
| 3573 | if (flags & PIN_OFFSET_FIXED) { |
| 3574 | uint64_t offset = flags & PIN_OFFSET_MASK; |
| 3575 | |
| 3576 | if (offset & (alignment - 1) || offset + size > end) { |
| 3577 | ret = -EINVAL; |
| 3578 | goto err_free_vma; |
| 3579 | } |
| 3580 | vma->node.start = offset; |
| 3581 | vma->node.size = size; |
| 3582 | vma->node.color = obj->cache_level; |
| 3583 | ret = drm_mm_reserve_node(&vm->mm, &vma->node); |
| 3584 | if (ret) { |
| 3585 | ret = i915_gem_evict_for_vma(vma); |
| 3586 | if (ret == 0) |
| 3587 | ret = drm_mm_reserve_node(&vm->mm, &vma->node); |
| 3588 | } |
| 3589 | if (ret) |
| 3590 | goto err_free_vma; |
| 3591 | } else { |
| 3592 | if (flags & PIN_HIGH) { |
| 3593 | search_flag = DRM_MM_SEARCH_BELOW; |
| 3594 | alloc_flag = DRM_MM_CREATE_TOP; |
| 3595 | } else { |
| 3596 | search_flag = DRM_MM_SEARCH_DEFAULT; |
| 3597 | alloc_flag = DRM_MM_CREATE_DEFAULT; |
| 3598 | } |
| 3599 | |
| 3600 | search_free: |
| 3601 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
| 3602 | size, alignment, |
| 3603 | obj->cache_level, |
| 3604 | start, end, |
| 3605 | search_flag, |
| 3606 | alloc_flag); |
| 3607 | if (ret) { |
| 3608 | ret = i915_gem_evict_something(dev, vm, size, alignment, |
| 3609 | obj->cache_level, |
| 3610 | start, end, |
| 3611 | flags); |
| 3612 | if (ret == 0) |
| 3613 | goto search_free; |
| 3614 | |
| 3615 | goto err_free_vma; |
| 3616 | } |
| 3617 | } |
| 3618 | if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) { |
| 3619 | ret = -EINVAL; |
| 3620 | goto err_remove_node; |
| 3621 | } |
| 3622 | |
| 3623 | trace_i915_vma_bind(vma, flags); |
| 3624 | ret = i915_vma_bind(vma, obj->cache_level, flags); |
| 3625 | if (ret) |
| 3626 | goto err_remove_node; |
| 3627 | |
| 3628 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
| 3629 | list_add_tail(&vma->vm_link, &vm->inactive_list); |
| 3630 | |
| 3631 | return vma; |
| 3632 | |
| 3633 | err_remove_node: |
| 3634 | drm_mm_remove_node(&vma->node); |
| 3635 | err_free_vma: |
| 3636 | i915_gem_vma_destroy(vma); |
| 3637 | vma = ERR_PTR(ret); |
| 3638 | err_unpin: |
| 3639 | i915_gem_object_unpin_pages(obj); |
| 3640 | return vma; |
| 3641 | } |
| 3642 | |
| 3643 | bool |
| 3644 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
| 3645 | bool force) |
| 3646 | { |
| 3647 | /* If we don't have a page list set up, then we're not pinned |
| 3648 | * to GPU, and we can ignore the cache flush because it'll happen |
| 3649 | * again at bind time. |
| 3650 | */ |
| 3651 | if (obj->pages == NULL) |
| 3652 | return false; |
| 3653 | |
| 3654 | /* |
| 3655 | * Stolen memory is always coherent with the GPU as it is explicitly |
| 3656 | * marked as wc by the system, or the system is cache-coherent. |
| 3657 | */ |
| 3658 | if (obj->stolen || obj->phys_handle) |
| 3659 | return false; |
| 3660 | |
| 3661 | /* If the GPU is snooping the contents of the CPU cache, |
| 3662 | * we do not need to manually clear the CPU cache lines. However, |
| 3663 | * the caches are only snooped when the render cache is |
| 3664 | * flushed/invalidated. As we always have to emit invalidations |
| 3665 | * and flushes when moving into and out of the RENDER domain, correct |
| 3666 | * snooping behaviour occurs naturally as the result of our domain |
| 3667 | * tracking. |
| 3668 | */ |
| 3669 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) { |
| 3670 | obj->cache_dirty = true; |
| 3671 | return false; |
| 3672 | } |
| 3673 | |
| 3674 | trace_i915_gem_object_clflush(obj); |
| 3675 | drm_clflush_sg(obj->pages); |
| 3676 | obj->cache_dirty = false; |
| 3677 | |
| 3678 | return true; |
| 3679 | } |
| 3680 | |
| 3681 | /** Flushes the GTT write domain for the object if it's dirty. */ |
| 3682 | static void |
| 3683 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
| 3684 | { |
| 3685 | uint32_t old_write_domain; |
| 3686 | |
| 3687 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
| 3688 | return; |
| 3689 | |
| 3690 | /* No actual flushing is required for the GTT write domain. Writes |
| 3691 | * to it immediately go to main memory as far as we know, so there's |
| 3692 | * no chipset flush. It also doesn't land in render cache. |
| 3693 | * |
| 3694 | * However, we do have to enforce the order so that all writes through |
| 3695 | * the GTT land before any writes to the device, such as updates to |
| 3696 | * the GATT itself. |
| 3697 | */ |
| 3698 | wmb(); |
| 3699 | |
| 3700 | old_write_domain = obj->base.write_domain; |
| 3701 | obj->base.write_domain = 0; |
| 3702 | |
| 3703 | intel_fb_obj_flush(obj, false, ORIGIN_GTT); |
| 3704 | |
| 3705 | trace_i915_gem_object_change_domain(obj, |
| 3706 | obj->base.read_domains, |
| 3707 | old_write_domain); |
| 3708 | } |
| 3709 | |
| 3710 | /** Flushes the CPU write domain for the object if it's dirty. */ |
| 3711 | static void |
| 3712 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
| 3713 | { |
| 3714 | uint32_t old_write_domain; |
| 3715 | |
| 3716 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
| 3717 | return; |
| 3718 | |
| 3719 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
| 3720 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
| 3721 | |
| 3722 | old_write_domain = obj->base.write_domain; |
| 3723 | obj->base.write_domain = 0; |
| 3724 | |
| 3725 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
| 3726 | |
| 3727 | trace_i915_gem_object_change_domain(obj, |
| 3728 | obj->base.read_domains, |
| 3729 | old_write_domain); |
| 3730 | } |
| 3731 | |
| 3732 | /** |
| 3733 | * Moves a single object to the GTT read, and possibly write domain. |
| 3734 | * |
| 3735 | * This function returns when the move is complete, including waiting on |
| 3736 | * flushes to occur. |
| 3737 | */ |
| 3738 | int |
| 3739 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
| 3740 | { |
| 3741 | struct drm_device *dev = obj->base.dev; |
| 3742 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 3743 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
| 3744 | uint32_t old_write_domain, old_read_domains; |
| 3745 | struct i915_vma *vma; |
| 3746 | int ret; |
| 3747 | |
| 3748 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
| 3749 | return 0; |
| 3750 | |
| 3751 | ret = i915_gem_object_wait_rendering(obj, !write); |
| 3752 | if (ret) |
| 3753 | return ret; |
| 3754 | |
| 3755 | /* Flush and acquire obj->pages so that we are coherent through |
| 3756 | * direct access in memory with previous cached writes through |
| 3757 | * shmemfs and that our cache domain tracking remains valid. |
| 3758 | * For example, if the obj->filp was moved to swap without us |
| 3759 | * being notified and releasing the pages, we would mistakenly |
| 3760 | * continue to assume that the obj remained out of the CPU cached |
| 3761 | * domain. |
| 3762 | */ |
| 3763 | ret = i915_gem_object_get_pages(obj); |
| 3764 | if (ret) |
| 3765 | return ret; |
| 3766 | |
| 3767 | i915_gem_object_flush_cpu_write_domain(obj); |
| 3768 | |
| 3769 | /* Serialise direct access to this object with the barriers for |
| 3770 | * coherent writes from the GPU, by effectively invalidating the |
| 3771 | * GTT domain upon first access. |
| 3772 | */ |
| 3773 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
| 3774 | mb(); |
| 3775 | |
| 3776 | old_write_domain = obj->base.write_domain; |
| 3777 | old_read_domains = obj->base.read_domains; |
| 3778 | |
| 3779 | /* It should now be out of any other write domains, and we can update |
| 3780 | * the domain values for our changes. |
| 3781 | */ |
| 3782 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
| 3783 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
| 3784 | if (write) { |
| 3785 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
| 3786 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; |
| 3787 | obj->dirty = 1; |
| 3788 | } |
| 3789 | |
| 3790 | trace_i915_gem_object_change_domain(obj, |
| 3791 | old_read_domains, |
| 3792 | old_write_domain); |
| 3793 | |
| 3794 | /* And bump the LRU for this access */ |
| 3795 | vma = i915_gem_obj_to_ggtt(obj); |
| 3796 | if (vma && drm_mm_node_allocated(&vma->node) && !obj->active) |
| 3797 | list_move_tail(&vma->vm_link, |
| 3798 | &ggtt->base.inactive_list); |
| 3799 | |
| 3800 | return 0; |
| 3801 | } |
| 3802 | |
| 3803 | /** |
| 3804 | * Changes the cache-level of an object across all VMA. |
| 3805 | * |
| 3806 | * After this function returns, the object will be in the new cache-level |
| 3807 | * across all GTT and the contents of the backing storage will be coherent, |
| 3808 | * with respect to the new cache-level. In order to keep the backing storage |
| 3809 | * coherent for all users, we only allow a single cache level to be set |
| 3810 | * globally on the object and prevent it from being changed whilst the |
| 3811 | * hardware is reading from the object. That is if the object is currently |
| 3812 | * on the scanout it will be set to uncached (or equivalent display |
| 3813 | * cache coherency) and all non-MOCS GPU access will also be uncached so |
| 3814 | * that all direct access to the scanout remains coherent. |
| 3815 | */ |
| 3816 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
| 3817 | enum i915_cache_level cache_level) |
| 3818 | { |
| 3819 | struct drm_device *dev = obj->base.dev; |
| 3820 | struct i915_vma *vma, *next; |
| 3821 | bool bound = false; |
| 3822 | int ret = 0; |
| 3823 | |
| 3824 | if (obj->cache_level == cache_level) |
| 3825 | goto out; |
| 3826 | |
| 3827 | /* Inspect the list of currently bound VMA and unbind any that would |
| 3828 | * be invalid given the new cache-level. This is principally to |
| 3829 | * catch the issue of the CS prefetch crossing page boundaries and |
| 3830 | * reading an invalid PTE on older architectures. |
| 3831 | */ |
| 3832 | list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) { |
| 3833 | if (!drm_mm_node_allocated(&vma->node)) |
| 3834 | continue; |
| 3835 | |
| 3836 | if (vma->pin_count) { |
| 3837 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
| 3838 | return -EBUSY; |
| 3839 | } |
| 3840 | |
| 3841 | if (!i915_gem_valid_gtt_space(vma, cache_level)) { |
| 3842 | ret = i915_vma_unbind(vma); |
| 3843 | if (ret) |
| 3844 | return ret; |
| 3845 | } else |
| 3846 | bound = true; |
| 3847 | } |
| 3848 | |
| 3849 | /* We can reuse the existing drm_mm nodes but need to change the |
| 3850 | * cache-level on the PTE. We could simply unbind them all and |
| 3851 | * rebind with the correct cache-level on next use. However since |
| 3852 | * we already have a valid slot, dma mapping, pages etc, we may as |
| 3853 | * rewrite the PTE in the belief that doing so tramples upon less |
| 3854 | * state and so involves less work. |
| 3855 | */ |
| 3856 | if (bound) { |
| 3857 | /* Before we change the PTE, the GPU must not be accessing it. |
| 3858 | * If we wait upon the object, we know that all the bound |
| 3859 | * VMA are no longer active. |
| 3860 | */ |
| 3861 | ret = i915_gem_object_wait_rendering(obj, false); |
| 3862 | if (ret) |
| 3863 | return ret; |
| 3864 | |
| 3865 | if (!HAS_LLC(dev) && cache_level != I915_CACHE_NONE) { |
| 3866 | /* Access to snoopable pages through the GTT is |
| 3867 | * incoherent and on some machines causes a hard |
| 3868 | * lockup. Relinquish the CPU mmaping to force |
| 3869 | * userspace to refault in the pages and we can |
| 3870 | * then double check if the GTT mapping is still |
| 3871 | * valid for that pointer access. |
| 3872 | */ |
| 3873 | i915_gem_release_mmap(obj); |
| 3874 | |
| 3875 | /* As we no longer need a fence for GTT access, |
| 3876 | * we can relinquish it now (and so prevent having |
| 3877 | * to steal a fence from someone else on the next |
| 3878 | * fence request). Note GPU activity would have |
| 3879 | * dropped the fence as all snoopable access is |
| 3880 | * supposed to be linear. |
| 3881 | */ |
| 3882 | ret = i915_gem_object_put_fence(obj); |
| 3883 | if (ret) |
| 3884 | return ret; |
| 3885 | } else { |
| 3886 | /* We either have incoherent backing store and |
| 3887 | * so no GTT access or the architecture is fully |
| 3888 | * coherent. In such cases, existing GTT mmaps |
| 3889 | * ignore the cache bit in the PTE and we can |
| 3890 | * rewrite it without confusing the GPU or having |
| 3891 | * to force userspace to fault back in its mmaps. |
| 3892 | */ |
| 3893 | } |
| 3894 | |
| 3895 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
| 3896 | if (!drm_mm_node_allocated(&vma->node)) |
| 3897 | continue; |
| 3898 | |
| 3899 | ret = i915_vma_bind(vma, cache_level, PIN_UPDATE); |
| 3900 | if (ret) |
| 3901 | return ret; |
| 3902 | } |
| 3903 | } |
| 3904 | |
| 3905 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
| 3906 | vma->node.color = cache_level; |
| 3907 | obj->cache_level = cache_level; |
| 3908 | |
| 3909 | out: |
| 3910 | /* Flush the dirty CPU caches to the backing storage so that the |
| 3911 | * object is now coherent at its new cache level (with respect |
| 3912 | * to the access domain). |
| 3913 | */ |
| 3914 | if (obj->cache_dirty && |
| 3915 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && |
| 3916 | cpu_write_needs_clflush(obj)) { |
| 3917 | if (i915_gem_clflush_object(obj, true)) |
| 3918 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
| 3919 | } |
| 3920 | |
| 3921 | return 0; |
| 3922 | } |
| 3923 | |
| 3924 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
| 3925 | struct drm_file *file) |
| 3926 | { |
| 3927 | struct drm_i915_gem_caching *args = data; |
| 3928 | struct drm_i915_gem_object *obj; |
| 3929 | |
| 3930 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
| 3931 | if (&obj->base == NULL) |
| 3932 | return -ENOENT; |
| 3933 | |
| 3934 | switch (obj->cache_level) { |
| 3935 | case I915_CACHE_LLC: |
| 3936 | case I915_CACHE_L3_LLC: |
| 3937 | args->caching = I915_CACHING_CACHED; |
| 3938 | break; |
| 3939 | |
| 3940 | case I915_CACHE_WT: |
| 3941 | args->caching = I915_CACHING_DISPLAY; |
| 3942 | break; |
| 3943 | |
| 3944 | default: |
| 3945 | args->caching = I915_CACHING_NONE; |
| 3946 | break; |
| 3947 | } |
| 3948 | |
| 3949 | drm_gem_object_unreference_unlocked(&obj->base); |
| 3950 | return 0; |
| 3951 | } |
| 3952 | |
| 3953 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
| 3954 | struct drm_file *file) |
| 3955 | { |
| 3956 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3957 | struct drm_i915_gem_caching *args = data; |
| 3958 | struct drm_i915_gem_object *obj; |
| 3959 | enum i915_cache_level level; |
| 3960 | int ret; |
| 3961 | |
| 3962 | switch (args->caching) { |
| 3963 | case I915_CACHING_NONE: |
| 3964 | level = I915_CACHE_NONE; |
| 3965 | break; |
| 3966 | case I915_CACHING_CACHED: |
| 3967 | /* |
| 3968 | * Due to a HW issue on BXT A stepping, GPU stores via a |
| 3969 | * snooped mapping may leave stale data in a corresponding CPU |
| 3970 | * cacheline, whereas normally such cachelines would get |
| 3971 | * invalidated. |
| 3972 | */ |
| 3973 | if (!HAS_LLC(dev) && !HAS_SNOOP(dev)) |
| 3974 | return -ENODEV; |
| 3975 | |
| 3976 | level = I915_CACHE_LLC; |
| 3977 | break; |
| 3978 | case I915_CACHING_DISPLAY: |
| 3979 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; |
| 3980 | break; |
| 3981 | default: |
| 3982 | return -EINVAL; |
| 3983 | } |
| 3984 | |
| 3985 | intel_runtime_pm_get(dev_priv); |
| 3986 | |
| 3987 | ret = i915_mutex_lock_interruptible(dev); |
| 3988 | if (ret) |
| 3989 | goto rpm_put; |
| 3990 | |
| 3991 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
| 3992 | if (&obj->base == NULL) { |
| 3993 | ret = -ENOENT; |
| 3994 | goto unlock; |
| 3995 | } |
| 3996 | |
| 3997 | ret = i915_gem_object_set_cache_level(obj, level); |
| 3998 | |
| 3999 | drm_gem_object_unreference(&obj->base); |
| 4000 | unlock: |
| 4001 | mutex_unlock(&dev->struct_mutex); |
| 4002 | rpm_put: |
| 4003 | intel_runtime_pm_put(dev_priv); |
| 4004 | |
| 4005 | return ret; |
| 4006 | } |
| 4007 | |
| 4008 | /* |
| 4009 | * Prepare buffer for display plane (scanout, cursors, etc). |
| 4010 | * Can be called from an uninterruptible phase (modesetting) and allows |
| 4011 | * any flushes to be pipelined (for pageflips). |
| 4012 | */ |
| 4013 | int |
| 4014 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
| 4015 | u32 alignment, |
| 4016 | const struct i915_ggtt_view *view) |
| 4017 | { |
| 4018 | u32 old_read_domains, old_write_domain; |
| 4019 | int ret; |
| 4020 | |
| 4021 | /* Mark the pin_display early so that we account for the |
| 4022 | * display coherency whilst setting up the cache domains. |
| 4023 | */ |
| 4024 | obj->pin_display++; |
| 4025 | |
| 4026 | /* The display engine is not coherent with the LLC cache on gen6. As |
| 4027 | * a result, we make sure that the pinning that is about to occur is |
| 4028 | * done with uncached PTEs. This is lowest common denominator for all |
| 4029 | * chipsets. |
| 4030 | * |
| 4031 | * However for gen6+, we could do better by using the GFDT bit instead |
| 4032 | * of uncaching, which would allow us to flush all the LLC-cached data |
| 4033 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. |
| 4034 | */ |
| 4035 | ret = i915_gem_object_set_cache_level(obj, |
| 4036 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); |
| 4037 | if (ret) |
| 4038 | goto err_unpin_display; |
| 4039 | |
| 4040 | /* As the user may map the buffer once pinned in the display plane |
| 4041 | * (e.g. libkms for the bootup splash), we have to ensure that we |
| 4042 | * always use map_and_fenceable for all scanout buffers. |
| 4043 | */ |
| 4044 | ret = i915_gem_object_ggtt_pin(obj, view, alignment, |
| 4045 | view->type == I915_GGTT_VIEW_NORMAL ? |
| 4046 | PIN_MAPPABLE : 0); |
| 4047 | if (ret) |
| 4048 | goto err_unpin_display; |
| 4049 | |
| 4050 | i915_gem_object_flush_cpu_write_domain(obj); |
| 4051 | |
| 4052 | old_write_domain = obj->base.write_domain; |
| 4053 | old_read_domains = obj->base.read_domains; |
| 4054 | |
| 4055 | /* It should now be out of any other write domains, and we can update |
| 4056 | * the domain values for our changes. |
| 4057 | */ |
| 4058 | obj->base.write_domain = 0; |
| 4059 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
| 4060 | |
| 4061 | trace_i915_gem_object_change_domain(obj, |
| 4062 | old_read_domains, |
| 4063 | old_write_domain); |
| 4064 | |
| 4065 | return 0; |
| 4066 | |
| 4067 | err_unpin_display: |
| 4068 | obj->pin_display--; |
| 4069 | return ret; |
| 4070 | } |
| 4071 | |
| 4072 | void |
| 4073 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj, |
| 4074 | const struct i915_ggtt_view *view) |
| 4075 | { |
| 4076 | if (WARN_ON(obj->pin_display == 0)) |
| 4077 | return; |
| 4078 | |
| 4079 | i915_gem_object_ggtt_unpin_view(obj, view); |
| 4080 | |
| 4081 | obj->pin_display--; |
| 4082 | } |
| 4083 | |
| 4084 | /** |
| 4085 | * Moves a single object to the CPU read, and possibly write domain. |
| 4086 | * |
| 4087 | * This function returns when the move is complete, including waiting on |
| 4088 | * flushes to occur. |
| 4089 | */ |
| 4090 | int |
| 4091 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
| 4092 | { |
| 4093 | uint32_t old_write_domain, old_read_domains; |
| 4094 | int ret; |
| 4095 | |
| 4096 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
| 4097 | return 0; |
| 4098 | |
| 4099 | ret = i915_gem_object_wait_rendering(obj, !write); |
| 4100 | if (ret) |
| 4101 | return ret; |
| 4102 | |
| 4103 | i915_gem_object_flush_gtt_write_domain(obj); |
| 4104 | |
| 4105 | old_write_domain = obj->base.write_domain; |
| 4106 | old_read_domains = obj->base.read_domains; |
| 4107 | |
| 4108 | /* Flush the CPU cache if it's still invalid. */ |
| 4109 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
| 4110 | i915_gem_clflush_object(obj, false); |
| 4111 | |
| 4112 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
| 4113 | } |
| 4114 | |
| 4115 | /* It should now be out of any other write domains, and we can update |
| 4116 | * the domain values for our changes. |
| 4117 | */ |
| 4118 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
| 4119 | |
| 4120 | /* If we're writing through the CPU, then the GPU read domains will |
| 4121 | * need to be invalidated at next use. |
| 4122 | */ |
| 4123 | if (write) { |
| 4124 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 4125 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 4126 | } |
| 4127 | |
| 4128 | trace_i915_gem_object_change_domain(obj, |
| 4129 | old_read_domains, |
| 4130 | old_write_domain); |
| 4131 | |
| 4132 | return 0; |
| 4133 | } |
| 4134 | |
| 4135 | /* Throttle our rendering by waiting until the ring has completed our requests |
| 4136 | * emitted over 20 msec ago. |
| 4137 | * |
| 4138 | * Note that if we were to use the current jiffies each time around the loop, |
| 4139 | * we wouldn't escape the function with any frames outstanding if the time to |
| 4140 | * render a frame was over 20ms. |
| 4141 | * |
| 4142 | * This should get us reasonable parallelism between CPU and GPU but also |
| 4143 | * relatively low latency when blocking on a particular request to finish. |
| 4144 | */ |
| 4145 | static int |
| 4146 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
| 4147 | { |
| 4148 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4149 | struct drm_i915_file_private *file_priv = file->driver_priv; |
| 4150 | unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES; |
| 4151 | struct drm_i915_gem_request *request, *target = NULL; |
| 4152 | int ret; |
| 4153 | |
| 4154 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
| 4155 | if (ret) |
| 4156 | return ret; |
| 4157 | |
| 4158 | /* ABI: return -EIO if already wedged */ |
| 4159 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
| 4160 | return -EIO; |
| 4161 | |
| 4162 | spin_lock(&file_priv->mm.lock); |
| 4163 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
| 4164 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
| 4165 | break; |
| 4166 | |
| 4167 | /* |
| 4168 | * Note that the request might not have been submitted yet. |
| 4169 | * In which case emitted_jiffies will be zero. |
| 4170 | */ |
| 4171 | if (!request->emitted_jiffies) |
| 4172 | continue; |
| 4173 | |
| 4174 | target = request; |
| 4175 | } |
| 4176 | if (target) |
| 4177 | i915_gem_request_reference(target); |
| 4178 | spin_unlock(&file_priv->mm.lock); |
| 4179 | |
| 4180 | if (target == NULL) |
| 4181 | return 0; |
| 4182 | |
| 4183 | ret = __i915_wait_request(target, true, NULL, NULL); |
| 4184 | if (ret == 0) |
| 4185 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); |
| 4186 | |
| 4187 | i915_gem_request_unreference(target); |
| 4188 | |
| 4189 | return ret; |
| 4190 | } |
| 4191 | |
| 4192 | static bool |
| 4193 | i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags) |
| 4194 | { |
| 4195 | struct drm_i915_gem_object *obj = vma->obj; |
| 4196 | |
| 4197 | if (alignment && |
| 4198 | vma->node.start & (alignment - 1)) |
| 4199 | return true; |
| 4200 | |
| 4201 | if (flags & PIN_MAPPABLE && !obj->map_and_fenceable) |
| 4202 | return true; |
| 4203 | |
| 4204 | if (flags & PIN_OFFSET_BIAS && |
| 4205 | vma->node.start < (flags & PIN_OFFSET_MASK)) |
| 4206 | return true; |
| 4207 | |
| 4208 | if (flags & PIN_OFFSET_FIXED && |
| 4209 | vma->node.start != (flags & PIN_OFFSET_MASK)) |
| 4210 | return true; |
| 4211 | |
| 4212 | return false; |
| 4213 | } |
| 4214 | |
| 4215 | void __i915_vma_set_map_and_fenceable(struct i915_vma *vma) |
| 4216 | { |
| 4217 | struct drm_i915_gem_object *obj = vma->obj; |
| 4218 | bool mappable, fenceable; |
| 4219 | u32 fence_size, fence_alignment; |
| 4220 | |
| 4221 | fence_size = i915_gem_get_gtt_size(obj->base.dev, |
| 4222 | obj->base.size, |
| 4223 | obj->tiling_mode); |
| 4224 | fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev, |
| 4225 | obj->base.size, |
| 4226 | obj->tiling_mode, |
| 4227 | true); |
| 4228 | |
| 4229 | fenceable = (vma->node.size == fence_size && |
| 4230 | (vma->node.start & (fence_alignment - 1)) == 0); |
| 4231 | |
| 4232 | mappable = (vma->node.start + fence_size <= |
| 4233 | to_i915(obj->base.dev)->ggtt.mappable_end); |
| 4234 | |
| 4235 | obj->map_and_fenceable = mappable && fenceable; |
| 4236 | } |
| 4237 | |
| 4238 | static int |
| 4239 | i915_gem_object_do_pin(struct drm_i915_gem_object *obj, |
| 4240 | struct i915_address_space *vm, |
| 4241 | const struct i915_ggtt_view *ggtt_view, |
| 4242 | uint32_t alignment, |
| 4243 | uint64_t flags) |
| 4244 | { |
| 4245 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 4246 | struct i915_vma *vma; |
| 4247 | unsigned bound; |
| 4248 | int ret; |
| 4249 | |
| 4250 | if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base)) |
| 4251 | return -ENODEV; |
| 4252 | |
| 4253 | if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm))) |
| 4254 | return -EINVAL; |
| 4255 | |
| 4256 | if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE)) |
| 4257 | return -EINVAL; |
| 4258 | |
| 4259 | if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view)) |
| 4260 | return -EINVAL; |
| 4261 | |
| 4262 | vma = ggtt_view ? i915_gem_obj_to_ggtt_view(obj, ggtt_view) : |
| 4263 | i915_gem_obj_to_vma(obj, vm); |
| 4264 | |
| 4265 | if (vma) { |
| 4266 | if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
| 4267 | return -EBUSY; |
| 4268 | |
| 4269 | if (i915_vma_misplaced(vma, alignment, flags)) { |
| 4270 | WARN(vma->pin_count, |
| 4271 | "bo is already pinned in %s with incorrect alignment:" |
| 4272 | " offset=%08x %08x, req.alignment=%x, req.map_and_fenceable=%d," |
| 4273 | " obj->map_and_fenceable=%d\n", |
| 4274 | ggtt_view ? "ggtt" : "ppgtt", |
| 4275 | upper_32_bits(vma->node.start), |
| 4276 | lower_32_bits(vma->node.start), |
| 4277 | alignment, |
| 4278 | !!(flags & PIN_MAPPABLE), |
| 4279 | obj->map_and_fenceable); |
| 4280 | ret = i915_vma_unbind(vma); |
| 4281 | if (ret) |
| 4282 | return ret; |
| 4283 | |
| 4284 | vma = NULL; |
| 4285 | } |
| 4286 | } |
| 4287 | |
| 4288 | bound = vma ? vma->bound : 0; |
| 4289 | if (vma == NULL || !drm_mm_node_allocated(&vma->node)) { |
| 4290 | vma = i915_gem_object_bind_to_vm(obj, vm, ggtt_view, alignment, |
| 4291 | flags); |
| 4292 | if (IS_ERR(vma)) |
| 4293 | return PTR_ERR(vma); |
| 4294 | } else { |
| 4295 | ret = i915_vma_bind(vma, obj->cache_level, flags); |
| 4296 | if (ret) |
| 4297 | return ret; |
| 4298 | } |
| 4299 | |
| 4300 | if (ggtt_view && ggtt_view->type == I915_GGTT_VIEW_NORMAL && |
| 4301 | (bound ^ vma->bound) & GLOBAL_BIND) { |
| 4302 | __i915_vma_set_map_and_fenceable(vma); |
| 4303 | WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); |
| 4304 | } |
| 4305 | |
| 4306 | vma->pin_count++; |
| 4307 | return 0; |
| 4308 | } |
| 4309 | |
| 4310 | int |
| 4311 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
| 4312 | struct i915_address_space *vm, |
| 4313 | uint32_t alignment, |
| 4314 | uint64_t flags) |
| 4315 | { |
| 4316 | return i915_gem_object_do_pin(obj, vm, |
| 4317 | i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL, |
| 4318 | alignment, flags); |
| 4319 | } |
| 4320 | |
| 4321 | int |
| 4322 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, |
| 4323 | const struct i915_ggtt_view *view, |
| 4324 | uint32_t alignment, |
| 4325 | uint64_t flags) |
| 4326 | { |
| 4327 | struct drm_device *dev = obj->base.dev; |
| 4328 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 4329 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
| 4330 | |
| 4331 | BUG_ON(!view); |
| 4332 | |
| 4333 | return i915_gem_object_do_pin(obj, &ggtt->base, view, |
| 4334 | alignment, flags | PIN_GLOBAL); |
| 4335 | } |
| 4336 | |
| 4337 | void |
| 4338 | i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj, |
| 4339 | const struct i915_ggtt_view *view) |
| 4340 | { |
| 4341 | struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view); |
| 4342 | |
| 4343 | WARN_ON(vma->pin_count == 0); |
| 4344 | WARN_ON(!i915_gem_obj_ggtt_bound_view(obj, view)); |
| 4345 | |
| 4346 | --vma->pin_count; |
| 4347 | } |
| 4348 | |
| 4349 | int |
| 4350 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
| 4351 | struct drm_file *file) |
| 4352 | { |
| 4353 | struct drm_i915_gem_busy *args = data; |
| 4354 | struct drm_i915_gem_object *obj; |
| 4355 | int ret; |
| 4356 | |
| 4357 | ret = i915_mutex_lock_interruptible(dev); |
| 4358 | if (ret) |
| 4359 | return ret; |
| 4360 | |
| 4361 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
| 4362 | if (&obj->base == NULL) { |
| 4363 | ret = -ENOENT; |
| 4364 | goto unlock; |
| 4365 | } |
| 4366 | |
| 4367 | /* Count all active objects as busy, even if they are currently not used |
| 4368 | * by the gpu. Users of this interface expect objects to eventually |
| 4369 | * become non-busy without any further actions, therefore emit any |
| 4370 | * necessary flushes here. |
| 4371 | */ |
| 4372 | ret = i915_gem_object_flush_active(obj); |
| 4373 | if (ret) |
| 4374 | goto unref; |
| 4375 | |
| 4376 | args->busy = 0; |
| 4377 | if (obj->active) { |
| 4378 | int i; |
| 4379 | |
| 4380 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
| 4381 | struct drm_i915_gem_request *req; |
| 4382 | |
| 4383 | req = obj->last_read_req[i]; |
| 4384 | if (req) |
| 4385 | args->busy |= 1 << (16 + req->engine->exec_id); |
| 4386 | } |
| 4387 | if (obj->last_write_req) |
| 4388 | args->busy |= obj->last_write_req->engine->exec_id; |
| 4389 | } |
| 4390 | |
| 4391 | unref: |
| 4392 | drm_gem_object_unreference(&obj->base); |
| 4393 | unlock: |
| 4394 | mutex_unlock(&dev->struct_mutex); |
| 4395 | return ret; |
| 4396 | } |
| 4397 | |
| 4398 | int |
| 4399 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 4400 | struct drm_file *file_priv) |
| 4401 | { |
| 4402 | return i915_gem_ring_throttle(dev, file_priv); |
| 4403 | } |
| 4404 | |
| 4405 | int |
| 4406 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
| 4407 | struct drm_file *file_priv) |
| 4408 | { |
| 4409 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4410 | struct drm_i915_gem_madvise *args = data; |
| 4411 | struct drm_i915_gem_object *obj; |
| 4412 | int ret; |
| 4413 | |
| 4414 | switch (args->madv) { |
| 4415 | case I915_MADV_DONTNEED: |
| 4416 | case I915_MADV_WILLNEED: |
| 4417 | break; |
| 4418 | default: |
| 4419 | return -EINVAL; |
| 4420 | } |
| 4421 | |
| 4422 | ret = i915_mutex_lock_interruptible(dev); |
| 4423 | if (ret) |
| 4424 | return ret; |
| 4425 | |
| 4426 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
| 4427 | if (&obj->base == NULL) { |
| 4428 | ret = -ENOENT; |
| 4429 | goto unlock; |
| 4430 | } |
| 4431 | |
| 4432 | if (i915_gem_obj_is_pinned(obj)) { |
| 4433 | ret = -EINVAL; |
| 4434 | goto out; |
| 4435 | } |
| 4436 | |
| 4437 | if (obj->pages && |
| 4438 | obj->tiling_mode != I915_TILING_NONE && |
| 4439 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { |
| 4440 | if (obj->madv == I915_MADV_WILLNEED) |
| 4441 | i915_gem_object_unpin_pages(obj); |
| 4442 | if (args->madv == I915_MADV_WILLNEED) |
| 4443 | i915_gem_object_pin_pages(obj); |
| 4444 | } |
| 4445 | |
| 4446 | if (obj->madv != __I915_MADV_PURGED) |
| 4447 | obj->madv = args->madv; |
| 4448 | |
| 4449 | /* if the object is no longer attached, discard its backing storage */ |
| 4450 | if (obj->madv == I915_MADV_DONTNEED && obj->pages == NULL) |
| 4451 | i915_gem_object_truncate(obj); |
| 4452 | |
| 4453 | args->retained = obj->madv != __I915_MADV_PURGED; |
| 4454 | |
| 4455 | out: |
| 4456 | drm_gem_object_unreference(&obj->base); |
| 4457 | unlock: |
| 4458 | mutex_unlock(&dev->struct_mutex); |
| 4459 | return ret; |
| 4460 | } |
| 4461 | |
| 4462 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
| 4463 | const struct drm_i915_gem_object_ops *ops) |
| 4464 | { |
| 4465 | int i; |
| 4466 | |
| 4467 | INIT_LIST_HEAD(&obj->global_list); |
| 4468 | for (i = 0; i < I915_NUM_ENGINES; i++) |
| 4469 | INIT_LIST_HEAD(&obj->engine_list[i]); |
| 4470 | INIT_LIST_HEAD(&obj->obj_exec_link); |
| 4471 | INIT_LIST_HEAD(&obj->vma_list); |
| 4472 | INIT_LIST_HEAD(&obj->batch_pool_link); |
| 4473 | |
| 4474 | obj->ops = ops; |
| 4475 | |
| 4476 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 4477 | obj->madv = I915_MADV_WILLNEED; |
| 4478 | |
| 4479 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); |
| 4480 | } |
| 4481 | |
| 4482 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
| 4483 | .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE, |
| 4484 | .get_pages = i915_gem_object_get_pages_gtt, |
| 4485 | .put_pages = i915_gem_object_put_pages_gtt, |
| 4486 | }; |
| 4487 | |
| 4488 | struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev, |
| 4489 | size_t size) |
| 4490 | { |
| 4491 | struct drm_i915_gem_object *obj; |
| 4492 | struct address_space *mapping; |
| 4493 | gfp_t mask; |
| 4494 | int ret; |
| 4495 | |
| 4496 | obj = i915_gem_object_alloc(dev); |
| 4497 | if (obj == NULL) |
| 4498 | return ERR_PTR(-ENOMEM); |
| 4499 | |
| 4500 | ret = drm_gem_object_init(dev, &obj->base, size); |
| 4501 | if (ret) |
| 4502 | goto fail; |
| 4503 | |
| 4504 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
| 4505 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { |
| 4506 | /* 965gm cannot relocate objects above 4GiB. */ |
| 4507 | mask &= ~__GFP_HIGHMEM; |
| 4508 | mask |= __GFP_DMA32; |
| 4509 | } |
| 4510 | |
| 4511 | mapping = file_inode(obj->base.filp)->i_mapping; |
| 4512 | mapping_set_gfp_mask(mapping, mask); |
| 4513 | |
| 4514 | i915_gem_object_init(obj, &i915_gem_object_ops); |
| 4515 | |
| 4516 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 4517 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 4518 | |
| 4519 | if (HAS_LLC(dev)) { |
| 4520 | /* On some devices, we can have the GPU use the LLC (the CPU |
| 4521 | * cache) for about a 10% performance improvement |
| 4522 | * compared to uncached. Graphics requests other than |
| 4523 | * display scanout are coherent with the CPU in |
| 4524 | * accessing this cache. This means in this mode we |
| 4525 | * don't need to clflush on the CPU side, and on the |
| 4526 | * GPU side we only need to flush internal caches to |
| 4527 | * get data visible to the CPU. |
| 4528 | * |
| 4529 | * However, we maintain the display planes as UC, and so |
| 4530 | * need to rebind when first used as such. |
| 4531 | */ |
| 4532 | obj->cache_level = I915_CACHE_LLC; |
| 4533 | } else |
| 4534 | obj->cache_level = I915_CACHE_NONE; |
| 4535 | |
| 4536 | trace_i915_gem_object_create(obj); |
| 4537 | |
| 4538 | return obj; |
| 4539 | |
| 4540 | fail: |
| 4541 | i915_gem_object_free(obj); |
| 4542 | |
| 4543 | return ERR_PTR(ret); |
| 4544 | } |
| 4545 | |
| 4546 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
| 4547 | { |
| 4548 | /* If we are the last user of the backing storage (be it shmemfs |
| 4549 | * pages or stolen etc), we know that the pages are going to be |
| 4550 | * immediately released. In this case, we can then skip copying |
| 4551 | * back the contents from the GPU. |
| 4552 | */ |
| 4553 | |
| 4554 | if (obj->madv != I915_MADV_WILLNEED) |
| 4555 | return false; |
| 4556 | |
| 4557 | if (obj->base.filp == NULL) |
| 4558 | return true; |
| 4559 | |
| 4560 | /* At first glance, this looks racy, but then again so would be |
| 4561 | * userspace racing mmap against close. However, the first external |
| 4562 | * reference to the filp can only be obtained through the |
| 4563 | * i915_gem_mmap_ioctl() which safeguards us against the user |
| 4564 | * acquiring such a reference whilst we are in the middle of |
| 4565 | * freeing the object. |
| 4566 | */ |
| 4567 | return atomic_long_read(&obj->base.filp->f_count) == 1; |
| 4568 | } |
| 4569 | |
| 4570 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
| 4571 | { |
| 4572 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
| 4573 | struct drm_device *dev = obj->base.dev; |
| 4574 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4575 | struct i915_vma *vma, *next; |
| 4576 | |
| 4577 | intel_runtime_pm_get(dev_priv); |
| 4578 | |
| 4579 | trace_i915_gem_object_destroy(obj); |
| 4580 | |
| 4581 | list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) { |
| 4582 | int ret; |
| 4583 | |
| 4584 | vma->pin_count = 0; |
| 4585 | ret = i915_vma_unbind(vma); |
| 4586 | if (WARN_ON(ret == -ERESTARTSYS)) { |
| 4587 | bool was_interruptible; |
| 4588 | |
| 4589 | was_interruptible = dev_priv->mm.interruptible; |
| 4590 | dev_priv->mm.interruptible = false; |
| 4591 | |
| 4592 | WARN_ON(i915_vma_unbind(vma)); |
| 4593 | |
| 4594 | dev_priv->mm.interruptible = was_interruptible; |
| 4595 | } |
| 4596 | } |
| 4597 | |
| 4598 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
| 4599 | * before progressing. */ |
| 4600 | if (obj->stolen) |
| 4601 | i915_gem_object_unpin_pages(obj); |
| 4602 | |
| 4603 | WARN_ON(obj->frontbuffer_bits); |
| 4604 | |
| 4605 | if (obj->pages && obj->madv == I915_MADV_WILLNEED && |
| 4606 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES && |
| 4607 | obj->tiling_mode != I915_TILING_NONE) |
| 4608 | i915_gem_object_unpin_pages(obj); |
| 4609 | |
| 4610 | if (WARN_ON(obj->pages_pin_count)) |
| 4611 | obj->pages_pin_count = 0; |
| 4612 | if (discard_backing_storage(obj)) |
| 4613 | obj->madv = I915_MADV_DONTNEED; |
| 4614 | i915_gem_object_put_pages(obj); |
| 4615 | i915_gem_object_free_mmap_offset(obj); |
| 4616 | |
| 4617 | BUG_ON(obj->pages); |
| 4618 | |
| 4619 | if (obj->base.import_attach) |
| 4620 | drm_prime_gem_destroy(&obj->base, NULL); |
| 4621 | |
| 4622 | if (obj->ops->release) |
| 4623 | obj->ops->release(obj); |
| 4624 | |
| 4625 | drm_gem_object_release(&obj->base); |
| 4626 | i915_gem_info_remove_obj(dev_priv, obj->base.size); |
| 4627 | |
| 4628 | kfree(obj->bit_17); |
| 4629 | i915_gem_object_free(obj); |
| 4630 | |
| 4631 | intel_runtime_pm_put(dev_priv); |
| 4632 | } |
| 4633 | |
| 4634 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
| 4635 | struct i915_address_space *vm) |
| 4636 | { |
| 4637 | struct i915_vma *vma; |
| 4638 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
| 4639 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL && |
| 4640 | vma->vm == vm) |
| 4641 | return vma; |
| 4642 | } |
| 4643 | return NULL; |
| 4644 | } |
| 4645 | |
| 4646 | struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj, |
| 4647 | const struct i915_ggtt_view *view) |
| 4648 | { |
| 4649 | struct i915_vma *vma; |
| 4650 | |
| 4651 | GEM_BUG_ON(!view); |
| 4652 | |
| 4653 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
| 4654 | if (vma->is_ggtt && i915_ggtt_view_equal(&vma->ggtt_view, view)) |
| 4655 | return vma; |
| 4656 | return NULL; |
| 4657 | } |
| 4658 | |
| 4659 | void i915_gem_vma_destroy(struct i915_vma *vma) |
| 4660 | { |
| 4661 | WARN_ON(vma->node.allocated); |
| 4662 | |
| 4663 | /* Keep the vma as a placeholder in the execbuffer reservation lists */ |
| 4664 | if (!list_empty(&vma->exec_list)) |
| 4665 | return; |
| 4666 | |
| 4667 | if (!vma->is_ggtt) |
| 4668 | i915_ppgtt_put(i915_vm_to_ppgtt(vma->vm)); |
| 4669 | |
| 4670 | list_del(&vma->obj_link); |
| 4671 | |
| 4672 | kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma); |
| 4673 | } |
| 4674 | |
| 4675 | static void |
| 4676 | i915_gem_stop_engines(struct drm_device *dev) |
| 4677 | { |
| 4678 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4679 | struct intel_engine_cs *engine; |
| 4680 | |
| 4681 | for_each_engine(engine, dev_priv) |
| 4682 | dev_priv->gt.stop_engine(engine); |
| 4683 | } |
| 4684 | |
| 4685 | int |
| 4686 | i915_gem_suspend(struct drm_device *dev) |
| 4687 | { |
| 4688 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4689 | int ret = 0; |
| 4690 | |
| 4691 | mutex_lock(&dev->struct_mutex); |
| 4692 | ret = i915_gpu_idle(dev); |
| 4693 | if (ret) |
| 4694 | goto err; |
| 4695 | |
| 4696 | i915_gem_retire_requests(dev_priv); |
| 4697 | |
| 4698 | i915_gem_stop_engines(dev); |
| 4699 | i915_gem_context_lost(dev_priv); |
| 4700 | mutex_unlock(&dev->struct_mutex); |
| 4701 | |
| 4702 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
| 4703 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
| 4704 | flush_delayed_work(&dev_priv->mm.idle_work); |
| 4705 | |
| 4706 | /* Assert that we sucessfully flushed all the work and |
| 4707 | * reset the GPU back to its idle, low power state. |
| 4708 | */ |
| 4709 | WARN_ON(dev_priv->mm.busy); |
| 4710 | |
| 4711 | return 0; |
| 4712 | |
| 4713 | err: |
| 4714 | mutex_unlock(&dev->struct_mutex); |
| 4715 | return ret; |
| 4716 | } |
| 4717 | |
| 4718 | void i915_gem_init_swizzling(struct drm_device *dev) |
| 4719 | { |
| 4720 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4721 | |
| 4722 | if (INTEL_INFO(dev)->gen < 5 || |
| 4723 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
| 4724 | return; |
| 4725 | |
| 4726 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | |
| 4727 | DISP_TILE_SURFACE_SWIZZLING); |
| 4728 | |
| 4729 | if (IS_GEN5(dev)) |
| 4730 | return; |
| 4731 | |
| 4732 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
| 4733 | if (IS_GEN6(dev)) |
| 4734 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
| 4735 | else if (IS_GEN7(dev)) |
| 4736 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
| 4737 | else if (IS_GEN8(dev)) |
| 4738 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); |
| 4739 | else |
| 4740 | BUG(); |
| 4741 | } |
| 4742 | |
| 4743 | static void init_unused_ring(struct drm_device *dev, u32 base) |
| 4744 | { |
| 4745 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4746 | |
| 4747 | I915_WRITE(RING_CTL(base), 0); |
| 4748 | I915_WRITE(RING_HEAD(base), 0); |
| 4749 | I915_WRITE(RING_TAIL(base), 0); |
| 4750 | I915_WRITE(RING_START(base), 0); |
| 4751 | } |
| 4752 | |
| 4753 | static void init_unused_rings(struct drm_device *dev) |
| 4754 | { |
| 4755 | if (IS_I830(dev)) { |
| 4756 | init_unused_ring(dev, PRB1_BASE); |
| 4757 | init_unused_ring(dev, SRB0_BASE); |
| 4758 | init_unused_ring(dev, SRB1_BASE); |
| 4759 | init_unused_ring(dev, SRB2_BASE); |
| 4760 | init_unused_ring(dev, SRB3_BASE); |
| 4761 | } else if (IS_GEN2(dev)) { |
| 4762 | init_unused_ring(dev, SRB0_BASE); |
| 4763 | init_unused_ring(dev, SRB1_BASE); |
| 4764 | } else if (IS_GEN3(dev)) { |
| 4765 | init_unused_ring(dev, PRB1_BASE); |
| 4766 | init_unused_ring(dev, PRB2_BASE); |
| 4767 | } |
| 4768 | } |
| 4769 | |
| 4770 | int i915_gem_init_engines(struct drm_device *dev) |
| 4771 | { |
| 4772 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4773 | int ret; |
| 4774 | |
| 4775 | ret = intel_init_render_ring_buffer(dev); |
| 4776 | if (ret) |
| 4777 | return ret; |
| 4778 | |
| 4779 | if (HAS_BSD(dev)) { |
| 4780 | ret = intel_init_bsd_ring_buffer(dev); |
| 4781 | if (ret) |
| 4782 | goto cleanup_render_ring; |
| 4783 | } |
| 4784 | |
| 4785 | if (HAS_BLT(dev)) { |
| 4786 | ret = intel_init_blt_ring_buffer(dev); |
| 4787 | if (ret) |
| 4788 | goto cleanup_bsd_ring; |
| 4789 | } |
| 4790 | |
| 4791 | if (HAS_VEBOX(dev)) { |
| 4792 | ret = intel_init_vebox_ring_buffer(dev); |
| 4793 | if (ret) |
| 4794 | goto cleanup_blt_ring; |
| 4795 | } |
| 4796 | |
| 4797 | if (HAS_BSD2(dev)) { |
| 4798 | ret = intel_init_bsd2_ring_buffer(dev); |
| 4799 | if (ret) |
| 4800 | goto cleanup_vebox_ring; |
| 4801 | } |
| 4802 | |
| 4803 | return 0; |
| 4804 | |
| 4805 | cleanup_vebox_ring: |
| 4806 | intel_cleanup_engine(&dev_priv->engine[VECS]); |
| 4807 | cleanup_blt_ring: |
| 4808 | intel_cleanup_engine(&dev_priv->engine[BCS]); |
| 4809 | cleanup_bsd_ring: |
| 4810 | intel_cleanup_engine(&dev_priv->engine[VCS]); |
| 4811 | cleanup_render_ring: |
| 4812 | intel_cleanup_engine(&dev_priv->engine[RCS]); |
| 4813 | |
| 4814 | return ret; |
| 4815 | } |
| 4816 | |
| 4817 | int |
| 4818 | i915_gem_init_hw(struct drm_device *dev) |
| 4819 | { |
| 4820 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4821 | struct intel_engine_cs *engine; |
| 4822 | int ret; |
| 4823 | |
| 4824 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) |
| 4825 | return -EIO; |
| 4826 | |
| 4827 | /* Double layer security blanket, see i915_gem_init() */ |
| 4828 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
| 4829 | |
| 4830 | if (HAS_EDRAM(dev) && INTEL_GEN(dev_priv) < 9) |
| 4831 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
| 4832 | |
| 4833 | if (IS_HASWELL(dev)) |
| 4834 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? |
| 4835 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); |
| 4836 | |
| 4837 | if (HAS_PCH_NOP(dev)) { |
| 4838 | if (IS_IVYBRIDGE(dev)) { |
| 4839 | u32 temp = I915_READ(GEN7_MSG_CTL); |
| 4840 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); |
| 4841 | I915_WRITE(GEN7_MSG_CTL, temp); |
| 4842 | } else if (INTEL_INFO(dev)->gen >= 7) { |
| 4843 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); |
| 4844 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; |
| 4845 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); |
| 4846 | } |
| 4847 | } |
| 4848 | |
| 4849 | i915_gem_init_swizzling(dev); |
| 4850 | |
| 4851 | /* |
| 4852 | * At least 830 can leave some of the unused rings |
| 4853 | * "active" (ie. head != tail) after resume which |
| 4854 | * will prevent c3 entry. Makes sure all unused rings |
| 4855 | * are totally idle. |
| 4856 | */ |
| 4857 | init_unused_rings(dev); |
| 4858 | |
| 4859 | BUG_ON(!dev_priv->kernel_context); |
| 4860 | |
| 4861 | ret = i915_ppgtt_init_hw(dev); |
| 4862 | if (ret) { |
| 4863 | DRM_ERROR("PPGTT enable HW failed %d\n", ret); |
| 4864 | goto out; |
| 4865 | } |
| 4866 | |
| 4867 | /* Need to do basic initialisation of all rings first: */ |
| 4868 | for_each_engine(engine, dev_priv) { |
| 4869 | ret = engine->init_hw(engine); |
| 4870 | if (ret) |
| 4871 | goto out; |
| 4872 | } |
| 4873 | |
| 4874 | intel_mocs_init_l3cc_table(dev); |
| 4875 | |
| 4876 | /* We can't enable contexts until all firmware is loaded */ |
| 4877 | if (HAS_GUC_UCODE(dev)) { |
| 4878 | ret = intel_guc_ucode_load(dev); |
| 4879 | if (ret) { |
| 4880 | DRM_ERROR("Failed to initialize GuC, error %d\n", ret); |
| 4881 | ret = -EIO; |
| 4882 | goto out; |
| 4883 | } |
| 4884 | } |
| 4885 | |
| 4886 | /* |
| 4887 | * Increment the next seqno by 0x100 so we have a visible break |
| 4888 | * on re-initialisation |
| 4889 | */ |
| 4890 | ret = i915_gem_set_seqno(dev, dev_priv->next_seqno+0x100); |
| 4891 | |
| 4892 | out: |
| 4893 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
| 4894 | return ret; |
| 4895 | } |
| 4896 | |
| 4897 | int i915_gem_init(struct drm_device *dev) |
| 4898 | { |
| 4899 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4900 | int ret; |
| 4901 | |
| 4902 | mutex_lock(&dev->struct_mutex); |
| 4903 | |
| 4904 | if (!i915.enable_execlists) { |
| 4905 | dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission; |
| 4906 | dev_priv->gt.init_engines = i915_gem_init_engines; |
| 4907 | dev_priv->gt.cleanup_engine = intel_cleanup_engine; |
| 4908 | dev_priv->gt.stop_engine = intel_stop_engine; |
| 4909 | } else { |
| 4910 | dev_priv->gt.execbuf_submit = intel_execlists_submission; |
| 4911 | dev_priv->gt.init_engines = intel_logical_rings_init; |
| 4912 | dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup; |
| 4913 | dev_priv->gt.stop_engine = intel_logical_ring_stop; |
| 4914 | } |
| 4915 | |
| 4916 | /* This is just a security blanket to placate dragons. |
| 4917 | * On some systems, we very sporadically observe that the first TLBs |
| 4918 | * used by the CS may be stale, despite us poking the TLB reset. If |
| 4919 | * we hold the forcewake during initialisation these problems |
| 4920 | * just magically go away. |
| 4921 | */ |
| 4922 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
| 4923 | |
| 4924 | ret = i915_gem_init_userptr(dev); |
| 4925 | if (ret) |
| 4926 | goto out_unlock; |
| 4927 | |
| 4928 | i915_gem_init_ggtt(dev); |
| 4929 | |
| 4930 | ret = i915_gem_context_init(dev); |
| 4931 | if (ret) |
| 4932 | goto out_unlock; |
| 4933 | |
| 4934 | ret = dev_priv->gt.init_engines(dev); |
| 4935 | if (ret) |
| 4936 | goto out_unlock; |
| 4937 | |
| 4938 | ret = i915_gem_init_hw(dev); |
| 4939 | if (ret == -EIO) { |
| 4940 | /* Allow ring initialisation to fail by marking the GPU as |
| 4941 | * wedged. But we only want to do this where the GPU is angry, |
| 4942 | * for all other failure, such as an allocation failure, bail. |
| 4943 | */ |
| 4944 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); |
| 4945 | atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter); |
| 4946 | ret = 0; |
| 4947 | } |
| 4948 | |
| 4949 | out_unlock: |
| 4950 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
| 4951 | mutex_unlock(&dev->struct_mutex); |
| 4952 | |
| 4953 | return ret; |
| 4954 | } |
| 4955 | |
| 4956 | void |
| 4957 | i915_gem_cleanup_engines(struct drm_device *dev) |
| 4958 | { |
| 4959 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4960 | struct intel_engine_cs *engine; |
| 4961 | |
| 4962 | for_each_engine(engine, dev_priv) |
| 4963 | dev_priv->gt.cleanup_engine(engine); |
| 4964 | } |
| 4965 | |
| 4966 | static void |
| 4967 | init_engine_lists(struct intel_engine_cs *engine) |
| 4968 | { |
| 4969 | INIT_LIST_HEAD(&engine->active_list); |
| 4970 | INIT_LIST_HEAD(&engine->request_list); |
| 4971 | } |
| 4972 | |
| 4973 | void |
| 4974 | i915_gem_load_init_fences(struct drm_i915_private *dev_priv) |
| 4975 | { |
| 4976 | struct drm_device *dev = dev_priv->dev; |
| 4977 | |
| 4978 | if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) && |
| 4979 | !IS_CHERRYVIEW(dev_priv)) |
| 4980 | dev_priv->num_fence_regs = 32; |
| 4981 | else if (INTEL_INFO(dev_priv)->gen >= 4 || IS_I945G(dev_priv) || |
| 4982 | IS_I945GM(dev_priv) || IS_G33(dev_priv)) |
| 4983 | dev_priv->num_fence_regs = 16; |
| 4984 | else |
| 4985 | dev_priv->num_fence_regs = 8; |
| 4986 | |
| 4987 | if (intel_vgpu_active(dev_priv)) |
| 4988 | dev_priv->num_fence_regs = |
| 4989 | I915_READ(vgtif_reg(avail_rs.fence_num)); |
| 4990 | |
| 4991 | /* Initialize fence registers to zero */ |
| 4992 | i915_gem_restore_fences(dev); |
| 4993 | |
| 4994 | i915_gem_detect_bit_6_swizzle(dev); |
| 4995 | } |
| 4996 | |
| 4997 | void |
| 4998 | i915_gem_load_init(struct drm_device *dev) |
| 4999 | { |
| 5000 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5001 | int i; |
| 5002 | |
| 5003 | dev_priv->objects = |
| 5004 | kmem_cache_create("i915_gem_object", |
| 5005 | sizeof(struct drm_i915_gem_object), 0, |
| 5006 | SLAB_HWCACHE_ALIGN, |
| 5007 | NULL); |
| 5008 | dev_priv->vmas = |
| 5009 | kmem_cache_create("i915_gem_vma", |
| 5010 | sizeof(struct i915_vma), 0, |
| 5011 | SLAB_HWCACHE_ALIGN, |
| 5012 | NULL); |
| 5013 | dev_priv->requests = |
| 5014 | kmem_cache_create("i915_gem_request", |
| 5015 | sizeof(struct drm_i915_gem_request), 0, |
| 5016 | SLAB_HWCACHE_ALIGN, |
| 5017 | NULL); |
| 5018 | |
| 5019 | INIT_LIST_HEAD(&dev_priv->vm_list); |
| 5020 | INIT_LIST_HEAD(&dev_priv->context_list); |
| 5021 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
| 5022 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); |
| 5023 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
| 5024 | for (i = 0; i < I915_NUM_ENGINES; i++) |
| 5025 | init_engine_lists(&dev_priv->engine[i]); |
| 5026 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
| 5027 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
| 5028 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
| 5029 | i915_gem_retire_work_handler); |
| 5030 | INIT_DELAYED_WORK(&dev_priv->mm.idle_work, |
| 5031 | i915_gem_idle_work_handler); |
| 5032 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
| 5033 | |
| 5034 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
| 5035 | |
| 5036 | /* |
| 5037 | * Set initial sequence number for requests. |
| 5038 | * Using this number allows the wraparound to happen early, |
| 5039 | * catching any obvious problems. |
| 5040 | */ |
| 5041 | dev_priv->next_seqno = ((u32)~0 - 0x1100); |
| 5042 | dev_priv->last_seqno = ((u32)~0 - 0x1101); |
| 5043 | |
| 5044 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
| 5045 | |
| 5046 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
| 5047 | |
| 5048 | dev_priv->mm.interruptible = true; |
| 5049 | |
| 5050 | mutex_init(&dev_priv->fb_tracking.lock); |
| 5051 | } |
| 5052 | |
| 5053 | void i915_gem_load_cleanup(struct drm_device *dev) |
| 5054 | { |
| 5055 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 5056 | |
| 5057 | kmem_cache_destroy(dev_priv->requests); |
| 5058 | kmem_cache_destroy(dev_priv->vmas); |
| 5059 | kmem_cache_destroy(dev_priv->objects); |
| 5060 | } |
| 5061 | |
| 5062 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
| 5063 | { |
| 5064 | struct drm_i915_file_private *file_priv = file->driver_priv; |
| 5065 | |
| 5066 | /* Clean up our request list when the client is going away, so that |
| 5067 | * later retire_requests won't dereference our soon-to-be-gone |
| 5068 | * file_priv. |
| 5069 | */ |
| 5070 | spin_lock(&file_priv->mm.lock); |
| 5071 | while (!list_empty(&file_priv->mm.request_list)) { |
| 5072 | struct drm_i915_gem_request *request; |
| 5073 | |
| 5074 | request = list_first_entry(&file_priv->mm.request_list, |
| 5075 | struct drm_i915_gem_request, |
| 5076 | client_list); |
| 5077 | list_del(&request->client_list); |
| 5078 | request->file_priv = NULL; |
| 5079 | } |
| 5080 | spin_unlock(&file_priv->mm.lock); |
| 5081 | |
| 5082 | if (!list_empty(&file_priv->rps.link)) { |
| 5083 | spin_lock(&to_i915(dev)->rps.client_lock); |
| 5084 | list_del(&file_priv->rps.link); |
| 5085 | spin_unlock(&to_i915(dev)->rps.client_lock); |
| 5086 | } |
| 5087 | } |
| 5088 | |
| 5089 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) |
| 5090 | { |
| 5091 | struct drm_i915_file_private *file_priv; |
| 5092 | int ret; |
| 5093 | |
| 5094 | DRM_DEBUG_DRIVER("\n"); |
| 5095 | |
| 5096 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); |
| 5097 | if (!file_priv) |
| 5098 | return -ENOMEM; |
| 5099 | |
| 5100 | file->driver_priv = file_priv; |
| 5101 | file_priv->dev_priv = dev->dev_private; |
| 5102 | file_priv->file = file; |
| 5103 | INIT_LIST_HEAD(&file_priv->rps.link); |
| 5104 | |
| 5105 | spin_lock_init(&file_priv->mm.lock); |
| 5106 | INIT_LIST_HEAD(&file_priv->mm.request_list); |
| 5107 | |
| 5108 | file_priv->bsd_ring = -1; |
| 5109 | |
| 5110 | ret = i915_gem_context_open(dev, file); |
| 5111 | if (ret) |
| 5112 | kfree(file_priv); |
| 5113 | |
| 5114 | return ret; |
| 5115 | } |
| 5116 | |
| 5117 | /** |
| 5118 | * i915_gem_track_fb - update frontbuffer tracking |
| 5119 | * @old: current GEM buffer for the frontbuffer slots |
| 5120 | * @new: new GEM buffer for the frontbuffer slots |
| 5121 | * @frontbuffer_bits: bitmask of frontbuffer slots |
| 5122 | * |
| 5123 | * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them |
| 5124 | * from @old and setting them in @new. Both @old and @new can be NULL. |
| 5125 | */ |
| 5126 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
| 5127 | struct drm_i915_gem_object *new, |
| 5128 | unsigned frontbuffer_bits) |
| 5129 | { |
| 5130 | if (old) { |
| 5131 | WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex)); |
| 5132 | WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits)); |
| 5133 | old->frontbuffer_bits &= ~frontbuffer_bits; |
| 5134 | } |
| 5135 | |
| 5136 | if (new) { |
| 5137 | WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex)); |
| 5138 | WARN_ON(new->frontbuffer_bits & frontbuffer_bits); |
| 5139 | new->frontbuffer_bits |= frontbuffer_bits; |
| 5140 | } |
| 5141 | } |
| 5142 | |
| 5143 | /* All the new VM stuff */ |
| 5144 | u64 i915_gem_obj_offset(struct drm_i915_gem_object *o, |
| 5145 | struct i915_address_space *vm) |
| 5146 | { |
| 5147 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; |
| 5148 | struct i915_vma *vma; |
| 5149 | |
| 5150 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
| 5151 | |
| 5152 | list_for_each_entry(vma, &o->vma_list, obj_link) { |
| 5153 | if (vma->is_ggtt && |
| 5154 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) |
| 5155 | continue; |
| 5156 | if (vma->vm == vm) |
| 5157 | return vma->node.start; |
| 5158 | } |
| 5159 | |
| 5160 | WARN(1, "%s vma for this object not found.\n", |
| 5161 | i915_is_ggtt(vm) ? "global" : "ppgtt"); |
| 5162 | return -1; |
| 5163 | } |
| 5164 | |
| 5165 | u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o, |
| 5166 | const struct i915_ggtt_view *view) |
| 5167 | { |
| 5168 | struct i915_vma *vma; |
| 5169 | |
| 5170 | list_for_each_entry(vma, &o->vma_list, obj_link) |
| 5171 | if (vma->is_ggtt && i915_ggtt_view_equal(&vma->ggtt_view, view)) |
| 5172 | return vma->node.start; |
| 5173 | |
| 5174 | WARN(1, "global vma for this object not found. (view=%u)\n", view->type); |
| 5175 | return -1; |
| 5176 | } |
| 5177 | |
| 5178 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, |
| 5179 | struct i915_address_space *vm) |
| 5180 | { |
| 5181 | struct i915_vma *vma; |
| 5182 | |
| 5183 | list_for_each_entry(vma, &o->vma_list, obj_link) { |
| 5184 | if (vma->is_ggtt && |
| 5185 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) |
| 5186 | continue; |
| 5187 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) |
| 5188 | return true; |
| 5189 | } |
| 5190 | |
| 5191 | return false; |
| 5192 | } |
| 5193 | |
| 5194 | bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o, |
| 5195 | const struct i915_ggtt_view *view) |
| 5196 | { |
| 5197 | struct i915_vma *vma; |
| 5198 | |
| 5199 | list_for_each_entry(vma, &o->vma_list, obj_link) |
| 5200 | if (vma->is_ggtt && |
| 5201 | i915_ggtt_view_equal(&vma->ggtt_view, view) && |
| 5202 | drm_mm_node_allocated(&vma->node)) |
| 5203 | return true; |
| 5204 | |
| 5205 | return false; |
| 5206 | } |
| 5207 | |
| 5208 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) |
| 5209 | { |
| 5210 | struct i915_vma *vma; |
| 5211 | |
| 5212 | list_for_each_entry(vma, &o->vma_list, obj_link) |
| 5213 | if (drm_mm_node_allocated(&vma->node)) |
| 5214 | return true; |
| 5215 | |
| 5216 | return false; |
| 5217 | } |
| 5218 | |
| 5219 | unsigned long i915_gem_obj_ggtt_size(struct drm_i915_gem_object *o) |
| 5220 | { |
| 5221 | struct i915_vma *vma; |
| 5222 | |
| 5223 | GEM_BUG_ON(list_empty(&o->vma_list)); |
| 5224 | |
| 5225 | list_for_each_entry(vma, &o->vma_list, obj_link) { |
| 5226 | if (vma->is_ggtt && |
| 5227 | vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) |
| 5228 | return vma->node.size; |
| 5229 | } |
| 5230 | |
| 5231 | return 0; |
| 5232 | } |
| 5233 | |
| 5234 | bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) |
| 5235 | { |
| 5236 | struct i915_vma *vma; |
| 5237 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
| 5238 | if (vma->pin_count > 0) |
| 5239 | return true; |
| 5240 | |
| 5241 | return false; |
| 5242 | } |
| 5243 | |
| 5244 | /* Like i915_gem_object_get_page(), but mark the returned page dirty */ |
| 5245 | struct page * |
| 5246 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n) |
| 5247 | { |
| 5248 | struct page *page; |
| 5249 | |
| 5250 | /* Only default objects have per-page dirty tracking */ |
| 5251 | if (WARN_ON((obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE) == 0)) |
| 5252 | return NULL; |
| 5253 | |
| 5254 | page = i915_gem_object_get_page(obj, n); |
| 5255 | set_page_dirty(page); |
| 5256 | return page; |
| 5257 | } |
| 5258 | |
| 5259 | /* Allocate a new GEM object and fill it with the supplied data */ |
| 5260 | struct drm_i915_gem_object * |
| 5261 | i915_gem_object_create_from_data(struct drm_device *dev, |
| 5262 | const void *data, size_t size) |
| 5263 | { |
| 5264 | struct drm_i915_gem_object *obj; |
| 5265 | struct sg_table *sg; |
| 5266 | size_t bytes; |
| 5267 | int ret; |
| 5268 | |
| 5269 | obj = i915_gem_object_create(dev, round_up(size, PAGE_SIZE)); |
| 5270 | if (IS_ERR(obj)) |
| 5271 | return obj; |
| 5272 | |
| 5273 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
| 5274 | if (ret) |
| 5275 | goto fail; |
| 5276 | |
| 5277 | ret = i915_gem_object_get_pages(obj); |
| 5278 | if (ret) |
| 5279 | goto fail; |
| 5280 | |
| 5281 | i915_gem_object_pin_pages(obj); |
| 5282 | sg = obj->pages; |
| 5283 | bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size); |
| 5284 | obj->dirty = 1; /* Backing store is now out of date */ |
| 5285 | i915_gem_object_unpin_pages(obj); |
| 5286 | |
| 5287 | if (WARN_ON(bytes != size)) { |
| 5288 | DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size); |
| 5289 | ret = -EFAULT; |
| 5290 | goto fail; |
| 5291 | } |
| 5292 | |
| 5293 | return obj; |
| 5294 | |
| 5295 | fail: |
| 5296 | drm_gem_object_unreference(&obj->base); |
| 5297 | return ERR_PTR(ret); |
| 5298 | } |