| 1 | /* |
| 2 | * Copyright © 2006-2007 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 21 | * DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | */ |
| 26 | |
| 27 | #include <linux/dmi.h> |
| 28 | #include <linux/module.h> |
| 29 | #include <linux/input.h> |
| 30 | #include <linux/i2c.h> |
| 31 | #include <linux/kernel.h> |
| 32 | #include <linux/slab.h> |
| 33 | #include <linux/vgaarb.h> |
| 34 | #include <drm/drm_edid.h> |
| 35 | #include <drm/drmP.h> |
| 36 | #include "intel_drv.h" |
| 37 | #include <drm/i915_drm.h> |
| 38 | #include "i915_drv.h" |
| 39 | #include "i915_trace.h" |
| 40 | #include <drm/drm_atomic.h> |
| 41 | #include <drm/drm_atomic_helper.h> |
| 42 | #include <drm/drm_dp_helper.h> |
| 43 | #include <drm/drm_crtc_helper.h> |
| 44 | #include <drm/drm_plane_helper.h> |
| 45 | #include <drm/drm_rect.h> |
| 46 | #include <linux/dma_remapping.h> |
| 47 | #include <linux/reservation.h> |
| 48 | #include <linux/dma-buf.h> |
| 49 | |
| 50 | /* Primary plane formats for gen <= 3 */ |
| 51 | static const uint32_t i8xx_primary_formats[] = { |
| 52 | DRM_FORMAT_C8, |
| 53 | DRM_FORMAT_RGB565, |
| 54 | DRM_FORMAT_XRGB1555, |
| 55 | DRM_FORMAT_XRGB8888, |
| 56 | }; |
| 57 | |
| 58 | /* Primary plane formats for gen >= 4 */ |
| 59 | static const uint32_t i965_primary_formats[] = { |
| 60 | DRM_FORMAT_C8, |
| 61 | DRM_FORMAT_RGB565, |
| 62 | DRM_FORMAT_XRGB8888, |
| 63 | DRM_FORMAT_XBGR8888, |
| 64 | DRM_FORMAT_XRGB2101010, |
| 65 | DRM_FORMAT_XBGR2101010, |
| 66 | }; |
| 67 | |
| 68 | static const uint32_t skl_primary_formats[] = { |
| 69 | DRM_FORMAT_C8, |
| 70 | DRM_FORMAT_RGB565, |
| 71 | DRM_FORMAT_XRGB8888, |
| 72 | DRM_FORMAT_XBGR8888, |
| 73 | DRM_FORMAT_ARGB8888, |
| 74 | DRM_FORMAT_ABGR8888, |
| 75 | DRM_FORMAT_XRGB2101010, |
| 76 | DRM_FORMAT_XBGR2101010, |
| 77 | DRM_FORMAT_YUYV, |
| 78 | DRM_FORMAT_YVYU, |
| 79 | DRM_FORMAT_UYVY, |
| 80 | DRM_FORMAT_VYUY, |
| 81 | }; |
| 82 | |
| 83 | /* Cursor formats */ |
| 84 | static const uint32_t intel_cursor_formats[] = { |
| 85 | DRM_FORMAT_ARGB8888, |
| 86 | }; |
| 87 | |
| 88 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
| 89 | struct intel_crtc_state *pipe_config); |
| 90 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
| 91 | struct intel_crtc_state *pipe_config); |
| 92 | |
| 93 | static int intel_framebuffer_init(struct drm_device *dev, |
| 94 | struct intel_framebuffer *ifb, |
| 95 | struct drm_mode_fb_cmd2 *mode_cmd, |
| 96 | struct drm_i915_gem_object *obj); |
| 97 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
| 98 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); |
| 99 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
| 100 | struct intel_link_m_n *m_n, |
| 101 | struct intel_link_m_n *m2_n2); |
| 102 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
| 103 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
| 104 | static void intel_set_pipe_csc(struct drm_crtc *crtc); |
| 105 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
| 106 | const struct intel_crtc_state *pipe_config); |
| 107 | static void chv_prepare_pll(struct intel_crtc *crtc, |
| 108 | const struct intel_crtc_state *pipe_config); |
| 109 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
| 110 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
| 111 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
| 112 | struct intel_crtc_state *crtc_state); |
| 113 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
| 114 | int num_connectors); |
| 115 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
| 116 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); |
| 117 | static void ironlake_pfit_enable(struct intel_crtc *crtc); |
| 118 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
| 119 | static void intel_pre_disable_primary(struct drm_crtc *crtc); |
| 120 | |
| 121 | typedef struct { |
| 122 | int min, max; |
| 123 | } intel_range_t; |
| 124 | |
| 125 | typedef struct { |
| 126 | int dot_limit; |
| 127 | int p2_slow, p2_fast; |
| 128 | } intel_p2_t; |
| 129 | |
| 130 | typedef struct intel_limit intel_limit_t; |
| 131 | struct intel_limit { |
| 132 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
| 133 | intel_p2_t p2; |
| 134 | }; |
| 135 | |
| 136 | /* returns HPLL frequency in kHz */ |
| 137 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) |
| 138 | { |
| 139 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
| 140 | |
| 141 | /* Obtain SKU information */ |
| 142 | mutex_lock(&dev_priv->sb_lock); |
| 143 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & |
| 144 | CCK_FUSE_HPLL_FREQ_MASK; |
| 145 | mutex_unlock(&dev_priv->sb_lock); |
| 146 | |
| 147 | return vco_freq[hpll_freq] * 1000; |
| 148 | } |
| 149 | |
| 150 | static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, |
| 151 | const char *name, u32 reg) |
| 152 | { |
| 153 | u32 val; |
| 154 | int divider; |
| 155 | |
| 156 | if (dev_priv->hpll_freq == 0) |
| 157 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); |
| 158 | |
| 159 | mutex_lock(&dev_priv->sb_lock); |
| 160 | val = vlv_cck_read(dev_priv, reg); |
| 161 | mutex_unlock(&dev_priv->sb_lock); |
| 162 | |
| 163 | divider = val & CCK_FREQUENCY_VALUES; |
| 164 | |
| 165 | WARN((val & CCK_FREQUENCY_STATUS) != |
| 166 | (divider << CCK_FREQUENCY_STATUS_SHIFT), |
| 167 | "%s change in progress\n", name); |
| 168 | |
| 169 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); |
| 170 | } |
| 171 | |
| 172 | int |
| 173 | intel_pch_rawclk(struct drm_device *dev) |
| 174 | { |
| 175 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 176 | |
| 177 | WARN_ON(!HAS_PCH_SPLIT(dev)); |
| 178 | |
| 179 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; |
| 180 | } |
| 181 | |
| 182 | /* hrawclock is 1/4 the FSB frequency */ |
| 183 | int intel_hrawclk(struct drm_device *dev) |
| 184 | { |
| 185 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 186 | uint32_t clkcfg; |
| 187 | |
| 188 | /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ |
| 189 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
| 190 | return 200; |
| 191 | |
| 192 | clkcfg = I915_READ(CLKCFG); |
| 193 | switch (clkcfg & CLKCFG_FSB_MASK) { |
| 194 | case CLKCFG_FSB_400: |
| 195 | return 100; |
| 196 | case CLKCFG_FSB_533: |
| 197 | return 133; |
| 198 | case CLKCFG_FSB_667: |
| 199 | return 166; |
| 200 | case CLKCFG_FSB_800: |
| 201 | return 200; |
| 202 | case CLKCFG_FSB_1067: |
| 203 | return 266; |
| 204 | case CLKCFG_FSB_1333: |
| 205 | return 333; |
| 206 | /* these two are just a guess; one of them might be right */ |
| 207 | case CLKCFG_FSB_1600: |
| 208 | case CLKCFG_FSB_1600_ALT: |
| 209 | return 400; |
| 210 | default: |
| 211 | return 133; |
| 212 | } |
| 213 | } |
| 214 | |
| 215 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
| 216 | { |
| 217 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
| 218 | return; |
| 219 | |
| 220 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", |
| 221 | CCK_CZ_CLOCK_CONTROL); |
| 222 | |
| 223 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); |
| 224 | } |
| 225 | |
| 226 | static inline u32 /* units of 100MHz */ |
| 227 | intel_fdi_link_freq(struct drm_device *dev) |
| 228 | { |
| 229 | if (IS_GEN5(dev)) { |
| 230 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 231 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; |
| 232 | } else |
| 233 | return 27; |
| 234 | } |
| 235 | |
| 236 | static const intel_limit_t intel_limits_i8xx_dac = { |
| 237 | .dot = { .min = 25000, .max = 350000 }, |
| 238 | .vco = { .min = 908000, .max = 1512000 }, |
| 239 | .n = { .min = 2, .max = 16 }, |
| 240 | .m = { .min = 96, .max = 140 }, |
| 241 | .m1 = { .min = 18, .max = 26 }, |
| 242 | .m2 = { .min = 6, .max = 16 }, |
| 243 | .p = { .min = 4, .max = 128 }, |
| 244 | .p1 = { .min = 2, .max = 33 }, |
| 245 | .p2 = { .dot_limit = 165000, |
| 246 | .p2_slow = 4, .p2_fast = 2 }, |
| 247 | }; |
| 248 | |
| 249 | static const intel_limit_t intel_limits_i8xx_dvo = { |
| 250 | .dot = { .min = 25000, .max = 350000 }, |
| 251 | .vco = { .min = 908000, .max = 1512000 }, |
| 252 | .n = { .min = 2, .max = 16 }, |
| 253 | .m = { .min = 96, .max = 140 }, |
| 254 | .m1 = { .min = 18, .max = 26 }, |
| 255 | .m2 = { .min = 6, .max = 16 }, |
| 256 | .p = { .min = 4, .max = 128 }, |
| 257 | .p1 = { .min = 2, .max = 33 }, |
| 258 | .p2 = { .dot_limit = 165000, |
| 259 | .p2_slow = 4, .p2_fast = 4 }, |
| 260 | }; |
| 261 | |
| 262 | static const intel_limit_t intel_limits_i8xx_lvds = { |
| 263 | .dot = { .min = 25000, .max = 350000 }, |
| 264 | .vco = { .min = 908000, .max = 1512000 }, |
| 265 | .n = { .min = 2, .max = 16 }, |
| 266 | .m = { .min = 96, .max = 140 }, |
| 267 | .m1 = { .min = 18, .max = 26 }, |
| 268 | .m2 = { .min = 6, .max = 16 }, |
| 269 | .p = { .min = 4, .max = 128 }, |
| 270 | .p1 = { .min = 1, .max = 6 }, |
| 271 | .p2 = { .dot_limit = 165000, |
| 272 | .p2_slow = 14, .p2_fast = 7 }, |
| 273 | }; |
| 274 | |
| 275 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
| 276 | .dot = { .min = 20000, .max = 400000 }, |
| 277 | .vco = { .min = 1400000, .max = 2800000 }, |
| 278 | .n = { .min = 1, .max = 6 }, |
| 279 | .m = { .min = 70, .max = 120 }, |
| 280 | .m1 = { .min = 8, .max = 18 }, |
| 281 | .m2 = { .min = 3, .max = 7 }, |
| 282 | .p = { .min = 5, .max = 80 }, |
| 283 | .p1 = { .min = 1, .max = 8 }, |
| 284 | .p2 = { .dot_limit = 200000, |
| 285 | .p2_slow = 10, .p2_fast = 5 }, |
| 286 | }; |
| 287 | |
| 288 | static const intel_limit_t intel_limits_i9xx_lvds = { |
| 289 | .dot = { .min = 20000, .max = 400000 }, |
| 290 | .vco = { .min = 1400000, .max = 2800000 }, |
| 291 | .n = { .min = 1, .max = 6 }, |
| 292 | .m = { .min = 70, .max = 120 }, |
| 293 | .m1 = { .min = 8, .max = 18 }, |
| 294 | .m2 = { .min = 3, .max = 7 }, |
| 295 | .p = { .min = 7, .max = 98 }, |
| 296 | .p1 = { .min = 1, .max = 8 }, |
| 297 | .p2 = { .dot_limit = 112000, |
| 298 | .p2_slow = 14, .p2_fast = 7 }, |
| 299 | }; |
| 300 | |
| 301 | |
| 302 | static const intel_limit_t intel_limits_g4x_sdvo = { |
| 303 | .dot = { .min = 25000, .max = 270000 }, |
| 304 | .vco = { .min = 1750000, .max = 3500000}, |
| 305 | .n = { .min = 1, .max = 4 }, |
| 306 | .m = { .min = 104, .max = 138 }, |
| 307 | .m1 = { .min = 17, .max = 23 }, |
| 308 | .m2 = { .min = 5, .max = 11 }, |
| 309 | .p = { .min = 10, .max = 30 }, |
| 310 | .p1 = { .min = 1, .max = 3}, |
| 311 | .p2 = { .dot_limit = 270000, |
| 312 | .p2_slow = 10, |
| 313 | .p2_fast = 10 |
| 314 | }, |
| 315 | }; |
| 316 | |
| 317 | static const intel_limit_t intel_limits_g4x_hdmi = { |
| 318 | .dot = { .min = 22000, .max = 400000 }, |
| 319 | .vco = { .min = 1750000, .max = 3500000}, |
| 320 | .n = { .min = 1, .max = 4 }, |
| 321 | .m = { .min = 104, .max = 138 }, |
| 322 | .m1 = { .min = 16, .max = 23 }, |
| 323 | .m2 = { .min = 5, .max = 11 }, |
| 324 | .p = { .min = 5, .max = 80 }, |
| 325 | .p1 = { .min = 1, .max = 8}, |
| 326 | .p2 = { .dot_limit = 165000, |
| 327 | .p2_slow = 10, .p2_fast = 5 }, |
| 328 | }; |
| 329 | |
| 330 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { |
| 331 | .dot = { .min = 20000, .max = 115000 }, |
| 332 | .vco = { .min = 1750000, .max = 3500000 }, |
| 333 | .n = { .min = 1, .max = 3 }, |
| 334 | .m = { .min = 104, .max = 138 }, |
| 335 | .m1 = { .min = 17, .max = 23 }, |
| 336 | .m2 = { .min = 5, .max = 11 }, |
| 337 | .p = { .min = 28, .max = 112 }, |
| 338 | .p1 = { .min = 2, .max = 8 }, |
| 339 | .p2 = { .dot_limit = 0, |
| 340 | .p2_slow = 14, .p2_fast = 14 |
| 341 | }, |
| 342 | }; |
| 343 | |
| 344 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { |
| 345 | .dot = { .min = 80000, .max = 224000 }, |
| 346 | .vco = { .min = 1750000, .max = 3500000 }, |
| 347 | .n = { .min = 1, .max = 3 }, |
| 348 | .m = { .min = 104, .max = 138 }, |
| 349 | .m1 = { .min = 17, .max = 23 }, |
| 350 | .m2 = { .min = 5, .max = 11 }, |
| 351 | .p = { .min = 14, .max = 42 }, |
| 352 | .p1 = { .min = 2, .max = 6 }, |
| 353 | .p2 = { .dot_limit = 0, |
| 354 | .p2_slow = 7, .p2_fast = 7 |
| 355 | }, |
| 356 | }; |
| 357 | |
| 358 | static const intel_limit_t intel_limits_pineview_sdvo = { |
| 359 | .dot = { .min = 20000, .max = 400000}, |
| 360 | .vco = { .min = 1700000, .max = 3500000 }, |
| 361 | /* Pineview's Ncounter is a ring counter */ |
| 362 | .n = { .min = 3, .max = 6 }, |
| 363 | .m = { .min = 2, .max = 256 }, |
| 364 | /* Pineview only has one combined m divider, which we treat as m2. */ |
| 365 | .m1 = { .min = 0, .max = 0 }, |
| 366 | .m2 = { .min = 0, .max = 254 }, |
| 367 | .p = { .min = 5, .max = 80 }, |
| 368 | .p1 = { .min = 1, .max = 8 }, |
| 369 | .p2 = { .dot_limit = 200000, |
| 370 | .p2_slow = 10, .p2_fast = 5 }, |
| 371 | }; |
| 372 | |
| 373 | static const intel_limit_t intel_limits_pineview_lvds = { |
| 374 | .dot = { .min = 20000, .max = 400000 }, |
| 375 | .vco = { .min = 1700000, .max = 3500000 }, |
| 376 | .n = { .min = 3, .max = 6 }, |
| 377 | .m = { .min = 2, .max = 256 }, |
| 378 | .m1 = { .min = 0, .max = 0 }, |
| 379 | .m2 = { .min = 0, .max = 254 }, |
| 380 | .p = { .min = 7, .max = 112 }, |
| 381 | .p1 = { .min = 1, .max = 8 }, |
| 382 | .p2 = { .dot_limit = 112000, |
| 383 | .p2_slow = 14, .p2_fast = 14 }, |
| 384 | }; |
| 385 | |
| 386 | /* Ironlake / Sandybridge |
| 387 | * |
| 388 | * We calculate clock using (register_value + 2) for N/M1/M2, so here |
| 389 | * the range value for them is (actual_value - 2). |
| 390 | */ |
| 391 | static const intel_limit_t intel_limits_ironlake_dac = { |
| 392 | .dot = { .min = 25000, .max = 350000 }, |
| 393 | .vco = { .min = 1760000, .max = 3510000 }, |
| 394 | .n = { .min = 1, .max = 5 }, |
| 395 | .m = { .min = 79, .max = 127 }, |
| 396 | .m1 = { .min = 12, .max = 22 }, |
| 397 | .m2 = { .min = 5, .max = 9 }, |
| 398 | .p = { .min = 5, .max = 80 }, |
| 399 | .p1 = { .min = 1, .max = 8 }, |
| 400 | .p2 = { .dot_limit = 225000, |
| 401 | .p2_slow = 10, .p2_fast = 5 }, |
| 402 | }; |
| 403 | |
| 404 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
| 405 | .dot = { .min = 25000, .max = 350000 }, |
| 406 | .vco = { .min = 1760000, .max = 3510000 }, |
| 407 | .n = { .min = 1, .max = 3 }, |
| 408 | .m = { .min = 79, .max = 118 }, |
| 409 | .m1 = { .min = 12, .max = 22 }, |
| 410 | .m2 = { .min = 5, .max = 9 }, |
| 411 | .p = { .min = 28, .max = 112 }, |
| 412 | .p1 = { .min = 2, .max = 8 }, |
| 413 | .p2 = { .dot_limit = 225000, |
| 414 | .p2_slow = 14, .p2_fast = 14 }, |
| 415 | }; |
| 416 | |
| 417 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { |
| 418 | .dot = { .min = 25000, .max = 350000 }, |
| 419 | .vco = { .min = 1760000, .max = 3510000 }, |
| 420 | .n = { .min = 1, .max = 3 }, |
| 421 | .m = { .min = 79, .max = 127 }, |
| 422 | .m1 = { .min = 12, .max = 22 }, |
| 423 | .m2 = { .min = 5, .max = 9 }, |
| 424 | .p = { .min = 14, .max = 56 }, |
| 425 | .p1 = { .min = 2, .max = 8 }, |
| 426 | .p2 = { .dot_limit = 225000, |
| 427 | .p2_slow = 7, .p2_fast = 7 }, |
| 428 | }; |
| 429 | |
| 430 | /* LVDS 100mhz refclk limits. */ |
| 431 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
| 432 | .dot = { .min = 25000, .max = 350000 }, |
| 433 | .vco = { .min = 1760000, .max = 3510000 }, |
| 434 | .n = { .min = 1, .max = 2 }, |
| 435 | .m = { .min = 79, .max = 126 }, |
| 436 | .m1 = { .min = 12, .max = 22 }, |
| 437 | .m2 = { .min = 5, .max = 9 }, |
| 438 | .p = { .min = 28, .max = 112 }, |
| 439 | .p1 = { .min = 2, .max = 8 }, |
| 440 | .p2 = { .dot_limit = 225000, |
| 441 | .p2_slow = 14, .p2_fast = 14 }, |
| 442 | }; |
| 443 | |
| 444 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { |
| 445 | .dot = { .min = 25000, .max = 350000 }, |
| 446 | .vco = { .min = 1760000, .max = 3510000 }, |
| 447 | .n = { .min = 1, .max = 3 }, |
| 448 | .m = { .min = 79, .max = 126 }, |
| 449 | .m1 = { .min = 12, .max = 22 }, |
| 450 | .m2 = { .min = 5, .max = 9 }, |
| 451 | .p = { .min = 14, .max = 42 }, |
| 452 | .p1 = { .min = 2, .max = 6 }, |
| 453 | .p2 = { .dot_limit = 225000, |
| 454 | .p2_slow = 7, .p2_fast = 7 }, |
| 455 | }; |
| 456 | |
| 457 | static const intel_limit_t intel_limits_vlv = { |
| 458 | /* |
| 459 | * These are the data rate limits (measured in fast clocks) |
| 460 | * since those are the strictest limits we have. The fast |
| 461 | * clock and actual rate limits are more relaxed, so checking |
| 462 | * them would make no difference. |
| 463 | */ |
| 464 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, |
| 465 | .vco = { .min = 4000000, .max = 6000000 }, |
| 466 | .n = { .min = 1, .max = 7 }, |
| 467 | .m1 = { .min = 2, .max = 3 }, |
| 468 | .m2 = { .min = 11, .max = 156 }, |
| 469 | .p1 = { .min = 2, .max = 3 }, |
| 470 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
| 471 | }; |
| 472 | |
| 473 | static const intel_limit_t intel_limits_chv = { |
| 474 | /* |
| 475 | * These are the data rate limits (measured in fast clocks) |
| 476 | * since those are the strictest limits we have. The fast |
| 477 | * clock and actual rate limits are more relaxed, so checking |
| 478 | * them would make no difference. |
| 479 | */ |
| 480 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, |
| 481 | .vco = { .min = 4800000, .max = 6480000 }, |
| 482 | .n = { .min = 1, .max = 1 }, |
| 483 | .m1 = { .min = 2, .max = 2 }, |
| 484 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, |
| 485 | .p1 = { .min = 2, .max = 4 }, |
| 486 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, |
| 487 | }; |
| 488 | |
| 489 | static const intel_limit_t intel_limits_bxt = { |
| 490 | /* FIXME: find real dot limits */ |
| 491 | .dot = { .min = 0, .max = INT_MAX }, |
| 492 | .vco = { .min = 4800000, .max = 6700000 }, |
| 493 | .n = { .min = 1, .max = 1 }, |
| 494 | .m1 = { .min = 2, .max = 2 }, |
| 495 | /* FIXME: find real m2 limits */ |
| 496 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, |
| 497 | .p1 = { .min = 2, .max = 4 }, |
| 498 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, |
| 499 | }; |
| 500 | |
| 501 | static bool |
| 502 | needs_modeset(struct drm_crtc_state *state) |
| 503 | { |
| 504 | return drm_atomic_crtc_needs_modeset(state); |
| 505 | } |
| 506 | |
| 507 | /** |
| 508 | * Returns whether any output on the specified pipe is of the specified type |
| 509 | */ |
| 510 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
| 511 | { |
| 512 | struct drm_device *dev = crtc->base.dev; |
| 513 | struct intel_encoder *encoder; |
| 514 | |
| 515 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
| 516 | if (encoder->type == type) |
| 517 | return true; |
| 518 | |
| 519 | return false; |
| 520 | } |
| 521 | |
| 522 | /** |
| 523 | * Returns whether any output on the specified pipe will have the specified |
| 524 | * type after a staged modeset is complete, i.e., the same as |
| 525 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of |
| 526 | * encoder->crtc. |
| 527 | */ |
| 528 | static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, |
| 529 | int type) |
| 530 | { |
| 531 | struct drm_atomic_state *state = crtc_state->base.state; |
| 532 | struct drm_connector *connector; |
| 533 | struct drm_connector_state *connector_state; |
| 534 | struct intel_encoder *encoder; |
| 535 | int i, num_connectors = 0; |
| 536 | |
| 537 | for_each_connector_in_state(state, connector, connector_state, i) { |
| 538 | if (connector_state->crtc != crtc_state->base.crtc) |
| 539 | continue; |
| 540 | |
| 541 | num_connectors++; |
| 542 | |
| 543 | encoder = to_intel_encoder(connector_state->best_encoder); |
| 544 | if (encoder->type == type) |
| 545 | return true; |
| 546 | } |
| 547 | |
| 548 | WARN_ON(num_connectors == 0); |
| 549 | |
| 550 | return false; |
| 551 | } |
| 552 | |
| 553 | static const intel_limit_t * |
| 554 | intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk) |
| 555 | { |
| 556 | struct drm_device *dev = crtc_state->base.crtc->dev; |
| 557 | const intel_limit_t *limit; |
| 558 | |
| 559 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
| 560 | if (intel_is_dual_link_lvds(dev)) { |
| 561 | if (refclk == 100000) |
| 562 | limit = &intel_limits_ironlake_dual_lvds_100m; |
| 563 | else |
| 564 | limit = &intel_limits_ironlake_dual_lvds; |
| 565 | } else { |
| 566 | if (refclk == 100000) |
| 567 | limit = &intel_limits_ironlake_single_lvds_100m; |
| 568 | else |
| 569 | limit = &intel_limits_ironlake_single_lvds; |
| 570 | } |
| 571 | } else |
| 572 | limit = &intel_limits_ironlake_dac; |
| 573 | |
| 574 | return limit; |
| 575 | } |
| 576 | |
| 577 | static const intel_limit_t * |
| 578 | intel_g4x_limit(struct intel_crtc_state *crtc_state) |
| 579 | { |
| 580 | struct drm_device *dev = crtc_state->base.crtc->dev; |
| 581 | const intel_limit_t *limit; |
| 582 | |
| 583 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
| 584 | if (intel_is_dual_link_lvds(dev)) |
| 585 | limit = &intel_limits_g4x_dual_channel_lvds; |
| 586 | else |
| 587 | limit = &intel_limits_g4x_single_channel_lvds; |
| 588 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || |
| 589 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { |
| 590 | limit = &intel_limits_g4x_hdmi; |
| 591 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
| 592 | limit = &intel_limits_g4x_sdvo; |
| 593 | } else /* The option is for other outputs */ |
| 594 | limit = &intel_limits_i9xx_sdvo; |
| 595 | |
| 596 | return limit; |
| 597 | } |
| 598 | |
| 599 | static const intel_limit_t * |
| 600 | intel_limit(struct intel_crtc_state *crtc_state, int refclk) |
| 601 | { |
| 602 | struct drm_device *dev = crtc_state->base.crtc->dev; |
| 603 | const intel_limit_t *limit; |
| 604 | |
| 605 | if (IS_BROXTON(dev)) |
| 606 | limit = &intel_limits_bxt; |
| 607 | else if (HAS_PCH_SPLIT(dev)) |
| 608 | limit = intel_ironlake_limit(crtc_state, refclk); |
| 609 | else if (IS_G4X(dev)) { |
| 610 | limit = intel_g4x_limit(crtc_state); |
| 611 | } else if (IS_PINEVIEW(dev)) { |
| 612 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
| 613 | limit = &intel_limits_pineview_lvds; |
| 614 | else |
| 615 | limit = &intel_limits_pineview_sdvo; |
| 616 | } else if (IS_CHERRYVIEW(dev)) { |
| 617 | limit = &intel_limits_chv; |
| 618 | } else if (IS_VALLEYVIEW(dev)) { |
| 619 | limit = &intel_limits_vlv; |
| 620 | } else if (!IS_GEN2(dev)) { |
| 621 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
| 622 | limit = &intel_limits_i9xx_lvds; |
| 623 | else |
| 624 | limit = &intel_limits_i9xx_sdvo; |
| 625 | } else { |
| 626 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
| 627 | limit = &intel_limits_i8xx_lvds; |
| 628 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
| 629 | limit = &intel_limits_i8xx_dvo; |
| 630 | else |
| 631 | limit = &intel_limits_i8xx_dac; |
| 632 | } |
| 633 | return limit; |
| 634 | } |
| 635 | |
| 636 | /* |
| 637 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), |
| 638 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast |
| 639 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. |
| 640 | * The helpers' return value is the rate of the clock that is fed to the |
| 641 | * display engine's pipe which can be the above fast dot clock rate or a |
| 642 | * divided-down version of it. |
| 643 | */ |
| 644 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
| 645 | static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock) |
| 646 | { |
| 647 | clock->m = clock->m2 + 2; |
| 648 | clock->p = clock->p1 * clock->p2; |
| 649 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
| 650 | return 0; |
| 651 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
| 652 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
| 653 | |
| 654 | return clock->dot; |
| 655 | } |
| 656 | |
| 657 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
| 658 | { |
| 659 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); |
| 660 | } |
| 661 | |
| 662 | static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock) |
| 663 | { |
| 664 | clock->m = i9xx_dpll_compute_m(clock); |
| 665 | clock->p = clock->p1 * clock->p2; |
| 666 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
| 667 | return 0; |
| 668 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
| 669 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
| 670 | |
| 671 | return clock->dot; |
| 672 | } |
| 673 | |
| 674 | static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock) |
| 675 | { |
| 676 | clock->m = clock->m1 * clock->m2; |
| 677 | clock->p = clock->p1 * clock->p2; |
| 678 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
| 679 | return 0; |
| 680 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
| 681 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
| 682 | |
| 683 | return clock->dot / 5; |
| 684 | } |
| 685 | |
| 686 | int chv_calc_dpll_params(int refclk, intel_clock_t *clock) |
| 687 | { |
| 688 | clock->m = clock->m1 * clock->m2; |
| 689 | clock->p = clock->p1 * clock->p2; |
| 690 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
| 691 | return 0; |
| 692 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
| 693 | clock->n << 22); |
| 694 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
| 695 | |
| 696 | return clock->dot / 5; |
| 697 | } |
| 698 | |
| 699 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
| 700 | /** |
| 701 | * Returns whether the given set of divisors are valid for a given refclk with |
| 702 | * the given connectors. |
| 703 | */ |
| 704 | |
| 705 | static bool intel_PLL_is_valid(struct drm_device *dev, |
| 706 | const intel_limit_t *limit, |
| 707 | const intel_clock_t *clock) |
| 708 | { |
| 709 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
| 710 | INTELPllInvalid("n out of range\n"); |
| 711 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
| 712 | INTELPllInvalid("p1 out of range\n"); |
| 713 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
| 714 | INTELPllInvalid("m2 out of range\n"); |
| 715 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
| 716 | INTELPllInvalid("m1 out of range\n"); |
| 717 | |
| 718 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && |
| 719 | !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) |
| 720 | if (clock->m1 <= clock->m2) |
| 721 | INTELPllInvalid("m1 <= m2\n"); |
| 722 | |
| 723 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) { |
| 724 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
| 725 | INTELPllInvalid("p out of range\n"); |
| 726 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
| 727 | INTELPllInvalid("m out of range\n"); |
| 728 | } |
| 729 | |
| 730 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
| 731 | INTELPllInvalid("vco out of range\n"); |
| 732 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
| 733 | * connector, etc., rather than just a single range. |
| 734 | */ |
| 735 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) |
| 736 | INTELPllInvalid("dot out of range\n"); |
| 737 | |
| 738 | return true; |
| 739 | } |
| 740 | |
| 741 | static int |
| 742 | i9xx_select_p2_div(const intel_limit_t *limit, |
| 743 | const struct intel_crtc_state *crtc_state, |
| 744 | int target) |
| 745 | { |
| 746 | struct drm_device *dev = crtc_state->base.crtc->dev; |
| 747 | |
| 748 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
| 749 | /* |
| 750 | * For LVDS just rely on its current settings for dual-channel. |
| 751 | * We haven't figured out how to reliably set up different |
| 752 | * single/dual channel state, if we even can. |
| 753 | */ |
| 754 | if (intel_is_dual_link_lvds(dev)) |
| 755 | return limit->p2.p2_fast; |
| 756 | else |
| 757 | return limit->p2.p2_slow; |
| 758 | } else { |
| 759 | if (target < limit->p2.dot_limit) |
| 760 | return limit->p2.p2_slow; |
| 761 | else |
| 762 | return limit->p2.p2_fast; |
| 763 | } |
| 764 | } |
| 765 | |
| 766 | static bool |
| 767 | i9xx_find_best_dpll(const intel_limit_t *limit, |
| 768 | struct intel_crtc_state *crtc_state, |
| 769 | int target, int refclk, intel_clock_t *match_clock, |
| 770 | intel_clock_t *best_clock) |
| 771 | { |
| 772 | struct drm_device *dev = crtc_state->base.crtc->dev; |
| 773 | intel_clock_t clock; |
| 774 | int err = target; |
| 775 | |
| 776 | memset(best_clock, 0, sizeof(*best_clock)); |
| 777 | |
| 778 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
| 779 | |
| 780 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
| 781 | clock.m1++) { |
| 782 | for (clock.m2 = limit->m2.min; |
| 783 | clock.m2 <= limit->m2.max; clock.m2++) { |
| 784 | if (clock.m2 >= clock.m1) |
| 785 | break; |
| 786 | for (clock.n = limit->n.min; |
| 787 | clock.n <= limit->n.max; clock.n++) { |
| 788 | for (clock.p1 = limit->p1.min; |
| 789 | clock.p1 <= limit->p1.max; clock.p1++) { |
| 790 | int this_err; |
| 791 | |
| 792 | i9xx_calc_dpll_params(refclk, &clock); |
| 793 | if (!intel_PLL_is_valid(dev, limit, |
| 794 | &clock)) |
| 795 | continue; |
| 796 | if (match_clock && |
| 797 | clock.p != match_clock->p) |
| 798 | continue; |
| 799 | |
| 800 | this_err = abs(clock.dot - target); |
| 801 | if (this_err < err) { |
| 802 | *best_clock = clock; |
| 803 | err = this_err; |
| 804 | } |
| 805 | } |
| 806 | } |
| 807 | } |
| 808 | } |
| 809 | |
| 810 | return (err != target); |
| 811 | } |
| 812 | |
| 813 | static bool |
| 814 | pnv_find_best_dpll(const intel_limit_t *limit, |
| 815 | struct intel_crtc_state *crtc_state, |
| 816 | int target, int refclk, intel_clock_t *match_clock, |
| 817 | intel_clock_t *best_clock) |
| 818 | { |
| 819 | struct drm_device *dev = crtc_state->base.crtc->dev; |
| 820 | intel_clock_t clock; |
| 821 | int err = target; |
| 822 | |
| 823 | memset(best_clock, 0, sizeof(*best_clock)); |
| 824 | |
| 825 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
| 826 | |
| 827 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
| 828 | clock.m1++) { |
| 829 | for (clock.m2 = limit->m2.min; |
| 830 | clock.m2 <= limit->m2.max; clock.m2++) { |
| 831 | for (clock.n = limit->n.min; |
| 832 | clock.n <= limit->n.max; clock.n++) { |
| 833 | for (clock.p1 = limit->p1.min; |
| 834 | clock.p1 <= limit->p1.max; clock.p1++) { |
| 835 | int this_err; |
| 836 | |
| 837 | pnv_calc_dpll_params(refclk, &clock); |
| 838 | if (!intel_PLL_is_valid(dev, limit, |
| 839 | &clock)) |
| 840 | continue; |
| 841 | if (match_clock && |
| 842 | clock.p != match_clock->p) |
| 843 | continue; |
| 844 | |
| 845 | this_err = abs(clock.dot - target); |
| 846 | if (this_err < err) { |
| 847 | *best_clock = clock; |
| 848 | err = this_err; |
| 849 | } |
| 850 | } |
| 851 | } |
| 852 | } |
| 853 | } |
| 854 | |
| 855 | return (err != target); |
| 856 | } |
| 857 | |
| 858 | static bool |
| 859 | g4x_find_best_dpll(const intel_limit_t *limit, |
| 860 | struct intel_crtc_state *crtc_state, |
| 861 | int target, int refclk, intel_clock_t *match_clock, |
| 862 | intel_clock_t *best_clock) |
| 863 | { |
| 864 | struct drm_device *dev = crtc_state->base.crtc->dev; |
| 865 | intel_clock_t clock; |
| 866 | int max_n; |
| 867 | bool found = false; |
| 868 | /* approximately equals target * 0.00585 */ |
| 869 | int err_most = (target >> 8) + (target >> 9); |
| 870 | |
| 871 | memset(best_clock, 0, sizeof(*best_clock)); |
| 872 | |
| 873 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
| 874 | |
| 875 | max_n = limit->n.max; |
| 876 | /* based on hardware requirement, prefer smaller n to precision */ |
| 877 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
| 878 | /* based on hardware requirement, prefere larger m1,m2 */ |
| 879 | for (clock.m1 = limit->m1.max; |
| 880 | clock.m1 >= limit->m1.min; clock.m1--) { |
| 881 | for (clock.m2 = limit->m2.max; |
| 882 | clock.m2 >= limit->m2.min; clock.m2--) { |
| 883 | for (clock.p1 = limit->p1.max; |
| 884 | clock.p1 >= limit->p1.min; clock.p1--) { |
| 885 | int this_err; |
| 886 | |
| 887 | i9xx_calc_dpll_params(refclk, &clock); |
| 888 | if (!intel_PLL_is_valid(dev, limit, |
| 889 | &clock)) |
| 890 | continue; |
| 891 | |
| 892 | this_err = abs(clock.dot - target); |
| 893 | if (this_err < err_most) { |
| 894 | *best_clock = clock; |
| 895 | err_most = this_err; |
| 896 | max_n = clock.n; |
| 897 | found = true; |
| 898 | } |
| 899 | } |
| 900 | } |
| 901 | } |
| 902 | } |
| 903 | return found; |
| 904 | } |
| 905 | |
| 906 | /* |
| 907 | * Check if the calculated PLL configuration is more optimal compared to the |
| 908 | * best configuration and error found so far. Return the calculated error. |
| 909 | */ |
| 910 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, |
| 911 | const intel_clock_t *calculated_clock, |
| 912 | const intel_clock_t *best_clock, |
| 913 | unsigned int best_error_ppm, |
| 914 | unsigned int *error_ppm) |
| 915 | { |
| 916 | /* |
| 917 | * For CHV ignore the error and consider only the P value. |
| 918 | * Prefer a bigger P value based on HW requirements. |
| 919 | */ |
| 920 | if (IS_CHERRYVIEW(dev)) { |
| 921 | *error_ppm = 0; |
| 922 | |
| 923 | return calculated_clock->p > best_clock->p; |
| 924 | } |
| 925 | |
| 926 | if (WARN_ON_ONCE(!target_freq)) |
| 927 | return false; |
| 928 | |
| 929 | *error_ppm = div_u64(1000000ULL * |
| 930 | abs(target_freq - calculated_clock->dot), |
| 931 | target_freq); |
| 932 | /* |
| 933 | * Prefer a better P value over a better (smaller) error if the error |
| 934 | * is small. Ensure this preference for future configurations too by |
| 935 | * setting the error to 0. |
| 936 | */ |
| 937 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { |
| 938 | *error_ppm = 0; |
| 939 | |
| 940 | return true; |
| 941 | } |
| 942 | |
| 943 | return *error_ppm + 10 < best_error_ppm; |
| 944 | } |
| 945 | |
| 946 | static bool |
| 947 | vlv_find_best_dpll(const intel_limit_t *limit, |
| 948 | struct intel_crtc_state *crtc_state, |
| 949 | int target, int refclk, intel_clock_t *match_clock, |
| 950 | intel_clock_t *best_clock) |
| 951 | { |
| 952 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
| 953 | struct drm_device *dev = crtc->base.dev; |
| 954 | intel_clock_t clock; |
| 955 | unsigned int bestppm = 1000000; |
| 956 | /* min update 19.2 MHz */ |
| 957 | int max_n = min(limit->n.max, refclk / 19200); |
| 958 | bool found = false; |
| 959 | |
| 960 | target *= 5; /* fast clock */ |
| 961 | |
| 962 | memset(best_clock, 0, sizeof(*best_clock)); |
| 963 | |
| 964 | /* based on hardware requirement, prefer smaller n to precision */ |
| 965 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
| 966 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
| 967 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
| 968 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
| 969 | clock.p = clock.p1 * clock.p2; |
| 970 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
| 971 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
| 972 | unsigned int ppm; |
| 973 | |
| 974 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
| 975 | refclk * clock.m1); |
| 976 | |
| 977 | vlv_calc_dpll_params(refclk, &clock); |
| 978 | |
| 979 | if (!intel_PLL_is_valid(dev, limit, |
| 980 | &clock)) |
| 981 | continue; |
| 982 | |
| 983 | if (!vlv_PLL_is_optimal(dev, target, |
| 984 | &clock, |
| 985 | best_clock, |
| 986 | bestppm, &ppm)) |
| 987 | continue; |
| 988 | |
| 989 | *best_clock = clock; |
| 990 | bestppm = ppm; |
| 991 | found = true; |
| 992 | } |
| 993 | } |
| 994 | } |
| 995 | } |
| 996 | |
| 997 | return found; |
| 998 | } |
| 999 | |
| 1000 | static bool |
| 1001 | chv_find_best_dpll(const intel_limit_t *limit, |
| 1002 | struct intel_crtc_state *crtc_state, |
| 1003 | int target, int refclk, intel_clock_t *match_clock, |
| 1004 | intel_clock_t *best_clock) |
| 1005 | { |
| 1006 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
| 1007 | struct drm_device *dev = crtc->base.dev; |
| 1008 | unsigned int best_error_ppm; |
| 1009 | intel_clock_t clock; |
| 1010 | uint64_t m2; |
| 1011 | int found = false; |
| 1012 | |
| 1013 | memset(best_clock, 0, sizeof(*best_clock)); |
| 1014 | best_error_ppm = 1000000; |
| 1015 | |
| 1016 | /* |
| 1017 | * Based on hardware doc, the n always set to 1, and m1 always |
| 1018 | * set to 2. If requires to support 200Mhz refclk, we need to |
| 1019 | * revisit this because n may not 1 anymore. |
| 1020 | */ |
| 1021 | clock.n = 1, clock.m1 = 2; |
| 1022 | target *= 5; /* fast clock */ |
| 1023 | |
| 1024 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
| 1025 | for (clock.p2 = limit->p2.p2_fast; |
| 1026 | clock.p2 >= limit->p2.p2_slow; |
| 1027 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
| 1028 | unsigned int error_ppm; |
| 1029 | |
| 1030 | clock.p = clock.p1 * clock.p2; |
| 1031 | |
| 1032 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * |
| 1033 | clock.n) << 22, refclk * clock.m1); |
| 1034 | |
| 1035 | if (m2 > INT_MAX/clock.m1) |
| 1036 | continue; |
| 1037 | |
| 1038 | clock.m2 = m2; |
| 1039 | |
| 1040 | chv_calc_dpll_params(refclk, &clock); |
| 1041 | |
| 1042 | if (!intel_PLL_is_valid(dev, limit, &clock)) |
| 1043 | continue; |
| 1044 | |
| 1045 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
| 1046 | best_error_ppm, &error_ppm)) |
| 1047 | continue; |
| 1048 | |
| 1049 | *best_clock = clock; |
| 1050 | best_error_ppm = error_ppm; |
| 1051 | found = true; |
| 1052 | } |
| 1053 | } |
| 1054 | |
| 1055 | return found; |
| 1056 | } |
| 1057 | |
| 1058 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
| 1059 | intel_clock_t *best_clock) |
| 1060 | { |
| 1061 | int refclk = i9xx_get_refclk(crtc_state, 0); |
| 1062 | |
| 1063 | return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state, |
| 1064 | target_clock, refclk, NULL, best_clock); |
| 1065 | } |
| 1066 | |
| 1067 | bool intel_crtc_active(struct drm_crtc *crtc) |
| 1068 | { |
| 1069 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 1070 | |
| 1071 | /* Be paranoid as we can arrive here with only partial |
| 1072 | * state retrieved from the hardware during setup. |
| 1073 | * |
| 1074 | * We can ditch the adjusted_mode.crtc_clock check as soon |
| 1075 | * as Haswell has gained clock readout/fastboot support. |
| 1076 | * |
| 1077 | * We can ditch the crtc->primary->fb check as soon as we can |
| 1078 | * properly reconstruct framebuffers. |
| 1079 | * |
| 1080 | * FIXME: The intel_crtc->active here should be switched to |
| 1081 | * crtc->state->active once we have proper CRTC states wired up |
| 1082 | * for atomic. |
| 1083 | */ |
| 1084 | return intel_crtc->active && crtc->primary->state->fb && |
| 1085 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
| 1086 | } |
| 1087 | |
| 1088 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
| 1089 | enum pipe pipe) |
| 1090 | { |
| 1091 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 1092 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 1093 | |
| 1094 | return intel_crtc->config->cpu_transcoder; |
| 1095 | } |
| 1096 | |
| 1097 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
| 1098 | { |
| 1099 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1100 | i915_reg_t reg = PIPEDSL(pipe); |
| 1101 | u32 line1, line2; |
| 1102 | u32 line_mask; |
| 1103 | |
| 1104 | if (IS_GEN2(dev)) |
| 1105 | line_mask = DSL_LINEMASK_GEN2; |
| 1106 | else |
| 1107 | line_mask = DSL_LINEMASK_GEN3; |
| 1108 | |
| 1109 | line1 = I915_READ(reg) & line_mask; |
| 1110 | msleep(5); |
| 1111 | line2 = I915_READ(reg) & line_mask; |
| 1112 | |
| 1113 | return line1 == line2; |
| 1114 | } |
| 1115 | |
| 1116 | /* |
| 1117 | * intel_wait_for_pipe_off - wait for pipe to turn off |
| 1118 | * @crtc: crtc whose pipe to wait for |
| 1119 | * |
| 1120 | * After disabling a pipe, we can't wait for vblank in the usual way, |
| 1121 | * spinning on the vblank interrupt status bit, since we won't actually |
| 1122 | * see an interrupt when the pipe is disabled. |
| 1123 | * |
| 1124 | * On Gen4 and above: |
| 1125 | * wait for the pipe register state bit to turn off |
| 1126 | * |
| 1127 | * Otherwise: |
| 1128 | * wait for the display line value to settle (it usually |
| 1129 | * ends up stopping at the start of the next frame). |
| 1130 | * |
| 1131 | */ |
| 1132 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
| 1133 | { |
| 1134 | struct drm_device *dev = crtc->base.dev; |
| 1135 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1136 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
| 1137 | enum pipe pipe = crtc->pipe; |
| 1138 | |
| 1139 | if (INTEL_INFO(dev)->gen >= 4) { |
| 1140 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
| 1141 | |
| 1142 | /* Wait for the Pipe State to go off */ |
| 1143 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
| 1144 | 100)) |
| 1145 | WARN(1, "pipe_off wait timed out\n"); |
| 1146 | } else { |
| 1147 | /* Wait for the display line to settle */ |
| 1148 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
| 1149 | WARN(1, "pipe_off wait timed out\n"); |
| 1150 | } |
| 1151 | } |
| 1152 | |
| 1153 | static const char *state_string(bool enabled) |
| 1154 | { |
| 1155 | return enabled ? "on" : "off"; |
| 1156 | } |
| 1157 | |
| 1158 | /* Only for pre-ILK configs */ |
| 1159 | void assert_pll(struct drm_i915_private *dev_priv, |
| 1160 | enum pipe pipe, bool state) |
| 1161 | { |
| 1162 | u32 val; |
| 1163 | bool cur_state; |
| 1164 | |
| 1165 | val = I915_READ(DPLL(pipe)); |
| 1166 | cur_state = !!(val & DPLL_VCO_ENABLE); |
| 1167 | I915_STATE_WARN(cur_state != state, |
| 1168 | "PLL state assertion failure (expected %s, current %s)\n", |
| 1169 | state_string(state), state_string(cur_state)); |
| 1170 | } |
| 1171 | |
| 1172 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
| 1173 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
| 1174 | { |
| 1175 | u32 val; |
| 1176 | bool cur_state; |
| 1177 | |
| 1178 | mutex_lock(&dev_priv->sb_lock); |
| 1179 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
| 1180 | mutex_unlock(&dev_priv->sb_lock); |
| 1181 | |
| 1182 | cur_state = val & DSI_PLL_VCO_EN; |
| 1183 | I915_STATE_WARN(cur_state != state, |
| 1184 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
| 1185 | state_string(state), state_string(cur_state)); |
| 1186 | } |
| 1187 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) |
| 1188 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) |
| 1189 | |
| 1190 | struct intel_shared_dpll * |
| 1191 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
| 1192 | { |
| 1193 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
| 1194 | |
| 1195 | if (crtc->config->shared_dpll < 0) |
| 1196 | return NULL; |
| 1197 | |
| 1198 | return &dev_priv->shared_dplls[crtc->config->shared_dpll]; |
| 1199 | } |
| 1200 | |
| 1201 | /* For ILK+ */ |
| 1202 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
| 1203 | struct intel_shared_dpll *pll, |
| 1204 | bool state) |
| 1205 | { |
| 1206 | bool cur_state; |
| 1207 | struct intel_dpll_hw_state hw_state; |
| 1208 | |
| 1209 | if (WARN (!pll, |
| 1210 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
| 1211 | return; |
| 1212 | |
| 1213 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
| 1214 | I915_STATE_WARN(cur_state != state, |
| 1215 | "%s assertion failure (expected %s, current %s)\n", |
| 1216 | pll->name, state_string(state), state_string(cur_state)); |
| 1217 | } |
| 1218 | |
| 1219 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
| 1220 | enum pipe pipe, bool state) |
| 1221 | { |
| 1222 | bool cur_state; |
| 1223 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
| 1224 | pipe); |
| 1225 | |
| 1226 | if (HAS_DDI(dev_priv->dev)) { |
| 1227 | /* DDI does not have a specific FDI_TX register */ |
| 1228 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
| 1229 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
| 1230 | } else { |
| 1231 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
| 1232 | cur_state = !!(val & FDI_TX_ENABLE); |
| 1233 | } |
| 1234 | I915_STATE_WARN(cur_state != state, |
| 1235 | "FDI TX state assertion failure (expected %s, current %s)\n", |
| 1236 | state_string(state), state_string(cur_state)); |
| 1237 | } |
| 1238 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) |
| 1239 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) |
| 1240 | |
| 1241 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, |
| 1242 | enum pipe pipe, bool state) |
| 1243 | { |
| 1244 | u32 val; |
| 1245 | bool cur_state; |
| 1246 | |
| 1247 | val = I915_READ(FDI_RX_CTL(pipe)); |
| 1248 | cur_state = !!(val & FDI_RX_ENABLE); |
| 1249 | I915_STATE_WARN(cur_state != state, |
| 1250 | "FDI RX state assertion failure (expected %s, current %s)\n", |
| 1251 | state_string(state), state_string(cur_state)); |
| 1252 | } |
| 1253 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) |
| 1254 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) |
| 1255 | |
| 1256 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, |
| 1257 | enum pipe pipe) |
| 1258 | { |
| 1259 | u32 val; |
| 1260 | |
| 1261 | /* ILK FDI PLL is always enabled */ |
| 1262 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
| 1263 | return; |
| 1264 | |
| 1265 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
| 1266 | if (HAS_DDI(dev_priv->dev)) |
| 1267 | return; |
| 1268 | |
| 1269 | val = I915_READ(FDI_TX_CTL(pipe)); |
| 1270 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
| 1271 | } |
| 1272 | |
| 1273 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
| 1274 | enum pipe pipe, bool state) |
| 1275 | { |
| 1276 | u32 val; |
| 1277 | bool cur_state; |
| 1278 | |
| 1279 | val = I915_READ(FDI_RX_CTL(pipe)); |
| 1280 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
| 1281 | I915_STATE_WARN(cur_state != state, |
| 1282 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
| 1283 | state_string(state), state_string(cur_state)); |
| 1284 | } |
| 1285 | |
| 1286 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
| 1287 | enum pipe pipe) |
| 1288 | { |
| 1289 | struct drm_device *dev = dev_priv->dev; |
| 1290 | i915_reg_t pp_reg; |
| 1291 | u32 val; |
| 1292 | enum pipe panel_pipe = PIPE_A; |
| 1293 | bool locked = true; |
| 1294 | |
| 1295 | if (WARN_ON(HAS_DDI(dev))) |
| 1296 | return; |
| 1297 | |
| 1298 | if (HAS_PCH_SPLIT(dev)) { |
| 1299 | u32 port_sel; |
| 1300 | |
| 1301 | pp_reg = PCH_PP_CONTROL; |
| 1302 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
| 1303 | |
| 1304 | if (port_sel == PANEL_PORT_SELECT_LVDS && |
| 1305 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) |
| 1306 | panel_pipe = PIPE_B; |
| 1307 | /* XXX: else fix for eDP */ |
| 1308 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
| 1309 | /* presumably write lock depends on pipe, not port select */ |
| 1310 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); |
| 1311 | panel_pipe = pipe; |
| 1312 | } else { |
| 1313 | pp_reg = PP_CONTROL; |
| 1314 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
| 1315 | panel_pipe = PIPE_B; |
| 1316 | } |
| 1317 | |
| 1318 | val = I915_READ(pp_reg); |
| 1319 | if (!(val & PANEL_POWER_ON) || |
| 1320 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
| 1321 | locked = false; |
| 1322 | |
| 1323 | I915_STATE_WARN(panel_pipe == pipe && locked, |
| 1324 | "panel assertion failure, pipe %c regs locked\n", |
| 1325 | pipe_name(pipe)); |
| 1326 | } |
| 1327 | |
| 1328 | static void assert_cursor(struct drm_i915_private *dev_priv, |
| 1329 | enum pipe pipe, bool state) |
| 1330 | { |
| 1331 | struct drm_device *dev = dev_priv->dev; |
| 1332 | bool cur_state; |
| 1333 | |
| 1334 | if (IS_845G(dev) || IS_I865G(dev)) |
| 1335 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
| 1336 | else |
| 1337 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
| 1338 | |
| 1339 | I915_STATE_WARN(cur_state != state, |
| 1340 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
| 1341 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
| 1342 | } |
| 1343 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) |
| 1344 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) |
| 1345 | |
| 1346 | void assert_pipe(struct drm_i915_private *dev_priv, |
| 1347 | enum pipe pipe, bool state) |
| 1348 | { |
| 1349 | bool cur_state; |
| 1350 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
| 1351 | pipe); |
| 1352 | |
| 1353 | /* if we need the pipe quirk it must be always on */ |
| 1354 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
| 1355 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) |
| 1356 | state = true; |
| 1357 | |
| 1358 | if (!intel_display_power_is_enabled(dev_priv, |
| 1359 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
| 1360 | cur_state = false; |
| 1361 | } else { |
| 1362 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
| 1363 | cur_state = !!(val & PIPECONF_ENABLE); |
| 1364 | } |
| 1365 | |
| 1366 | I915_STATE_WARN(cur_state != state, |
| 1367 | "pipe %c assertion failure (expected %s, current %s)\n", |
| 1368 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
| 1369 | } |
| 1370 | |
| 1371 | static void assert_plane(struct drm_i915_private *dev_priv, |
| 1372 | enum plane plane, bool state) |
| 1373 | { |
| 1374 | u32 val; |
| 1375 | bool cur_state; |
| 1376 | |
| 1377 | val = I915_READ(DSPCNTR(plane)); |
| 1378 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
| 1379 | I915_STATE_WARN(cur_state != state, |
| 1380 | "plane %c assertion failure (expected %s, current %s)\n", |
| 1381 | plane_name(plane), state_string(state), state_string(cur_state)); |
| 1382 | } |
| 1383 | |
| 1384 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
| 1385 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) |
| 1386 | |
| 1387 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
| 1388 | enum pipe pipe) |
| 1389 | { |
| 1390 | struct drm_device *dev = dev_priv->dev; |
| 1391 | int i; |
| 1392 | |
| 1393 | /* Primary planes are fixed to pipes on gen4+ */ |
| 1394 | if (INTEL_INFO(dev)->gen >= 4) { |
| 1395 | u32 val = I915_READ(DSPCNTR(pipe)); |
| 1396 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
| 1397 | "plane %c assertion failure, should be disabled but not\n", |
| 1398 | plane_name(pipe)); |
| 1399 | return; |
| 1400 | } |
| 1401 | |
| 1402 | /* Need to check both planes against the pipe */ |
| 1403 | for_each_pipe(dev_priv, i) { |
| 1404 | u32 val = I915_READ(DSPCNTR(i)); |
| 1405 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> |
| 1406 | DISPPLANE_SEL_PIPE_SHIFT; |
| 1407 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
| 1408 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
| 1409 | plane_name(i), pipe_name(pipe)); |
| 1410 | } |
| 1411 | } |
| 1412 | |
| 1413 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
| 1414 | enum pipe pipe) |
| 1415 | { |
| 1416 | struct drm_device *dev = dev_priv->dev; |
| 1417 | int sprite; |
| 1418 | |
| 1419 | if (INTEL_INFO(dev)->gen >= 9) { |
| 1420 | for_each_sprite(dev_priv, pipe, sprite) { |
| 1421 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
| 1422 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
| 1423 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
| 1424 | sprite, pipe_name(pipe)); |
| 1425 | } |
| 1426 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
| 1427 | for_each_sprite(dev_priv, pipe, sprite) { |
| 1428 | u32 val = I915_READ(SPCNTR(pipe, sprite)); |
| 1429 | I915_STATE_WARN(val & SP_ENABLE, |
| 1430 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
| 1431 | sprite_name(pipe, sprite), pipe_name(pipe)); |
| 1432 | } |
| 1433 | } else if (INTEL_INFO(dev)->gen >= 7) { |
| 1434 | u32 val = I915_READ(SPRCTL(pipe)); |
| 1435 | I915_STATE_WARN(val & SPRITE_ENABLE, |
| 1436 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
| 1437 | plane_name(pipe), pipe_name(pipe)); |
| 1438 | } else if (INTEL_INFO(dev)->gen >= 5) { |
| 1439 | u32 val = I915_READ(DVSCNTR(pipe)); |
| 1440 | I915_STATE_WARN(val & DVS_ENABLE, |
| 1441 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
| 1442 | plane_name(pipe), pipe_name(pipe)); |
| 1443 | } |
| 1444 | } |
| 1445 | |
| 1446 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
| 1447 | { |
| 1448 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
| 1449 | drm_crtc_vblank_put(crtc); |
| 1450 | } |
| 1451 | |
| 1452 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
| 1453 | { |
| 1454 | u32 val; |
| 1455 | bool enabled; |
| 1456 | |
| 1457 | I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
| 1458 | |
| 1459 | val = I915_READ(PCH_DREF_CONTROL); |
| 1460 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | |
| 1461 | DREF_SUPERSPREAD_SOURCE_MASK)); |
| 1462 | I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
| 1463 | } |
| 1464 | |
| 1465 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
| 1466 | enum pipe pipe) |
| 1467 | { |
| 1468 | u32 val; |
| 1469 | bool enabled; |
| 1470 | |
| 1471 | val = I915_READ(PCH_TRANSCONF(pipe)); |
| 1472 | enabled = !!(val & TRANS_ENABLE); |
| 1473 | I915_STATE_WARN(enabled, |
| 1474 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
| 1475 | pipe_name(pipe)); |
| 1476 | } |
| 1477 | |
| 1478 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
| 1479 | enum pipe pipe, u32 port_sel, u32 val) |
| 1480 | { |
| 1481 | if ((val & DP_PORT_EN) == 0) |
| 1482 | return false; |
| 1483 | |
| 1484 | if (HAS_PCH_CPT(dev_priv->dev)) { |
| 1485 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
| 1486 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
| 1487 | return false; |
| 1488 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
| 1489 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) |
| 1490 | return false; |
| 1491 | } else { |
| 1492 | if ((val & DP_PIPE_MASK) != (pipe << 30)) |
| 1493 | return false; |
| 1494 | } |
| 1495 | return true; |
| 1496 | } |
| 1497 | |
| 1498 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
| 1499 | enum pipe pipe, u32 val) |
| 1500 | { |
| 1501 | if ((val & SDVO_ENABLE) == 0) |
| 1502 | return false; |
| 1503 | |
| 1504 | if (HAS_PCH_CPT(dev_priv->dev)) { |
| 1505 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
| 1506 | return false; |
| 1507 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
| 1508 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) |
| 1509 | return false; |
| 1510 | } else { |
| 1511 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
| 1512 | return false; |
| 1513 | } |
| 1514 | return true; |
| 1515 | } |
| 1516 | |
| 1517 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, |
| 1518 | enum pipe pipe, u32 val) |
| 1519 | { |
| 1520 | if ((val & LVDS_PORT_EN) == 0) |
| 1521 | return false; |
| 1522 | |
| 1523 | if (HAS_PCH_CPT(dev_priv->dev)) { |
| 1524 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
| 1525 | return false; |
| 1526 | } else { |
| 1527 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) |
| 1528 | return false; |
| 1529 | } |
| 1530 | return true; |
| 1531 | } |
| 1532 | |
| 1533 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, |
| 1534 | enum pipe pipe, u32 val) |
| 1535 | { |
| 1536 | if ((val & ADPA_DAC_ENABLE) == 0) |
| 1537 | return false; |
| 1538 | if (HAS_PCH_CPT(dev_priv->dev)) { |
| 1539 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
| 1540 | return false; |
| 1541 | } else { |
| 1542 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) |
| 1543 | return false; |
| 1544 | } |
| 1545 | return true; |
| 1546 | } |
| 1547 | |
| 1548 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
| 1549 | enum pipe pipe, i915_reg_t reg, |
| 1550 | u32 port_sel) |
| 1551 | { |
| 1552 | u32 val = I915_READ(reg); |
| 1553 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
| 1554 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
| 1555 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
| 1556 | |
| 1557 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
| 1558 | && (val & DP_PIPEB_SELECT), |
| 1559 | "IBX PCH dp port still using transcoder B\n"); |
| 1560 | } |
| 1561 | |
| 1562 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, |
| 1563 | enum pipe pipe, i915_reg_t reg) |
| 1564 | { |
| 1565 | u32 val = I915_READ(reg); |
| 1566 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
| 1567 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
| 1568 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
| 1569 | |
| 1570 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
| 1571 | && (val & SDVO_PIPE_B_SELECT), |
| 1572 | "IBX PCH hdmi port still using transcoder B\n"); |
| 1573 | } |
| 1574 | |
| 1575 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, |
| 1576 | enum pipe pipe) |
| 1577 | { |
| 1578 | u32 val; |
| 1579 | |
| 1580 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
| 1581 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); |
| 1582 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); |
| 1583 | |
| 1584 | val = I915_READ(PCH_ADPA); |
| 1585 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
| 1586 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
| 1587 | pipe_name(pipe)); |
| 1588 | |
| 1589 | val = I915_READ(PCH_LVDS); |
| 1590 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
| 1591 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
| 1592 | pipe_name(pipe)); |
| 1593 | |
| 1594 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
| 1595 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); |
| 1596 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); |
| 1597 | } |
| 1598 | |
| 1599 | static void vlv_enable_pll(struct intel_crtc *crtc, |
| 1600 | const struct intel_crtc_state *pipe_config) |
| 1601 | { |
| 1602 | struct drm_device *dev = crtc->base.dev; |
| 1603 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1604 | i915_reg_t reg = DPLL(crtc->pipe); |
| 1605 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
| 1606 | |
| 1607 | assert_pipe_disabled(dev_priv, crtc->pipe); |
| 1608 | |
| 1609 | /* PLL is protected by panel, make sure we can write it */ |
| 1610 | if (IS_MOBILE(dev_priv->dev)) |
| 1611 | assert_panel_unlocked(dev_priv, crtc->pipe); |
| 1612 | |
| 1613 | I915_WRITE(reg, dpll); |
| 1614 | POSTING_READ(reg); |
| 1615 | udelay(150); |
| 1616 | |
| 1617 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
| 1618 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); |
| 1619 | |
| 1620 | I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); |
| 1621 | POSTING_READ(DPLL_MD(crtc->pipe)); |
| 1622 | |
| 1623 | /* We do this three times for luck */ |
| 1624 | I915_WRITE(reg, dpll); |
| 1625 | POSTING_READ(reg); |
| 1626 | udelay(150); /* wait for warmup */ |
| 1627 | I915_WRITE(reg, dpll); |
| 1628 | POSTING_READ(reg); |
| 1629 | udelay(150); /* wait for warmup */ |
| 1630 | I915_WRITE(reg, dpll); |
| 1631 | POSTING_READ(reg); |
| 1632 | udelay(150); /* wait for warmup */ |
| 1633 | } |
| 1634 | |
| 1635 | static void chv_enable_pll(struct intel_crtc *crtc, |
| 1636 | const struct intel_crtc_state *pipe_config) |
| 1637 | { |
| 1638 | struct drm_device *dev = crtc->base.dev; |
| 1639 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1640 | int pipe = crtc->pipe; |
| 1641 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
| 1642 | u32 tmp; |
| 1643 | |
| 1644 | assert_pipe_disabled(dev_priv, crtc->pipe); |
| 1645 | |
| 1646 | mutex_lock(&dev_priv->sb_lock); |
| 1647 | |
| 1648 | /* Enable back the 10bit clock to display controller */ |
| 1649 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); |
| 1650 | tmp |= DPIO_DCLKP_EN; |
| 1651 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); |
| 1652 | |
| 1653 | mutex_unlock(&dev_priv->sb_lock); |
| 1654 | |
| 1655 | /* |
| 1656 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. |
| 1657 | */ |
| 1658 | udelay(1); |
| 1659 | |
| 1660 | /* Enable PLL */ |
| 1661 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
| 1662 | |
| 1663 | /* Check PLL is locked */ |
| 1664 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
| 1665 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
| 1666 | |
| 1667 | /* not sure when this should be written */ |
| 1668 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
| 1669 | POSTING_READ(DPLL_MD(pipe)); |
| 1670 | } |
| 1671 | |
| 1672 | static int intel_num_dvo_pipes(struct drm_device *dev) |
| 1673 | { |
| 1674 | struct intel_crtc *crtc; |
| 1675 | int count = 0; |
| 1676 | |
| 1677 | for_each_intel_crtc(dev, crtc) |
| 1678 | count += crtc->base.state->active && |
| 1679 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
| 1680 | |
| 1681 | return count; |
| 1682 | } |
| 1683 | |
| 1684 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
| 1685 | { |
| 1686 | struct drm_device *dev = crtc->base.dev; |
| 1687 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1688 | i915_reg_t reg = DPLL(crtc->pipe); |
| 1689 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
| 1690 | |
| 1691 | assert_pipe_disabled(dev_priv, crtc->pipe); |
| 1692 | |
| 1693 | /* No really, not for ILK+ */ |
| 1694 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
| 1695 | |
| 1696 | /* PLL is protected by panel, make sure we can write it */ |
| 1697 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
| 1698 | assert_panel_unlocked(dev_priv, crtc->pipe); |
| 1699 | |
| 1700 | /* Enable DVO 2x clock on both PLLs if necessary */ |
| 1701 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { |
| 1702 | /* |
| 1703 | * It appears to be important that we don't enable this |
| 1704 | * for the current pipe before otherwise configuring the |
| 1705 | * PLL. No idea how this should be handled if multiple |
| 1706 | * DVO outputs are enabled simultaneosly. |
| 1707 | */ |
| 1708 | dpll |= DPLL_DVO_2X_MODE; |
| 1709 | I915_WRITE(DPLL(!crtc->pipe), |
| 1710 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); |
| 1711 | } |
| 1712 | |
| 1713 | /* |
| 1714 | * Apparently we need to have VGA mode enabled prior to changing |
| 1715 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old |
| 1716 | * dividers, even though the register value does change. |
| 1717 | */ |
| 1718 | I915_WRITE(reg, 0); |
| 1719 | |
| 1720 | I915_WRITE(reg, dpll); |
| 1721 | |
| 1722 | /* Wait for the clocks to stabilize. */ |
| 1723 | POSTING_READ(reg); |
| 1724 | udelay(150); |
| 1725 | |
| 1726 | if (INTEL_INFO(dev)->gen >= 4) { |
| 1727 | I915_WRITE(DPLL_MD(crtc->pipe), |
| 1728 | crtc->config->dpll_hw_state.dpll_md); |
| 1729 | } else { |
| 1730 | /* The pixel multiplier can only be updated once the |
| 1731 | * DPLL is enabled and the clocks are stable. |
| 1732 | * |
| 1733 | * So write it again. |
| 1734 | */ |
| 1735 | I915_WRITE(reg, dpll); |
| 1736 | } |
| 1737 | |
| 1738 | /* We do this three times for luck */ |
| 1739 | I915_WRITE(reg, dpll); |
| 1740 | POSTING_READ(reg); |
| 1741 | udelay(150); /* wait for warmup */ |
| 1742 | I915_WRITE(reg, dpll); |
| 1743 | POSTING_READ(reg); |
| 1744 | udelay(150); /* wait for warmup */ |
| 1745 | I915_WRITE(reg, dpll); |
| 1746 | POSTING_READ(reg); |
| 1747 | udelay(150); /* wait for warmup */ |
| 1748 | } |
| 1749 | |
| 1750 | /** |
| 1751 | * i9xx_disable_pll - disable a PLL |
| 1752 | * @dev_priv: i915 private structure |
| 1753 | * @pipe: pipe PLL to disable |
| 1754 | * |
| 1755 | * Disable the PLL for @pipe, making sure the pipe is off first. |
| 1756 | * |
| 1757 | * Note! This is for pre-ILK only. |
| 1758 | */ |
| 1759 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
| 1760 | { |
| 1761 | struct drm_device *dev = crtc->base.dev; |
| 1762 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1763 | enum pipe pipe = crtc->pipe; |
| 1764 | |
| 1765 | /* Disable DVO 2x clock on both PLLs if necessary */ |
| 1766 | if (IS_I830(dev) && |
| 1767 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
| 1768 | !intel_num_dvo_pipes(dev)) { |
| 1769 | I915_WRITE(DPLL(PIPE_B), |
| 1770 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); |
| 1771 | I915_WRITE(DPLL(PIPE_A), |
| 1772 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); |
| 1773 | } |
| 1774 | |
| 1775 | /* Don't disable pipe or pipe PLLs if needed */ |
| 1776 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
| 1777 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) |
| 1778 | return; |
| 1779 | |
| 1780 | /* Make sure the pipe isn't still relying on us */ |
| 1781 | assert_pipe_disabled(dev_priv, pipe); |
| 1782 | |
| 1783 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
| 1784 | POSTING_READ(DPLL(pipe)); |
| 1785 | } |
| 1786 | |
| 1787 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
| 1788 | { |
| 1789 | u32 val; |
| 1790 | |
| 1791 | /* Make sure the pipe isn't still relying on us */ |
| 1792 | assert_pipe_disabled(dev_priv, pipe); |
| 1793 | |
| 1794 | /* |
| 1795 | * Leave integrated clock source and reference clock enabled for pipe B. |
| 1796 | * The latter is needed for VGA hotplug / manual detection. |
| 1797 | */ |
| 1798 | val = DPLL_VGA_MODE_DIS; |
| 1799 | if (pipe == PIPE_B) |
| 1800 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV; |
| 1801 | I915_WRITE(DPLL(pipe), val); |
| 1802 | POSTING_READ(DPLL(pipe)); |
| 1803 | |
| 1804 | } |
| 1805 | |
| 1806 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
| 1807 | { |
| 1808 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
| 1809 | u32 val; |
| 1810 | |
| 1811 | /* Make sure the pipe isn't still relying on us */ |
| 1812 | assert_pipe_disabled(dev_priv, pipe); |
| 1813 | |
| 1814 | /* Set PLL en = 0 */ |
| 1815 | val = DPLL_SSC_REF_CLK_CHV | |
| 1816 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
| 1817 | if (pipe != PIPE_A) |
| 1818 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; |
| 1819 | I915_WRITE(DPLL(pipe), val); |
| 1820 | POSTING_READ(DPLL(pipe)); |
| 1821 | |
| 1822 | mutex_lock(&dev_priv->sb_lock); |
| 1823 | |
| 1824 | /* Disable 10bit clock to display controller */ |
| 1825 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); |
| 1826 | val &= ~DPIO_DCLKP_EN; |
| 1827 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); |
| 1828 | |
| 1829 | mutex_unlock(&dev_priv->sb_lock); |
| 1830 | } |
| 1831 | |
| 1832 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
| 1833 | struct intel_digital_port *dport, |
| 1834 | unsigned int expected_mask) |
| 1835 | { |
| 1836 | u32 port_mask; |
| 1837 | i915_reg_t dpll_reg; |
| 1838 | |
| 1839 | switch (dport->port) { |
| 1840 | case PORT_B: |
| 1841 | port_mask = DPLL_PORTB_READY_MASK; |
| 1842 | dpll_reg = DPLL(0); |
| 1843 | break; |
| 1844 | case PORT_C: |
| 1845 | port_mask = DPLL_PORTC_READY_MASK; |
| 1846 | dpll_reg = DPLL(0); |
| 1847 | expected_mask <<= 4; |
| 1848 | break; |
| 1849 | case PORT_D: |
| 1850 | port_mask = DPLL_PORTD_READY_MASK; |
| 1851 | dpll_reg = DPIO_PHY_STATUS; |
| 1852 | break; |
| 1853 | default: |
| 1854 | BUG(); |
| 1855 | } |
| 1856 | |
| 1857 | if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000)) |
| 1858 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", |
| 1859 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); |
| 1860 | } |
| 1861 | |
| 1862 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
| 1863 | { |
| 1864 | struct drm_device *dev = crtc->base.dev; |
| 1865 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1866 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
| 1867 | |
| 1868 | if (WARN_ON(pll == NULL)) |
| 1869 | return; |
| 1870 | |
| 1871 | WARN_ON(!pll->config.crtc_mask); |
| 1872 | if (pll->active == 0) { |
| 1873 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); |
| 1874 | WARN_ON(pll->on); |
| 1875 | assert_shared_dpll_disabled(dev_priv, pll); |
| 1876 | |
| 1877 | pll->mode_set(dev_priv, pll); |
| 1878 | } |
| 1879 | } |
| 1880 | |
| 1881 | /** |
| 1882 | * intel_enable_shared_dpll - enable PCH PLL |
| 1883 | * @dev_priv: i915 private structure |
| 1884 | * @pipe: pipe PLL to enable |
| 1885 | * |
| 1886 | * The PCH PLL needs to be enabled before the PCH transcoder, since it |
| 1887 | * drives the transcoder clock. |
| 1888 | */ |
| 1889 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
| 1890 | { |
| 1891 | struct drm_device *dev = crtc->base.dev; |
| 1892 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1893 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
| 1894 | |
| 1895 | if (WARN_ON(pll == NULL)) |
| 1896 | return; |
| 1897 | |
| 1898 | if (WARN_ON(pll->config.crtc_mask == 0)) |
| 1899 | return; |
| 1900 | |
| 1901 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
| 1902 | pll->name, pll->active, pll->on, |
| 1903 | crtc->base.base.id); |
| 1904 | |
| 1905 | if (pll->active++) { |
| 1906 | WARN_ON(!pll->on); |
| 1907 | assert_shared_dpll_enabled(dev_priv, pll); |
| 1908 | return; |
| 1909 | } |
| 1910 | WARN_ON(pll->on); |
| 1911 | |
| 1912 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
| 1913 | |
| 1914 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
| 1915 | pll->enable(dev_priv, pll); |
| 1916 | pll->on = true; |
| 1917 | } |
| 1918 | |
| 1919 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
| 1920 | { |
| 1921 | struct drm_device *dev = crtc->base.dev; |
| 1922 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1923 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
| 1924 | |
| 1925 | /* PCH only available on ILK+ */ |
| 1926 | if (INTEL_INFO(dev)->gen < 5) |
| 1927 | return; |
| 1928 | |
| 1929 | if (pll == NULL) |
| 1930 | return; |
| 1931 | |
| 1932 | if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base))))) |
| 1933 | return; |
| 1934 | |
| 1935 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
| 1936 | pll->name, pll->active, pll->on, |
| 1937 | crtc->base.base.id); |
| 1938 | |
| 1939 | if (WARN_ON(pll->active == 0)) { |
| 1940 | assert_shared_dpll_disabled(dev_priv, pll); |
| 1941 | return; |
| 1942 | } |
| 1943 | |
| 1944 | assert_shared_dpll_enabled(dev_priv, pll); |
| 1945 | WARN_ON(!pll->on); |
| 1946 | if (--pll->active) |
| 1947 | return; |
| 1948 | |
| 1949 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
| 1950 | pll->disable(dev_priv, pll); |
| 1951 | pll->on = false; |
| 1952 | |
| 1953 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
| 1954 | } |
| 1955 | |
| 1956 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
| 1957 | enum pipe pipe) |
| 1958 | { |
| 1959 | struct drm_device *dev = dev_priv->dev; |
| 1960 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 1961 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 1962 | i915_reg_t reg; |
| 1963 | uint32_t val, pipeconf_val; |
| 1964 | |
| 1965 | /* PCH only available on ILK+ */ |
| 1966 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
| 1967 | |
| 1968 | /* Make sure PCH DPLL is enabled */ |
| 1969 | assert_shared_dpll_enabled(dev_priv, |
| 1970 | intel_crtc_to_shared_dpll(intel_crtc)); |
| 1971 | |
| 1972 | /* FDI must be feeding us bits for PCH ports */ |
| 1973 | assert_fdi_tx_enabled(dev_priv, pipe); |
| 1974 | assert_fdi_rx_enabled(dev_priv, pipe); |
| 1975 | |
| 1976 | if (HAS_PCH_CPT(dev)) { |
| 1977 | /* Workaround: Set the timing override bit before enabling the |
| 1978 | * pch transcoder. */ |
| 1979 | reg = TRANS_CHICKEN2(pipe); |
| 1980 | val = I915_READ(reg); |
| 1981 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
| 1982 | I915_WRITE(reg, val); |
| 1983 | } |
| 1984 | |
| 1985 | reg = PCH_TRANSCONF(pipe); |
| 1986 | val = I915_READ(reg); |
| 1987 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
| 1988 | |
| 1989 | if (HAS_PCH_IBX(dev_priv->dev)) { |
| 1990 | /* |
| 1991 | * Make the BPC in transcoder be consistent with |
| 1992 | * that in pipeconf reg. For HDMI we must use 8bpc |
| 1993 | * here for both 8bpc and 12bpc. |
| 1994 | */ |
| 1995 | val &= ~PIPECONF_BPC_MASK; |
| 1996 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI)) |
| 1997 | val |= PIPECONF_8BPC; |
| 1998 | else |
| 1999 | val |= pipeconf_val & PIPECONF_BPC_MASK; |
| 2000 | } |
| 2001 | |
| 2002 | val &= ~TRANS_INTERLACE_MASK; |
| 2003 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) |
| 2004 | if (HAS_PCH_IBX(dev_priv->dev) && |
| 2005 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
| 2006 | val |= TRANS_LEGACY_INTERLACED_ILK; |
| 2007 | else |
| 2008 | val |= TRANS_INTERLACED; |
| 2009 | else |
| 2010 | val |= TRANS_PROGRESSIVE; |
| 2011 | |
| 2012 | I915_WRITE(reg, val | TRANS_ENABLE); |
| 2013 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) |
| 2014 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
| 2015 | } |
| 2016 | |
| 2017 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
| 2018 | enum transcoder cpu_transcoder) |
| 2019 | { |
| 2020 | u32 val, pipeconf_val; |
| 2021 | |
| 2022 | /* PCH only available on ILK+ */ |
| 2023 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
| 2024 | |
| 2025 | /* FDI must be feeding us bits for PCH ports */ |
| 2026 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
| 2027 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
| 2028 | |
| 2029 | /* Workaround: set timing override bit. */ |
| 2030 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
| 2031 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
| 2032 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
| 2033 | |
| 2034 | val = TRANS_ENABLE; |
| 2035 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
| 2036 | |
| 2037 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
| 2038 | PIPECONF_INTERLACED_ILK) |
| 2039 | val |= TRANS_INTERLACED; |
| 2040 | else |
| 2041 | val |= TRANS_PROGRESSIVE; |
| 2042 | |
| 2043 | I915_WRITE(LPT_TRANSCONF, val); |
| 2044 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) |
| 2045 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
| 2046 | } |
| 2047 | |
| 2048 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
| 2049 | enum pipe pipe) |
| 2050 | { |
| 2051 | struct drm_device *dev = dev_priv->dev; |
| 2052 | i915_reg_t reg; |
| 2053 | uint32_t val; |
| 2054 | |
| 2055 | /* FDI relies on the transcoder */ |
| 2056 | assert_fdi_tx_disabled(dev_priv, pipe); |
| 2057 | assert_fdi_rx_disabled(dev_priv, pipe); |
| 2058 | |
| 2059 | /* Ports must be off as well */ |
| 2060 | assert_pch_ports_disabled(dev_priv, pipe); |
| 2061 | |
| 2062 | reg = PCH_TRANSCONF(pipe); |
| 2063 | val = I915_READ(reg); |
| 2064 | val &= ~TRANS_ENABLE; |
| 2065 | I915_WRITE(reg, val); |
| 2066 | /* wait for PCH transcoder off, transcoder state */ |
| 2067 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) |
| 2068 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
| 2069 | |
| 2070 | if (HAS_PCH_CPT(dev)) { |
| 2071 | /* Workaround: Clear the timing override chicken bit again. */ |
| 2072 | reg = TRANS_CHICKEN2(pipe); |
| 2073 | val = I915_READ(reg); |
| 2074 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
| 2075 | I915_WRITE(reg, val); |
| 2076 | } |
| 2077 | } |
| 2078 | |
| 2079 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
| 2080 | { |
| 2081 | u32 val; |
| 2082 | |
| 2083 | val = I915_READ(LPT_TRANSCONF); |
| 2084 | val &= ~TRANS_ENABLE; |
| 2085 | I915_WRITE(LPT_TRANSCONF, val); |
| 2086 | /* wait for PCH transcoder off, transcoder state */ |
| 2087 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
| 2088 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
| 2089 | |
| 2090 | /* Workaround: clear timing override bit. */ |
| 2091 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
| 2092 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
| 2093 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
| 2094 | } |
| 2095 | |
| 2096 | /** |
| 2097 | * intel_enable_pipe - enable a pipe, asserting requirements |
| 2098 | * @crtc: crtc responsible for the pipe |
| 2099 | * |
| 2100 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
| 2101 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
| 2102 | */ |
| 2103 | static void intel_enable_pipe(struct intel_crtc *crtc) |
| 2104 | { |
| 2105 | struct drm_device *dev = crtc->base.dev; |
| 2106 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2107 | enum pipe pipe = crtc->pipe; |
| 2108 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
| 2109 | enum pipe pch_transcoder; |
| 2110 | i915_reg_t reg; |
| 2111 | u32 val; |
| 2112 | |
| 2113 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
| 2114 | |
| 2115 | assert_planes_disabled(dev_priv, pipe); |
| 2116 | assert_cursor_disabled(dev_priv, pipe); |
| 2117 | assert_sprites_disabled(dev_priv, pipe); |
| 2118 | |
| 2119 | if (HAS_PCH_LPT(dev_priv->dev)) |
| 2120 | pch_transcoder = TRANSCODER_A; |
| 2121 | else |
| 2122 | pch_transcoder = pipe; |
| 2123 | |
| 2124 | /* |
| 2125 | * A pipe without a PLL won't actually be able to drive bits from |
| 2126 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't |
| 2127 | * need the check. |
| 2128 | */ |
| 2129 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) |
| 2130 | if (crtc->config->has_dsi_encoder) |
| 2131 | assert_dsi_pll_enabled(dev_priv); |
| 2132 | else |
| 2133 | assert_pll_enabled(dev_priv, pipe); |
| 2134 | else { |
| 2135 | if (crtc->config->has_pch_encoder) { |
| 2136 | /* if driving the PCH, we need FDI enabled */ |
| 2137 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
| 2138 | assert_fdi_tx_pll_enabled(dev_priv, |
| 2139 | (enum pipe) cpu_transcoder); |
| 2140 | } |
| 2141 | /* FIXME: assert CPU port conditions for SNB+ */ |
| 2142 | } |
| 2143 | |
| 2144 | reg = PIPECONF(cpu_transcoder); |
| 2145 | val = I915_READ(reg); |
| 2146 | if (val & PIPECONF_ENABLE) { |
| 2147 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
| 2148 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); |
| 2149 | return; |
| 2150 | } |
| 2151 | |
| 2152 | I915_WRITE(reg, val | PIPECONF_ENABLE); |
| 2153 | POSTING_READ(reg); |
| 2154 | |
| 2155 | /* |
| 2156 | * Until the pipe starts DSL will read as 0, which would cause |
| 2157 | * an apparent vblank timestamp jump, which messes up also the |
| 2158 | * frame count when it's derived from the timestamps. So let's |
| 2159 | * wait for the pipe to start properly before we call |
| 2160 | * drm_crtc_vblank_on() |
| 2161 | */ |
| 2162 | if (dev->max_vblank_count == 0 && |
| 2163 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) |
| 2164 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); |
| 2165 | } |
| 2166 | |
| 2167 | /** |
| 2168 | * intel_disable_pipe - disable a pipe, asserting requirements |
| 2169 | * @crtc: crtc whose pipes is to be disabled |
| 2170 | * |
| 2171 | * Disable the pipe of @crtc, making sure that various hardware |
| 2172 | * specific requirements are met, if applicable, e.g. plane |
| 2173 | * disabled, panel fitter off, etc. |
| 2174 | * |
| 2175 | * Will wait until the pipe has shut down before returning. |
| 2176 | */ |
| 2177 | static void intel_disable_pipe(struct intel_crtc *crtc) |
| 2178 | { |
| 2179 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
| 2180 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
| 2181 | enum pipe pipe = crtc->pipe; |
| 2182 | i915_reg_t reg; |
| 2183 | u32 val; |
| 2184 | |
| 2185 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
| 2186 | |
| 2187 | /* |
| 2188 | * Make sure planes won't keep trying to pump pixels to us, |
| 2189 | * or we might hang the display. |
| 2190 | */ |
| 2191 | assert_planes_disabled(dev_priv, pipe); |
| 2192 | assert_cursor_disabled(dev_priv, pipe); |
| 2193 | assert_sprites_disabled(dev_priv, pipe); |
| 2194 | |
| 2195 | reg = PIPECONF(cpu_transcoder); |
| 2196 | val = I915_READ(reg); |
| 2197 | if ((val & PIPECONF_ENABLE) == 0) |
| 2198 | return; |
| 2199 | |
| 2200 | /* |
| 2201 | * Double wide has implications for planes |
| 2202 | * so best keep it disabled when not needed. |
| 2203 | */ |
| 2204 | if (crtc->config->double_wide) |
| 2205 | val &= ~PIPECONF_DOUBLE_WIDE; |
| 2206 | |
| 2207 | /* Don't disable pipe or pipe PLLs if needed */ |
| 2208 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
| 2209 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) |
| 2210 | val &= ~PIPECONF_ENABLE; |
| 2211 | |
| 2212 | I915_WRITE(reg, val); |
| 2213 | if ((val & PIPECONF_ENABLE) == 0) |
| 2214 | intel_wait_for_pipe_off(crtc); |
| 2215 | } |
| 2216 | |
| 2217 | static bool need_vtd_wa(struct drm_device *dev) |
| 2218 | { |
| 2219 | #ifdef CONFIG_INTEL_IOMMU |
| 2220 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) |
| 2221 | return true; |
| 2222 | #endif |
| 2223 | return false; |
| 2224 | } |
| 2225 | |
| 2226 | unsigned int |
| 2227 | intel_tile_height(struct drm_device *dev, uint32_t pixel_format, |
| 2228 | uint64_t fb_format_modifier, unsigned int plane) |
| 2229 | { |
| 2230 | unsigned int tile_height; |
| 2231 | uint32_t pixel_bytes; |
| 2232 | |
| 2233 | switch (fb_format_modifier) { |
| 2234 | case DRM_FORMAT_MOD_NONE: |
| 2235 | tile_height = 1; |
| 2236 | break; |
| 2237 | case I915_FORMAT_MOD_X_TILED: |
| 2238 | tile_height = IS_GEN2(dev) ? 16 : 8; |
| 2239 | break; |
| 2240 | case I915_FORMAT_MOD_Y_TILED: |
| 2241 | tile_height = 32; |
| 2242 | break; |
| 2243 | case I915_FORMAT_MOD_Yf_TILED: |
| 2244 | pixel_bytes = drm_format_plane_cpp(pixel_format, plane); |
| 2245 | switch (pixel_bytes) { |
| 2246 | default: |
| 2247 | case 1: |
| 2248 | tile_height = 64; |
| 2249 | break; |
| 2250 | case 2: |
| 2251 | case 4: |
| 2252 | tile_height = 32; |
| 2253 | break; |
| 2254 | case 8: |
| 2255 | tile_height = 16; |
| 2256 | break; |
| 2257 | case 16: |
| 2258 | WARN_ONCE(1, |
| 2259 | "128-bit pixels are not supported for display!"); |
| 2260 | tile_height = 16; |
| 2261 | break; |
| 2262 | } |
| 2263 | break; |
| 2264 | default: |
| 2265 | MISSING_CASE(fb_format_modifier); |
| 2266 | tile_height = 1; |
| 2267 | break; |
| 2268 | } |
| 2269 | |
| 2270 | return tile_height; |
| 2271 | } |
| 2272 | |
| 2273 | unsigned int |
| 2274 | intel_fb_align_height(struct drm_device *dev, unsigned int height, |
| 2275 | uint32_t pixel_format, uint64_t fb_format_modifier) |
| 2276 | { |
| 2277 | return ALIGN(height, intel_tile_height(dev, pixel_format, |
| 2278 | fb_format_modifier, 0)); |
| 2279 | } |
| 2280 | |
| 2281 | static void |
| 2282 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb, |
| 2283 | const struct drm_plane_state *plane_state) |
| 2284 | { |
| 2285 | struct intel_rotation_info *info = &view->params.rotation_info; |
| 2286 | unsigned int tile_height, tile_pitch; |
| 2287 | |
| 2288 | *view = i915_ggtt_view_normal; |
| 2289 | |
| 2290 | if (!plane_state) |
| 2291 | return; |
| 2292 | |
| 2293 | if (!intel_rotation_90_or_270(plane_state->rotation)) |
| 2294 | return; |
| 2295 | |
| 2296 | *view = i915_ggtt_view_rotated; |
| 2297 | |
| 2298 | info->height = fb->height; |
| 2299 | info->pixel_format = fb->pixel_format; |
| 2300 | info->pitch = fb->pitches[0]; |
| 2301 | info->uv_offset = fb->offsets[1]; |
| 2302 | info->fb_modifier = fb->modifier[0]; |
| 2303 | |
| 2304 | tile_height = intel_tile_height(fb->dev, fb->pixel_format, |
| 2305 | fb->modifier[0], 0); |
| 2306 | tile_pitch = PAGE_SIZE / tile_height; |
| 2307 | info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch); |
| 2308 | info->height_pages = DIV_ROUND_UP(fb->height, tile_height); |
| 2309 | info->size = info->width_pages * info->height_pages * PAGE_SIZE; |
| 2310 | |
| 2311 | if (info->pixel_format == DRM_FORMAT_NV12) { |
| 2312 | tile_height = intel_tile_height(fb->dev, fb->pixel_format, |
| 2313 | fb->modifier[0], 1); |
| 2314 | tile_pitch = PAGE_SIZE / tile_height; |
| 2315 | info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch); |
| 2316 | info->height_pages_uv = DIV_ROUND_UP(fb->height / 2, |
| 2317 | tile_height); |
| 2318 | info->size_uv = info->width_pages_uv * info->height_pages_uv * |
| 2319 | PAGE_SIZE; |
| 2320 | } |
| 2321 | } |
| 2322 | |
| 2323 | static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv) |
| 2324 | { |
| 2325 | if (INTEL_INFO(dev_priv)->gen >= 9) |
| 2326 | return 256 * 1024; |
| 2327 | else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || |
| 2328 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
| 2329 | return 128 * 1024; |
| 2330 | else if (INTEL_INFO(dev_priv)->gen >= 4) |
| 2331 | return 4 * 1024; |
| 2332 | else |
| 2333 | return 0; |
| 2334 | } |
| 2335 | |
| 2336 | int |
| 2337 | intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
| 2338 | struct drm_framebuffer *fb, |
| 2339 | const struct drm_plane_state *plane_state) |
| 2340 | { |
| 2341 | struct drm_device *dev = fb->dev; |
| 2342 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2343 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
| 2344 | struct i915_ggtt_view view; |
| 2345 | u32 alignment; |
| 2346 | int ret; |
| 2347 | |
| 2348 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 2349 | |
| 2350 | switch (fb->modifier[0]) { |
| 2351 | case DRM_FORMAT_MOD_NONE: |
| 2352 | alignment = intel_linear_alignment(dev_priv); |
| 2353 | break; |
| 2354 | case I915_FORMAT_MOD_X_TILED: |
| 2355 | if (INTEL_INFO(dev)->gen >= 9) |
| 2356 | alignment = 256 * 1024; |
| 2357 | else { |
| 2358 | /* pin() will align the object as required by fence */ |
| 2359 | alignment = 0; |
| 2360 | } |
| 2361 | break; |
| 2362 | case I915_FORMAT_MOD_Y_TILED: |
| 2363 | case I915_FORMAT_MOD_Yf_TILED: |
| 2364 | if (WARN_ONCE(INTEL_INFO(dev)->gen < 9, |
| 2365 | "Y tiling bo slipped through, driver bug!\n")) |
| 2366 | return -EINVAL; |
| 2367 | alignment = 1 * 1024 * 1024; |
| 2368 | break; |
| 2369 | default: |
| 2370 | MISSING_CASE(fb->modifier[0]); |
| 2371 | return -EINVAL; |
| 2372 | } |
| 2373 | |
| 2374 | intel_fill_fb_ggtt_view(&view, fb, plane_state); |
| 2375 | |
| 2376 | /* Note that the w/a also requires 64 PTE of padding following the |
| 2377 | * bo. We currently fill all unused PTE with the shadow page and so |
| 2378 | * we should always have valid PTE following the scanout preventing |
| 2379 | * the VT-d warning. |
| 2380 | */ |
| 2381 | if (need_vtd_wa(dev) && alignment < 256 * 1024) |
| 2382 | alignment = 256 * 1024; |
| 2383 | |
| 2384 | /* |
| 2385 | * Global gtt pte registers are special registers which actually forward |
| 2386 | * writes to a chunk of system memory. Which means that there is no risk |
| 2387 | * that the register values disappear as soon as we call |
| 2388 | * intel_runtime_pm_put(), so it is correct to wrap only the |
| 2389 | * pin/unpin/fence and not more. |
| 2390 | */ |
| 2391 | intel_runtime_pm_get(dev_priv); |
| 2392 | |
| 2393 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, |
| 2394 | &view); |
| 2395 | if (ret) |
| 2396 | goto err_pm; |
| 2397 | |
| 2398 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
| 2399 | * fence, whereas 965+ only requires a fence if using |
| 2400 | * framebuffer compression. For simplicity, we always install |
| 2401 | * a fence as the cost is not that onerous. |
| 2402 | */ |
| 2403 | if (view.type == I915_GGTT_VIEW_NORMAL) { |
| 2404 | ret = i915_gem_object_get_fence(obj); |
| 2405 | if (ret == -EDEADLK) { |
| 2406 | /* |
| 2407 | * -EDEADLK means there are no free fences |
| 2408 | * no pending flips. |
| 2409 | * |
| 2410 | * This is propagated to atomic, but it uses |
| 2411 | * -EDEADLK to force a locking recovery, so |
| 2412 | * change the returned error to -EBUSY. |
| 2413 | */ |
| 2414 | ret = -EBUSY; |
| 2415 | goto err_unpin; |
| 2416 | } else if (ret) |
| 2417 | goto err_unpin; |
| 2418 | |
| 2419 | i915_gem_object_pin_fence(obj); |
| 2420 | } |
| 2421 | |
| 2422 | intel_runtime_pm_put(dev_priv); |
| 2423 | return 0; |
| 2424 | |
| 2425 | err_unpin: |
| 2426 | i915_gem_object_unpin_from_display_plane(obj, &view); |
| 2427 | err_pm: |
| 2428 | intel_runtime_pm_put(dev_priv); |
| 2429 | return ret; |
| 2430 | } |
| 2431 | |
| 2432 | static void intel_unpin_fb_obj(struct drm_framebuffer *fb, |
| 2433 | const struct drm_plane_state *plane_state) |
| 2434 | { |
| 2435 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
| 2436 | struct i915_ggtt_view view; |
| 2437 | |
| 2438 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
| 2439 | |
| 2440 | intel_fill_fb_ggtt_view(&view, fb, plane_state); |
| 2441 | |
| 2442 | if (view.type == I915_GGTT_VIEW_NORMAL) |
| 2443 | i915_gem_object_unpin_fence(obj); |
| 2444 | |
| 2445 | i915_gem_object_unpin_from_display_plane(obj, &view); |
| 2446 | } |
| 2447 | |
| 2448 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
| 2449 | * is assumed to be a power-of-two. */ |
| 2450 | unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv, |
| 2451 | int *x, int *y, |
| 2452 | unsigned int tiling_mode, |
| 2453 | unsigned int cpp, |
| 2454 | unsigned int pitch) |
| 2455 | { |
| 2456 | if (tiling_mode != I915_TILING_NONE) { |
| 2457 | unsigned int tile_rows, tiles; |
| 2458 | |
| 2459 | tile_rows = *y / 8; |
| 2460 | *y %= 8; |
| 2461 | |
| 2462 | tiles = *x / (512/cpp); |
| 2463 | *x %= 512/cpp; |
| 2464 | |
| 2465 | return tile_rows * pitch * 8 + tiles * 4096; |
| 2466 | } else { |
| 2467 | unsigned int alignment = intel_linear_alignment(dev_priv) - 1; |
| 2468 | unsigned int offset; |
| 2469 | |
| 2470 | offset = *y * pitch + *x * cpp; |
| 2471 | *y = (offset & alignment) / pitch; |
| 2472 | *x = ((offset & alignment) - *y * pitch) / cpp; |
| 2473 | return offset & ~alignment; |
| 2474 | } |
| 2475 | } |
| 2476 | |
| 2477 | static int i9xx_format_to_fourcc(int format) |
| 2478 | { |
| 2479 | switch (format) { |
| 2480 | case DISPPLANE_8BPP: |
| 2481 | return DRM_FORMAT_C8; |
| 2482 | case DISPPLANE_BGRX555: |
| 2483 | return DRM_FORMAT_XRGB1555; |
| 2484 | case DISPPLANE_BGRX565: |
| 2485 | return DRM_FORMAT_RGB565; |
| 2486 | default: |
| 2487 | case DISPPLANE_BGRX888: |
| 2488 | return DRM_FORMAT_XRGB8888; |
| 2489 | case DISPPLANE_RGBX888: |
| 2490 | return DRM_FORMAT_XBGR8888; |
| 2491 | case DISPPLANE_BGRX101010: |
| 2492 | return DRM_FORMAT_XRGB2101010; |
| 2493 | case DISPPLANE_RGBX101010: |
| 2494 | return DRM_FORMAT_XBGR2101010; |
| 2495 | } |
| 2496 | } |
| 2497 | |
| 2498 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
| 2499 | { |
| 2500 | switch (format) { |
| 2501 | case PLANE_CTL_FORMAT_RGB_565: |
| 2502 | return DRM_FORMAT_RGB565; |
| 2503 | default: |
| 2504 | case PLANE_CTL_FORMAT_XRGB_8888: |
| 2505 | if (rgb_order) { |
| 2506 | if (alpha) |
| 2507 | return DRM_FORMAT_ABGR8888; |
| 2508 | else |
| 2509 | return DRM_FORMAT_XBGR8888; |
| 2510 | } else { |
| 2511 | if (alpha) |
| 2512 | return DRM_FORMAT_ARGB8888; |
| 2513 | else |
| 2514 | return DRM_FORMAT_XRGB8888; |
| 2515 | } |
| 2516 | case PLANE_CTL_FORMAT_XRGB_2101010: |
| 2517 | if (rgb_order) |
| 2518 | return DRM_FORMAT_XBGR2101010; |
| 2519 | else |
| 2520 | return DRM_FORMAT_XRGB2101010; |
| 2521 | } |
| 2522 | } |
| 2523 | |
| 2524 | static bool |
| 2525 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
| 2526 | struct intel_initial_plane_config *plane_config) |
| 2527 | { |
| 2528 | struct drm_device *dev = crtc->base.dev; |
| 2529 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 2530 | struct drm_i915_gem_object *obj = NULL; |
| 2531 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
| 2532 | struct drm_framebuffer *fb = &plane_config->fb->base; |
| 2533 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
| 2534 | u32 size_aligned = round_up(plane_config->base + plane_config->size, |
| 2535 | PAGE_SIZE); |
| 2536 | |
| 2537 | size_aligned -= base_aligned; |
| 2538 | |
| 2539 | if (plane_config->size == 0) |
| 2540 | return false; |
| 2541 | |
| 2542 | /* If the FB is too big, just don't use it since fbdev is not very |
| 2543 | * important and we should probably use that space with FBC or other |
| 2544 | * features. */ |
| 2545 | if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size) |
| 2546 | return false; |
| 2547 | |
| 2548 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
| 2549 | base_aligned, |
| 2550 | base_aligned, |
| 2551 | size_aligned); |
| 2552 | if (!obj) |
| 2553 | return false; |
| 2554 | |
| 2555 | obj->tiling_mode = plane_config->tiling; |
| 2556 | if (obj->tiling_mode == I915_TILING_X) |
| 2557 | obj->stride = fb->pitches[0]; |
| 2558 | |
| 2559 | mode_cmd.pixel_format = fb->pixel_format; |
| 2560 | mode_cmd.width = fb->width; |
| 2561 | mode_cmd.height = fb->height; |
| 2562 | mode_cmd.pitches[0] = fb->pitches[0]; |
| 2563 | mode_cmd.modifier[0] = fb->modifier[0]; |
| 2564 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; |
| 2565 | |
| 2566 | mutex_lock(&dev->struct_mutex); |
| 2567 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
| 2568 | &mode_cmd, obj)) { |
| 2569 | DRM_DEBUG_KMS("intel fb init failed\n"); |
| 2570 | goto out_unref_obj; |
| 2571 | } |
| 2572 | mutex_unlock(&dev->struct_mutex); |
| 2573 | |
| 2574 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
| 2575 | return true; |
| 2576 | |
| 2577 | out_unref_obj: |
| 2578 | drm_gem_object_unreference(&obj->base); |
| 2579 | mutex_unlock(&dev->struct_mutex); |
| 2580 | return false; |
| 2581 | } |
| 2582 | |
| 2583 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
| 2584 | static void |
| 2585 | update_state_fb(struct drm_plane *plane) |
| 2586 | { |
| 2587 | if (plane->fb == plane->state->fb) |
| 2588 | return; |
| 2589 | |
| 2590 | if (plane->state->fb) |
| 2591 | drm_framebuffer_unreference(plane->state->fb); |
| 2592 | plane->state->fb = plane->fb; |
| 2593 | if (plane->state->fb) |
| 2594 | drm_framebuffer_reference(plane->state->fb); |
| 2595 | } |
| 2596 | |
| 2597 | static void |
| 2598 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
| 2599 | struct intel_initial_plane_config *plane_config) |
| 2600 | { |
| 2601 | struct drm_device *dev = intel_crtc->base.dev; |
| 2602 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2603 | struct drm_crtc *c; |
| 2604 | struct intel_crtc *i; |
| 2605 | struct drm_i915_gem_object *obj; |
| 2606 | struct drm_plane *primary = intel_crtc->base.primary; |
| 2607 | struct drm_plane_state *plane_state = primary->state; |
| 2608 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
| 2609 | struct intel_plane *intel_plane = to_intel_plane(primary); |
| 2610 | struct intel_plane_state *intel_state = |
| 2611 | to_intel_plane_state(plane_state); |
| 2612 | struct drm_framebuffer *fb; |
| 2613 | |
| 2614 | if (!plane_config->fb) |
| 2615 | return; |
| 2616 | |
| 2617 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
| 2618 | fb = &plane_config->fb->base; |
| 2619 | goto valid_fb; |
| 2620 | } |
| 2621 | |
| 2622 | kfree(plane_config->fb); |
| 2623 | |
| 2624 | /* |
| 2625 | * Failed to alloc the obj, check to see if we should share |
| 2626 | * an fb with another CRTC instead |
| 2627 | */ |
| 2628 | for_each_crtc(dev, c) { |
| 2629 | i = to_intel_crtc(c); |
| 2630 | |
| 2631 | if (c == &intel_crtc->base) |
| 2632 | continue; |
| 2633 | |
| 2634 | if (!i->active) |
| 2635 | continue; |
| 2636 | |
| 2637 | fb = c->primary->fb; |
| 2638 | if (!fb) |
| 2639 | continue; |
| 2640 | |
| 2641 | obj = intel_fb_obj(fb); |
| 2642 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
| 2643 | drm_framebuffer_reference(fb); |
| 2644 | goto valid_fb; |
| 2645 | } |
| 2646 | } |
| 2647 | |
| 2648 | /* |
| 2649 | * We've failed to reconstruct the BIOS FB. Current display state |
| 2650 | * indicates that the primary plane is visible, but has a NULL FB, |
| 2651 | * which will lead to problems later if we don't fix it up. The |
| 2652 | * simplest solution is to just disable the primary plane now and |
| 2653 | * pretend the BIOS never had it enabled. |
| 2654 | */ |
| 2655 | to_intel_plane_state(plane_state)->visible = false; |
| 2656 | crtc_state->plane_mask &= ~(1 << drm_plane_index(primary)); |
| 2657 | intel_pre_disable_primary(&intel_crtc->base); |
| 2658 | intel_plane->disable_plane(primary, &intel_crtc->base); |
| 2659 | |
| 2660 | return; |
| 2661 | |
| 2662 | valid_fb: |
| 2663 | plane_state->src_x = 0; |
| 2664 | plane_state->src_y = 0; |
| 2665 | plane_state->src_w = fb->width << 16; |
| 2666 | plane_state->src_h = fb->height << 16; |
| 2667 | |
| 2668 | plane_state->crtc_x = 0; |
| 2669 | plane_state->crtc_y = 0; |
| 2670 | plane_state->crtc_w = fb->width; |
| 2671 | plane_state->crtc_h = fb->height; |
| 2672 | |
| 2673 | intel_state->src.x1 = plane_state->src_x; |
| 2674 | intel_state->src.y1 = plane_state->src_y; |
| 2675 | intel_state->src.x2 = plane_state->src_x + plane_state->src_w; |
| 2676 | intel_state->src.y2 = plane_state->src_y + plane_state->src_h; |
| 2677 | intel_state->dst.x1 = plane_state->crtc_x; |
| 2678 | intel_state->dst.y1 = plane_state->crtc_y; |
| 2679 | intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w; |
| 2680 | intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h; |
| 2681 | |
| 2682 | obj = intel_fb_obj(fb); |
| 2683 | if (obj->tiling_mode != I915_TILING_NONE) |
| 2684 | dev_priv->preserve_bios_swizzle = true; |
| 2685 | |
| 2686 | drm_framebuffer_reference(fb); |
| 2687 | primary->fb = primary->state->fb = fb; |
| 2688 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
| 2689 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
| 2690 | obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit; |
| 2691 | } |
| 2692 | |
| 2693 | static void i9xx_update_primary_plane(struct drm_plane *primary, |
| 2694 | const struct intel_crtc_state *crtc_state, |
| 2695 | const struct intel_plane_state *plane_state) |
| 2696 | { |
| 2697 | struct drm_device *dev = primary->dev; |
| 2698 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2699 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
| 2700 | struct drm_framebuffer *fb = plane_state->base.fb; |
| 2701 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
| 2702 | int plane = intel_crtc->plane; |
| 2703 | unsigned long linear_offset; |
| 2704 | int x = plane_state->src.x1 >> 16; |
| 2705 | int y = plane_state->src.y1 >> 16; |
| 2706 | u32 dspcntr; |
| 2707 | i915_reg_t reg = DSPCNTR(plane); |
| 2708 | int pixel_size; |
| 2709 | |
| 2710 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
| 2711 | |
| 2712 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
| 2713 | |
| 2714 | dspcntr |= DISPLAY_PLANE_ENABLE; |
| 2715 | |
| 2716 | if (INTEL_INFO(dev)->gen < 4) { |
| 2717 | if (intel_crtc->pipe == PIPE_B) |
| 2718 | dspcntr |= DISPPLANE_SEL_PIPE_B; |
| 2719 | |
| 2720 | /* pipesrc and dspsize control the size that is scaled from, |
| 2721 | * which should always be the user's requested size. |
| 2722 | */ |
| 2723 | I915_WRITE(DSPSIZE(plane), |
| 2724 | ((crtc_state->pipe_src_h - 1) << 16) | |
| 2725 | (crtc_state->pipe_src_w - 1)); |
| 2726 | I915_WRITE(DSPPOS(plane), 0); |
| 2727 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
| 2728 | I915_WRITE(PRIMSIZE(plane), |
| 2729 | ((crtc_state->pipe_src_h - 1) << 16) | |
| 2730 | (crtc_state->pipe_src_w - 1)); |
| 2731 | I915_WRITE(PRIMPOS(plane), 0); |
| 2732 | I915_WRITE(PRIMCNSTALPHA(plane), 0); |
| 2733 | } |
| 2734 | |
| 2735 | switch (fb->pixel_format) { |
| 2736 | case DRM_FORMAT_C8: |
| 2737 | dspcntr |= DISPPLANE_8BPP; |
| 2738 | break; |
| 2739 | case DRM_FORMAT_XRGB1555: |
| 2740 | dspcntr |= DISPPLANE_BGRX555; |
| 2741 | break; |
| 2742 | case DRM_FORMAT_RGB565: |
| 2743 | dspcntr |= DISPPLANE_BGRX565; |
| 2744 | break; |
| 2745 | case DRM_FORMAT_XRGB8888: |
| 2746 | dspcntr |= DISPPLANE_BGRX888; |
| 2747 | break; |
| 2748 | case DRM_FORMAT_XBGR8888: |
| 2749 | dspcntr |= DISPPLANE_RGBX888; |
| 2750 | break; |
| 2751 | case DRM_FORMAT_XRGB2101010: |
| 2752 | dspcntr |= DISPPLANE_BGRX101010; |
| 2753 | break; |
| 2754 | case DRM_FORMAT_XBGR2101010: |
| 2755 | dspcntr |= DISPPLANE_RGBX101010; |
| 2756 | break; |
| 2757 | default: |
| 2758 | BUG(); |
| 2759 | } |
| 2760 | |
| 2761 | if (INTEL_INFO(dev)->gen >= 4 && |
| 2762 | obj->tiling_mode != I915_TILING_NONE) |
| 2763 | dspcntr |= DISPPLANE_TILED; |
| 2764 | |
| 2765 | if (IS_G4X(dev)) |
| 2766 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
| 2767 | |
| 2768 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
| 2769 | |
| 2770 | if (INTEL_INFO(dev)->gen >= 4) { |
| 2771 | intel_crtc->dspaddr_offset = |
| 2772 | intel_gen4_compute_page_offset(dev_priv, |
| 2773 | &x, &y, obj->tiling_mode, |
| 2774 | pixel_size, |
| 2775 | fb->pitches[0]); |
| 2776 | linear_offset -= intel_crtc->dspaddr_offset; |
| 2777 | } else { |
| 2778 | intel_crtc->dspaddr_offset = linear_offset; |
| 2779 | } |
| 2780 | |
| 2781 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) { |
| 2782 | dspcntr |= DISPPLANE_ROTATE_180; |
| 2783 | |
| 2784 | x += (crtc_state->pipe_src_w - 1); |
| 2785 | y += (crtc_state->pipe_src_h - 1); |
| 2786 | |
| 2787 | /* Finding the last pixel of the last line of the display |
| 2788 | data and adding to linear_offset*/ |
| 2789 | linear_offset += |
| 2790 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
| 2791 | (crtc_state->pipe_src_w - 1) * pixel_size; |
| 2792 | } |
| 2793 | |
| 2794 | intel_crtc->adjusted_x = x; |
| 2795 | intel_crtc->adjusted_y = y; |
| 2796 | |
| 2797 | I915_WRITE(reg, dspcntr); |
| 2798 | |
| 2799 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
| 2800 | if (INTEL_INFO(dev)->gen >= 4) { |
| 2801 | I915_WRITE(DSPSURF(plane), |
| 2802 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
| 2803 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
| 2804 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
| 2805 | } else |
| 2806 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
| 2807 | POSTING_READ(reg); |
| 2808 | } |
| 2809 | |
| 2810 | static void i9xx_disable_primary_plane(struct drm_plane *primary, |
| 2811 | struct drm_crtc *crtc) |
| 2812 | { |
| 2813 | struct drm_device *dev = crtc->dev; |
| 2814 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2815 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2816 | int plane = intel_crtc->plane; |
| 2817 | |
| 2818 | I915_WRITE(DSPCNTR(plane), 0); |
| 2819 | if (INTEL_INFO(dev_priv)->gen >= 4) |
| 2820 | I915_WRITE(DSPSURF(plane), 0); |
| 2821 | else |
| 2822 | I915_WRITE(DSPADDR(plane), 0); |
| 2823 | POSTING_READ(DSPCNTR(plane)); |
| 2824 | } |
| 2825 | |
| 2826 | static void ironlake_update_primary_plane(struct drm_plane *primary, |
| 2827 | const struct intel_crtc_state *crtc_state, |
| 2828 | const struct intel_plane_state *plane_state) |
| 2829 | { |
| 2830 | struct drm_device *dev = primary->dev; |
| 2831 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2832 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
| 2833 | struct drm_framebuffer *fb = plane_state->base.fb; |
| 2834 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
| 2835 | int plane = intel_crtc->plane; |
| 2836 | unsigned long linear_offset; |
| 2837 | u32 dspcntr; |
| 2838 | i915_reg_t reg = DSPCNTR(plane); |
| 2839 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
| 2840 | int x = plane_state->src.x1 >> 16; |
| 2841 | int y = plane_state->src.y1 >> 16; |
| 2842 | |
| 2843 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
| 2844 | dspcntr |= DISPLAY_PLANE_ENABLE; |
| 2845 | |
| 2846 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
| 2847 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; |
| 2848 | |
| 2849 | switch (fb->pixel_format) { |
| 2850 | case DRM_FORMAT_C8: |
| 2851 | dspcntr |= DISPPLANE_8BPP; |
| 2852 | break; |
| 2853 | case DRM_FORMAT_RGB565: |
| 2854 | dspcntr |= DISPPLANE_BGRX565; |
| 2855 | break; |
| 2856 | case DRM_FORMAT_XRGB8888: |
| 2857 | dspcntr |= DISPPLANE_BGRX888; |
| 2858 | break; |
| 2859 | case DRM_FORMAT_XBGR8888: |
| 2860 | dspcntr |= DISPPLANE_RGBX888; |
| 2861 | break; |
| 2862 | case DRM_FORMAT_XRGB2101010: |
| 2863 | dspcntr |= DISPPLANE_BGRX101010; |
| 2864 | break; |
| 2865 | case DRM_FORMAT_XBGR2101010: |
| 2866 | dspcntr |= DISPPLANE_RGBX101010; |
| 2867 | break; |
| 2868 | default: |
| 2869 | BUG(); |
| 2870 | } |
| 2871 | |
| 2872 | if (obj->tiling_mode != I915_TILING_NONE) |
| 2873 | dspcntr |= DISPPLANE_TILED; |
| 2874 | |
| 2875 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
| 2876 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
| 2877 | |
| 2878 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
| 2879 | intel_crtc->dspaddr_offset = |
| 2880 | intel_gen4_compute_page_offset(dev_priv, |
| 2881 | &x, &y, obj->tiling_mode, |
| 2882 | pixel_size, |
| 2883 | fb->pitches[0]); |
| 2884 | linear_offset -= intel_crtc->dspaddr_offset; |
| 2885 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) { |
| 2886 | dspcntr |= DISPPLANE_ROTATE_180; |
| 2887 | |
| 2888 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { |
| 2889 | x += (crtc_state->pipe_src_w - 1); |
| 2890 | y += (crtc_state->pipe_src_h - 1); |
| 2891 | |
| 2892 | /* Finding the last pixel of the last line of the display |
| 2893 | data and adding to linear_offset*/ |
| 2894 | linear_offset += |
| 2895 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
| 2896 | (crtc_state->pipe_src_w - 1) * pixel_size; |
| 2897 | } |
| 2898 | } |
| 2899 | |
| 2900 | intel_crtc->adjusted_x = x; |
| 2901 | intel_crtc->adjusted_y = y; |
| 2902 | |
| 2903 | I915_WRITE(reg, dspcntr); |
| 2904 | |
| 2905 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
| 2906 | I915_WRITE(DSPSURF(plane), |
| 2907 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
| 2908 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
| 2909 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
| 2910 | } else { |
| 2911 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
| 2912 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
| 2913 | } |
| 2914 | POSTING_READ(reg); |
| 2915 | } |
| 2916 | |
| 2917 | u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier, |
| 2918 | uint32_t pixel_format) |
| 2919 | { |
| 2920 | u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8; |
| 2921 | |
| 2922 | /* |
| 2923 | * The stride is either expressed as a multiple of 64 bytes |
| 2924 | * chunks for linear buffers or in number of tiles for tiled |
| 2925 | * buffers. |
| 2926 | */ |
| 2927 | switch (fb_modifier) { |
| 2928 | case DRM_FORMAT_MOD_NONE: |
| 2929 | return 64; |
| 2930 | case I915_FORMAT_MOD_X_TILED: |
| 2931 | if (INTEL_INFO(dev)->gen == 2) |
| 2932 | return 128; |
| 2933 | return 512; |
| 2934 | case I915_FORMAT_MOD_Y_TILED: |
| 2935 | /* No need to check for old gens and Y tiling since this is |
| 2936 | * about the display engine and those will be blocked before |
| 2937 | * we get here. |
| 2938 | */ |
| 2939 | return 128; |
| 2940 | case I915_FORMAT_MOD_Yf_TILED: |
| 2941 | if (bits_per_pixel == 8) |
| 2942 | return 64; |
| 2943 | else |
| 2944 | return 128; |
| 2945 | default: |
| 2946 | MISSING_CASE(fb_modifier); |
| 2947 | return 64; |
| 2948 | } |
| 2949 | } |
| 2950 | |
| 2951 | u32 intel_plane_obj_offset(struct intel_plane *intel_plane, |
| 2952 | struct drm_i915_gem_object *obj, |
| 2953 | unsigned int plane) |
| 2954 | { |
| 2955 | struct i915_ggtt_view view; |
| 2956 | struct i915_vma *vma; |
| 2957 | u64 offset; |
| 2958 | |
| 2959 | intel_fill_fb_ggtt_view(&view, intel_plane->base.fb, |
| 2960 | intel_plane->base.state); |
| 2961 | |
| 2962 | vma = i915_gem_obj_to_ggtt_view(obj, &view); |
| 2963 | if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n", |
| 2964 | view.type)) |
| 2965 | return -1; |
| 2966 | |
| 2967 | offset = vma->node.start; |
| 2968 | |
| 2969 | if (plane == 1) { |
| 2970 | offset += vma->ggtt_view.params.rotation_info.uv_start_page * |
| 2971 | PAGE_SIZE; |
| 2972 | } |
| 2973 | |
| 2974 | WARN_ON(upper_32_bits(offset)); |
| 2975 | |
| 2976 | return lower_32_bits(offset); |
| 2977 | } |
| 2978 | |
| 2979 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
| 2980 | { |
| 2981 | struct drm_device *dev = intel_crtc->base.dev; |
| 2982 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2983 | |
| 2984 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); |
| 2985 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); |
| 2986 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); |
| 2987 | } |
| 2988 | |
| 2989 | /* |
| 2990 | * This function detaches (aka. unbinds) unused scalers in hardware |
| 2991 | */ |
| 2992 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
| 2993 | { |
| 2994 | struct intel_crtc_scaler_state *scaler_state; |
| 2995 | int i; |
| 2996 | |
| 2997 | scaler_state = &intel_crtc->config->scaler_state; |
| 2998 | |
| 2999 | /* loop through and disable scalers that aren't in use */ |
| 3000 | for (i = 0; i < intel_crtc->num_scalers; i++) { |
| 3001 | if (!scaler_state->scalers[i].in_use) |
| 3002 | skl_detach_scaler(intel_crtc, i); |
| 3003 | } |
| 3004 | } |
| 3005 | |
| 3006 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
| 3007 | { |
| 3008 | switch (pixel_format) { |
| 3009 | case DRM_FORMAT_C8: |
| 3010 | return PLANE_CTL_FORMAT_INDEXED; |
| 3011 | case DRM_FORMAT_RGB565: |
| 3012 | return PLANE_CTL_FORMAT_RGB_565; |
| 3013 | case DRM_FORMAT_XBGR8888: |
| 3014 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
| 3015 | case DRM_FORMAT_XRGB8888: |
| 3016 | return PLANE_CTL_FORMAT_XRGB_8888; |
| 3017 | /* |
| 3018 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers |
| 3019 | * to be already pre-multiplied. We need to add a knob (or a different |
| 3020 | * DRM_FORMAT) for user-space to configure that. |
| 3021 | */ |
| 3022 | case DRM_FORMAT_ABGR8888: |
| 3023 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
| 3024 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
| 3025 | case DRM_FORMAT_ARGB8888: |
| 3026 | return PLANE_CTL_FORMAT_XRGB_8888 | |
| 3027 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
| 3028 | case DRM_FORMAT_XRGB2101010: |
| 3029 | return PLANE_CTL_FORMAT_XRGB_2101010; |
| 3030 | case DRM_FORMAT_XBGR2101010: |
| 3031 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
| 3032 | case DRM_FORMAT_YUYV: |
| 3033 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
| 3034 | case DRM_FORMAT_YVYU: |
| 3035 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
| 3036 | case DRM_FORMAT_UYVY: |
| 3037 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
| 3038 | case DRM_FORMAT_VYUY: |
| 3039 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
| 3040 | default: |
| 3041 | MISSING_CASE(pixel_format); |
| 3042 | } |
| 3043 | |
| 3044 | return 0; |
| 3045 | } |
| 3046 | |
| 3047 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
| 3048 | { |
| 3049 | switch (fb_modifier) { |
| 3050 | case DRM_FORMAT_MOD_NONE: |
| 3051 | break; |
| 3052 | case I915_FORMAT_MOD_X_TILED: |
| 3053 | return PLANE_CTL_TILED_X; |
| 3054 | case I915_FORMAT_MOD_Y_TILED: |
| 3055 | return PLANE_CTL_TILED_Y; |
| 3056 | case I915_FORMAT_MOD_Yf_TILED: |
| 3057 | return PLANE_CTL_TILED_YF; |
| 3058 | default: |
| 3059 | MISSING_CASE(fb_modifier); |
| 3060 | } |
| 3061 | |
| 3062 | return 0; |
| 3063 | } |
| 3064 | |
| 3065 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
| 3066 | { |
| 3067 | switch (rotation) { |
| 3068 | case BIT(DRM_ROTATE_0): |
| 3069 | break; |
| 3070 | /* |
| 3071 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr |
| 3072 | * while i915 HW rotation is clockwise, thats why this swapping. |
| 3073 | */ |
| 3074 | case BIT(DRM_ROTATE_90): |
| 3075 | return PLANE_CTL_ROTATE_270; |
| 3076 | case BIT(DRM_ROTATE_180): |
| 3077 | return PLANE_CTL_ROTATE_180; |
| 3078 | case BIT(DRM_ROTATE_270): |
| 3079 | return PLANE_CTL_ROTATE_90; |
| 3080 | default: |
| 3081 | MISSING_CASE(rotation); |
| 3082 | } |
| 3083 | |
| 3084 | return 0; |
| 3085 | } |
| 3086 | |
| 3087 | static void skylake_update_primary_plane(struct drm_plane *plane, |
| 3088 | const struct intel_crtc_state *crtc_state, |
| 3089 | const struct intel_plane_state *plane_state) |
| 3090 | { |
| 3091 | struct drm_device *dev = plane->dev; |
| 3092 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3093 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
| 3094 | struct drm_framebuffer *fb = plane_state->base.fb; |
| 3095 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
| 3096 | int pipe = intel_crtc->pipe; |
| 3097 | u32 plane_ctl, stride_div, stride; |
| 3098 | u32 tile_height, plane_offset, plane_size; |
| 3099 | unsigned int rotation = plane_state->base.rotation; |
| 3100 | int x_offset, y_offset; |
| 3101 | u32 surf_addr; |
| 3102 | int scaler_id = plane_state->scaler_id; |
| 3103 | int src_x = plane_state->src.x1 >> 16; |
| 3104 | int src_y = plane_state->src.y1 >> 16; |
| 3105 | int src_w = drm_rect_width(&plane_state->src) >> 16; |
| 3106 | int src_h = drm_rect_height(&plane_state->src) >> 16; |
| 3107 | int dst_x = plane_state->dst.x1; |
| 3108 | int dst_y = plane_state->dst.y1; |
| 3109 | int dst_w = drm_rect_width(&plane_state->dst); |
| 3110 | int dst_h = drm_rect_height(&plane_state->dst); |
| 3111 | |
| 3112 | plane_ctl = PLANE_CTL_ENABLE | |
| 3113 | PLANE_CTL_PIPE_GAMMA_ENABLE | |
| 3114 | PLANE_CTL_PIPE_CSC_ENABLE; |
| 3115 | |
| 3116 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); |
| 3117 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); |
| 3118 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; |
| 3119 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
| 3120 | |
| 3121 | stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], |
| 3122 | fb->pixel_format); |
| 3123 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0); |
| 3124 | |
| 3125 | WARN_ON(drm_rect_width(&plane_state->src) == 0); |
| 3126 | |
| 3127 | if (intel_rotation_90_or_270(rotation)) { |
| 3128 | /* stride = Surface height in tiles */ |
| 3129 | tile_height = intel_tile_height(dev, fb->pixel_format, |
| 3130 | fb->modifier[0], 0); |
| 3131 | stride = DIV_ROUND_UP(fb->height, tile_height); |
| 3132 | x_offset = stride * tile_height - src_y - src_h; |
| 3133 | y_offset = src_x; |
| 3134 | plane_size = (src_w - 1) << 16 | (src_h - 1); |
| 3135 | } else { |
| 3136 | stride = fb->pitches[0] / stride_div; |
| 3137 | x_offset = src_x; |
| 3138 | y_offset = src_y; |
| 3139 | plane_size = (src_h - 1) << 16 | (src_w - 1); |
| 3140 | } |
| 3141 | plane_offset = y_offset << 16 | x_offset; |
| 3142 | |
| 3143 | intel_crtc->adjusted_x = x_offset; |
| 3144 | intel_crtc->adjusted_y = y_offset; |
| 3145 | |
| 3146 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
| 3147 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
| 3148 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); |
| 3149 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); |
| 3150 | |
| 3151 | if (scaler_id >= 0) { |
| 3152 | uint32_t ps_ctrl = 0; |
| 3153 | |
| 3154 | WARN_ON(!dst_w || !dst_h); |
| 3155 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | |
| 3156 | crtc_state->scaler_state.scalers[scaler_id].mode; |
| 3157 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); |
| 3158 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); |
| 3159 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); |
| 3160 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); |
| 3161 | I915_WRITE(PLANE_POS(pipe, 0), 0); |
| 3162 | } else { |
| 3163 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); |
| 3164 | } |
| 3165 | |
| 3166 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
| 3167 | |
| 3168 | POSTING_READ(PLANE_SURF(pipe, 0)); |
| 3169 | } |
| 3170 | |
| 3171 | static void skylake_disable_primary_plane(struct drm_plane *primary, |
| 3172 | struct drm_crtc *crtc) |
| 3173 | { |
| 3174 | struct drm_device *dev = crtc->dev; |
| 3175 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3176 | int pipe = to_intel_crtc(crtc)->pipe; |
| 3177 | |
| 3178 | if (dev_priv->fbc.deactivate) |
| 3179 | dev_priv->fbc.deactivate(dev_priv); |
| 3180 | |
| 3181 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
| 3182 | I915_WRITE(PLANE_SURF(pipe, 0), 0); |
| 3183 | POSTING_READ(PLANE_SURF(pipe, 0)); |
| 3184 | } |
| 3185 | |
| 3186 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
| 3187 | static int |
| 3188 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
| 3189 | int x, int y, enum mode_set_atomic state) |
| 3190 | { |
| 3191 | /* Support for kgdboc is disabled, this needs a major rework. */ |
| 3192 | DRM_ERROR("legacy panic handler not supported any more.\n"); |
| 3193 | |
| 3194 | return -ENODEV; |
| 3195 | } |
| 3196 | |
| 3197 | static void intel_complete_page_flips(struct drm_device *dev) |
| 3198 | { |
| 3199 | struct drm_crtc *crtc; |
| 3200 | |
| 3201 | for_each_crtc(dev, crtc) { |
| 3202 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3203 | enum plane plane = intel_crtc->plane; |
| 3204 | |
| 3205 | intel_prepare_page_flip(dev, plane); |
| 3206 | intel_finish_page_flip_plane(dev, plane); |
| 3207 | } |
| 3208 | } |
| 3209 | |
| 3210 | static void intel_update_primary_planes(struct drm_device *dev) |
| 3211 | { |
| 3212 | struct drm_crtc *crtc; |
| 3213 | |
| 3214 | for_each_crtc(dev, crtc) { |
| 3215 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
| 3216 | struct intel_plane_state *plane_state; |
| 3217 | |
| 3218 | drm_modeset_lock_crtc(crtc, &plane->base); |
| 3219 | plane_state = to_intel_plane_state(plane->base.state); |
| 3220 | |
| 3221 | if (plane_state->visible) |
| 3222 | plane->update_plane(&plane->base, |
| 3223 | to_intel_crtc_state(crtc->state), |
| 3224 | plane_state); |
| 3225 | |
| 3226 | drm_modeset_unlock_crtc(crtc); |
| 3227 | } |
| 3228 | } |
| 3229 | |
| 3230 | void intel_prepare_reset(struct drm_device *dev) |
| 3231 | { |
| 3232 | /* no reset support for gen2 */ |
| 3233 | if (IS_GEN2(dev)) |
| 3234 | return; |
| 3235 | |
| 3236 | /* reset doesn't touch the display */ |
| 3237 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
| 3238 | return; |
| 3239 | |
| 3240 | drm_modeset_lock_all(dev); |
| 3241 | /* |
| 3242 | * Disabling the crtcs gracefully seems nicer. Also the |
| 3243 | * g33 docs say we should at least disable all the planes. |
| 3244 | */ |
| 3245 | intel_display_suspend(dev); |
| 3246 | } |
| 3247 | |
| 3248 | void intel_finish_reset(struct drm_device *dev) |
| 3249 | { |
| 3250 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 3251 | |
| 3252 | /* |
| 3253 | * Flips in the rings will be nuked by the reset, |
| 3254 | * so complete all pending flips so that user space |
| 3255 | * will get its events and not get stuck. |
| 3256 | */ |
| 3257 | intel_complete_page_flips(dev); |
| 3258 | |
| 3259 | /* no reset support for gen2 */ |
| 3260 | if (IS_GEN2(dev)) |
| 3261 | return; |
| 3262 | |
| 3263 | /* reset doesn't touch the display */ |
| 3264 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { |
| 3265 | /* |
| 3266 | * Flips in the rings have been nuked by the reset, |
| 3267 | * so update the base address of all primary |
| 3268 | * planes to the the last fb to make sure we're |
| 3269 | * showing the correct fb after a reset. |
| 3270 | * |
| 3271 | * FIXME: Atomic will make this obsolete since we won't schedule |
| 3272 | * CS-based flips (which might get lost in gpu resets) any more. |
| 3273 | */ |
| 3274 | intel_update_primary_planes(dev); |
| 3275 | return; |
| 3276 | } |
| 3277 | |
| 3278 | /* |
| 3279 | * The display has been reset as well, |
| 3280 | * so need a full re-initialization. |
| 3281 | */ |
| 3282 | intel_runtime_pm_disable_interrupts(dev_priv); |
| 3283 | intel_runtime_pm_enable_interrupts(dev_priv); |
| 3284 | |
| 3285 | intel_modeset_init_hw(dev); |
| 3286 | |
| 3287 | spin_lock_irq(&dev_priv->irq_lock); |
| 3288 | if (dev_priv->display.hpd_irq_setup) |
| 3289 | dev_priv->display.hpd_irq_setup(dev); |
| 3290 | spin_unlock_irq(&dev_priv->irq_lock); |
| 3291 | |
| 3292 | intel_display_resume(dev); |
| 3293 | |
| 3294 | intel_hpd_init(dev_priv); |
| 3295 | |
| 3296 | drm_modeset_unlock_all(dev); |
| 3297 | } |
| 3298 | |
| 3299 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
| 3300 | { |
| 3301 | struct drm_device *dev = crtc->dev; |
| 3302 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3303 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3304 | bool pending; |
| 3305 | |
| 3306 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
| 3307 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) |
| 3308 | return false; |
| 3309 | |
| 3310 | spin_lock_irq(&dev->event_lock); |
| 3311 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
| 3312 | spin_unlock_irq(&dev->event_lock); |
| 3313 | |
| 3314 | return pending; |
| 3315 | } |
| 3316 | |
| 3317 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
| 3318 | struct intel_crtc_state *old_crtc_state) |
| 3319 | { |
| 3320 | struct drm_device *dev = crtc->base.dev; |
| 3321 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3322 | struct intel_crtc_state *pipe_config = |
| 3323 | to_intel_crtc_state(crtc->base.state); |
| 3324 | |
| 3325 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
| 3326 | crtc->base.mode = crtc->base.state->mode; |
| 3327 | |
| 3328 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", |
| 3329 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, |
| 3330 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); |
| 3331 | |
| 3332 | if (HAS_DDI(dev)) |
| 3333 | intel_set_pipe_csc(&crtc->base); |
| 3334 | |
| 3335 | /* |
| 3336 | * Update pipe size and adjust fitter if needed: the reason for this is |
| 3337 | * that in compute_mode_changes we check the native mode (not the pfit |
| 3338 | * mode) to see if we can flip rather than do a full mode set. In the |
| 3339 | * fastboot case, we'll flip, but if we don't update the pipesrc and |
| 3340 | * pfit state, we'll end up with a big fb scanned out into the wrong |
| 3341 | * sized surface. |
| 3342 | */ |
| 3343 | |
| 3344 | I915_WRITE(PIPESRC(crtc->pipe), |
| 3345 | ((pipe_config->pipe_src_w - 1) << 16) | |
| 3346 | (pipe_config->pipe_src_h - 1)); |
| 3347 | |
| 3348 | /* on skylake this is done by detaching scalers */ |
| 3349 | if (INTEL_INFO(dev)->gen >= 9) { |
| 3350 | skl_detach_scalers(crtc); |
| 3351 | |
| 3352 | if (pipe_config->pch_pfit.enabled) |
| 3353 | skylake_pfit_enable(crtc); |
| 3354 | } else if (HAS_PCH_SPLIT(dev)) { |
| 3355 | if (pipe_config->pch_pfit.enabled) |
| 3356 | ironlake_pfit_enable(crtc); |
| 3357 | else if (old_crtc_state->pch_pfit.enabled) |
| 3358 | ironlake_pfit_disable(crtc, true); |
| 3359 | } |
| 3360 | } |
| 3361 | |
| 3362 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
| 3363 | { |
| 3364 | struct drm_device *dev = crtc->dev; |
| 3365 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3366 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3367 | int pipe = intel_crtc->pipe; |
| 3368 | i915_reg_t reg; |
| 3369 | u32 temp; |
| 3370 | |
| 3371 | /* enable normal train */ |
| 3372 | reg = FDI_TX_CTL(pipe); |
| 3373 | temp = I915_READ(reg); |
| 3374 | if (IS_IVYBRIDGE(dev)) { |
| 3375 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
| 3376 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; |
| 3377 | } else { |
| 3378 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3379 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; |
| 3380 | } |
| 3381 | I915_WRITE(reg, temp); |
| 3382 | |
| 3383 | reg = FDI_RX_CTL(pipe); |
| 3384 | temp = I915_READ(reg); |
| 3385 | if (HAS_PCH_CPT(dev)) { |
| 3386 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 3387 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; |
| 3388 | } else { |
| 3389 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3390 | temp |= FDI_LINK_TRAIN_NONE; |
| 3391 | } |
| 3392 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); |
| 3393 | |
| 3394 | /* wait one idle pattern time */ |
| 3395 | POSTING_READ(reg); |
| 3396 | udelay(1000); |
| 3397 | |
| 3398 | /* IVB wants error correction enabled */ |
| 3399 | if (IS_IVYBRIDGE(dev)) |
| 3400 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | |
| 3401 | FDI_FE_ERRC_ENABLE); |
| 3402 | } |
| 3403 | |
| 3404 | /* The FDI link training functions for ILK/Ibexpeak. */ |
| 3405 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) |
| 3406 | { |
| 3407 | struct drm_device *dev = crtc->dev; |
| 3408 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3409 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3410 | int pipe = intel_crtc->pipe; |
| 3411 | i915_reg_t reg; |
| 3412 | u32 temp, tries; |
| 3413 | |
| 3414 | /* FDI needs bits from pipe first */ |
| 3415 | assert_pipe_enabled(dev_priv, pipe); |
| 3416 | |
| 3417 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
| 3418 | for train result */ |
| 3419 | reg = FDI_RX_IMR(pipe); |
| 3420 | temp = I915_READ(reg); |
| 3421 | temp &= ~FDI_RX_SYMBOL_LOCK; |
| 3422 | temp &= ~FDI_RX_BIT_LOCK; |
| 3423 | I915_WRITE(reg, temp); |
| 3424 | I915_READ(reg); |
| 3425 | udelay(150); |
| 3426 | |
| 3427 | /* enable CPU FDI TX and PCH FDI RX */ |
| 3428 | reg = FDI_TX_CTL(pipe); |
| 3429 | temp = I915_READ(reg); |
| 3430 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
| 3431 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
| 3432 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3433 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 3434 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
| 3435 | |
| 3436 | reg = FDI_RX_CTL(pipe); |
| 3437 | temp = I915_READ(reg); |
| 3438 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3439 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 3440 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
| 3441 | |
| 3442 | POSTING_READ(reg); |
| 3443 | udelay(150); |
| 3444 | |
| 3445 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
| 3446 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
| 3447 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | |
| 3448 | FDI_RX_PHASE_SYNC_POINTER_EN); |
| 3449 | |
| 3450 | reg = FDI_RX_IIR(pipe); |
| 3451 | for (tries = 0; tries < 5; tries++) { |
| 3452 | temp = I915_READ(reg); |
| 3453 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 3454 | |
| 3455 | if ((temp & FDI_RX_BIT_LOCK)) { |
| 3456 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
| 3457 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
| 3458 | break; |
| 3459 | } |
| 3460 | } |
| 3461 | if (tries == 5) |
| 3462 | DRM_ERROR("FDI train 1 fail!\n"); |
| 3463 | |
| 3464 | /* Train 2 */ |
| 3465 | reg = FDI_TX_CTL(pipe); |
| 3466 | temp = I915_READ(reg); |
| 3467 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3468 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
| 3469 | I915_WRITE(reg, temp); |
| 3470 | |
| 3471 | reg = FDI_RX_CTL(pipe); |
| 3472 | temp = I915_READ(reg); |
| 3473 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3474 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
| 3475 | I915_WRITE(reg, temp); |
| 3476 | |
| 3477 | POSTING_READ(reg); |
| 3478 | udelay(150); |
| 3479 | |
| 3480 | reg = FDI_RX_IIR(pipe); |
| 3481 | for (tries = 0; tries < 5; tries++) { |
| 3482 | temp = I915_READ(reg); |
| 3483 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 3484 | |
| 3485 | if (temp & FDI_RX_SYMBOL_LOCK) { |
| 3486 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
| 3487 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
| 3488 | break; |
| 3489 | } |
| 3490 | } |
| 3491 | if (tries == 5) |
| 3492 | DRM_ERROR("FDI train 2 fail!\n"); |
| 3493 | |
| 3494 | DRM_DEBUG_KMS("FDI train done\n"); |
| 3495 | |
| 3496 | } |
| 3497 | |
| 3498 | static const int snb_b_fdi_train_param[] = { |
| 3499 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
| 3500 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, |
| 3501 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, |
| 3502 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, |
| 3503 | }; |
| 3504 | |
| 3505 | /* The FDI link training functions for SNB/Cougarpoint. */ |
| 3506 | static void gen6_fdi_link_train(struct drm_crtc *crtc) |
| 3507 | { |
| 3508 | struct drm_device *dev = crtc->dev; |
| 3509 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3510 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3511 | int pipe = intel_crtc->pipe; |
| 3512 | i915_reg_t reg; |
| 3513 | u32 temp, i, retry; |
| 3514 | |
| 3515 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
| 3516 | for train result */ |
| 3517 | reg = FDI_RX_IMR(pipe); |
| 3518 | temp = I915_READ(reg); |
| 3519 | temp &= ~FDI_RX_SYMBOL_LOCK; |
| 3520 | temp &= ~FDI_RX_BIT_LOCK; |
| 3521 | I915_WRITE(reg, temp); |
| 3522 | |
| 3523 | POSTING_READ(reg); |
| 3524 | udelay(150); |
| 3525 | |
| 3526 | /* enable CPU FDI TX and PCH FDI RX */ |
| 3527 | reg = FDI_TX_CTL(pipe); |
| 3528 | temp = I915_READ(reg); |
| 3529 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
| 3530 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
| 3531 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3532 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 3533 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 3534 | /* SNB-B */ |
| 3535 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
| 3536 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
| 3537 | |
| 3538 | I915_WRITE(FDI_RX_MISC(pipe), |
| 3539 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); |
| 3540 | |
| 3541 | reg = FDI_RX_CTL(pipe); |
| 3542 | temp = I915_READ(reg); |
| 3543 | if (HAS_PCH_CPT(dev)) { |
| 3544 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 3545 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
| 3546 | } else { |
| 3547 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3548 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 3549 | } |
| 3550 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
| 3551 | |
| 3552 | POSTING_READ(reg); |
| 3553 | udelay(150); |
| 3554 | |
| 3555 | for (i = 0; i < 4; i++) { |
| 3556 | reg = FDI_TX_CTL(pipe); |
| 3557 | temp = I915_READ(reg); |
| 3558 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 3559 | temp |= snb_b_fdi_train_param[i]; |
| 3560 | I915_WRITE(reg, temp); |
| 3561 | |
| 3562 | POSTING_READ(reg); |
| 3563 | udelay(500); |
| 3564 | |
| 3565 | for (retry = 0; retry < 5; retry++) { |
| 3566 | reg = FDI_RX_IIR(pipe); |
| 3567 | temp = I915_READ(reg); |
| 3568 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 3569 | if (temp & FDI_RX_BIT_LOCK) { |
| 3570 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
| 3571 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
| 3572 | break; |
| 3573 | } |
| 3574 | udelay(50); |
| 3575 | } |
| 3576 | if (retry < 5) |
| 3577 | break; |
| 3578 | } |
| 3579 | if (i == 4) |
| 3580 | DRM_ERROR("FDI train 1 fail!\n"); |
| 3581 | |
| 3582 | /* Train 2 */ |
| 3583 | reg = FDI_TX_CTL(pipe); |
| 3584 | temp = I915_READ(reg); |
| 3585 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3586 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
| 3587 | if (IS_GEN6(dev)) { |
| 3588 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 3589 | /* SNB-B */ |
| 3590 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
| 3591 | } |
| 3592 | I915_WRITE(reg, temp); |
| 3593 | |
| 3594 | reg = FDI_RX_CTL(pipe); |
| 3595 | temp = I915_READ(reg); |
| 3596 | if (HAS_PCH_CPT(dev)) { |
| 3597 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 3598 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; |
| 3599 | } else { |
| 3600 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3601 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
| 3602 | } |
| 3603 | I915_WRITE(reg, temp); |
| 3604 | |
| 3605 | POSTING_READ(reg); |
| 3606 | udelay(150); |
| 3607 | |
| 3608 | for (i = 0; i < 4; i++) { |
| 3609 | reg = FDI_TX_CTL(pipe); |
| 3610 | temp = I915_READ(reg); |
| 3611 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 3612 | temp |= snb_b_fdi_train_param[i]; |
| 3613 | I915_WRITE(reg, temp); |
| 3614 | |
| 3615 | POSTING_READ(reg); |
| 3616 | udelay(500); |
| 3617 | |
| 3618 | for (retry = 0; retry < 5; retry++) { |
| 3619 | reg = FDI_RX_IIR(pipe); |
| 3620 | temp = I915_READ(reg); |
| 3621 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 3622 | if (temp & FDI_RX_SYMBOL_LOCK) { |
| 3623 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
| 3624 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
| 3625 | break; |
| 3626 | } |
| 3627 | udelay(50); |
| 3628 | } |
| 3629 | if (retry < 5) |
| 3630 | break; |
| 3631 | } |
| 3632 | if (i == 4) |
| 3633 | DRM_ERROR("FDI train 2 fail!\n"); |
| 3634 | |
| 3635 | DRM_DEBUG_KMS("FDI train done.\n"); |
| 3636 | } |
| 3637 | |
| 3638 | /* Manual link training for Ivy Bridge A0 parts */ |
| 3639 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) |
| 3640 | { |
| 3641 | struct drm_device *dev = crtc->dev; |
| 3642 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3643 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3644 | int pipe = intel_crtc->pipe; |
| 3645 | i915_reg_t reg; |
| 3646 | u32 temp, i, j; |
| 3647 | |
| 3648 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
| 3649 | for train result */ |
| 3650 | reg = FDI_RX_IMR(pipe); |
| 3651 | temp = I915_READ(reg); |
| 3652 | temp &= ~FDI_RX_SYMBOL_LOCK; |
| 3653 | temp &= ~FDI_RX_BIT_LOCK; |
| 3654 | I915_WRITE(reg, temp); |
| 3655 | |
| 3656 | POSTING_READ(reg); |
| 3657 | udelay(150); |
| 3658 | |
| 3659 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
| 3660 | I915_READ(FDI_RX_IIR(pipe))); |
| 3661 | |
| 3662 | /* Try each vswing and preemphasis setting twice before moving on */ |
| 3663 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { |
| 3664 | /* disable first in case we need to retry */ |
| 3665 | reg = FDI_TX_CTL(pipe); |
| 3666 | temp = I915_READ(reg); |
| 3667 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); |
| 3668 | temp &= ~FDI_TX_ENABLE; |
| 3669 | I915_WRITE(reg, temp); |
| 3670 | |
| 3671 | reg = FDI_RX_CTL(pipe); |
| 3672 | temp = I915_READ(reg); |
| 3673 | temp &= ~FDI_LINK_TRAIN_AUTO; |
| 3674 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 3675 | temp &= ~FDI_RX_ENABLE; |
| 3676 | I915_WRITE(reg, temp); |
| 3677 | |
| 3678 | /* enable CPU FDI TX and PCH FDI RX */ |
| 3679 | reg = FDI_TX_CTL(pipe); |
| 3680 | temp = I915_READ(reg); |
| 3681 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
| 3682 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
| 3683 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
| 3684 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 3685 | temp |= snb_b_fdi_train_param[j/2]; |
| 3686 | temp |= FDI_COMPOSITE_SYNC; |
| 3687 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
| 3688 | |
| 3689 | I915_WRITE(FDI_RX_MISC(pipe), |
| 3690 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); |
| 3691 | |
| 3692 | reg = FDI_RX_CTL(pipe); |
| 3693 | temp = I915_READ(reg); |
| 3694 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
| 3695 | temp |= FDI_COMPOSITE_SYNC; |
| 3696 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
| 3697 | |
| 3698 | POSTING_READ(reg); |
| 3699 | udelay(1); /* should be 0.5us */ |
| 3700 | |
| 3701 | for (i = 0; i < 4; i++) { |
| 3702 | reg = FDI_RX_IIR(pipe); |
| 3703 | temp = I915_READ(reg); |
| 3704 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 3705 | |
| 3706 | if (temp & FDI_RX_BIT_LOCK || |
| 3707 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { |
| 3708 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
| 3709 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", |
| 3710 | i); |
| 3711 | break; |
| 3712 | } |
| 3713 | udelay(1); /* should be 0.5us */ |
| 3714 | } |
| 3715 | if (i == 4) { |
| 3716 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); |
| 3717 | continue; |
| 3718 | } |
| 3719 | |
| 3720 | /* Train 2 */ |
| 3721 | reg = FDI_TX_CTL(pipe); |
| 3722 | temp = I915_READ(reg); |
| 3723 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
| 3724 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; |
| 3725 | I915_WRITE(reg, temp); |
| 3726 | |
| 3727 | reg = FDI_RX_CTL(pipe); |
| 3728 | temp = I915_READ(reg); |
| 3729 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 3730 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; |
| 3731 | I915_WRITE(reg, temp); |
| 3732 | |
| 3733 | POSTING_READ(reg); |
| 3734 | udelay(2); /* should be 1.5us */ |
| 3735 | |
| 3736 | for (i = 0; i < 4; i++) { |
| 3737 | reg = FDI_RX_IIR(pipe); |
| 3738 | temp = I915_READ(reg); |
| 3739 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 3740 | |
| 3741 | if (temp & FDI_RX_SYMBOL_LOCK || |
| 3742 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { |
| 3743 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
| 3744 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", |
| 3745 | i); |
| 3746 | goto train_done; |
| 3747 | } |
| 3748 | udelay(2); /* should be 1.5us */ |
| 3749 | } |
| 3750 | if (i == 4) |
| 3751 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); |
| 3752 | } |
| 3753 | |
| 3754 | train_done: |
| 3755 | DRM_DEBUG_KMS("FDI train done.\n"); |
| 3756 | } |
| 3757 | |
| 3758 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
| 3759 | { |
| 3760 | struct drm_device *dev = intel_crtc->base.dev; |
| 3761 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3762 | int pipe = intel_crtc->pipe; |
| 3763 | i915_reg_t reg; |
| 3764 | u32 temp; |
| 3765 | |
| 3766 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
| 3767 | reg = FDI_RX_CTL(pipe); |
| 3768 | temp = I915_READ(reg); |
| 3769 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
| 3770 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
| 3771 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
| 3772 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
| 3773 | |
| 3774 | POSTING_READ(reg); |
| 3775 | udelay(200); |
| 3776 | |
| 3777 | /* Switch from Rawclk to PCDclk */ |
| 3778 | temp = I915_READ(reg); |
| 3779 | I915_WRITE(reg, temp | FDI_PCDCLK); |
| 3780 | |
| 3781 | POSTING_READ(reg); |
| 3782 | udelay(200); |
| 3783 | |
| 3784 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
| 3785 | reg = FDI_TX_CTL(pipe); |
| 3786 | temp = I915_READ(reg); |
| 3787 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { |
| 3788 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); |
| 3789 | |
| 3790 | POSTING_READ(reg); |
| 3791 | udelay(100); |
| 3792 | } |
| 3793 | } |
| 3794 | |
| 3795 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
| 3796 | { |
| 3797 | struct drm_device *dev = intel_crtc->base.dev; |
| 3798 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3799 | int pipe = intel_crtc->pipe; |
| 3800 | i915_reg_t reg; |
| 3801 | u32 temp; |
| 3802 | |
| 3803 | /* Switch from PCDclk to Rawclk */ |
| 3804 | reg = FDI_RX_CTL(pipe); |
| 3805 | temp = I915_READ(reg); |
| 3806 | I915_WRITE(reg, temp & ~FDI_PCDCLK); |
| 3807 | |
| 3808 | /* Disable CPU FDI TX PLL */ |
| 3809 | reg = FDI_TX_CTL(pipe); |
| 3810 | temp = I915_READ(reg); |
| 3811 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); |
| 3812 | |
| 3813 | POSTING_READ(reg); |
| 3814 | udelay(100); |
| 3815 | |
| 3816 | reg = FDI_RX_CTL(pipe); |
| 3817 | temp = I915_READ(reg); |
| 3818 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); |
| 3819 | |
| 3820 | /* Wait for the clocks to turn off. */ |
| 3821 | POSTING_READ(reg); |
| 3822 | udelay(100); |
| 3823 | } |
| 3824 | |
| 3825 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
| 3826 | { |
| 3827 | struct drm_device *dev = crtc->dev; |
| 3828 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3829 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3830 | int pipe = intel_crtc->pipe; |
| 3831 | i915_reg_t reg; |
| 3832 | u32 temp; |
| 3833 | |
| 3834 | /* disable CPU FDI tx and PCH FDI rx */ |
| 3835 | reg = FDI_TX_CTL(pipe); |
| 3836 | temp = I915_READ(reg); |
| 3837 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); |
| 3838 | POSTING_READ(reg); |
| 3839 | |
| 3840 | reg = FDI_RX_CTL(pipe); |
| 3841 | temp = I915_READ(reg); |
| 3842 | temp &= ~(0x7 << 16); |
| 3843 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
| 3844 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
| 3845 | |
| 3846 | POSTING_READ(reg); |
| 3847 | udelay(100); |
| 3848 | |
| 3849 | /* Ironlake workaround, disable clock pointer after downing FDI */ |
| 3850 | if (HAS_PCH_IBX(dev)) |
| 3851 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
| 3852 | |
| 3853 | /* still set train pattern 1 */ |
| 3854 | reg = FDI_TX_CTL(pipe); |
| 3855 | temp = I915_READ(reg); |
| 3856 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3857 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 3858 | I915_WRITE(reg, temp); |
| 3859 | |
| 3860 | reg = FDI_RX_CTL(pipe); |
| 3861 | temp = I915_READ(reg); |
| 3862 | if (HAS_PCH_CPT(dev)) { |
| 3863 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 3864 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
| 3865 | } else { |
| 3866 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3867 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 3868 | } |
| 3869 | /* BPC in FDI rx is consistent with that in PIPECONF */ |
| 3870 | temp &= ~(0x07 << 16); |
| 3871 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
| 3872 | I915_WRITE(reg, temp); |
| 3873 | |
| 3874 | POSTING_READ(reg); |
| 3875 | udelay(100); |
| 3876 | } |
| 3877 | |
| 3878 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
| 3879 | { |
| 3880 | struct intel_crtc *crtc; |
| 3881 | |
| 3882 | /* Note that we don't need to be called with mode_config.lock here |
| 3883 | * as our list of CRTC objects is static for the lifetime of the |
| 3884 | * device and so cannot disappear as we iterate. Similarly, we can |
| 3885 | * happily treat the predicates as racy, atomic checks as userspace |
| 3886 | * cannot claim and pin a new fb without at least acquring the |
| 3887 | * struct_mutex and so serialising with us. |
| 3888 | */ |
| 3889 | for_each_intel_crtc(dev, crtc) { |
| 3890 | if (atomic_read(&crtc->unpin_work_count) == 0) |
| 3891 | continue; |
| 3892 | |
| 3893 | if (crtc->unpin_work) |
| 3894 | intel_wait_for_vblank(dev, crtc->pipe); |
| 3895 | |
| 3896 | return true; |
| 3897 | } |
| 3898 | |
| 3899 | return false; |
| 3900 | } |
| 3901 | |
| 3902 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
| 3903 | { |
| 3904 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
| 3905 | struct intel_unpin_work *work = intel_crtc->unpin_work; |
| 3906 | |
| 3907 | /* ensure that the unpin work is consistent wrt ->pending. */ |
| 3908 | smp_rmb(); |
| 3909 | intel_crtc->unpin_work = NULL; |
| 3910 | |
| 3911 | if (work->event) |
| 3912 | drm_send_vblank_event(intel_crtc->base.dev, |
| 3913 | intel_crtc->pipe, |
| 3914 | work->event); |
| 3915 | |
| 3916 | drm_crtc_vblank_put(&intel_crtc->base); |
| 3917 | |
| 3918 | wake_up_all(&dev_priv->pending_flip_queue); |
| 3919 | queue_work(dev_priv->wq, &work->work); |
| 3920 | |
| 3921 | trace_i915_flip_complete(intel_crtc->plane, |
| 3922 | work->pending_flip_obj); |
| 3923 | } |
| 3924 | |
| 3925 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
| 3926 | { |
| 3927 | struct drm_device *dev = crtc->dev; |
| 3928 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3929 | long ret; |
| 3930 | |
| 3931 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
| 3932 | |
| 3933 | ret = wait_event_interruptible_timeout( |
| 3934 | dev_priv->pending_flip_queue, |
| 3935 | !intel_crtc_has_pending_flip(crtc), |
| 3936 | 60*HZ); |
| 3937 | |
| 3938 | if (ret < 0) |
| 3939 | return ret; |
| 3940 | |
| 3941 | if (ret == 0) { |
| 3942 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3943 | |
| 3944 | spin_lock_irq(&dev->event_lock); |
| 3945 | if (intel_crtc->unpin_work) { |
| 3946 | WARN_ONCE(1, "Removing stuck page flip\n"); |
| 3947 | page_flip_completed(intel_crtc); |
| 3948 | } |
| 3949 | spin_unlock_irq(&dev->event_lock); |
| 3950 | } |
| 3951 | |
| 3952 | return 0; |
| 3953 | } |
| 3954 | |
| 3955 | static void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
| 3956 | { |
| 3957 | u32 temp; |
| 3958 | |
| 3959 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); |
| 3960 | |
| 3961 | mutex_lock(&dev_priv->sb_lock); |
| 3962 | |
| 3963 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
| 3964 | temp |= SBI_SSCCTL_DISABLE; |
| 3965 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
| 3966 | |
| 3967 | mutex_unlock(&dev_priv->sb_lock); |
| 3968 | } |
| 3969 | |
| 3970 | /* Program iCLKIP clock to the desired frequency */ |
| 3971 | static void lpt_program_iclkip(struct drm_crtc *crtc) |
| 3972 | { |
| 3973 | struct drm_device *dev = crtc->dev; |
| 3974 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3975 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
| 3976 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
| 3977 | u32 temp; |
| 3978 | |
| 3979 | lpt_disable_iclkip(dev_priv); |
| 3980 | |
| 3981 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ |
| 3982 | if (clock == 20000) { |
| 3983 | auxdiv = 1; |
| 3984 | divsel = 0x41; |
| 3985 | phaseinc = 0x20; |
| 3986 | } else { |
| 3987 | /* The iCLK virtual clock root frequency is in MHz, |
| 3988 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
| 3989 | * divisors, it is necessary to divide one by another, so we |
| 3990 | * convert the virtual clock precision to KHz here for higher |
| 3991 | * precision. |
| 3992 | */ |
| 3993 | u32 iclk_virtual_root_freq = 172800 * 1000; |
| 3994 | u32 iclk_pi_range = 64; |
| 3995 | u32 desired_divisor, msb_divisor_value, pi_value; |
| 3996 | |
| 3997 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, clock); |
| 3998 | msb_divisor_value = desired_divisor / iclk_pi_range; |
| 3999 | pi_value = desired_divisor % iclk_pi_range; |
| 4000 | |
| 4001 | auxdiv = 0; |
| 4002 | divsel = msb_divisor_value - 2; |
| 4003 | phaseinc = pi_value; |
| 4004 | } |
| 4005 | |
| 4006 | /* This should not happen with any sane values */ |
| 4007 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & |
| 4008 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); |
| 4009 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & |
| 4010 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); |
| 4011 | |
| 4012 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", |
| 4013 | clock, |
| 4014 | auxdiv, |
| 4015 | divsel, |
| 4016 | phasedir, |
| 4017 | phaseinc); |
| 4018 | |
| 4019 | mutex_lock(&dev_priv->sb_lock); |
| 4020 | |
| 4021 | /* Program SSCDIVINTPHASE6 */ |
| 4022 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
| 4023 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
| 4024 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); |
| 4025 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; |
| 4026 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); |
| 4027 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); |
| 4028 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; |
| 4029 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
| 4030 | |
| 4031 | /* Program SSCAUXDIV */ |
| 4032 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
| 4033 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
| 4034 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); |
| 4035 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
| 4036 | |
| 4037 | /* Enable modulator and associated divider */ |
| 4038 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
| 4039 | temp &= ~SBI_SSCCTL_DISABLE; |
| 4040 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
| 4041 | |
| 4042 | mutex_unlock(&dev_priv->sb_lock); |
| 4043 | |
| 4044 | /* Wait for initialization time */ |
| 4045 | udelay(24); |
| 4046 | |
| 4047 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); |
| 4048 | } |
| 4049 | |
| 4050 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
| 4051 | enum pipe pch_transcoder) |
| 4052 | { |
| 4053 | struct drm_device *dev = crtc->base.dev; |
| 4054 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4055 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
| 4056 | |
| 4057 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), |
| 4058 | I915_READ(HTOTAL(cpu_transcoder))); |
| 4059 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), |
| 4060 | I915_READ(HBLANK(cpu_transcoder))); |
| 4061 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), |
| 4062 | I915_READ(HSYNC(cpu_transcoder))); |
| 4063 | |
| 4064 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), |
| 4065 | I915_READ(VTOTAL(cpu_transcoder))); |
| 4066 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), |
| 4067 | I915_READ(VBLANK(cpu_transcoder))); |
| 4068 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), |
| 4069 | I915_READ(VSYNC(cpu_transcoder))); |
| 4070 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), |
| 4071 | I915_READ(VSYNCSHIFT(cpu_transcoder))); |
| 4072 | } |
| 4073 | |
| 4074 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
| 4075 | { |
| 4076 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4077 | uint32_t temp; |
| 4078 | |
| 4079 | temp = I915_READ(SOUTH_CHICKEN1); |
| 4080 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
| 4081 | return; |
| 4082 | |
| 4083 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
| 4084 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); |
| 4085 | |
| 4086 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
| 4087 | if (enable) |
| 4088 | temp |= FDI_BC_BIFURCATION_SELECT; |
| 4089 | |
| 4090 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); |
| 4091 | I915_WRITE(SOUTH_CHICKEN1, temp); |
| 4092 | POSTING_READ(SOUTH_CHICKEN1); |
| 4093 | } |
| 4094 | |
| 4095 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) |
| 4096 | { |
| 4097 | struct drm_device *dev = intel_crtc->base.dev; |
| 4098 | |
| 4099 | switch (intel_crtc->pipe) { |
| 4100 | case PIPE_A: |
| 4101 | break; |
| 4102 | case PIPE_B: |
| 4103 | if (intel_crtc->config->fdi_lanes > 2) |
| 4104 | cpt_set_fdi_bc_bifurcation(dev, false); |
| 4105 | else |
| 4106 | cpt_set_fdi_bc_bifurcation(dev, true); |
| 4107 | |
| 4108 | break; |
| 4109 | case PIPE_C: |
| 4110 | cpt_set_fdi_bc_bifurcation(dev, true); |
| 4111 | |
| 4112 | break; |
| 4113 | default: |
| 4114 | BUG(); |
| 4115 | } |
| 4116 | } |
| 4117 | |
| 4118 | /* Return which DP Port should be selected for Transcoder DP control */ |
| 4119 | static enum port |
| 4120 | intel_trans_dp_port_sel(struct drm_crtc *crtc) |
| 4121 | { |
| 4122 | struct drm_device *dev = crtc->dev; |
| 4123 | struct intel_encoder *encoder; |
| 4124 | |
| 4125 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
| 4126 | if (encoder->type == INTEL_OUTPUT_DISPLAYPORT || |
| 4127 | encoder->type == INTEL_OUTPUT_EDP) |
| 4128 | return enc_to_dig_port(&encoder->base)->port; |
| 4129 | } |
| 4130 | |
| 4131 | return -1; |
| 4132 | } |
| 4133 | |
| 4134 | /* |
| 4135 | * Enable PCH resources required for PCH ports: |
| 4136 | * - PCH PLLs |
| 4137 | * - FDI training & RX/TX |
| 4138 | * - update transcoder timings |
| 4139 | * - DP transcoding bits |
| 4140 | * - transcoder |
| 4141 | */ |
| 4142 | static void ironlake_pch_enable(struct drm_crtc *crtc) |
| 4143 | { |
| 4144 | struct drm_device *dev = crtc->dev; |
| 4145 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4146 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4147 | int pipe = intel_crtc->pipe; |
| 4148 | u32 temp; |
| 4149 | |
| 4150 | assert_pch_transcoder_disabled(dev_priv, pipe); |
| 4151 | |
| 4152 | if (IS_IVYBRIDGE(dev)) |
| 4153 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); |
| 4154 | |
| 4155 | /* Write the TU size bits before fdi link training, so that error |
| 4156 | * detection works. */ |
| 4157 | I915_WRITE(FDI_RX_TUSIZE1(pipe), |
| 4158 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); |
| 4159 | |
| 4160 | /* |
| 4161 | * Sometimes spurious CPU pipe underruns happen during FDI |
| 4162 | * training, at least with VGA+HDMI cloning. Suppress them. |
| 4163 | */ |
| 4164 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
| 4165 | |
| 4166 | /* For PCH output, training FDI link */ |
| 4167 | dev_priv->display.fdi_link_train(crtc); |
| 4168 | |
| 4169 | /* We need to program the right clock selection before writing the pixel |
| 4170 | * mutliplier into the DPLL. */ |
| 4171 | if (HAS_PCH_CPT(dev)) { |
| 4172 | u32 sel; |
| 4173 | |
| 4174 | temp = I915_READ(PCH_DPLL_SEL); |
| 4175 | temp |= TRANS_DPLL_ENABLE(pipe); |
| 4176 | sel = TRANS_DPLLB_SEL(pipe); |
| 4177 | if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) |
| 4178 | temp |= sel; |
| 4179 | else |
| 4180 | temp &= ~sel; |
| 4181 | I915_WRITE(PCH_DPLL_SEL, temp); |
| 4182 | } |
| 4183 | |
| 4184 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
| 4185 | * transcoder, and we actually should do this to not upset any PCH |
| 4186 | * transcoder that already use the clock when we share it. |
| 4187 | * |
| 4188 | * Note that enable_shared_dpll tries to do the right thing, but |
| 4189 | * get_shared_dpll unconditionally resets the pll - we need that to have |
| 4190 | * the right LVDS enable sequence. */ |
| 4191 | intel_enable_shared_dpll(intel_crtc); |
| 4192 | |
| 4193 | /* set transcoder timing, panel must allow it */ |
| 4194 | assert_panel_unlocked(dev_priv, pipe); |
| 4195 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
| 4196 | |
| 4197 | intel_fdi_normal_train(crtc); |
| 4198 | |
| 4199 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
| 4200 | |
| 4201 | /* For PCH DP, enable TRANS_DP_CTL */ |
| 4202 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
| 4203 | const struct drm_display_mode *adjusted_mode = |
| 4204 | &intel_crtc->config->base.adjusted_mode; |
| 4205 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
| 4206 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
| 4207 | temp = I915_READ(reg); |
| 4208 | temp &= ~(TRANS_DP_PORT_SEL_MASK | |
| 4209 | TRANS_DP_SYNC_MASK | |
| 4210 | TRANS_DP_BPC_MASK); |
| 4211 | temp |= TRANS_DP_OUTPUT_ENABLE; |
| 4212 | temp |= bpc << 9; /* same format but at 11:9 */ |
| 4213 | |
| 4214 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
| 4215 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
| 4216 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
| 4217 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
| 4218 | |
| 4219 | switch (intel_trans_dp_port_sel(crtc)) { |
| 4220 | case PORT_B: |
| 4221 | temp |= TRANS_DP_PORT_SEL_B; |
| 4222 | break; |
| 4223 | case PORT_C: |
| 4224 | temp |= TRANS_DP_PORT_SEL_C; |
| 4225 | break; |
| 4226 | case PORT_D: |
| 4227 | temp |= TRANS_DP_PORT_SEL_D; |
| 4228 | break; |
| 4229 | default: |
| 4230 | BUG(); |
| 4231 | } |
| 4232 | |
| 4233 | I915_WRITE(reg, temp); |
| 4234 | } |
| 4235 | |
| 4236 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
| 4237 | } |
| 4238 | |
| 4239 | static void lpt_pch_enable(struct drm_crtc *crtc) |
| 4240 | { |
| 4241 | struct drm_device *dev = crtc->dev; |
| 4242 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4243 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4244 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
| 4245 | |
| 4246 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
| 4247 | |
| 4248 | lpt_program_iclkip(crtc); |
| 4249 | |
| 4250 | /* Set transcoder timing. */ |
| 4251 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
| 4252 | |
| 4253 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
| 4254 | } |
| 4255 | |
| 4256 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
| 4257 | struct intel_crtc_state *crtc_state) |
| 4258 | { |
| 4259 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
| 4260 | struct intel_shared_dpll *pll; |
| 4261 | struct intel_shared_dpll_config *shared_dpll; |
| 4262 | enum intel_dpll_id i; |
| 4263 | int max = dev_priv->num_shared_dpll; |
| 4264 | |
| 4265 | shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state); |
| 4266 | |
| 4267 | if (HAS_PCH_IBX(dev_priv->dev)) { |
| 4268 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ |
| 4269 | i = (enum intel_dpll_id) crtc->pipe; |
| 4270 | pll = &dev_priv->shared_dplls[i]; |
| 4271 | |
| 4272 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
| 4273 | crtc->base.base.id, pll->name); |
| 4274 | |
| 4275 | WARN_ON(shared_dpll[i].crtc_mask); |
| 4276 | |
| 4277 | goto found; |
| 4278 | } |
| 4279 | |
| 4280 | if (IS_BROXTON(dev_priv->dev)) { |
| 4281 | /* PLL is attached to port in bxt */ |
| 4282 | struct intel_encoder *encoder; |
| 4283 | struct intel_digital_port *intel_dig_port; |
| 4284 | |
| 4285 | encoder = intel_ddi_get_crtc_new_encoder(crtc_state); |
| 4286 | if (WARN_ON(!encoder)) |
| 4287 | return NULL; |
| 4288 | |
| 4289 | intel_dig_port = enc_to_dig_port(&encoder->base); |
| 4290 | /* 1:1 mapping between ports and PLLs */ |
| 4291 | i = (enum intel_dpll_id)intel_dig_port->port; |
| 4292 | pll = &dev_priv->shared_dplls[i]; |
| 4293 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
| 4294 | crtc->base.base.id, pll->name); |
| 4295 | WARN_ON(shared_dpll[i].crtc_mask); |
| 4296 | |
| 4297 | goto found; |
| 4298 | } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv)) |
| 4299 | /* Do not consider SPLL */ |
| 4300 | max = 2; |
| 4301 | |
| 4302 | for (i = 0; i < max; i++) { |
| 4303 | pll = &dev_priv->shared_dplls[i]; |
| 4304 | |
| 4305 | /* Only want to check enabled timings first */ |
| 4306 | if (shared_dpll[i].crtc_mask == 0) |
| 4307 | continue; |
| 4308 | |
| 4309 | if (memcmp(&crtc_state->dpll_hw_state, |
| 4310 | &shared_dpll[i].hw_state, |
| 4311 | sizeof(crtc_state->dpll_hw_state)) == 0) { |
| 4312 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", |
| 4313 | crtc->base.base.id, pll->name, |
| 4314 | shared_dpll[i].crtc_mask, |
| 4315 | pll->active); |
| 4316 | goto found; |
| 4317 | } |
| 4318 | } |
| 4319 | |
| 4320 | /* Ok no matching timings, maybe there's a free one? */ |
| 4321 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
| 4322 | pll = &dev_priv->shared_dplls[i]; |
| 4323 | if (shared_dpll[i].crtc_mask == 0) { |
| 4324 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
| 4325 | crtc->base.base.id, pll->name); |
| 4326 | goto found; |
| 4327 | } |
| 4328 | } |
| 4329 | |
| 4330 | return NULL; |
| 4331 | |
| 4332 | found: |
| 4333 | if (shared_dpll[i].crtc_mask == 0) |
| 4334 | shared_dpll[i].hw_state = |
| 4335 | crtc_state->dpll_hw_state; |
| 4336 | |
| 4337 | crtc_state->shared_dpll = i; |
| 4338 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
| 4339 | pipe_name(crtc->pipe)); |
| 4340 | |
| 4341 | shared_dpll[i].crtc_mask |= 1 << crtc->pipe; |
| 4342 | |
| 4343 | return pll; |
| 4344 | } |
| 4345 | |
| 4346 | static void intel_shared_dpll_commit(struct drm_atomic_state *state) |
| 4347 | { |
| 4348 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
| 4349 | struct intel_shared_dpll_config *shared_dpll; |
| 4350 | struct intel_shared_dpll *pll; |
| 4351 | enum intel_dpll_id i; |
| 4352 | |
| 4353 | if (!to_intel_atomic_state(state)->dpll_set) |
| 4354 | return; |
| 4355 | |
| 4356 | shared_dpll = to_intel_atomic_state(state)->shared_dpll; |
| 4357 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
| 4358 | pll = &dev_priv->shared_dplls[i]; |
| 4359 | pll->config = shared_dpll[i]; |
| 4360 | } |
| 4361 | } |
| 4362 | |
| 4363 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
| 4364 | { |
| 4365 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4366 | i915_reg_t dslreg = PIPEDSL(pipe); |
| 4367 | u32 temp; |
| 4368 | |
| 4369 | temp = I915_READ(dslreg); |
| 4370 | udelay(500); |
| 4371 | if (wait_for(I915_READ(dslreg) != temp, 5)) { |
| 4372 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
| 4373 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
| 4374 | } |
| 4375 | } |
| 4376 | |
| 4377 | static int |
| 4378 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, |
| 4379 | unsigned scaler_user, int *scaler_id, unsigned int rotation, |
| 4380 | int src_w, int src_h, int dst_w, int dst_h) |
| 4381 | { |
| 4382 | struct intel_crtc_scaler_state *scaler_state = |
| 4383 | &crtc_state->scaler_state; |
| 4384 | struct intel_crtc *intel_crtc = |
| 4385 | to_intel_crtc(crtc_state->base.crtc); |
| 4386 | int need_scaling; |
| 4387 | |
| 4388 | need_scaling = intel_rotation_90_or_270(rotation) ? |
| 4389 | (src_h != dst_w || src_w != dst_h): |
| 4390 | (src_w != dst_w || src_h != dst_h); |
| 4391 | |
| 4392 | /* |
| 4393 | * if plane is being disabled or scaler is no more required or force detach |
| 4394 | * - free scaler binded to this plane/crtc |
| 4395 | * - in order to do this, update crtc->scaler_usage |
| 4396 | * |
| 4397 | * Here scaler state in crtc_state is set free so that |
| 4398 | * scaler can be assigned to other user. Actual register |
| 4399 | * update to free the scaler is done in plane/panel-fit programming. |
| 4400 | * For this purpose crtc/plane_state->scaler_id isn't reset here. |
| 4401 | */ |
| 4402 | if (force_detach || !need_scaling) { |
| 4403 | if (*scaler_id >= 0) { |
| 4404 | scaler_state->scaler_users &= ~(1 << scaler_user); |
| 4405 | scaler_state->scalers[*scaler_id].in_use = 0; |
| 4406 | |
| 4407 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
| 4408 | "Staged freeing scaler id %d scaler_users = 0x%x\n", |
| 4409 | intel_crtc->pipe, scaler_user, *scaler_id, |
| 4410 | scaler_state->scaler_users); |
| 4411 | *scaler_id = -1; |
| 4412 | } |
| 4413 | return 0; |
| 4414 | } |
| 4415 | |
| 4416 | /* range checks */ |
| 4417 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || |
| 4418 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || |
| 4419 | |
| 4420 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || |
| 4421 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { |
| 4422 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
| 4423 | "size is out of scaler range\n", |
| 4424 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
| 4425 | return -EINVAL; |
| 4426 | } |
| 4427 | |
| 4428 | /* mark this plane as a scaler user in crtc_state */ |
| 4429 | scaler_state->scaler_users |= (1 << scaler_user); |
| 4430 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
| 4431 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", |
| 4432 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, |
| 4433 | scaler_state->scaler_users); |
| 4434 | |
| 4435 | return 0; |
| 4436 | } |
| 4437 | |
| 4438 | /** |
| 4439 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. |
| 4440 | * |
| 4441 | * @state: crtc's scaler state |
| 4442 | * |
| 4443 | * Return |
| 4444 | * 0 - scaler_usage updated successfully |
| 4445 | * error - requested scaling cannot be supported or other error condition |
| 4446 | */ |
| 4447 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
| 4448 | { |
| 4449 | struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); |
| 4450 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
| 4451 | |
| 4452 | DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n", |
| 4453 | intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX); |
| 4454 | |
| 4455 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
| 4456 | &state->scaler_state.scaler_id, DRM_ROTATE_0, |
| 4457 | state->pipe_src_w, state->pipe_src_h, |
| 4458 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
| 4459 | } |
| 4460 | |
| 4461 | /** |
| 4462 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. |
| 4463 | * |
| 4464 | * @state: crtc's scaler state |
| 4465 | * @plane_state: atomic plane state to update |
| 4466 | * |
| 4467 | * Return |
| 4468 | * 0 - scaler_usage updated successfully |
| 4469 | * error - requested scaling cannot be supported or other error condition |
| 4470 | */ |
| 4471 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
| 4472 | struct intel_plane_state *plane_state) |
| 4473 | { |
| 4474 | |
| 4475 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
| 4476 | struct intel_plane *intel_plane = |
| 4477 | to_intel_plane(plane_state->base.plane); |
| 4478 | struct drm_framebuffer *fb = plane_state->base.fb; |
| 4479 | int ret; |
| 4480 | |
| 4481 | bool force_detach = !fb || !plane_state->visible; |
| 4482 | |
| 4483 | DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n", |
| 4484 | intel_plane->base.base.id, intel_crtc->pipe, |
| 4485 | drm_plane_index(&intel_plane->base)); |
| 4486 | |
| 4487 | ret = skl_update_scaler(crtc_state, force_detach, |
| 4488 | drm_plane_index(&intel_plane->base), |
| 4489 | &plane_state->scaler_id, |
| 4490 | plane_state->base.rotation, |
| 4491 | drm_rect_width(&plane_state->src) >> 16, |
| 4492 | drm_rect_height(&plane_state->src) >> 16, |
| 4493 | drm_rect_width(&plane_state->dst), |
| 4494 | drm_rect_height(&plane_state->dst)); |
| 4495 | |
| 4496 | if (ret || plane_state->scaler_id < 0) |
| 4497 | return ret; |
| 4498 | |
| 4499 | /* check colorkey */ |
| 4500 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
| 4501 | DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed", |
| 4502 | intel_plane->base.base.id); |
| 4503 | return -EINVAL; |
| 4504 | } |
| 4505 | |
| 4506 | /* Check src format */ |
| 4507 | switch (fb->pixel_format) { |
| 4508 | case DRM_FORMAT_RGB565: |
| 4509 | case DRM_FORMAT_XBGR8888: |
| 4510 | case DRM_FORMAT_XRGB8888: |
| 4511 | case DRM_FORMAT_ABGR8888: |
| 4512 | case DRM_FORMAT_ARGB8888: |
| 4513 | case DRM_FORMAT_XRGB2101010: |
| 4514 | case DRM_FORMAT_XBGR2101010: |
| 4515 | case DRM_FORMAT_YUYV: |
| 4516 | case DRM_FORMAT_YVYU: |
| 4517 | case DRM_FORMAT_UYVY: |
| 4518 | case DRM_FORMAT_VYUY: |
| 4519 | break; |
| 4520 | default: |
| 4521 | DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n", |
| 4522 | intel_plane->base.base.id, fb->base.id, fb->pixel_format); |
| 4523 | return -EINVAL; |
| 4524 | } |
| 4525 | |
| 4526 | return 0; |
| 4527 | } |
| 4528 | |
| 4529 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
| 4530 | { |
| 4531 | int i; |
| 4532 | |
| 4533 | for (i = 0; i < crtc->num_scalers; i++) |
| 4534 | skl_detach_scaler(crtc, i); |
| 4535 | } |
| 4536 | |
| 4537 | static void skylake_pfit_enable(struct intel_crtc *crtc) |
| 4538 | { |
| 4539 | struct drm_device *dev = crtc->base.dev; |
| 4540 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4541 | int pipe = crtc->pipe; |
| 4542 | struct intel_crtc_scaler_state *scaler_state = |
| 4543 | &crtc->config->scaler_state; |
| 4544 | |
| 4545 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); |
| 4546 | |
| 4547 | if (crtc->config->pch_pfit.enabled) { |
| 4548 | int id; |
| 4549 | |
| 4550 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { |
| 4551 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); |
| 4552 | return; |
| 4553 | } |
| 4554 | |
| 4555 | id = scaler_state->scaler_id; |
| 4556 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | |
| 4557 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); |
| 4558 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); |
| 4559 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); |
| 4560 | |
| 4561 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); |
| 4562 | } |
| 4563 | } |
| 4564 | |
| 4565 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
| 4566 | { |
| 4567 | struct drm_device *dev = crtc->base.dev; |
| 4568 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4569 | int pipe = crtc->pipe; |
| 4570 | |
| 4571 | if (crtc->config->pch_pfit.enabled) { |
| 4572 | /* Force use of hard-coded filter coefficients |
| 4573 | * as some pre-programmed values are broken, |
| 4574 | * e.g. x201. |
| 4575 | */ |
| 4576 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
| 4577 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | |
| 4578 | PF_PIPE_SEL_IVB(pipe)); |
| 4579 | else |
| 4580 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); |
| 4581 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
| 4582 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); |
| 4583 | } |
| 4584 | } |
| 4585 | |
| 4586 | void hsw_enable_ips(struct intel_crtc *crtc) |
| 4587 | { |
| 4588 | struct drm_device *dev = crtc->base.dev; |
| 4589 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4590 | |
| 4591 | if (!crtc->config->ips_enabled) |
| 4592 | return; |
| 4593 | |
| 4594 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
| 4595 | intel_wait_for_vblank(dev, crtc->pipe); |
| 4596 | |
| 4597 | assert_plane_enabled(dev_priv, crtc->plane); |
| 4598 | if (IS_BROADWELL(dev)) { |
| 4599 | mutex_lock(&dev_priv->rps.hw_lock); |
| 4600 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); |
| 4601 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 4602 | /* Quoting Art Runyan: "its not safe to expect any particular |
| 4603 | * value in IPS_CTL bit 31 after enabling IPS through the |
| 4604 | * mailbox." Moreover, the mailbox may return a bogus state, |
| 4605 | * so we need to just enable it and continue on. |
| 4606 | */ |
| 4607 | } else { |
| 4608 | I915_WRITE(IPS_CTL, IPS_ENABLE); |
| 4609 | /* The bit only becomes 1 in the next vblank, so this wait here |
| 4610 | * is essentially intel_wait_for_vblank. If we don't have this |
| 4611 | * and don't wait for vblanks until the end of crtc_enable, then |
| 4612 | * the HW state readout code will complain that the expected |
| 4613 | * IPS_CTL value is not the one we read. */ |
| 4614 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) |
| 4615 | DRM_ERROR("Timed out waiting for IPS enable\n"); |
| 4616 | } |
| 4617 | } |
| 4618 | |
| 4619 | void hsw_disable_ips(struct intel_crtc *crtc) |
| 4620 | { |
| 4621 | struct drm_device *dev = crtc->base.dev; |
| 4622 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4623 | |
| 4624 | if (!crtc->config->ips_enabled) |
| 4625 | return; |
| 4626 | |
| 4627 | assert_plane_enabled(dev_priv, crtc->plane); |
| 4628 | if (IS_BROADWELL(dev)) { |
| 4629 | mutex_lock(&dev_priv->rps.hw_lock); |
| 4630 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); |
| 4631 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 4632 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
| 4633 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) |
| 4634 | DRM_ERROR("Timed out waiting for IPS disable\n"); |
| 4635 | } else { |
| 4636 | I915_WRITE(IPS_CTL, 0); |
| 4637 | POSTING_READ(IPS_CTL); |
| 4638 | } |
| 4639 | |
| 4640 | /* We need to wait for a vblank before we can disable the plane. */ |
| 4641 | intel_wait_for_vblank(dev, crtc->pipe); |
| 4642 | } |
| 4643 | |
| 4644 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
| 4645 | static void intel_crtc_load_lut(struct drm_crtc *crtc) |
| 4646 | { |
| 4647 | struct drm_device *dev = crtc->dev; |
| 4648 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4649 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4650 | enum pipe pipe = intel_crtc->pipe; |
| 4651 | int i; |
| 4652 | bool reenable_ips = false; |
| 4653 | |
| 4654 | /* The clocks have to be on to load the palette. */ |
| 4655 | if (!crtc->state->active) |
| 4656 | return; |
| 4657 | |
| 4658 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) { |
| 4659 | if (intel_crtc->config->has_dsi_encoder) |
| 4660 | assert_dsi_pll_enabled(dev_priv); |
| 4661 | else |
| 4662 | assert_pll_enabled(dev_priv, pipe); |
| 4663 | } |
| 4664 | |
| 4665 | /* Workaround : Do not read or write the pipe palette/gamma data while |
| 4666 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. |
| 4667 | */ |
| 4668 | if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && |
| 4669 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
| 4670 | GAMMA_MODE_MODE_SPLIT)) { |
| 4671 | hsw_disable_ips(intel_crtc); |
| 4672 | reenable_ips = true; |
| 4673 | } |
| 4674 | |
| 4675 | for (i = 0; i < 256; i++) { |
| 4676 | i915_reg_t palreg; |
| 4677 | |
| 4678 | if (HAS_GMCH_DISPLAY(dev)) |
| 4679 | palreg = PALETTE(pipe, i); |
| 4680 | else |
| 4681 | palreg = LGC_PALETTE(pipe, i); |
| 4682 | |
| 4683 | I915_WRITE(palreg, |
| 4684 | (intel_crtc->lut_r[i] << 16) | |
| 4685 | (intel_crtc->lut_g[i] << 8) | |
| 4686 | intel_crtc->lut_b[i]); |
| 4687 | } |
| 4688 | |
| 4689 | if (reenable_ips) |
| 4690 | hsw_enable_ips(intel_crtc); |
| 4691 | } |
| 4692 | |
| 4693 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
| 4694 | { |
| 4695 | if (intel_crtc->overlay) { |
| 4696 | struct drm_device *dev = intel_crtc->base.dev; |
| 4697 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4698 | |
| 4699 | mutex_lock(&dev->struct_mutex); |
| 4700 | dev_priv->mm.interruptible = false; |
| 4701 | (void) intel_overlay_switch_off(intel_crtc->overlay); |
| 4702 | dev_priv->mm.interruptible = true; |
| 4703 | mutex_unlock(&dev->struct_mutex); |
| 4704 | } |
| 4705 | |
| 4706 | /* Let userspace switch the overlay on again. In most cases userspace |
| 4707 | * has to recompute where to put it anyway. |
| 4708 | */ |
| 4709 | } |
| 4710 | |
| 4711 | /** |
| 4712 | * intel_post_enable_primary - Perform operations after enabling primary plane |
| 4713 | * @crtc: the CRTC whose primary plane was just enabled |
| 4714 | * |
| 4715 | * Performs potentially sleeping operations that must be done after the primary |
| 4716 | * plane is enabled, such as updating FBC and IPS. Note that this may be |
| 4717 | * called due to an explicit primary plane update, or due to an implicit |
| 4718 | * re-enable that is caused when a sprite plane is updated to no longer |
| 4719 | * completely hide the primary plane. |
| 4720 | */ |
| 4721 | static void |
| 4722 | intel_post_enable_primary(struct drm_crtc *crtc) |
| 4723 | { |
| 4724 | struct drm_device *dev = crtc->dev; |
| 4725 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4726 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4727 | int pipe = intel_crtc->pipe; |
| 4728 | |
| 4729 | /* |
| 4730 | * FIXME IPS should be fine as long as one plane is |
| 4731 | * enabled, but in practice it seems to have problems |
| 4732 | * when going from primary only to sprite only and vice |
| 4733 | * versa. |
| 4734 | */ |
| 4735 | hsw_enable_ips(intel_crtc); |
| 4736 | |
| 4737 | /* |
| 4738 | * Gen2 reports pipe underruns whenever all planes are disabled. |
| 4739 | * So don't enable underrun reporting before at least some planes |
| 4740 | * are enabled. |
| 4741 | * FIXME: Need to fix the logic to work when we turn off all planes |
| 4742 | * but leave the pipe running. |
| 4743 | */ |
| 4744 | if (IS_GEN2(dev)) |
| 4745 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
| 4746 | |
| 4747 | /* Underruns don't always raise interrupts, so check manually. */ |
| 4748 | intel_check_cpu_fifo_underruns(dev_priv); |
| 4749 | intel_check_pch_fifo_underruns(dev_priv); |
| 4750 | } |
| 4751 | |
| 4752 | /** |
| 4753 | * intel_pre_disable_primary - Perform operations before disabling primary plane |
| 4754 | * @crtc: the CRTC whose primary plane is to be disabled |
| 4755 | * |
| 4756 | * Performs potentially sleeping operations that must be done before the |
| 4757 | * primary plane is disabled, such as updating FBC and IPS. Note that this may |
| 4758 | * be called due to an explicit primary plane update, or due to an implicit |
| 4759 | * disable that is caused when a sprite plane completely hides the primary |
| 4760 | * plane. |
| 4761 | */ |
| 4762 | static void |
| 4763 | intel_pre_disable_primary(struct drm_crtc *crtc) |
| 4764 | { |
| 4765 | struct drm_device *dev = crtc->dev; |
| 4766 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4767 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4768 | int pipe = intel_crtc->pipe; |
| 4769 | |
| 4770 | /* |
| 4771 | * Gen2 reports pipe underruns whenever all planes are disabled. |
| 4772 | * So diasble underrun reporting before all the planes get disabled. |
| 4773 | * FIXME: Need to fix the logic to work when we turn off all planes |
| 4774 | * but leave the pipe running. |
| 4775 | */ |
| 4776 | if (IS_GEN2(dev)) |
| 4777 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
| 4778 | |
| 4779 | /* |
| 4780 | * Vblank time updates from the shadow to live plane control register |
| 4781 | * are blocked if the memory self-refresh mode is active at that |
| 4782 | * moment. So to make sure the plane gets truly disabled, disable |
| 4783 | * first the self-refresh mode. The self-refresh enable bit in turn |
| 4784 | * will be checked/applied by the HW only at the next frame start |
| 4785 | * event which is after the vblank start event, so we need to have a |
| 4786 | * wait-for-vblank between disabling the plane and the pipe. |
| 4787 | */ |
| 4788 | if (HAS_GMCH_DISPLAY(dev)) { |
| 4789 | intel_set_memory_cxsr(dev_priv, false); |
| 4790 | dev_priv->wm.vlv.cxsr = false; |
| 4791 | intel_wait_for_vblank(dev, pipe); |
| 4792 | } |
| 4793 | |
| 4794 | /* |
| 4795 | * FIXME IPS should be fine as long as one plane is |
| 4796 | * enabled, but in practice it seems to have problems |
| 4797 | * when going from primary only to sprite only and vice |
| 4798 | * versa. |
| 4799 | */ |
| 4800 | hsw_disable_ips(intel_crtc); |
| 4801 | } |
| 4802 | |
| 4803 | static void intel_post_plane_update(struct intel_crtc *crtc) |
| 4804 | { |
| 4805 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; |
| 4806 | struct intel_crtc_state *pipe_config = |
| 4807 | to_intel_crtc_state(crtc->base.state); |
| 4808 | struct drm_device *dev = crtc->base.dev; |
| 4809 | |
| 4810 | if (atomic->wait_vblank) |
| 4811 | intel_wait_for_vblank(dev, crtc->pipe); |
| 4812 | |
| 4813 | intel_frontbuffer_flip(dev, atomic->fb_bits); |
| 4814 | |
| 4815 | crtc->wm.cxsr_allowed = true; |
| 4816 | |
| 4817 | if (pipe_config->wm_changed && pipe_config->base.active) |
| 4818 | intel_update_watermarks(&crtc->base); |
| 4819 | |
| 4820 | if (atomic->update_fbc) |
| 4821 | intel_fbc_update(crtc); |
| 4822 | |
| 4823 | if (atomic->post_enable_primary) |
| 4824 | intel_post_enable_primary(&crtc->base); |
| 4825 | |
| 4826 | memset(atomic, 0, sizeof(*atomic)); |
| 4827 | } |
| 4828 | |
| 4829 | static void intel_pre_plane_update(struct intel_crtc *crtc) |
| 4830 | { |
| 4831 | struct drm_device *dev = crtc->base.dev; |
| 4832 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4833 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; |
| 4834 | struct intel_crtc_state *pipe_config = |
| 4835 | to_intel_crtc_state(crtc->base.state); |
| 4836 | |
| 4837 | if (atomic->disable_fbc) |
| 4838 | intel_fbc_deactivate(crtc); |
| 4839 | |
| 4840 | if (crtc->atomic.disable_ips) |
| 4841 | hsw_disable_ips(crtc); |
| 4842 | |
| 4843 | if (atomic->pre_disable_primary) |
| 4844 | intel_pre_disable_primary(&crtc->base); |
| 4845 | |
| 4846 | if (pipe_config->disable_cxsr) { |
| 4847 | crtc->wm.cxsr_allowed = false; |
| 4848 | intel_set_memory_cxsr(dev_priv, false); |
| 4849 | } |
| 4850 | |
| 4851 | /* |
| 4852 | * IVB workaround: must disable low power watermarks for at least |
| 4853 | * one frame before enabling scaling. LP watermarks can be re-enabled |
| 4854 | * when scaling is disabled. |
| 4855 | * |
| 4856 | * WaCxSRDisabledForSpriteScaling:ivb |
| 4857 | */ |
| 4858 | if (pipe_config->disable_lp_wm) { |
| 4859 | ilk_disable_lp_wm(dev); |
| 4860 | intel_wait_for_vblank(dev, crtc->pipe); |
| 4861 | } |
| 4862 | |
| 4863 | /* |
| 4864 | * If we're doing a modeset, we're done. No need to do any pre-vblank |
| 4865 | * watermark programming here. |
| 4866 | */ |
| 4867 | if (needs_modeset(&pipe_config->base)) |
| 4868 | return; |
| 4869 | |
| 4870 | /* |
| 4871 | * For platforms that support atomic watermarks, program the |
| 4872 | * 'intermediate' watermarks immediately. On pre-gen9 platforms, these |
| 4873 | * will be the intermediate values that are safe for both pre- and |
| 4874 | * post- vblank; when vblank happens, the 'active' values will be set |
| 4875 | * to the final 'target' values and we'll do this again to get the |
| 4876 | * optimal watermarks. For gen9+ platforms, the values we program here |
| 4877 | * will be the final target values which will get automatically latched |
| 4878 | * at vblank time; no further programming will be necessary. |
| 4879 | * |
| 4880 | * If a platform hasn't been transitioned to atomic watermarks yet, |
| 4881 | * we'll continue to update watermarks the old way, if flags tell |
| 4882 | * us to. |
| 4883 | */ |
| 4884 | if (dev_priv->display.initial_watermarks != NULL) |
| 4885 | dev_priv->display.initial_watermarks(pipe_config); |
| 4886 | else if (pipe_config->wm_changed) |
| 4887 | intel_update_watermarks(&crtc->base); |
| 4888 | } |
| 4889 | |
| 4890 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
| 4891 | { |
| 4892 | struct drm_device *dev = crtc->dev; |
| 4893 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4894 | struct drm_plane *p; |
| 4895 | int pipe = intel_crtc->pipe; |
| 4896 | |
| 4897 | intel_crtc_dpms_overlay_disable(intel_crtc); |
| 4898 | |
| 4899 | drm_for_each_plane_mask(p, dev, plane_mask) |
| 4900 | to_intel_plane(p)->disable_plane(p, crtc); |
| 4901 | |
| 4902 | /* |
| 4903 | * FIXME: Once we grow proper nuclear flip support out of this we need |
| 4904 | * to compute the mask of flip planes precisely. For the time being |
| 4905 | * consider this a flip to a NULL plane. |
| 4906 | */ |
| 4907 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); |
| 4908 | } |
| 4909 | |
| 4910 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
| 4911 | { |
| 4912 | struct drm_device *dev = crtc->dev; |
| 4913 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4914 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4915 | struct intel_encoder *encoder; |
| 4916 | int pipe = intel_crtc->pipe; |
| 4917 | |
| 4918 | if (WARN_ON(intel_crtc->active)) |
| 4919 | return; |
| 4920 | |
| 4921 | if (intel_crtc->config->has_pch_encoder) |
| 4922 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
| 4923 | |
| 4924 | if (intel_crtc->config->has_pch_encoder) |
| 4925 | intel_prepare_shared_dpll(intel_crtc); |
| 4926 | |
| 4927 | if (intel_crtc->config->has_dp_encoder) |
| 4928 | intel_dp_set_m_n(intel_crtc, M1_N1); |
| 4929 | |
| 4930 | intel_set_pipe_timings(intel_crtc); |
| 4931 | |
| 4932 | if (intel_crtc->config->has_pch_encoder) { |
| 4933 | intel_cpu_transcoder_set_m_n(intel_crtc, |
| 4934 | &intel_crtc->config->fdi_m_n, NULL); |
| 4935 | } |
| 4936 | |
| 4937 | ironlake_set_pipeconf(crtc); |
| 4938 | |
| 4939 | intel_crtc->active = true; |
| 4940 | |
| 4941 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
| 4942 | |
| 4943 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 4944 | if (encoder->pre_enable) |
| 4945 | encoder->pre_enable(encoder); |
| 4946 | |
| 4947 | if (intel_crtc->config->has_pch_encoder) { |
| 4948 | /* Note: FDI PLL enabling _must_ be done before we enable the |
| 4949 | * cpu pipes, hence this is separate from all the other fdi/pch |
| 4950 | * enabling. */ |
| 4951 | ironlake_fdi_pll_enable(intel_crtc); |
| 4952 | } else { |
| 4953 | assert_fdi_tx_disabled(dev_priv, pipe); |
| 4954 | assert_fdi_rx_disabled(dev_priv, pipe); |
| 4955 | } |
| 4956 | |
| 4957 | ironlake_pfit_enable(intel_crtc); |
| 4958 | |
| 4959 | /* |
| 4960 | * On ILK+ LUT must be loaded before the pipe is running but with |
| 4961 | * clocks enabled |
| 4962 | */ |
| 4963 | intel_crtc_load_lut(crtc); |
| 4964 | |
| 4965 | intel_update_watermarks(crtc); |
| 4966 | intel_enable_pipe(intel_crtc); |
| 4967 | |
| 4968 | if (intel_crtc->config->has_pch_encoder) |
| 4969 | ironlake_pch_enable(crtc); |
| 4970 | |
| 4971 | assert_vblank_disabled(crtc); |
| 4972 | drm_crtc_vblank_on(crtc); |
| 4973 | |
| 4974 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 4975 | encoder->enable(encoder); |
| 4976 | |
| 4977 | if (HAS_PCH_CPT(dev)) |
| 4978 | cpt_verify_modeset(dev, intel_crtc->pipe); |
| 4979 | |
| 4980 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ |
| 4981 | if (intel_crtc->config->has_pch_encoder) |
| 4982 | intel_wait_for_vblank(dev, pipe); |
| 4983 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
| 4984 | |
| 4985 | intel_fbc_enable(intel_crtc); |
| 4986 | } |
| 4987 | |
| 4988 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
| 4989 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) |
| 4990 | { |
| 4991 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
| 4992 | } |
| 4993 | |
| 4994 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
| 4995 | { |
| 4996 | struct drm_device *dev = crtc->dev; |
| 4997 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4998 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4999 | struct intel_encoder *encoder; |
| 5000 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
| 5001 | struct intel_crtc_state *pipe_config = |
| 5002 | to_intel_crtc_state(crtc->state); |
| 5003 | |
| 5004 | if (WARN_ON(intel_crtc->active)) |
| 5005 | return; |
| 5006 | |
| 5007 | if (intel_crtc->config->has_pch_encoder) |
| 5008 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
| 5009 | false); |
| 5010 | |
| 5011 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
| 5012 | intel_enable_shared_dpll(intel_crtc); |
| 5013 | |
| 5014 | if (intel_crtc->config->has_dp_encoder) |
| 5015 | intel_dp_set_m_n(intel_crtc, M1_N1); |
| 5016 | |
| 5017 | intel_set_pipe_timings(intel_crtc); |
| 5018 | |
| 5019 | if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { |
| 5020 | I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), |
| 5021 | intel_crtc->config->pixel_multiplier - 1); |
| 5022 | } |
| 5023 | |
| 5024 | if (intel_crtc->config->has_pch_encoder) { |
| 5025 | intel_cpu_transcoder_set_m_n(intel_crtc, |
| 5026 | &intel_crtc->config->fdi_m_n, NULL); |
| 5027 | } |
| 5028 | |
| 5029 | haswell_set_pipeconf(crtc); |
| 5030 | |
| 5031 | intel_set_pipe_csc(crtc); |
| 5032 | |
| 5033 | intel_crtc->active = true; |
| 5034 | |
| 5035 | if (intel_crtc->config->has_pch_encoder) |
| 5036 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
| 5037 | else |
| 5038 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
| 5039 | |
| 5040 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
| 5041 | if (encoder->pre_enable) |
| 5042 | encoder->pre_enable(encoder); |
| 5043 | } |
| 5044 | |
| 5045 | if (intel_crtc->config->has_pch_encoder) |
| 5046 | dev_priv->display.fdi_link_train(crtc); |
| 5047 | |
| 5048 | if (!intel_crtc->config->has_dsi_encoder) |
| 5049 | intel_ddi_enable_pipe_clock(intel_crtc); |
| 5050 | |
| 5051 | if (INTEL_INFO(dev)->gen >= 9) |
| 5052 | skylake_pfit_enable(intel_crtc); |
| 5053 | else |
| 5054 | ironlake_pfit_enable(intel_crtc); |
| 5055 | |
| 5056 | /* |
| 5057 | * On ILK+ LUT must be loaded before the pipe is running but with |
| 5058 | * clocks enabled |
| 5059 | */ |
| 5060 | intel_crtc_load_lut(crtc); |
| 5061 | |
| 5062 | intel_ddi_set_pipe_settings(crtc); |
| 5063 | if (!intel_crtc->config->has_dsi_encoder) |
| 5064 | intel_ddi_enable_transcoder_func(crtc); |
| 5065 | |
| 5066 | intel_update_watermarks(crtc); |
| 5067 | intel_enable_pipe(intel_crtc); |
| 5068 | |
| 5069 | if (intel_crtc->config->has_pch_encoder) |
| 5070 | lpt_pch_enable(crtc); |
| 5071 | |
| 5072 | if (intel_crtc->config->dp_encoder_is_mst) |
| 5073 | intel_ddi_set_vc_payload_alloc(crtc, true); |
| 5074 | |
| 5075 | assert_vblank_disabled(crtc); |
| 5076 | drm_crtc_vblank_on(crtc); |
| 5077 | |
| 5078 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
| 5079 | encoder->enable(encoder); |
| 5080 | intel_opregion_notify_encoder(encoder, true); |
| 5081 | } |
| 5082 | |
| 5083 | if (intel_crtc->config->has_pch_encoder) { |
| 5084 | intel_wait_for_vblank(dev, pipe); |
| 5085 | intel_wait_for_vblank(dev, pipe); |
| 5086 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
| 5087 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
| 5088 | true); |
| 5089 | } |
| 5090 | |
| 5091 | /* If we change the relative order between pipe/planes enabling, we need |
| 5092 | * to change the workaround. */ |
| 5093 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
| 5094 | if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { |
| 5095 | intel_wait_for_vblank(dev, hsw_workaround_pipe); |
| 5096 | intel_wait_for_vblank(dev, hsw_workaround_pipe); |
| 5097 | } |
| 5098 | |
| 5099 | intel_fbc_enable(intel_crtc); |
| 5100 | } |
| 5101 | |
| 5102 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
| 5103 | { |
| 5104 | struct drm_device *dev = crtc->base.dev; |
| 5105 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5106 | int pipe = crtc->pipe; |
| 5107 | |
| 5108 | /* To avoid upsetting the power well on haswell only disable the pfit if |
| 5109 | * it's in use. The hw state code will make sure we get this right. */ |
| 5110 | if (force || crtc->config->pch_pfit.enabled) { |
| 5111 | I915_WRITE(PF_CTL(pipe), 0); |
| 5112 | I915_WRITE(PF_WIN_POS(pipe), 0); |
| 5113 | I915_WRITE(PF_WIN_SZ(pipe), 0); |
| 5114 | } |
| 5115 | } |
| 5116 | |
| 5117 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
| 5118 | { |
| 5119 | struct drm_device *dev = crtc->dev; |
| 5120 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5121 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 5122 | struct intel_encoder *encoder; |
| 5123 | int pipe = intel_crtc->pipe; |
| 5124 | |
| 5125 | if (intel_crtc->config->has_pch_encoder) |
| 5126 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
| 5127 | |
| 5128 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 5129 | encoder->disable(encoder); |
| 5130 | |
| 5131 | drm_crtc_vblank_off(crtc); |
| 5132 | assert_vblank_disabled(crtc); |
| 5133 | |
| 5134 | /* |
| 5135 | * Sometimes spurious CPU pipe underruns happen when the |
| 5136 | * pipe is already disabled, but FDI RX/TX is still enabled. |
| 5137 | * Happens at least with VGA+HDMI cloning. Suppress them. |
| 5138 | */ |
| 5139 | if (intel_crtc->config->has_pch_encoder) |
| 5140 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
| 5141 | |
| 5142 | intel_disable_pipe(intel_crtc); |
| 5143 | |
| 5144 | ironlake_pfit_disable(intel_crtc, false); |
| 5145 | |
| 5146 | if (intel_crtc->config->has_pch_encoder) { |
| 5147 | ironlake_fdi_disable(crtc); |
| 5148 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
| 5149 | } |
| 5150 | |
| 5151 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 5152 | if (encoder->post_disable) |
| 5153 | encoder->post_disable(encoder); |
| 5154 | |
| 5155 | if (intel_crtc->config->has_pch_encoder) { |
| 5156 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
| 5157 | |
| 5158 | if (HAS_PCH_CPT(dev)) { |
| 5159 | i915_reg_t reg; |
| 5160 | u32 temp; |
| 5161 | |
| 5162 | /* disable TRANS_DP_CTL */ |
| 5163 | reg = TRANS_DP_CTL(pipe); |
| 5164 | temp = I915_READ(reg); |
| 5165 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | |
| 5166 | TRANS_DP_PORT_SEL_MASK); |
| 5167 | temp |= TRANS_DP_PORT_SEL_NONE; |
| 5168 | I915_WRITE(reg, temp); |
| 5169 | |
| 5170 | /* disable DPLL_SEL */ |
| 5171 | temp = I915_READ(PCH_DPLL_SEL); |
| 5172 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
| 5173 | I915_WRITE(PCH_DPLL_SEL, temp); |
| 5174 | } |
| 5175 | |
| 5176 | ironlake_fdi_pll_disable(intel_crtc); |
| 5177 | } |
| 5178 | |
| 5179 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
| 5180 | |
| 5181 | intel_fbc_disable_crtc(intel_crtc); |
| 5182 | } |
| 5183 | |
| 5184 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
| 5185 | { |
| 5186 | struct drm_device *dev = crtc->dev; |
| 5187 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5188 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 5189 | struct intel_encoder *encoder; |
| 5190 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
| 5191 | |
| 5192 | if (intel_crtc->config->has_pch_encoder) |
| 5193 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
| 5194 | false); |
| 5195 | |
| 5196 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
| 5197 | intel_opregion_notify_encoder(encoder, false); |
| 5198 | encoder->disable(encoder); |
| 5199 | } |
| 5200 | |
| 5201 | drm_crtc_vblank_off(crtc); |
| 5202 | assert_vblank_disabled(crtc); |
| 5203 | |
| 5204 | intel_disable_pipe(intel_crtc); |
| 5205 | |
| 5206 | if (intel_crtc->config->dp_encoder_is_mst) |
| 5207 | intel_ddi_set_vc_payload_alloc(crtc, false); |
| 5208 | |
| 5209 | if (!intel_crtc->config->has_dsi_encoder) |
| 5210 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
| 5211 | |
| 5212 | if (INTEL_INFO(dev)->gen >= 9) |
| 5213 | skylake_scaler_disable(intel_crtc); |
| 5214 | else |
| 5215 | ironlake_pfit_disable(intel_crtc, false); |
| 5216 | |
| 5217 | if (!intel_crtc->config->has_dsi_encoder) |
| 5218 | intel_ddi_disable_pipe_clock(intel_crtc); |
| 5219 | |
| 5220 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 5221 | if (encoder->post_disable) |
| 5222 | encoder->post_disable(encoder); |
| 5223 | |
| 5224 | if (intel_crtc->config->has_pch_encoder) { |
| 5225 | lpt_disable_pch_transcoder(dev_priv); |
| 5226 | lpt_disable_iclkip(dev_priv); |
| 5227 | intel_ddi_fdi_disable(crtc); |
| 5228 | |
| 5229 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
| 5230 | true); |
| 5231 | } |
| 5232 | |
| 5233 | intel_fbc_disable_crtc(intel_crtc); |
| 5234 | } |
| 5235 | |
| 5236 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
| 5237 | { |
| 5238 | struct drm_device *dev = crtc->base.dev; |
| 5239 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5240 | struct intel_crtc_state *pipe_config = crtc->config; |
| 5241 | |
| 5242 | if (!pipe_config->gmch_pfit.control) |
| 5243 | return; |
| 5244 | |
| 5245 | /* |
| 5246 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
| 5247 | * according to register description and PRM. |
| 5248 | */ |
| 5249 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
| 5250 | assert_pipe_disabled(dev_priv, crtc->pipe); |
| 5251 | |
| 5252 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
| 5253 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); |
| 5254 | |
| 5255 | /* Border color in case we don't scale up to the full screen. Black by |
| 5256 | * default, change to something else for debugging. */ |
| 5257 | I915_WRITE(BCLRPAT(crtc->pipe), 0); |
| 5258 | } |
| 5259 | |
| 5260 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
| 5261 | { |
| 5262 | switch (port) { |
| 5263 | case PORT_A: |
| 5264 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
| 5265 | case PORT_B: |
| 5266 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
| 5267 | case PORT_C: |
| 5268 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
| 5269 | case PORT_D: |
| 5270 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
| 5271 | case PORT_E: |
| 5272 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
| 5273 | default: |
| 5274 | MISSING_CASE(port); |
| 5275 | return POWER_DOMAIN_PORT_OTHER; |
| 5276 | } |
| 5277 | } |
| 5278 | |
| 5279 | static enum intel_display_power_domain port_to_aux_power_domain(enum port port) |
| 5280 | { |
| 5281 | switch (port) { |
| 5282 | case PORT_A: |
| 5283 | return POWER_DOMAIN_AUX_A; |
| 5284 | case PORT_B: |
| 5285 | return POWER_DOMAIN_AUX_B; |
| 5286 | case PORT_C: |
| 5287 | return POWER_DOMAIN_AUX_C; |
| 5288 | case PORT_D: |
| 5289 | return POWER_DOMAIN_AUX_D; |
| 5290 | case PORT_E: |
| 5291 | /* FIXME: Check VBT for actual wiring of PORT E */ |
| 5292 | return POWER_DOMAIN_AUX_D; |
| 5293 | default: |
| 5294 | MISSING_CASE(port); |
| 5295 | return POWER_DOMAIN_AUX_A; |
| 5296 | } |
| 5297 | } |
| 5298 | |
| 5299 | enum intel_display_power_domain |
| 5300 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) |
| 5301 | { |
| 5302 | struct drm_device *dev = intel_encoder->base.dev; |
| 5303 | struct intel_digital_port *intel_dig_port; |
| 5304 | |
| 5305 | switch (intel_encoder->type) { |
| 5306 | case INTEL_OUTPUT_UNKNOWN: |
| 5307 | /* Only DDI platforms should ever use this output type */ |
| 5308 | WARN_ON_ONCE(!HAS_DDI(dev)); |
| 5309 | case INTEL_OUTPUT_DISPLAYPORT: |
| 5310 | case INTEL_OUTPUT_HDMI: |
| 5311 | case INTEL_OUTPUT_EDP: |
| 5312 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); |
| 5313 | return port_to_power_domain(intel_dig_port->port); |
| 5314 | case INTEL_OUTPUT_DP_MST: |
| 5315 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; |
| 5316 | return port_to_power_domain(intel_dig_port->port); |
| 5317 | case INTEL_OUTPUT_ANALOG: |
| 5318 | return POWER_DOMAIN_PORT_CRT; |
| 5319 | case INTEL_OUTPUT_DSI: |
| 5320 | return POWER_DOMAIN_PORT_DSI; |
| 5321 | default: |
| 5322 | return POWER_DOMAIN_PORT_OTHER; |
| 5323 | } |
| 5324 | } |
| 5325 | |
| 5326 | enum intel_display_power_domain |
| 5327 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) |
| 5328 | { |
| 5329 | struct drm_device *dev = intel_encoder->base.dev; |
| 5330 | struct intel_digital_port *intel_dig_port; |
| 5331 | |
| 5332 | switch (intel_encoder->type) { |
| 5333 | case INTEL_OUTPUT_UNKNOWN: |
| 5334 | case INTEL_OUTPUT_HDMI: |
| 5335 | /* |
| 5336 | * Only DDI platforms should ever use these output types. |
| 5337 | * We can get here after the HDMI detect code has already set |
| 5338 | * the type of the shared encoder. Since we can't be sure |
| 5339 | * what's the status of the given connectors, play safe and |
| 5340 | * run the DP detection too. |
| 5341 | */ |
| 5342 | WARN_ON_ONCE(!HAS_DDI(dev)); |
| 5343 | case INTEL_OUTPUT_DISPLAYPORT: |
| 5344 | case INTEL_OUTPUT_EDP: |
| 5345 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); |
| 5346 | return port_to_aux_power_domain(intel_dig_port->port); |
| 5347 | case INTEL_OUTPUT_DP_MST: |
| 5348 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; |
| 5349 | return port_to_aux_power_domain(intel_dig_port->port); |
| 5350 | default: |
| 5351 | MISSING_CASE(intel_encoder->type); |
| 5352 | return POWER_DOMAIN_AUX_A; |
| 5353 | } |
| 5354 | } |
| 5355 | |
| 5356 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) |
| 5357 | { |
| 5358 | struct drm_device *dev = crtc->dev; |
| 5359 | struct intel_encoder *intel_encoder; |
| 5360 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 5361 | enum pipe pipe = intel_crtc->pipe; |
| 5362 | unsigned long mask; |
| 5363 | enum transcoder transcoder = intel_crtc->config->cpu_transcoder; |
| 5364 | |
| 5365 | if (!crtc->state->active) |
| 5366 | return 0; |
| 5367 | |
| 5368 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
| 5369 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); |
| 5370 | if (intel_crtc->config->pch_pfit.enabled || |
| 5371 | intel_crtc->config->pch_pfit.force_thru) |
| 5372 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
| 5373 | |
| 5374 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
| 5375 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); |
| 5376 | |
| 5377 | return mask; |
| 5378 | } |
| 5379 | |
| 5380 | static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc) |
| 5381 | { |
| 5382 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
| 5383 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 5384 | enum intel_display_power_domain domain; |
| 5385 | unsigned long domains, new_domains, old_domains; |
| 5386 | |
| 5387 | old_domains = intel_crtc->enabled_power_domains; |
| 5388 | intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc); |
| 5389 | |
| 5390 | domains = new_domains & ~old_domains; |
| 5391 | |
| 5392 | for_each_power_domain(domain, domains) |
| 5393 | intel_display_power_get(dev_priv, domain); |
| 5394 | |
| 5395 | return old_domains & ~new_domains; |
| 5396 | } |
| 5397 | |
| 5398 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, |
| 5399 | unsigned long domains) |
| 5400 | { |
| 5401 | enum intel_display_power_domain domain; |
| 5402 | |
| 5403 | for_each_power_domain(domain, domains) |
| 5404 | intel_display_power_put(dev_priv, domain); |
| 5405 | } |
| 5406 | |
| 5407 | static void modeset_update_crtc_power_domains(struct drm_atomic_state *state) |
| 5408 | { |
| 5409 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
| 5410 | struct drm_device *dev = state->dev; |
| 5411 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5412 | unsigned long put_domains[I915_MAX_PIPES] = {}; |
| 5413 | struct drm_crtc_state *crtc_state; |
| 5414 | struct drm_crtc *crtc; |
| 5415 | int i; |
| 5416 | |
| 5417 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
| 5418 | if (needs_modeset(crtc->state)) |
| 5419 | put_domains[to_intel_crtc(crtc)->pipe] = |
| 5420 | modeset_get_crtc_power_domains(crtc); |
| 5421 | } |
| 5422 | |
| 5423 | if (dev_priv->display.modeset_commit_cdclk && |
| 5424 | intel_state->dev_cdclk != dev_priv->cdclk_freq) |
| 5425 | dev_priv->display.modeset_commit_cdclk(state); |
| 5426 | |
| 5427 | for (i = 0; i < I915_MAX_PIPES; i++) |
| 5428 | if (put_domains[i]) |
| 5429 | modeset_put_power_domains(dev_priv, put_domains[i]); |
| 5430 | } |
| 5431 | |
| 5432 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
| 5433 | { |
| 5434 | int max_cdclk_freq = dev_priv->max_cdclk_freq; |
| 5435 | |
| 5436 | if (INTEL_INFO(dev_priv)->gen >= 9 || |
| 5437 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
| 5438 | return max_cdclk_freq; |
| 5439 | else if (IS_CHERRYVIEW(dev_priv)) |
| 5440 | return max_cdclk_freq*95/100; |
| 5441 | else if (INTEL_INFO(dev_priv)->gen < 4) |
| 5442 | return 2*max_cdclk_freq*90/100; |
| 5443 | else |
| 5444 | return max_cdclk_freq*90/100; |
| 5445 | } |
| 5446 | |
| 5447 | static void intel_update_max_cdclk(struct drm_device *dev) |
| 5448 | { |
| 5449 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5450 | |
| 5451 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
| 5452 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
| 5453 | |
| 5454 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) |
| 5455 | dev_priv->max_cdclk_freq = 675000; |
| 5456 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) |
| 5457 | dev_priv->max_cdclk_freq = 540000; |
| 5458 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) |
| 5459 | dev_priv->max_cdclk_freq = 450000; |
| 5460 | else |
| 5461 | dev_priv->max_cdclk_freq = 337500; |
| 5462 | } else if (IS_BROADWELL(dev)) { |
| 5463 | /* |
| 5464 | * FIXME with extra cooling we can allow |
| 5465 | * 540 MHz for ULX and 675 Mhz for ULT. |
| 5466 | * How can we know if extra cooling is |
| 5467 | * available? PCI ID, VTB, something else? |
| 5468 | */ |
| 5469 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) |
| 5470 | dev_priv->max_cdclk_freq = 450000; |
| 5471 | else if (IS_BDW_ULX(dev)) |
| 5472 | dev_priv->max_cdclk_freq = 450000; |
| 5473 | else if (IS_BDW_ULT(dev)) |
| 5474 | dev_priv->max_cdclk_freq = 540000; |
| 5475 | else |
| 5476 | dev_priv->max_cdclk_freq = 675000; |
| 5477 | } else if (IS_CHERRYVIEW(dev)) { |
| 5478 | dev_priv->max_cdclk_freq = 320000; |
| 5479 | } else if (IS_VALLEYVIEW(dev)) { |
| 5480 | dev_priv->max_cdclk_freq = 400000; |
| 5481 | } else { |
| 5482 | /* otherwise assume cdclk is fixed */ |
| 5483 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; |
| 5484 | } |
| 5485 | |
| 5486 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); |
| 5487 | |
| 5488 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", |
| 5489 | dev_priv->max_cdclk_freq); |
| 5490 | |
| 5491 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", |
| 5492 | dev_priv->max_dotclk_freq); |
| 5493 | } |
| 5494 | |
| 5495 | static void intel_update_cdclk(struct drm_device *dev) |
| 5496 | { |
| 5497 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5498 | |
| 5499 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); |
| 5500 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", |
| 5501 | dev_priv->cdclk_freq); |
| 5502 | |
| 5503 | /* |
| 5504 | * Program the gmbus_freq based on the cdclk frequency. |
| 5505 | * BSpec erroneously claims we should aim for 4MHz, but |
| 5506 | * in fact 1MHz is the correct frequency. |
| 5507 | */ |
| 5508 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
| 5509 | /* |
| 5510 | * Program the gmbus_freq based on the cdclk frequency. |
| 5511 | * BSpec erroneously claims we should aim for 4MHz, but |
| 5512 | * in fact 1MHz is the correct frequency. |
| 5513 | */ |
| 5514 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); |
| 5515 | } |
| 5516 | |
| 5517 | if (dev_priv->max_cdclk_freq == 0) |
| 5518 | intel_update_max_cdclk(dev); |
| 5519 | } |
| 5520 | |
| 5521 | static void broxton_set_cdclk(struct drm_device *dev, int frequency) |
| 5522 | { |
| 5523 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5524 | uint32_t divider; |
| 5525 | uint32_t ratio; |
| 5526 | uint32_t current_freq; |
| 5527 | int ret; |
| 5528 | |
| 5529 | /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */ |
| 5530 | switch (frequency) { |
| 5531 | case 144000: |
| 5532 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; |
| 5533 | ratio = BXT_DE_PLL_RATIO(60); |
| 5534 | break; |
| 5535 | case 288000: |
| 5536 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; |
| 5537 | ratio = BXT_DE_PLL_RATIO(60); |
| 5538 | break; |
| 5539 | case 384000: |
| 5540 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; |
| 5541 | ratio = BXT_DE_PLL_RATIO(60); |
| 5542 | break; |
| 5543 | case 576000: |
| 5544 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; |
| 5545 | ratio = BXT_DE_PLL_RATIO(60); |
| 5546 | break; |
| 5547 | case 624000: |
| 5548 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; |
| 5549 | ratio = BXT_DE_PLL_RATIO(65); |
| 5550 | break; |
| 5551 | case 19200: |
| 5552 | /* |
| 5553 | * Bypass frequency with DE PLL disabled. Init ratio, divider |
| 5554 | * to suppress GCC warning. |
| 5555 | */ |
| 5556 | ratio = 0; |
| 5557 | divider = 0; |
| 5558 | break; |
| 5559 | default: |
| 5560 | DRM_ERROR("unsupported CDCLK freq %d", frequency); |
| 5561 | |
| 5562 | return; |
| 5563 | } |
| 5564 | |
| 5565 | mutex_lock(&dev_priv->rps.hw_lock); |
| 5566 | /* Inform power controller of upcoming frequency change */ |
| 5567 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, |
| 5568 | 0x80000000); |
| 5569 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 5570 | |
| 5571 | if (ret) { |
| 5572 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", |
| 5573 | ret, frequency); |
| 5574 | return; |
| 5575 | } |
| 5576 | |
| 5577 | current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK; |
| 5578 | /* convert from .1 fixpoint MHz with -1MHz offset to kHz */ |
| 5579 | current_freq = current_freq * 500 + 1000; |
| 5580 | |
| 5581 | /* |
| 5582 | * DE PLL has to be disabled when |
| 5583 | * - setting to 19.2MHz (bypass, PLL isn't used) |
| 5584 | * - before setting to 624MHz (PLL needs toggling) |
| 5585 | * - before setting to any frequency from 624MHz (PLL needs toggling) |
| 5586 | */ |
| 5587 | if (frequency == 19200 || frequency == 624000 || |
| 5588 | current_freq == 624000) { |
| 5589 | I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE); |
| 5590 | /* Timeout 200us */ |
| 5591 | if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), |
| 5592 | 1)) |
| 5593 | DRM_ERROR("timout waiting for DE PLL unlock\n"); |
| 5594 | } |
| 5595 | |
| 5596 | if (frequency != 19200) { |
| 5597 | uint32_t val; |
| 5598 | |
| 5599 | val = I915_READ(BXT_DE_PLL_CTL); |
| 5600 | val &= ~BXT_DE_PLL_RATIO_MASK; |
| 5601 | val |= ratio; |
| 5602 | I915_WRITE(BXT_DE_PLL_CTL, val); |
| 5603 | |
| 5604 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); |
| 5605 | /* Timeout 200us */ |
| 5606 | if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) |
| 5607 | DRM_ERROR("timeout waiting for DE PLL lock\n"); |
| 5608 | |
| 5609 | val = I915_READ(CDCLK_CTL); |
| 5610 | val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK; |
| 5611 | val |= divider; |
| 5612 | /* |
| 5613 | * Disable SSA Precharge when CD clock frequency < 500 MHz, |
| 5614 | * enable otherwise. |
| 5615 | */ |
| 5616 | val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE; |
| 5617 | if (frequency >= 500000) |
| 5618 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; |
| 5619 | |
| 5620 | val &= ~CDCLK_FREQ_DECIMAL_MASK; |
| 5621 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ |
| 5622 | val |= (frequency - 1000) / 500; |
| 5623 | I915_WRITE(CDCLK_CTL, val); |
| 5624 | } |
| 5625 | |
| 5626 | mutex_lock(&dev_priv->rps.hw_lock); |
| 5627 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, |
| 5628 | DIV_ROUND_UP(frequency, 25000)); |
| 5629 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 5630 | |
| 5631 | if (ret) { |
| 5632 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", |
| 5633 | ret, frequency); |
| 5634 | return; |
| 5635 | } |
| 5636 | |
| 5637 | intel_update_cdclk(dev); |
| 5638 | } |
| 5639 | |
| 5640 | void broxton_init_cdclk(struct drm_device *dev) |
| 5641 | { |
| 5642 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5643 | uint32_t val; |
| 5644 | |
| 5645 | /* |
| 5646 | * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT |
| 5647 | * or else the reset will hang because there is no PCH to respond. |
| 5648 | * Move the handshake programming to initialization sequence. |
| 5649 | * Previously was left up to BIOS. |
| 5650 | */ |
| 5651 | val = I915_READ(HSW_NDE_RSTWRN_OPT); |
| 5652 | val &= ~RESET_PCH_HANDSHAKE_ENABLE; |
| 5653 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val); |
| 5654 | |
| 5655 | /* Enable PG1 for cdclk */ |
| 5656 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
| 5657 | |
| 5658 | /* check if cd clock is enabled */ |
| 5659 | if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) { |
| 5660 | DRM_DEBUG_KMS("Display already initialized\n"); |
| 5661 | return; |
| 5662 | } |
| 5663 | |
| 5664 | /* |
| 5665 | * FIXME: |
| 5666 | * - The initial CDCLK needs to be read from VBT. |
| 5667 | * Need to make this change after VBT has changes for BXT. |
| 5668 | * - check if setting the max (or any) cdclk freq is really necessary |
| 5669 | * here, it belongs to modeset time |
| 5670 | */ |
| 5671 | broxton_set_cdclk(dev, 624000); |
| 5672 | |
| 5673 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); |
| 5674 | POSTING_READ(DBUF_CTL); |
| 5675 | |
| 5676 | udelay(10); |
| 5677 | |
| 5678 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) |
| 5679 | DRM_ERROR("DBuf power enable timeout!\n"); |
| 5680 | } |
| 5681 | |
| 5682 | void broxton_uninit_cdclk(struct drm_device *dev) |
| 5683 | { |
| 5684 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5685 | |
| 5686 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); |
| 5687 | POSTING_READ(DBUF_CTL); |
| 5688 | |
| 5689 | udelay(10); |
| 5690 | |
| 5691 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) |
| 5692 | DRM_ERROR("DBuf power disable timeout!\n"); |
| 5693 | |
| 5694 | /* Set minimum (bypass) frequency, in effect turning off the DE PLL */ |
| 5695 | broxton_set_cdclk(dev, 19200); |
| 5696 | |
| 5697 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
| 5698 | } |
| 5699 | |
| 5700 | static const struct skl_cdclk_entry { |
| 5701 | unsigned int freq; |
| 5702 | unsigned int vco; |
| 5703 | } skl_cdclk_frequencies[] = { |
| 5704 | { .freq = 308570, .vco = 8640 }, |
| 5705 | { .freq = 337500, .vco = 8100 }, |
| 5706 | { .freq = 432000, .vco = 8640 }, |
| 5707 | { .freq = 450000, .vco = 8100 }, |
| 5708 | { .freq = 540000, .vco = 8100 }, |
| 5709 | { .freq = 617140, .vco = 8640 }, |
| 5710 | { .freq = 675000, .vco = 8100 }, |
| 5711 | }; |
| 5712 | |
| 5713 | static unsigned int skl_cdclk_decimal(unsigned int freq) |
| 5714 | { |
| 5715 | return (freq - 1000) / 500; |
| 5716 | } |
| 5717 | |
| 5718 | static unsigned int skl_cdclk_get_vco(unsigned int freq) |
| 5719 | { |
| 5720 | unsigned int i; |
| 5721 | |
| 5722 | for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) { |
| 5723 | const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i]; |
| 5724 | |
| 5725 | if (e->freq == freq) |
| 5726 | return e->vco; |
| 5727 | } |
| 5728 | |
| 5729 | return 8100; |
| 5730 | } |
| 5731 | |
| 5732 | static void |
| 5733 | skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco) |
| 5734 | { |
| 5735 | unsigned int min_freq; |
| 5736 | u32 val; |
| 5737 | |
| 5738 | /* select the minimum CDCLK before enabling DPLL 0 */ |
| 5739 | val = I915_READ(CDCLK_CTL); |
| 5740 | val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK; |
| 5741 | val |= CDCLK_FREQ_337_308; |
| 5742 | |
| 5743 | if (required_vco == 8640) |
| 5744 | min_freq = 308570; |
| 5745 | else |
| 5746 | min_freq = 337500; |
| 5747 | |
| 5748 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq); |
| 5749 | |
| 5750 | I915_WRITE(CDCLK_CTL, val); |
| 5751 | POSTING_READ(CDCLK_CTL); |
| 5752 | |
| 5753 | /* |
| 5754 | * We always enable DPLL0 with the lowest link rate possible, but still |
| 5755 | * taking into account the VCO required to operate the eDP panel at the |
| 5756 | * desired frequency. The usual DP link rates operate with a VCO of |
| 5757 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. |
| 5758 | * The modeset code is responsible for the selection of the exact link |
| 5759 | * rate later on, with the constraint of choosing a frequency that |
| 5760 | * works with required_vco. |
| 5761 | */ |
| 5762 | val = I915_READ(DPLL_CTRL1); |
| 5763 | |
| 5764 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | |
| 5765 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); |
| 5766 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); |
| 5767 | if (required_vco == 8640) |
| 5768 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, |
| 5769 | SKL_DPLL0); |
| 5770 | else |
| 5771 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, |
| 5772 | SKL_DPLL0); |
| 5773 | |
| 5774 | I915_WRITE(DPLL_CTRL1, val); |
| 5775 | POSTING_READ(DPLL_CTRL1); |
| 5776 | |
| 5777 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); |
| 5778 | |
| 5779 | if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5)) |
| 5780 | DRM_ERROR("DPLL0 not locked\n"); |
| 5781 | } |
| 5782 | |
| 5783 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) |
| 5784 | { |
| 5785 | int ret; |
| 5786 | u32 val; |
| 5787 | |
| 5788 | /* inform PCU we want to change CDCLK */ |
| 5789 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; |
| 5790 | mutex_lock(&dev_priv->rps.hw_lock); |
| 5791 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); |
| 5792 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 5793 | |
| 5794 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); |
| 5795 | } |
| 5796 | |
| 5797 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) |
| 5798 | { |
| 5799 | unsigned int i; |
| 5800 | |
| 5801 | for (i = 0; i < 15; i++) { |
| 5802 | if (skl_cdclk_pcu_ready(dev_priv)) |
| 5803 | return true; |
| 5804 | udelay(10); |
| 5805 | } |
| 5806 | |
| 5807 | return false; |
| 5808 | } |
| 5809 | |
| 5810 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq) |
| 5811 | { |
| 5812 | struct drm_device *dev = dev_priv->dev; |
| 5813 | u32 freq_select, pcu_ack; |
| 5814 | |
| 5815 | DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq); |
| 5816 | |
| 5817 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { |
| 5818 | DRM_ERROR("failed to inform PCU about cdclk change\n"); |
| 5819 | return; |
| 5820 | } |
| 5821 | |
| 5822 | /* set CDCLK_CTL */ |
| 5823 | switch(freq) { |
| 5824 | case 450000: |
| 5825 | case 432000: |
| 5826 | freq_select = CDCLK_FREQ_450_432; |
| 5827 | pcu_ack = 1; |
| 5828 | break; |
| 5829 | case 540000: |
| 5830 | freq_select = CDCLK_FREQ_540; |
| 5831 | pcu_ack = 2; |
| 5832 | break; |
| 5833 | case 308570: |
| 5834 | case 337500: |
| 5835 | default: |
| 5836 | freq_select = CDCLK_FREQ_337_308; |
| 5837 | pcu_ack = 0; |
| 5838 | break; |
| 5839 | case 617140: |
| 5840 | case 675000: |
| 5841 | freq_select = CDCLK_FREQ_675_617; |
| 5842 | pcu_ack = 3; |
| 5843 | break; |
| 5844 | } |
| 5845 | |
| 5846 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq)); |
| 5847 | POSTING_READ(CDCLK_CTL); |
| 5848 | |
| 5849 | /* inform PCU of the change */ |
| 5850 | mutex_lock(&dev_priv->rps.hw_lock); |
| 5851 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); |
| 5852 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 5853 | |
| 5854 | intel_update_cdclk(dev); |
| 5855 | } |
| 5856 | |
| 5857 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) |
| 5858 | { |
| 5859 | /* disable DBUF power */ |
| 5860 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); |
| 5861 | POSTING_READ(DBUF_CTL); |
| 5862 | |
| 5863 | udelay(10); |
| 5864 | |
| 5865 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) |
| 5866 | DRM_ERROR("DBuf power disable timeout\n"); |
| 5867 | |
| 5868 | /* disable DPLL0 */ |
| 5869 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); |
| 5870 | if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) |
| 5871 | DRM_ERROR("Couldn't disable DPLL0\n"); |
| 5872 | } |
| 5873 | |
| 5874 | void skl_init_cdclk(struct drm_i915_private *dev_priv) |
| 5875 | { |
| 5876 | unsigned int required_vco; |
| 5877 | |
| 5878 | /* DPLL0 not enabled (happens on early BIOS versions) */ |
| 5879 | if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) { |
| 5880 | /* enable DPLL0 */ |
| 5881 | required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk); |
| 5882 | skl_dpll0_enable(dev_priv, required_vco); |
| 5883 | } |
| 5884 | |
| 5885 | /* set CDCLK to the frequency the BIOS chose */ |
| 5886 | skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk); |
| 5887 | |
| 5888 | /* enable DBUF power */ |
| 5889 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); |
| 5890 | POSTING_READ(DBUF_CTL); |
| 5891 | |
| 5892 | udelay(10); |
| 5893 | |
| 5894 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) |
| 5895 | DRM_ERROR("DBuf power enable timeout\n"); |
| 5896 | } |
| 5897 | |
| 5898 | int skl_sanitize_cdclk(struct drm_i915_private *dev_priv) |
| 5899 | { |
| 5900 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); |
| 5901 | uint32_t cdctl = I915_READ(CDCLK_CTL); |
| 5902 | int freq = dev_priv->skl_boot_cdclk; |
| 5903 | |
| 5904 | /* |
| 5905 | * check if the pre-os intialized the display |
| 5906 | * There is SWF18 scratchpad register defined which is set by the |
| 5907 | * pre-os which can be used by the OS drivers to check the status |
| 5908 | */ |
| 5909 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) |
| 5910 | goto sanitize; |
| 5911 | |
| 5912 | /* Is PLL enabled and locked ? */ |
| 5913 | if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK))) |
| 5914 | goto sanitize; |
| 5915 | |
| 5916 | /* DPLL okay; verify the cdclock |
| 5917 | * |
| 5918 | * Noticed in some instances that the freq selection is correct but |
| 5919 | * decimal part is programmed wrong from BIOS where pre-os does not |
| 5920 | * enable display. Verify the same as well. |
| 5921 | */ |
| 5922 | if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq))) |
| 5923 | /* All well; nothing to sanitize */ |
| 5924 | return false; |
| 5925 | sanitize: |
| 5926 | /* |
| 5927 | * As of now initialize with max cdclk till |
| 5928 | * we get dynamic cdclk support |
| 5929 | * */ |
| 5930 | dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq; |
| 5931 | skl_init_cdclk(dev_priv); |
| 5932 | |
| 5933 | /* we did have to sanitize */ |
| 5934 | return true; |
| 5935 | } |
| 5936 | |
| 5937 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
| 5938 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) |
| 5939 | { |
| 5940 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5941 | u32 val, cmd; |
| 5942 | |
| 5943 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
| 5944 | != dev_priv->cdclk_freq); |
| 5945 | |
| 5946 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
| 5947 | cmd = 2; |
| 5948 | else if (cdclk == 266667) |
| 5949 | cmd = 1; |
| 5950 | else |
| 5951 | cmd = 0; |
| 5952 | |
| 5953 | mutex_lock(&dev_priv->rps.hw_lock); |
| 5954 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); |
| 5955 | val &= ~DSPFREQGUAR_MASK; |
| 5956 | val |= (cmd << DSPFREQGUAR_SHIFT); |
| 5957 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); |
| 5958 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & |
| 5959 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), |
| 5960 | 50)) { |
| 5961 | DRM_ERROR("timed out waiting for CDclk change\n"); |
| 5962 | } |
| 5963 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 5964 | |
| 5965 | mutex_lock(&dev_priv->sb_lock); |
| 5966 | |
| 5967 | if (cdclk == 400000) { |
| 5968 | u32 divider; |
| 5969 | |
| 5970 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
| 5971 | |
| 5972 | /* adjust cdclk divider */ |
| 5973 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); |
| 5974 | val &= ~CCK_FREQUENCY_VALUES; |
| 5975 | val |= divider; |
| 5976 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); |
| 5977 | |
| 5978 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & |
| 5979 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), |
| 5980 | 50)) |
| 5981 | DRM_ERROR("timed out waiting for CDclk change\n"); |
| 5982 | } |
| 5983 | |
| 5984 | /* adjust self-refresh exit latency value */ |
| 5985 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); |
| 5986 | val &= ~0x7f; |
| 5987 | |
| 5988 | /* |
| 5989 | * For high bandwidth configs, we set a higher latency in the bunit |
| 5990 | * so that the core display fetch happens in time to avoid underruns. |
| 5991 | */ |
| 5992 | if (cdclk == 400000) |
| 5993 | val |= 4500 / 250; /* 4.5 usec */ |
| 5994 | else |
| 5995 | val |= 3000 / 250; /* 3.0 usec */ |
| 5996 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); |
| 5997 | |
| 5998 | mutex_unlock(&dev_priv->sb_lock); |
| 5999 | |
| 6000 | intel_update_cdclk(dev); |
| 6001 | } |
| 6002 | |
| 6003 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
| 6004 | { |
| 6005 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6006 | u32 val, cmd; |
| 6007 | |
| 6008 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
| 6009 | != dev_priv->cdclk_freq); |
| 6010 | |
| 6011 | switch (cdclk) { |
| 6012 | case 333333: |
| 6013 | case 320000: |
| 6014 | case 266667: |
| 6015 | case 200000: |
| 6016 | break; |
| 6017 | default: |
| 6018 | MISSING_CASE(cdclk); |
| 6019 | return; |
| 6020 | } |
| 6021 | |
| 6022 | /* |
| 6023 | * Specs are full of misinformation, but testing on actual |
| 6024 | * hardware has shown that we just need to write the desired |
| 6025 | * CCK divider into the Punit register. |
| 6026 | */ |
| 6027 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
| 6028 | |
| 6029 | mutex_lock(&dev_priv->rps.hw_lock); |
| 6030 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); |
| 6031 | val &= ~DSPFREQGUAR_MASK_CHV; |
| 6032 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); |
| 6033 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); |
| 6034 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & |
| 6035 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), |
| 6036 | 50)) { |
| 6037 | DRM_ERROR("timed out waiting for CDclk change\n"); |
| 6038 | } |
| 6039 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 6040 | |
| 6041 | intel_update_cdclk(dev); |
| 6042 | } |
| 6043 | |
| 6044 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
| 6045 | int max_pixclk) |
| 6046 | { |
| 6047 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
| 6048 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
| 6049 | |
| 6050 | /* |
| 6051 | * Really only a few cases to deal with, as only 4 CDclks are supported: |
| 6052 | * 200MHz |
| 6053 | * 267MHz |
| 6054 | * 320/333MHz (depends on HPLL freq) |
| 6055 | * 400MHz (VLV only) |
| 6056 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) |
| 6057 | * of the lower bin and adjust if needed. |
| 6058 | * |
| 6059 | * We seem to get an unstable or solid color picture at 200MHz. |
| 6060 | * Not sure what's wrong. For now use 200MHz only when all pipes |
| 6061 | * are off. |
| 6062 | */ |
| 6063 | if (!IS_CHERRYVIEW(dev_priv) && |
| 6064 | max_pixclk > freq_320*limit/100) |
| 6065 | return 400000; |
| 6066 | else if (max_pixclk > 266667*limit/100) |
| 6067 | return freq_320; |
| 6068 | else if (max_pixclk > 0) |
| 6069 | return 266667; |
| 6070 | else |
| 6071 | return 200000; |
| 6072 | } |
| 6073 | |
| 6074 | static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, |
| 6075 | int max_pixclk) |
| 6076 | { |
| 6077 | /* |
| 6078 | * FIXME: |
| 6079 | * - remove the guardband, it's not needed on BXT |
| 6080 | * - set 19.2MHz bypass frequency if there are no active pipes |
| 6081 | */ |
| 6082 | if (max_pixclk > 576000*9/10) |
| 6083 | return 624000; |
| 6084 | else if (max_pixclk > 384000*9/10) |
| 6085 | return 576000; |
| 6086 | else if (max_pixclk > 288000*9/10) |
| 6087 | return 384000; |
| 6088 | else if (max_pixclk > 144000*9/10) |
| 6089 | return 288000; |
| 6090 | else |
| 6091 | return 144000; |
| 6092 | } |
| 6093 | |
| 6094 | /* Compute the max pixel clock for new configuration. Uses atomic state if |
| 6095 | * that's non-NULL, look at current state otherwise. */ |
| 6096 | static int intel_mode_max_pixclk(struct drm_device *dev, |
| 6097 | struct drm_atomic_state *state) |
| 6098 | { |
| 6099 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
| 6100 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6101 | struct drm_crtc *crtc; |
| 6102 | struct drm_crtc_state *crtc_state; |
| 6103 | unsigned max_pixclk = 0, i; |
| 6104 | enum pipe pipe; |
| 6105 | |
| 6106 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
| 6107 | sizeof(intel_state->min_pixclk)); |
| 6108 | |
| 6109 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
| 6110 | int pixclk = 0; |
| 6111 | |
| 6112 | if (crtc_state->enable) |
| 6113 | pixclk = crtc_state->adjusted_mode.crtc_clock; |
| 6114 | |
| 6115 | intel_state->min_pixclk[i] = pixclk; |
| 6116 | } |
| 6117 | |
| 6118 | if (!intel_state->active_crtcs) |
| 6119 | return 0; |
| 6120 | |
| 6121 | for_each_pipe(dev_priv, pipe) |
| 6122 | max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk); |
| 6123 | |
| 6124 | return max_pixclk; |
| 6125 | } |
| 6126 | |
| 6127 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
| 6128 | { |
| 6129 | struct drm_device *dev = state->dev; |
| 6130 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6131 | int max_pixclk = intel_mode_max_pixclk(dev, state); |
| 6132 | struct intel_atomic_state *intel_state = |
| 6133 | to_intel_atomic_state(state); |
| 6134 | |
| 6135 | if (max_pixclk < 0) |
| 6136 | return max_pixclk; |
| 6137 | |
| 6138 | intel_state->cdclk = intel_state->dev_cdclk = |
| 6139 | valleyview_calc_cdclk(dev_priv, max_pixclk); |
| 6140 | |
| 6141 | if (!intel_state->active_crtcs) |
| 6142 | intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0); |
| 6143 | |
| 6144 | return 0; |
| 6145 | } |
| 6146 | |
| 6147 | static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state) |
| 6148 | { |
| 6149 | struct drm_device *dev = state->dev; |
| 6150 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6151 | int max_pixclk = intel_mode_max_pixclk(dev, state); |
| 6152 | struct intel_atomic_state *intel_state = |
| 6153 | to_intel_atomic_state(state); |
| 6154 | |
| 6155 | if (max_pixclk < 0) |
| 6156 | return max_pixclk; |
| 6157 | |
| 6158 | intel_state->cdclk = intel_state->dev_cdclk = |
| 6159 | broxton_calc_cdclk(dev_priv, max_pixclk); |
| 6160 | |
| 6161 | if (!intel_state->active_crtcs) |
| 6162 | intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0); |
| 6163 | |
| 6164 | return 0; |
| 6165 | } |
| 6166 | |
| 6167 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
| 6168 | { |
| 6169 | unsigned int credits, default_credits; |
| 6170 | |
| 6171 | if (IS_CHERRYVIEW(dev_priv)) |
| 6172 | default_credits = PFI_CREDIT(12); |
| 6173 | else |
| 6174 | default_credits = PFI_CREDIT(8); |
| 6175 | |
| 6176 | if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { |
| 6177 | /* CHV suggested value is 31 or 63 */ |
| 6178 | if (IS_CHERRYVIEW(dev_priv)) |
| 6179 | credits = PFI_CREDIT_63; |
| 6180 | else |
| 6181 | credits = PFI_CREDIT(15); |
| 6182 | } else { |
| 6183 | credits = default_credits; |
| 6184 | } |
| 6185 | |
| 6186 | /* |
| 6187 | * WA - write default credits before re-programming |
| 6188 | * FIXME: should we also set the resend bit here? |
| 6189 | */ |
| 6190 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | |
| 6191 | default_credits); |
| 6192 | |
| 6193 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | |
| 6194 | credits | PFI_CREDIT_RESEND); |
| 6195 | |
| 6196 | /* |
| 6197 | * FIXME is this guaranteed to clear |
| 6198 | * immediately or should we poll for it? |
| 6199 | */ |
| 6200 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); |
| 6201 | } |
| 6202 | |
| 6203 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
| 6204 | { |
| 6205 | struct drm_device *dev = old_state->dev; |
| 6206 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6207 | struct intel_atomic_state *old_intel_state = |
| 6208 | to_intel_atomic_state(old_state); |
| 6209 | unsigned req_cdclk = old_intel_state->dev_cdclk; |
| 6210 | |
| 6211 | /* |
| 6212 | * FIXME: We can end up here with all power domains off, yet |
| 6213 | * with a CDCLK frequency other than the minimum. To account |
| 6214 | * for this take the PIPE-A power domain, which covers the HW |
| 6215 | * blocks needed for the following programming. This can be |
| 6216 | * removed once it's guaranteed that we get here either with |
| 6217 | * the minimum CDCLK set, or the required power domains |
| 6218 | * enabled. |
| 6219 | */ |
| 6220 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); |
| 6221 | |
| 6222 | if (IS_CHERRYVIEW(dev)) |
| 6223 | cherryview_set_cdclk(dev, req_cdclk); |
| 6224 | else |
| 6225 | valleyview_set_cdclk(dev, req_cdclk); |
| 6226 | |
| 6227 | vlv_program_pfi_credits(dev_priv); |
| 6228 | |
| 6229 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
| 6230 | } |
| 6231 | |
| 6232 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
| 6233 | { |
| 6234 | struct drm_device *dev = crtc->dev; |
| 6235 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 6236 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 6237 | struct intel_encoder *encoder; |
| 6238 | int pipe = intel_crtc->pipe; |
| 6239 | |
| 6240 | if (WARN_ON(intel_crtc->active)) |
| 6241 | return; |
| 6242 | |
| 6243 | if (intel_crtc->config->has_dp_encoder) |
| 6244 | intel_dp_set_m_n(intel_crtc, M1_N1); |
| 6245 | |
| 6246 | intel_set_pipe_timings(intel_crtc); |
| 6247 | |
| 6248 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
| 6249 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6250 | |
| 6251 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); |
| 6252 | I915_WRITE(CHV_CANVAS(pipe), 0); |
| 6253 | } |
| 6254 | |
| 6255 | i9xx_set_pipeconf(intel_crtc); |
| 6256 | |
| 6257 | intel_crtc->active = true; |
| 6258 | |
| 6259 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
| 6260 | |
| 6261 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 6262 | if (encoder->pre_pll_enable) |
| 6263 | encoder->pre_pll_enable(encoder); |
| 6264 | |
| 6265 | if (!intel_crtc->config->has_dsi_encoder) { |
| 6266 | if (IS_CHERRYVIEW(dev)) { |
| 6267 | chv_prepare_pll(intel_crtc, intel_crtc->config); |
| 6268 | chv_enable_pll(intel_crtc, intel_crtc->config); |
| 6269 | } else { |
| 6270 | vlv_prepare_pll(intel_crtc, intel_crtc->config); |
| 6271 | vlv_enable_pll(intel_crtc, intel_crtc->config); |
| 6272 | } |
| 6273 | } |
| 6274 | |
| 6275 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 6276 | if (encoder->pre_enable) |
| 6277 | encoder->pre_enable(encoder); |
| 6278 | |
| 6279 | i9xx_pfit_enable(intel_crtc); |
| 6280 | |
| 6281 | intel_crtc_load_lut(crtc); |
| 6282 | |
| 6283 | intel_enable_pipe(intel_crtc); |
| 6284 | |
| 6285 | assert_vblank_disabled(crtc); |
| 6286 | drm_crtc_vblank_on(crtc); |
| 6287 | |
| 6288 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 6289 | encoder->enable(encoder); |
| 6290 | } |
| 6291 | |
| 6292 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
| 6293 | { |
| 6294 | struct drm_device *dev = crtc->base.dev; |
| 6295 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6296 | |
| 6297 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
| 6298 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); |
| 6299 | } |
| 6300 | |
| 6301 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
| 6302 | { |
| 6303 | struct drm_device *dev = crtc->dev; |
| 6304 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 6305 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 6306 | struct intel_encoder *encoder; |
| 6307 | int pipe = intel_crtc->pipe; |
| 6308 | |
| 6309 | if (WARN_ON(intel_crtc->active)) |
| 6310 | return; |
| 6311 | |
| 6312 | i9xx_set_pll_dividers(intel_crtc); |
| 6313 | |
| 6314 | if (intel_crtc->config->has_dp_encoder) |
| 6315 | intel_dp_set_m_n(intel_crtc, M1_N1); |
| 6316 | |
| 6317 | intel_set_pipe_timings(intel_crtc); |
| 6318 | |
| 6319 | i9xx_set_pipeconf(intel_crtc); |
| 6320 | |
| 6321 | intel_crtc->active = true; |
| 6322 | |
| 6323 | if (!IS_GEN2(dev)) |
| 6324 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
| 6325 | |
| 6326 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 6327 | if (encoder->pre_enable) |
| 6328 | encoder->pre_enable(encoder); |
| 6329 | |
| 6330 | i9xx_enable_pll(intel_crtc); |
| 6331 | |
| 6332 | i9xx_pfit_enable(intel_crtc); |
| 6333 | |
| 6334 | intel_crtc_load_lut(crtc); |
| 6335 | |
| 6336 | intel_update_watermarks(crtc); |
| 6337 | intel_enable_pipe(intel_crtc); |
| 6338 | |
| 6339 | assert_vblank_disabled(crtc); |
| 6340 | drm_crtc_vblank_on(crtc); |
| 6341 | |
| 6342 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 6343 | encoder->enable(encoder); |
| 6344 | |
| 6345 | intel_fbc_enable(intel_crtc); |
| 6346 | } |
| 6347 | |
| 6348 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
| 6349 | { |
| 6350 | struct drm_device *dev = crtc->base.dev; |
| 6351 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6352 | |
| 6353 | if (!crtc->config->gmch_pfit.control) |
| 6354 | return; |
| 6355 | |
| 6356 | assert_pipe_disabled(dev_priv, crtc->pipe); |
| 6357 | |
| 6358 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
| 6359 | I915_READ(PFIT_CONTROL)); |
| 6360 | I915_WRITE(PFIT_CONTROL, 0); |
| 6361 | } |
| 6362 | |
| 6363 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
| 6364 | { |
| 6365 | struct drm_device *dev = crtc->dev; |
| 6366 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6367 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 6368 | struct intel_encoder *encoder; |
| 6369 | int pipe = intel_crtc->pipe; |
| 6370 | |
| 6371 | /* |
| 6372 | * On gen2 planes are double buffered but the pipe isn't, so we must |
| 6373 | * wait for planes to fully turn off before disabling the pipe. |
| 6374 | * We also need to wait on all gmch platforms because of the |
| 6375 | * self-refresh mode constraint explained above. |
| 6376 | */ |
| 6377 | intel_wait_for_vblank(dev, pipe); |
| 6378 | |
| 6379 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 6380 | encoder->disable(encoder); |
| 6381 | |
| 6382 | drm_crtc_vblank_off(crtc); |
| 6383 | assert_vblank_disabled(crtc); |
| 6384 | |
| 6385 | intel_disable_pipe(intel_crtc); |
| 6386 | |
| 6387 | i9xx_pfit_disable(intel_crtc); |
| 6388 | |
| 6389 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 6390 | if (encoder->post_disable) |
| 6391 | encoder->post_disable(encoder); |
| 6392 | |
| 6393 | if (!intel_crtc->config->has_dsi_encoder) { |
| 6394 | if (IS_CHERRYVIEW(dev)) |
| 6395 | chv_disable_pll(dev_priv, pipe); |
| 6396 | else if (IS_VALLEYVIEW(dev)) |
| 6397 | vlv_disable_pll(dev_priv, pipe); |
| 6398 | else |
| 6399 | i9xx_disable_pll(intel_crtc); |
| 6400 | } |
| 6401 | |
| 6402 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 6403 | if (encoder->post_pll_disable) |
| 6404 | encoder->post_pll_disable(encoder); |
| 6405 | |
| 6406 | if (!IS_GEN2(dev)) |
| 6407 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
| 6408 | |
| 6409 | intel_fbc_disable_crtc(intel_crtc); |
| 6410 | } |
| 6411 | |
| 6412 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
| 6413 | { |
| 6414 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 6415 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
| 6416 | enum intel_display_power_domain domain; |
| 6417 | unsigned long domains; |
| 6418 | |
| 6419 | if (!intel_crtc->active) |
| 6420 | return; |
| 6421 | |
| 6422 | if (to_intel_plane_state(crtc->primary->state)->visible) { |
| 6423 | WARN_ON(intel_crtc->unpin_work); |
| 6424 | |
| 6425 | intel_pre_disable_primary(crtc); |
| 6426 | |
| 6427 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); |
| 6428 | to_intel_plane_state(crtc->primary->state)->visible = false; |
| 6429 | } |
| 6430 | |
| 6431 | dev_priv->display.crtc_disable(crtc); |
| 6432 | intel_crtc->active = false; |
| 6433 | intel_update_watermarks(crtc); |
| 6434 | intel_disable_shared_dpll(intel_crtc); |
| 6435 | |
| 6436 | domains = intel_crtc->enabled_power_domains; |
| 6437 | for_each_power_domain(domain, domains) |
| 6438 | intel_display_power_put(dev_priv, domain); |
| 6439 | intel_crtc->enabled_power_domains = 0; |
| 6440 | |
| 6441 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); |
| 6442 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; |
| 6443 | } |
| 6444 | |
| 6445 | /* |
| 6446 | * turn all crtc's off, but do not adjust state |
| 6447 | * This has to be paired with a call to intel_modeset_setup_hw_state. |
| 6448 | */ |
| 6449 | int intel_display_suspend(struct drm_device *dev) |
| 6450 | { |
| 6451 | struct drm_mode_config *config = &dev->mode_config; |
| 6452 | struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx; |
| 6453 | struct drm_atomic_state *state; |
| 6454 | struct drm_crtc *crtc; |
| 6455 | unsigned crtc_mask = 0; |
| 6456 | int ret = 0; |
| 6457 | |
| 6458 | if (WARN_ON(!ctx)) |
| 6459 | return 0; |
| 6460 | |
| 6461 | lockdep_assert_held(&ctx->ww_ctx); |
| 6462 | state = drm_atomic_state_alloc(dev); |
| 6463 | if (WARN_ON(!state)) |
| 6464 | return -ENOMEM; |
| 6465 | |
| 6466 | state->acquire_ctx = ctx; |
| 6467 | state->allow_modeset = true; |
| 6468 | |
| 6469 | for_each_crtc(dev, crtc) { |
| 6470 | struct drm_crtc_state *crtc_state = |
| 6471 | drm_atomic_get_crtc_state(state, crtc); |
| 6472 | |
| 6473 | ret = PTR_ERR_OR_ZERO(crtc_state); |
| 6474 | if (ret) |
| 6475 | goto free; |
| 6476 | |
| 6477 | if (!crtc_state->active) |
| 6478 | continue; |
| 6479 | |
| 6480 | crtc_state->active = false; |
| 6481 | crtc_mask |= 1 << drm_crtc_index(crtc); |
| 6482 | } |
| 6483 | |
| 6484 | if (crtc_mask) { |
| 6485 | ret = drm_atomic_commit(state); |
| 6486 | |
| 6487 | if (!ret) { |
| 6488 | for_each_crtc(dev, crtc) |
| 6489 | if (crtc_mask & (1 << drm_crtc_index(crtc))) |
| 6490 | crtc->state->active = true; |
| 6491 | |
| 6492 | return ret; |
| 6493 | } |
| 6494 | } |
| 6495 | |
| 6496 | free: |
| 6497 | if (ret) |
| 6498 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); |
| 6499 | drm_atomic_state_free(state); |
| 6500 | return ret; |
| 6501 | } |
| 6502 | |
| 6503 | void intel_encoder_destroy(struct drm_encoder *encoder) |
| 6504 | { |
| 6505 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
| 6506 | |
| 6507 | drm_encoder_cleanup(encoder); |
| 6508 | kfree(intel_encoder); |
| 6509 | } |
| 6510 | |
| 6511 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
| 6512 | * internal consistency). */ |
| 6513 | static void intel_connector_check_state(struct intel_connector *connector) |
| 6514 | { |
| 6515 | struct drm_crtc *crtc = connector->base.state->crtc; |
| 6516 | |
| 6517 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
| 6518 | connector->base.base.id, |
| 6519 | connector->base.name); |
| 6520 | |
| 6521 | if (connector->get_hw_state(connector)) { |
| 6522 | struct intel_encoder *encoder = connector->encoder; |
| 6523 | struct drm_connector_state *conn_state = connector->base.state; |
| 6524 | |
| 6525 | I915_STATE_WARN(!crtc, |
| 6526 | "connector enabled without attached crtc\n"); |
| 6527 | |
| 6528 | if (!crtc) |
| 6529 | return; |
| 6530 | |
| 6531 | I915_STATE_WARN(!crtc->state->active, |
| 6532 | "connector is active, but attached crtc isn't\n"); |
| 6533 | |
| 6534 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
| 6535 | return; |
| 6536 | |
| 6537 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
| 6538 | "atomic encoder doesn't match attached encoder\n"); |
| 6539 | |
| 6540 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
| 6541 | "attached encoder crtc differs from connector crtc\n"); |
| 6542 | } else { |
| 6543 | I915_STATE_WARN(crtc && crtc->state->active, |
| 6544 | "attached crtc is active, but connector isn't\n"); |
| 6545 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
| 6546 | "best encoder set without crtc!\n"); |
| 6547 | } |
| 6548 | } |
| 6549 | |
| 6550 | int intel_connector_init(struct intel_connector *connector) |
| 6551 | { |
| 6552 | struct drm_connector_state *connector_state; |
| 6553 | |
| 6554 | connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL); |
| 6555 | if (!connector_state) |
| 6556 | return -ENOMEM; |
| 6557 | |
| 6558 | connector->base.state = connector_state; |
| 6559 | return 0; |
| 6560 | } |
| 6561 | |
| 6562 | struct intel_connector *intel_connector_alloc(void) |
| 6563 | { |
| 6564 | struct intel_connector *connector; |
| 6565 | |
| 6566 | connector = kzalloc(sizeof *connector, GFP_KERNEL); |
| 6567 | if (!connector) |
| 6568 | return NULL; |
| 6569 | |
| 6570 | if (intel_connector_init(connector) < 0) { |
| 6571 | kfree(connector); |
| 6572 | return NULL; |
| 6573 | } |
| 6574 | |
| 6575 | return connector; |
| 6576 | } |
| 6577 | |
| 6578 | /* Simple connector->get_hw_state implementation for encoders that support only |
| 6579 | * one connector and no cloning and hence the encoder state determines the state |
| 6580 | * of the connector. */ |
| 6581 | bool intel_connector_get_hw_state(struct intel_connector *connector) |
| 6582 | { |
| 6583 | enum pipe pipe = 0; |
| 6584 | struct intel_encoder *encoder = connector->encoder; |
| 6585 | |
| 6586 | return encoder->get_hw_state(encoder, &pipe); |
| 6587 | } |
| 6588 | |
| 6589 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
| 6590 | { |
| 6591 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
| 6592 | return crtc_state->fdi_lanes; |
| 6593 | |
| 6594 | return 0; |
| 6595 | } |
| 6596 | |
| 6597 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
| 6598 | struct intel_crtc_state *pipe_config) |
| 6599 | { |
| 6600 | struct drm_atomic_state *state = pipe_config->base.state; |
| 6601 | struct intel_crtc *other_crtc; |
| 6602 | struct intel_crtc_state *other_crtc_state; |
| 6603 | |
| 6604 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
| 6605 | pipe_name(pipe), pipe_config->fdi_lanes); |
| 6606 | if (pipe_config->fdi_lanes > 4) { |
| 6607 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", |
| 6608 | pipe_name(pipe), pipe_config->fdi_lanes); |
| 6609 | return -EINVAL; |
| 6610 | } |
| 6611 | |
| 6612 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
| 6613 | if (pipe_config->fdi_lanes > 2) { |
| 6614 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", |
| 6615 | pipe_config->fdi_lanes); |
| 6616 | return -EINVAL; |
| 6617 | } else { |
| 6618 | return 0; |
| 6619 | } |
| 6620 | } |
| 6621 | |
| 6622 | if (INTEL_INFO(dev)->num_pipes == 2) |
| 6623 | return 0; |
| 6624 | |
| 6625 | /* Ivybridge 3 pipe is really complicated */ |
| 6626 | switch (pipe) { |
| 6627 | case PIPE_A: |
| 6628 | return 0; |
| 6629 | case PIPE_B: |
| 6630 | if (pipe_config->fdi_lanes <= 2) |
| 6631 | return 0; |
| 6632 | |
| 6633 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); |
| 6634 | other_crtc_state = |
| 6635 | intel_atomic_get_crtc_state(state, other_crtc); |
| 6636 | if (IS_ERR(other_crtc_state)) |
| 6637 | return PTR_ERR(other_crtc_state); |
| 6638 | |
| 6639 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { |
| 6640 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
| 6641 | pipe_name(pipe), pipe_config->fdi_lanes); |
| 6642 | return -EINVAL; |
| 6643 | } |
| 6644 | return 0; |
| 6645 | case PIPE_C: |
| 6646 | if (pipe_config->fdi_lanes > 2) { |
| 6647 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", |
| 6648 | pipe_name(pipe), pipe_config->fdi_lanes); |
| 6649 | return -EINVAL; |
| 6650 | } |
| 6651 | |
| 6652 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); |
| 6653 | other_crtc_state = |
| 6654 | intel_atomic_get_crtc_state(state, other_crtc); |
| 6655 | if (IS_ERR(other_crtc_state)) |
| 6656 | return PTR_ERR(other_crtc_state); |
| 6657 | |
| 6658 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { |
| 6659 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
| 6660 | return -EINVAL; |
| 6661 | } |
| 6662 | return 0; |
| 6663 | default: |
| 6664 | BUG(); |
| 6665 | } |
| 6666 | } |
| 6667 | |
| 6668 | #define RETRY 1 |
| 6669 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, |
| 6670 | struct intel_crtc_state *pipe_config) |
| 6671 | { |
| 6672 | struct drm_device *dev = intel_crtc->base.dev; |
| 6673 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
| 6674 | int lane, link_bw, fdi_dotclock, ret; |
| 6675 | bool needs_recompute = false; |
| 6676 | |
| 6677 | retry: |
| 6678 | /* FDI is a binary signal running at ~2.7GHz, encoding |
| 6679 | * each output octet as 10 bits. The actual frequency |
| 6680 | * is stored as a divider into a 100MHz clock, and the |
| 6681 | * mode pixel clock is stored in units of 1KHz. |
| 6682 | * Hence the bw of each lane in terms of the mode signal |
| 6683 | * is: |
| 6684 | */ |
| 6685 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; |
| 6686 | |
| 6687 | fdi_dotclock = adjusted_mode->crtc_clock; |
| 6688 | |
| 6689 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
| 6690 | pipe_config->pipe_bpp); |
| 6691 | |
| 6692 | pipe_config->fdi_lanes = lane; |
| 6693 | |
| 6694 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
| 6695 | link_bw, &pipe_config->fdi_m_n); |
| 6696 | |
| 6697 | ret = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
| 6698 | intel_crtc->pipe, pipe_config); |
| 6699 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { |
| 6700 | pipe_config->pipe_bpp -= 2*3; |
| 6701 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", |
| 6702 | pipe_config->pipe_bpp); |
| 6703 | needs_recompute = true; |
| 6704 | pipe_config->bw_constrained = true; |
| 6705 | |
| 6706 | goto retry; |
| 6707 | } |
| 6708 | |
| 6709 | if (needs_recompute) |
| 6710 | return RETRY; |
| 6711 | |
| 6712 | return ret; |
| 6713 | } |
| 6714 | |
| 6715 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
| 6716 | struct intel_crtc_state *pipe_config) |
| 6717 | { |
| 6718 | if (pipe_config->pipe_bpp > 24) |
| 6719 | return false; |
| 6720 | |
| 6721 | /* HSW can handle pixel rate up to cdclk? */ |
| 6722 | if (IS_HASWELL(dev_priv->dev)) |
| 6723 | return true; |
| 6724 | |
| 6725 | /* |
| 6726 | * We compare against max which means we must take |
| 6727 | * the increased cdclk requirement into account when |
| 6728 | * calculating the new cdclk. |
| 6729 | * |
| 6730 | * Should measure whether using a lower cdclk w/o IPS |
| 6731 | */ |
| 6732 | return ilk_pipe_pixel_rate(pipe_config) <= |
| 6733 | dev_priv->max_cdclk_freq * 95 / 100; |
| 6734 | } |
| 6735 | |
| 6736 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
| 6737 | struct intel_crtc_state *pipe_config) |
| 6738 | { |
| 6739 | struct drm_device *dev = crtc->base.dev; |
| 6740 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6741 | |
| 6742 | pipe_config->ips_enabled = i915.enable_ips && |
| 6743 | hsw_crtc_supports_ips(crtc) && |
| 6744 | pipe_config_supports_ips(dev_priv, pipe_config); |
| 6745 | } |
| 6746 | |
| 6747 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
| 6748 | { |
| 6749 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
| 6750 | |
| 6751 | /* GDG double wide on either pipe, otherwise pipe A only */ |
| 6752 | return INTEL_INFO(dev_priv)->gen < 4 && |
| 6753 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); |
| 6754 | } |
| 6755 | |
| 6756 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
| 6757 | struct intel_crtc_state *pipe_config) |
| 6758 | { |
| 6759 | struct drm_device *dev = crtc->base.dev; |
| 6760 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6761 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
| 6762 | |
| 6763 | /* FIXME should check pixel clock limits on all platforms */ |
| 6764 | if (INTEL_INFO(dev)->gen < 4) { |
| 6765 | int clock_limit = dev_priv->max_cdclk_freq * 9 / 10; |
| 6766 | |
| 6767 | /* |
| 6768 | * Enable double wide mode when the dot clock |
| 6769 | * is > 90% of the (display) core speed. |
| 6770 | */ |
| 6771 | if (intel_crtc_supports_double_wide(crtc) && |
| 6772 | adjusted_mode->crtc_clock > clock_limit) { |
| 6773 | clock_limit *= 2; |
| 6774 | pipe_config->double_wide = true; |
| 6775 | } |
| 6776 | |
| 6777 | if (adjusted_mode->crtc_clock > clock_limit) { |
| 6778 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", |
| 6779 | adjusted_mode->crtc_clock, clock_limit, |
| 6780 | yesno(pipe_config->double_wide)); |
| 6781 | return -EINVAL; |
| 6782 | } |
| 6783 | } |
| 6784 | |
| 6785 | /* |
| 6786 | * Pipe horizontal size must be even in: |
| 6787 | * - DVO ganged mode |
| 6788 | * - LVDS dual channel mode |
| 6789 | * - Double wide pipe |
| 6790 | */ |
| 6791 | if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && |
| 6792 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
| 6793 | pipe_config->pipe_src_w &= ~1; |
| 6794 | |
| 6795 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
| 6796 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. |
| 6797 | */ |
| 6798 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && |
| 6799 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) |
| 6800 | return -EINVAL; |
| 6801 | |
| 6802 | if (HAS_IPS(dev)) |
| 6803 | hsw_compute_ips_config(crtc, pipe_config); |
| 6804 | |
| 6805 | if (pipe_config->has_pch_encoder) |
| 6806 | return ironlake_fdi_compute_config(crtc, pipe_config); |
| 6807 | |
| 6808 | return 0; |
| 6809 | } |
| 6810 | |
| 6811 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
| 6812 | { |
| 6813 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 6814 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); |
| 6815 | uint32_t cdctl = I915_READ(CDCLK_CTL); |
| 6816 | uint32_t linkrate; |
| 6817 | |
| 6818 | if (!(lcpll1 & LCPLL_PLL_ENABLE)) |
| 6819 | return 24000; /* 24MHz is the cd freq with NSSC ref */ |
| 6820 | |
| 6821 | if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) |
| 6822 | return 540000; |
| 6823 | |
| 6824 | linkrate = (I915_READ(DPLL_CTRL1) & |
| 6825 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; |
| 6826 | |
| 6827 | if (linkrate == DPLL_CTRL1_LINK_RATE_2160 || |
| 6828 | linkrate == DPLL_CTRL1_LINK_RATE_1080) { |
| 6829 | /* vco 8640 */ |
| 6830 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
| 6831 | case CDCLK_FREQ_450_432: |
| 6832 | return 432000; |
| 6833 | case CDCLK_FREQ_337_308: |
| 6834 | return 308570; |
| 6835 | case CDCLK_FREQ_675_617: |
| 6836 | return 617140; |
| 6837 | default: |
| 6838 | WARN(1, "Unknown cd freq selection\n"); |
| 6839 | } |
| 6840 | } else { |
| 6841 | /* vco 8100 */ |
| 6842 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
| 6843 | case CDCLK_FREQ_450_432: |
| 6844 | return 450000; |
| 6845 | case CDCLK_FREQ_337_308: |
| 6846 | return 337500; |
| 6847 | case CDCLK_FREQ_675_617: |
| 6848 | return 675000; |
| 6849 | default: |
| 6850 | WARN(1, "Unknown cd freq selection\n"); |
| 6851 | } |
| 6852 | } |
| 6853 | |
| 6854 | /* error case, do as if DPLL0 isn't enabled */ |
| 6855 | return 24000; |
| 6856 | } |
| 6857 | |
| 6858 | static int broxton_get_display_clock_speed(struct drm_device *dev) |
| 6859 | { |
| 6860 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 6861 | uint32_t cdctl = I915_READ(CDCLK_CTL); |
| 6862 | uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; |
| 6863 | uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE); |
| 6864 | int cdclk; |
| 6865 | |
| 6866 | if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE)) |
| 6867 | return 19200; |
| 6868 | |
| 6869 | cdclk = 19200 * pll_ratio / 2; |
| 6870 | |
| 6871 | switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) { |
| 6872 | case BXT_CDCLK_CD2X_DIV_SEL_1: |
| 6873 | return cdclk; /* 576MHz or 624MHz */ |
| 6874 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: |
| 6875 | return cdclk * 2 / 3; /* 384MHz */ |
| 6876 | case BXT_CDCLK_CD2X_DIV_SEL_2: |
| 6877 | return cdclk / 2; /* 288MHz */ |
| 6878 | case BXT_CDCLK_CD2X_DIV_SEL_4: |
| 6879 | return cdclk / 4; /* 144MHz */ |
| 6880 | } |
| 6881 | |
| 6882 | /* error case, do as if DE PLL isn't enabled */ |
| 6883 | return 19200; |
| 6884 | } |
| 6885 | |
| 6886 | static int broadwell_get_display_clock_speed(struct drm_device *dev) |
| 6887 | { |
| 6888 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6889 | uint32_t lcpll = I915_READ(LCPLL_CTL); |
| 6890 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; |
| 6891 | |
| 6892 | if (lcpll & LCPLL_CD_SOURCE_FCLK) |
| 6893 | return 800000; |
| 6894 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) |
| 6895 | return 450000; |
| 6896 | else if (freq == LCPLL_CLK_FREQ_450) |
| 6897 | return 450000; |
| 6898 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) |
| 6899 | return 540000; |
| 6900 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) |
| 6901 | return 337500; |
| 6902 | else |
| 6903 | return 675000; |
| 6904 | } |
| 6905 | |
| 6906 | static int haswell_get_display_clock_speed(struct drm_device *dev) |
| 6907 | { |
| 6908 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6909 | uint32_t lcpll = I915_READ(LCPLL_CTL); |
| 6910 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; |
| 6911 | |
| 6912 | if (lcpll & LCPLL_CD_SOURCE_FCLK) |
| 6913 | return 800000; |
| 6914 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) |
| 6915 | return 450000; |
| 6916 | else if (freq == LCPLL_CLK_FREQ_450) |
| 6917 | return 450000; |
| 6918 | else if (IS_HSW_ULT(dev)) |
| 6919 | return 337500; |
| 6920 | else |
| 6921 | return 540000; |
| 6922 | } |
| 6923 | |
| 6924 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
| 6925 | { |
| 6926 | return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk", |
| 6927 | CCK_DISPLAY_CLOCK_CONTROL); |
| 6928 | } |
| 6929 | |
| 6930 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
| 6931 | { |
| 6932 | return 450000; |
| 6933 | } |
| 6934 | |
| 6935 | static int i945_get_display_clock_speed(struct drm_device *dev) |
| 6936 | { |
| 6937 | return 400000; |
| 6938 | } |
| 6939 | |
| 6940 | static int i915_get_display_clock_speed(struct drm_device *dev) |
| 6941 | { |
| 6942 | return 333333; |
| 6943 | } |
| 6944 | |
| 6945 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
| 6946 | { |
| 6947 | return 200000; |
| 6948 | } |
| 6949 | |
| 6950 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
| 6951 | { |
| 6952 | u16 gcfgc = 0; |
| 6953 | |
| 6954 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
| 6955 | |
| 6956 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { |
| 6957 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: |
| 6958 | return 266667; |
| 6959 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
| 6960 | return 333333; |
| 6961 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
| 6962 | return 444444; |
| 6963 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
| 6964 | return 200000; |
| 6965 | default: |
| 6966 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); |
| 6967 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: |
| 6968 | return 133333; |
| 6969 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
| 6970 | return 166667; |
| 6971 | } |
| 6972 | } |
| 6973 | |
| 6974 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
| 6975 | { |
| 6976 | u16 gcfgc = 0; |
| 6977 | |
| 6978 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
| 6979 | |
| 6980 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) |
| 6981 | return 133333; |
| 6982 | else { |
| 6983 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { |
| 6984 | case GC_DISPLAY_CLOCK_333_MHZ: |
| 6985 | return 333333; |
| 6986 | default: |
| 6987 | case GC_DISPLAY_CLOCK_190_200_MHZ: |
| 6988 | return 190000; |
| 6989 | } |
| 6990 | } |
| 6991 | } |
| 6992 | |
| 6993 | static int i865_get_display_clock_speed(struct drm_device *dev) |
| 6994 | { |
| 6995 | return 266667; |
| 6996 | } |
| 6997 | |
| 6998 | static int i85x_get_display_clock_speed(struct drm_device *dev) |
| 6999 | { |
| 7000 | u16 hpllcc = 0; |
| 7001 | |
| 7002 | /* |
| 7003 | * 852GM/852GMV only supports 133 MHz and the HPLLCC |
| 7004 | * encoding is different :( |
| 7005 | * FIXME is this the right way to detect 852GM/852GMV? |
| 7006 | */ |
| 7007 | if (dev->pdev->revision == 0x1) |
| 7008 | return 133333; |
| 7009 | |
| 7010 | pci_bus_read_config_word(dev->pdev->bus, |
| 7011 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); |
| 7012 | |
| 7013 | /* Assume that the hardware is in the high speed state. This |
| 7014 | * should be the default. |
| 7015 | */ |
| 7016 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { |
| 7017 | case GC_CLOCK_133_200: |
| 7018 | case GC_CLOCK_133_200_2: |
| 7019 | case GC_CLOCK_100_200: |
| 7020 | return 200000; |
| 7021 | case GC_CLOCK_166_250: |
| 7022 | return 250000; |
| 7023 | case GC_CLOCK_100_133: |
| 7024 | return 133333; |
| 7025 | case GC_CLOCK_133_266: |
| 7026 | case GC_CLOCK_133_266_2: |
| 7027 | case GC_CLOCK_166_266: |
| 7028 | return 266667; |
| 7029 | } |
| 7030 | |
| 7031 | /* Shouldn't happen */ |
| 7032 | return 0; |
| 7033 | } |
| 7034 | |
| 7035 | static int i830_get_display_clock_speed(struct drm_device *dev) |
| 7036 | { |
| 7037 | return 133333; |
| 7038 | } |
| 7039 | |
| 7040 | static unsigned int intel_hpll_vco(struct drm_device *dev) |
| 7041 | { |
| 7042 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7043 | static const unsigned int blb_vco[8] = { |
| 7044 | [0] = 3200000, |
| 7045 | [1] = 4000000, |
| 7046 | [2] = 5333333, |
| 7047 | [3] = 4800000, |
| 7048 | [4] = 6400000, |
| 7049 | }; |
| 7050 | static const unsigned int pnv_vco[8] = { |
| 7051 | [0] = 3200000, |
| 7052 | [1] = 4000000, |
| 7053 | [2] = 5333333, |
| 7054 | [3] = 4800000, |
| 7055 | [4] = 2666667, |
| 7056 | }; |
| 7057 | static const unsigned int cl_vco[8] = { |
| 7058 | [0] = 3200000, |
| 7059 | [1] = 4000000, |
| 7060 | [2] = 5333333, |
| 7061 | [3] = 6400000, |
| 7062 | [4] = 3333333, |
| 7063 | [5] = 3566667, |
| 7064 | [6] = 4266667, |
| 7065 | }; |
| 7066 | static const unsigned int elk_vco[8] = { |
| 7067 | [0] = 3200000, |
| 7068 | [1] = 4000000, |
| 7069 | [2] = 5333333, |
| 7070 | [3] = 4800000, |
| 7071 | }; |
| 7072 | static const unsigned int ctg_vco[8] = { |
| 7073 | [0] = 3200000, |
| 7074 | [1] = 4000000, |
| 7075 | [2] = 5333333, |
| 7076 | [3] = 6400000, |
| 7077 | [4] = 2666667, |
| 7078 | [5] = 4266667, |
| 7079 | }; |
| 7080 | const unsigned int *vco_table; |
| 7081 | unsigned int vco; |
| 7082 | uint8_t tmp = 0; |
| 7083 | |
| 7084 | /* FIXME other chipsets? */ |
| 7085 | if (IS_GM45(dev)) |
| 7086 | vco_table = ctg_vco; |
| 7087 | else if (IS_G4X(dev)) |
| 7088 | vco_table = elk_vco; |
| 7089 | else if (IS_CRESTLINE(dev)) |
| 7090 | vco_table = cl_vco; |
| 7091 | else if (IS_PINEVIEW(dev)) |
| 7092 | vco_table = pnv_vco; |
| 7093 | else if (IS_G33(dev)) |
| 7094 | vco_table = blb_vco; |
| 7095 | else |
| 7096 | return 0; |
| 7097 | |
| 7098 | tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); |
| 7099 | |
| 7100 | vco = vco_table[tmp & 0x7]; |
| 7101 | if (vco == 0) |
| 7102 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); |
| 7103 | else |
| 7104 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); |
| 7105 | |
| 7106 | return vco; |
| 7107 | } |
| 7108 | |
| 7109 | static int gm45_get_display_clock_speed(struct drm_device *dev) |
| 7110 | { |
| 7111 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); |
| 7112 | uint16_t tmp = 0; |
| 7113 | |
| 7114 | pci_read_config_word(dev->pdev, GCFGC, &tmp); |
| 7115 | |
| 7116 | cdclk_sel = (tmp >> 12) & 0x1; |
| 7117 | |
| 7118 | switch (vco) { |
| 7119 | case 2666667: |
| 7120 | case 4000000: |
| 7121 | case 5333333: |
| 7122 | return cdclk_sel ? 333333 : 222222; |
| 7123 | case 3200000: |
| 7124 | return cdclk_sel ? 320000 : 228571; |
| 7125 | default: |
| 7126 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); |
| 7127 | return 222222; |
| 7128 | } |
| 7129 | } |
| 7130 | |
| 7131 | static int i965gm_get_display_clock_speed(struct drm_device *dev) |
| 7132 | { |
| 7133 | static const uint8_t div_3200[] = { 16, 10, 8 }; |
| 7134 | static const uint8_t div_4000[] = { 20, 12, 10 }; |
| 7135 | static const uint8_t div_5333[] = { 24, 16, 14 }; |
| 7136 | const uint8_t *div_table; |
| 7137 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); |
| 7138 | uint16_t tmp = 0; |
| 7139 | |
| 7140 | pci_read_config_word(dev->pdev, GCFGC, &tmp); |
| 7141 | |
| 7142 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; |
| 7143 | |
| 7144 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) |
| 7145 | goto fail; |
| 7146 | |
| 7147 | switch (vco) { |
| 7148 | case 3200000: |
| 7149 | div_table = div_3200; |
| 7150 | break; |
| 7151 | case 4000000: |
| 7152 | div_table = div_4000; |
| 7153 | break; |
| 7154 | case 5333333: |
| 7155 | div_table = div_5333; |
| 7156 | break; |
| 7157 | default: |
| 7158 | goto fail; |
| 7159 | } |
| 7160 | |
| 7161 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); |
| 7162 | |
| 7163 | fail: |
| 7164 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); |
| 7165 | return 200000; |
| 7166 | } |
| 7167 | |
| 7168 | static int g33_get_display_clock_speed(struct drm_device *dev) |
| 7169 | { |
| 7170 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; |
| 7171 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; |
| 7172 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; |
| 7173 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; |
| 7174 | const uint8_t *div_table; |
| 7175 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); |
| 7176 | uint16_t tmp = 0; |
| 7177 | |
| 7178 | pci_read_config_word(dev->pdev, GCFGC, &tmp); |
| 7179 | |
| 7180 | cdclk_sel = (tmp >> 4) & 0x7; |
| 7181 | |
| 7182 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) |
| 7183 | goto fail; |
| 7184 | |
| 7185 | switch (vco) { |
| 7186 | case 3200000: |
| 7187 | div_table = div_3200; |
| 7188 | break; |
| 7189 | case 4000000: |
| 7190 | div_table = div_4000; |
| 7191 | break; |
| 7192 | case 4800000: |
| 7193 | div_table = div_4800; |
| 7194 | break; |
| 7195 | case 5333333: |
| 7196 | div_table = div_5333; |
| 7197 | break; |
| 7198 | default: |
| 7199 | goto fail; |
| 7200 | } |
| 7201 | |
| 7202 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); |
| 7203 | |
| 7204 | fail: |
| 7205 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); |
| 7206 | return 190476; |
| 7207 | } |
| 7208 | |
| 7209 | static void |
| 7210 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
| 7211 | { |
| 7212 | while (*num > DATA_LINK_M_N_MASK || |
| 7213 | *den > DATA_LINK_M_N_MASK) { |
| 7214 | *num >>= 1; |
| 7215 | *den >>= 1; |
| 7216 | } |
| 7217 | } |
| 7218 | |
| 7219 | static void compute_m_n(unsigned int m, unsigned int n, |
| 7220 | uint32_t *ret_m, uint32_t *ret_n) |
| 7221 | { |
| 7222 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); |
| 7223 | *ret_m = div_u64((uint64_t) m * *ret_n, n); |
| 7224 | intel_reduce_m_n_ratio(ret_m, ret_n); |
| 7225 | } |
| 7226 | |
| 7227 | void |
| 7228 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, |
| 7229 | int pixel_clock, int link_clock, |
| 7230 | struct intel_link_m_n *m_n) |
| 7231 | { |
| 7232 | m_n->tu = 64; |
| 7233 | |
| 7234 | compute_m_n(bits_per_pixel * pixel_clock, |
| 7235 | link_clock * nlanes * 8, |
| 7236 | &m_n->gmch_m, &m_n->gmch_n); |
| 7237 | |
| 7238 | compute_m_n(pixel_clock, link_clock, |
| 7239 | &m_n->link_m, &m_n->link_n); |
| 7240 | } |
| 7241 | |
| 7242 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
| 7243 | { |
| 7244 | if (i915.panel_use_ssc >= 0) |
| 7245 | return i915.panel_use_ssc != 0; |
| 7246 | return dev_priv->vbt.lvds_use_ssc |
| 7247 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
| 7248 | } |
| 7249 | |
| 7250 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
| 7251 | int num_connectors) |
| 7252 | { |
| 7253 | struct drm_device *dev = crtc_state->base.crtc->dev; |
| 7254 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7255 | int refclk; |
| 7256 | |
| 7257 | WARN_ON(!crtc_state->base.state); |
| 7258 | |
| 7259 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) { |
| 7260 | refclk = 100000; |
| 7261 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
| 7262 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
| 7263 | refclk = dev_priv->vbt.lvds_ssc_freq; |
| 7264 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); |
| 7265 | } else if (!IS_GEN2(dev)) { |
| 7266 | refclk = 96000; |
| 7267 | } else { |
| 7268 | refclk = 48000; |
| 7269 | } |
| 7270 | |
| 7271 | return refclk; |
| 7272 | } |
| 7273 | |
| 7274 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
| 7275 | { |
| 7276 | return (1 << dpll->n) << 16 | dpll->m2; |
| 7277 | } |
| 7278 | |
| 7279 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
| 7280 | { |
| 7281 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; |
| 7282 | } |
| 7283 | |
| 7284 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
| 7285 | struct intel_crtc_state *crtc_state, |
| 7286 | intel_clock_t *reduced_clock) |
| 7287 | { |
| 7288 | struct drm_device *dev = crtc->base.dev; |
| 7289 | u32 fp, fp2 = 0; |
| 7290 | |
| 7291 | if (IS_PINEVIEW(dev)) { |
| 7292 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
| 7293 | if (reduced_clock) |
| 7294 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
| 7295 | } else { |
| 7296 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
| 7297 | if (reduced_clock) |
| 7298 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
| 7299 | } |
| 7300 | |
| 7301 | crtc_state->dpll_hw_state.fp0 = fp; |
| 7302 | |
| 7303 | crtc->lowfreq_avail = false; |
| 7304 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
| 7305 | reduced_clock) { |
| 7306 | crtc_state->dpll_hw_state.fp1 = fp2; |
| 7307 | crtc->lowfreq_avail = true; |
| 7308 | } else { |
| 7309 | crtc_state->dpll_hw_state.fp1 = fp; |
| 7310 | } |
| 7311 | } |
| 7312 | |
| 7313 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
| 7314 | pipe) |
| 7315 | { |
| 7316 | u32 reg_val; |
| 7317 | |
| 7318 | /* |
| 7319 | * PLLB opamp always calibrates to max value of 0x3f, force enable it |
| 7320 | * and set it to a reasonable value instead. |
| 7321 | */ |
| 7322 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
| 7323 | reg_val &= 0xffffff00; |
| 7324 | reg_val |= 0x00000030; |
| 7325 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
| 7326 | |
| 7327 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
| 7328 | reg_val &= 0x8cffffff; |
| 7329 | reg_val = 0x8c000000; |
| 7330 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
| 7331 | |
| 7332 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
| 7333 | reg_val &= 0xffffff00; |
| 7334 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
| 7335 | |
| 7336 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
| 7337 | reg_val &= 0x00ffffff; |
| 7338 | reg_val |= 0xb0000000; |
| 7339 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
| 7340 | } |
| 7341 | |
| 7342 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
| 7343 | struct intel_link_m_n *m_n) |
| 7344 | { |
| 7345 | struct drm_device *dev = crtc->base.dev; |
| 7346 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7347 | int pipe = crtc->pipe; |
| 7348 | |
| 7349 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
| 7350 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); |
| 7351 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); |
| 7352 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); |
| 7353 | } |
| 7354 | |
| 7355 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
| 7356 | struct intel_link_m_n *m_n, |
| 7357 | struct intel_link_m_n *m2_n2) |
| 7358 | { |
| 7359 | struct drm_device *dev = crtc->base.dev; |
| 7360 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7361 | int pipe = crtc->pipe; |
| 7362 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
| 7363 | |
| 7364 | if (INTEL_INFO(dev)->gen >= 5) { |
| 7365 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); |
| 7366 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); |
| 7367 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); |
| 7368 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); |
| 7369 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
| 7370 | * for gen < 8) and if DRRS is supported (to make sure the |
| 7371 | * registers are not unnecessarily accessed). |
| 7372 | */ |
| 7373 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
| 7374 | crtc->config->has_drrs) { |
| 7375 | I915_WRITE(PIPE_DATA_M2(transcoder), |
| 7376 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); |
| 7377 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); |
| 7378 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); |
| 7379 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); |
| 7380 | } |
| 7381 | } else { |
| 7382 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
| 7383 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); |
| 7384 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); |
| 7385 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); |
| 7386 | } |
| 7387 | } |
| 7388 | |
| 7389 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
| 7390 | { |
| 7391 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
| 7392 | |
| 7393 | if (m_n == M1_N1) { |
| 7394 | dp_m_n = &crtc->config->dp_m_n; |
| 7395 | dp_m2_n2 = &crtc->config->dp_m2_n2; |
| 7396 | } else if (m_n == M2_N2) { |
| 7397 | |
| 7398 | /* |
| 7399 | * M2_N2 registers are not supported. Hence m2_n2 divider value |
| 7400 | * needs to be programmed into M1_N1. |
| 7401 | */ |
| 7402 | dp_m_n = &crtc->config->dp_m2_n2; |
| 7403 | } else { |
| 7404 | DRM_ERROR("Unsupported divider value\n"); |
| 7405 | return; |
| 7406 | } |
| 7407 | |
| 7408 | if (crtc->config->has_pch_encoder) |
| 7409 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); |
| 7410 | else |
| 7411 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
| 7412 | } |
| 7413 | |
| 7414 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
| 7415 | struct intel_crtc_state *pipe_config) |
| 7416 | { |
| 7417 | u32 dpll, dpll_md; |
| 7418 | |
| 7419 | /* |
| 7420 | * Enable DPIO clock input. We should never disable the reference |
| 7421 | * clock for pipe B, since VGA hotplug / manual detection depends |
| 7422 | * on it. |
| 7423 | */ |
| 7424 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV | |
| 7425 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV; |
| 7426 | /* We should never disable this, set it here for state tracking */ |
| 7427 | if (crtc->pipe == PIPE_B) |
| 7428 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
| 7429 | dpll |= DPLL_VCO_ENABLE; |
| 7430 | pipe_config->dpll_hw_state.dpll = dpll; |
| 7431 | |
| 7432 | dpll_md = (pipe_config->pixel_multiplier - 1) |
| 7433 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
| 7434 | pipe_config->dpll_hw_state.dpll_md = dpll_md; |
| 7435 | } |
| 7436 | |
| 7437 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
| 7438 | const struct intel_crtc_state *pipe_config) |
| 7439 | { |
| 7440 | struct drm_device *dev = crtc->base.dev; |
| 7441 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7442 | int pipe = crtc->pipe; |
| 7443 | u32 mdiv; |
| 7444 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
| 7445 | u32 coreclk, reg_val; |
| 7446 | |
| 7447 | mutex_lock(&dev_priv->sb_lock); |
| 7448 | |
| 7449 | bestn = pipe_config->dpll.n; |
| 7450 | bestm1 = pipe_config->dpll.m1; |
| 7451 | bestm2 = pipe_config->dpll.m2; |
| 7452 | bestp1 = pipe_config->dpll.p1; |
| 7453 | bestp2 = pipe_config->dpll.p2; |
| 7454 | |
| 7455 | /* See eDP HDMI DPIO driver vbios notes doc */ |
| 7456 | |
| 7457 | /* PLL B needs special handling */ |
| 7458 | if (pipe == PIPE_B) |
| 7459 | vlv_pllb_recal_opamp(dev_priv, pipe); |
| 7460 | |
| 7461 | /* Set up Tx target for periodic Rcomp update */ |
| 7462 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
| 7463 | |
| 7464 | /* Disable target IRef on PLL */ |
| 7465 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
| 7466 | reg_val &= 0x00ffffff; |
| 7467 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
| 7468 | |
| 7469 | /* Disable fast lock */ |
| 7470 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
| 7471 | |
| 7472 | /* Set idtafcrecal before PLL is enabled */ |
| 7473 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
| 7474 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); |
| 7475 | mdiv |= ((bestn << DPIO_N_SHIFT)); |
| 7476 | mdiv |= (1 << DPIO_K_SHIFT); |
| 7477 | |
| 7478 | /* |
| 7479 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, |
| 7480 | * but we don't support that). |
| 7481 | * Note: don't use the DAC post divider as it seems unstable. |
| 7482 | */ |
| 7483 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); |
| 7484 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
| 7485 | |
| 7486 | mdiv |= DPIO_ENABLE_CALIBRATION; |
| 7487 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
| 7488 | |
| 7489 | /* Set HBR and RBR LPF coefficients */ |
| 7490 | if (pipe_config->port_clock == 162000 || |
| 7491 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
| 7492 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) |
| 7493 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
| 7494 | 0x009f0003); |
| 7495 | else |
| 7496 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
| 7497 | 0x00d0000f); |
| 7498 | |
| 7499 | if (pipe_config->has_dp_encoder) { |
| 7500 | /* Use SSC source */ |
| 7501 | if (pipe == PIPE_A) |
| 7502 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
| 7503 | 0x0df40000); |
| 7504 | else |
| 7505 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
| 7506 | 0x0df70000); |
| 7507 | } else { /* HDMI or VGA */ |
| 7508 | /* Use bend source */ |
| 7509 | if (pipe == PIPE_A) |
| 7510 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
| 7511 | 0x0df70000); |
| 7512 | else |
| 7513 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
| 7514 | 0x0df40000); |
| 7515 | } |
| 7516 | |
| 7517 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
| 7518 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
| 7519 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
| 7520 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) |
| 7521 | coreclk |= 0x01000000; |
| 7522 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
| 7523 | |
| 7524 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
| 7525 | mutex_unlock(&dev_priv->sb_lock); |
| 7526 | } |
| 7527 | |
| 7528 | static void chv_compute_dpll(struct intel_crtc *crtc, |
| 7529 | struct intel_crtc_state *pipe_config) |
| 7530 | { |
| 7531 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | |
| 7532 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | |
| 7533 | DPLL_VCO_ENABLE; |
| 7534 | if (crtc->pipe != PIPE_A) |
| 7535 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
| 7536 | |
| 7537 | pipe_config->dpll_hw_state.dpll_md = |
| 7538 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
| 7539 | } |
| 7540 | |
| 7541 | static void chv_prepare_pll(struct intel_crtc *crtc, |
| 7542 | const struct intel_crtc_state *pipe_config) |
| 7543 | { |
| 7544 | struct drm_device *dev = crtc->base.dev; |
| 7545 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7546 | int pipe = crtc->pipe; |
| 7547 | i915_reg_t dpll_reg = DPLL(crtc->pipe); |
| 7548 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
| 7549 | u32 loopfilter, tribuf_calcntr; |
| 7550 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
| 7551 | u32 dpio_val; |
| 7552 | int vco; |
| 7553 | |
| 7554 | bestn = pipe_config->dpll.n; |
| 7555 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; |
| 7556 | bestm1 = pipe_config->dpll.m1; |
| 7557 | bestm2 = pipe_config->dpll.m2 >> 22; |
| 7558 | bestp1 = pipe_config->dpll.p1; |
| 7559 | bestp2 = pipe_config->dpll.p2; |
| 7560 | vco = pipe_config->dpll.vco; |
| 7561 | dpio_val = 0; |
| 7562 | loopfilter = 0; |
| 7563 | |
| 7564 | /* |
| 7565 | * Enable Refclk and SSC |
| 7566 | */ |
| 7567 | I915_WRITE(dpll_reg, |
| 7568 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
| 7569 | |
| 7570 | mutex_lock(&dev_priv->sb_lock); |
| 7571 | |
| 7572 | /* p1 and p2 divider */ |
| 7573 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), |
| 7574 | 5 << DPIO_CHV_S1_DIV_SHIFT | |
| 7575 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | |
| 7576 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | |
| 7577 | 1 << DPIO_CHV_K_DIV_SHIFT); |
| 7578 | |
| 7579 | /* Feedback post-divider - m2 */ |
| 7580 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); |
| 7581 | |
| 7582 | /* Feedback refclk divider - n and m1 */ |
| 7583 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), |
| 7584 | DPIO_CHV_M1_DIV_BY_2 | |
| 7585 | 1 << DPIO_CHV_N_DIV_SHIFT); |
| 7586 | |
| 7587 | /* M2 fraction division */ |
| 7588 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
| 7589 | |
| 7590 | /* M2 fraction division enable */ |
| 7591 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
| 7592 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); |
| 7593 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); |
| 7594 | if (bestm2_frac) |
| 7595 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; |
| 7596 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); |
| 7597 | |
| 7598 | /* Program digital lock detect threshold */ |
| 7599 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); |
| 7600 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | |
| 7601 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); |
| 7602 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); |
| 7603 | if (!bestm2_frac) |
| 7604 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; |
| 7605 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); |
| 7606 | |
| 7607 | /* Loop filter */ |
| 7608 | if (vco == 5400000) { |
| 7609 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); |
| 7610 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); |
| 7611 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); |
| 7612 | tribuf_calcntr = 0x9; |
| 7613 | } else if (vco <= 6200000) { |
| 7614 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); |
| 7615 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); |
| 7616 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); |
| 7617 | tribuf_calcntr = 0x9; |
| 7618 | } else if (vco <= 6480000) { |
| 7619 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); |
| 7620 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); |
| 7621 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); |
| 7622 | tribuf_calcntr = 0x8; |
| 7623 | } else { |
| 7624 | /* Not supported. Apply the same limits as in the max case */ |
| 7625 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); |
| 7626 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); |
| 7627 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); |
| 7628 | tribuf_calcntr = 0; |
| 7629 | } |
| 7630 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
| 7631 | |
| 7632 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
| 7633 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
| 7634 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); |
| 7635 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); |
| 7636 | |
| 7637 | /* AFC Recal */ |
| 7638 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), |
| 7639 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | |
| 7640 | DPIO_AFC_RECAL); |
| 7641 | |
| 7642 | mutex_unlock(&dev_priv->sb_lock); |
| 7643 | } |
| 7644 | |
| 7645 | /** |
| 7646 | * vlv_force_pll_on - forcibly enable just the PLL |
| 7647 | * @dev_priv: i915 private structure |
| 7648 | * @pipe: pipe PLL to enable |
| 7649 | * @dpll: PLL configuration |
| 7650 | * |
| 7651 | * Enable the PLL for @pipe using the supplied @dpll config. To be used |
| 7652 | * in cases where we need the PLL enabled even when @pipe is not going to |
| 7653 | * be enabled. |
| 7654 | */ |
| 7655 | void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, |
| 7656 | const struct dpll *dpll) |
| 7657 | { |
| 7658 | struct intel_crtc *crtc = |
| 7659 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); |
| 7660 | struct intel_crtc_state pipe_config = { |
| 7661 | .base.crtc = &crtc->base, |
| 7662 | .pixel_multiplier = 1, |
| 7663 | .dpll = *dpll, |
| 7664 | }; |
| 7665 | |
| 7666 | if (IS_CHERRYVIEW(dev)) { |
| 7667 | chv_compute_dpll(crtc, &pipe_config); |
| 7668 | chv_prepare_pll(crtc, &pipe_config); |
| 7669 | chv_enable_pll(crtc, &pipe_config); |
| 7670 | } else { |
| 7671 | vlv_compute_dpll(crtc, &pipe_config); |
| 7672 | vlv_prepare_pll(crtc, &pipe_config); |
| 7673 | vlv_enable_pll(crtc, &pipe_config); |
| 7674 | } |
| 7675 | } |
| 7676 | |
| 7677 | /** |
| 7678 | * vlv_force_pll_off - forcibly disable just the PLL |
| 7679 | * @dev_priv: i915 private structure |
| 7680 | * @pipe: pipe PLL to disable |
| 7681 | * |
| 7682 | * Disable the PLL for @pipe. To be used in cases where we need |
| 7683 | * the PLL enabled even when @pipe is not going to be enabled. |
| 7684 | */ |
| 7685 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) |
| 7686 | { |
| 7687 | if (IS_CHERRYVIEW(dev)) |
| 7688 | chv_disable_pll(to_i915(dev), pipe); |
| 7689 | else |
| 7690 | vlv_disable_pll(to_i915(dev), pipe); |
| 7691 | } |
| 7692 | |
| 7693 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
| 7694 | struct intel_crtc_state *crtc_state, |
| 7695 | intel_clock_t *reduced_clock, |
| 7696 | int num_connectors) |
| 7697 | { |
| 7698 | struct drm_device *dev = crtc->base.dev; |
| 7699 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7700 | u32 dpll; |
| 7701 | bool is_sdvo; |
| 7702 | struct dpll *clock = &crtc_state->dpll; |
| 7703 | |
| 7704 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
| 7705 | |
| 7706 | is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || |
| 7707 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); |
| 7708 | |
| 7709 | dpll = DPLL_VGA_MODE_DIS; |
| 7710 | |
| 7711 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
| 7712 | dpll |= DPLLB_MODE_LVDS; |
| 7713 | else |
| 7714 | dpll |= DPLLB_MODE_DAC_SERIAL; |
| 7715 | |
| 7716 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
| 7717 | dpll |= (crtc_state->pixel_multiplier - 1) |
| 7718 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
| 7719 | } |
| 7720 | |
| 7721 | if (is_sdvo) |
| 7722 | dpll |= DPLL_SDVO_HIGH_SPEED; |
| 7723 | |
| 7724 | if (crtc_state->has_dp_encoder) |
| 7725 | dpll |= DPLL_SDVO_HIGH_SPEED; |
| 7726 | |
| 7727 | /* compute bitmask from p1 value */ |
| 7728 | if (IS_PINEVIEW(dev)) |
| 7729 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; |
| 7730 | else { |
| 7731 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
| 7732 | if (IS_G4X(dev) && reduced_clock) |
| 7733 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
| 7734 | } |
| 7735 | switch (clock->p2) { |
| 7736 | case 5: |
| 7737 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
| 7738 | break; |
| 7739 | case 7: |
| 7740 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; |
| 7741 | break; |
| 7742 | case 10: |
| 7743 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; |
| 7744 | break; |
| 7745 | case 14: |
| 7746 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; |
| 7747 | break; |
| 7748 | } |
| 7749 | if (INTEL_INFO(dev)->gen >= 4) |
| 7750 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
| 7751 | |
| 7752 | if (crtc_state->sdvo_tv_clock) |
| 7753 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
| 7754 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
| 7755 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
| 7756 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
| 7757 | else |
| 7758 | dpll |= PLL_REF_INPUT_DREFCLK; |
| 7759 | |
| 7760 | dpll |= DPLL_VCO_ENABLE; |
| 7761 | crtc_state->dpll_hw_state.dpll = dpll; |
| 7762 | |
| 7763 | if (INTEL_INFO(dev)->gen >= 4) { |
| 7764 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
| 7765 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
| 7766 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
| 7767 | } |
| 7768 | } |
| 7769 | |
| 7770 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
| 7771 | struct intel_crtc_state *crtc_state, |
| 7772 | intel_clock_t *reduced_clock, |
| 7773 | int num_connectors) |
| 7774 | { |
| 7775 | struct drm_device *dev = crtc->base.dev; |
| 7776 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7777 | u32 dpll; |
| 7778 | struct dpll *clock = &crtc_state->dpll; |
| 7779 | |
| 7780 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
| 7781 | |
| 7782 | dpll = DPLL_VGA_MODE_DIS; |
| 7783 | |
| 7784 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
| 7785 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
| 7786 | } else { |
| 7787 | if (clock->p1 == 2) |
| 7788 | dpll |= PLL_P1_DIVIDE_BY_TWO; |
| 7789 | else |
| 7790 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
| 7791 | if (clock->p2 == 4) |
| 7792 | dpll |= PLL_P2_DIVIDE_BY_4; |
| 7793 | } |
| 7794 | |
| 7795 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
| 7796 | dpll |= DPLL_DVO_2X_MODE; |
| 7797 | |
| 7798 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
| 7799 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
| 7800 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
| 7801 | else |
| 7802 | dpll |= PLL_REF_INPUT_DREFCLK; |
| 7803 | |
| 7804 | dpll |= DPLL_VCO_ENABLE; |
| 7805 | crtc_state->dpll_hw_state.dpll = dpll; |
| 7806 | } |
| 7807 | |
| 7808 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
| 7809 | { |
| 7810 | struct drm_device *dev = intel_crtc->base.dev; |
| 7811 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7812 | enum pipe pipe = intel_crtc->pipe; |
| 7813 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
| 7814 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
| 7815 | uint32_t crtc_vtotal, crtc_vblank_end; |
| 7816 | int vsyncshift = 0; |
| 7817 | |
| 7818 | /* We need to be careful not to changed the adjusted mode, for otherwise |
| 7819 | * the hw state checker will get angry at the mismatch. */ |
| 7820 | crtc_vtotal = adjusted_mode->crtc_vtotal; |
| 7821 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; |
| 7822 | |
| 7823 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
| 7824 | /* the chip adds 2 halflines automatically */ |
| 7825 | crtc_vtotal -= 1; |
| 7826 | crtc_vblank_end -= 1; |
| 7827 | |
| 7828 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
| 7829 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
| 7830 | else |
| 7831 | vsyncshift = adjusted_mode->crtc_hsync_start - |
| 7832 | adjusted_mode->crtc_htotal / 2; |
| 7833 | if (vsyncshift < 0) |
| 7834 | vsyncshift += adjusted_mode->crtc_htotal; |
| 7835 | } |
| 7836 | |
| 7837 | if (INTEL_INFO(dev)->gen > 3) |
| 7838 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
| 7839 | |
| 7840 | I915_WRITE(HTOTAL(cpu_transcoder), |
| 7841 | (adjusted_mode->crtc_hdisplay - 1) | |
| 7842 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
| 7843 | I915_WRITE(HBLANK(cpu_transcoder), |
| 7844 | (adjusted_mode->crtc_hblank_start - 1) | |
| 7845 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
| 7846 | I915_WRITE(HSYNC(cpu_transcoder), |
| 7847 | (adjusted_mode->crtc_hsync_start - 1) | |
| 7848 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
| 7849 | |
| 7850 | I915_WRITE(VTOTAL(cpu_transcoder), |
| 7851 | (adjusted_mode->crtc_vdisplay - 1) | |
| 7852 | ((crtc_vtotal - 1) << 16)); |
| 7853 | I915_WRITE(VBLANK(cpu_transcoder), |
| 7854 | (adjusted_mode->crtc_vblank_start - 1) | |
| 7855 | ((crtc_vblank_end - 1) << 16)); |
| 7856 | I915_WRITE(VSYNC(cpu_transcoder), |
| 7857 | (adjusted_mode->crtc_vsync_start - 1) | |
| 7858 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
| 7859 | |
| 7860 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
| 7861 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is |
| 7862 | * documented on the DDI_FUNC_CTL register description, EDP Input Select |
| 7863 | * bits. */ |
| 7864 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && |
| 7865 | (pipe == PIPE_B || pipe == PIPE_C)) |
| 7866 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); |
| 7867 | |
| 7868 | /* pipesrc controls the size that is scaled from, which should |
| 7869 | * always be the user's requested size. |
| 7870 | */ |
| 7871 | I915_WRITE(PIPESRC(pipe), |
| 7872 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
| 7873 | (intel_crtc->config->pipe_src_h - 1)); |
| 7874 | } |
| 7875 | |
| 7876 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
| 7877 | struct intel_crtc_state *pipe_config) |
| 7878 | { |
| 7879 | struct drm_device *dev = crtc->base.dev; |
| 7880 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7881 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
| 7882 | uint32_t tmp; |
| 7883 | |
| 7884 | tmp = I915_READ(HTOTAL(cpu_transcoder)); |
| 7885 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
| 7886 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; |
| 7887 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
| 7888 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
| 7889 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; |
| 7890 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
| 7891 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
| 7892 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; |
| 7893 | |
| 7894 | tmp = I915_READ(VTOTAL(cpu_transcoder)); |
| 7895 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
| 7896 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; |
| 7897 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
| 7898 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
| 7899 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; |
| 7900 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
| 7901 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
| 7902 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; |
| 7903 | |
| 7904 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { |
| 7905 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
| 7906 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; |
| 7907 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; |
| 7908 | } |
| 7909 | |
| 7910 | tmp = I915_READ(PIPESRC(crtc->pipe)); |
| 7911 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
| 7912 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; |
| 7913 | |
| 7914 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
| 7915 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; |
| 7916 | } |
| 7917 | |
| 7918 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
| 7919 | struct intel_crtc_state *pipe_config) |
| 7920 | { |
| 7921 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
| 7922 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; |
| 7923 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; |
| 7924 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; |
| 7925 | |
| 7926 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
| 7927 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; |
| 7928 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; |
| 7929 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; |
| 7930 | |
| 7931 | mode->flags = pipe_config->base.adjusted_mode.flags; |
| 7932 | mode->type = DRM_MODE_TYPE_DRIVER; |
| 7933 | |
| 7934 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
| 7935 | mode->flags |= pipe_config->base.adjusted_mode.flags; |
| 7936 | |
| 7937 | mode->hsync = drm_mode_hsync(mode); |
| 7938 | mode->vrefresh = drm_mode_vrefresh(mode); |
| 7939 | drm_mode_set_name(mode); |
| 7940 | } |
| 7941 | |
| 7942 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
| 7943 | { |
| 7944 | struct drm_device *dev = intel_crtc->base.dev; |
| 7945 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7946 | uint32_t pipeconf; |
| 7947 | |
| 7948 | pipeconf = 0; |
| 7949 | |
| 7950 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
| 7951 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) |
| 7952 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; |
| 7953 | |
| 7954 | if (intel_crtc->config->double_wide) |
| 7955 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
| 7956 | |
| 7957 | /* only g4x and later have fancy bpc/dither controls */ |
| 7958 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
| 7959 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
| 7960 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
| 7961 | pipeconf |= PIPECONF_DITHER_EN | |
| 7962 | PIPECONF_DITHER_TYPE_SP; |
| 7963 | |
| 7964 | switch (intel_crtc->config->pipe_bpp) { |
| 7965 | case 18: |
| 7966 | pipeconf |= PIPECONF_6BPC; |
| 7967 | break; |
| 7968 | case 24: |
| 7969 | pipeconf |= PIPECONF_8BPC; |
| 7970 | break; |
| 7971 | case 30: |
| 7972 | pipeconf |= PIPECONF_10BPC; |
| 7973 | break; |
| 7974 | default: |
| 7975 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
| 7976 | BUG(); |
| 7977 | } |
| 7978 | } |
| 7979 | |
| 7980 | if (HAS_PIPE_CXSR(dev)) { |
| 7981 | if (intel_crtc->lowfreq_avail) { |
| 7982 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
| 7983 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
| 7984 | } else { |
| 7985 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
| 7986 | } |
| 7987 | } |
| 7988 | |
| 7989 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
| 7990 | if (INTEL_INFO(dev)->gen < 4 || |
| 7991 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
| 7992 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
| 7993 | else |
| 7994 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; |
| 7995 | } else |
| 7996 | pipeconf |= PIPECONF_PROGRESSIVE; |
| 7997 | |
| 7998 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
| 7999 | intel_crtc->config->limited_color_range) |
| 8000 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
| 8001 | |
| 8002 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
| 8003 | POSTING_READ(PIPECONF(intel_crtc->pipe)); |
| 8004 | } |
| 8005 | |
| 8006 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
| 8007 | struct intel_crtc_state *crtc_state) |
| 8008 | { |
| 8009 | struct drm_device *dev = crtc->base.dev; |
| 8010 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8011 | int refclk, num_connectors = 0; |
| 8012 | intel_clock_t clock; |
| 8013 | bool ok; |
| 8014 | const intel_limit_t *limit; |
| 8015 | struct drm_atomic_state *state = crtc_state->base.state; |
| 8016 | struct drm_connector *connector; |
| 8017 | struct drm_connector_state *connector_state; |
| 8018 | int i; |
| 8019 | |
| 8020 | memset(&crtc_state->dpll_hw_state, 0, |
| 8021 | sizeof(crtc_state->dpll_hw_state)); |
| 8022 | |
| 8023 | if (crtc_state->has_dsi_encoder) |
| 8024 | return 0; |
| 8025 | |
| 8026 | for_each_connector_in_state(state, connector, connector_state, i) { |
| 8027 | if (connector_state->crtc == &crtc->base) |
| 8028 | num_connectors++; |
| 8029 | } |
| 8030 | |
| 8031 | if (!crtc_state->clock_set) { |
| 8032 | refclk = i9xx_get_refclk(crtc_state, num_connectors); |
| 8033 | |
| 8034 | /* |
| 8035 | * Returns a set of divisors for the desired target clock with |
| 8036 | * the given refclk, or FALSE. The returned values represent |
| 8037 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + |
| 8038 | * 2) / p1 / p2. |
| 8039 | */ |
| 8040 | limit = intel_limit(crtc_state, refclk); |
| 8041 | ok = dev_priv->display.find_dpll(limit, crtc_state, |
| 8042 | crtc_state->port_clock, |
| 8043 | refclk, NULL, &clock); |
| 8044 | if (!ok) { |
| 8045 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
| 8046 | return -EINVAL; |
| 8047 | } |
| 8048 | |
| 8049 | /* Compat-code for transition, will disappear. */ |
| 8050 | crtc_state->dpll.n = clock.n; |
| 8051 | crtc_state->dpll.m1 = clock.m1; |
| 8052 | crtc_state->dpll.m2 = clock.m2; |
| 8053 | crtc_state->dpll.p1 = clock.p1; |
| 8054 | crtc_state->dpll.p2 = clock.p2; |
| 8055 | } |
| 8056 | |
| 8057 | if (IS_GEN2(dev)) { |
| 8058 | i8xx_compute_dpll(crtc, crtc_state, NULL, |
| 8059 | num_connectors); |
| 8060 | } else if (IS_CHERRYVIEW(dev)) { |
| 8061 | chv_compute_dpll(crtc, crtc_state); |
| 8062 | } else if (IS_VALLEYVIEW(dev)) { |
| 8063 | vlv_compute_dpll(crtc, crtc_state); |
| 8064 | } else { |
| 8065 | i9xx_compute_dpll(crtc, crtc_state, NULL, |
| 8066 | num_connectors); |
| 8067 | } |
| 8068 | |
| 8069 | return 0; |
| 8070 | } |
| 8071 | |
| 8072 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
| 8073 | struct intel_crtc_state *pipe_config) |
| 8074 | { |
| 8075 | struct drm_device *dev = crtc->base.dev; |
| 8076 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8077 | uint32_t tmp; |
| 8078 | |
| 8079 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
| 8080 | return; |
| 8081 | |
| 8082 | tmp = I915_READ(PFIT_CONTROL); |
| 8083 | if (!(tmp & PFIT_ENABLE)) |
| 8084 | return; |
| 8085 | |
| 8086 | /* Check whether the pfit is attached to our pipe. */ |
| 8087 | if (INTEL_INFO(dev)->gen < 4) { |
| 8088 | if (crtc->pipe != PIPE_B) |
| 8089 | return; |
| 8090 | } else { |
| 8091 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) |
| 8092 | return; |
| 8093 | } |
| 8094 | |
| 8095 | pipe_config->gmch_pfit.control = tmp; |
| 8096 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
| 8097 | if (INTEL_INFO(dev)->gen < 5) |
| 8098 | pipe_config->gmch_pfit.lvds_border_bits = |
| 8099 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; |
| 8100 | } |
| 8101 | |
| 8102 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
| 8103 | struct intel_crtc_state *pipe_config) |
| 8104 | { |
| 8105 | struct drm_device *dev = crtc->base.dev; |
| 8106 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8107 | int pipe = pipe_config->cpu_transcoder; |
| 8108 | intel_clock_t clock; |
| 8109 | u32 mdiv; |
| 8110 | int refclk = 100000; |
| 8111 | |
| 8112 | /* In case of MIPI DPLL will not even be used */ |
| 8113 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) |
| 8114 | return; |
| 8115 | |
| 8116 | mutex_lock(&dev_priv->sb_lock); |
| 8117 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
| 8118 | mutex_unlock(&dev_priv->sb_lock); |
| 8119 | |
| 8120 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; |
| 8121 | clock.m2 = mdiv & DPIO_M2DIV_MASK; |
| 8122 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; |
| 8123 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; |
| 8124 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; |
| 8125 | |
| 8126 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
| 8127 | } |
| 8128 | |
| 8129 | static void |
| 8130 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, |
| 8131 | struct intel_initial_plane_config *plane_config) |
| 8132 | { |
| 8133 | struct drm_device *dev = crtc->base.dev; |
| 8134 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8135 | u32 val, base, offset; |
| 8136 | int pipe = crtc->pipe, plane = crtc->plane; |
| 8137 | int fourcc, pixel_format; |
| 8138 | unsigned int aligned_height; |
| 8139 | struct drm_framebuffer *fb; |
| 8140 | struct intel_framebuffer *intel_fb; |
| 8141 | |
| 8142 | val = I915_READ(DSPCNTR(plane)); |
| 8143 | if (!(val & DISPLAY_PLANE_ENABLE)) |
| 8144 | return; |
| 8145 | |
| 8146 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
| 8147 | if (!intel_fb) { |
| 8148 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
| 8149 | return; |
| 8150 | } |
| 8151 | |
| 8152 | fb = &intel_fb->base; |
| 8153 | |
| 8154 | if (INTEL_INFO(dev)->gen >= 4) { |
| 8155 | if (val & DISPPLANE_TILED) { |
| 8156 | plane_config->tiling = I915_TILING_X; |
| 8157 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
| 8158 | } |
| 8159 | } |
| 8160 | |
| 8161 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; |
| 8162 | fourcc = i9xx_format_to_fourcc(pixel_format); |
| 8163 | fb->pixel_format = fourcc; |
| 8164 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; |
| 8165 | |
| 8166 | if (INTEL_INFO(dev)->gen >= 4) { |
| 8167 | if (plane_config->tiling) |
| 8168 | offset = I915_READ(DSPTILEOFF(plane)); |
| 8169 | else |
| 8170 | offset = I915_READ(DSPLINOFF(plane)); |
| 8171 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; |
| 8172 | } else { |
| 8173 | base = I915_READ(DSPADDR(plane)); |
| 8174 | } |
| 8175 | plane_config->base = base; |
| 8176 | |
| 8177 | val = I915_READ(PIPESRC(pipe)); |
| 8178 | fb->width = ((val >> 16) & 0xfff) + 1; |
| 8179 | fb->height = ((val >> 0) & 0xfff) + 1; |
| 8180 | |
| 8181 | val = I915_READ(DSPSTRIDE(pipe)); |
| 8182 | fb->pitches[0] = val & 0xffffffc0; |
| 8183 | |
| 8184 | aligned_height = intel_fb_align_height(dev, fb->height, |
| 8185 | fb->pixel_format, |
| 8186 | fb->modifier[0]); |
| 8187 | |
| 8188 | plane_config->size = fb->pitches[0] * aligned_height; |
| 8189 | |
| 8190 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
| 8191 | pipe_name(pipe), plane, fb->width, fb->height, |
| 8192 | fb->bits_per_pixel, base, fb->pitches[0], |
| 8193 | plane_config->size); |
| 8194 | |
| 8195 | plane_config->fb = intel_fb; |
| 8196 | } |
| 8197 | |
| 8198 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
| 8199 | struct intel_crtc_state *pipe_config) |
| 8200 | { |
| 8201 | struct drm_device *dev = crtc->base.dev; |
| 8202 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8203 | int pipe = pipe_config->cpu_transcoder; |
| 8204 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
| 8205 | intel_clock_t clock; |
| 8206 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
| 8207 | int refclk = 100000; |
| 8208 | |
| 8209 | mutex_lock(&dev_priv->sb_lock); |
| 8210 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
| 8211 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); |
| 8212 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); |
| 8213 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); |
| 8214 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
| 8215 | mutex_unlock(&dev_priv->sb_lock); |
| 8216 | |
| 8217 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; |
| 8218 | clock.m2 = (pll_dw0 & 0xff) << 22; |
| 8219 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) |
| 8220 | clock.m2 |= pll_dw2 & 0x3fffff; |
| 8221 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
| 8222 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; |
| 8223 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; |
| 8224 | |
| 8225 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
| 8226 | } |
| 8227 | |
| 8228 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
| 8229 | struct intel_crtc_state *pipe_config) |
| 8230 | { |
| 8231 | struct drm_device *dev = crtc->base.dev; |
| 8232 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8233 | uint32_t tmp; |
| 8234 | |
| 8235 | if (!intel_display_power_is_enabled(dev_priv, |
| 8236 | POWER_DOMAIN_PIPE(crtc->pipe))) |
| 8237 | return false; |
| 8238 | |
| 8239 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
| 8240 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
| 8241 | |
| 8242 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
| 8243 | if (!(tmp & PIPECONF_ENABLE)) |
| 8244 | return false; |
| 8245 | |
| 8246 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
| 8247 | switch (tmp & PIPECONF_BPC_MASK) { |
| 8248 | case PIPECONF_6BPC: |
| 8249 | pipe_config->pipe_bpp = 18; |
| 8250 | break; |
| 8251 | case PIPECONF_8BPC: |
| 8252 | pipe_config->pipe_bpp = 24; |
| 8253 | break; |
| 8254 | case PIPECONF_10BPC: |
| 8255 | pipe_config->pipe_bpp = 30; |
| 8256 | break; |
| 8257 | default: |
| 8258 | break; |
| 8259 | } |
| 8260 | } |
| 8261 | |
| 8262 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
| 8263 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
| 8264 | pipe_config->limited_color_range = true; |
| 8265 | |
| 8266 | if (INTEL_INFO(dev)->gen < 4) |
| 8267 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; |
| 8268 | |
| 8269 | intel_get_pipe_timings(crtc, pipe_config); |
| 8270 | |
| 8271 | i9xx_get_pfit_config(crtc, pipe_config); |
| 8272 | |
| 8273 | if (INTEL_INFO(dev)->gen >= 4) { |
| 8274 | tmp = I915_READ(DPLL_MD(crtc->pipe)); |
| 8275 | pipe_config->pixel_multiplier = |
| 8276 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) |
| 8277 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; |
| 8278 | pipe_config->dpll_hw_state.dpll_md = tmp; |
| 8279 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
| 8280 | tmp = I915_READ(DPLL(crtc->pipe)); |
| 8281 | pipe_config->pixel_multiplier = |
| 8282 | ((tmp & SDVO_MULTIPLIER_MASK) |
| 8283 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; |
| 8284 | } else { |
| 8285 | /* Note that on i915G/GM the pixel multiplier is in the sdvo |
| 8286 | * port and will be fixed up in the encoder->get_config |
| 8287 | * function. */ |
| 8288 | pipe_config->pixel_multiplier = 1; |
| 8289 | } |
| 8290 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
| 8291 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
| 8292 | /* |
| 8293 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs |
| 8294 | * on 830. Filter it out here so that we don't |
| 8295 | * report errors due to that. |
| 8296 | */ |
| 8297 | if (IS_I830(dev)) |
| 8298 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; |
| 8299 | |
| 8300 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
| 8301 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); |
| 8302 | } else { |
| 8303 | /* Mask out read-only status bits. */ |
| 8304 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | |
| 8305 | DPLL_PORTC_READY_MASK | |
| 8306 | DPLL_PORTB_READY_MASK); |
| 8307 | } |
| 8308 | |
| 8309 | if (IS_CHERRYVIEW(dev)) |
| 8310 | chv_crtc_clock_get(crtc, pipe_config); |
| 8311 | else if (IS_VALLEYVIEW(dev)) |
| 8312 | vlv_crtc_clock_get(crtc, pipe_config); |
| 8313 | else |
| 8314 | i9xx_crtc_clock_get(crtc, pipe_config); |
| 8315 | |
| 8316 | /* |
| 8317 | * Normally the dotclock is filled in by the encoder .get_config() |
| 8318 | * but in case the pipe is enabled w/o any ports we need a sane |
| 8319 | * default. |
| 8320 | */ |
| 8321 | pipe_config->base.adjusted_mode.crtc_clock = |
| 8322 | pipe_config->port_clock / pipe_config->pixel_multiplier; |
| 8323 | |
| 8324 | return true; |
| 8325 | } |
| 8326 | |
| 8327 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
| 8328 | { |
| 8329 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8330 | struct intel_encoder *encoder; |
| 8331 | u32 val, final; |
| 8332 | bool has_lvds = false; |
| 8333 | bool has_cpu_edp = false; |
| 8334 | bool has_panel = false; |
| 8335 | bool has_ck505 = false; |
| 8336 | bool can_ssc = false; |
| 8337 | |
| 8338 | /* We need to take the global config into account */ |
| 8339 | for_each_intel_encoder(dev, encoder) { |
| 8340 | switch (encoder->type) { |
| 8341 | case INTEL_OUTPUT_LVDS: |
| 8342 | has_panel = true; |
| 8343 | has_lvds = true; |
| 8344 | break; |
| 8345 | case INTEL_OUTPUT_EDP: |
| 8346 | has_panel = true; |
| 8347 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
| 8348 | has_cpu_edp = true; |
| 8349 | break; |
| 8350 | default: |
| 8351 | break; |
| 8352 | } |
| 8353 | } |
| 8354 | |
| 8355 | if (HAS_PCH_IBX(dev)) { |
| 8356 | has_ck505 = dev_priv->vbt.display_clock_mode; |
| 8357 | can_ssc = has_ck505; |
| 8358 | } else { |
| 8359 | has_ck505 = false; |
| 8360 | can_ssc = true; |
| 8361 | } |
| 8362 | |
| 8363 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
| 8364 | has_panel, has_lvds, has_ck505); |
| 8365 | |
| 8366 | /* Ironlake: try to setup display ref clock before DPLL |
| 8367 | * enabling. This is only under driver's control after |
| 8368 | * PCH B stepping, previous chipset stepping should be |
| 8369 | * ignoring this setting. |
| 8370 | */ |
| 8371 | val = I915_READ(PCH_DREF_CONTROL); |
| 8372 | |
| 8373 | /* As we must carefully and slowly disable/enable each source in turn, |
| 8374 | * compute the final state we want first and check if we need to |
| 8375 | * make any changes at all. |
| 8376 | */ |
| 8377 | final = val; |
| 8378 | final &= ~DREF_NONSPREAD_SOURCE_MASK; |
| 8379 | if (has_ck505) |
| 8380 | final |= DREF_NONSPREAD_CK505_ENABLE; |
| 8381 | else |
| 8382 | final |= DREF_NONSPREAD_SOURCE_ENABLE; |
| 8383 | |
| 8384 | final &= ~DREF_SSC_SOURCE_MASK; |
| 8385 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
| 8386 | final &= ~DREF_SSC1_ENABLE; |
| 8387 | |
| 8388 | if (has_panel) { |
| 8389 | final |= DREF_SSC_SOURCE_ENABLE; |
| 8390 | |
| 8391 | if (intel_panel_use_ssc(dev_priv) && can_ssc) |
| 8392 | final |= DREF_SSC1_ENABLE; |
| 8393 | |
| 8394 | if (has_cpu_edp) { |
| 8395 | if (intel_panel_use_ssc(dev_priv) && can_ssc) |
| 8396 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
| 8397 | else |
| 8398 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
| 8399 | } else |
| 8400 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
| 8401 | } else { |
| 8402 | final |= DREF_SSC_SOURCE_DISABLE; |
| 8403 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
| 8404 | } |
| 8405 | |
| 8406 | if (final == val) |
| 8407 | return; |
| 8408 | |
| 8409 | /* Always enable nonspread source */ |
| 8410 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
| 8411 | |
| 8412 | if (has_ck505) |
| 8413 | val |= DREF_NONSPREAD_CK505_ENABLE; |
| 8414 | else |
| 8415 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
| 8416 | |
| 8417 | if (has_panel) { |
| 8418 | val &= ~DREF_SSC_SOURCE_MASK; |
| 8419 | val |= DREF_SSC_SOURCE_ENABLE; |
| 8420 | |
| 8421 | /* SSC must be turned on before enabling the CPU output */ |
| 8422 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
| 8423 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
| 8424 | val |= DREF_SSC1_ENABLE; |
| 8425 | } else |
| 8426 | val &= ~DREF_SSC1_ENABLE; |
| 8427 | |
| 8428 | /* Get SSC going before enabling the outputs */ |
| 8429 | I915_WRITE(PCH_DREF_CONTROL, val); |
| 8430 | POSTING_READ(PCH_DREF_CONTROL); |
| 8431 | udelay(200); |
| 8432 | |
| 8433 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
| 8434 | |
| 8435 | /* Enable CPU source on CPU attached eDP */ |
| 8436 | if (has_cpu_edp) { |
| 8437 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
| 8438 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
| 8439 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
| 8440 | } else |
| 8441 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
| 8442 | } else |
| 8443 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
| 8444 | |
| 8445 | I915_WRITE(PCH_DREF_CONTROL, val); |
| 8446 | POSTING_READ(PCH_DREF_CONTROL); |
| 8447 | udelay(200); |
| 8448 | } else { |
| 8449 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); |
| 8450 | |
| 8451 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
| 8452 | |
| 8453 | /* Turn off CPU output */ |
| 8454 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
| 8455 | |
| 8456 | I915_WRITE(PCH_DREF_CONTROL, val); |
| 8457 | POSTING_READ(PCH_DREF_CONTROL); |
| 8458 | udelay(200); |
| 8459 | |
| 8460 | /* Turn off the SSC source */ |
| 8461 | val &= ~DREF_SSC_SOURCE_MASK; |
| 8462 | val |= DREF_SSC_SOURCE_DISABLE; |
| 8463 | |
| 8464 | /* Turn off SSC1 */ |
| 8465 | val &= ~DREF_SSC1_ENABLE; |
| 8466 | |
| 8467 | I915_WRITE(PCH_DREF_CONTROL, val); |
| 8468 | POSTING_READ(PCH_DREF_CONTROL); |
| 8469 | udelay(200); |
| 8470 | } |
| 8471 | |
| 8472 | BUG_ON(val != final); |
| 8473 | } |
| 8474 | |
| 8475 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
| 8476 | { |
| 8477 | uint32_t tmp; |
| 8478 | |
| 8479 | tmp = I915_READ(SOUTH_CHICKEN2); |
| 8480 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; |
| 8481 | I915_WRITE(SOUTH_CHICKEN2, tmp); |
| 8482 | |
| 8483 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
| 8484 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) |
| 8485 | DRM_ERROR("FDI mPHY reset assert timeout\n"); |
| 8486 | |
| 8487 | tmp = I915_READ(SOUTH_CHICKEN2); |
| 8488 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; |
| 8489 | I915_WRITE(SOUTH_CHICKEN2, tmp); |
| 8490 | |
| 8491 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
| 8492 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) |
| 8493 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); |
| 8494 | } |
| 8495 | |
| 8496 | /* WaMPhyProgramming:hsw */ |
| 8497 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) |
| 8498 | { |
| 8499 | uint32_t tmp; |
| 8500 | |
| 8501 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); |
| 8502 | tmp &= ~(0xFF << 24); |
| 8503 | tmp |= (0x12 << 24); |
| 8504 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); |
| 8505 | |
| 8506 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
| 8507 | tmp |= (1 << 11); |
| 8508 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); |
| 8509 | |
| 8510 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); |
| 8511 | tmp |= (1 << 11); |
| 8512 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); |
| 8513 | |
| 8514 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
| 8515 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); |
| 8516 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); |
| 8517 | |
| 8518 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); |
| 8519 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); |
| 8520 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); |
| 8521 | |
| 8522 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
| 8523 | tmp &= ~(7 << 13); |
| 8524 | tmp |= (5 << 13); |
| 8525 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); |
| 8526 | |
| 8527 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
| 8528 | tmp &= ~(7 << 13); |
| 8529 | tmp |= (5 << 13); |
| 8530 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); |
| 8531 | |
| 8532 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); |
| 8533 | tmp &= ~0xFF; |
| 8534 | tmp |= 0x1C; |
| 8535 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); |
| 8536 | |
| 8537 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); |
| 8538 | tmp &= ~0xFF; |
| 8539 | tmp |= 0x1C; |
| 8540 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); |
| 8541 | |
| 8542 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); |
| 8543 | tmp &= ~(0xFF << 16); |
| 8544 | tmp |= (0x1C << 16); |
| 8545 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); |
| 8546 | |
| 8547 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); |
| 8548 | tmp &= ~(0xFF << 16); |
| 8549 | tmp |= (0x1C << 16); |
| 8550 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); |
| 8551 | |
| 8552 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
| 8553 | tmp |= (1 << 27); |
| 8554 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); |
| 8555 | |
| 8556 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
| 8557 | tmp |= (1 << 27); |
| 8558 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); |
| 8559 | |
| 8560 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
| 8561 | tmp &= ~(0xF << 28); |
| 8562 | tmp |= (4 << 28); |
| 8563 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); |
| 8564 | |
| 8565 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
| 8566 | tmp &= ~(0xF << 28); |
| 8567 | tmp |= (4 << 28); |
| 8568 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); |
| 8569 | } |
| 8570 | |
| 8571 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
| 8572 | * Programming" based on the parameters passed: |
| 8573 | * - Sequence to enable CLKOUT_DP |
| 8574 | * - Sequence to enable CLKOUT_DP without spread |
| 8575 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O |
| 8576 | */ |
| 8577 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, |
| 8578 | bool with_fdi) |
| 8579 | { |
| 8580 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8581 | uint32_t reg, tmp; |
| 8582 | |
| 8583 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) |
| 8584 | with_spread = true; |
| 8585 | if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n")) |
| 8586 | with_fdi = false; |
| 8587 | |
| 8588 | mutex_lock(&dev_priv->sb_lock); |
| 8589 | |
| 8590 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); |
| 8591 | tmp &= ~SBI_SSCCTL_DISABLE; |
| 8592 | tmp |= SBI_SSCCTL_PATHALT; |
| 8593 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
| 8594 | |
| 8595 | udelay(24); |
| 8596 | |
| 8597 | if (with_spread) { |
| 8598 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); |
| 8599 | tmp &= ~SBI_SSCCTL_PATHALT; |
| 8600 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
| 8601 | |
| 8602 | if (with_fdi) { |
| 8603 | lpt_reset_fdi_mphy(dev_priv); |
| 8604 | lpt_program_fdi_mphy(dev_priv); |
| 8605 | } |
| 8606 | } |
| 8607 | |
| 8608 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
| 8609 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
| 8610 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; |
| 8611 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); |
| 8612 | |
| 8613 | mutex_unlock(&dev_priv->sb_lock); |
| 8614 | } |
| 8615 | |
| 8616 | /* Sequence to disable CLKOUT_DP */ |
| 8617 | static void lpt_disable_clkout_dp(struct drm_device *dev) |
| 8618 | { |
| 8619 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8620 | uint32_t reg, tmp; |
| 8621 | |
| 8622 | mutex_lock(&dev_priv->sb_lock); |
| 8623 | |
| 8624 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
| 8625 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
| 8626 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; |
| 8627 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); |
| 8628 | |
| 8629 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); |
| 8630 | if (!(tmp & SBI_SSCCTL_DISABLE)) { |
| 8631 | if (!(tmp & SBI_SSCCTL_PATHALT)) { |
| 8632 | tmp |= SBI_SSCCTL_PATHALT; |
| 8633 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
| 8634 | udelay(32); |
| 8635 | } |
| 8636 | tmp |= SBI_SSCCTL_DISABLE; |
| 8637 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
| 8638 | } |
| 8639 | |
| 8640 | mutex_unlock(&dev_priv->sb_lock); |
| 8641 | } |
| 8642 | |
| 8643 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
| 8644 | |
| 8645 | static const uint16_t sscdivintphase[] = { |
| 8646 | [BEND_IDX( 50)] = 0x3B23, |
| 8647 | [BEND_IDX( 45)] = 0x3B23, |
| 8648 | [BEND_IDX( 40)] = 0x3C23, |
| 8649 | [BEND_IDX( 35)] = 0x3C23, |
| 8650 | [BEND_IDX( 30)] = 0x3D23, |
| 8651 | [BEND_IDX( 25)] = 0x3D23, |
| 8652 | [BEND_IDX( 20)] = 0x3E23, |
| 8653 | [BEND_IDX( 15)] = 0x3E23, |
| 8654 | [BEND_IDX( 10)] = 0x3F23, |
| 8655 | [BEND_IDX( 5)] = 0x3F23, |
| 8656 | [BEND_IDX( 0)] = 0x0025, |
| 8657 | [BEND_IDX( -5)] = 0x0025, |
| 8658 | [BEND_IDX(-10)] = 0x0125, |
| 8659 | [BEND_IDX(-15)] = 0x0125, |
| 8660 | [BEND_IDX(-20)] = 0x0225, |
| 8661 | [BEND_IDX(-25)] = 0x0225, |
| 8662 | [BEND_IDX(-30)] = 0x0325, |
| 8663 | [BEND_IDX(-35)] = 0x0325, |
| 8664 | [BEND_IDX(-40)] = 0x0425, |
| 8665 | [BEND_IDX(-45)] = 0x0425, |
| 8666 | [BEND_IDX(-50)] = 0x0525, |
| 8667 | }; |
| 8668 | |
| 8669 | /* |
| 8670 | * Bend CLKOUT_DP |
| 8671 | * steps -50 to 50 inclusive, in steps of 5 |
| 8672 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) |
| 8673 | * change in clock period = -(steps / 10) * 5.787 ps |
| 8674 | */ |
| 8675 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) |
| 8676 | { |
| 8677 | uint32_t tmp; |
| 8678 | int idx = BEND_IDX(steps); |
| 8679 | |
| 8680 | if (WARN_ON(steps % 5 != 0)) |
| 8681 | return; |
| 8682 | |
| 8683 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) |
| 8684 | return; |
| 8685 | |
| 8686 | mutex_lock(&dev_priv->sb_lock); |
| 8687 | |
| 8688 | if (steps % 10 != 0) |
| 8689 | tmp = 0xAAAAAAAB; |
| 8690 | else |
| 8691 | tmp = 0x00000000; |
| 8692 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); |
| 8693 | |
| 8694 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); |
| 8695 | tmp &= 0xffff0000; |
| 8696 | tmp |= sscdivintphase[idx]; |
| 8697 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); |
| 8698 | |
| 8699 | mutex_unlock(&dev_priv->sb_lock); |
| 8700 | } |
| 8701 | |
| 8702 | #undef BEND_IDX |
| 8703 | |
| 8704 | static void lpt_init_pch_refclk(struct drm_device *dev) |
| 8705 | { |
| 8706 | struct intel_encoder *encoder; |
| 8707 | bool has_vga = false; |
| 8708 | |
| 8709 | for_each_intel_encoder(dev, encoder) { |
| 8710 | switch (encoder->type) { |
| 8711 | case INTEL_OUTPUT_ANALOG: |
| 8712 | has_vga = true; |
| 8713 | break; |
| 8714 | default: |
| 8715 | break; |
| 8716 | } |
| 8717 | } |
| 8718 | |
| 8719 | if (has_vga) { |
| 8720 | lpt_bend_clkout_dp(to_i915(dev), 0); |
| 8721 | lpt_enable_clkout_dp(dev, true, true); |
| 8722 | } else { |
| 8723 | lpt_disable_clkout_dp(dev); |
| 8724 | } |
| 8725 | } |
| 8726 | |
| 8727 | /* |
| 8728 | * Initialize reference clocks when the driver loads |
| 8729 | */ |
| 8730 | void intel_init_pch_refclk(struct drm_device *dev) |
| 8731 | { |
| 8732 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
| 8733 | ironlake_init_pch_refclk(dev); |
| 8734 | else if (HAS_PCH_LPT(dev)) |
| 8735 | lpt_init_pch_refclk(dev); |
| 8736 | } |
| 8737 | |
| 8738 | static int ironlake_get_refclk(struct intel_crtc_state *crtc_state) |
| 8739 | { |
| 8740 | struct drm_device *dev = crtc_state->base.crtc->dev; |
| 8741 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8742 | struct drm_atomic_state *state = crtc_state->base.state; |
| 8743 | struct drm_connector *connector; |
| 8744 | struct drm_connector_state *connector_state; |
| 8745 | struct intel_encoder *encoder; |
| 8746 | int num_connectors = 0, i; |
| 8747 | bool is_lvds = false; |
| 8748 | |
| 8749 | for_each_connector_in_state(state, connector, connector_state, i) { |
| 8750 | if (connector_state->crtc != crtc_state->base.crtc) |
| 8751 | continue; |
| 8752 | |
| 8753 | encoder = to_intel_encoder(connector_state->best_encoder); |
| 8754 | |
| 8755 | switch (encoder->type) { |
| 8756 | case INTEL_OUTPUT_LVDS: |
| 8757 | is_lvds = true; |
| 8758 | break; |
| 8759 | default: |
| 8760 | break; |
| 8761 | } |
| 8762 | num_connectors++; |
| 8763 | } |
| 8764 | |
| 8765 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
| 8766 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
| 8767 | dev_priv->vbt.lvds_ssc_freq); |
| 8768 | return dev_priv->vbt.lvds_ssc_freq; |
| 8769 | } |
| 8770 | |
| 8771 | return 120000; |
| 8772 | } |
| 8773 | |
| 8774 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
| 8775 | { |
| 8776 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
| 8777 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 8778 | int pipe = intel_crtc->pipe; |
| 8779 | uint32_t val; |
| 8780 | |
| 8781 | val = 0; |
| 8782 | |
| 8783 | switch (intel_crtc->config->pipe_bpp) { |
| 8784 | case 18: |
| 8785 | val |= PIPECONF_6BPC; |
| 8786 | break; |
| 8787 | case 24: |
| 8788 | val |= PIPECONF_8BPC; |
| 8789 | break; |
| 8790 | case 30: |
| 8791 | val |= PIPECONF_10BPC; |
| 8792 | break; |
| 8793 | case 36: |
| 8794 | val |= PIPECONF_12BPC; |
| 8795 | break; |
| 8796 | default: |
| 8797 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
| 8798 | BUG(); |
| 8799 | } |
| 8800 | |
| 8801 | if (intel_crtc->config->dither) |
| 8802 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
| 8803 | |
| 8804 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
| 8805 | val |= PIPECONF_INTERLACED_ILK; |
| 8806 | else |
| 8807 | val |= PIPECONF_PROGRESSIVE; |
| 8808 | |
| 8809 | if (intel_crtc->config->limited_color_range) |
| 8810 | val |= PIPECONF_COLOR_RANGE_SELECT; |
| 8811 | |
| 8812 | I915_WRITE(PIPECONF(pipe), val); |
| 8813 | POSTING_READ(PIPECONF(pipe)); |
| 8814 | } |
| 8815 | |
| 8816 | /* |
| 8817 | * Set up the pipe CSC unit. |
| 8818 | * |
| 8819 | * Currently only full range RGB to limited range RGB conversion |
| 8820 | * is supported, but eventually this should handle various |
| 8821 | * RGB<->YCbCr scenarios as well. |
| 8822 | */ |
| 8823 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
| 8824 | { |
| 8825 | struct drm_device *dev = crtc->dev; |
| 8826 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8827 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 8828 | int pipe = intel_crtc->pipe; |
| 8829 | uint16_t coeff = 0x7800; /* 1.0 */ |
| 8830 | |
| 8831 | /* |
| 8832 | * TODO: Check what kind of values actually come out of the pipe |
| 8833 | * with these coeff/postoff values and adjust to get the best |
| 8834 | * accuracy. Perhaps we even need to take the bpc value into |
| 8835 | * consideration. |
| 8836 | */ |
| 8837 | |
| 8838 | if (intel_crtc->config->limited_color_range) |
| 8839 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
| 8840 | |
| 8841 | /* |
| 8842 | * GY/GU and RY/RU should be the other way around according |
| 8843 | * to BSpec, but reality doesn't agree. Just set them up in |
| 8844 | * a way that results in the correct picture. |
| 8845 | */ |
| 8846 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); |
| 8847 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); |
| 8848 | |
| 8849 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); |
| 8850 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); |
| 8851 | |
| 8852 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); |
| 8853 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); |
| 8854 | |
| 8855 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); |
| 8856 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); |
| 8857 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); |
| 8858 | |
| 8859 | if (INTEL_INFO(dev)->gen > 6) { |
| 8860 | uint16_t postoff = 0; |
| 8861 | |
| 8862 | if (intel_crtc->config->limited_color_range) |
| 8863 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
| 8864 | |
| 8865 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); |
| 8866 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); |
| 8867 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); |
| 8868 | |
| 8869 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); |
| 8870 | } else { |
| 8871 | uint32_t mode = CSC_MODE_YUV_TO_RGB; |
| 8872 | |
| 8873 | if (intel_crtc->config->limited_color_range) |
| 8874 | mode |= CSC_BLACK_SCREEN_OFFSET; |
| 8875 | |
| 8876 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); |
| 8877 | } |
| 8878 | } |
| 8879 | |
| 8880 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
| 8881 | { |
| 8882 | struct drm_device *dev = crtc->dev; |
| 8883 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8884 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 8885 | enum pipe pipe = intel_crtc->pipe; |
| 8886 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
| 8887 | uint32_t val; |
| 8888 | |
| 8889 | val = 0; |
| 8890 | |
| 8891 | if (IS_HASWELL(dev) && intel_crtc->config->dither) |
| 8892 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
| 8893 | |
| 8894 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
| 8895 | val |= PIPECONF_INTERLACED_ILK; |
| 8896 | else |
| 8897 | val |= PIPECONF_PROGRESSIVE; |
| 8898 | |
| 8899 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
| 8900 | POSTING_READ(PIPECONF(cpu_transcoder)); |
| 8901 | |
| 8902 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); |
| 8903 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); |
| 8904 | |
| 8905 | if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
| 8906 | val = 0; |
| 8907 | |
| 8908 | switch (intel_crtc->config->pipe_bpp) { |
| 8909 | case 18: |
| 8910 | val |= PIPEMISC_DITHER_6_BPC; |
| 8911 | break; |
| 8912 | case 24: |
| 8913 | val |= PIPEMISC_DITHER_8_BPC; |
| 8914 | break; |
| 8915 | case 30: |
| 8916 | val |= PIPEMISC_DITHER_10_BPC; |
| 8917 | break; |
| 8918 | case 36: |
| 8919 | val |= PIPEMISC_DITHER_12_BPC; |
| 8920 | break; |
| 8921 | default: |
| 8922 | /* Case prevented by pipe_config_set_bpp. */ |
| 8923 | BUG(); |
| 8924 | } |
| 8925 | |
| 8926 | if (intel_crtc->config->dither) |
| 8927 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
| 8928 | |
| 8929 | I915_WRITE(PIPEMISC(pipe), val); |
| 8930 | } |
| 8931 | } |
| 8932 | |
| 8933 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
| 8934 | struct intel_crtc_state *crtc_state, |
| 8935 | intel_clock_t *clock, |
| 8936 | bool *has_reduced_clock, |
| 8937 | intel_clock_t *reduced_clock) |
| 8938 | { |
| 8939 | struct drm_device *dev = crtc->dev; |
| 8940 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8941 | int refclk; |
| 8942 | const intel_limit_t *limit; |
| 8943 | bool ret; |
| 8944 | |
| 8945 | refclk = ironlake_get_refclk(crtc_state); |
| 8946 | |
| 8947 | /* |
| 8948 | * Returns a set of divisors for the desired target clock with the given |
| 8949 | * refclk, or FALSE. The returned values represent the clock equation: |
| 8950 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
| 8951 | */ |
| 8952 | limit = intel_limit(crtc_state, refclk); |
| 8953 | ret = dev_priv->display.find_dpll(limit, crtc_state, |
| 8954 | crtc_state->port_clock, |
| 8955 | refclk, NULL, clock); |
| 8956 | if (!ret) |
| 8957 | return false; |
| 8958 | |
| 8959 | return true; |
| 8960 | } |
| 8961 | |
| 8962 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
| 8963 | { |
| 8964 | /* |
| 8965 | * Account for spread spectrum to avoid |
| 8966 | * oversubscribing the link. Max center spread |
| 8967 | * is 2.5%; use 5% for safety's sake. |
| 8968 | */ |
| 8969 | u32 bps = target_clock * bpp * 21 / 20; |
| 8970 | return DIV_ROUND_UP(bps, link_bw * 8); |
| 8971 | } |
| 8972 | |
| 8973 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
| 8974 | { |
| 8975 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
| 8976 | } |
| 8977 | |
| 8978 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
| 8979 | struct intel_crtc_state *crtc_state, |
| 8980 | u32 *fp, |
| 8981 | intel_clock_t *reduced_clock, u32 *fp2) |
| 8982 | { |
| 8983 | struct drm_crtc *crtc = &intel_crtc->base; |
| 8984 | struct drm_device *dev = crtc->dev; |
| 8985 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8986 | struct drm_atomic_state *state = crtc_state->base.state; |
| 8987 | struct drm_connector *connector; |
| 8988 | struct drm_connector_state *connector_state; |
| 8989 | struct intel_encoder *encoder; |
| 8990 | uint32_t dpll; |
| 8991 | int factor, num_connectors = 0, i; |
| 8992 | bool is_lvds = false, is_sdvo = false; |
| 8993 | |
| 8994 | for_each_connector_in_state(state, connector, connector_state, i) { |
| 8995 | if (connector_state->crtc != crtc_state->base.crtc) |
| 8996 | continue; |
| 8997 | |
| 8998 | encoder = to_intel_encoder(connector_state->best_encoder); |
| 8999 | |
| 9000 | switch (encoder->type) { |
| 9001 | case INTEL_OUTPUT_LVDS: |
| 9002 | is_lvds = true; |
| 9003 | break; |
| 9004 | case INTEL_OUTPUT_SDVO: |
| 9005 | case INTEL_OUTPUT_HDMI: |
| 9006 | is_sdvo = true; |
| 9007 | break; |
| 9008 | default: |
| 9009 | break; |
| 9010 | } |
| 9011 | |
| 9012 | num_connectors++; |
| 9013 | } |
| 9014 | |
| 9015 | /* Enable autotuning of the PLL clock (if permissible) */ |
| 9016 | factor = 21; |
| 9017 | if (is_lvds) { |
| 9018 | if ((intel_panel_use_ssc(dev_priv) && |
| 9019 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
| 9020 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
| 9021 | factor = 25; |
| 9022 | } else if (crtc_state->sdvo_tv_clock) |
| 9023 | factor = 20; |
| 9024 | |
| 9025 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
| 9026 | *fp |= FP_CB_TUNE; |
| 9027 | |
| 9028 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
| 9029 | *fp2 |= FP_CB_TUNE; |
| 9030 | |
| 9031 | dpll = 0; |
| 9032 | |
| 9033 | if (is_lvds) |
| 9034 | dpll |= DPLLB_MODE_LVDS; |
| 9035 | else |
| 9036 | dpll |= DPLLB_MODE_DAC_SERIAL; |
| 9037 | |
| 9038 | dpll |= (crtc_state->pixel_multiplier - 1) |
| 9039 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
| 9040 | |
| 9041 | if (is_sdvo) |
| 9042 | dpll |= DPLL_SDVO_HIGH_SPEED; |
| 9043 | if (crtc_state->has_dp_encoder) |
| 9044 | dpll |= DPLL_SDVO_HIGH_SPEED; |
| 9045 | |
| 9046 | /* compute bitmask from p1 value */ |
| 9047 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
| 9048 | /* also FPA1 */ |
| 9049 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
| 9050 | |
| 9051 | switch (crtc_state->dpll.p2) { |
| 9052 | case 5: |
| 9053 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
| 9054 | break; |
| 9055 | case 7: |
| 9056 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; |
| 9057 | break; |
| 9058 | case 10: |
| 9059 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; |
| 9060 | break; |
| 9061 | case 14: |
| 9062 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; |
| 9063 | break; |
| 9064 | } |
| 9065 | |
| 9066 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
| 9067 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
| 9068 | else |
| 9069 | dpll |= PLL_REF_INPUT_DREFCLK; |
| 9070 | |
| 9071 | return dpll | DPLL_VCO_ENABLE; |
| 9072 | } |
| 9073 | |
| 9074 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
| 9075 | struct intel_crtc_state *crtc_state) |
| 9076 | { |
| 9077 | struct drm_device *dev = crtc->base.dev; |
| 9078 | intel_clock_t clock, reduced_clock; |
| 9079 | u32 dpll = 0, fp = 0, fp2 = 0; |
| 9080 | bool ok, has_reduced_clock = false; |
| 9081 | bool is_lvds = false; |
| 9082 | struct intel_shared_dpll *pll; |
| 9083 | |
| 9084 | memset(&crtc_state->dpll_hw_state, 0, |
| 9085 | sizeof(crtc_state->dpll_hw_state)); |
| 9086 | |
| 9087 | is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS); |
| 9088 | |
| 9089 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
| 9090 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); |
| 9091 | |
| 9092 | ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, |
| 9093 | &has_reduced_clock, &reduced_clock); |
| 9094 | if (!ok && !crtc_state->clock_set) { |
| 9095 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
| 9096 | return -EINVAL; |
| 9097 | } |
| 9098 | /* Compat-code for transition, will disappear. */ |
| 9099 | if (!crtc_state->clock_set) { |
| 9100 | crtc_state->dpll.n = clock.n; |
| 9101 | crtc_state->dpll.m1 = clock.m1; |
| 9102 | crtc_state->dpll.m2 = clock.m2; |
| 9103 | crtc_state->dpll.p1 = clock.p1; |
| 9104 | crtc_state->dpll.p2 = clock.p2; |
| 9105 | } |
| 9106 | |
| 9107 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
| 9108 | if (crtc_state->has_pch_encoder) { |
| 9109 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
| 9110 | if (has_reduced_clock) |
| 9111 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
| 9112 | |
| 9113 | dpll = ironlake_compute_dpll(crtc, crtc_state, |
| 9114 | &fp, &reduced_clock, |
| 9115 | has_reduced_clock ? &fp2 : NULL); |
| 9116 | |
| 9117 | crtc_state->dpll_hw_state.dpll = dpll; |
| 9118 | crtc_state->dpll_hw_state.fp0 = fp; |
| 9119 | if (has_reduced_clock) |
| 9120 | crtc_state->dpll_hw_state.fp1 = fp2; |
| 9121 | else |
| 9122 | crtc_state->dpll_hw_state.fp1 = fp; |
| 9123 | |
| 9124 | pll = intel_get_shared_dpll(crtc, crtc_state); |
| 9125 | if (pll == NULL) { |
| 9126 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
| 9127 | pipe_name(crtc->pipe)); |
| 9128 | return -EINVAL; |
| 9129 | } |
| 9130 | } |
| 9131 | |
| 9132 | if (is_lvds && has_reduced_clock) |
| 9133 | crtc->lowfreq_avail = true; |
| 9134 | else |
| 9135 | crtc->lowfreq_avail = false; |
| 9136 | |
| 9137 | return 0; |
| 9138 | } |
| 9139 | |
| 9140 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
| 9141 | struct intel_link_m_n *m_n) |
| 9142 | { |
| 9143 | struct drm_device *dev = crtc->base.dev; |
| 9144 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 9145 | enum pipe pipe = crtc->pipe; |
| 9146 | |
| 9147 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); |
| 9148 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); |
| 9149 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) |
| 9150 | & ~TU_SIZE_MASK; |
| 9151 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); |
| 9152 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) |
| 9153 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
| 9154 | } |
| 9155 | |
| 9156 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, |
| 9157 | enum transcoder transcoder, |
| 9158 | struct intel_link_m_n *m_n, |
| 9159 | struct intel_link_m_n *m2_n2) |
| 9160 | { |
| 9161 | struct drm_device *dev = crtc->base.dev; |
| 9162 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 9163 | enum pipe pipe = crtc->pipe; |
| 9164 | |
| 9165 | if (INTEL_INFO(dev)->gen >= 5) { |
| 9166 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); |
| 9167 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); |
| 9168 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) |
| 9169 | & ~TU_SIZE_MASK; |
| 9170 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); |
| 9171 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) |
| 9172 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
| 9173 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
| 9174 | * gen < 8) and if DRRS is supported (to make sure the |
| 9175 | * registers are not unnecessarily read). |
| 9176 | */ |
| 9177 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && |
| 9178 | crtc->config->has_drrs) { |
| 9179 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
| 9180 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); |
| 9181 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) |
| 9182 | & ~TU_SIZE_MASK; |
| 9183 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); |
| 9184 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) |
| 9185 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
| 9186 | } |
| 9187 | } else { |
| 9188 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); |
| 9189 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); |
| 9190 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) |
| 9191 | & ~TU_SIZE_MASK; |
| 9192 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); |
| 9193 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) |
| 9194 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
| 9195 | } |
| 9196 | } |
| 9197 | |
| 9198 | void intel_dp_get_m_n(struct intel_crtc *crtc, |
| 9199 | struct intel_crtc_state *pipe_config) |
| 9200 | { |
| 9201 | if (pipe_config->has_pch_encoder) |
| 9202 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
| 9203 | else |
| 9204 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, |
| 9205 | &pipe_config->dp_m_n, |
| 9206 | &pipe_config->dp_m2_n2); |
| 9207 | } |
| 9208 | |
| 9209 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
| 9210 | struct intel_crtc_state *pipe_config) |
| 9211 | { |
| 9212 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, |
| 9213 | &pipe_config->fdi_m_n, NULL); |
| 9214 | } |
| 9215 | |
| 9216 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
| 9217 | struct intel_crtc_state *pipe_config) |
| 9218 | { |
| 9219 | struct drm_device *dev = crtc->base.dev; |
| 9220 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 9221 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
| 9222 | uint32_t ps_ctrl = 0; |
| 9223 | int id = -1; |
| 9224 | int i; |
| 9225 | |
| 9226 | /* find scaler attached to this pipe */ |
| 9227 | for (i = 0; i < crtc->num_scalers; i++) { |
| 9228 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); |
| 9229 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { |
| 9230 | id = i; |
| 9231 | pipe_config->pch_pfit.enabled = true; |
| 9232 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); |
| 9233 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); |
| 9234 | break; |
| 9235 | } |
| 9236 | } |
| 9237 | |
| 9238 | scaler_state->scaler_id = id; |
| 9239 | if (id >= 0) { |
| 9240 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); |
| 9241 | } else { |
| 9242 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); |
| 9243 | } |
| 9244 | } |
| 9245 | |
| 9246 | static void |
| 9247 | skylake_get_initial_plane_config(struct intel_crtc *crtc, |
| 9248 | struct intel_initial_plane_config *plane_config) |
| 9249 | { |
| 9250 | struct drm_device *dev = crtc->base.dev; |
| 9251 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 9252 | u32 val, base, offset, stride_mult, tiling; |
| 9253 | int pipe = crtc->pipe; |
| 9254 | int fourcc, pixel_format; |
| 9255 | unsigned int aligned_height; |
| 9256 | struct drm_framebuffer *fb; |
| 9257 | struct intel_framebuffer *intel_fb; |
| 9258 | |
| 9259 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
| 9260 | if (!intel_fb) { |
| 9261 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
| 9262 | return; |
| 9263 | } |
| 9264 | |
| 9265 | fb = &intel_fb->base; |
| 9266 | |
| 9267 | val = I915_READ(PLANE_CTL(pipe, 0)); |
| 9268 | if (!(val & PLANE_CTL_ENABLE)) |
| 9269 | goto error; |
| 9270 | |
| 9271 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
| 9272 | fourcc = skl_format_to_fourcc(pixel_format, |
| 9273 | val & PLANE_CTL_ORDER_RGBX, |
| 9274 | val & PLANE_CTL_ALPHA_MASK); |
| 9275 | fb->pixel_format = fourcc; |
| 9276 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; |
| 9277 | |
| 9278 | tiling = val & PLANE_CTL_TILED_MASK; |
| 9279 | switch (tiling) { |
| 9280 | case PLANE_CTL_TILED_LINEAR: |
| 9281 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; |
| 9282 | break; |
| 9283 | case PLANE_CTL_TILED_X: |
| 9284 | plane_config->tiling = I915_TILING_X; |
| 9285 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
| 9286 | break; |
| 9287 | case PLANE_CTL_TILED_Y: |
| 9288 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; |
| 9289 | break; |
| 9290 | case PLANE_CTL_TILED_YF: |
| 9291 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; |
| 9292 | break; |
| 9293 | default: |
| 9294 | MISSING_CASE(tiling); |
| 9295 | goto error; |
| 9296 | } |
| 9297 | |
| 9298 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
| 9299 | plane_config->base = base; |
| 9300 | |
| 9301 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); |
| 9302 | |
| 9303 | val = I915_READ(PLANE_SIZE(pipe, 0)); |
| 9304 | fb->height = ((val >> 16) & 0xfff) + 1; |
| 9305 | fb->width = ((val >> 0) & 0x1fff) + 1; |
| 9306 | |
| 9307 | val = I915_READ(PLANE_STRIDE(pipe, 0)); |
| 9308 | stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0], |
| 9309 | fb->pixel_format); |
| 9310 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
| 9311 | |
| 9312 | aligned_height = intel_fb_align_height(dev, fb->height, |
| 9313 | fb->pixel_format, |
| 9314 | fb->modifier[0]); |
| 9315 | |
| 9316 | plane_config->size = fb->pitches[0] * aligned_height; |
| 9317 | |
| 9318 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
| 9319 | pipe_name(pipe), fb->width, fb->height, |
| 9320 | fb->bits_per_pixel, base, fb->pitches[0], |
| 9321 | plane_config->size); |
| 9322 | |
| 9323 | plane_config->fb = intel_fb; |
| 9324 | return; |
| 9325 | |
| 9326 | error: |
| 9327 | kfree(fb); |
| 9328 | } |
| 9329 | |
| 9330 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
| 9331 | struct intel_crtc_state *pipe_config) |
| 9332 | { |
| 9333 | struct drm_device *dev = crtc->base.dev; |
| 9334 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 9335 | uint32_t tmp; |
| 9336 | |
| 9337 | tmp = I915_READ(PF_CTL(crtc->pipe)); |
| 9338 | |
| 9339 | if (tmp & PF_ENABLE) { |
| 9340 | pipe_config->pch_pfit.enabled = true; |
| 9341 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
| 9342 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); |
| 9343 | |
| 9344 | /* We currently do not free assignements of panel fitters on |
| 9345 | * ivb/hsw (since we don't use the higher upscaling modes which |
| 9346 | * differentiates them) so just WARN about this case for now. */ |
| 9347 | if (IS_GEN7(dev)) { |
| 9348 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != |
| 9349 | PF_PIPE_SEL_IVB(crtc->pipe)); |
| 9350 | } |
| 9351 | } |
| 9352 | } |
| 9353 | |
| 9354 | static void |
| 9355 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, |
| 9356 | struct intel_initial_plane_config *plane_config) |
| 9357 | { |
| 9358 | struct drm_device *dev = crtc->base.dev; |
| 9359 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 9360 | u32 val, base, offset; |
| 9361 | int pipe = crtc->pipe; |
| 9362 | int fourcc, pixel_format; |
| 9363 | unsigned int aligned_height; |
| 9364 | struct drm_framebuffer *fb; |
| 9365 | struct intel_framebuffer *intel_fb; |
| 9366 | |
| 9367 | val = I915_READ(DSPCNTR(pipe)); |
| 9368 | if (!(val & DISPLAY_PLANE_ENABLE)) |
| 9369 | return; |
| 9370 | |
| 9371 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
| 9372 | if (!intel_fb) { |
| 9373 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
| 9374 | return; |
| 9375 | } |
| 9376 | |
| 9377 | fb = &intel_fb->base; |
| 9378 | |
| 9379 | if (INTEL_INFO(dev)->gen >= 4) { |
| 9380 | if (val & DISPPLANE_TILED) { |
| 9381 | plane_config->tiling = I915_TILING_X; |
| 9382 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
| 9383 | } |
| 9384 | } |
| 9385 | |
| 9386 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; |
| 9387 | fourcc = i9xx_format_to_fourcc(pixel_format); |
| 9388 | fb->pixel_format = fourcc; |
| 9389 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; |
| 9390 | |
| 9391 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
| 9392 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
| 9393 | offset = I915_READ(DSPOFFSET(pipe)); |
| 9394 | } else { |
| 9395 | if (plane_config->tiling) |
| 9396 | offset = I915_READ(DSPTILEOFF(pipe)); |
| 9397 | else |
| 9398 | offset = I915_READ(DSPLINOFF(pipe)); |
| 9399 | } |
| 9400 | plane_config->base = base; |
| 9401 | |
| 9402 | val = I915_READ(PIPESRC(pipe)); |
| 9403 | fb->width = ((val >> 16) & 0xfff) + 1; |
| 9404 | fb->height = ((val >> 0) & 0xfff) + 1; |
| 9405 | |
| 9406 | val = I915_READ(DSPSTRIDE(pipe)); |
| 9407 | fb->pitches[0] = val & 0xffffffc0; |
| 9408 | |
| 9409 | aligned_height = intel_fb_align_height(dev, fb->height, |
| 9410 | fb->pixel_format, |
| 9411 | fb->modifier[0]); |
| 9412 | |
| 9413 | plane_config->size = fb->pitches[0] * aligned_height; |
| 9414 | |
| 9415 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
| 9416 | pipe_name(pipe), fb->width, fb->height, |
| 9417 | fb->bits_per_pixel, base, fb->pitches[0], |
| 9418 | plane_config->size); |
| 9419 | |
| 9420 | plane_config->fb = intel_fb; |
| 9421 | } |
| 9422 | |
| 9423 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
| 9424 | struct intel_crtc_state *pipe_config) |
| 9425 | { |
| 9426 | struct drm_device *dev = crtc->base.dev; |
| 9427 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 9428 | uint32_t tmp; |
| 9429 | |
| 9430 | if (!intel_display_power_is_enabled(dev_priv, |
| 9431 | POWER_DOMAIN_PIPE(crtc->pipe))) |
| 9432 | return false; |
| 9433 | |
| 9434 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
| 9435 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
| 9436 | |
| 9437 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
| 9438 | if (!(tmp & PIPECONF_ENABLE)) |
| 9439 | return false; |
| 9440 | |
| 9441 | switch (tmp & PIPECONF_BPC_MASK) { |
| 9442 | case PIPECONF_6BPC: |
| 9443 | pipe_config->pipe_bpp = 18; |
| 9444 | break; |
| 9445 | case PIPECONF_8BPC: |
| 9446 | pipe_config->pipe_bpp = 24; |
| 9447 | break; |
| 9448 | case PIPECONF_10BPC: |
| 9449 | pipe_config->pipe_bpp = 30; |
| 9450 | break; |
| 9451 | case PIPECONF_12BPC: |
| 9452 | pipe_config->pipe_bpp = 36; |
| 9453 | break; |
| 9454 | default: |
| 9455 | break; |
| 9456 | } |
| 9457 | |
| 9458 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
| 9459 | pipe_config->limited_color_range = true; |
| 9460 | |
| 9461 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
| 9462 | struct intel_shared_dpll *pll; |
| 9463 | |
| 9464 | pipe_config->has_pch_encoder = true; |
| 9465 | |
| 9466 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
| 9467 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> |
| 9468 | FDI_DP_PORT_WIDTH_SHIFT) + 1; |
| 9469 | |
| 9470 | ironlake_get_fdi_m_n_config(crtc, pipe_config); |
| 9471 | |
| 9472 | if (HAS_PCH_IBX(dev_priv->dev)) { |
| 9473 | pipe_config->shared_dpll = |
| 9474 | (enum intel_dpll_id) crtc->pipe; |
| 9475 | } else { |
| 9476 | tmp = I915_READ(PCH_DPLL_SEL); |
| 9477 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) |
| 9478 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; |
| 9479 | else |
| 9480 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; |
| 9481 | } |
| 9482 | |
| 9483 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; |
| 9484 | |
| 9485 | WARN_ON(!pll->get_hw_state(dev_priv, pll, |
| 9486 | &pipe_config->dpll_hw_state)); |
| 9487 | |
| 9488 | tmp = pipe_config->dpll_hw_state.dpll; |
| 9489 | pipe_config->pixel_multiplier = |
| 9490 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) |
| 9491 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; |
| 9492 | |
| 9493 | ironlake_pch_clock_get(crtc, pipe_config); |
| 9494 | } else { |
| 9495 | pipe_config->pixel_multiplier = 1; |
| 9496 | } |
| 9497 | |
| 9498 | intel_get_pipe_timings(crtc, pipe_config); |
| 9499 | |
| 9500 | ironlake_get_pfit_config(crtc, pipe_config); |
| 9501 | |
| 9502 | return true; |
| 9503 | } |
| 9504 | |
| 9505 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
| 9506 | { |
| 9507 | struct drm_device *dev = dev_priv->dev; |
| 9508 | struct intel_crtc *crtc; |
| 9509 | |
| 9510 | for_each_intel_crtc(dev, crtc) |
| 9511 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
| 9512 | pipe_name(crtc->pipe)); |
| 9513 | |
| 9514 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
| 9515 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); |
| 9516 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
| 9517 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); |
| 9518 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
| 9519 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, |
| 9520 | "CPU PWM1 enabled\n"); |
| 9521 | if (IS_HASWELL(dev)) |
| 9522 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
| 9523 | "CPU PWM2 enabled\n"); |
| 9524 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
| 9525 | "PCH PWM1 enabled\n"); |
| 9526 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
| 9527 | "Utility pin enabled\n"); |
| 9528 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
| 9529 | |
| 9530 | /* |
| 9531 | * In theory we can still leave IRQs enabled, as long as only the HPD |
| 9532 | * interrupts remain enabled. We used to check for that, but since it's |
| 9533 | * gen-specific and since we only disable LCPLL after we fully disable |
| 9534 | * the interrupts, the check below should be enough. |
| 9535 | */ |
| 9536 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
| 9537 | } |
| 9538 | |
| 9539 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
| 9540 | { |
| 9541 | struct drm_device *dev = dev_priv->dev; |
| 9542 | |
| 9543 | if (IS_HASWELL(dev)) |
| 9544 | return I915_READ(D_COMP_HSW); |
| 9545 | else |
| 9546 | return I915_READ(D_COMP_BDW); |
| 9547 | } |
| 9548 | |
| 9549 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
| 9550 | { |
| 9551 | struct drm_device *dev = dev_priv->dev; |
| 9552 | |
| 9553 | if (IS_HASWELL(dev)) { |
| 9554 | mutex_lock(&dev_priv->rps.hw_lock); |
| 9555 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, |
| 9556 | val)) |
| 9557 | DRM_ERROR("Failed to write to D_COMP\n"); |
| 9558 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 9559 | } else { |
| 9560 | I915_WRITE(D_COMP_BDW, val); |
| 9561 | POSTING_READ(D_COMP_BDW); |
| 9562 | } |
| 9563 | } |
| 9564 | |
| 9565 | /* |
| 9566 | * This function implements pieces of two sequences from BSpec: |
| 9567 | * - Sequence for display software to disable LCPLL |
| 9568 | * - Sequence for display software to allow package C8+ |
| 9569 | * The steps implemented here are just the steps that actually touch the LCPLL |
| 9570 | * register. Callers should take care of disabling all the display engine |
| 9571 | * functions, doing the mode unset, fixing interrupts, etc. |
| 9572 | */ |
| 9573 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
| 9574 | bool switch_to_fclk, bool allow_power_down) |
| 9575 | { |
| 9576 | uint32_t val; |
| 9577 | |
| 9578 | assert_can_disable_lcpll(dev_priv); |
| 9579 | |
| 9580 | val = I915_READ(LCPLL_CTL); |
| 9581 | |
| 9582 | if (switch_to_fclk) { |
| 9583 | val |= LCPLL_CD_SOURCE_FCLK; |
| 9584 | I915_WRITE(LCPLL_CTL, val); |
| 9585 | |
| 9586 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & |
| 9587 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) |
| 9588 | DRM_ERROR("Switching to FCLK failed\n"); |
| 9589 | |
| 9590 | val = I915_READ(LCPLL_CTL); |
| 9591 | } |
| 9592 | |
| 9593 | val |= LCPLL_PLL_DISABLE; |
| 9594 | I915_WRITE(LCPLL_CTL, val); |
| 9595 | POSTING_READ(LCPLL_CTL); |
| 9596 | |
| 9597 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) |
| 9598 | DRM_ERROR("LCPLL still locked\n"); |
| 9599 | |
| 9600 | val = hsw_read_dcomp(dev_priv); |
| 9601 | val |= D_COMP_COMP_DISABLE; |
| 9602 | hsw_write_dcomp(dev_priv, val); |
| 9603 | ndelay(100); |
| 9604 | |
| 9605 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
| 9606 | 1)) |
| 9607 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
| 9608 | |
| 9609 | if (allow_power_down) { |
| 9610 | val = I915_READ(LCPLL_CTL); |
| 9611 | val |= LCPLL_POWER_DOWN_ALLOW; |
| 9612 | I915_WRITE(LCPLL_CTL, val); |
| 9613 | POSTING_READ(LCPLL_CTL); |
| 9614 | } |
| 9615 | } |
| 9616 | |
| 9617 | /* |
| 9618 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL |
| 9619 | * source. |
| 9620 | */ |
| 9621 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
| 9622 | { |
| 9623 | uint32_t val; |
| 9624 | |
| 9625 | val = I915_READ(LCPLL_CTL); |
| 9626 | |
| 9627 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | |
| 9628 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) |
| 9629 | return; |
| 9630 | |
| 9631 | /* |
| 9632 | * Make sure we're not on PC8 state before disabling PC8, otherwise |
| 9633 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. |
| 9634 | */ |
| 9635 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
| 9636 | |
| 9637 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
| 9638 | val &= ~LCPLL_POWER_DOWN_ALLOW; |
| 9639 | I915_WRITE(LCPLL_CTL, val); |
| 9640 | POSTING_READ(LCPLL_CTL); |
| 9641 | } |
| 9642 | |
| 9643 | val = hsw_read_dcomp(dev_priv); |
| 9644 | val |= D_COMP_COMP_FORCE; |
| 9645 | val &= ~D_COMP_COMP_DISABLE; |
| 9646 | hsw_write_dcomp(dev_priv, val); |
| 9647 | |
| 9648 | val = I915_READ(LCPLL_CTL); |
| 9649 | val &= ~LCPLL_PLL_DISABLE; |
| 9650 | I915_WRITE(LCPLL_CTL, val); |
| 9651 | |
| 9652 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) |
| 9653 | DRM_ERROR("LCPLL not locked yet\n"); |
| 9654 | |
| 9655 | if (val & LCPLL_CD_SOURCE_FCLK) { |
| 9656 | val = I915_READ(LCPLL_CTL); |
| 9657 | val &= ~LCPLL_CD_SOURCE_FCLK; |
| 9658 | I915_WRITE(LCPLL_CTL, val); |
| 9659 | |
| 9660 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & |
| 9661 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) |
| 9662 | DRM_ERROR("Switching back to LCPLL failed\n"); |
| 9663 | } |
| 9664 | |
| 9665 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
| 9666 | intel_update_cdclk(dev_priv->dev); |
| 9667 | } |
| 9668 | |
| 9669 | /* |
| 9670 | * Package states C8 and deeper are really deep PC states that can only be |
| 9671 | * reached when all the devices on the system allow it, so even if the graphics |
| 9672 | * device allows PC8+, it doesn't mean the system will actually get to these |
| 9673 | * states. Our driver only allows PC8+ when going into runtime PM. |
| 9674 | * |
| 9675 | * The requirements for PC8+ are that all the outputs are disabled, the power |
| 9676 | * well is disabled and most interrupts are disabled, and these are also |
| 9677 | * requirements for runtime PM. When these conditions are met, we manually do |
| 9678 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk |
| 9679 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard |
| 9680 | * hang the machine. |
| 9681 | * |
| 9682 | * When we really reach PC8 or deeper states (not just when we allow it) we lose |
| 9683 | * the state of some registers, so when we come back from PC8+ we need to |
| 9684 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't |
| 9685 | * need to take care of the registers kept by RC6. Notice that this happens even |
| 9686 | * if we don't put the device in PCI D3 state (which is what currently happens |
| 9687 | * because of the runtime PM support). |
| 9688 | * |
| 9689 | * For more, read "Display Sequences for Package C8" on the hardware |
| 9690 | * documentation. |
| 9691 | */ |
| 9692 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
| 9693 | { |
| 9694 | struct drm_device *dev = dev_priv->dev; |
| 9695 | uint32_t val; |
| 9696 | |
| 9697 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
| 9698 | |
| 9699 | if (HAS_PCH_LPT_LP(dev)) { |
| 9700 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
| 9701 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; |
| 9702 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
| 9703 | } |
| 9704 | |
| 9705 | lpt_disable_clkout_dp(dev); |
| 9706 | hsw_disable_lcpll(dev_priv, true, true); |
| 9707 | } |
| 9708 | |
| 9709 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
| 9710 | { |
| 9711 | struct drm_device *dev = dev_priv->dev; |
| 9712 | uint32_t val; |
| 9713 | |
| 9714 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
| 9715 | |
| 9716 | hsw_restore_lcpll(dev_priv); |
| 9717 | lpt_init_pch_refclk(dev); |
| 9718 | |
| 9719 | if (HAS_PCH_LPT_LP(dev)) { |
| 9720 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
| 9721 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; |
| 9722 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
| 9723 | } |
| 9724 | } |
| 9725 | |
| 9726 | static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
| 9727 | { |
| 9728 | struct drm_device *dev = old_state->dev; |
| 9729 | struct intel_atomic_state *old_intel_state = |
| 9730 | to_intel_atomic_state(old_state); |
| 9731 | unsigned int req_cdclk = old_intel_state->dev_cdclk; |
| 9732 | |
| 9733 | broxton_set_cdclk(dev, req_cdclk); |
| 9734 | } |
| 9735 | |
| 9736 | /* compute the max rate for new configuration */ |
| 9737 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
| 9738 | { |
| 9739 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
| 9740 | struct drm_i915_private *dev_priv = state->dev->dev_private; |
| 9741 | struct drm_crtc *crtc; |
| 9742 | struct drm_crtc_state *cstate; |
| 9743 | struct intel_crtc_state *crtc_state; |
| 9744 | unsigned max_pixel_rate = 0, i; |
| 9745 | enum pipe pipe; |
| 9746 | |
| 9747 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
| 9748 | sizeof(intel_state->min_pixclk)); |
| 9749 | |
| 9750 | for_each_crtc_in_state(state, crtc, cstate, i) { |
| 9751 | int pixel_rate; |
| 9752 | |
| 9753 | crtc_state = to_intel_crtc_state(cstate); |
| 9754 | if (!crtc_state->base.enable) { |
| 9755 | intel_state->min_pixclk[i] = 0; |
| 9756 | continue; |
| 9757 | } |
| 9758 | |
| 9759 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
| 9760 | |
| 9761 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ |
| 9762 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
| 9763 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
| 9764 | |
| 9765 | intel_state->min_pixclk[i] = pixel_rate; |
| 9766 | } |
| 9767 | |
| 9768 | if (!intel_state->active_crtcs) |
| 9769 | return 0; |
| 9770 | |
| 9771 | for_each_pipe(dev_priv, pipe) |
| 9772 | max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate); |
| 9773 | |
| 9774 | return max_pixel_rate; |
| 9775 | } |
| 9776 | |
| 9777 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) |
| 9778 | { |
| 9779 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 9780 | uint32_t val, data; |
| 9781 | int ret; |
| 9782 | |
| 9783 | if (WARN((I915_READ(LCPLL_CTL) & |
| 9784 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | |
| 9785 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | |
| 9786 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | |
| 9787 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, |
| 9788 | "trying to change cdclk frequency with cdclk not enabled\n")) |
| 9789 | return; |
| 9790 | |
| 9791 | mutex_lock(&dev_priv->rps.hw_lock); |
| 9792 | ret = sandybridge_pcode_write(dev_priv, |
| 9793 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); |
| 9794 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 9795 | if (ret) { |
| 9796 | DRM_ERROR("failed to inform pcode about cdclk change\n"); |
| 9797 | return; |
| 9798 | } |
| 9799 | |
| 9800 | val = I915_READ(LCPLL_CTL); |
| 9801 | val |= LCPLL_CD_SOURCE_FCLK; |
| 9802 | I915_WRITE(LCPLL_CTL, val); |
| 9803 | |
| 9804 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & |
| 9805 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) |
| 9806 | DRM_ERROR("Switching to FCLK failed\n"); |
| 9807 | |
| 9808 | val = I915_READ(LCPLL_CTL); |
| 9809 | val &= ~LCPLL_CLK_FREQ_MASK; |
| 9810 | |
| 9811 | switch (cdclk) { |
| 9812 | case 450000: |
| 9813 | val |= LCPLL_CLK_FREQ_450; |
| 9814 | data = 0; |
| 9815 | break; |
| 9816 | case 540000: |
| 9817 | val |= LCPLL_CLK_FREQ_54O_BDW; |
| 9818 | data = 1; |
| 9819 | break; |
| 9820 | case 337500: |
| 9821 | val |= LCPLL_CLK_FREQ_337_5_BDW; |
| 9822 | data = 2; |
| 9823 | break; |
| 9824 | case 675000: |
| 9825 | val |= LCPLL_CLK_FREQ_675_BDW; |
| 9826 | data = 3; |
| 9827 | break; |
| 9828 | default: |
| 9829 | WARN(1, "invalid cdclk frequency\n"); |
| 9830 | return; |
| 9831 | } |
| 9832 | |
| 9833 | I915_WRITE(LCPLL_CTL, val); |
| 9834 | |
| 9835 | val = I915_READ(LCPLL_CTL); |
| 9836 | val &= ~LCPLL_CD_SOURCE_FCLK; |
| 9837 | I915_WRITE(LCPLL_CTL, val); |
| 9838 | |
| 9839 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & |
| 9840 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) |
| 9841 | DRM_ERROR("Switching back to LCPLL failed\n"); |
| 9842 | |
| 9843 | mutex_lock(&dev_priv->rps.hw_lock); |
| 9844 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); |
| 9845 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 9846 | |
| 9847 | intel_update_cdclk(dev); |
| 9848 | |
| 9849 | WARN(cdclk != dev_priv->cdclk_freq, |
| 9850 | "cdclk requested %d kHz but got %d kHz\n", |
| 9851 | cdclk, dev_priv->cdclk_freq); |
| 9852 | } |
| 9853 | |
| 9854 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
| 9855 | { |
| 9856 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
| 9857 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
| 9858 | int max_pixclk = ilk_max_pixel_rate(state); |
| 9859 | int cdclk; |
| 9860 | |
| 9861 | /* |
| 9862 | * FIXME should also account for plane ratio |
| 9863 | * once 64bpp pixel formats are supported. |
| 9864 | */ |
| 9865 | if (max_pixclk > 540000) |
| 9866 | cdclk = 675000; |
| 9867 | else if (max_pixclk > 450000) |
| 9868 | cdclk = 540000; |
| 9869 | else if (max_pixclk > 337500) |
| 9870 | cdclk = 450000; |
| 9871 | else |
| 9872 | cdclk = 337500; |
| 9873 | |
| 9874 | if (cdclk > dev_priv->max_cdclk_freq) { |
| 9875 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
| 9876 | cdclk, dev_priv->max_cdclk_freq); |
| 9877 | return -EINVAL; |
| 9878 | } |
| 9879 | |
| 9880 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; |
| 9881 | if (!intel_state->active_crtcs) |
| 9882 | intel_state->dev_cdclk = 337500; |
| 9883 | |
| 9884 | return 0; |
| 9885 | } |
| 9886 | |
| 9887 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
| 9888 | { |
| 9889 | struct drm_device *dev = old_state->dev; |
| 9890 | struct intel_atomic_state *old_intel_state = |
| 9891 | to_intel_atomic_state(old_state); |
| 9892 | unsigned req_cdclk = old_intel_state->dev_cdclk; |
| 9893 | |
| 9894 | broadwell_set_cdclk(dev, req_cdclk); |
| 9895 | } |
| 9896 | |
| 9897 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
| 9898 | struct intel_crtc_state *crtc_state) |
| 9899 | { |
| 9900 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
| 9901 | return -EINVAL; |
| 9902 | |
| 9903 | crtc->lowfreq_avail = false; |
| 9904 | |
| 9905 | return 0; |
| 9906 | } |
| 9907 | |
| 9908 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
| 9909 | enum port port, |
| 9910 | struct intel_crtc_state *pipe_config) |
| 9911 | { |
| 9912 | switch (port) { |
| 9913 | case PORT_A: |
| 9914 | pipe_config->ddi_pll_sel = SKL_DPLL0; |
| 9915 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; |
| 9916 | break; |
| 9917 | case PORT_B: |
| 9918 | pipe_config->ddi_pll_sel = SKL_DPLL1; |
| 9919 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; |
| 9920 | break; |
| 9921 | case PORT_C: |
| 9922 | pipe_config->ddi_pll_sel = SKL_DPLL2; |
| 9923 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; |
| 9924 | break; |
| 9925 | default: |
| 9926 | DRM_ERROR("Incorrect port type\n"); |
| 9927 | } |
| 9928 | } |
| 9929 | |
| 9930 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
| 9931 | enum port port, |
| 9932 | struct intel_crtc_state *pipe_config) |
| 9933 | { |
| 9934 | u32 temp, dpll_ctl1; |
| 9935 | |
| 9936 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); |
| 9937 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); |
| 9938 | |
| 9939 | switch (pipe_config->ddi_pll_sel) { |
| 9940 | case SKL_DPLL0: |
| 9941 | /* |
| 9942 | * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part |
| 9943 | * of the shared DPLL framework and thus needs to be read out |
| 9944 | * separately |
| 9945 | */ |
| 9946 | dpll_ctl1 = I915_READ(DPLL_CTRL1); |
| 9947 | pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; |
| 9948 | break; |
| 9949 | case SKL_DPLL1: |
| 9950 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; |
| 9951 | break; |
| 9952 | case SKL_DPLL2: |
| 9953 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; |
| 9954 | break; |
| 9955 | case SKL_DPLL3: |
| 9956 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; |
| 9957 | break; |
| 9958 | } |
| 9959 | } |
| 9960 | |
| 9961 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
| 9962 | enum port port, |
| 9963 | struct intel_crtc_state *pipe_config) |
| 9964 | { |
| 9965 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); |
| 9966 | |
| 9967 | switch (pipe_config->ddi_pll_sel) { |
| 9968 | case PORT_CLK_SEL_WRPLL1: |
| 9969 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; |
| 9970 | break; |
| 9971 | case PORT_CLK_SEL_WRPLL2: |
| 9972 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; |
| 9973 | break; |
| 9974 | case PORT_CLK_SEL_SPLL: |
| 9975 | pipe_config->shared_dpll = DPLL_ID_SPLL; |
| 9976 | break; |
| 9977 | } |
| 9978 | } |
| 9979 | |
| 9980 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
| 9981 | struct intel_crtc_state *pipe_config) |
| 9982 | { |
| 9983 | struct drm_device *dev = crtc->base.dev; |
| 9984 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 9985 | struct intel_shared_dpll *pll; |
| 9986 | enum port port; |
| 9987 | uint32_t tmp; |
| 9988 | |
| 9989 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); |
| 9990 | |
| 9991 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; |
| 9992 | |
| 9993 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
| 9994 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
| 9995 | else if (IS_BROXTON(dev)) |
| 9996 | bxt_get_ddi_pll(dev_priv, port, pipe_config); |
| 9997 | else |
| 9998 | haswell_get_ddi_pll(dev_priv, port, pipe_config); |
| 9999 | |
| 10000 | if (pipe_config->shared_dpll >= 0) { |
| 10001 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; |
| 10002 | |
| 10003 | WARN_ON(!pll->get_hw_state(dev_priv, pll, |
| 10004 | &pipe_config->dpll_hw_state)); |
| 10005 | } |
| 10006 | |
| 10007 | /* |
| 10008 | * Haswell has only FDI/PCH transcoder A. It is which is connected to |
| 10009 | * DDI E. So just check whether this pipe is wired to DDI E and whether |
| 10010 | * the PCH transcoder is on. |
| 10011 | */ |
| 10012 | if (INTEL_INFO(dev)->gen < 9 && |
| 10013 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
| 10014 | pipe_config->has_pch_encoder = true; |
| 10015 | |
| 10016 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); |
| 10017 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> |
| 10018 | FDI_DP_PORT_WIDTH_SHIFT) + 1; |
| 10019 | |
| 10020 | ironlake_get_fdi_m_n_config(crtc, pipe_config); |
| 10021 | } |
| 10022 | } |
| 10023 | |
| 10024 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
| 10025 | struct intel_crtc_state *pipe_config) |
| 10026 | { |
| 10027 | struct drm_device *dev = crtc->base.dev; |
| 10028 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 10029 | enum intel_display_power_domain pfit_domain; |
| 10030 | uint32_t tmp; |
| 10031 | |
| 10032 | if (!intel_display_power_is_enabled(dev_priv, |
| 10033 | POWER_DOMAIN_PIPE(crtc->pipe))) |
| 10034 | return false; |
| 10035 | |
| 10036 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
| 10037 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
| 10038 | |
| 10039 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
| 10040 | if (tmp & TRANS_DDI_FUNC_ENABLE) { |
| 10041 | enum pipe trans_edp_pipe; |
| 10042 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { |
| 10043 | default: |
| 10044 | WARN(1, "unknown pipe linked to edp transcoder\n"); |
| 10045 | case TRANS_DDI_EDP_INPUT_A_ONOFF: |
| 10046 | case TRANS_DDI_EDP_INPUT_A_ON: |
| 10047 | trans_edp_pipe = PIPE_A; |
| 10048 | break; |
| 10049 | case TRANS_DDI_EDP_INPUT_B_ONOFF: |
| 10050 | trans_edp_pipe = PIPE_B; |
| 10051 | break; |
| 10052 | case TRANS_DDI_EDP_INPUT_C_ONOFF: |
| 10053 | trans_edp_pipe = PIPE_C; |
| 10054 | break; |
| 10055 | } |
| 10056 | |
| 10057 | if (trans_edp_pipe == crtc->pipe) |
| 10058 | pipe_config->cpu_transcoder = TRANSCODER_EDP; |
| 10059 | } |
| 10060 | |
| 10061 | if (!intel_display_power_is_enabled(dev_priv, |
| 10062 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
| 10063 | return false; |
| 10064 | |
| 10065 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
| 10066 | if (!(tmp & PIPECONF_ENABLE)) |
| 10067 | return false; |
| 10068 | |
| 10069 | haswell_get_ddi_port_state(crtc, pipe_config); |
| 10070 | |
| 10071 | intel_get_pipe_timings(crtc, pipe_config); |
| 10072 | |
| 10073 | if (INTEL_INFO(dev)->gen >= 9) { |
| 10074 | skl_init_scalers(dev, crtc, pipe_config); |
| 10075 | } |
| 10076 | |
| 10077 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
| 10078 | |
| 10079 | if (INTEL_INFO(dev)->gen >= 9) { |
| 10080 | pipe_config->scaler_state.scaler_id = -1; |
| 10081 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); |
| 10082 | } |
| 10083 | |
| 10084 | if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { |
| 10085 | if (INTEL_INFO(dev)->gen >= 9) |
| 10086 | skylake_get_pfit_config(crtc, pipe_config); |
| 10087 | else |
| 10088 | ironlake_get_pfit_config(crtc, pipe_config); |
| 10089 | } |
| 10090 | |
| 10091 | if (IS_HASWELL(dev)) |
| 10092 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && |
| 10093 | (I915_READ(IPS_CTL) & IPS_ENABLE); |
| 10094 | |
| 10095 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { |
| 10096 | pipe_config->pixel_multiplier = |
| 10097 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; |
| 10098 | } else { |
| 10099 | pipe_config->pixel_multiplier = 1; |
| 10100 | } |
| 10101 | |
| 10102 | return true; |
| 10103 | } |
| 10104 | |
| 10105 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, |
| 10106 | const struct intel_plane_state *plane_state) |
| 10107 | { |
| 10108 | struct drm_device *dev = crtc->dev; |
| 10109 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 10110 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 10111 | uint32_t cntl = 0, size = 0; |
| 10112 | |
| 10113 | if (plane_state && plane_state->visible) { |
| 10114 | unsigned int width = plane_state->base.crtc_w; |
| 10115 | unsigned int height = plane_state->base.crtc_h; |
| 10116 | unsigned int stride = roundup_pow_of_two(width) * 4; |
| 10117 | |
| 10118 | switch (stride) { |
| 10119 | default: |
| 10120 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", |
| 10121 | width, stride); |
| 10122 | stride = 256; |
| 10123 | /* fallthrough */ |
| 10124 | case 256: |
| 10125 | case 512: |
| 10126 | case 1024: |
| 10127 | case 2048: |
| 10128 | break; |
| 10129 | } |
| 10130 | |
| 10131 | cntl |= CURSOR_ENABLE | |
| 10132 | CURSOR_GAMMA_ENABLE | |
| 10133 | CURSOR_FORMAT_ARGB | |
| 10134 | CURSOR_STRIDE(stride); |
| 10135 | |
| 10136 | size = (height << 12) | width; |
| 10137 | } |
| 10138 | |
| 10139 | if (intel_crtc->cursor_cntl != 0 && |
| 10140 | (intel_crtc->cursor_base != base || |
| 10141 | intel_crtc->cursor_size != size || |
| 10142 | intel_crtc->cursor_cntl != cntl)) { |
| 10143 | /* On these chipsets we can only modify the base/size/stride |
| 10144 | * whilst the cursor is disabled. |
| 10145 | */ |
| 10146 | I915_WRITE(CURCNTR(PIPE_A), 0); |
| 10147 | POSTING_READ(CURCNTR(PIPE_A)); |
| 10148 | intel_crtc->cursor_cntl = 0; |
| 10149 | } |
| 10150 | |
| 10151 | if (intel_crtc->cursor_base != base) { |
| 10152 | I915_WRITE(CURBASE(PIPE_A), base); |
| 10153 | intel_crtc->cursor_base = base; |
| 10154 | } |
| 10155 | |
| 10156 | if (intel_crtc->cursor_size != size) { |
| 10157 | I915_WRITE(CURSIZE, size); |
| 10158 | intel_crtc->cursor_size = size; |
| 10159 | } |
| 10160 | |
| 10161 | if (intel_crtc->cursor_cntl != cntl) { |
| 10162 | I915_WRITE(CURCNTR(PIPE_A), cntl); |
| 10163 | POSTING_READ(CURCNTR(PIPE_A)); |
| 10164 | intel_crtc->cursor_cntl = cntl; |
| 10165 | } |
| 10166 | } |
| 10167 | |
| 10168 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, |
| 10169 | const struct intel_plane_state *plane_state) |
| 10170 | { |
| 10171 | struct drm_device *dev = crtc->dev; |
| 10172 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 10173 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 10174 | int pipe = intel_crtc->pipe; |
| 10175 | uint32_t cntl = 0; |
| 10176 | |
| 10177 | if (plane_state && plane_state->visible) { |
| 10178 | cntl = MCURSOR_GAMMA_ENABLE; |
| 10179 | switch (plane_state->base.crtc_w) { |
| 10180 | case 64: |
| 10181 | cntl |= CURSOR_MODE_64_ARGB_AX; |
| 10182 | break; |
| 10183 | case 128: |
| 10184 | cntl |= CURSOR_MODE_128_ARGB_AX; |
| 10185 | break; |
| 10186 | case 256: |
| 10187 | cntl |= CURSOR_MODE_256_ARGB_AX; |
| 10188 | break; |
| 10189 | default: |
| 10190 | MISSING_CASE(plane_state->base.crtc_w); |
| 10191 | return; |
| 10192 | } |
| 10193 | cntl |= pipe << 28; /* Connect to correct pipe */ |
| 10194 | |
| 10195 | if (HAS_DDI(dev)) |
| 10196 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
| 10197 | |
| 10198 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) |
| 10199 | cntl |= CURSOR_ROTATE_180; |
| 10200 | } |
| 10201 | |
| 10202 | if (intel_crtc->cursor_cntl != cntl) { |
| 10203 | I915_WRITE(CURCNTR(pipe), cntl); |
| 10204 | POSTING_READ(CURCNTR(pipe)); |
| 10205 | intel_crtc->cursor_cntl = cntl; |
| 10206 | } |
| 10207 | |
| 10208 | /* and commit changes on next vblank */ |
| 10209 | I915_WRITE(CURBASE(pipe), base); |
| 10210 | POSTING_READ(CURBASE(pipe)); |
| 10211 | |
| 10212 | intel_crtc->cursor_base = base; |
| 10213 | } |
| 10214 | |
| 10215 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
| 10216 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
| 10217 | const struct intel_plane_state *plane_state) |
| 10218 | { |
| 10219 | struct drm_device *dev = crtc->dev; |
| 10220 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 10221 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 10222 | int pipe = intel_crtc->pipe; |
| 10223 | u32 base = intel_crtc->cursor_addr; |
| 10224 | u32 pos = 0; |
| 10225 | |
| 10226 | if (plane_state) { |
| 10227 | int x = plane_state->base.crtc_x; |
| 10228 | int y = plane_state->base.crtc_y; |
| 10229 | |
| 10230 | if (x < 0) { |
| 10231 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; |
| 10232 | x = -x; |
| 10233 | } |
| 10234 | pos |= x << CURSOR_X_SHIFT; |
| 10235 | |
| 10236 | if (y < 0) { |
| 10237 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; |
| 10238 | y = -y; |
| 10239 | } |
| 10240 | pos |= y << CURSOR_Y_SHIFT; |
| 10241 | |
| 10242 | /* ILK+ do this automagically */ |
| 10243 | if (HAS_GMCH_DISPLAY(dev) && |
| 10244 | plane_state->base.rotation == BIT(DRM_ROTATE_180)) { |
| 10245 | base += (plane_state->base.crtc_h * |
| 10246 | plane_state->base.crtc_w - 1) * 4; |
| 10247 | } |
| 10248 | } |
| 10249 | |
| 10250 | I915_WRITE(CURPOS(pipe), pos); |
| 10251 | |
| 10252 | if (IS_845G(dev) || IS_I865G(dev)) |
| 10253 | i845_update_cursor(crtc, base, plane_state); |
| 10254 | else |
| 10255 | i9xx_update_cursor(crtc, base, plane_state); |
| 10256 | } |
| 10257 | |
| 10258 | static bool cursor_size_ok(struct drm_device *dev, |
| 10259 | uint32_t width, uint32_t height) |
| 10260 | { |
| 10261 | if (width == 0 || height == 0) |
| 10262 | return false; |
| 10263 | |
| 10264 | /* |
| 10265 | * 845g/865g are special in that they are only limited by |
| 10266 | * the width of their cursors, the height is arbitrary up to |
| 10267 | * the precision of the register. Everything else requires |
| 10268 | * square cursors, limited to a few power-of-two sizes. |
| 10269 | */ |
| 10270 | if (IS_845G(dev) || IS_I865G(dev)) { |
| 10271 | if ((width & 63) != 0) |
| 10272 | return false; |
| 10273 | |
| 10274 | if (width > (IS_845G(dev) ? 64 : 512)) |
| 10275 | return false; |
| 10276 | |
| 10277 | if (height > 1023) |
| 10278 | return false; |
| 10279 | } else { |
| 10280 | switch (width | height) { |
| 10281 | case 256: |
| 10282 | case 128: |
| 10283 | if (IS_GEN2(dev)) |
| 10284 | return false; |
| 10285 | case 64: |
| 10286 | break; |
| 10287 | default: |
| 10288 | return false; |
| 10289 | } |
| 10290 | } |
| 10291 | |
| 10292 | return true; |
| 10293 | } |
| 10294 | |
| 10295 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
| 10296 | u16 *blue, uint32_t start, uint32_t size) |
| 10297 | { |
| 10298 | int end = (start + size > 256) ? 256 : start + size, i; |
| 10299 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 10300 | |
| 10301 | for (i = start; i < end; i++) { |
| 10302 | intel_crtc->lut_r[i] = red[i] >> 8; |
| 10303 | intel_crtc->lut_g[i] = green[i] >> 8; |
| 10304 | intel_crtc->lut_b[i] = blue[i] >> 8; |
| 10305 | } |
| 10306 | |
| 10307 | intel_crtc_load_lut(crtc); |
| 10308 | } |
| 10309 | |
| 10310 | /* VESA 640x480x72Hz mode to set on the pipe */ |
| 10311 | static struct drm_display_mode load_detect_mode = { |
| 10312 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, |
| 10313 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
| 10314 | }; |
| 10315 | |
| 10316 | struct drm_framebuffer * |
| 10317 | __intel_framebuffer_create(struct drm_device *dev, |
| 10318 | struct drm_mode_fb_cmd2 *mode_cmd, |
| 10319 | struct drm_i915_gem_object *obj) |
| 10320 | { |
| 10321 | struct intel_framebuffer *intel_fb; |
| 10322 | int ret; |
| 10323 | |
| 10324 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
| 10325 | if (!intel_fb) |
| 10326 | return ERR_PTR(-ENOMEM); |
| 10327 | |
| 10328 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); |
| 10329 | if (ret) |
| 10330 | goto err; |
| 10331 | |
| 10332 | return &intel_fb->base; |
| 10333 | |
| 10334 | err: |
| 10335 | kfree(intel_fb); |
| 10336 | return ERR_PTR(ret); |
| 10337 | } |
| 10338 | |
| 10339 | static struct drm_framebuffer * |
| 10340 | intel_framebuffer_create(struct drm_device *dev, |
| 10341 | struct drm_mode_fb_cmd2 *mode_cmd, |
| 10342 | struct drm_i915_gem_object *obj) |
| 10343 | { |
| 10344 | struct drm_framebuffer *fb; |
| 10345 | int ret; |
| 10346 | |
| 10347 | ret = i915_mutex_lock_interruptible(dev); |
| 10348 | if (ret) |
| 10349 | return ERR_PTR(ret); |
| 10350 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); |
| 10351 | mutex_unlock(&dev->struct_mutex); |
| 10352 | |
| 10353 | return fb; |
| 10354 | } |
| 10355 | |
| 10356 | static u32 |
| 10357 | intel_framebuffer_pitch_for_width(int width, int bpp) |
| 10358 | { |
| 10359 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); |
| 10360 | return ALIGN(pitch, 64); |
| 10361 | } |
| 10362 | |
| 10363 | static u32 |
| 10364 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) |
| 10365 | { |
| 10366 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); |
| 10367 | return PAGE_ALIGN(pitch * mode->vdisplay); |
| 10368 | } |
| 10369 | |
| 10370 | static struct drm_framebuffer * |
| 10371 | intel_framebuffer_create_for_mode(struct drm_device *dev, |
| 10372 | struct drm_display_mode *mode, |
| 10373 | int depth, int bpp) |
| 10374 | { |
| 10375 | struct drm_framebuffer *fb; |
| 10376 | struct drm_i915_gem_object *obj; |
| 10377 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
| 10378 | |
| 10379 | obj = i915_gem_alloc_object(dev, |
| 10380 | intel_framebuffer_size_for_mode(mode, bpp)); |
| 10381 | if (obj == NULL) |
| 10382 | return ERR_PTR(-ENOMEM); |
| 10383 | |
| 10384 | mode_cmd.width = mode->hdisplay; |
| 10385 | mode_cmd.height = mode->vdisplay; |
| 10386 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
| 10387 | bpp); |
| 10388 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
| 10389 | |
| 10390 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
| 10391 | if (IS_ERR(fb)) |
| 10392 | drm_gem_object_unreference_unlocked(&obj->base); |
| 10393 | |
| 10394 | return fb; |
| 10395 | } |
| 10396 | |
| 10397 | static struct drm_framebuffer * |
| 10398 | mode_fits_in_fbdev(struct drm_device *dev, |
| 10399 | struct drm_display_mode *mode) |
| 10400 | { |
| 10401 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
| 10402 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 10403 | struct drm_i915_gem_object *obj; |
| 10404 | struct drm_framebuffer *fb; |
| 10405 | |
| 10406 | if (!dev_priv->fbdev) |
| 10407 | return NULL; |
| 10408 | |
| 10409 | if (!dev_priv->fbdev->fb) |
| 10410 | return NULL; |
| 10411 | |
| 10412 | obj = dev_priv->fbdev->fb->obj; |
| 10413 | BUG_ON(!obj); |
| 10414 | |
| 10415 | fb = &dev_priv->fbdev->fb->base; |
| 10416 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
| 10417 | fb->bits_per_pixel)) |
| 10418 | return NULL; |
| 10419 | |
| 10420 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
| 10421 | return NULL; |
| 10422 | |
| 10423 | return fb; |
| 10424 | #else |
| 10425 | return NULL; |
| 10426 | #endif |
| 10427 | } |
| 10428 | |
| 10429 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
| 10430 | struct drm_crtc *crtc, |
| 10431 | struct drm_display_mode *mode, |
| 10432 | struct drm_framebuffer *fb, |
| 10433 | int x, int y) |
| 10434 | { |
| 10435 | struct drm_plane_state *plane_state; |
| 10436 | int hdisplay, vdisplay; |
| 10437 | int ret; |
| 10438 | |
| 10439 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); |
| 10440 | if (IS_ERR(plane_state)) |
| 10441 | return PTR_ERR(plane_state); |
| 10442 | |
| 10443 | if (mode) |
| 10444 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); |
| 10445 | else |
| 10446 | hdisplay = vdisplay = 0; |
| 10447 | |
| 10448 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); |
| 10449 | if (ret) |
| 10450 | return ret; |
| 10451 | drm_atomic_set_fb_for_plane(plane_state, fb); |
| 10452 | plane_state->crtc_x = 0; |
| 10453 | plane_state->crtc_y = 0; |
| 10454 | plane_state->crtc_w = hdisplay; |
| 10455 | plane_state->crtc_h = vdisplay; |
| 10456 | plane_state->src_x = x << 16; |
| 10457 | plane_state->src_y = y << 16; |
| 10458 | plane_state->src_w = hdisplay << 16; |
| 10459 | plane_state->src_h = vdisplay << 16; |
| 10460 | |
| 10461 | return 0; |
| 10462 | } |
| 10463 | |
| 10464 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
| 10465 | struct drm_display_mode *mode, |
| 10466 | struct intel_load_detect_pipe *old, |
| 10467 | struct drm_modeset_acquire_ctx *ctx) |
| 10468 | { |
| 10469 | struct intel_crtc *intel_crtc; |
| 10470 | struct intel_encoder *intel_encoder = |
| 10471 | intel_attached_encoder(connector); |
| 10472 | struct drm_crtc *possible_crtc; |
| 10473 | struct drm_encoder *encoder = &intel_encoder->base; |
| 10474 | struct drm_crtc *crtc = NULL; |
| 10475 | struct drm_device *dev = encoder->dev; |
| 10476 | struct drm_framebuffer *fb; |
| 10477 | struct drm_mode_config *config = &dev->mode_config; |
| 10478 | struct drm_atomic_state *state = NULL; |
| 10479 | struct drm_connector_state *connector_state; |
| 10480 | struct intel_crtc_state *crtc_state; |
| 10481 | int ret, i = -1; |
| 10482 | |
| 10483 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
| 10484 | connector->base.id, connector->name, |
| 10485 | encoder->base.id, encoder->name); |
| 10486 | |
| 10487 | retry: |
| 10488 | ret = drm_modeset_lock(&config->connection_mutex, ctx); |
| 10489 | if (ret) |
| 10490 | goto fail; |
| 10491 | |
| 10492 | /* |
| 10493 | * Algorithm gets a little messy: |
| 10494 | * |
| 10495 | * - if the connector already has an assigned crtc, use it (but make |
| 10496 | * sure it's on first) |
| 10497 | * |
| 10498 | * - try to find the first unused crtc that can drive this connector, |
| 10499 | * and use that if we find one |
| 10500 | */ |
| 10501 | |
| 10502 | /* See if we already have a CRTC for this connector */ |
| 10503 | if (encoder->crtc) { |
| 10504 | crtc = encoder->crtc; |
| 10505 | |
| 10506 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
| 10507 | if (ret) |
| 10508 | goto fail; |
| 10509 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
| 10510 | if (ret) |
| 10511 | goto fail; |
| 10512 | |
| 10513 | old->dpms_mode = connector->dpms; |
| 10514 | old->load_detect_temp = false; |
| 10515 | |
| 10516 | /* Make sure the crtc and connector are running */ |
| 10517 | if (connector->dpms != DRM_MODE_DPMS_ON) |
| 10518 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); |
| 10519 | |
| 10520 | return true; |
| 10521 | } |
| 10522 | |
| 10523 | /* Find an unused one (if possible) */ |
| 10524 | for_each_crtc(dev, possible_crtc) { |
| 10525 | i++; |
| 10526 | if (!(encoder->possible_crtcs & (1 << i))) |
| 10527 | continue; |
| 10528 | if (possible_crtc->state->enable) |
| 10529 | continue; |
| 10530 | |
| 10531 | crtc = possible_crtc; |
| 10532 | break; |
| 10533 | } |
| 10534 | |
| 10535 | /* |
| 10536 | * If we didn't find an unused CRTC, don't use any. |
| 10537 | */ |
| 10538 | if (!crtc) { |
| 10539 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
| 10540 | goto fail; |
| 10541 | } |
| 10542 | |
| 10543 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
| 10544 | if (ret) |
| 10545 | goto fail; |
| 10546 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
| 10547 | if (ret) |
| 10548 | goto fail; |
| 10549 | |
| 10550 | intel_crtc = to_intel_crtc(crtc); |
| 10551 | old->dpms_mode = connector->dpms; |
| 10552 | old->load_detect_temp = true; |
| 10553 | old->release_fb = NULL; |
| 10554 | |
| 10555 | state = drm_atomic_state_alloc(dev); |
| 10556 | if (!state) |
| 10557 | return false; |
| 10558 | |
| 10559 | state->acquire_ctx = ctx; |
| 10560 | |
| 10561 | connector_state = drm_atomic_get_connector_state(state, connector); |
| 10562 | if (IS_ERR(connector_state)) { |
| 10563 | ret = PTR_ERR(connector_state); |
| 10564 | goto fail; |
| 10565 | } |
| 10566 | |
| 10567 | connector_state->crtc = crtc; |
| 10568 | connector_state->best_encoder = &intel_encoder->base; |
| 10569 | |
| 10570 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
| 10571 | if (IS_ERR(crtc_state)) { |
| 10572 | ret = PTR_ERR(crtc_state); |
| 10573 | goto fail; |
| 10574 | } |
| 10575 | |
| 10576 | crtc_state->base.active = crtc_state->base.enable = true; |
| 10577 | |
| 10578 | if (!mode) |
| 10579 | mode = &load_detect_mode; |
| 10580 | |
| 10581 | /* We need a framebuffer large enough to accommodate all accesses |
| 10582 | * that the plane may generate whilst we perform load detection. |
| 10583 | * We can not rely on the fbcon either being present (we get called |
| 10584 | * during its initialisation to detect all boot displays, or it may |
| 10585 | * not even exist) or that it is large enough to satisfy the |
| 10586 | * requested mode. |
| 10587 | */ |
| 10588 | fb = mode_fits_in_fbdev(dev, mode); |
| 10589 | if (fb == NULL) { |
| 10590 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
| 10591 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
| 10592 | old->release_fb = fb; |
| 10593 | } else |
| 10594 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); |
| 10595 | if (IS_ERR(fb)) { |
| 10596 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
| 10597 | goto fail; |
| 10598 | } |
| 10599 | |
| 10600 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
| 10601 | if (ret) |
| 10602 | goto fail; |
| 10603 | |
| 10604 | drm_mode_copy(&crtc_state->base.mode, mode); |
| 10605 | |
| 10606 | if (drm_atomic_commit(state)) { |
| 10607 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
| 10608 | if (old->release_fb) |
| 10609 | old->release_fb->funcs->destroy(old->release_fb); |
| 10610 | goto fail; |
| 10611 | } |
| 10612 | crtc->primary->crtc = crtc; |
| 10613 | |
| 10614 | /* let the connector get through one full cycle before testing */ |
| 10615 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
| 10616 | return true; |
| 10617 | |
| 10618 | fail: |
| 10619 | drm_atomic_state_free(state); |
| 10620 | state = NULL; |
| 10621 | |
| 10622 | if (ret == -EDEADLK) { |
| 10623 | drm_modeset_backoff(ctx); |
| 10624 | goto retry; |
| 10625 | } |
| 10626 | |
| 10627 | return false; |
| 10628 | } |
| 10629 | |
| 10630 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
| 10631 | struct intel_load_detect_pipe *old, |
| 10632 | struct drm_modeset_acquire_ctx *ctx) |
| 10633 | { |
| 10634 | struct drm_device *dev = connector->dev; |
| 10635 | struct intel_encoder *intel_encoder = |
| 10636 | intel_attached_encoder(connector); |
| 10637 | struct drm_encoder *encoder = &intel_encoder->base; |
| 10638 | struct drm_crtc *crtc = encoder->crtc; |
| 10639 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 10640 | struct drm_atomic_state *state; |
| 10641 | struct drm_connector_state *connector_state; |
| 10642 | struct intel_crtc_state *crtc_state; |
| 10643 | int ret; |
| 10644 | |
| 10645 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
| 10646 | connector->base.id, connector->name, |
| 10647 | encoder->base.id, encoder->name); |
| 10648 | |
| 10649 | if (old->load_detect_temp) { |
| 10650 | state = drm_atomic_state_alloc(dev); |
| 10651 | if (!state) |
| 10652 | goto fail; |
| 10653 | |
| 10654 | state->acquire_ctx = ctx; |
| 10655 | |
| 10656 | connector_state = drm_atomic_get_connector_state(state, connector); |
| 10657 | if (IS_ERR(connector_state)) |
| 10658 | goto fail; |
| 10659 | |
| 10660 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
| 10661 | if (IS_ERR(crtc_state)) |
| 10662 | goto fail; |
| 10663 | |
| 10664 | connector_state->best_encoder = NULL; |
| 10665 | connector_state->crtc = NULL; |
| 10666 | |
| 10667 | crtc_state->base.enable = crtc_state->base.active = false; |
| 10668 | |
| 10669 | ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL, |
| 10670 | 0, 0); |
| 10671 | if (ret) |
| 10672 | goto fail; |
| 10673 | |
| 10674 | ret = drm_atomic_commit(state); |
| 10675 | if (ret) |
| 10676 | goto fail; |
| 10677 | |
| 10678 | if (old->release_fb) { |
| 10679 | drm_framebuffer_unregister_private(old->release_fb); |
| 10680 | drm_framebuffer_unreference(old->release_fb); |
| 10681 | } |
| 10682 | |
| 10683 | return; |
| 10684 | } |
| 10685 | |
| 10686 | /* Switch crtc and encoder back off if necessary */ |
| 10687 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
| 10688 | connector->funcs->dpms(connector, old->dpms_mode); |
| 10689 | |
| 10690 | return; |
| 10691 | fail: |
| 10692 | DRM_DEBUG_KMS("Couldn't release load detect pipe.\n"); |
| 10693 | drm_atomic_state_free(state); |
| 10694 | } |
| 10695 | |
| 10696 | static int i9xx_pll_refclk(struct drm_device *dev, |
| 10697 | const struct intel_crtc_state *pipe_config) |
| 10698 | { |
| 10699 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 10700 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
| 10701 | |
| 10702 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) |
| 10703 | return dev_priv->vbt.lvds_ssc_freq; |
| 10704 | else if (HAS_PCH_SPLIT(dev)) |
| 10705 | return 120000; |
| 10706 | else if (!IS_GEN2(dev)) |
| 10707 | return 96000; |
| 10708 | else |
| 10709 | return 48000; |
| 10710 | } |
| 10711 | |
| 10712 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
| 10713 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
| 10714 | struct intel_crtc_state *pipe_config) |
| 10715 | { |
| 10716 | struct drm_device *dev = crtc->base.dev; |
| 10717 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 10718 | int pipe = pipe_config->cpu_transcoder; |
| 10719 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
| 10720 | u32 fp; |
| 10721 | intel_clock_t clock; |
| 10722 | int port_clock; |
| 10723 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
| 10724 | |
| 10725 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) |
| 10726 | fp = pipe_config->dpll_hw_state.fp0; |
| 10727 | else |
| 10728 | fp = pipe_config->dpll_hw_state.fp1; |
| 10729 | |
| 10730 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; |
| 10731 | if (IS_PINEVIEW(dev)) { |
| 10732 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; |
| 10733 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; |
| 10734 | } else { |
| 10735 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; |
| 10736 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; |
| 10737 | } |
| 10738 | |
| 10739 | if (!IS_GEN2(dev)) { |
| 10740 | if (IS_PINEVIEW(dev)) |
| 10741 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> |
| 10742 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); |
| 10743 | else |
| 10744 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> |
| 10745 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
| 10746 | |
| 10747 | switch (dpll & DPLL_MODE_MASK) { |
| 10748 | case DPLLB_MODE_DAC_SERIAL: |
| 10749 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? |
| 10750 | 5 : 10; |
| 10751 | break; |
| 10752 | case DPLLB_MODE_LVDS: |
| 10753 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? |
| 10754 | 7 : 14; |
| 10755 | break; |
| 10756 | default: |
| 10757 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
| 10758 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
| 10759 | return; |
| 10760 | } |
| 10761 | |
| 10762 | if (IS_PINEVIEW(dev)) |
| 10763 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
| 10764 | else |
| 10765 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
| 10766 | } else { |
| 10767 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
| 10768 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
| 10769 | |
| 10770 | if (is_lvds) { |
| 10771 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> |
| 10772 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
| 10773 | |
| 10774 | if (lvds & LVDS_CLKB_POWER_UP) |
| 10775 | clock.p2 = 7; |
| 10776 | else |
| 10777 | clock.p2 = 14; |
| 10778 | } else { |
| 10779 | if (dpll & PLL_P1_DIVIDE_BY_TWO) |
| 10780 | clock.p1 = 2; |
| 10781 | else { |
| 10782 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> |
| 10783 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; |
| 10784 | } |
| 10785 | if (dpll & PLL_P2_DIVIDE_BY_4) |
| 10786 | clock.p2 = 4; |
| 10787 | else |
| 10788 | clock.p2 = 2; |
| 10789 | } |
| 10790 | |
| 10791 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
| 10792 | } |
| 10793 | |
| 10794 | /* |
| 10795 | * This value includes pixel_multiplier. We will use |
| 10796 | * port_clock to compute adjusted_mode.crtc_clock in the |
| 10797 | * encoder's get_config() function. |
| 10798 | */ |
| 10799 | pipe_config->port_clock = port_clock; |
| 10800 | } |
| 10801 | |
| 10802 | int intel_dotclock_calculate(int link_freq, |
| 10803 | const struct intel_link_m_n *m_n) |
| 10804 | { |
| 10805 | /* |
| 10806 | * The calculation for the data clock is: |
| 10807 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
| 10808 | * But we want to avoid losing precison if possible, so: |
| 10809 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
| 10810 | * |
| 10811 | * and the link clock is simpler: |
| 10812 | * link_clock = (m * link_clock) / n |
| 10813 | */ |
| 10814 | |
| 10815 | if (!m_n->link_n) |
| 10816 | return 0; |
| 10817 | |
| 10818 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
| 10819 | } |
| 10820 | |
| 10821 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
| 10822 | struct intel_crtc_state *pipe_config) |
| 10823 | { |
| 10824 | struct drm_device *dev = crtc->base.dev; |
| 10825 | |
| 10826 | /* read out port_clock from the DPLL */ |
| 10827 | i9xx_crtc_clock_get(crtc, pipe_config); |
| 10828 | |
| 10829 | /* |
| 10830 | * This value does not include pixel_multiplier. |
| 10831 | * We will check that port_clock and adjusted_mode.crtc_clock |
| 10832 | * agree once we know their relationship in the encoder's |
| 10833 | * get_config() function. |
| 10834 | */ |
| 10835 | pipe_config->base.adjusted_mode.crtc_clock = |
| 10836 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
| 10837 | &pipe_config->fdi_m_n); |
| 10838 | } |
| 10839 | |
| 10840 | /** Returns the currently programmed mode of the given pipe. */ |
| 10841 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, |
| 10842 | struct drm_crtc *crtc) |
| 10843 | { |
| 10844 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 10845 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 10846 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
| 10847 | struct drm_display_mode *mode; |
| 10848 | struct intel_crtc_state pipe_config; |
| 10849 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
| 10850 | int hsync = I915_READ(HSYNC(cpu_transcoder)); |
| 10851 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); |
| 10852 | int vsync = I915_READ(VSYNC(cpu_transcoder)); |
| 10853 | enum pipe pipe = intel_crtc->pipe; |
| 10854 | |
| 10855 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); |
| 10856 | if (!mode) |
| 10857 | return NULL; |
| 10858 | |
| 10859 | /* |
| 10860 | * Construct a pipe_config sufficient for getting the clock info |
| 10861 | * back out of crtc_clock_get. |
| 10862 | * |
| 10863 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need |
| 10864 | * to use a real value here instead. |
| 10865 | */ |
| 10866 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
| 10867 | pipe_config.pixel_multiplier = 1; |
| 10868 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
| 10869 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); |
| 10870 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); |
| 10871 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
| 10872 | |
| 10873 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
| 10874 | mode->hdisplay = (htot & 0xffff) + 1; |
| 10875 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; |
| 10876 | mode->hsync_start = (hsync & 0xffff) + 1; |
| 10877 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; |
| 10878 | mode->vdisplay = (vtot & 0xffff) + 1; |
| 10879 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; |
| 10880 | mode->vsync_start = (vsync & 0xffff) + 1; |
| 10881 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; |
| 10882 | |
| 10883 | drm_mode_set_name(mode); |
| 10884 | |
| 10885 | return mode; |
| 10886 | } |
| 10887 | |
| 10888 | void intel_mark_busy(struct drm_device *dev) |
| 10889 | { |
| 10890 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 10891 | |
| 10892 | if (dev_priv->mm.busy) |
| 10893 | return; |
| 10894 | |
| 10895 | intel_runtime_pm_get(dev_priv); |
| 10896 | i915_update_gfx_val(dev_priv); |
| 10897 | if (INTEL_INFO(dev)->gen >= 6) |
| 10898 | gen6_rps_busy(dev_priv); |
| 10899 | dev_priv->mm.busy = true; |
| 10900 | } |
| 10901 | |
| 10902 | void intel_mark_idle(struct drm_device *dev) |
| 10903 | { |
| 10904 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 10905 | |
| 10906 | if (!dev_priv->mm.busy) |
| 10907 | return; |
| 10908 | |
| 10909 | dev_priv->mm.busy = false; |
| 10910 | |
| 10911 | if (INTEL_INFO(dev)->gen >= 6) |
| 10912 | gen6_rps_idle(dev->dev_private); |
| 10913 | |
| 10914 | intel_runtime_pm_put(dev_priv); |
| 10915 | } |
| 10916 | |
| 10917 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
| 10918 | { |
| 10919 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 10920 | struct drm_device *dev = crtc->dev; |
| 10921 | struct intel_unpin_work *work; |
| 10922 | |
| 10923 | spin_lock_irq(&dev->event_lock); |
| 10924 | work = intel_crtc->unpin_work; |
| 10925 | intel_crtc->unpin_work = NULL; |
| 10926 | spin_unlock_irq(&dev->event_lock); |
| 10927 | |
| 10928 | if (work) { |
| 10929 | cancel_work_sync(&work->work); |
| 10930 | kfree(work); |
| 10931 | } |
| 10932 | |
| 10933 | drm_crtc_cleanup(crtc); |
| 10934 | |
| 10935 | kfree(intel_crtc); |
| 10936 | } |
| 10937 | |
| 10938 | static void intel_unpin_work_fn(struct work_struct *__work) |
| 10939 | { |
| 10940 | struct intel_unpin_work *work = |
| 10941 | container_of(__work, struct intel_unpin_work, work); |
| 10942 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
| 10943 | struct drm_device *dev = crtc->base.dev; |
| 10944 | struct drm_plane *primary = crtc->base.primary; |
| 10945 | |
| 10946 | mutex_lock(&dev->struct_mutex); |
| 10947 | intel_unpin_fb_obj(work->old_fb, primary->state); |
| 10948 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
| 10949 | |
| 10950 | if (work->flip_queued_req) |
| 10951 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
| 10952 | mutex_unlock(&dev->struct_mutex); |
| 10953 | |
| 10954 | intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit); |
| 10955 | drm_framebuffer_unreference(work->old_fb); |
| 10956 | |
| 10957 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
| 10958 | atomic_dec(&crtc->unpin_work_count); |
| 10959 | |
| 10960 | kfree(work); |
| 10961 | } |
| 10962 | |
| 10963 | static void do_intel_finish_page_flip(struct drm_device *dev, |
| 10964 | struct drm_crtc *crtc) |
| 10965 | { |
| 10966 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 10967 | struct intel_unpin_work *work; |
| 10968 | unsigned long flags; |
| 10969 | |
| 10970 | /* Ignore early vblank irqs */ |
| 10971 | if (intel_crtc == NULL) |
| 10972 | return; |
| 10973 | |
| 10974 | /* |
| 10975 | * This is called both by irq handlers and the reset code (to complete |
| 10976 | * lost pageflips) so needs the full irqsave spinlocks. |
| 10977 | */ |
| 10978 | spin_lock_irqsave(&dev->event_lock, flags); |
| 10979 | work = intel_crtc->unpin_work; |
| 10980 | |
| 10981 | /* Ensure we don't miss a work->pending update ... */ |
| 10982 | smp_rmb(); |
| 10983 | |
| 10984 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
| 10985 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 10986 | return; |
| 10987 | } |
| 10988 | |
| 10989 | page_flip_completed(intel_crtc); |
| 10990 | |
| 10991 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 10992 | } |
| 10993 | |
| 10994 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
| 10995 | { |
| 10996 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 10997 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 10998 | |
| 10999 | do_intel_finish_page_flip(dev, crtc); |
| 11000 | } |
| 11001 | |
| 11002 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) |
| 11003 | { |
| 11004 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 11005 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
| 11006 | |
| 11007 | do_intel_finish_page_flip(dev, crtc); |
| 11008 | } |
| 11009 | |
| 11010 | /* Is 'a' after or equal to 'b'? */ |
| 11011 | static bool g4x_flip_count_after_eq(u32 a, u32 b) |
| 11012 | { |
| 11013 | return !((a - b) & 0x80000000); |
| 11014 | } |
| 11015 | |
| 11016 | static bool page_flip_finished(struct intel_crtc *crtc) |
| 11017 | { |
| 11018 | struct drm_device *dev = crtc->base.dev; |
| 11019 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 11020 | |
| 11021 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
| 11022 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) |
| 11023 | return true; |
| 11024 | |
| 11025 | /* |
| 11026 | * The relevant registers doen't exist on pre-ctg. |
| 11027 | * As the flip done interrupt doesn't trigger for mmio |
| 11028 | * flips on gmch platforms, a flip count check isn't |
| 11029 | * really needed there. But since ctg has the registers, |
| 11030 | * include it in the check anyway. |
| 11031 | */ |
| 11032 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) |
| 11033 | return true; |
| 11034 | |
| 11035 | /* |
| 11036 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips |
| 11037 | * used the same base address. In that case the mmio flip might |
| 11038 | * have completed, but the CS hasn't even executed the flip yet. |
| 11039 | * |
| 11040 | * A flip count check isn't enough as the CS might have updated |
| 11041 | * the base address just after start of vblank, but before we |
| 11042 | * managed to process the interrupt. This means we'd complete the |
| 11043 | * CS flip too soon. |
| 11044 | * |
| 11045 | * Combining both checks should get us a good enough result. It may |
| 11046 | * still happen that the CS flip has been executed, but has not |
| 11047 | * yet actually completed. But in case the base address is the same |
| 11048 | * anyway, we don't really care. |
| 11049 | */ |
| 11050 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == |
| 11051 | crtc->unpin_work->gtt_offset && |
| 11052 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), |
| 11053 | crtc->unpin_work->flip_count); |
| 11054 | } |
| 11055 | |
| 11056 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
| 11057 | { |
| 11058 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 11059 | struct intel_crtc *intel_crtc = |
| 11060 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); |
| 11061 | unsigned long flags; |
| 11062 | |
| 11063 | |
| 11064 | /* |
| 11065 | * This is called both by irq handlers and the reset code (to complete |
| 11066 | * lost pageflips) so needs the full irqsave spinlocks. |
| 11067 | * |
| 11068 | * NB: An MMIO update of the plane base pointer will also |
| 11069 | * generate a page-flip completion irq, i.e. every modeset |
| 11070 | * is also accompanied by a spurious intel_prepare_page_flip(). |
| 11071 | */ |
| 11072 | spin_lock_irqsave(&dev->event_lock, flags); |
| 11073 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
| 11074 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
| 11075 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 11076 | } |
| 11077 | |
| 11078 | static inline void intel_mark_page_flip_active(struct intel_unpin_work *work) |
| 11079 | { |
| 11080 | /* Ensure that the work item is consistent when activating it ... */ |
| 11081 | smp_wmb(); |
| 11082 | atomic_set(&work->pending, INTEL_FLIP_PENDING); |
| 11083 | /* and that it is marked active as soon as the irq could fire. */ |
| 11084 | smp_wmb(); |
| 11085 | } |
| 11086 | |
| 11087 | static int intel_gen2_queue_flip(struct drm_device *dev, |
| 11088 | struct drm_crtc *crtc, |
| 11089 | struct drm_framebuffer *fb, |
| 11090 | struct drm_i915_gem_object *obj, |
| 11091 | struct drm_i915_gem_request *req, |
| 11092 | uint32_t flags) |
| 11093 | { |
| 11094 | struct intel_engine_cs *ring = req->ring; |
| 11095 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 11096 | u32 flip_mask; |
| 11097 | int ret; |
| 11098 | |
| 11099 | ret = intel_ring_begin(req, 6); |
| 11100 | if (ret) |
| 11101 | return ret; |
| 11102 | |
| 11103 | /* Can't queue multiple flips, so wait for the previous |
| 11104 | * one to finish before executing the next. |
| 11105 | */ |
| 11106 | if (intel_crtc->plane) |
| 11107 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
| 11108 | else |
| 11109 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
| 11110 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
| 11111 | intel_ring_emit(ring, MI_NOOP); |
| 11112 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
| 11113 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
| 11114 | intel_ring_emit(ring, fb->pitches[0]); |
| 11115 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
| 11116 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
| 11117 | |
| 11118 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
| 11119 | return 0; |
| 11120 | } |
| 11121 | |
| 11122 | static int intel_gen3_queue_flip(struct drm_device *dev, |
| 11123 | struct drm_crtc *crtc, |
| 11124 | struct drm_framebuffer *fb, |
| 11125 | struct drm_i915_gem_object *obj, |
| 11126 | struct drm_i915_gem_request *req, |
| 11127 | uint32_t flags) |
| 11128 | { |
| 11129 | struct intel_engine_cs *ring = req->ring; |
| 11130 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 11131 | u32 flip_mask; |
| 11132 | int ret; |
| 11133 | |
| 11134 | ret = intel_ring_begin(req, 6); |
| 11135 | if (ret) |
| 11136 | return ret; |
| 11137 | |
| 11138 | if (intel_crtc->plane) |
| 11139 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
| 11140 | else |
| 11141 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
| 11142 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
| 11143 | intel_ring_emit(ring, MI_NOOP); |
| 11144 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | |
| 11145 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
| 11146 | intel_ring_emit(ring, fb->pitches[0]); |
| 11147 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
| 11148 | intel_ring_emit(ring, MI_NOOP); |
| 11149 | |
| 11150 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
| 11151 | return 0; |
| 11152 | } |
| 11153 | |
| 11154 | static int intel_gen4_queue_flip(struct drm_device *dev, |
| 11155 | struct drm_crtc *crtc, |
| 11156 | struct drm_framebuffer *fb, |
| 11157 | struct drm_i915_gem_object *obj, |
| 11158 | struct drm_i915_gem_request *req, |
| 11159 | uint32_t flags) |
| 11160 | { |
| 11161 | struct intel_engine_cs *ring = req->ring; |
| 11162 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 11163 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 11164 | uint32_t pf, pipesrc; |
| 11165 | int ret; |
| 11166 | |
| 11167 | ret = intel_ring_begin(req, 4); |
| 11168 | if (ret) |
| 11169 | return ret; |
| 11170 | |
| 11171 | /* i965+ uses the linear or tiled offsets from the |
| 11172 | * Display Registers (which do not change across a page-flip) |
| 11173 | * so we need only reprogram the base address. |
| 11174 | */ |
| 11175 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
| 11176 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
| 11177 | intel_ring_emit(ring, fb->pitches[0]); |
| 11178 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
| 11179 | obj->tiling_mode); |
| 11180 | |
| 11181 | /* XXX Enabling the panel-fitter across page-flip is so far |
| 11182 | * untested on non-native modes, so ignore it for now. |
| 11183 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; |
| 11184 | */ |
| 11185 | pf = 0; |
| 11186 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
| 11187 | intel_ring_emit(ring, pf | pipesrc); |
| 11188 | |
| 11189 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
| 11190 | return 0; |
| 11191 | } |
| 11192 | |
| 11193 | static int intel_gen6_queue_flip(struct drm_device *dev, |
| 11194 | struct drm_crtc *crtc, |
| 11195 | struct drm_framebuffer *fb, |
| 11196 | struct drm_i915_gem_object *obj, |
| 11197 | struct drm_i915_gem_request *req, |
| 11198 | uint32_t flags) |
| 11199 | { |
| 11200 | struct intel_engine_cs *ring = req->ring; |
| 11201 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 11202 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 11203 | uint32_t pf, pipesrc; |
| 11204 | int ret; |
| 11205 | |
| 11206 | ret = intel_ring_begin(req, 4); |
| 11207 | if (ret) |
| 11208 | return ret; |
| 11209 | |
| 11210 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
| 11211 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
| 11212 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); |
| 11213 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
| 11214 | |
| 11215 | /* Contrary to the suggestions in the documentation, |
| 11216 | * "Enable Panel Fitter" does not seem to be required when page |
| 11217 | * flipping with a non-native mode, and worse causes a normal |
| 11218 | * modeset to fail. |
| 11219 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; |
| 11220 | */ |
| 11221 | pf = 0; |
| 11222 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
| 11223 | intel_ring_emit(ring, pf | pipesrc); |
| 11224 | |
| 11225 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
| 11226 | return 0; |
| 11227 | } |
| 11228 | |
| 11229 | static int intel_gen7_queue_flip(struct drm_device *dev, |
| 11230 | struct drm_crtc *crtc, |
| 11231 | struct drm_framebuffer *fb, |
| 11232 | struct drm_i915_gem_object *obj, |
| 11233 | struct drm_i915_gem_request *req, |
| 11234 | uint32_t flags) |
| 11235 | { |
| 11236 | struct intel_engine_cs *ring = req->ring; |
| 11237 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 11238 | uint32_t plane_bit = 0; |
| 11239 | int len, ret; |
| 11240 | |
| 11241 | switch (intel_crtc->plane) { |
| 11242 | case PLANE_A: |
| 11243 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; |
| 11244 | break; |
| 11245 | case PLANE_B: |
| 11246 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; |
| 11247 | break; |
| 11248 | case PLANE_C: |
| 11249 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; |
| 11250 | break; |
| 11251 | default: |
| 11252 | WARN_ONCE(1, "unknown plane in flip command\n"); |
| 11253 | return -ENODEV; |
| 11254 | } |
| 11255 | |
| 11256 | len = 4; |
| 11257 | if (ring->id == RCS) { |
| 11258 | len += 6; |
| 11259 | /* |
| 11260 | * On Gen 8, SRM is now taking an extra dword to accommodate |
| 11261 | * 48bits addresses, and we need a NOOP for the batch size to |
| 11262 | * stay even. |
| 11263 | */ |
| 11264 | if (IS_GEN8(dev)) |
| 11265 | len += 2; |
| 11266 | } |
| 11267 | |
| 11268 | /* |
| 11269 | * BSpec MI_DISPLAY_FLIP for IVB: |
| 11270 | * "The full packet must be contained within the same cache line." |
| 11271 | * |
| 11272 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same |
| 11273 | * cacheline, if we ever start emitting more commands before |
| 11274 | * the MI_DISPLAY_FLIP we may need to first emit everything else, |
| 11275 | * then do the cacheline alignment, and finally emit the |
| 11276 | * MI_DISPLAY_FLIP. |
| 11277 | */ |
| 11278 | ret = intel_ring_cacheline_align(req); |
| 11279 | if (ret) |
| 11280 | return ret; |
| 11281 | |
| 11282 | ret = intel_ring_begin(req, len); |
| 11283 | if (ret) |
| 11284 | return ret; |
| 11285 | |
| 11286 | /* Unmask the flip-done completion message. Note that the bspec says that |
| 11287 | * we should do this for both the BCS and RCS, and that we must not unmask |
| 11288 | * more than one flip event at any time (or ensure that one flip message |
| 11289 | * can be sent by waiting for flip-done prior to queueing new flips). |
| 11290 | * Experimentation says that BCS works despite DERRMR masking all |
| 11291 | * flip-done completion events and that unmasking all planes at once |
| 11292 | * for the RCS also doesn't appear to drop events. Setting the DERRMR |
| 11293 | * to zero does lead to lockups within MI_DISPLAY_FLIP. |
| 11294 | */ |
| 11295 | if (ring->id == RCS) { |
| 11296 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
| 11297 | intel_ring_emit_reg(ring, DERRMR); |
| 11298 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | |
| 11299 | DERRMR_PIPEB_PRI_FLIP_DONE | |
| 11300 | DERRMR_PIPEC_PRI_FLIP_DONE)); |
| 11301 | if (IS_GEN8(dev)) |
| 11302 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 | |
| 11303 | MI_SRM_LRM_GLOBAL_GTT); |
| 11304 | else |
| 11305 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM | |
| 11306 | MI_SRM_LRM_GLOBAL_GTT); |
| 11307 | intel_ring_emit_reg(ring, DERRMR); |
| 11308 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); |
| 11309 | if (IS_GEN8(dev)) { |
| 11310 | intel_ring_emit(ring, 0); |
| 11311 | intel_ring_emit(ring, MI_NOOP); |
| 11312 | } |
| 11313 | } |
| 11314 | |
| 11315 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
| 11316 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
| 11317 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
| 11318 | intel_ring_emit(ring, (MI_NOOP)); |
| 11319 | |
| 11320 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
| 11321 | return 0; |
| 11322 | } |
| 11323 | |
| 11324 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
| 11325 | struct drm_i915_gem_object *obj) |
| 11326 | { |
| 11327 | /* |
| 11328 | * This is not being used for older platforms, because |
| 11329 | * non-availability of flip done interrupt forces us to use |
| 11330 | * CS flips. Older platforms derive flip done using some clever |
| 11331 | * tricks involving the flip_pending status bits and vblank irqs. |
| 11332 | * So using MMIO flips there would disrupt this mechanism. |
| 11333 | */ |
| 11334 | |
| 11335 | if (ring == NULL) |
| 11336 | return true; |
| 11337 | |
| 11338 | if (INTEL_INFO(ring->dev)->gen < 5) |
| 11339 | return false; |
| 11340 | |
| 11341 | if (i915.use_mmio_flip < 0) |
| 11342 | return false; |
| 11343 | else if (i915.use_mmio_flip > 0) |
| 11344 | return true; |
| 11345 | else if (i915.enable_execlists) |
| 11346 | return true; |
| 11347 | else if (obj->base.dma_buf && |
| 11348 | !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv, |
| 11349 | false)) |
| 11350 | return true; |
| 11351 | else |
| 11352 | return ring != i915_gem_request_get_ring(obj->last_write_req); |
| 11353 | } |
| 11354 | |
| 11355 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, |
| 11356 | unsigned int rotation, |
| 11357 | struct intel_unpin_work *work) |
| 11358 | { |
| 11359 | struct drm_device *dev = intel_crtc->base.dev; |
| 11360 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 11361 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; |
| 11362 | const enum pipe pipe = intel_crtc->pipe; |
| 11363 | u32 ctl, stride, tile_height; |
| 11364 | |
| 11365 | ctl = I915_READ(PLANE_CTL(pipe, 0)); |
| 11366 | ctl &= ~PLANE_CTL_TILED_MASK; |
| 11367 | switch (fb->modifier[0]) { |
| 11368 | case DRM_FORMAT_MOD_NONE: |
| 11369 | break; |
| 11370 | case I915_FORMAT_MOD_X_TILED: |
| 11371 | ctl |= PLANE_CTL_TILED_X; |
| 11372 | break; |
| 11373 | case I915_FORMAT_MOD_Y_TILED: |
| 11374 | ctl |= PLANE_CTL_TILED_Y; |
| 11375 | break; |
| 11376 | case I915_FORMAT_MOD_Yf_TILED: |
| 11377 | ctl |= PLANE_CTL_TILED_YF; |
| 11378 | break; |
| 11379 | default: |
| 11380 | MISSING_CASE(fb->modifier[0]); |
| 11381 | } |
| 11382 | |
| 11383 | /* |
| 11384 | * The stride is either expressed as a multiple of 64 bytes chunks for |
| 11385 | * linear buffers or in number of tiles for tiled buffers. |
| 11386 | */ |
| 11387 | if (intel_rotation_90_or_270(rotation)) { |
| 11388 | /* stride = Surface height in tiles */ |
| 11389 | tile_height = intel_tile_height(dev, fb->pixel_format, |
| 11390 | fb->modifier[0], 0); |
| 11391 | stride = DIV_ROUND_UP(fb->height, tile_height); |
| 11392 | } else { |
| 11393 | stride = fb->pitches[0] / |
| 11394 | intel_fb_stride_alignment(dev, fb->modifier[0], |
| 11395 | fb->pixel_format); |
| 11396 | } |
| 11397 | |
| 11398 | /* |
| 11399 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on |
| 11400 | * PLANE_SURF updates, the update is then guaranteed to be atomic. |
| 11401 | */ |
| 11402 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); |
| 11403 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); |
| 11404 | |
| 11405 | I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); |
| 11406 | POSTING_READ(PLANE_SURF(pipe, 0)); |
| 11407 | } |
| 11408 | |
| 11409 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, |
| 11410 | struct intel_unpin_work *work) |
| 11411 | { |
| 11412 | struct drm_device *dev = intel_crtc->base.dev; |
| 11413 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 11414 | struct intel_framebuffer *intel_fb = |
| 11415 | to_intel_framebuffer(intel_crtc->base.primary->fb); |
| 11416 | struct drm_i915_gem_object *obj = intel_fb->obj; |
| 11417 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); |
| 11418 | u32 dspcntr; |
| 11419 | |
| 11420 | dspcntr = I915_READ(reg); |
| 11421 | |
| 11422 | if (obj->tiling_mode != I915_TILING_NONE) |
| 11423 | dspcntr |= DISPPLANE_TILED; |
| 11424 | else |
| 11425 | dspcntr &= ~DISPPLANE_TILED; |
| 11426 | |
| 11427 | I915_WRITE(reg, dspcntr); |
| 11428 | |
| 11429 | I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); |
| 11430 | POSTING_READ(DSPSURF(intel_crtc->plane)); |
| 11431 | } |
| 11432 | |
| 11433 | /* |
| 11434 | * XXX: This is the temporary way to update the plane registers until we get |
| 11435 | * around to using the usual plane update functions for MMIO flips |
| 11436 | */ |
| 11437 | static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip) |
| 11438 | { |
| 11439 | struct intel_crtc *crtc = mmio_flip->crtc; |
| 11440 | struct intel_unpin_work *work; |
| 11441 | |
| 11442 | spin_lock_irq(&crtc->base.dev->event_lock); |
| 11443 | work = crtc->unpin_work; |
| 11444 | spin_unlock_irq(&crtc->base.dev->event_lock); |
| 11445 | if (work == NULL) |
| 11446 | return; |
| 11447 | |
| 11448 | intel_mark_page_flip_active(work); |
| 11449 | |
| 11450 | intel_pipe_update_start(crtc); |
| 11451 | |
| 11452 | if (INTEL_INFO(mmio_flip->i915)->gen >= 9) |
| 11453 | skl_do_mmio_flip(crtc, mmio_flip->rotation, work); |
| 11454 | else |
| 11455 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ |
| 11456 | ilk_do_mmio_flip(crtc, work); |
| 11457 | |
| 11458 | intel_pipe_update_end(crtc); |
| 11459 | } |
| 11460 | |
| 11461 | static void intel_mmio_flip_work_func(struct work_struct *work) |
| 11462 | { |
| 11463 | struct intel_mmio_flip *mmio_flip = |
| 11464 | container_of(work, struct intel_mmio_flip, work); |
| 11465 | struct intel_framebuffer *intel_fb = |
| 11466 | to_intel_framebuffer(mmio_flip->crtc->base.primary->fb); |
| 11467 | struct drm_i915_gem_object *obj = intel_fb->obj; |
| 11468 | |
| 11469 | if (mmio_flip->req) { |
| 11470 | WARN_ON(__i915_wait_request(mmio_flip->req, |
| 11471 | mmio_flip->crtc->reset_counter, |
| 11472 | false, NULL, |
| 11473 | &mmio_flip->i915->rps.mmioflips)); |
| 11474 | i915_gem_request_unreference__unlocked(mmio_flip->req); |
| 11475 | } |
| 11476 | |
| 11477 | /* For framebuffer backed by dmabuf, wait for fence */ |
| 11478 | if (obj->base.dma_buf) |
| 11479 | WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, |
| 11480 | false, false, |
| 11481 | MAX_SCHEDULE_TIMEOUT) < 0); |
| 11482 | |
| 11483 | intel_do_mmio_flip(mmio_flip); |
| 11484 | kfree(mmio_flip); |
| 11485 | } |
| 11486 | |
| 11487 | static int intel_queue_mmio_flip(struct drm_device *dev, |
| 11488 | struct drm_crtc *crtc, |
| 11489 | struct drm_i915_gem_object *obj) |
| 11490 | { |
| 11491 | struct intel_mmio_flip *mmio_flip; |
| 11492 | |
| 11493 | mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL); |
| 11494 | if (mmio_flip == NULL) |
| 11495 | return -ENOMEM; |
| 11496 | |
| 11497 | mmio_flip->i915 = to_i915(dev); |
| 11498 | mmio_flip->req = i915_gem_request_reference(obj->last_write_req); |
| 11499 | mmio_flip->crtc = to_intel_crtc(crtc); |
| 11500 | mmio_flip->rotation = crtc->primary->state->rotation; |
| 11501 | |
| 11502 | INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func); |
| 11503 | schedule_work(&mmio_flip->work); |
| 11504 | |
| 11505 | return 0; |
| 11506 | } |
| 11507 | |
| 11508 | static int intel_default_queue_flip(struct drm_device *dev, |
| 11509 | struct drm_crtc *crtc, |
| 11510 | struct drm_framebuffer *fb, |
| 11511 | struct drm_i915_gem_object *obj, |
| 11512 | struct drm_i915_gem_request *req, |
| 11513 | uint32_t flags) |
| 11514 | { |
| 11515 | return -ENODEV; |
| 11516 | } |
| 11517 | |
| 11518 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
| 11519 | struct drm_crtc *crtc) |
| 11520 | { |
| 11521 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 11522 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 11523 | struct intel_unpin_work *work = intel_crtc->unpin_work; |
| 11524 | u32 addr; |
| 11525 | |
| 11526 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) |
| 11527 | return true; |
| 11528 | |
| 11529 | if (atomic_read(&work->pending) < INTEL_FLIP_PENDING) |
| 11530 | return false; |
| 11531 | |
| 11532 | if (!work->enable_stall_check) |
| 11533 | return false; |
| 11534 | |
| 11535 | if (work->flip_ready_vblank == 0) { |
| 11536 | if (work->flip_queued_req && |
| 11537 | !i915_gem_request_completed(work->flip_queued_req, true)) |
| 11538 | return false; |
| 11539 | |
| 11540 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
| 11541 | } |
| 11542 | |
| 11543 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
| 11544 | return false; |
| 11545 | |
| 11546 | /* Potential stall - if we see that the flip has happened, |
| 11547 | * assume a missed interrupt. */ |
| 11548 | if (INTEL_INFO(dev)->gen >= 4) |
| 11549 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); |
| 11550 | else |
| 11551 | addr = I915_READ(DSPADDR(intel_crtc->plane)); |
| 11552 | |
| 11553 | /* There is a potential issue here with a false positive after a flip |
| 11554 | * to the same address. We could address this by checking for a |
| 11555 | * non-incrementing frame counter. |
| 11556 | */ |
| 11557 | return addr == work->gtt_offset; |
| 11558 | } |
| 11559 | |
| 11560 | void intel_check_page_flip(struct drm_device *dev, int pipe) |
| 11561 | { |
| 11562 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 11563 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 11564 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 11565 | struct intel_unpin_work *work; |
| 11566 | |
| 11567 | WARN_ON(!in_interrupt()); |
| 11568 | |
| 11569 | if (crtc == NULL) |
| 11570 | return; |
| 11571 | |
| 11572 | spin_lock(&dev->event_lock); |
| 11573 | work = intel_crtc->unpin_work; |
| 11574 | if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { |
| 11575 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", |
| 11576 | work->flip_queued_vblank, drm_vblank_count(dev, pipe)); |
| 11577 | page_flip_completed(intel_crtc); |
| 11578 | work = NULL; |
| 11579 | } |
| 11580 | if (work != NULL && |
| 11581 | drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) |
| 11582 | intel_queue_rps_boost_for_request(dev, work->flip_queued_req); |
| 11583 | spin_unlock(&dev->event_lock); |
| 11584 | } |
| 11585 | |
| 11586 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
| 11587 | struct drm_framebuffer *fb, |
| 11588 | struct drm_pending_vblank_event *event, |
| 11589 | uint32_t page_flip_flags) |
| 11590 | { |
| 11591 | struct drm_device *dev = crtc->dev; |
| 11592 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 11593 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
| 11594 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
| 11595 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 11596 | struct drm_plane *primary = crtc->primary; |
| 11597 | enum pipe pipe = intel_crtc->pipe; |
| 11598 | struct intel_unpin_work *work; |
| 11599 | struct intel_engine_cs *ring; |
| 11600 | bool mmio_flip; |
| 11601 | struct drm_i915_gem_request *request = NULL; |
| 11602 | int ret; |
| 11603 | |
| 11604 | /* |
| 11605 | * drm_mode_page_flip_ioctl() should already catch this, but double |
| 11606 | * check to be safe. In the future we may enable pageflipping from |
| 11607 | * a disabled primary plane. |
| 11608 | */ |
| 11609 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) |
| 11610 | return -EBUSY; |
| 11611 | |
| 11612 | /* Can't change pixel format via MI display flips. */ |
| 11613 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
| 11614 | return -EINVAL; |
| 11615 | |
| 11616 | /* |
| 11617 | * TILEOFF/LINOFF registers can't be changed via MI display flips. |
| 11618 | * Note that pitch changes could also affect these register. |
| 11619 | */ |
| 11620 | if (INTEL_INFO(dev)->gen > 3 && |
| 11621 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
| 11622 | fb->pitches[0] != crtc->primary->fb->pitches[0])) |
| 11623 | return -EINVAL; |
| 11624 | |
| 11625 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
| 11626 | goto out_hang; |
| 11627 | |
| 11628 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
| 11629 | if (work == NULL) |
| 11630 | return -ENOMEM; |
| 11631 | |
| 11632 | work->event = event; |
| 11633 | work->crtc = crtc; |
| 11634 | work->old_fb = old_fb; |
| 11635 | INIT_WORK(&work->work, intel_unpin_work_fn); |
| 11636 | |
| 11637 | ret = drm_crtc_vblank_get(crtc); |
| 11638 | if (ret) |
| 11639 | goto free_work; |
| 11640 | |
| 11641 | /* We borrow the event spin lock for protecting unpin_work */ |
| 11642 | spin_lock_irq(&dev->event_lock); |
| 11643 | if (intel_crtc->unpin_work) { |
| 11644 | /* Before declaring the flip queue wedged, check if |
| 11645 | * the hardware completed the operation behind our backs. |
| 11646 | */ |
| 11647 | if (__intel_pageflip_stall_check(dev, crtc)) { |
| 11648 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); |
| 11649 | page_flip_completed(intel_crtc); |
| 11650 | } else { |
| 11651 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); |
| 11652 | spin_unlock_irq(&dev->event_lock); |
| 11653 | |
| 11654 | drm_crtc_vblank_put(crtc); |
| 11655 | kfree(work); |
| 11656 | return -EBUSY; |
| 11657 | } |
| 11658 | } |
| 11659 | intel_crtc->unpin_work = work; |
| 11660 | spin_unlock_irq(&dev->event_lock); |
| 11661 | |
| 11662 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
| 11663 | flush_workqueue(dev_priv->wq); |
| 11664 | |
| 11665 | /* Reference the objects for the scheduled work. */ |
| 11666 | drm_framebuffer_reference(work->old_fb); |
| 11667 | drm_gem_object_reference(&obj->base); |
| 11668 | |
| 11669 | crtc->primary->fb = fb; |
| 11670 | update_state_fb(crtc->primary); |
| 11671 | |
| 11672 | work->pending_flip_obj = obj; |
| 11673 | |
| 11674 | ret = i915_mutex_lock_interruptible(dev); |
| 11675 | if (ret) |
| 11676 | goto cleanup; |
| 11677 | |
| 11678 | atomic_inc(&intel_crtc->unpin_work_count); |
| 11679 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
| 11680 | |
| 11681 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
| 11682 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; |
| 11683 | |
| 11684 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
| 11685 | ring = &dev_priv->ring[BCS]; |
| 11686 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
| 11687 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
| 11688 | ring = NULL; |
| 11689 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
| 11690 | ring = &dev_priv->ring[BCS]; |
| 11691 | } else if (INTEL_INFO(dev)->gen >= 7) { |
| 11692 | ring = i915_gem_request_get_ring(obj->last_write_req); |
| 11693 | if (ring == NULL || ring->id != RCS) |
| 11694 | ring = &dev_priv->ring[BCS]; |
| 11695 | } else { |
| 11696 | ring = &dev_priv->ring[RCS]; |
| 11697 | } |
| 11698 | |
| 11699 | mmio_flip = use_mmio_flip(ring, obj); |
| 11700 | |
| 11701 | /* When using CS flips, we want to emit semaphores between rings. |
| 11702 | * However, when using mmio flips we will create a task to do the |
| 11703 | * synchronisation, so all we want here is to pin the framebuffer |
| 11704 | * into the display plane and skip any waits. |
| 11705 | */ |
| 11706 | if (!mmio_flip) { |
| 11707 | ret = i915_gem_object_sync(obj, ring, &request); |
| 11708 | if (ret) |
| 11709 | goto cleanup_pending; |
| 11710 | } |
| 11711 | |
| 11712 | ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, |
| 11713 | crtc->primary->state); |
| 11714 | if (ret) |
| 11715 | goto cleanup_pending; |
| 11716 | |
| 11717 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), |
| 11718 | obj, 0); |
| 11719 | work->gtt_offset += intel_crtc->dspaddr_offset; |
| 11720 | |
| 11721 | if (mmio_flip) { |
| 11722 | ret = intel_queue_mmio_flip(dev, crtc, obj); |
| 11723 | if (ret) |
| 11724 | goto cleanup_unpin; |
| 11725 | |
| 11726 | i915_gem_request_assign(&work->flip_queued_req, |
| 11727 | obj->last_write_req); |
| 11728 | } else { |
| 11729 | if (!request) { |
| 11730 | ret = i915_gem_request_alloc(ring, ring->default_context, &request); |
| 11731 | if (ret) |
| 11732 | goto cleanup_unpin; |
| 11733 | } |
| 11734 | |
| 11735 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, |
| 11736 | page_flip_flags); |
| 11737 | if (ret) |
| 11738 | goto cleanup_unpin; |
| 11739 | |
| 11740 | i915_gem_request_assign(&work->flip_queued_req, request); |
| 11741 | } |
| 11742 | |
| 11743 | if (request) |
| 11744 | i915_add_request_no_flush(request); |
| 11745 | |
| 11746 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
| 11747 | work->enable_stall_check = true; |
| 11748 | |
| 11749 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
| 11750 | to_intel_plane(primary)->frontbuffer_bit); |
| 11751 | mutex_unlock(&dev->struct_mutex); |
| 11752 | |
| 11753 | intel_fbc_deactivate(intel_crtc); |
| 11754 | intel_frontbuffer_flip_prepare(dev, |
| 11755 | to_intel_plane(primary)->frontbuffer_bit); |
| 11756 | |
| 11757 | trace_i915_flip_request(intel_crtc->plane, obj); |
| 11758 | |
| 11759 | return 0; |
| 11760 | |
| 11761 | cleanup_unpin: |
| 11762 | intel_unpin_fb_obj(fb, crtc->primary->state); |
| 11763 | cleanup_pending: |
| 11764 | if (request) |
| 11765 | i915_gem_request_cancel(request); |
| 11766 | atomic_dec(&intel_crtc->unpin_work_count); |
| 11767 | mutex_unlock(&dev->struct_mutex); |
| 11768 | cleanup: |
| 11769 | crtc->primary->fb = old_fb; |
| 11770 | update_state_fb(crtc->primary); |
| 11771 | |
| 11772 | drm_gem_object_unreference_unlocked(&obj->base); |
| 11773 | drm_framebuffer_unreference(work->old_fb); |
| 11774 | |
| 11775 | spin_lock_irq(&dev->event_lock); |
| 11776 | intel_crtc->unpin_work = NULL; |
| 11777 | spin_unlock_irq(&dev->event_lock); |
| 11778 | |
| 11779 | drm_crtc_vblank_put(crtc); |
| 11780 | free_work: |
| 11781 | kfree(work); |
| 11782 | |
| 11783 | if (ret == -EIO) { |
| 11784 | struct drm_atomic_state *state; |
| 11785 | struct drm_plane_state *plane_state; |
| 11786 | |
| 11787 | out_hang: |
| 11788 | state = drm_atomic_state_alloc(dev); |
| 11789 | if (!state) |
| 11790 | return -ENOMEM; |
| 11791 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
| 11792 | |
| 11793 | retry: |
| 11794 | plane_state = drm_atomic_get_plane_state(state, primary); |
| 11795 | ret = PTR_ERR_OR_ZERO(plane_state); |
| 11796 | if (!ret) { |
| 11797 | drm_atomic_set_fb_for_plane(plane_state, fb); |
| 11798 | |
| 11799 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); |
| 11800 | if (!ret) |
| 11801 | ret = drm_atomic_commit(state); |
| 11802 | } |
| 11803 | |
| 11804 | if (ret == -EDEADLK) { |
| 11805 | drm_modeset_backoff(state->acquire_ctx); |
| 11806 | drm_atomic_state_clear(state); |
| 11807 | goto retry; |
| 11808 | } |
| 11809 | |
| 11810 | if (ret) |
| 11811 | drm_atomic_state_free(state); |
| 11812 | |
| 11813 | if (ret == 0 && event) { |
| 11814 | spin_lock_irq(&dev->event_lock); |
| 11815 | drm_send_vblank_event(dev, pipe, event); |
| 11816 | spin_unlock_irq(&dev->event_lock); |
| 11817 | } |
| 11818 | } |
| 11819 | return ret; |
| 11820 | } |
| 11821 | |
| 11822 | |
| 11823 | /** |
| 11824 | * intel_wm_need_update - Check whether watermarks need updating |
| 11825 | * @plane: drm plane |
| 11826 | * @state: new plane state |
| 11827 | * |
| 11828 | * Check current plane state versus the new one to determine whether |
| 11829 | * watermarks need to be recalculated. |
| 11830 | * |
| 11831 | * Returns true or false. |
| 11832 | */ |
| 11833 | static bool intel_wm_need_update(struct drm_plane *plane, |
| 11834 | struct drm_plane_state *state) |
| 11835 | { |
| 11836 | struct intel_plane_state *new = to_intel_plane_state(state); |
| 11837 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); |
| 11838 | |
| 11839 | /* Update watermarks on tiling or size changes. */ |
| 11840 | if (new->visible != cur->visible) |
| 11841 | return true; |
| 11842 | |
| 11843 | if (!cur->base.fb || !new->base.fb) |
| 11844 | return false; |
| 11845 | |
| 11846 | if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] || |
| 11847 | cur->base.rotation != new->base.rotation || |
| 11848 | drm_rect_width(&new->src) != drm_rect_width(&cur->src) || |
| 11849 | drm_rect_height(&new->src) != drm_rect_height(&cur->src) || |
| 11850 | drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) || |
| 11851 | drm_rect_height(&new->dst) != drm_rect_height(&cur->dst)) |
| 11852 | return true; |
| 11853 | |
| 11854 | return false; |
| 11855 | } |
| 11856 | |
| 11857 | static bool needs_scaling(struct intel_plane_state *state) |
| 11858 | { |
| 11859 | int src_w = drm_rect_width(&state->src) >> 16; |
| 11860 | int src_h = drm_rect_height(&state->src) >> 16; |
| 11861 | int dst_w = drm_rect_width(&state->dst); |
| 11862 | int dst_h = drm_rect_height(&state->dst); |
| 11863 | |
| 11864 | return (src_w != dst_w || src_h != dst_h); |
| 11865 | } |
| 11866 | |
| 11867 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
| 11868 | struct drm_plane_state *plane_state) |
| 11869 | { |
| 11870 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
| 11871 | struct drm_crtc *crtc = crtc_state->crtc; |
| 11872 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 11873 | struct drm_plane *plane = plane_state->plane; |
| 11874 | struct drm_device *dev = crtc->dev; |
| 11875 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 11876 | struct intel_plane_state *old_plane_state = |
| 11877 | to_intel_plane_state(plane->state); |
| 11878 | int idx = intel_crtc->base.base.id, ret; |
| 11879 | int i = drm_plane_index(plane); |
| 11880 | bool mode_changed = needs_modeset(crtc_state); |
| 11881 | bool was_crtc_enabled = crtc->state->active; |
| 11882 | bool is_crtc_enabled = crtc_state->active; |
| 11883 | bool turn_off, turn_on, visible, was_visible; |
| 11884 | struct drm_framebuffer *fb = plane_state->fb; |
| 11885 | |
| 11886 | if (crtc_state && INTEL_INFO(dev)->gen >= 9 && |
| 11887 | plane->type != DRM_PLANE_TYPE_CURSOR) { |
| 11888 | ret = skl_update_scaler_plane( |
| 11889 | to_intel_crtc_state(crtc_state), |
| 11890 | to_intel_plane_state(plane_state)); |
| 11891 | if (ret) |
| 11892 | return ret; |
| 11893 | } |
| 11894 | |
| 11895 | was_visible = old_plane_state->visible; |
| 11896 | visible = to_intel_plane_state(plane_state)->visible; |
| 11897 | |
| 11898 | if (!was_crtc_enabled && WARN_ON(was_visible)) |
| 11899 | was_visible = false; |
| 11900 | |
| 11901 | /* |
| 11902 | * Visibility is calculated as if the crtc was on, but |
| 11903 | * after scaler setup everything depends on it being off |
| 11904 | * when the crtc isn't active. |
| 11905 | */ |
| 11906 | if (!is_crtc_enabled) |
| 11907 | to_intel_plane_state(plane_state)->visible = visible = false; |
| 11908 | |
| 11909 | if (!was_visible && !visible) |
| 11910 | return 0; |
| 11911 | |
| 11912 | turn_off = was_visible && (!visible || mode_changed); |
| 11913 | turn_on = visible && (!was_visible || mode_changed); |
| 11914 | |
| 11915 | DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx, |
| 11916 | plane->base.id, fb ? fb->base.id : -1); |
| 11917 | |
| 11918 | DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n", |
| 11919 | plane->base.id, was_visible, visible, |
| 11920 | turn_off, turn_on, mode_changed); |
| 11921 | |
| 11922 | if (turn_on || turn_off) { |
| 11923 | pipe_config->wm_changed = true; |
| 11924 | |
| 11925 | /* must disable cxsr around plane enable/disable */ |
| 11926 | if (plane->type != DRM_PLANE_TYPE_CURSOR) { |
| 11927 | if (is_crtc_enabled) |
| 11928 | intel_crtc->atomic.wait_vblank = true; |
| 11929 | pipe_config->disable_cxsr = true; |
| 11930 | } |
| 11931 | } else if (intel_wm_need_update(plane, plane_state)) { |
| 11932 | pipe_config->wm_changed = true; |
| 11933 | } |
| 11934 | |
| 11935 | /* Pre-gen9 platforms need two-step watermark updates */ |
| 11936 | if (pipe_config->wm_changed && INTEL_INFO(dev)->gen < 9 && |
| 11937 | dev_priv->display.optimize_watermarks) |
| 11938 | to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true; |
| 11939 | |
| 11940 | if (visible || was_visible) |
| 11941 | intel_crtc->atomic.fb_bits |= |
| 11942 | to_intel_plane(plane)->frontbuffer_bit; |
| 11943 | |
| 11944 | switch (plane->type) { |
| 11945 | case DRM_PLANE_TYPE_PRIMARY: |
| 11946 | intel_crtc->atomic.pre_disable_primary = turn_off; |
| 11947 | intel_crtc->atomic.post_enable_primary = turn_on; |
| 11948 | |
| 11949 | if (turn_off) { |
| 11950 | /* |
| 11951 | * FIXME: Actually if we will still have any other |
| 11952 | * plane enabled on the pipe we could let IPS enabled |
| 11953 | * still, but for now lets consider that when we make |
| 11954 | * primary invisible by setting DSPCNTR to 0 on |
| 11955 | * update_primary_plane function IPS needs to be |
| 11956 | * disable. |
| 11957 | */ |
| 11958 | intel_crtc->atomic.disable_ips = true; |
| 11959 | |
| 11960 | intel_crtc->atomic.disable_fbc = true; |
| 11961 | } |
| 11962 | |
| 11963 | /* |
| 11964 | * FBC does not work on some platforms for rotated |
| 11965 | * planes, so disable it when rotation is not 0 and |
| 11966 | * update it when rotation is set back to 0. |
| 11967 | * |
| 11968 | * FIXME: This is redundant with the fbc update done in |
| 11969 | * the primary plane enable function except that that |
| 11970 | * one is done too late. We eventually need to unify |
| 11971 | * this. |
| 11972 | */ |
| 11973 | |
| 11974 | if (visible && |
| 11975 | INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && |
| 11976 | dev_priv->fbc.crtc == intel_crtc && |
| 11977 | plane_state->rotation != BIT(DRM_ROTATE_0)) |
| 11978 | intel_crtc->atomic.disable_fbc = true; |
| 11979 | |
| 11980 | /* |
| 11981 | * BDW signals flip done immediately if the plane |
| 11982 | * is disabled, even if the plane enable is already |
| 11983 | * armed to occur at the next vblank :( |
| 11984 | */ |
| 11985 | if (turn_on && IS_BROADWELL(dev)) |
| 11986 | intel_crtc->atomic.wait_vblank = true; |
| 11987 | |
| 11988 | intel_crtc->atomic.update_fbc |= visible || mode_changed; |
| 11989 | break; |
| 11990 | case DRM_PLANE_TYPE_CURSOR: |
| 11991 | break; |
| 11992 | case DRM_PLANE_TYPE_OVERLAY: |
| 11993 | /* |
| 11994 | * WaCxSRDisabledForSpriteScaling:ivb |
| 11995 | * |
| 11996 | * cstate->update_wm was already set above, so this flag will |
| 11997 | * take effect when we commit and program watermarks. |
| 11998 | */ |
| 11999 | if (IS_IVYBRIDGE(dev) && |
| 12000 | needs_scaling(to_intel_plane_state(plane_state)) && |
| 12001 | !needs_scaling(old_plane_state)) { |
| 12002 | to_intel_crtc_state(crtc_state)->disable_lp_wm = true; |
| 12003 | } else if (turn_off && !mode_changed) { |
| 12004 | intel_crtc->atomic.wait_vblank = true; |
| 12005 | intel_crtc->atomic.update_sprite_watermarks |= |
| 12006 | 1 << i; |
| 12007 | } |
| 12008 | |
| 12009 | break; |
| 12010 | } |
| 12011 | return 0; |
| 12012 | } |
| 12013 | |
| 12014 | static bool encoders_cloneable(const struct intel_encoder *a, |
| 12015 | const struct intel_encoder *b) |
| 12016 | { |
| 12017 | /* masks could be asymmetric, so check both ways */ |
| 12018 | return a == b || (a->cloneable & (1 << b->type) && |
| 12019 | b->cloneable & (1 << a->type)); |
| 12020 | } |
| 12021 | |
| 12022 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, |
| 12023 | struct intel_crtc *crtc, |
| 12024 | struct intel_encoder *encoder) |
| 12025 | { |
| 12026 | struct intel_encoder *source_encoder; |
| 12027 | struct drm_connector *connector; |
| 12028 | struct drm_connector_state *connector_state; |
| 12029 | int i; |
| 12030 | |
| 12031 | for_each_connector_in_state(state, connector, connector_state, i) { |
| 12032 | if (connector_state->crtc != &crtc->base) |
| 12033 | continue; |
| 12034 | |
| 12035 | source_encoder = |
| 12036 | to_intel_encoder(connector_state->best_encoder); |
| 12037 | if (!encoders_cloneable(encoder, source_encoder)) |
| 12038 | return false; |
| 12039 | } |
| 12040 | |
| 12041 | return true; |
| 12042 | } |
| 12043 | |
| 12044 | static bool check_encoder_cloning(struct drm_atomic_state *state, |
| 12045 | struct intel_crtc *crtc) |
| 12046 | { |
| 12047 | struct intel_encoder *encoder; |
| 12048 | struct drm_connector *connector; |
| 12049 | struct drm_connector_state *connector_state; |
| 12050 | int i; |
| 12051 | |
| 12052 | for_each_connector_in_state(state, connector, connector_state, i) { |
| 12053 | if (connector_state->crtc != &crtc->base) |
| 12054 | continue; |
| 12055 | |
| 12056 | encoder = to_intel_encoder(connector_state->best_encoder); |
| 12057 | if (!check_single_encoder_cloning(state, crtc, encoder)) |
| 12058 | return false; |
| 12059 | } |
| 12060 | |
| 12061 | return true; |
| 12062 | } |
| 12063 | |
| 12064 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, |
| 12065 | struct drm_crtc_state *crtc_state) |
| 12066 | { |
| 12067 | struct drm_device *dev = crtc->dev; |
| 12068 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 12069 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 12070 | struct intel_crtc_state *pipe_config = |
| 12071 | to_intel_crtc_state(crtc_state); |
| 12072 | struct drm_atomic_state *state = crtc_state->state; |
| 12073 | int ret; |
| 12074 | bool mode_changed = needs_modeset(crtc_state); |
| 12075 | |
| 12076 | if (mode_changed && !check_encoder_cloning(state, intel_crtc)) { |
| 12077 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
| 12078 | return -EINVAL; |
| 12079 | } |
| 12080 | |
| 12081 | if (mode_changed && !crtc_state->active) |
| 12082 | pipe_config->wm_changed = true; |
| 12083 | |
| 12084 | if (mode_changed && crtc_state->enable && |
| 12085 | dev_priv->display.crtc_compute_clock && |
| 12086 | !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) { |
| 12087 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
| 12088 | pipe_config); |
| 12089 | if (ret) |
| 12090 | return ret; |
| 12091 | } |
| 12092 | |
| 12093 | ret = 0; |
| 12094 | if (dev_priv->display.compute_pipe_wm) { |
| 12095 | ret = dev_priv->display.compute_pipe_wm(intel_crtc, state); |
| 12096 | if (ret) { |
| 12097 | DRM_DEBUG_KMS("Target pipe watermarks are invalid\n"); |
| 12098 | return ret; |
| 12099 | } |
| 12100 | } |
| 12101 | |
| 12102 | if (dev_priv->display.compute_intermediate_wm && |
| 12103 | !to_intel_atomic_state(state)->skip_intermediate_wm) { |
| 12104 | if (WARN_ON(!dev_priv->display.compute_pipe_wm)) |
| 12105 | return 0; |
| 12106 | |
| 12107 | /* |
| 12108 | * Calculate 'intermediate' watermarks that satisfy both the |
| 12109 | * old state and the new state. We can program these |
| 12110 | * immediately. |
| 12111 | */ |
| 12112 | ret = dev_priv->display.compute_intermediate_wm(crtc->dev, |
| 12113 | intel_crtc, |
| 12114 | pipe_config); |
| 12115 | if (ret) { |
| 12116 | DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n"); |
| 12117 | return ret; |
| 12118 | } |
| 12119 | } |
| 12120 | |
| 12121 | if (INTEL_INFO(dev)->gen >= 9) { |
| 12122 | if (mode_changed) |
| 12123 | ret = skl_update_scaler_crtc(pipe_config); |
| 12124 | |
| 12125 | if (!ret) |
| 12126 | ret = intel_atomic_setup_scalers(dev, intel_crtc, |
| 12127 | pipe_config); |
| 12128 | } |
| 12129 | |
| 12130 | return ret; |
| 12131 | } |
| 12132 | |
| 12133 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
| 12134 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
| 12135 | .load_lut = intel_crtc_load_lut, |
| 12136 | .atomic_begin = intel_begin_crtc_commit, |
| 12137 | .atomic_flush = intel_finish_crtc_commit, |
| 12138 | .atomic_check = intel_crtc_atomic_check, |
| 12139 | }; |
| 12140 | |
| 12141 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
| 12142 | { |
| 12143 | struct intel_connector *connector; |
| 12144 | |
| 12145 | for_each_intel_connector(dev, connector) { |
| 12146 | if (connector->base.encoder) { |
| 12147 | connector->base.state->best_encoder = |
| 12148 | connector->base.encoder; |
| 12149 | connector->base.state->crtc = |
| 12150 | connector->base.encoder->crtc; |
| 12151 | } else { |
| 12152 | connector->base.state->best_encoder = NULL; |
| 12153 | connector->base.state->crtc = NULL; |
| 12154 | } |
| 12155 | } |
| 12156 | } |
| 12157 | |
| 12158 | static void |
| 12159 | connected_sink_compute_bpp(struct intel_connector *connector, |
| 12160 | struct intel_crtc_state *pipe_config) |
| 12161 | { |
| 12162 | int bpp = pipe_config->pipe_bpp; |
| 12163 | |
| 12164 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", |
| 12165 | connector->base.base.id, |
| 12166 | connector->base.name); |
| 12167 | |
| 12168 | /* Don't use an invalid EDID bpc value */ |
| 12169 | if (connector->base.display_info.bpc && |
| 12170 | connector->base.display_info.bpc * 3 < bpp) { |
| 12171 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", |
| 12172 | bpp, connector->base.display_info.bpc*3); |
| 12173 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; |
| 12174 | } |
| 12175 | |
| 12176 | /* Clamp bpp to 8 on screens without EDID 1.4 */ |
| 12177 | if (connector->base.display_info.bpc == 0 && bpp > 24) { |
| 12178 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", |
| 12179 | bpp); |
| 12180 | pipe_config->pipe_bpp = 24; |
| 12181 | } |
| 12182 | } |
| 12183 | |
| 12184 | static int |
| 12185 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
| 12186 | struct intel_crtc_state *pipe_config) |
| 12187 | { |
| 12188 | struct drm_device *dev = crtc->base.dev; |
| 12189 | struct drm_atomic_state *state; |
| 12190 | struct drm_connector *connector; |
| 12191 | struct drm_connector_state *connector_state; |
| 12192 | int bpp, i; |
| 12193 | |
| 12194 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) |
| 12195 | bpp = 10*3; |
| 12196 | else if (INTEL_INFO(dev)->gen >= 5) |
| 12197 | bpp = 12*3; |
| 12198 | else |
| 12199 | bpp = 8*3; |
| 12200 | |
| 12201 | |
| 12202 | pipe_config->pipe_bpp = bpp; |
| 12203 | |
| 12204 | state = pipe_config->base.state; |
| 12205 | |
| 12206 | /* Clamp display bpp to EDID value */ |
| 12207 | for_each_connector_in_state(state, connector, connector_state, i) { |
| 12208 | if (connector_state->crtc != &crtc->base) |
| 12209 | continue; |
| 12210 | |
| 12211 | connected_sink_compute_bpp(to_intel_connector(connector), |
| 12212 | pipe_config); |
| 12213 | } |
| 12214 | |
| 12215 | return bpp; |
| 12216 | } |
| 12217 | |
| 12218 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
| 12219 | { |
| 12220 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " |
| 12221 | "type: 0x%x flags: 0x%x\n", |
| 12222 | mode->crtc_clock, |
| 12223 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
| 12224 | mode->crtc_hsync_end, mode->crtc_htotal, |
| 12225 | mode->crtc_vdisplay, mode->crtc_vsync_start, |
| 12226 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); |
| 12227 | } |
| 12228 | |
| 12229 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
| 12230 | struct intel_crtc_state *pipe_config, |
| 12231 | const char *context) |
| 12232 | { |
| 12233 | struct drm_device *dev = crtc->base.dev; |
| 12234 | struct drm_plane *plane; |
| 12235 | struct intel_plane *intel_plane; |
| 12236 | struct intel_plane_state *state; |
| 12237 | struct drm_framebuffer *fb; |
| 12238 | |
| 12239 | DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, |
| 12240 | context, pipe_config, pipe_name(crtc->pipe)); |
| 12241 | |
| 12242 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); |
| 12243 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", |
| 12244 | pipe_config->pipe_bpp, pipe_config->dither); |
| 12245 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
| 12246 | pipe_config->has_pch_encoder, |
| 12247 | pipe_config->fdi_lanes, |
| 12248 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, |
| 12249 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, |
| 12250 | pipe_config->fdi_m_n.tu); |
| 12251 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
| 12252 | pipe_config->has_dp_encoder, |
| 12253 | pipe_config->lane_count, |
| 12254 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
| 12255 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, |
| 12256 | pipe_config->dp_m_n.tu); |
| 12257 | |
| 12258 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", |
| 12259 | pipe_config->has_dp_encoder, |
| 12260 | pipe_config->lane_count, |
| 12261 | pipe_config->dp_m2_n2.gmch_m, |
| 12262 | pipe_config->dp_m2_n2.gmch_n, |
| 12263 | pipe_config->dp_m2_n2.link_m, |
| 12264 | pipe_config->dp_m2_n2.link_n, |
| 12265 | pipe_config->dp_m2_n2.tu); |
| 12266 | |
| 12267 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
| 12268 | pipe_config->has_audio, |
| 12269 | pipe_config->has_infoframe); |
| 12270 | |
| 12271 | DRM_DEBUG_KMS("requested mode:\n"); |
| 12272 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
| 12273 | DRM_DEBUG_KMS("adjusted mode:\n"); |
| 12274 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
| 12275 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); |
| 12276 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
| 12277 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
| 12278 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); |
| 12279 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
| 12280 | crtc->num_scalers, |
| 12281 | pipe_config->scaler_state.scaler_users, |
| 12282 | pipe_config->scaler_state.scaler_id); |
| 12283 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
| 12284 | pipe_config->gmch_pfit.control, |
| 12285 | pipe_config->gmch_pfit.pgm_ratios, |
| 12286 | pipe_config->gmch_pfit.lvds_border_bits); |
| 12287 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
| 12288 | pipe_config->pch_pfit.pos, |
| 12289 | pipe_config->pch_pfit.size, |
| 12290 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); |
| 12291 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
| 12292 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
| 12293 | |
| 12294 | if (IS_BROXTON(dev)) { |
| 12295 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," |
| 12296 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " |
| 12297 | "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", |
| 12298 | pipe_config->ddi_pll_sel, |
| 12299 | pipe_config->dpll_hw_state.ebb0, |
| 12300 | pipe_config->dpll_hw_state.ebb4, |
| 12301 | pipe_config->dpll_hw_state.pll0, |
| 12302 | pipe_config->dpll_hw_state.pll1, |
| 12303 | pipe_config->dpll_hw_state.pll2, |
| 12304 | pipe_config->dpll_hw_state.pll3, |
| 12305 | pipe_config->dpll_hw_state.pll6, |
| 12306 | pipe_config->dpll_hw_state.pll8, |
| 12307 | pipe_config->dpll_hw_state.pll9, |
| 12308 | pipe_config->dpll_hw_state.pll10, |
| 12309 | pipe_config->dpll_hw_state.pcsdw12); |
| 12310 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
| 12311 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " |
| 12312 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", |
| 12313 | pipe_config->ddi_pll_sel, |
| 12314 | pipe_config->dpll_hw_state.ctrl1, |
| 12315 | pipe_config->dpll_hw_state.cfgcr1, |
| 12316 | pipe_config->dpll_hw_state.cfgcr2); |
| 12317 | } else if (HAS_DDI(dev)) { |
| 12318 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", |
| 12319 | pipe_config->ddi_pll_sel, |
| 12320 | pipe_config->dpll_hw_state.wrpll, |
| 12321 | pipe_config->dpll_hw_state.spll); |
| 12322 | } else { |
| 12323 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " |
| 12324 | "fp0: 0x%x, fp1: 0x%x\n", |
| 12325 | pipe_config->dpll_hw_state.dpll, |
| 12326 | pipe_config->dpll_hw_state.dpll_md, |
| 12327 | pipe_config->dpll_hw_state.fp0, |
| 12328 | pipe_config->dpll_hw_state.fp1); |
| 12329 | } |
| 12330 | |
| 12331 | DRM_DEBUG_KMS("planes on this crtc\n"); |
| 12332 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { |
| 12333 | intel_plane = to_intel_plane(plane); |
| 12334 | if (intel_plane->pipe != crtc->pipe) |
| 12335 | continue; |
| 12336 | |
| 12337 | state = to_intel_plane_state(plane->state); |
| 12338 | fb = state->base.fb; |
| 12339 | if (!fb) { |
| 12340 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d " |
| 12341 | "disabled, scaler_id = %d\n", |
| 12342 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", |
| 12343 | plane->base.id, intel_plane->pipe, |
| 12344 | (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, |
| 12345 | drm_plane_index(plane), state->scaler_id); |
| 12346 | continue; |
| 12347 | } |
| 12348 | |
| 12349 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled", |
| 12350 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", |
| 12351 | plane->base.id, intel_plane->pipe, |
| 12352 | crtc->base.primary == plane ? 0 : intel_plane->plane + 1, |
| 12353 | drm_plane_index(plane)); |
| 12354 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x", |
| 12355 | fb->base.id, fb->width, fb->height, fb->pixel_format); |
| 12356 | DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n", |
| 12357 | state->scaler_id, |
| 12358 | state->src.x1 >> 16, state->src.y1 >> 16, |
| 12359 | drm_rect_width(&state->src) >> 16, |
| 12360 | drm_rect_height(&state->src) >> 16, |
| 12361 | state->dst.x1, state->dst.y1, |
| 12362 | drm_rect_width(&state->dst), drm_rect_height(&state->dst)); |
| 12363 | } |
| 12364 | } |
| 12365 | |
| 12366 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
| 12367 | { |
| 12368 | struct drm_device *dev = state->dev; |
| 12369 | struct drm_connector *connector; |
| 12370 | unsigned int used_ports = 0; |
| 12371 | |
| 12372 | /* |
| 12373 | * Walk the connector list instead of the encoder |
| 12374 | * list to detect the problem on ddi platforms |
| 12375 | * where there's just one encoder per digital port. |
| 12376 | */ |
| 12377 | drm_for_each_connector(connector, dev) { |
| 12378 | struct drm_connector_state *connector_state; |
| 12379 | struct intel_encoder *encoder; |
| 12380 | |
| 12381 | connector_state = drm_atomic_get_existing_connector_state(state, connector); |
| 12382 | if (!connector_state) |
| 12383 | connector_state = connector->state; |
| 12384 | |
| 12385 | if (!connector_state->best_encoder) |
| 12386 | continue; |
| 12387 | |
| 12388 | encoder = to_intel_encoder(connector_state->best_encoder); |
| 12389 | |
| 12390 | WARN_ON(!connector_state->crtc); |
| 12391 | |
| 12392 | switch (encoder->type) { |
| 12393 | unsigned int port_mask; |
| 12394 | case INTEL_OUTPUT_UNKNOWN: |
| 12395 | if (WARN_ON(!HAS_DDI(dev))) |
| 12396 | break; |
| 12397 | case INTEL_OUTPUT_DISPLAYPORT: |
| 12398 | case INTEL_OUTPUT_HDMI: |
| 12399 | case INTEL_OUTPUT_EDP: |
| 12400 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; |
| 12401 | |
| 12402 | /* the same port mustn't appear more than once */ |
| 12403 | if (used_ports & port_mask) |
| 12404 | return false; |
| 12405 | |
| 12406 | used_ports |= port_mask; |
| 12407 | default: |
| 12408 | break; |
| 12409 | } |
| 12410 | } |
| 12411 | |
| 12412 | return true; |
| 12413 | } |
| 12414 | |
| 12415 | static void |
| 12416 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) |
| 12417 | { |
| 12418 | struct drm_crtc_state tmp_state; |
| 12419 | struct intel_crtc_scaler_state scaler_state; |
| 12420 | struct intel_dpll_hw_state dpll_hw_state; |
| 12421 | enum intel_dpll_id shared_dpll; |
| 12422 | uint32_t ddi_pll_sel; |
| 12423 | bool force_thru; |
| 12424 | |
| 12425 | /* FIXME: before the switch to atomic started, a new pipe_config was |
| 12426 | * kzalloc'd. Code that depends on any field being zero should be |
| 12427 | * fixed, so that the crtc_state can be safely duplicated. For now, |
| 12428 | * only fields that are know to not cause problems are preserved. */ |
| 12429 | |
| 12430 | tmp_state = crtc_state->base; |
| 12431 | scaler_state = crtc_state->scaler_state; |
| 12432 | shared_dpll = crtc_state->shared_dpll; |
| 12433 | dpll_hw_state = crtc_state->dpll_hw_state; |
| 12434 | ddi_pll_sel = crtc_state->ddi_pll_sel; |
| 12435 | force_thru = crtc_state->pch_pfit.force_thru; |
| 12436 | |
| 12437 | memset(crtc_state, 0, sizeof *crtc_state); |
| 12438 | |
| 12439 | crtc_state->base = tmp_state; |
| 12440 | crtc_state->scaler_state = scaler_state; |
| 12441 | crtc_state->shared_dpll = shared_dpll; |
| 12442 | crtc_state->dpll_hw_state = dpll_hw_state; |
| 12443 | crtc_state->ddi_pll_sel = ddi_pll_sel; |
| 12444 | crtc_state->pch_pfit.force_thru = force_thru; |
| 12445 | } |
| 12446 | |
| 12447 | static int |
| 12448 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
| 12449 | struct intel_crtc_state *pipe_config) |
| 12450 | { |
| 12451 | struct drm_atomic_state *state = pipe_config->base.state; |
| 12452 | struct intel_encoder *encoder; |
| 12453 | struct drm_connector *connector; |
| 12454 | struct drm_connector_state *connector_state; |
| 12455 | int base_bpp, ret = -EINVAL; |
| 12456 | int i; |
| 12457 | bool retry = true; |
| 12458 | |
| 12459 | clear_intel_crtc_state(pipe_config); |
| 12460 | |
| 12461 | pipe_config->cpu_transcoder = |
| 12462 | (enum transcoder) to_intel_crtc(crtc)->pipe; |
| 12463 | |
| 12464 | /* |
| 12465 | * Sanitize sync polarity flags based on requested ones. If neither |
| 12466 | * positive or negative polarity is requested, treat this as meaning |
| 12467 | * negative polarity. |
| 12468 | */ |
| 12469 | if (!(pipe_config->base.adjusted_mode.flags & |
| 12470 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
| 12471 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
| 12472 | |
| 12473 | if (!(pipe_config->base.adjusted_mode.flags & |
| 12474 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
| 12475 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
| 12476 | |
| 12477 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
| 12478 | pipe_config); |
| 12479 | if (base_bpp < 0) |
| 12480 | goto fail; |
| 12481 | |
| 12482 | /* |
| 12483 | * Determine the real pipe dimensions. Note that stereo modes can |
| 12484 | * increase the actual pipe size due to the frame doubling and |
| 12485 | * insertion of additional space for blanks between the frame. This |
| 12486 | * is stored in the crtc timings. We use the requested mode to do this |
| 12487 | * computation to clearly distinguish it from the adjusted mode, which |
| 12488 | * can be changed by the connectors in the below retry loop. |
| 12489 | */ |
| 12490 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
| 12491 | &pipe_config->pipe_src_w, |
| 12492 | &pipe_config->pipe_src_h); |
| 12493 | |
| 12494 | encoder_retry: |
| 12495 | /* Ensure the port clock defaults are reset when retrying. */ |
| 12496 | pipe_config->port_clock = 0; |
| 12497 | pipe_config->pixel_multiplier = 1; |
| 12498 | |
| 12499 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
| 12500 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
| 12501 | CRTC_STEREO_DOUBLE); |
| 12502 | |
| 12503 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
| 12504 | * adjust it according to limitations or connector properties, and also |
| 12505 | * a chance to reject the mode entirely. |
| 12506 | */ |
| 12507 | for_each_connector_in_state(state, connector, connector_state, i) { |
| 12508 | if (connector_state->crtc != crtc) |
| 12509 | continue; |
| 12510 | |
| 12511 | encoder = to_intel_encoder(connector_state->best_encoder); |
| 12512 | |
| 12513 | if (!(encoder->compute_config(encoder, pipe_config))) { |
| 12514 | DRM_DEBUG_KMS("Encoder config failure\n"); |
| 12515 | goto fail; |
| 12516 | } |
| 12517 | } |
| 12518 | |
| 12519 | /* Set default port clock if not overwritten by the encoder. Needs to be |
| 12520 | * done afterwards in case the encoder adjusts the mode. */ |
| 12521 | if (!pipe_config->port_clock) |
| 12522 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
| 12523 | * pipe_config->pixel_multiplier; |
| 12524 | |
| 12525 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
| 12526 | if (ret < 0) { |
| 12527 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
| 12528 | goto fail; |
| 12529 | } |
| 12530 | |
| 12531 | if (ret == RETRY) { |
| 12532 | if (WARN(!retry, "loop in pipe configuration computation\n")) { |
| 12533 | ret = -EINVAL; |
| 12534 | goto fail; |
| 12535 | } |
| 12536 | |
| 12537 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); |
| 12538 | retry = false; |
| 12539 | goto encoder_retry; |
| 12540 | } |
| 12541 | |
| 12542 | /* Dithering seems to not pass-through bits correctly when it should, so |
| 12543 | * only enable it on 6bpc panels. */ |
| 12544 | pipe_config->dither = pipe_config->pipe_bpp == 6*3; |
| 12545 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
| 12546 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
| 12547 | |
| 12548 | fail: |
| 12549 | return ret; |
| 12550 | } |
| 12551 | |
| 12552 | static void |
| 12553 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
| 12554 | { |
| 12555 | struct drm_crtc *crtc; |
| 12556 | struct drm_crtc_state *crtc_state; |
| 12557 | int i; |
| 12558 | |
| 12559 | /* Double check state. */ |
| 12560 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
| 12561 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
| 12562 | |
| 12563 | /* Update hwmode for vblank functions */ |
| 12564 | if (crtc->state->active) |
| 12565 | crtc->hwmode = crtc->state->adjusted_mode; |
| 12566 | else |
| 12567 | crtc->hwmode.crtc_clock = 0; |
| 12568 | |
| 12569 | /* |
| 12570 | * Update legacy state to satisfy fbc code. This can |
| 12571 | * be removed when fbc uses the atomic state. |
| 12572 | */ |
| 12573 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { |
| 12574 | struct drm_plane_state *plane_state = crtc->primary->state; |
| 12575 | |
| 12576 | crtc->primary->fb = plane_state->fb; |
| 12577 | crtc->x = plane_state->src_x >> 16; |
| 12578 | crtc->y = plane_state->src_y >> 16; |
| 12579 | } |
| 12580 | } |
| 12581 | } |
| 12582 | |
| 12583 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
| 12584 | { |
| 12585 | int diff; |
| 12586 | |
| 12587 | if (clock1 == clock2) |
| 12588 | return true; |
| 12589 | |
| 12590 | if (!clock1 || !clock2) |
| 12591 | return false; |
| 12592 | |
| 12593 | diff = abs(clock1 - clock2); |
| 12594 | |
| 12595 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) |
| 12596 | return true; |
| 12597 | |
| 12598 | return false; |
| 12599 | } |
| 12600 | |
| 12601 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
| 12602 | list_for_each_entry((intel_crtc), \ |
| 12603 | &(dev)->mode_config.crtc_list, \ |
| 12604 | base.head) \ |
| 12605 | for_each_if (mask & (1 <<(intel_crtc)->pipe)) |
| 12606 | |
| 12607 | static bool |
| 12608 | intel_compare_m_n(unsigned int m, unsigned int n, |
| 12609 | unsigned int m2, unsigned int n2, |
| 12610 | bool exact) |
| 12611 | { |
| 12612 | if (m == m2 && n == n2) |
| 12613 | return true; |
| 12614 | |
| 12615 | if (exact || !m || !n || !m2 || !n2) |
| 12616 | return false; |
| 12617 | |
| 12618 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); |
| 12619 | |
| 12620 | if (n > n2) { |
| 12621 | while (n > n2) { |
| 12622 | m2 <<= 1; |
| 12623 | n2 <<= 1; |
| 12624 | } |
| 12625 | } else if (n < n2) { |
| 12626 | while (n < n2) { |
| 12627 | m <<= 1; |
| 12628 | n <<= 1; |
| 12629 | } |
| 12630 | } |
| 12631 | |
| 12632 | if (n != n2) |
| 12633 | return false; |
| 12634 | |
| 12635 | return intel_fuzzy_clock_check(m, m2); |
| 12636 | } |
| 12637 | |
| 12638 | static bool |
| 12639 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, |
| 12640 | struct intel_link_m_n *m2_n2, |
| 12641 | bool adjust) |
| 12642 | { |
| 12643 | if (m_n->tu == m2_n2->tu && |
| 12644 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, |
| 12645 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && |
| 12646 | intel_compare_m_n(m_n->link_m, m_n->link_n, |
| 12647 | m2_n2->link_m, m2_n2->link_n, !adjust)) { |
| 12648 | if (adjust) |
| 12649 | *m2_n2 = *m_n; |
| 12650 | |
| 12651 | return true; |
| 12652 | } |
| 12653 | |
| 12654 | return false; |
| 12655 | } |
| 12656 | |
| 12657 | static bool |
| 12658 | intel_pipe_config_compare(struct drm_device *dev, |
| 12659 | struct intel_crtc_state *current_config, |
| 12660 | struct intel_crtc_state *pipe_config, |
| 12661 | bool adjust) |
| 12662 | { |
| 12663 | bool ret = true; |
| 12664 | |
| 12665 | #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ |
| 12666 | do { \ |
| 12667 | if (!adjust) \ |
| 12668 | DRM_ERROR(fmt, ##__VA_ARGS__); \ |
| 12669 | else \ |
| 12670 | DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ |
| 12671 | } while (0) |
| 12672 | |
| 12673 | #define PIPE_CONF_CHECK_X(name) \ |
| 12674 | if (current_config->name != pipe_config->name) { \ |
| 12675 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
| 12676 | "(expected 0x%08x, found 0x%08x)\n", \ |
| 12677 | current_config->name, \ |
| 12678 | pipe_config->name); \ |
| 12679 | ret = false; \ |
| 12680 | } |
| 12681 | |
| 12682 | #define PIPE_CONF_CHECK_I(name) \ |
| 12683 | if (current_config->name != pipe_config->name) { \ |
| 12684 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
| 12685 | "(expected %i, found %i)\n", \ |
| 12686 | current_config->name, \ |
| 12687 | pipe_config->name); \ |
| 12688 | ret = false; \ |
| 12689 | } |
| 12690 | |
| 12691 | #define PIPE_CONF_CHECK_M_N(name) \ |
| 12692 | if (!intel_compare_link_m_n(¤t_config->name, \ |
| 12693 | &pipe_config->name,\ |
| 12694 | adjust)) { \ |
| 12695 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
| 12696 | "(expected tu %i gmch %i/%i link %i/%i, " \ |
| 12697 | "found tu %i, gmch %i/%i link %i/%i)\n", \ |
| 12698 | current_config->name.tu, \ |
| 12699 | current_config->name.gmch_m, \ |
| 12700 | current_config->name.gmch_n, \ |
| 12701 | current_config->name.link_m, \ |
| 12702 | current_config->name.link_n, \ |
| 12703 | pipe_config->name.tu, \ |
| 12704 | pipe_config->name.gmch_m, \ |
| 12705 | pipe_config->name.gmch_n, \ |
| 12706 | pipe_config->name.link_m, \ |
| 12707 | pipe_config->name.link_n); \ |
| 12708 | ret = false; \ |
| 12709 | } |
| 12710 | |
| 12711 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ |
| 12712 | if (!intel_compare_link_m_n(¤t_config->name, \ |
| 12713 | &pipe_config->name, adjust) && \ |
| 12714 | !intel_compare_link_m_n(¤t_config->alt_name, \ |
| 12715 | &pipe_config->name, adjust)) { \ |
| 12716 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
| 12717 | "(expected tu %i gmch %i/%i link %i/%i, " \ |
| 12718 | "or tu %i gmch %i/%i link %i/%i, " \ |
| 12719 | "found tu %i, gmch %i/%i link %i/%i)\n", \ |
| 12720 | current_config->name.tu, \ |
| 12721 | current_config->name.gmch_m, \ |
| 12722 | current_config->name.gmch_n, \ |
| 12723 | current_config->name.link_m, \ |
| 12724 | current_config->name.link_n, \ |
| 12725 | current_config->alt_name.tu, \ |
| 12726 | current_config->alt_name.gmch_m, \ |
| 12727 | current_config->alt_name.gmch_n, \ |
| 12728 | current_config->alt_name.link_m, \ |
| 12729 | current_config->alt_name.link_n, \ |
| 12730 | pipe_config->name.tu, \ |
| 12731 | pipe_config->name.gmch_m, \ |
| 12732 | pipe_config->name.gmch_n, \ |
| 12733 | pipe_config->name.link_m, \ |
| 12734 | pipe_config->name.link_n); \ |
| 12735 | ret = false; \ |
| 12736 | } |
| 12737 | |
| 12738 | /* This is required for BDW+ where there is only one set of registers for |
| 12739 | * switching between high and low RR. |
| 12740 | * This macro can be used whenever a comparison has to be made between one |
| 12741 | * hw state and multiple sw state variables. |
| 12742 | */ |
| 12743 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ |
| 12744 | if ((current_config->name != pipe_config->name) && \ |
| 12745 | (current_config->alt_name != pipe_config->name)) { \ |
| 12746 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
| 12747 | "(expected %i or %i, found %i)\n", \ |
| 12748 | current_config->name, \ |
| 12749 | current_config->alt_name, \ |
| 12750 | pipe_config->name); \ |
| 12751 | ret = false; \ |
| 12752 | } |
| 12753 | |
| 12754 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
| 12755 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ |
| 12756 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ |
| 12757 | "(expected %i, found %i)\n", \ |
| 12758 | current_config->name & (mask), \ |
| 12759 | pipe_config->name & (mask)); \ |
| 12760 | ret = false; \ |
| 12761 | } |
| 12762 | |
| 12763 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
| 12764 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ |
| 12765 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
| 12766 | "(expected %i, found %i)\n", \ |
| 12767 | current_config->name, \ |
| 12768 | pipe_config->name); \ |
| 12769 | ret = false; \ |
| 12770 | } |
| 12771 | |
| 12772 | #define PIPE_CONF_QUIRK(quirk) \ |
| 12773 | ((current_config->quirks | pipe_config->quirks) & (quirk)) |
| 12774 | |
| 12775 | PIPE_CONF_CHECK_I(cpu_transcoder); |
| 12776 | |
| 12777 | PIPE_CONF_CHECK_I(has_pch_encoder); |
| 12778 | PIPE_CONF_CHECK_I(fdi_lanes); |
| 12779 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
| 12780 | |
| 12781 | PIPE_CONF_CHECK_I(has_dp_encoder); |
| 12782 | PIPE_CONF_CHECK_I(lane_count); |
| 12783 | |
| 12784 | if (INTEL_INFO(dev)->gen < 8) { |
| 12785 | PIPE_CONF_CHECK_M_N(dp_m_n); |
| 12786 | |
| 12787 | if (current_config->has_drrs) |
| 12788 | PIPE_CONF_CHECK_M_N(dp_m2_n2); |
| 12789 | } else |
| 12790 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); |
| 12791 | |
| 12792 | PIPE_CONF_CHECK_I(has_dsi_encoder); |
| 12793 | |
| 12794 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
| 12795 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); |
| 12796 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); |
| 12797 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); |
| 12798 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); |
| 12799 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); |
| 12800 | |
| 12801 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
| 12802 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); |
| 12803 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); |
| 12804 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); |
| 12805 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); |
| 12806 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); |
| 12807 | |
| 12808 | PIPE_CONF_CHECK_I(pixel_multiplier); |
| 12809 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
| 12810 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
| 12811 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
| 12812 | PIPE_CONF_CHECK_I(limited_color_range); |
| 12813 | PIPE_CONF_CHECK_I(has_infoframe); |
| 12814 | |
| 12815 | PIPE_CONF_CHECK_I(has_audio); |
| 12816 | |
| 12817 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
| 12818 | DRM_MODE_FLAG_INTERLACE); |
| 12819 | |
| 12820 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
| 12821 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
| 12822 | DRM_MODE_FLAG_PHSYNC); |
| 12823 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
| 12824 | DRM_MODE_FLAG_NHSYNC); |
| 12825 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
| 12826 | DRM_MODE_FLAG_PVSYNC); |
| 12827 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
| 12828 | DRM_MODE_FLAG_NVSYNC); |
| 12829 | } |
| 12830 | |
| 12831 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
| 12832 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
| 12833 | if (INTEL_INFO(dev)->gen < 4) |
| 12834 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); |
| 12835 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
| 12836 | |
| 12837 | if (!adjust) { |
| 12838 | PIPE_CONF_CHECK_I(pipe_src_w); |
| 12839 | PIPE_CONF_CHECK_I(pipe_src_h); |
| 12840 | |
| 12841 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
| 12842 | if (current_config->pch_pfit.enabled) { |
| 12843 | PIPE_CONF_CHECK_X(pch_pfit.pos); |
| 12844 | PIPE_CONF_CHECK_X(pch_pfit.size); |
| 12845 | } |
| 12846 | |
| 12847 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
| 12848 | } |
| 12849 | |
| 12850 | /* BDW+ don't expose a synchronous way to read the state */ |
| 12851 | if (IS_HASWELL(dev)) |
| 12852 | PIPE_CONF_CHECK_I(ips_enabled); |
| 12853 | |
| 12854 | PIPE_CONF_CHECK_I(double_wide); |
| 12855 | |
| 12856 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
| 12857 | |
| 12858 | PIPE_CONF_CHECK_I(shared_dpll); |
| 12859 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
| 12860 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
| 12861 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
| 12862 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); |
| 12863 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
| 12864 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
| 12865 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
| 12866 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); |
| 12867 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); |
| 12868 | |
| 12869 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
| 12870 | PIPE_CONF_CHECK_I(pipe_bpp); |
| 12871 | |
| 12872 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
| 12873 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
| 12874 | |
| 12875 | #undef PIPE_CONF_CHECK_X |
| 12876 | #undef PIPE_CONF_CHECK_I |
| 12877 | #undef PIPE_CONF_CHECK_I_ALT |
| 12878 | #undef PIPE_CONF_CHECK_FLAGS |
| 12879 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
| 12880 | #undef PIPE_CONF_QUIRK |
| 12881 | #undef INTEL_ERR_OR_DBG_KMS |
| 12882 | |
| 12883 | return ret; |
| 12884 | } |
| 12885 | |
| 12886 | static void check_wm_state(struct drm_device *dev) |
| 12887 | { |
| 12888 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 12889 | struct skl_ddb_allocation hw_ddb, *sw_ddb; |
| 12890 | struct intel_crtc *intel_crtc; |
| 12891 | int plane; |
| 12892 | |
| 12893 | if (INTEL_INFO(dev)->gen < 9) |
| 12894 | return; |
| 12895 | |
| 12896 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); |
| 12897 | sw_ddb = &dev_priv->wm.skl_hw.ddb; |
| 12898 | |
| 12899 | for_each_intel_crtc(dev, intel_crtc) { |
| 12900 | struct skl_ddb_entry *hw_entry, *sw_entry; |
| 12901 | const enum pipe pipe = intel_crtc->pipe; |
| 12902 | |
| 12903 | if (!intel_crtc->active) |
| 12904 | continue; |
| 12905 | |
| 12906 | /* planes */ |
| 12907 | for_each_plane(dev_priv, pipe, plane) { |
| 12908 | hw_entry = &hw_ddb.plane[pipe][plane]; |
| 12909 | sw_entry = &sw_ddb->plane[pipe][plane]; |
| 12910 | |
| 12911 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) |
| 12912 | continue; |
| 12913 | |
| 12914 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " |
| 12915 | "(expected (%u,%u), found (%u,%u))\n", |
| 12916 | pipe_name(pipe), plane + 1, |
| 12917 | sw_entry->start, sw_entry->end, |
| 12918 | hw_entry->start, hw_entry->end); |
| 12919 | } |
| 12920 | |
| 12921 | /* cursor */ |
| 12922 | hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; |
| 12923 | sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; |
| 12924 | |
| 12925 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) |
| 12926 | continue; |
| 12927 | |
| 12928 | DRM_ERROR("mismatch in DDB state pipe %c cursor " |
| 12929 | "(expected (%u,%u), found (%u,%u))\n", |
| 12930 | pipe_name(pipe), |
| 12931 | sw_entry->start, sw_entry->end, |
| 12932 | hw_entry->start, hw_entry->end); |
| 12933 | } |
| 12934 | } |
| 12935 | |
| 12936 | static void |
| 12937 | check_connector_state(struct drm_device *dev, |
| 12938 | struct drm_atomic_state *old_state) |
| 12939 | { |
| 12940 | struct drm_connector_state *old_conn_state; |
| 12941 | struct drm_connector *connector; |
| 12942 | int i; |
| 12943 | |
| 12944 | for_each_connector_in_state(old_state, connector, old_conn_state, i) { |
| 12945 | struct drm_encoder *encoder = connector->encoder; |
| 12946 | struct drm_connector_state *state = connector->state; |
| 12947 | |
| 12948 | /* This also checks the encoder/connector hw state with the |
| 12949 | * ->get_hw_state callbacks. */ |
| 12950 | intel_connector_check_state(to_intel_connector(connector)); |
| 12951 | |
| 12952 | I915_STATE_WARN(state->best_encoder != encoder, |
| 12953 | "connector's atomic encoder doesn't match legacy encoder\n"); |
| 12954 | } |
| 12955 | } |
| 12956 | |
| 12957 | static void |
| 12958 | check_encoder_state(struct drm_device *dev) |
| 12959 | { |
| 12960 | struct intel_encoder *encoder; |
| 12961 | struct intel_connector *connector; |
| 12962 | |
| 12963 | for_each_intel_encoder(dev, encoder) { |
| 12964 | bool enabled = false; |
| 12965 | enum pipe pipe; |
| 12966 | |
| 12967 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", |
| 12968 | encoder->base.base.id, |
| 12969 | encoder->base.name); |
| 12970 | |
| 12971 | for_each_intel_connector(dev, connector) { |
| 12972 | if (connector->base.state->best_encoder != &encoder->base) |
| 12973 | continue; |
| 12974 | enabled = true; |
| 12975 | |
| 12976 | I915_STATE_WARN(connector->base.state->crtc != |
| 12977 | encoder->base.crtc, |
| 12978 | "connector's crtc doesn't match encoder crtc\n"); |
| 12979 | } |
| 12980 | |
| 12981 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
| 12982 | "encoder's enabled state mismatch " |
| 12983 | "(expected %i, found %i)\n", |
| 12984 | !!encoder->base.crtc, enabled); |
| 12985 | |
| 12986 | if (!encoder->base.crtc) { |
| 12987 | bool active; |
| 12988 | |
| 12989 | active = encoder->get_hw_state(encoder, &pipe); |
| 12990 | I915_STATE_WARN(active, |
| 12991 | "encoder detached but still enabled on pipe %c.\n", |
| 12992 | pipe_name(pipe)); |
| 12993 | } |
| 12994 | } |
| 12995 | } |
| 12996 | |
| 12997 | static void |
| 12998 | check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state) |
| 12999 | { |
| 13000 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 13001 | struct intel_encoder *encoder; |
| 13002 | struct drm_crtc_state *old_crtc_state; |
| 13003 | struct drm_crtc *crtc; |
| 13004 | int i; |
| 13005 | |
| 13006 | for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) { |
| 13007 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 13008 | struct intel_crtc_state *pipe_config, *sw_config; |
| 13009 | bool active; |
| 13010 | |
| 13011 | if (!needs_modeset(crtc->state) && |
| 13012 | !to_intel_crtc_state(crtc->state)->update_pipe) |
| 13013 | continue; |
| 13014 | |
| 13015 | __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state); |
| 13016 | pipe_config = to_intel_crtc_state(old_crtc_state); |
| 13017 | memset(pipe_config, 0, sizeof(*pipe_config)); |
| 13018 | pipe_config->base.crtc = crtc; |
| 13019 | pipe_config->base.state = old_state; |
| 13020 | |
| 13021 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
| 13022 | crtc->base.id); |
| 13023 | |
| 13024 | active = dev_priv->display.get_pipe_config(intel_crtc, |
| 13025 | pipe_config); |
| 13026 | |
| 13027 | /* hw state is inconsistent with the pipe quirk */ |
| 13028 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
| 13029 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) |
| 13030 | active = crtc->state->active; |
| 13031 | |
| 13032 | I915_STATE_WARN(crtc->state->active != active, |
| 13033 | "crtc active state doesn't match with hw state " |
| 13034 | "(expected %i, found %i)\n", crtc->state->active, active); |
| 13035 | |
| 13036 | I915_STATE_WARN(intel_crtc->active != crtc->state->active, |
| 13037 | "transitional active state does not match atomic hw state " |
| 13038 | "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active); |
| 13039 | |
| 13040 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
| 13041 | enum pipe pipe; |
| 13042 | |
| 13043 | active = encoder->get_hw_state(encoder, &pipe); |
| 13044 | I915_STATE_WARN(active != crtc->state->active, |
| 13045 | "[ENCODER:%i] active %i with crtc active %i\n", |
| 13046 | encoder->base.base.id, active, crtc->state->active); |
| 13047 | |
| 13048 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, |
| 13049 | "Encoder connected to wrong pipe %c\n", |
| 13050 | pipe_name(pipe)); |
| 13051 | |
| 13052 | if (active) |
| 13053 | encoder->get_config(encoder, pipe_config); |
| 13054 | } |
| 13055 | |
| 13056 | if (!crtc->state->active) |
| 13057 | continue; |
| 13058 | |
| 13059 | sw_config = to_intel_crtc_state(crtc->state); |
| 13060 | if (!intel_pipe_config_compare(dev, sw_config, |
| 13061 | pipe_config, false)) { |
| 13062 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
| 13063 | intel_dump_pipe_config(intel_crtc, pipe_config, |
| 13064 | "[hw state]"); |
| 13065 | intel_dump_pipe_config(intel_crtc, sw_config, |
| 13066 | "[sw state]"); |
| 13067 | } |
| 13068 | } |
| 13069 | } |
| 13070 | |
| 13071 | static void |
| 13072 | check_shared_dpll_state(struct drm_device *dev) |
| 13073 | { |
| 13074 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 13075 | struct intel_crtc *crtc; |
| 13076 | struct intel_dpll_hw_state dpll_hw_state; |
| 13077 | int i; |
| 13078 | |
| 13079 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
| 13080 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
| 13081 | int enabled_crtcs = 0, active_crtcs = 0; |
| 13082 | bool active; |
| 13083 | |
| 13084 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
| 13085 | |
| 13086 | DRM_DEBUG_KMS("%s\n", pll->name); |
| 13087 | |
| 13088 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); |
| 13089 | |
| 13090 | I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask), |
| 13091 | "more active pll users than references: %i vs %i\n", |
| 13092 | pll->active, hweight32(pll->config.crtc_mask)); |
| 13093 | I915_STATE_WARN(pll->active && !pll->on, |
| 13094 | "pll in active use but not on in sw tracking\n"); |
| 13095 | I915_STATE_WARN(pll->on && !pll->active, |
| 13096 | "pll in on but not on in use in sw tracking\n"); |
| 13097 | I915_STATE_WARN(pll->on != active, |
| 13098 | "pll on state mismatch (expected %i, found %i)\n", |
| 13099 | pll->on, active); |
| 13100 | |
| 13101 | for_each_intel_crtc(dev, crtc) { |
| 13102 | if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll) |
| 13103 | enabled_crtcs++; |
| 13104 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) |
| 13105 | active_crtcs++; |
| 13106 | } |
| 13107 | I915_STATE_WARN(pll->active != active_crtcs, |
| 13108 | "pll active crtcs mismatch (expected %i, found %i)\n", |
| 13109 | pll->active, active_crtcs); |
| 13110 | I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, |
| 13111 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
| 13112 | hweight32(pll->config.crtc_mask), enabled_crtcs); |
| 13113 | |
| 13114 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
| 13115 | sizeof(dpll_hw_state)), |
| 13116 | "pll hw state mismatch\n"); |
| 13117 | } |
| 13118 | } |
| 13119 | |
| 13120 | static void |
| 13121 | intel_modeset_check_state(struct drm_device *dev, |
| 13122 | struct drm_atomic_state *old_state) |
| 13123 | { |
| 13124 | check_wm_state(dev); |
| 13125 | check_connector_state(dev, old_state); |
| 13126 | check_encoder_state(dev); |
| 13127 | check_crtc_state(dev, old_state); |
| 13128 | check_shared_dpll_state(dev); |
| 13129 | } |
| 13130 | |
| 13131 | void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, |
| 13132 | int dotclock) |
| 13133 | { |
| 13134 | /* |
| 13135 | * FDI already provided one idea for the dotclock. |
| 13136 | * Yell if the encoder disagrees. |
| 13137 | */ |
| 13138 | WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock), |
| 13139 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
| 13140 | pipe_config->base.adjusted_mode.crtc_clock, dotclock); |
| 13141 | } |
| 13142 | |
| 13143 | static void update_scanline_offset(struct intel_crtc *crtc) |
| 13144 | { |
| 13145 | struct drm_device *dev = crtc->base.dev; |
| 13146 | |
| 13147 | /* |
| 13148 | * The scanline counter increments at the leading edge of hsync. |
| 13149 | * |
| 13150 | * On most platforms it starts counting from vtotal-1 on the |
| 13151 | * first active line. That means the scanline counter value is |
| 13152 | * always one less than what we would expect. Ie. just after |
| 13153 | * start of vblank, which also occurs at start of hsync (on the |
| 13154 | * last active line), the scanline counter will read vblank_start-1. |
| 13155 | * |
| 13156 | * On gen2 the scanline counter starts counting from 1 instead |
| 13157 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 |
| 13158 | * to keep the value positive), instead of adding one. |
| 13159 | * |
| 13160 | * On HSW+ the behaviour of the scanline counter depends on the output |
| 13161 | * type. For DP ports it behaves like most other platforms, but on HDMI |
| 13162 | * there's an extra 1 line difference. So we need to add two instead of |
| 13163 | * one to the value. |
| 13164 | */ |
| 13165 | if (IS_GEN2(dev)) { |
| 13166 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
| 13167 | int vtotal; |
| 13168 | |
| 13169 | vtotal = adjusted_mode->crtc_vtotal; |
| 13170 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) |
| 13171 | vtotal /= 2; |
| 13172 | |
| 13173 | crtc->scanline_offset = vtotal - 1; |
| 13174 | } else if (HAS_DDI(dev) && |
| 13175 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
| 13176 | crtc->scanline_offset = 2; |
| 13177 | } else |
| 13178 | crtc->scanline_offset = 1; |
| 13179 | } |
| 13180 | |
| 13181 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
| 13182 | { |
| 13183 | struct drm_device *dev = state->dev; |
| 13184 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 13185 | struct intel_shared_dpll_config *shared_dpll = NULL; |
| 13186 | struct intel_crtc *intel_crtc; |
| 13187 | struct intel_crtc_state *intel_crtc_state; |
| 13188 | struct drm_crtc *crtc; |
| 13189 | struct drm_crtc_state *crtc_state; |
| 13190 | int i; |
| 13191 | |
| 13192 | if (!dev_priv->display.crtc_compute_clock) |
| 13193 | return; |
| 13194 | |
| 13195 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
| 13196 | int dpll; |
| 13197 | |
| 13198 | intel_crtc = to_intel_crtc(crtc); |
| 13199 | intel_crtc_state = to_intel_crtc_state(crtc_state); |
| 13200 | dpll = intel_crtc_state->shared_dpll; |
| 13201 | |
| 13202 | if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE) |
| 13203 | continue; |
| 13204 | |
| 13205 | intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE; |
| 13206 | |
| 13207 | if (!shared_dpll) |
| 13208 | shared_dpll = intel_atomic_get_shared_dpll_state(state); |
| 13209 | |
| 13210 | shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe); |
| 13211 | } |
| 13212 | } |
| 13213 | |
| 13214 | /* |
| 13215 | * This implements the workaround described in the "notes" section of the mode |
| 13216 | * set sequence documentation. When going from no pipes or single pipe to |
| 13217 | * multiple pipes, and planes are enabled after the pipe, we need to wait at |
| 13218 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. |
| 13219 | */ |
| 13220 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) |
| 13221 | { |
| 13222 | struct drm_crtc_state *crtc_state; |
| 13223 | struct intel_crtc *intel_crtc; |
| 13224 | struct drm_crtc *crtc; |
| 13225 | struct intel_crtc_state *first_crtc_state = NULL; |
| 13226 | struct intel_crtc_state *other_crtc_state = NULL; |
| 13227 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; |
| 13228 | int i; |
| 13229 | |
| 13230 | /* look at all crtc's that are going to be enabled in during modeset */ |
| 13231 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
| 13232 | intel_crtc = to_intel_crtc(crtc); |
| 13233 | |
| 13234 | if (!crtc_state->active || !needs_modeset(crtc_state)) |
| 13235 | continue; |
| 13236 | |
| 13237 | if (first_crtc_state) { |
| 13238 | other_crtc_state = to_intel_crtc_state(crtc_state); |
| 13239 | break; |
| 13240 | } else { |
| 13241 | first_crtc_state = to_intel_crtc_state(crtc_state); |
| 13242 | first_pipe = intel_crtc->pipe; |
| 13243 | } |
| 13244 | } |
| 13245 | |
| 13246 | /* No workaround needed? */ |
| 13247 | if (!first_crtc_state) |
| 13248 | return 0; |
| 13249 | |
| 13250 | /* w/a possibly needed, check how many crtc's are already enabled. */ |
| 13251 | for_each_intel_crtc(state->dev, intel_crtc) { |
| 13252 | struct intel_crtc_state *pipe_config; |
| 13253 | |
| 13254 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); |
| 13255 | if (IS_ERR(pipe_config)) |
| 13256 | return PTR_ERR(pipe_config); |
| 13257 | |
| 13258 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; |
| 13259 | |
| 13260 | if (!pipe_config->base.active || |
| 13261 | needs_modeset(&pipe_config->base)) |
| 13262 | continue; |
| 13263 | |
| 13264 | /* 2 or more enabled crtcs means no need for w/a */ |
| 13265 | if (enabled_pipe != INVALID_PIPE) |
| 13266 | return 0; |
| 13267 | |
| 13268 | enabled_pipe = intel_crtc->pipe; |
| 13269 | } |
| 13270 | |
| 13271 | if (enabled_pipe != INVALID_PIPE) |
| 13272 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; |
| 13273 | else if (other_crtc_state) |
| 13274 | other_crtc_state->hsw_workaround_pipe = first_pipe; |
| 13275 | |
| 13276 | return 0; |
| 13277 | } |
| 13278 | |
| 13279 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
| 13280 | { |
| 13281 | struct drm_crtc *crtc; |
| 13282 | struct drm_crtc_state *crtc_state; |
| 13283 | int ret = 0; |
| 13284 | |
| 13285 | /* add all active pipes to the state */ |
| 13286 | for_each_crtc(state->dev, crtc) { |
| 13287 | crtc_state = drm_atomic_get_crtc_state(state, crtc); |
| 13288 | if (IS_ERR(crtc_state)) |
| 13289 | return PTR_ERR(crtc_state); |
| 13290 | |
| 13291 | if (!crtc_state->active || needs_modeset(crtc_state)) |
| 13292 | continue; |
| 13293 | |
| 13294 | crtc_state->mode_changed = true; |
| 13295 | |
| 13296 | ret = drm_atomic_add_affected_connectors(state, crtc); |
| 13297 | if (ret) |
| 13298 | break; |
| 13299 | |
| 13300 | ret = drm_atomic_add_affected_planes(state, crtc); |
| 13301 | if (ret) |
| 13302 | break; |
| 13303 | } |
| 13304 | |
| 13305 | return ret; |
| 13306 | } |
| 13307 | |
| 13308 | static int intel_modeset_checks(struct drm_atomic_state *state) |
| 13309 | { |
| 13310 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
| 13311 | struct drm_i915_private *dev_priv = state->dev->dev_private; |
| 13312 | struct drm_crtc *crtc; |
| 13313 | struct drm_crtc_state *crtc_state; |
| 13314 | int ret = 0, i; |
| 13315 | |
| 13316 | if (!check_digital_port_conflicts(state)) { |
| 13317 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); |
| 13318 | return -EINVAL; |
| 13319 | } |
| 13320 | |
| 13321 | intel_state->modeset = true; |
| 13322 | intel_state->active_crtcs = dev_priv->active_crtcs; |
| 13323 | |
| 13324 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
| 13325 | if (crtc_state->active) |
| 13326 | intel_state->active_crtcs |= 1 << i; |
| 13327 | else |
| 13328 | intel_state->active_crtcs &= ~(1 << i); |
| 13329 | } |
| 13330 | |
| 13331 | /* |
| 13332 | * See if the config requires any additional preparation, e.g. |
| 13333 | * to adjust global state with pipes off. We need to do this |
| 13334 | * here so we can get the modeset_pipe updated config for the new |
| 13335 | * mode set on this crtc. For other crtcs we need to use the |
| 13336 | * adjusted_mode bits in the crtc directly. |
| 13337 | */ |
| 13338 | if (dev_priv->display.modeset_calc_cdclk) { |
| 13339 | ret = dev_priv->display.modeset_calc_cdclk(state); |
| 13340 | |
| 13341 | if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq) |
| 13342 | ret = intel_modeset_all_pipes(state); |
| 13343 | |
| 13344 | if (ret < 0) |
| 13345 | return ret; |
| 13346 | } else |
| 13347 | to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq; |
| 13348 | |
| 13349 | intel_modeset_clear_plls(state); |
| 13350 | |
| 13351 | if (IS_HASWELL(dev_priv)) |
| 13352 | return haswell_mode_set_planes_workaround(state); |
| 13353 | |
| 13354 | return 0; |
| 13355 | } |
| 13356 | |
| 13357 | /* |
| 13358 | * Handle calculation of various watermark data at the end of the atomic check |
| 13359 | * phase. The code here should be run after the per-crtc and per-plane 'check' |
| 13360 | * handlers to ensure that all derived state has been updated. |
| 13361 | */ |
| 13362 | static void calc_watermark_data(struct drm_atomic_state *state) |
| 13363 | { |
| 13364 | struct drm_device *dev = state->dev; |
| 13365 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
| 13366 | struct drm_crtc *crtc; |
| 13367 | struct drm_crtc_state *cstate; |
| 13368 | struct drm_plane *plane; |
| 13369 | struct drm_plane_state *pstate; |
| 13370 | |
| 13371 | /* |
| 13372 | * Calculate watermark configuration details now that derived |
| 13373 | * plane/crtc state is all properly updated. |
| 13374 | */ |
| 13375 | drm_for_each_crtc(crtc, dev) { |
| 13376 | cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?: |
| 13377 | crtc->state; |
| 13378 | |
| 13379 | if (cstate->active) |
| 13380 | intel_state->wm_config.num_pipes_active++; |
| 13381 | } |
| 13382 | drm_for_each_legacy_plane(plane, dev) { |
| 13383 | pstate = drm_atomic_get_existing_plane_state(state, plane) ?: |
| 13384 | plane->state; |
| 13385 | |
| 13386 | if (!to_intel_plane_state(pstate)->visible) |
| 13387 | continue; |
| 13388 | |
| 13389 | intel_state->wm_config.sprites_enabled = true; |
| 13390 | if (pstate->crtc_w != pstate->src_w >> 16 || |
| 13391 | pstate->crtc_h != pstate->src_h >> 16) |
| 13392 | intel_state->wm_config.sprites_scaled = true; |
| 13393 | } |
| 13394 | } |
| 13395 | |
| 13396 | /** |
| 13397 | * intel_atomic_check - validate state object |
| 13398 | * @dev: drm device |
| 13399 | * @state: state to validate |
| 13400 | */ |
| 13401 | static int intel_atomic_check(struct drm_device *dev, |
| 13402 | struct drm_atomic_state *state) |
| 13403 | { |
| 13404 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
| 13405 | struct drm_crtc *crtc; |
| 13406 | struct drm_crtc_state *crtc_state; |
| 13407 | int ret, i; |
| 13408 | bool any_ms = false; |
| 13409 | |
| 13410 | ret = drm_atomic_helper_check_modeset(dev, state); |
| 13411 | if (ret) |
| 13412 | return ret; |
| 13413 | |
| 13414 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
| 13415 | struct intel_crtc_state *pipe_config = |
| 13416 | to_intel_crtc_state(crtc_state); |
| 13417 | |
| 13418 | memset(&to_intel_crtc(crtc)->atomic, 0, |
| 13419 | sizeof(struct intel_crtc_atomic_commit)); |
| 13420 | |
| 13421 | /* Catch I915_MODE_FLAG_INHERITED */ |
| 13422 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) |
| 13423 | crtc_state->mode_changed = true; |
| 13424 | |
| 13425 | if (!crtc_state->enable) { |
| 13426 | if (needs_modeset(crtc_state)) |
| 13427 | any_ms = true; |
| 13428 | continue; |
| 13429 | } |
| 13430 | |
| 13431 | if (!needs_modeset(crtc_state)) |
| 13432 | continue; |
| 13433 | |
| 13434 | /* FIXME: For only active_changed we shouldn't need to do any |
| 13435 | * state recomputation at all. */ |
| 13436 | |
| 13437 | ret = drm_atomic_add_affected_connectors(state, crtc); |
| 13438 | if (ret) |
| 13439 | return ret; |
| 13440 | |
| 13441 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
| 13442 | if (ret) |
| 13443 | return ret; |
| 13444 | |
| 13445 | if (i915.fastboot && |
| 13446 | intel_pipe_config_compare(state->dev, |
| 13447 | to_intel_crtc_state(crtc->state), |
| 13448 | pipe_config, true)) { |
| 13449 | crtc_state->mode_changed = false; |
| 13450 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
| 13451 | } |
| 13452 | |
| 13453 | if (needs_modeset(crtc_state)) { |
| 13454 | any_ms = true; |
| 13455 | |
| 13456 | ret = drm_atomic_add_affected_planes(state, crtc); |
| 13457 | if (ret) |
| 13458 | return ret; |
| 13459 | } |
| 13460 | |
| 13461 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
| 13462 | needs_modeset(crtc_state) ? |
| 13463 | "[modeset]" : "[fastset]"); |
| 13464 | } |
| 13465 | |
| 13466 | if (any_ms) { |
| 13467 | ret = intel_modeset_checks(state); |
| 13468 | |
| 13469 | if (ret) |
| 13470 | return ret; |
| 13471 | } else |
| 13472 | intel_state->cdclk = to_i915(state->dev)->cdclk_freq; |
| 13473 | |
| 13474 | ret = drm_atomic_helper_check_planes(state->dev, state); |
| 13475 | if (ret) |
| 13476 | return ret; |
| 13477 | |
| 13478 | calc_watermark_data(state); |
| 13479 | |
| 13480 | return 0; |
| 13481 | } |
| 13482 | |
| 13483 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
| 13484 | struct drm_atomic_state *state, |
| 13485 | bool async) |
| 13486 | { |
| 13487 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 13488 | struct drm_plane_state *plane_state; |
| 13489 | struct drm_crtc_state *crtc_state; |
| 13490 | struct drm_plane *plane; |
| 13491 | struct drm_crtc *crtc; |
| 13492 | int i, ret; |
| 13493 | |
| 13494 | if (async) { |
| 13495 | DRM_DEBUG_KMS("i915 does not yet support async commit\n"); |
| 13496 | return -EINVAL; |
| 13497 | } |
| 13498 | |
| 13499 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
| 13500 | ret = intel_crtc_wait_for_pending_flips(crtc); |
| 13501 | if (ret) |
| 13502 | return ret; |
| 13503 | |
| 13504 | if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) |
| 13505 | flush_workqueue(dev_priv->wq); |
| 13506 | } |
| 13507 | |
| 13508 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 13509 | if (ret) |
| 13510 | return ret; |
| 13511 | |
| 13512 | ret = drm_atomic_helper_prepare_planes(dev, state); |
| 13513 | if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) { |
| 13514 | u32 reset_counter; |
| 13515 | |
| 13516 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
| 13517 | mutex_unlock(&dev->struct_mutex); |
| 13518 | |
| 13519 | for_each_plane_in_state(state, plane, plane_state, i) { |
| 13520 | struct intel_plane_state *intel_plane_state = |
| 13521 | to_intel_plane_state(plane_state); |
| 13522 | |
| 13523 | if (!intel_plane_state->wait_req) |
| 13524 | continue; |
| 13525 | |
| 13526 | ret = __i915_wait_request(intel_plane_state->wait_req, |
| 13527 | reset_counter, true, |
| 13528 | NULL, NULL); |
| 13529 | |
| 13530 | /* Swallow -EIO errors to allow updates during hw lockup. */ |
| 13531 | if (ret == -EIO) |
| 13532 | ret = 0; |
| 13533 | |
| 13534 | if (ret) |
| 13535 | break; |
| 13536 | } |
| 13537 | |
| 13538 | if (!ret) |
| 13539 | return 0; |
| 13540 | |
| 13541 | mutex_lock(&dev->struct_mutex); |
| 13542 | drm_atomic_helper_cleanup_planes(dev, state); |
| 13543 | } |
| 13544 | |
| 13545 | mutex_unlock(&dev->struct_mutex); |
| 13546 | return ret; |
| 13547 | } |
| 13548 | |
| 13549 | /** |
| 13550 | * intel_atomic_commit - commit validated state object |
| 13551 | * @dev: DRM device |
| 13552 | * @state: the top-level driver state object |
| 13553 | * @async: asynchronous commit |
| 13554 | * |
| 13555 | * This function commits a top-level state object that has been validated |
| 13556 | * with drm_atomic_helper_check(). |
| 13557 | * |
| 13558 | * FIXME: Atomic modeset support for i915 is not yet complete. At the moment |
| 13559 | * we can only handle plane-related operations and do not yet support |
| 13560 | * asynchronous commit. |
| 13561 | * |
| 13562 | * RETURNS |
| 13563 | * Zero for success or -errno. |
| 13564 | */ |
| 13565 | static int intel_atomic_commit(struct drm_device *dev, |
| 13566 | struct drm_atomic_state *state, |
| 13567 | bool async) |
| 13568 | { |
| 13569 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
| 13570 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 13571 | struct drm_crtc_state *crtc_state; |
| 13572 | struct drm_crtc *crtc; |
| 13573 | struct intel_crtc_state *intel_cstate; |
| 13574 | int ret = 0, i; |
| 13575 | bool hw_check = intel_state->modeset; |
| 13576 | |
| 13577 | ret = intel_atomic_prepare_commit(dev, state, async); |
| 13578 | if (ret) { |
| 13579 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); |
| 13580 | return ret; |
| 13581 | } |
| 13582 | |
| 13583 | drm_atomic_helper_swap_state(dev, state); |
| 13584 | dev_priv->wm.config = to_intel_atomic_state(state)->wm_config; |
| 13585 | |
| 13586 | if (intel_state->modeset) { |
| 13587 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, |
| 13588 | sizeof(intel_state->min_pixclk)); |
| 13589 | dev_priv->active_crtcs = intel_state->active_crtcs; |
| 13590 | dev_priv->atomic_cdclk_freq = intel_state->cdclk; |
| 13591 | } |
| 13592 | |
| 13593 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
| 13594 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 13595 | |
| 13596 | if (!needs_modeset(crtc->state)) |
| 13597 | continue; |
| 13598 | |
| 13599 | intel_pre_plane_update(intel_crtc); |
| 13600 | |
| 13601 | if (crtc_state->active) { |
| 13602 | intel_crtc_disable_planes(crtc, crtc_state->plane_mask); |
| 13603 | dev_priv->display.crtc_disable(crtc); |
| 13604 | intel_crtc->active = false; |
| 13605 | intel_disable_shared_dpll(intel_crtc); |
| 13606 | |
| 13607 | /* |
| 13608 | * Underruns don't always raise |
| 13609 | * interrupts, so check manually. |
| 13610 | */ |
| 13611 | intel_check_cpu_fifo_underruns(dev_priv); |
| 13612 | intel_check_pch_fifo_underruns(dev_priv); |
| 13613 | |
| 13614 | if (!crtc->state->active) |
| 13615 | intel_update_watermarks(crtc); |
| 13616 | } |
| 13617 | } |
| 13618 | |
| 13619 | /* Only after disabling all output pipelines that will be changed can we |
| 13620 | * update the the output configuration. */ |
| 13621 | intel_modeset_update_crtc_state(state); |
| 13622 | |
| 13623 | if (intel_state->modeset) { |
| 13624 | intel_shared_dpll_commit(state); |
| 13625 | |
| 13626 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); |
| 13627 | modeset_update_crtc_power_domains(state); |
| 13628 | } |
| 13629 | |
| 13630 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
| 13631 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
| 13632 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 13633 | bool modeset = needs_modeset(crtc->state); |
| 13634 | bool update_pipe = !modeset && |
| 13635 | to_intel_crtc_state(crtc->state)->update_pipe; |
| 13636 | unsigned long put_domains = 0; |
| 13637 | |
| 13638 | if (modeset) |
| 13639 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); |
| 13640 | |
| 13641 | if (modeset && crtc->state->active) { |
| 13642 | update_scanline_offset(to_intel_crtc(crtc)); |
| 13643 | dev_priv->display.crtc_enable(crtc); |
| 13644 | } |
| 13645 | |
| 13646 | if (update_pipe) { |
| 13647 | put_domains = modeset_get_crtc_power_domains(crtc); |
| 13648 | |
| 13649 | /* make sure intel_modeset_check_state runs */ |
| 13650 | hw_check = true; |
| 13651 | } |
| 13652 | |
| 13653 | if (!modeset) |
| 13654 | intel_pre_plane_update(intel_crtc); |
| 13655 | |
| 13656 | if (crtc->state->active && |
| 13657 | (crtc->state->planes_changed || update_pipe)) |
| 13658 | drm_atomic_helper_commit_planes_on_crtc(crtc_state); |
| 13659 | |
| 13660 | if (put_domains) |
| 13661 | modeset_put_power_domains(dev_priv, put_domains); |
| 13662 | |
| 13663 | intel_post_plane_update(intel_crtc); |
| 13664 | |
| 13665 | if (modeset) |
| 13666 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); |
| 13667 | } |
| 13668 | |
| 13669 | /* FIXME: add subpixel order */ |
| 13670 | |
| 13671 | drm_atomic_helper_wait_for_vblanks(dev, state); |
| 13672 | |
| 13673 | /* |
| 13674 | * Now that the vblank has passed, we can go ahead and program the |
| 13675 | * optimal watermarks on platforms that need two-step watermark |
| 13676 | * programming. |
| 13677 | * |
| 13678 | * TODO: Move this (and other cleanup) to an async worker eventually. |
| 13679 | */ |
| 13680 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
| 13681 | intel_cstate = to_intel_crtc_state(crtc->state); |
| 13682 | |
| 13683 | if (dev_priv->display.optimize_watermarks) |
| 13684 | dev_priv->display.optimize_watermarks(intel_cstate); |
| 13685 | } |
| 13686 | |
| 13687 | mutex_lock(&dev->struct_mutex); |
| 13688 | drm_atomic_helper_cleanup_planes(dev, state); |
| 13689 | mutex_unlock(&dev->struct_mutex); |
| 13690 | |
| 13691 | if (hw_check) |
| 13692 | intel_modeset_check_state(dev, state); |
| 13693 | |
| 13694 | drm_atomic_state_free(state); |
| 13695 | |
| 13696 | /* As one of the primary mmio accessors, KMS has a high likelihood |
| 13697 | * of triggering bugs in unclaimed access. After we finish |
| 13698 | * modesetting, see if an error has been flagged, and if so |
| 13699 | * enable debugging for the next modeset - and hope we catch |
| 13700 | * the culprit. |
| 13701 | * |
| 13702 | * XXX note that we assume display power is on at this point. |
| 13703 | * This might hold true now but we need to add pm helper to check |
| 13704 | * unclaimed only when the hardware is on, as atomic commits |
| 13705 | * can happen also when the device is completely off. |
| 13706 | */ |
| 13707 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); |
| 13708 | |
| 13709 | return 0; |
| 13710 | } |
| 13711 | |
| 13712 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
| 13713 | { |
| 13714 | struct drm_device *dev = crtc->dev; |
| 13715 | struct drm_atomic_state *state; |
| 13716 | struct drm_crtc_state *crtc_state; |
| 13717 | int ret; |
| 13718 | |
| 13719 | state = drm_atomic_state_alloc(dev); |
| 13720 | if (!state) { |
| 13721 | DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory", |
| 13722 | crtc->base.id); |
| 13723 | return; |
| 13724 | } |
| 13725 | |
| 13726 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
| 13727 | |
| 13728 | retry: |
| 13729 | crtc_state = drm_atomic_get_crtc_state(state, crtc); |
| 13730 | ret = PTR_ERR_OR_ZERO(crtc_state); |
| 13731 | if (!ret) { |
| 13732 | if (!crtc_state->active) |
| 13733 | goto out; |
| 13734 | |
| 13735 | crtc_state->mode_changed = true; |
| 13736 | ret = drm_atomic_commit(state); |
| 13737 | } |
| 13738 | |
| 13739 | if (ret == -EDEADLK) { |
| 13740 | drm_atomic_state_clear(state); |
| 13741 | drm_modeset_backoff(state->acquire_ctx); |
| 13742 | goto retry; |
| 13743 | } |
| 13744 | |
| 13745 | if (ret) |
| 13746 | out: |
| 13747 | drm_atomic_state_free(state); |
| 13748 | } |
| 13749 | |
| 13750 | #undef for_each_intel_crtc_masked |
| 13751 | |
| 13752 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
| 13753 | .gamma_set = intel_crtc_gamma_set, |
| 13754 | .set_config = drm_atomic_helper_set_config, |
| 13755 | .destroy = intel_crtc_destroy, |
| 13756 | .page_flip = intel_crtc_page_flip, |
| 13757 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
| 13758 | .atomic_destroy_state = intel_crtc_destroy_state, |
| 13759 | }; |
| 13760 | |
| 13761 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
| 13762 | struct intel_shared_dpll *pll, |
| 13763 | struct intel_dpll_hw_state *hw_state) |
| 13764 | { |
| 13765 | uint32_t val; |
| 13766 | |
| 13767 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
| 13768 | return false; |
| 13769 | |
| 13770 | val = I915_READ(PCH_DPLL(pll->id)); |
| 13771 | hw_state->dpll = val; |
| 13772 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); |
| 13773 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); |
| 13774 | |
| 13775 | return val & DPLL_VCO_ENABLE; |
| 13776 | } |
| 13777 | |
| 13778 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
| 13779 | struct intel_shared_dpll *pll) |
| 13780 | { |
| 13781 | I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); |
| 13782 | I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); |
| 13783 | } |
| 13784 | |
| 13785 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
| 13786 | struct intel_shared_dpll *pll) |
| 13787 | { |
| 13788 | /* PCH refclock must be enabled first */ |
| 13789 | ibx_assert_pch_refclk_enabled(dev_priv); |
| 13790 | |
| 13791 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
| 13792 | |
| 13793 | /* Wait for the clocks to stabilize. */ |
| 13794 | POSTING_READ(PCH_DPLL(pll->id)); |
| 13795 | udelay(150); |
| 13796 | |
| 13797 | /* The pixel multiplier can only be updated once the |
| 13798 | * DPLL is enabled and the clocks are stable. |
| 13799 | * |
| 13800 | * So write it again. |
| 13801 | */ |
| 13802 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
| 13803 | POSTING_READ(PCH_DPLL(pll->id)); |
| 13804 | udelay(200); |
| 13805 | } |
| 13806 | |
| 13807 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, |
| 13808 | struct intel_shared_dpll *pll) |
| 13809 | { |
| 13810 | struct drm_device *dev = dev_priv->dev; |
| 13811 | struct intel_crtc *crtc; |
| 13812 | |
| 13813 | /* Make sure no transcoder isn't still depending on us. */ |
| 13814 | for_each_intel_crtc(dev, crtc) { |
| 13815 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
| 13816 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); |
| 13817 | } |
| 13818 | |
| 13819 | I915_WRITE(PCH_DPLL(pll->id), 0); |
| 13820 | POSTING_READ(PCH_DPLL(pll->id)); |
| 13821 | udelay(200); |
| 13822 | } |
| 13823 | |
| 13824 | static char *ibx_pch_dpll_names[] = { |
| 13825 | "PCH DPLL A", |
| 13826 | "PCH DPLL B", |
| 13827 | }; |
| 13828 | |
| 13829 | static void ibx_pch_dpll_init(struct drm_device *dev) |
| 13830 | { |
| 13831 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 13832 | int i; |
| 13833 | |
| 13834 | dev_priv->num_shared_dpll = 2; |
| 13835 | |
| 13836 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
| 13837 | dev_priv->shared_dplls[i].id = i; |
| 13838 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; |
| 13839 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
| 13840 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
| 13841 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; |
| 13842 | dev_priv->shared_dplls[i].get_hw_state = |
| 13843 | ibx_pch_dpll_get_hw_state; |
| 13844 | } |
| 13845 | } |
| 13846 | |
| 13847 | static void intel_shared_dpll_init(struct drm_device *dev) |
| 13848 | { |
| 13849 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 13850 | |
| 13851 | if (HAS_DDI(dev)) |
| 13852 | intel_ddi_pll_init(dev); |
| 13853 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
| 13854 | ibx_pch_dpll_init(dev); |
| 13855 | else |
| 13856 | dev_priv->num_shared_dpll = 0; |
| 13857 | |
| 13858 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); |
| 13859 | } |
| 13860 | |
| 13861 | /** |
| 13862 | * intel_prepare_plane_fb - Prepare fb for usage on plane |
| 13863 | * @plane: drm plane to prepare for |
| 13864 | * @fb: framebuffer to prepare for presentation |
| 13865 | * |
| 13866 | * Prepares a framebuffer for usage on a display plane. Generally this |
| 13867 | * involves pinning the underlying object and updating the frontbuffer tracking |
| 13868 | * bits. Some older platforms need special physical address handling for |
| 13869 | * cursor planes. |
| 13870 | * |
| 13871 | * Must be called with struct_mutex held. |
| 13872 | * |
| 13873 | * Returns 0 on success, negative error code on failure. |
| 13874 | */ |
| 13875 | int |
| 13876 | intel_prepare_plane_fb(struct drm_plane *plane, |
| 13877 | const struct drm_plane_state *new_state) |
| 13878 | { |
| 13879 | struct drm_device *dev = plane->dev; |
| 13880 | struct drm_framebuffer *fb = new_state->fb; |
| 13881 | struct intel_plane *intel_plane = to_intel_plane(plane); |
| 13882 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
| 13883 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
| 13884 | int ret = 0; |
| 13885 | |
| 13886 | if (!obj && !old_obj) |
| 13887 | return 0; |
| 13888 | |
| 13889 | if (old_obj) { |
| 13890 | struct drm_crtc_state *crtc_state = |
| 13891 | drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc); |
| 13892 | |
| 13893 | /* Big Hammer, we also need to ensure that any pending |
| 13894 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the |
| 13895 | * current scanout is retired before unpinning the old |
| 13896 | * framebuffer. Note that we rely on userspace rendering |
| 13897 | * into the buffer attached to the pipe they are waiting |
| 13898 | * on. If not, userspace generates a GPU hang with IPEHR |
| 13899 | * point to the MI_WAIT_FOR_EVENT. |
| 13900 | * |
| 13901 | * This should only fail upon a hung GPU, in which case we |
| 13902 | * can safely continue. |
| 13903 | */ |
| 13904 | if (needs_modeset(crtc_state)) |
| 13905 | ret = i915_gem_object_wait_rendering(old_obj, true); |
| 13906 | |
| 13907 | /* Swallow -EIO errors to allow updates during hw lockup. */ |
| 13908 | if (ret && ret != -EIO) |
| 13909 | return ret; |
| 13910 | } |
| 13911 | |
| 13912 | /* For framebuffer backed by dmabuf, wait for fence */ |
| 13913 | if (obj && obj->base.dma_buf) { |
| 13914 | long lret; |
| 13915 | |
| 13916 | lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, |
| 13917 | false, true, |
| 13918 | MAX_SCHEDULE_TIMEOUT); |
| 13919 | if (lret == -ERESTARTSYS) |
| 13920 | return lret; |
| 13921 | |
| 13922 | WARN(lret < 0, "waiting returns %li\n", lret); |
| 13923 | } |
| 13924 | |
| 13925 | if (!obj) { |
| 13926 | ret = 0; |
| 13927 | } else if (plane->type == DRM_PLANE_TYPE_CURSOR && |
| 13928 | INTEL_INFO(dev)->cursor_needs_physical) { |
| 13929 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
| 13930 | ret = i915_gem_object_attach_phys(obj, align); |
| 13931 | if (ret) |
| 13932 | DRM_DEBUG_KMS("failed to attach phys object\n"); |
| 13933 | } else { |
| 13934 | ret = intel_pin_and_fence_fb_obj(plane, fb, new_state); |
| 13935 | } |
| 13936 | |
| 13937 | if (ret == 0) { |
| 13938 | if (obj) { |
| 13939 | struct intel_plane_state *plane_state = |
| 13940 | to_intel_plane_state(new_state); |
| 13941 | |
| 13942 | i915_gem_request_assign(&plane_state->wait_req, |
| 13943 | obj->last_write_req); |
| 13944 | } |
| 13945 | |
| 13946 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); |
| 13947 | } |
| 13948 | |
| 13949 | return ret; |
| 13950 | } |
| 13951 | |
| 13952 | /** |
| 13953 | * intel_cleanup_plane_fb - Cleans up an fb after plane use |
| 13954 | * @plane: drm plane to clean up for |
| 13955 | * @fb: old framebuffer that was on plane |
| 13956 | * |
| 13957 | * Cleans up a framebuffer that has just been removed from a plane. |
| 13958 | * |
| 13959 | * Must be called with struct_mutex held. |
| 13960 | */ |
| 13961 | void |
| 13962 | intel_cleanup_plane_fb(struct drm_plane *plane, |
| 13963 | const struct drm_plane_state *old_state) |
| 13964 | { |
| 13965 | struct drm_device *dev = plane->dev; |
| 13966 | struct intel_plane *intel_plane = to_intel_plane(plane); |
| 13967 | struct intel_plane_state *old_intel_state; |
| 13968 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb); |
| 13969 | struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb); |
| 13970 | |
| 13971 | old_intel_state = to_intel_plane_state(old_state); |
| 13972 | |
| 13973 | if (!obj && !old_obj) |
| 13974 | return; |
| 13975 | |
| 13976 | if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR || |
| 13977 | !INTEL_INFO(dev)->cursor_needs_physical)) |
| 13978 | intel_unpin_fb_obj(old_state->fb, old_state); |
| 13979 | |
| 13980 | /* prepare_fb aborted? */ |
| 13981 | if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) || |
| 13982 | (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit))) |
| 13983 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); |
| 13984 | |
| 13985 | i915_gem_request_assign(&old_intel_state->wait_req, NULL); |
| 13986 | |
| 13987 | } |
| 13988 | |
| 13989 | int |
| 13990 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) |
| 13991 | { |
| 13992 | int max_scale; |
| 13993 | struct drm_device *dev; |
| 13994 | struct drm_i915_private *dev_priv; |
| 13995 | int crtc_clock, cdclk; |
| 13996 | |
| 13997 | if (!intel_crtc || !crtc_state->base.enable) |
| 13998 | return DRM_PLANE_HELPER_NO_SCALING; |
| 13999 | |
| 14000 | dev = intel_crtc->base.dev; |
| 14001 | dev_priv = dev->dev_private; |
| 14002 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; |
| 14003 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
| 14004 | |
| 14005 | if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)) |
| 14006 | return DRM_PLANE_HELPER_NO_SCALING; |
| 14007 | |
| 14008 | /* |
| 14009 | * skl max scale is lower of: |
| 14010 | * close to 3 but not 3, -1 is for that purpose |
| 14011 | * or |
| 14012 | * cdclk/crtc_clock |
| 14013 | */ |
| 14014 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); |
| 14015 | |
| 14016 | return max_scale; |
| 14017 | } |
| 14018 | |
| 14019 | static int |
| 14020 | intel_check_primary_plane(struct drm_plane *plane, |
| 14021 | struct intel_crtc_state *crtc_state, |
| 14022 | struct intel_plane_state *state) |
| 14023 | { |
| 14024 | struct drm_crtc *crtc = state->base.crtc; |
| 14025 | struct drm_framebuffer *fb = state->base.fb; |
| 14026 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
| 14027 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
| 14028 | bool can_position = false; |
| 14029 | |
| 14030 | /* use scaler when colorkey is not required */ |
| 14031 | if (INTEL_INFO(plane->dev)->gen >= 9 && |
| 14032 | state->ckey.flags == I915_SET_COLORKEY_NONE) { |
| 14033 | min_scale = 1; |
| 14034 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); |
| 14035 | can_position = true; |
| 14036 | } |
| 14037 | |
| 14038 | return drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
| 14039 | &state->dst, &state->clip, |
| 14040 | min_scale, max_scale, |
| 14041 | can_position, true, |
| 14042 | &state->visible); |
| 14043 | } |
| 14044 | |
| 14045 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
| 14046 | struct drm_crtc_state *old_crtc_state) |
| 14047 | { |
| 14048 | struct drm_device *dev = crtc->dev; |
| 14049 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 14050 | struct intel_crtc_state *old_intel_state = |
| 14051 | to_intel_crtc_state(old_crtc_state); |
| 14052 | bool modeset = needs_modeset(crtc->state); |
| 14053 | |
| 14054 | /* Perform vblank evasion around commit operation */ |
| 14055 | intel_pipe_update_start(intel_crtc); |
| 14056 | |
| 14057 | if (modeset) |
| 14058 | return; |
| 14059 | |
| 14060 | if (to_intel_crtc_state(crtc->state)->update_pipe) |
| 14061 | intel_update_pipe_config(intel_crtc, old_intel_state); |
| 14062 | else if (INTEL_INFO(dev)->gen >= 9) |
| 14063 | skl_detach_scalers(intel_crtc); |
| 14064 | } |
| 14065 | |
| 14066 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, |
| 14067 | struct drm_crtc_state *old_crtc_state) |
| 14068 | { |
| 14069 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 14070 | |
| 14071 | intel_pipe_update_end(intel_crtc); |
| 14072 | } |
| 14073 | |
| 14074 | /** |
| 14075 | * intel_plane_destroy - destroy a plane |
| 14076 | * @plane: plane to destroy |
| 14077 | * |
| 14078 | * Common destruction function for all types of planes (primary, cursor, |
| 14079 | * sprite). |
| 14080 | */ |
| 14081 | void intel_plane_destroy(struct drm_plane *plane) |
| 14082 | { |
| 14083 | struct intel_plane *intel_plane = to_intel_plane(plane); |
| 14084 | drm_plane_cleanup(plane); |
| 14085 | kfree(intel_plane); |
| 14086 | } |
| 14087 | |
| 14088 | const struct drm_plane_funcs intel_plane_funcs = { |
| 14089 | .update_plane = drm_atomic_helper_update_plane, |
| 14090 | .disable_plane = drm_atomic_helper_disable_plane, |
| 14091 | .destroy = intel_plane_destroy, |
| 14092 | .set_property = drm_atomic_helper_plane_set_property, |
| 14093 | .atomic_get_property = intel_plane_atomic_get_property, |
| 14094 | .atomic_set_property = intel_plane_atomic_set_property, |
| 14095 | .atomic_duplicate_state = intel_plane_duplicate_state, |
| 14096 | .atomic_destroy_state = intel_plane_destroy_state, |
| 14097 | |
| 14098 | }; |
| 14099 | |
| 14100 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, |
| 14101 | int pipe) |
| 14102 | { |
| 14103 | struct intel_plane *primary; |
| 14104 | struct intel_plane_state *state; |
| 14105 | const uint32_t *intel_primary_formats; |
| 14106 | unsigned int num_formats; |
| 14107 | |
| 14108 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); |
| 14109 | if (primary == NULL) |
| 14110 | return NULL; |
| 14111 | |
| 14112 | state = intel_create_plane_state(&primary->base); |
| 14113 | if (!state) { |
| 14114 | kfree(primary); |
| 14115 | return NULL; |
| 14116 | } |
| 14117 | primary->base.state = &state->base; |
| 14118 | |
| 14119 | primary->can_scale = false; |
| 14120 | primary->max_downscale = 1; |
| 14121 | if (INTEL_INFO(dev)->gen >= 9) { |
| 14122 | primary->can_scale = true; |
| 14123 | state->scaler_id = -1; |
| 14124 | } |
| 14125 | primary->pipe = pipe; |
| 14126 | primary->plane = pipe; |
| 14127 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
| 14128 | primary->check_plane = intel_check_primary_plane; |
| 14129 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
| 14130 | primary->plane = !pipe; |
| 14131 | |
| 14132 | if (INTEL_INFO(dev)->gen >= 9) { |
| 14133 | intel_primary_formats = skl_primary_formats; |
| 14134 | num_formats = ARRAY_SIZE(skl_primary_formats); |
| 14135 | |
| 14136 | primary->update_plane = skylake_update_primary_plane; |
| 14137 | primary->disable_plane = skylake_disable_primary_plane; |
| 14138 | } else if (HAS_PCH_SPLIT(dev)) { |
| 14139 | intel_primary_formats = i965_primary_formats; |
| 14140 | num_formats = ARRAY_SIZE(i965_primary_formats); |
| 14141 | |
| 14142 | primary->update_plane = ironlake_update_primary_plane; |
| 14143 | primary->disable_plane = i9xx_disable_primary_plane; |
| 14144 | } else if (INTEL_INFO(dev)->gen >= 4) { |
| 14145 | intel_primary_formats = i965_primary_formats; |
| 14146 | num_formats = ARRAY_SIZE(i965_primary_formats); |
| 14147 | |
| 14148 | primary->update_plane = i9xx_update_primary_plane; |
| 14149 | primary->disable_plane = i9xx_disable_primary_plane; |
| 14150 | } else { |
| 14151 | intel_primary_formats = i8xx_primary_formats; |
| 14152 | num_formats = ARRAY_SIZE(i8xx_primary_formats); |
| 14153 | |
| 14154 | primary->update_plane = i9xx_update_primary_plane; |
| 14155 | primary->disable_plane = i9xx_disable_primary_plane; |
| 14156 | } |
| 14157 | |
| 14158 | drm_universal_plane_init(dev, &primary->base, 0, |
| 14159 | &intel_plane_funcs, |
| 14160 | intel_primary_formats, num_formats, |
| 14161 | DRM_PLANE_TYPE_PRIMARY); |
| 14162 | |
| 14163 | if (INTEL_INFO(dev)->gen >= 4) |
| 14164 | intel_create_rotation_property(dev, primary); |
| 14165 | |
| 14166 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
| 14167 | |
| 14168 | return &primary->base; |
| 14169 | } |
| 14170 | |
| 14171 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
| 14172 | { |
| 14173 | if (!dev->mode_config.rotation_property) { |
| 14174 | unsigned long flags = BIT(DRM_ROTATE_0) | |
| 14175 | BIT(DRM_ROTATE_180); |
| 14176 | |
| 14177 | if (INTEL_INFO(dev)->gen >= 9) |
| 14178 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); |
| 14179 | |
| 14180 | dev->mode_config.rotation_property = |
| 14181 | drm_mode_create_rotation_property(dev, flags); |
| 14182 | } |
| 14183 | if (dev->mode_config.rotation_property) |
| 14184 | drm_object_attach_property(&plane->base.base, |
| 14185 | dev->mode_config.rotation_property, |
| 14186 | plane->base.state->rotation); |
| 14187 | } |
| 14188 | |
| 14189 | static int |
| 14190 | intel_check_cursor_plane(struct drm_plane *plane, |
| 14191 | struct intel_crtc_state *crtc_state, |
| 14192 | struct intel_plane_state *state) |
| 14193 | { |
| 14194 | struct drm_crtc *crtc = crtc_state->base.crtc; |
| 14195 | struct drm_framebuffer *fb = state->base.fb; |
| 14196 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
| 14197 | enum pipe pipe = to_intel_plane(plane)->pipe; |
| 14198 | unsigned stride; |
| 14199 | int ret; |
| 14200 | |
| 14201 | ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
| 14202 | &state->dst, &state->clip, |
| 14203 | DRM_PLANE_HELPER_NO_SCALING, |
| 14204 | DRM_PLANE_HELPER_NO_SCALING, |
| 14205 | true, true, &state->visible); |
| 14206 | if (ret) |
| 14207 | return ret; |
| 14208 | |
| 14209 | /* if we want to turn off the cursor ignore width and height */ |
| 14210 | if (!obj) |
| 14211 | return 0; |
| 14212 | |
| 14213 | /* Check for which cursor types we support */ |
| 14214 | if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) { |
| 14215 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
| 14216 | state->base.crtc_w, state->base.crtc_h); |
| 14217 | return -EINVAL; |
| 14218 | } |
| 14219 | |
| 14220 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
| 14221 | if (obj->base.size < stride * state->base.crtc_h) { |
| 14222 | DRM_DEBUG_KMS("buffer is too small\n"); |
| 14223 | return -ENOMEM; |
| 14224 | } |
| 14225 | |
| 14226 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
| 14227 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
| 14228 | return -EINVAL; |
| 14229 | } |
| 14230 | |
| 14231 | /* |
| 14232 | * There's something wrong with the cursor on CHV pipe C. |
| 14233 | * If it straddles the left edge of the screen then |
| 14234 | * moving it away from the edge or disabling it often |
| 14235 | * results in a pipe underrun, and often that can lead to |
| 14236 | * dead pipe (constant underrun reported, and it scans |
| 14237 | * out just a solid color). To recover from that, the |
| 14238 | * display power well must be turned off and on again. |
| 14239 | * Refuse the put the cursor into that compromised position. |
| 14240 | */ |
| 14241 | if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C && |
| 14242 | state->visible && state->base.crtc_x < 0) { |
| 14243 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); |
| 14244 | return -EINVAL; |
| 14245 | } |
| 14246 | |
| 14247 | return 0; |
| 14248 | } |
| 14249 | |
| 14250 | static void |
| 14251 | intel_disable_cursor_plane(struct drm_plane *plane, |
| 14252 | struct drm_crtc *crtc) |
| 14253 | { |
| 14254 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 14255 | |
| 14256 | intel_crtc->cursor_addr = 0; |
| 14257 | intel_crtc_update_cursor(crtc, NULL); |
| 14258 | } |
| 14259 | |
| 14260 | static void |
| 14261 | intel_update_cursor_plane(struct drm_plane *plane, |
| 14262 | const struct intel_crtc_state *crtc_state, |
| 14263 | const struct intel_plane_state *state) |
| 14264 | { |
| 14265 | struct drm_crtc *crtc = crtc_state->base.crtc; |
| 14266 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 14267 | struct drm_device *dev = plane->dev; |
| 14268 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
| 14269 | uint32_t addr; |
| 14270 | |
| 14271 | if (!obj) |
| 14272 | addr = 0; |
| 14273 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
| 14274 | addr = i915_gem_obj_ggtt_offset(obj); |
| 14275 | else |
| 14276 | addr = obj->phys_handle->busaddr; |
| 14277 | |
| 14278 | intel_crtc->cursor_addr = addr; |
| 14279 | intel_crtc_update_cursor(crtc, state); |
| 14280 | } |
| 14281 | |
| 14282 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
| 14283 | int pipe) |
| 14284 | { |
| 14285 | struct intel_plane *cursor; |
| 14286 | struct intel_plane_state *state; |
| 14287 | |
| 14288 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); |
| 14289 | if (cursor == NULL) |
| 14290 | return NULL; |
| 14291 | |
| 14292 | state = intel_create_plane_state(&cursor->base); |
| 14293 | if (!state) { |
| 14294 | kfree(cursor); |
| 14295 | return NULL; |
| 14296 | } |
| 14297 | cursor->base.state = &state->base; |
| 14298 | |
| 14299 | cursor->can_scale = false; |
| 14300 | cursor->max_downscale = 1; |
| 14301 | cursor->pipe = pipe; |
| 14302 | cursor->plane = pipe; |
| 14303 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
| 14304 | cursor->check_plane = intel_check_cursor_plane; |
| 14305 | cursor->update_plane = intel_update_cursor_plane; |
| 14306 | cursor->disable_plane = intel_disable_cursor_plane; |
| 14307 | |
| 14308 | drm_universal_plane_init(dev, &cursor->base, 0, |
| 14309 | &intel_plane_funcs, |
| 14310 | intel_cursor_formats, |
| 14311 | ARRAY_SIZE(intel_cursor_formats), |
| 14312 | DRM_PLANE_TYPE_CURSOR); |
| 14313 | |
| 14314 | if (INTEL_INFO(dev)->gen >= 4) { |
| 14315 | if (!dev->mode_config.rotation_property) |
| 14316 | dev->mode_config.rotation_property = |
| 14317 | drm_mode_create_rotation_property(dev, |
| 14318 | BIT(DRM_ROTATE_0) | |
| 14319 | BIT(DRM_ROTATE_180)); |
| 14320 | if (dev->mode_config.rotation_property) |
| 14321 | drm_object_attach_property(&cursor->base.base, |
| 14322 | dev->mode_config.rotation_property, |
| 14323 | state->base.rotation); |
| 14324 | } |
| 14325 | |
| 14326 | if (INTEL_INFO(dev)->gen >=9) |
| 14327 | state->scaler_id = -1; |
| 14328 | |
| 14329 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
| 14330 | |
| 14331 | return &cursor->base; |
| 14332 | } |
| 14333 | |
| 14334 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
| 14335 | struct intel_crtc_state *crtc_state) |
| 14336 | { |
| 14337 | int i; |
| 14338 | struct intel_scaler *intel_scaler; |
| 14339 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; |
| 14340 | |
| 14341 | for (i = 0; i < intel_crtc->num_scalers; i++) { |
| 14342 | intel_scaler = &scaler_state->scalers[i]; |
| 14343 | intel_scaler->in_use = 0; |
| 14344 | intel_scaler->mode = PS_SCALER_MODE_DYN; |
| 14345 | } |
| 14346 | |
| 14347 | scaler_state->scaler_id = -1; |
| 14348 | } |
| 14349 | |
| 14350 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
| 14351 | { |
| 14352 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 14353 | struct intel_crtc *intel_crtc; |
| 14354 | struct intel_crtc_state *crtc_state = NULL; |
| 14355 | struct drm_plane *primary = NULL; |
| 14356 | struct drm_plane *cursor = NULL; |
| 14357 | int i, ret; |
| 14358 | |
| 14359 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
| 14360 | if (intel_crtc == NULL) |
| 14361 | return; |
| 14362 | |
| 14363 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
| 14364 | if (!crtc_state) |
| 14365 | goto fail; |
| 14366 | intel_crtc->config = crtc_state; |
| 14367 | intel_crtc->base.state = &crtc_state->base; |
| 14368 | crtc_state->base.crtc = &intel_crtc->base; |
| 14369 | |
| 14370 | /* initialize shared scalers */ |
| 14371 | if (INTEL_INFO(dev)->gen >= 9) { |
| 14372 | if (pipe == PIPE_C) |
| 14373 | intel_crtc->num_scalers = 1; |
| 14374 | else |
| 14375 | intel_crtc->num_scalers = SKL_NUM_SCALERS; |
| 14376 | |
| 14377 | skl_init_scalers(dev, intel_crtc, crtc_state); |
| 14378 | } |
| 14379 | |
| 14380 | primary = intel_primary_plane_create(dev, pipe); |
| 14381 | if (!primary) |
| 14382 | goto fail; |
| 14383 | |
| 14384 | cursor = intel_cursor_plane_create(dev, pipe); |
| 14385 | if (!cursor) |
| 14386 | goto fail; |
| 14387 | |
| 14388 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
| 14389 | cursor, &intel_crtc_funcs); |
| 14390 | if (ret) |
| 14391 | goto fail; |
| 14392 | |
| 14393 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); |
| 14394 | for (i = 0; i < 256; i++) { |
| 14395 | intel_crtc->lut_r[i] = i; |
| 14396 | intel_crtc->lut_g[i] = i; |
| 14397 | intel_crtc->lut_b[i] = i; |
| 14398 | } |
| 14399 | |
| 14400 | /* |
| 14401 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port |
| 14402 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
| 14403 | */ |
| 14404 | intel_crtc->pipe = pipe; |
| 14405 | intel_crtc->plane = pipe; |
| 14406 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
| 14407 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
| 14408 | intel_crtc->plane = !pipe; |
| 14409 | } |
| 14410 | |
| 14411 | intel_crtc->cursor_base = ~0; |
| 14412 | intel_crtc->cursor_cntl = ~0; |
| 14413 | intel_crtc->cursor_size = ~0; |
| 14414 | |
| 14415 | intel_crtc->wm.cxsr_allowed = true; |
| 14416 | |
| 14417 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
| 14418 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); |
| 14419 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; |
| 14420 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; |
| 14421 | |
| 14422 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
| 14423 | |
| 14424 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); |
| 14425 | return; |
| 14426 | |
| 14427 | fail: |
| 14428 | if (primary) |
| 14429 | drm_plane_cleanup(primary); |
| 14430 | if (cursor) |
| 14431 | drm_plane_cleanup(cursor); |
| 14432 | kfree(crtc_state); |
| 14433 | kfree(intel_crtc); |
| 14434 | } |
| 14435 | |
| 14436 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
| 14437 | { |
| 14438 | struct drm_encoder *encoder = connector->base.encoder; |
| 14439 | struct drm_device *dev = connector->base.dev; |
| 14440 | |
| 14441 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
| 14442 | |
| 14443 | if (!encoder || WARN_ON(!encoder->crtc)) |
| 14444 | return INVALID_PIPE; |
| 14445 | |
| 14446 | return to_intel_crtc(encoder->crtc)->pipe; |
| 14447 | } |
| 14448 | |
| 14449 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
| 14450 | struct drm_file *file) |
| 14451 | { |
| 14452 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
| 14453 | struct drm_crtc *drmmode_crtc; |
| 14454 | struct intel_crtc *crtc; |
| 14455 | |
| 14456 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
| 14457 | |
| 14458 | if (!drmmode_crtc) { |
| 14459 | DRM_ERROR("no such CRTC id\n"); |
| 14460 | return -ENOENT; |
| 14461 | } |
| 14462 | |
| 14463 | crtc = to_intel_crtc(drmmode_crtc); |
| 14464 | pipe_from_crtc_id->pipe = crtc->pipe; |
| 14465 | |
| 14466 | return 0; |
| 14467 | } |
| 14468 | |
| 14469 | static int intel_encoder_clones(struct intel_encoder *encoder) |
| 14470 | { |
| 14471 | struct drm_device *dev = encoder->base.dev; |
| 14472 | struct intel_encoder *source_encoder; |
| 14473 | int index_mask = 0; |
| 14474 | int entry = 0; |
| 14475 | |
| 14476 | for_each_intel_encoder(dev, source_encoder) { |
| 14477 | if (encoders_cloneable(encoder, source_encoder)) |
| 14478 | index_mask |= (1 << entry); |
| 14479 | |
| 14480 | entry++; |
| 14481 | } |
| 14482 | |
| 14483 | return index_mask; |
| 14484 | } |
| 14485 | |
| 14486 | static bool has_edp_a(struct drm_device *dev) |
| 14487 | { |
| 14488 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 14489 | |
| 14490 | if (!IS_MOBILE(dev)) |
| 14491 | return false; |
| 14492 | |
| 14493 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) |
| 14494 | return false; |
| 14495 | |
| 14496 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
| 14497 | return false; |
| 14498 | |
| 14499 | return true; |
| 14500 | } |
| 14501 | |
| 14502 | static bool intel_crt_present(struct drm_device *dev) |
| 14503 | { |
| 14504 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 14505 | |
| 14506 | if (INTEL_INFO(dev)->gen >= 9) |
| 14507 | return false; |
| 14508 | |
| 14509 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
| 14510 | return false; |
| 14511 | |
| 14512 | if (IS_CHERRYVIEW(dev)) |
| 14513 | return false; |
| 14514 | |
| 14515 | if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) |
| 14516 | return false; |
| 14517 | |
| 14518 | /* DDI E can't be used if DDI A requires 4 lanes */ |
| 14519 | if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) |
| 14520 | return false; |
| 14521 | |
| 14522 | if (!dev_priv->vbt.int_crt_support) |
| 14523 | return false; |
| 14524 | |
| 14525 | return true; |
| 14526 | } |
| 14527 | |
| 14528 | static void intel_setup_outputs(struct drm_device *dev) |
| 14529 | { |
| 14530 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 14531 | struct intel_encoder *encoder; |
| 14532 | bool dpd_is_edp = false; |
| 14533 | |
| 14534 | intel_lvds_init(dev); |
| 14535 | |
| 14536 | if (intel_crt_present(dev)) |
| 14537 | intel_crt_init(dev); |
| 14538 | |
| 14539 | if (IS_BROXTON(dev)) { |
| 14540 | /* |
| 14541 | * FIXME: Broxton doesn't support port detection via the |
| 14542 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to |
| 14543 | * detect the ports. |
| 14544 | */ |
| 14545 | intel_ddi_init(dev, PORT_A); |
| 14546 | intel_ddi_init(dev, PORT_B); |
| 14547 | intel_ddi_init(dev, PORT_C); |
| 14548 | } else if (HAS_DDI(dev)) { |
| 14549 | int found; |
| 14550 | |
| 14551 | /* |
| 14552 | * Haswell uses DDI functions to detect digital outputs. |
| 14553 | * On SKL pre-D0 the strap isn't connected, so we assume |
| 14554 | * it's there. |
| 14555 | */ |
| 14556 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
| 14557 | /* WaIgnoreDDIAStrap: skl */ |
| 14558 | if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
| 14559 | intel_ddi_init(dev, PORT_A); |
| 14560 | |
| 14561 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP |
| 14562 | * register */ |
| 14563 | found = I915_READ(SFUSE_STRAP); |
| 14564 | |
| 14565 | if (found & SFUSE_STRAP_DDIB_DETECTED) |
| 14566 | intel_ddi_init(dev, PORT_B); |
| 14567 | if (found & SFUSE_STRAP_DDIC_DETECTED) |
| 14568 | intel_ddi_init(dev, PORT_C); |
| 14569 | if (found & SFUSE_STRAP_DDID_DETECTED) |
| 14570 | intel_ddi_init(dev, PORT_D); |
| 14571 | /* |
| 14572 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. |
| 14573 | */ |
| 14574 | if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && |
| 14575 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
| 14576 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || |
| 14577 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) |
| 14578 | intel_ddi_init(dev, PORT_E); |
| 14579 | |
| 14580 | } else if (HAS_PCH_SPLIT(dev)) { |
| 14581 | int found; |
| 14582 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
| 14583 | |
| 14584 | if (has_edp_a(dev)) |
| 14585 | intel_dp_init(dev, DP_A, PORT_A); |
| 14586 | |
| 14587 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
| 14588 | /* PCH SDVOB multiplex with HDMIB */ |
| 14589 | found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B); |
| 14590 | if (!found) |
| 14591 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
| 14592 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
| 14593 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
| 14594 | } |
| 14595 | |
| 14596 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
| 14597 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
| 14598 | |
| 14599 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
| 14600 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
| 14601 | |
| 14602 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
| 14603 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
| 14604 | |
| 14605 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
| 14606 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
| 14607 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
| 14608 | /* |
| 14609 | * The DP_DETECTED bit is the latched state of the DDC |
| 14610 | * SDA pin at boot. However since eDP doesn't require DDC |
| 14611 | * (no way to plug in a DP->HDMI dongle) the DDC pins for |
| 14612 | * eDP ports may have been muxed to an alternate function. |
| 14613 | * Thus we can't rely on the DP_DETECTED bit alone to detect |
| 14614 | * eDP ports. Consult the VBT as well as DP_DETECTED to |
| 14615 | * detect eDP ports. |
| 14616 | */ |
| 14617 | if (I915_READ(VLV_HDMIB) & SDVO_DETECTED && |
| 14618 | !intel_dp_is_edp(dev, PORT_B)) |
| 14619 | intel_hdmi_init(dev, VLV_HDMIB, PORT_B); |
| 14620 | if (I915_READ(VLV_DP_B) & DP_DETECTED || |
| 14621 | intel_dp_is_edp(dev, PORT_B)) |
| 14622 | intel_dp_init(dev, VLV_DP_B, PORT_B); |
| 14623 | |
| 14624 | if (I915_READ(VLV_HDMIC) & SDVO_DETECTED && |
| 14625 | !intel_dp_is_edp(dev, PORT_C)) |
| 14626 | intel_hdmi_init(dev, VLV_HDMIC, PORT_C); |
| 14627 | if (I915_READ(VLV_DP_C) & DP_DETECTED || |
| 14628 | intel_dp_is_edp(dev, PORT_C)) |
| 14629 | intel_dp_init(dev, VLV_DP_C, PORT_C); |
| 14630 | |
| 14631 | if (IS_CHERRYVIEW(dev)) { |
| 14632 | /* eDP not supported on port D, so don't check VBT */ |
| 14633 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED) |
| 14634 | intel_hdmi_init(dev, CHV_HDMID, PORT_D); |
| 14635 | if (I915_READ(CHV_DP_D) & DP_DETECTED) |
| 14636 | intel_dp_init(dev, CHV_DP_D, PORT_D); |
| 14637 | } |
| 14638 | |
| 14639 | intel_dsi_init(dev); |
| 14640 | } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) { |
| 14641 | bool found = false; |
| 14642 | |
| 14643 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
| 14644 | DRM_DEBUG_KMS("probing SDVOB\n"); |
| 14645 | found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B); |
| 14646 | if (!found && IS_G4X(dev)) { |
| 14647 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
| 14648 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
| 14649 | } |
| 14650 | |
| 14651 | if (!found && IS_G4X(dev)) |
| 14652 | intel_dp_init(dev, DP_B, PORT_B); |
| 14653 | } |
| 14654 | |
| 14655 | /* Before G4X SDVOC doesn't have its own detect register */ |
| 14656 | |
| 14657 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
| 14658 | DRM_DEBUG_KMS("probing SDVOC\n"); |
| 14659 | found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C); |
| 14660 | } |
| 14661 | |
| 14662 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
| 14663 | |
| 14664 | if (IS_G4X(dev)) { |
| 14665 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
| 14666 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
| 14667 | } |
| 14668 | if (IS_G4X(dev)) |
| 14669 | intel_dp_init(dev, DP_C, PORT_C); |
| 14670 | } |
| 14671 | |
| 14672 | if (IS_G4X(dev) && |
| 14673 | (I915_READ(DP_D) & DP_DETECTED)) |
| 14674 | intel_dp_init(dev, DP_D, PORT_D); |
| 14675 | } else if (IS_GEN2(dev)) |
| 14676 | intel_dvo_init(dev); |
| 14677 | |
| 14678 | if (SUPPORTS_TV(dev)) |
| 14679 | intel_tv_init(dev); |
| 14680 | |
| 14681 | intel_psr_init(dev); |
| 14682 | |
| 14683 | for_each_intel_encoder(dev, encoder) { |
| 14684 | encoder->base.possible_crtcs = encoder->crtc_mask; |
| 14685 | encoder->base.possible_clones = |
| 14686 | intel_encoder_clones(encoder); |
| 14687 | } |
| 14688 | |
| 14689 | intel_init_pch_refclk(dev); |
| 14690 | |
| 14691 | drm_helper_move_panel_connectors_to_head(dev); |
| 14692 | } |
| 14693 | |
| 14694 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) |
| 14695 | { |
| 14696 | struct drm_device *dev = fb->dev; |
| 14697 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
| 14698 | |
| 14699 | drm_framebuffer_cleanup(fb); |
| 14700 | mutex_lock(&dev->struct_mutex); |
| 14701 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
| 14702 | drm_gem_object_unreference(&intel_fb->obj->base); |
| 14703 | mutex_unlock(&dev->struct_mutex); |
| 14704 | kfree(intel_fb); |
| 14705 | } |
| 14706 | |
| 14707 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, |
| 14708 | struct drm_file *file, |
| 14709 | unsigned int *handle) |
| 14710 | { |
| 14711 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
| 14712 | struct drm_i915_gem_object *obj = intel_fb->obj; |
| 14713 | |
| 14714 | if (obj->userptr.mm) { |
| 14715 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); |
| 14716 | return -EINVAL; |
| 14717 | } |
| 14718 | |
| 14719 | return drm_gem_handle_create(file, &obj->base, handle); |
| 14720 | } |
| 14721 | |
| 14722 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
| 14723 | struct drm_file *file, |
| 14724 | unsigned flags, unsigned color, |
| 14725 | struct drm_clip_rect *clips, |
| 14726 | unsigned num_clips) |
| 14727 | { |
| 14728 | struct drm_device *dev = fb->dev; |
| 14729 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
| 14730 | struct drm_i915_gem_object *obj = intel_fb->obj; |
| 14731 | |
| 14732 | mutex_lock(&dev->struct_mutex); |
| 14733 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); |
| 14734 | mutex_unlock(&dev->struct_mutex); |
| 14735 | |
| 14736 | return 0; |
| 14737 | } |
| 14738 | |
| 14739 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
| 14740 | .destroy = intel_user_framebuffer_destroy, |
| 14741 | .create_handle = intel_user_framebuffer_create_handle, |
| 14742 | .dirty = intel_user_framebuffer_dirty, |
| 14743 | }; |
| 14744 | |
| 14745 | static |
| 14746 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, |
| 14747 | uint32_t pixel_format) |
| 14748 | { |
| 14749 | u32 gen = INTEL_INFO(dev)->gen; |
| 14750 | |
| 14751 | if (gen >= 9) { |
| 14752 | /* "The stride in bytes must not exceed the of the size of 8K |
| 14753 | * pixels and 32K bytes." |
| 14754 | */ |
| 14755 | return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768); |
| 14756 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
| 14757 | return 32*1024; |
| 14758 | } else if (gen >= 4) { |
| 14759 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) |
| 14760 | return 16*1024; |
| 14761 | else |
| 14762 | return 32*1024; |
| 14763 | } else if (gen >= 3) { |
| 14764 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) |
| 14765 | return 8*1024; |
| 14766 | else |
| 14767 | return 16*1024; |
| 14768 | } else { |
| 14769 | /* XXX DSPC is limited to 4k tiled */ |
| 14770 | return 8*1024; |
| 14771 | } |
| 14772 | } |
| 14773 | |
| 14774 | static int intel_framebuffer_init(struct drm_device *dev, |
| 14775 | struct intel_framebuffer *intel_fb, |
| 14776 | struct drm_mode_fb_cmd2 *mode_cmd, |
| 14777 | struct drm_i915_gem_object *obj) |
| 14778 | { |
| 14779 | unsigned int aligned_height; |
| 14780 | int ret; |
| 14781 | u32 pitch_limit, stride_alignment; |
| 14782 | |
| 14783 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 14784 | |
| 14785 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
| 14786 | /* Enforce that fb modifier and tiling mode match, but only for |
| 14787 | * X-tiled. This is needed for FBC. */ |
| 14788 | if (!!(obj->tiling_mode == I915_TILING_X) != |
| 14789 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { |
| 14790 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); |
| 14791 | return -EINVAL; |
| 14792 | } |
| 14793 | } else { |
| 14794 | if (obj->tiling_mode == I915_TILING_X) |
| 14795 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; |
| 14796 | else if (obj->tiling_mode == I915_TILING_Y) { |
| 14797 | DRM_DEBUG("No Y tiling for legacy addfb\n"); |
| 14798 | return -EINVAL; |
| 14799 | } |
| 14800 | } |
| 14801 | |
| 14802 | /* Passed in modifier sanity checking. */ |
| 14803 | switch (mode_cmd->modifier[0]) { |
| 14804 | case I915_FORMAT_MOD_Y_TILED: |
| 14805 | case I915_FORMAT_MOD_Yf_TILED: |
| 14806 | if (INTEL_INFO(dev)->gen < 9) { |
| 14807 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", |
| 14808 | mode_cmd->modifier[0]); |
| 14809 | return -EINVAL; |
| 14810 | } |
| 14811 | case DRM_FORMAT_MOD_NONE: |
| 14812 | case I915_FORMAT_MOD_X_TILED: |
| 14813 | break; |
| 14814 | default: |
| 14815 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
| 14816 | mode_cmd->modifier[0]); |
| 14817 | return -EINVAL; |
| 14818 | } |
| 14819 | |
| 14820 | stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0], |
| 14821 | mode_cmd->pixel_format); |
| 14822 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { |
| 14823 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", |
| 14824 | mode_cmd->pitches[0], stride_alignment); |
| 14825 | return -EINVAL; |
| 14826 | } |
| 14827 | |
| 14828 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
| 14829 | mode_cmd->pixel_format); |
| 14830 | if (mode_cmd->pitches[0] > pitch_limit) { |
| 14831 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
| 14832 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? |
| 14833 | "tiled" : "linear", |
| 14834 | mode_cmd->pitches[0], pitch_limit); |
| 14835 | return -EINVAL; |
| 14836 | } |
| 14837 | |
| 14838 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
| 14839 | mode_cmd->pitches[0] != obj->stride) { |
| 14840 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", |
| 14841 | mode_cmd->pitches[0], obj->stride); |
| 14842 | return -EINVAL; |
| 14843 | } |
| 14844 | |
| 14845 | /* Reject formats not supported by any plane early. */ |
| 14846 | switch (mode_cmd->pixel_format) { |
| 14847 | case DRM_FORMAT_C8: |
| 14848 | case DRM_FORMAT_RGB565: |
| 14849 | case DRM_FORMAT_XRGB8888: |
| 14850 | case DRM_FORMAT_ARGB8888: |
| 14851 | break; |
| 14852 | case DRM_FORMAT_XRGB1555: |
| 14853 | if (INTEL_INFO(dev)->gen > 3) { |
| 14854 | DRM_DEBUG("unsupported pixel format: %s\n", |
| 14855 | drm_get_format_name(mode_cmd->pixel_format)); |
| 14856 | return -EINVAL; |
| 14857 | } |
| 14858 | break; |
| 14859 | case DRM_FORMAT_ABGR8888: |
| 14860 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
| 14861 | INTEL_INFO(dev)->gen < 9) { |
| 14862 | DRM_DEBUG("unsupported pixel format: %s\n", |
| 14863 | drm_get_format_name(mode_cmd->pixel_format)); |
| 14864 | return -EINVAL; |
| 14865 | } |
| 14866 | break; |
| 14867 | case DRM_FORMAT_XBGR8888: |
| 14868 | case DRM_FORMAT_XRGB2101010: |
| 14869 | case DRM_FORMAT_XBGR2101010: |
| 14870 | if (INTEL_INFO(dev)->gen < 4) { |
| 14871 | DRM_DEBUG("unsupported pixel format: %s\n", |
| 14872 | drm_get_format_name(mode_cmd->pixel_format)); |
| 14873 | return -EINVAL; |
| 14874 | } |
| 14875 | break; |
| 14876 | case DRM_FORMAT_ABGR2101010: |
| 14877 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
| 14878 | DRM_DEBUG("unsupported pixel format: %s\n", |
| 14879 | drm_get_format_name(mode_cmd->pixel_format)); |
| 14880 | return -EINVAL; |
| 14881 | } |
| 14882 | break; |
| 14883 | case DRM_FORMAT_YUYV: |
| 14884 | case DRM_FORMAT_UYVY: |
| 14885 | case DRM_FORMAT_YVYU: |
| 14886 | case DRM_FORMAT_VYUY: |
| 14887 | if (INTEL_INFO(dev)->gen < 5) { |
| 14888 | DRM_DEBUG("unsupported pixel format: %s\n", |
| 14889 | drm_get_format_name(mode_cmd->pixel_format)); |
| 14890 | return -EINVAL; |
| 14891 | } |
| 14892 | break; |
| 14893 | default: |
| 14894 | DRM_DEBUG("unsupported pixel format: %s\n", |
| 14895 | drm_get_format_name(mode_cmd->pixel_format)); |
| 14896 | return -EINVAL; |
| 14897 | } |
| 14898 | |
| 14899 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
| 14900 | if (mode_cmd->offsets[0] != 0) |
| 14901 | return -EINVAL; |
| 14902 | |
| 14903 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
| 14904 | mode_cmd->pixel_format, |
| 14905 | mode_cmd->modifier[0]); |
| 14906 | /* FIXME drm helper for size checks (especially planar formats)? */ |
| 14907 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) |
| 14908 | return -EINVAL; |
| 14909 | |
| 14910 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
| 14911 | intel_fb->obj = obj; |
| 14912 | intel_fb->obj->framebuffer_references++; |
| 14913 | |
| 14914 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
| 14915 | if (ret) { |
| 14916 | DRM_ERROR("framebuffer init failed %d\n", ret); |
| 14917 | return ret; |
| 14918 | } |
| 14919 | |
| 14920 | return 0; |
| 14921 | } |
| 14922 | |
| 14923 | static struct drm_framebuffer * |
| 14924 | intel_user_framebuffer_create(struct drm_device *dev, |
| 14925 | struct drm_file *filp, |
| 14926 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
| 14927 | { |
| 14928 | struct drm_framebuffer *fb; |
| 14929 | struct drm_i915_gem_object *obj; |
| 14930 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
| 14931 | |
| 14932 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
| 14933 | mode_cmd.handles[0])); |
| 14934 | if (&obj->base == NULL) |
| 14935 | return ERR_PTR(-ENOENT); |
| 14936 | |
| 14937 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
| 14938 | if (IS_ERR(fb)) |
| 14939 | drm_gem_object_unreference_unlocked(&obj->base); |
| 14940 | |
| 14941 | return fb; |
| 14942 | } |
| 14943 | |
| 14944 | #ifndef CONFIG_DRM_FBDEV_EMULATION |
| 14945 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
| 14946 | { |
| 14947 | } |
| 14948 | #endif |
| 14949 | |
| 14950 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
| 14951 | .fb_create = intel_user_framebuffer_create, |
| 14952 | .output_poll_changed = intel_fbdev_output_poll_changed, |
| 14953 | .atomic_check = intel_atomic_check, |
| 14954 | .atomic_commit = intel_atomic_commit, |
| 14955 | .atomic_state_alloc = intel_atomic_state_alloc, |
| 14956 | .atomic_state_clear = intel_atomic_state_clear, |
| 14957 | }; |
| 14958 | |
| 14959 | /* Set up chip specific display functions */ |
| 14960 | static void intel_init_display(struct drm_device *dev) |
| 14961 | { |
| 14962 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 14963 | |
| 14964 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
| 14965 | dev_priv->display.find_dpll = g4x_find_best_dpll; |
| 14966 | else if (IS_CHERRYVIEW(dev)) |
| 14967 | dev_priv->display.find_dpll = chv_find_best_dpll; |
| 14968 | else if (IS_VALLEYVIEW(dev)) |
| 14969 | dev_priv->display.find_dpll = vlv_find_best_dpll; |
| 14970 | else if (IS_PINEVIEW(dev)) |
| 14971 | dev_priv->display.find_dpll = pnv_find_best_dpll; |
| 14972 | else |
| 14973 | dev_priv->display.find_dpll = i9xx_find_best_dpll; |
| 14974 | |
| 14975 | if (INTEL_INFO(dev)->gen >= 9) { |
| 14976 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
| 14977 | dev_priv->display.get_initial_plane_config = |
| 14978 | skylake_get_initial_plane_config; |
| 14979 | dev_priv->display.crtc_compute_clock = |
| 14980 | haswell_crtc_compute_clock; |
| 14981 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
| 14982 | dev_priv->display.crtc_disable = haswell_crtc_disable; |
| 14983 | } else if (HAS_DDI(dev)) { |
| 14984 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
| 14985 | dev_priv->display.get_initial_plane_config = |
| 14986 | ironlake_get_initial_plane_config; |
| 14987 | dev_priv->display.crtc_compute_clock = |
| 14988 | haswell_crtc_compute_clock; |
| 14989 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
| 14990 | dev_priv->display.crtc_disable = haswell_crtc_disable; |
| 14991 | } else if (HAS_PCH_SPLIT(dev)) { |
| 14992 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
| 14993 | dev_priv->display.get_initial_plane_config = |
| 14994 | ironlake_get_initial_plane_config; |
| 14995 | dev_priv->display.crtc_compute_clock = |
| 14996 | ironlake_crtc_compute_clock; |
| 14997 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
| 14998 | dev_priv->display.crtc_disable = ironlake_crtc_disable; |
| 14999 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
| 15000 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
| 15001 | dev_priv->display.get_initial_plane_config = |
| 15002 | i9xx_get_initial_plane_config; |
| 15003 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
| 15004 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
| 15005 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
| 15006 | } else { |
| 15007 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
| 15008 | dev_priv->display.get_initial_plane_config = |
| 15009 | i9xx_get_initial_plane_config; |
| 15010 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
| 15011 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
| 15012 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
| 15013 | } |
| 15014 | |
| 15015 | /* Returns the core display clock speed */ |
| 15016 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
| 15017 | dev_priv->display.get_display_clock_speed = |
| 15018 | skylake_get_display_clock_speed; |
| 15019 | else if (IS_BROXTON(dev)) |
| 15020 | dev_priv->display.get_display_clock_speed = |
| 15021 | broxton_get_display_clock_speed; |
| 15022 | else if (IS_BROADWELL(dev)) |
| 15023 | dev_priv->display.get_display_clock_speed = |
| 15024 | broadwell_get_display_clock_speed; |
| 15025 | else if (IS_HASWELL(dev)) |
| 15026 | dev_priv->display.get_display_clock_speed = |
| 15027 | haswell_get_display_clock_speed; |
| 15028 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
| 15029 | dev_priv->display.get_display_clock_speed = |
| 15030 | valleyview_get_display_clock_speed; |
| 15031 | else if (IS_GEN5(dev)) |
| 15032 | dev_priv->display.get_display_clock_speed = |
| 15033 | ilk_get_display_clock_speed; |
| 15034 | else if (IS_I945G(dev) || IS_BROADWATER(dev) || |
| 15035 | IS_GEN6(dev) || IS_IVYBRIDGE(dev)) |
| 15036 | dev_priv->display.get_display_clock_speed = |
| 15037 | i945_get_display_clock_speed; |
| 15038 | else if (IS_GM45(dev)) |
| 15039 | dev_priv->display.get_display_clock_speed = |
| 15040 | gm45_get_display_clock_speed; |
| 15041 | else if (IS_CRESTLINE(dev)) |
| 15042 | dev_priv->display.get_display_clock_speed = |
| 15043 | i965gm_get_display_clock_speed; |
| 15044 | else if (IS_PINEVIEW(dev)) |
| 15045 | dev_priv->display.get_display_clock_speed = |
| 15046 | pnv_get_display_clock_speed; |
| 15047 | else if (IS_G33(dev) || IS_G4X(dev)) |
| 15048 | dev_priv->display.get_display_clock_speed = |
| 15049 | g33_get_display_clock_speed; |
| 15050 | else if (IS_I915G(dev)) |
| 15051 | dev_priv->display.get_display_clock_speed = |
| 15052 | i915_get_display_clock_speed; |
| 15053 | else if (IS_I945GM(dev) || IS_845G(dev)) |
| 15054 | dev_priv->display.get_display_clock_speed = |
| 15055 | i9xx_misc_get_display_clock_speed; |
| 15056 | else if (IS_I915GM(dev)) |
| 15057 | dev_priv->display.get_display_clock_speed = |
| 15058 | i915gm_get_display_clock_speed; |
| 15059 | else if (IS_I865G(dev)) |
| 15060 | dev_priv->display.get_display_clock_speed = |
| 15061 | i865_get_display_clock_speed; |
| 15062 | else if (IS_I85X(dev)) |
| 15063 | dev_priv->display.get_display_clock_speed = |
| 15064 | i85x_get_display_clock_speed; |
| 15065 | else { /* 830 */ |
| 15066 | WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n"); |
| 15067 | dev_priv->display.get_display_clock_speed = |
| 15068 | i830_get_display_clock_speed; |
| 15069 | } |
| 15070 | |
| 15071 | if (IS_GEN5(dev)) { |
| 15072 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
| 15073 | } else if (IS_GEN6(dev)) { |
| 15074 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
| 15075 | } else if (IS_IVYBRIDGE(dev)) { |
| 15076 | /* FIXME: detect B0+ stepping and use auto training */ |
| 15077 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; |
| 15078 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
| 15079 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
| 15080 | if (IS_BROADWELL(dev)) { |
| 15081 | dev_priv->display.modeset_commit_cdclk = |
| 15082 | broadwell_modeset_commit_cdclk; |
| 15083 | dev_priv->display.modeset_calc_cdclk = |
| 15084 | broadwell_modeset_calc_cdclk; |
| 15085 | } |
| 15086 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
| 15087 | dev_priv->display.modeset_commit_cdclk = |
| 15088 | valleyview_modeset_commit_cdclk; |
| 15089 | dev_priv->display.modeset_calc_cdclk = |
| 15090 | valleyview_modeset_calc_cdclk; |
| 15091 | } else if (IS_BROXTON(dev)) { |
| 15092 | dev_priv->display.modeset_commit_cdclk = |
| 15093 | broxton_modeset_commit_cdclk; |
| 15094 | dev_priv->display.modeset_calc_cdclk = |
| 15095 | broxton_modeset_calc_cdclk; |
| 15096 | } |
| 15097 | |
| 15098 | switch (INTEL_INFO(dev)->gen) { |
| 15099 | case 2: |
| 15100 | dev_priv->display.queue_flip = intel_gen2_queue_flip; |
| 15101 | break; |
| 15102 | |
| 15103 | case 3: |
| 15104 | dev_priv->display.queue_flip = intel_gen3_queue_flip; |
| 15105 | break; |
| 15106 | |
| 15107 | case 4: |
| 15108 | case 5: |
| 15109 | dev_priv->display.queue_flip = intel_gen4_queue_flip; |
| 15110 | break; |
| 15111 | |
| 15112 | case 6: |
| 15113 | dev_priv->display.queue_flip = intel_gen6_queue_flip; |
| 15114 | break; |
| 15115 | case 7: |
| 15116 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
| 15117 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
| 15118 | break; |
| 15119 | case 9: |
| 15120 | /* Drop through - unsupported since execlist only. */ |
| 15121 | default: |
| 15122 | /* Default just returns -ENODEV to indicate unsupported */ |
| 15123 | dev_priv->display.queue_flip = intel_default_queue_flip; |
| 15124 | } |
| 15125 | |
| 15126 | mutex_init(&dev_priv->pps_mutex); |
| 15127 | } |
| 15128 | |
| 15129 | /* |
| 15130 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, |
| 15131 | * resume, or other times. This quirk makes sure that's the case for |
| 15132 | * affected systems. |
| 15133 | */ |
| 15134 | static void quirk_pipea_force(struct drm_device *dev) |
| 15135 | { |
| 15136 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 15137 | |
| 15138 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; |
| 15139 | DRM_INFO("applying pipe a force quirk\n"); |
| 15140 | } |
| 15141 | |
| 15142 | static void quirk_pipeb_force(struct drm_device *dev) |
| 15143 | { |
| 15144 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 15145 | |
| 15146 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; |
| 15147 | DRM_INFO("applying pipe b force quirk\n"); |
| 15148 | } |
| 15149 | |
| 15150 | /* |
| 15151 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason |
| 15152 | */ |
| 15153 | static void quirk_ssc_force_disable(struct drm_device *dev) |
| 15154 | { |
| 15155 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 15156 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; |
| 15157 | DRM_INFO("applying lvds SSC disable quirk\n"); |
| 15158 | } |
| 15159 | |
| 15160 | /* |
| 15161 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
| 15162 | * brightness value |
| 15163 | */ |
| 15164 | static void quirk_invert_brightness(struct drm_device *dev) |
| 15165 | { |
| 15166 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 15167 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
| 15168 | DRM_INFO("applying inverted panel brightness quirk\n"); |
| 15169 | } |
| 15170 | |
| 15171 | /* Some VBT's incorrectly indicate no backlight is present */ |
| 15172 | static void quirk_backlight_present(struct drm_device *dev) |
| 15173 | { |
| 15174 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 15175 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; |
| 15176 | DRM_INFO("applying backlight present quirk\n"); |
| 15177 | } |
| 15178 | |
| 15179 | struct intel_quirk { |
| 15180 | int device; |
| 15181 | int subsystem_vendor; |
| 15182 | int subsystem_device; |
| 15183 | void (*hook)(struct drm_device *dev); |
| 15184 | }; |
| 15185 | |
| 15186 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
| 15187 | struct intel_dmi_quirk { |
| 15188 | void (*hook)(struct drm_device *dev); |
| 15189 | const struct dmi_system_id (*dmi_id_list)[]; |
| 15190 | }; |
| 15191 | |
| 15192 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) |
| 15193 | { |
| 15194 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); |
| 15195 | return 1; |
| 15196 | } |
| 15197 | |
| 15198 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { |
| 15199 | { |
| 15200 | .dmi_id_list = &(const struct dmi_system_id[]) { |
| 15201 | { |
| 15202 | .callback = intel_dmi_reverse_brightness, |
| 15203 | .ident = "NCR Corporation", |
| 15204 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), |
| 15205 | DMI_MATCH(DMI_PRODUCT_NAME, ""), |
| 15206 | }, |
| 15207 | }, |
| 15208 | { } /* terminating entry */ |
| 15209 | }, |
| 15210 | .hook = quirk_invert_brightness, |
| 15211 | }, |
| 15212 | }; |
| 15213 | |
| 15214 | static struct intel_quirk intel_quirks[] = { |
| 15215 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
| 15216 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, |
| 15217 | |
| 15218 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
| 15219 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, |
| 15220 | |
| 15221 | /* 830 needs to leave pipe A & dpll A up */ |
| 15222 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
| 15223 | |
| 15224 | /* 830 needs to leave pipe B & dpll B up */ |
| 15225 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, |
| 15226 | |
| 15227 | /* Lenovo U160 cannot use SSC on LVDS */ |
| 15228 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, |
| 15229 | |
| 15230 | /* Sony Vaio Y cannot use SSC on LVDS */ |
| 15231 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, |
| 15232 | |
| 15233 | /* Acer Aspire 5734Z must invert backlight brightness */ |
| 15234 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, |
| 15235 | |
| 15236 | /* Acer/eMachines G725 */ |
| 15237 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, |
| 15238 | |
| 15239 | /* Acer/eMachines e725 */ |
| 15240 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, |
| 15241 | |
| 15242 | /* Acer/Packard Bell NCL20 */ |
| 15243 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, |
| 15244 | |
| 15245 | /* Acer Aspire 4736Z */ |
| 15246 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, |
| 15247 | |
| 15248 | /* Acer Aspire 5336 */ |
| 15249 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, |
| 15250 | |
| 15251 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ |
| 15252 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, |
| 15253 | |
| 15254 | /* Acer C720 Chromebook (Core i3 4005U) */ |
| 15255 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, |
| 15256 | |
| 15257 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
| 15258 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, |
| 15259 | |
| 15260 | /* Apple Macbook 4,1 */ |
| 15261 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, |
| 15262 | |
| 15263 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
| 15264 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, |
| 15265 | |
| 15266 | /* HP Chromebook 14 (Celeron 2955U) */ |
| 15267 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, |
| 15268 | |
| 15269 | /* Dell Chromebook 11 */ |
| 15270 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, |
| 15271 | |
| 15272 | /* Dell Chromebook 11 (2015 version) */ |
| 15273 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, |
| 15274 | }; |
| 15275 | |
| 15276 | static void intel_init_quirks(struct drm_device *dev) |
| 15277 | { |
| 15278 | struct pci_dev *d = dev->pdev; |
| 15279 | int i; |
| 15280 | |
| 15281 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { |
| 15282 | struct intel_quirk *q = &intel_quirks[i]; |
| 15283 | |
| 15284 | if (d->device == q->device && |
| 15285 | (d->subsystem_vendor == q->subsystem_vendor || |
| 15286 | q->subsystem_vendor == PCI_ANY_ID) && |
| 15287 | (d->subsystem_device == q->subsystem_device || |
| 15288 | q->subsystem_device == PCI_ANY_ID)) |
| 15289 | q->hook(dev); |
| 15290 | } |
| 15291 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
| 15292 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) |
| 15293 | intel_dmi_quirks[i].hook(dev); |
| 15294 | } |
| 15295 | } |
| 15296 | |
| 15297 | /* Disable the VGA plane that we never use */ |
| 15298 | static void i915_disable_vga(struct drm_device *dev) |
| 15299 | { |
| 15300 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 15301 | u8 sr1; |
| 15302 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
| 15303 | |
| 15304 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
| 15305 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
| 15306 | outb(SR01, VGA_SR_INDEX); |
| 15307 | sr1 = inb(VGA_SR_DATA); |
| 15308 | outb(sr1 | 1<<5, VGA_SR_DATA); |
| 15309 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); |
| 15310 | udelay(300); |
| 15311 | |
| 15312 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
| 15313 | POSTING_READ(vga_reg); |
| 15314 | } |
| 15315 | |
| 15316 | void intel_modeset_init_hw(struct drm_device *dev) |
| 15317 | { |
| 15318 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 15319 | |
| 15320 | intel_update_cdclk(dev); |
| 15321 | |
| 15322 | dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq; |
| 15323 | |
| 15324 | intel_init_clock_gating(dev); |
| 15325 | intel_enable_gt_powersave(dev); |
| 15326 | } |
| 15327 | |
| 15328 | /* |
| 15329 | * Calculate what we think the watermarks should be for the state we've read |
| 15330 | * out of the hardware and then immediately program those watermarks so that |
| 15331 | * we ensure the hardware settings match our internal state. |
| 15332 | * |
| 15333 | * We can calculate what we think WM's should be by creating a duplicate of the |
| 15334 | * current state (which was constructed during hardware readout) and running it |
| 15335 | * through the atomic check code to calculate new watermark values in the |
| 15336 | * state object. |
| 15337 | */ |
| 15338 | static void sanitize_watermarks(struct drm_device *dev) |
| 15339 | { |
| 15340 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 15341 | struct drm_atomic_state *state; |
| 15342 | struct drm_crtc *crtc; |
| 15343 | struct drm_crtc_state *cstate; |
| 15344 | struct drm_modeset_acquire_ctx ctx; |
| 15345 | int ret; |
| 15346 | int i; |
| 15347 | |
| 15348 | /* Only supported on platforms that use atomic watermark design */ |
| 15349 | if (!dev_priv->display.optimize_watermarks) |
| 15350 | return; |
| 15351 | |
| 15352 | /* |
| 15353 | * We need to hold connection_mutex before calling duplicate_state so |
| 15354 | * that the connector loop is protected. |
| 15355 | */ |
| 15356 | drm_modeset_acquire_init(&ctx, 0); |
| 15357 | retry: |
| 15358 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
| 15359 | if (ret == -EDEADLK) { |
| 15360 | drm_modeset_backoff(&ctx); |
| 15361 | goto retry; |
| 15362 | } else if (WARN_ON(ret)) { |
| 15363 | goto fail; |
| 15364 | } |
| 15365 | |
| 15366 | state = drm_atomic_helper_duplicate_state(dev, &ctx); |
| 15367 | if (WARN_ON(IS_ERR(state))) |
| 15368 | goto fail; |
| 15369 | |
| 15370 | /* |
| 15371 | * Hardware readout is the only time we don't want to calculate |
| 15372 | * intermediate watermarks (since we don't trust the current |
| 15373 | * watermarks). |
| 15374 | */ |
| 15375 | to_intel_atomic_state(state)->skip_intermediate_wm = true; |
| 15376 | |
| 15377 | ret = intel_atomic_check(dev, state); |
| 15378 | if (ret) { |
| 15379 | /* |
| 15380 | * If we fail here, it means that the hardware appears to be |
| 15381 | * programmed in a way that shouldn't be possible, given our |
| 15382 | * understanding of watermark requirements. This might mean a |
| 15383 | * mistake in the hardware readout code or a mistake in the |
| 15384 | * watermark calculations for a given platform. Raise a WARN |
| 15385 | * so that this is noticeable. |
| 15386 | * |
| 15387 | * If this actually happens, we'll have to just leave the |
| 15388 | * BIOS-programmed watermarks untouched and hope for the best. |
| 15389 | */ |
| 15390 | WARN(true, "Could not determine valid watermarks for inherited state\n"); |
| 15391 | goto fail; |
| 15392 | } |
| 15393 | |
| 15394 | /* Write calculated watermark values back */ |
| 15395 | to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config; |
| 15396 | for_each_crtc_in_state(state, crtc, cstate, i) { |
| 15397 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); |
| 15398 | |
| 15399 | cs->wm.need_postvbl_update = true; |
| 15400 | dev_priv->display.optimize_watermarks(cs); |
| 15401 | } |
| 15402 | |
| 15403 | drm_atomic_state_free(state); |
| 15404 | fail: |
| 15405 | drm_modeset_drop_locks(&ctx); |
| 15406 | drm_modeset_acquire_fini(&ctx); |
| 15407 | } |
| 15408 | |
| 15409 | void intel_modeset_init(struct drm_device *dev) |
| 15410 | { |
| 15411 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 15412 | int sprite, ret; |
| 15413 | enum pipe pipe; |
| 15414 | struct intel_crtc *crtc; |
| 15415 | |
| 15416 | drm_mode_config_init(dev); |
| 15417 | |
| 15418 | dev->mode_config.min_width = 0; |
| 15419 | dev->mode_config.min_height = 0; |
| 15420 | |
| 15421 | dev->mode_config.preferred_depth = 24; |
| 15422 | dev->mode_config.prefer_shadow = 1; |
| 15423 | |
| 15424 | dev->mode_config.allow_fb_modifiers = true; |
| 15425 | |
| 15426 | dev->mode_config.funcs = &intel_mode_funcs; |
| 15427 | |
| 15428 | intel_init_quirks(dev); |
| 15429 | |
| 15430 | intel_init_pm(dev); |
| 15431 | |
| 15432 | if (INTEL_INFO(dev)->num_pipes == 0) |
| 15433 | return; |
| 15434 | |
| 15435 | /* |
| 15436 | * There may be no VBT; and if the BIOS enabled SSC we can |
| 15437 | * just keep using it to avoid unnecessary flicker. Whereas if the |
| 15438 | * BIOS isn't using it, don't assume it will work even if the VBT |
| 15439 | * indicates as much. |
| 15440 | */ |
| 15441 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { |
| 15442 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & |
| 15443 | DREF_SSC1_ENABLE); |
| 15444 | |
| 15445 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { |
| 15446 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", |
| 15447 | bios_lvds_use_ssc ? "en" : "dis", |
| 15448 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); |
| 15449 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; |
| 15450 | } |
| 15451 | } |
| 15452 | |
| 15453 | intel_init_display(dev); |
| 15454 | intel_init_audio(dev); |
| 15455 | |
| 15456 | if (IS_GEN2(dev)) { |
| 15457 | dev->mode_config.max_width = 2048; |
| 15458 | dev->mode_config.max_height = 2048; |
| 15459 | } else if (IS_GEN3(dev)) { |
| 15460 | dev->mode_config.max_width = 4096; |
| 15461 | dev->mode_config.max_height = 4096; |
| 15462 | } else { |
| 15463 | dev->mode_config.max_width = 8192; |
| 15464 | dev->mode_config.max_height = 8192; |
| 15465 | } |
| 15466 | |
| 15467 | if (IS_845G(dev) || IS_I865G(dev)) { |
| 15468 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; |
| 15469 | dev->mode_config.cursor_height = 1023; |
| 15470 | } else if (IS_GEN2(dev)) { |
| 15471 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
| 15472 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; |
| 15473 | } else { |
| 15474 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; |
| 15475 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; |
| 15476 | } |
| 15477 | |
| 15478 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
| 15479 | |
| 15480 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
| 15481 | INTEL_INFO(dev)->num_pipes, |
| 15482 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); |
| 15483 | |
| 15484 | for_each_pipe(dev_priv, pipe) { |
| 15485 | intel_crtc_init(dev, pipe); |
| 15486 | for_each_sprite(dev_priv, pipe, sprite) { |
| 15487 | ret = intel_plane_init(dev, pipe, sprite); |
| 15488 | if (ret) |
| 15489 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
| 15490 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
| 15491 | } |
| 15492 | } |
| 15493 | |
| 15494 | intel_update_czclk(dev_priv); |
| 15495 | intel_update_cdclk(dev); |
| 15496 | |
| 15497 | intel_shared_dpll_init(dev); |
| 15498 | |
| 15499 | /* Just disable it once at startup */ |
| 15500 | i915_disable_vga(dev); |
| 15501 | intel_setup_outputs(dev); |
| 15502 | |
| 15503 | drm_modeset_lock_all(dev); |
| 15504 | intel_modeset_setup_hw_state(dev); |
| 15505 | drm_modeset_unlock_all(dev); |
| 15506 | |
| 15507 | for_each_intel_crtc(dev, crtc) { |
| 15508 | struct intel_initial_plane_config plane_config = {}; |
| 15509 | |
| 15510 | if (!crtc->active) |
| 15511 | continue; |
| 15512 | |
| 15513 | /* |
| 15514 | * Note that reserving the BIOS fb up front prevents us |
| 15515 | * from stuffing other stolen allocations like the ring |
| 15516 | * on top. This prevents some ugliness at boot time, and |
| 15517 | * can even allow for smooth boot transitions if the BIOS |
| 15518 | * fb is large enough for the active pipe configuration. |
| 15519 | */ |
| 15520 | dev_priv->display.get_initial_plane_config(crtc, |
| 15521 | &plane_config); |
| 15522 | |
| 15523 | /* |
| 15524 | * If the fb is shared between multiple heads, we'll |
| 15525 | * just get the first one. |
| 15526 | */ |
| 15527 | intel_find_initial_plane_obj(crtc, &plane_config); |
| 15528 | } |
| 15529 | |
| 15530 | /* |
| 15531 | * Make sure hardware watermarks really match the state we read out. |
| 15532 | * Note that we need to do this after reconstructing the BIOS fb's |
| 15533 | * since the watermark calculation done here will use pstate->fb. |
| 15534 | */ |
| 15535 | sanitize_watermarks(dev); |
| 15536 | } |
| 15537 | |
| 15538 | static void intel_enable_pipe_a(struct drm_device *dev) |
| 15539 | { |
| 15540 | struct intel_connector *connector; |
| 15541 | struct drm_connector *crt = NULL; |
| 15542 | struct intel_load_detect_pipe load_detect_temp; |
| 15543 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
| 15544 | |
| 15545 | /* We can't just switch on the pipe A, we need to set things up with a |
| 15546 | * proper mode and output configuration. As a gross hack, enable pipe A |
| 15547 | * by enabling the load detect pipe once. */ |
| 15548 | for_each_intel_connector(dev, connector) { |
| 15549 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
| 15550 | crt = &connector->base; |
| 15551 | break; |
| 15552 | } |
| 15553 | } |
| 15554 | |
| 15555 | if (!crt) |
| 15556 | return; |
| 15557 | |
| 15558 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
| 15559 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
| 15560 | } |
| 15561 | |
| 15562 | static bool |
| 15563 | intel_check_plane_mapping(struct intel_crtc *crtc) |
| 15564 | { |
| 15565 | struct drm_device *dev = crtc->base.dev; |
| 15566 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 15567 | u32 val; |
| 15568 | |
| 15569 | if (INTEL_INFO(dev)->num_pipes == 1) |
| 15570 | return true; |
| 15571 | |
| 15572 | val = I915_READ(DSPCNTR(!crtc->plane)); |
| 15573 | |
| 15574 | if ((val & DISPLAY_PLANE_ENABLE) && |
| 15575 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) |
| 15576 | return false; |
| 15577 | |
| 15578 | return true; |
| 15579 | } |
| 15580 | |
| 15581 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
| 15582 | { |
| 15583 | struct drm_device *dev = crtc->base.dev; |
| 15584 | struct intel_encoder *encoder; |
| 15585 | |
| 15586 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
| 15587 | return true; |
| 15588 | |
| 15589 | return false; |
| 15590 | } |
| 15591 | |
| 15592 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
| 15593 | { |
| 15594 | struct drm_device *dev = crtc->base.dev; |
| 15595 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 15596 | i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder); |
| 15597 | |
| 15598 | /* Clear any frame start delays used for debugging left by the BIOS */ |
| 15599 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
| 15600 | |
| 15601 | /* restore vblank interrupts to correct state */ |
| 15602 | drm_crtc_vblank_reset(&crtc->base); |
| 15603 | if (crtc->active) { |
| 15604 | struct intel_plane *plane; |
| 15605 | |
| 15606 | drm_crtc_vblank_on(&crtc->base); |
| 15607 | |
| 15608 | /* Disable everything but the primary plane */ |
| 15609 | for_each_intel_plane_on_crtc(dev, crtc, plane) { |
| 15610 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) |
| 15611 | continue; |
| 15612 | |
| 15613 | plane->disable_plane(&plane->base, &crtc->base); |
| 15614 | } |
| 15615 | } |
| 15616 | |
| 15617 | /* We need to sanitize the plane -> pipe mapping first because this will |
| 15618 | * disable the crtc (and hence change the state) if it is wrong. Note |
| 15619 | * that gen4+ has a fixed plane -> pipe mapping. */ |
| 15620 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { |
| 15621 | bool plane; |
| 15622 | |
| 15623 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
| 15624 | crtc->base.base.id); |
| 15625 | |
| 15626 | /* Pipe has the wrong plane attached and the plane is active. |
| 15627 | * Temporarily change the plane mapping and disable everything |
| 15628 | * ... */ |
| 15629 | plane = crtc->plane; |
| 15630 | to_intel_plane_state(crtc->base.primary->state)->visible = true; |
| 15631 | crtc->plane = !plane; |
| 15632 | intel_crtc_disable_noatomic(&crtc->base); |
| 15633 | crtc->plane = plane; |
| 15634 | } |
| 15635 | |
| 15636 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
| 15637 | crtc->pipe == PIPE_A && !crtc->active) { |
| 15638 | /* BIOS forgot to enable pipe A, this mostly happens after |
| 15639 | * resume. Force-enable the pipe to fix this, the update_dpms |
| 15640 | * call below we restore the pipe to the right state, but leave |
| 15641 | * the required bits on. */ |
| 15642 | intel_enable_pipe_a(dev); |
| 15643 | } |
| 15644 | |
| 15645 | /* Adjust the state of the output pipe according to whether we |
| 15646 | * have active connectors/encoders. */ |
| 15647 | if (!intel_crtc_has_encoders(crtc)) |
| 15648 | intel_crtc_disable_noatomic(&crtc->base); |
| 15649 | |
| 15650 | if (crtc->active != crtc->base.state->active) { |
| 15651 | struct intel_encoder *encoder; |
| 15652 | |
| 15653 | /* This can happen either due to bugs in the get_hw_state |
| 15654 | * functions or because of calls to intel_crtc_disable_noatomic, |
| 15655 | * or because the pipe is force-enabled due to the |
| 15656 | * pipe A quirk. */ |
| 15657 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", |
| 15658 | crtc->base.base.id, |
| 15659 | crtc->base.state->enable ? "enabled" : "disabled", |
| 15660 | crtc->active ? "enabled" : "disabled"); |
| 15661 | |
| 15662 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0); |
| 15663 | crtc->base.state->active = crtc->active; |
| 15664 | crtc->base.enabled = crtc->active; |
| 15665 | |
| 15666 | /* Because we only establish the connector -> encoder -> |
| 15667 | * crtc links if something is active, this means the |
| 15668 | * crtc is now deactivated. Break the links. connector |
| 15669 | * -> encoder links are only establish when things are |
| 15670 | * actually up, hence no need to break them. */ |
| 15671 | WARN_ON(crtc->active); |
| 15672 | |
| 15673 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
| 15674 | encoder->base.crtc = NULL; |
| 15675 | } |
| 15676 | |
| 15677 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
| 15678 | /* |
| 15679 | * We start out with underrun reporting disabled to avoid races. |
| 15680 | * For correct bookkeeping mark this on active crtcs. |
| 15681 | * |
| 15682 | * Also on gmch platforms we dont have any hardware bits to |
| 15683 | * disable the underrun reporting. Which means we need to start |
| 15684 | * out with underrun reporting disabled also on inactive pipes, |
| 15685 | * since otherwise we'll complain about the garbage we read when |
| 15686 | * e.g. coming up after runtime pm. |
| 15687 | * |
| 15688 | * No protection against concurrent access is required - at |
| 15689 | * worst a fifo underrun happens which also sets this to false. |
| 15690 | */ |
| 15691 | crtc->cpu_fifo_underrun_disabled = true; |
| 15692 | crtc->pch_fifo_underrun_disabled = true; |
| 15693 | } |
| 15694 | } |
| 15695 | |
| 15696 | static void intel_sanitize_encoder(struct intel_encoder *encoder) |
| 15697 | { |
| 15698 | struct intel_connector *connector; |
| 15699 | struct drm_device *dev = encoder->base.dev; |
| 15700 | bool active = false; |
| 15701 | |
| 15702 | /* We need to check both for a crtc link (meaning that the |
| 15703 | * encoder is active and trying to read from a pipe) and the |
| 15704 | * pipe itself being active. */ |
| 15705 | bool has_active_crtc = encoder->base.crtc && |
| 15706 | to_intel_crtc(encoder->base.crtc)->active; |
| 15707 | |
| 15708 | for_each_intel_connector(dev, connector) { |
| 15709 | if (connector->base.encoder != &encoder->base) |
| 15710 | continue; |
| 15711 | |
| 15712 | active = true; |
| 15713 | break; |
| 15714 | } |
| 15715 | |
| 15716 | if (active && !has_active_crtc) { |
| 15717 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
| 15718 | encoder->base.base.id, |
| 15719 | encoder->base.name); |
| 15720 | |
| 15721 | /* Connector is active, but has no active pipe. This is |
| 15722 | * fallout from our resume register restoring. Disable |
| 15723 | * the encoder manually again. */ |
| 15724 | if (encoder->base.crtc) { |
| 15725 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", |
| 15726 | encoder->base.base.id, |
| 15727 | encoder->base.name); |
| 15728 | encoder->disable(encoder); |
| 15729 | if (encoder->post_disable) |
| 15730 | encoder->post_disable(encoder); |
| 15731 | } |
| 15732 | encoder->base.crtc = NULL; |
| 15733 | |
| 15734 | /* Inconsistent output/port/pipe state happens presumably due to |
| 15735 | * a bug in one of the get_hw_state functions. Or someplace else |
| 15736 | * in our code, like the register restore mess on resume. Clamp |
| 15737 | * things to off as a safer default. */ |
| 15738 | for_each_intel_connector(dev, connector) { |
| 15739 | if (connector->encoder != encoder) |
| 15740 | continue; |
| 15741 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
| 15742 | connector->base.encoder = NULL; |
| 15743 | } |
| 15744 | } |
| 15745 | /* Enabled encoders without active connectors will be fixed in |
| 15746 | * the crtc fixup. */ |
| 15747 | } |
| 15748 | |
| 15749 | void i915_redisable_vga_power_on(struct drm_device *dev) |
| 15750 | { |
| 15751 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 15752 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
| 15753 | |
| 15754 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
| 15755 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); |
| 15756 | i915_disable_vga(dev); |
| 15757 | } |
| 15758 | } |
| 15759 | |
| 15760 | void i915_redisable_vga(struct drm_device *dev) |
| 15761 | { |
| 15762 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 15763 | |
| 15764 | /* This function can be called both from intel_modeset_setup_hw_state or |
| 15765 | * at a very early point in our resume sequence, where the power well |
| 15766 | * structures are not yet restored. Since this function is at a very |
| 15767 | * paranoid "someone might have enabled VGA while we were not looking" |
| 15768 | * level, just check if the power well is enabled instead of trying to |
| 15769 | * follow the "don't touch the power well if we don't need it" policy |
| 15770 | * the rest of the driver uses. */ |
| 15771 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA)) |
| 15772 | return; |
| 15773 | |
| 15774 | i915_redisable_vga_power_on(dev); |
| 15775 | } |
| 15776 | |
| 15777 | static bool primary_get_hw_state(struct intel_plane *plane) |
| 15778 | { |
| 15779 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
| 15780 | |
| 15781 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
| 15782 | } |
| 15783 | |
| 15784 | /* FIXME read out full plane state for all planes */ |
| 15785 | static void readout_plane_state(struct intel_crtc *crtc) |
| 15786 | { |
| 15787 | struct drm_plane *primary = crtc->base.primary; |
| 15788 | struct intel_plane_state *plane_state = |
| 15789 | to_intel_plane_state(primary->state); |
| 15790 | |
| 15791 | plane_state->visible = crtc->active && |
| 15792 | primary_get_hw_state(to_intel_plane(primary)); |
| 15793 | |
| 15794 | if (plane_state->visible) |
| 15795 | crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); |
| 15796 | } |
| 15797 | |
| 15798 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
| 15799 | { |
| 15800 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 15801 | enum pipe pipe; |
| 15802 | struct intel_crtc *crtc; |
| 15803 | struct intel_encoder *encoder; |
| 15804 | struct intel_connector *connector; |
| 15805 | int i; |
| 15806 | |
| 15807 | dev_priv->active_crtcs = 0; |
| 15808 | |
| 15809 | for_each_intel_crtc(dev, crtc) { |
| 15810 | struct intel_crtc_state *crtc_state = crtc->config; |
| 15811 | int pixclk = 0; |
| 15812 | |
| 15813 | __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base); |
| 15814 | memset(crtc_state, 0, sizeof(*crtc_state)); |
| 15815 | crtc_state->base.crtc = &crtc->base; |
| 15816 | |
| 15817 | crtc_state->base.active = crtc_state->base.enable = |
| 15818 | dev_priv->display.get_pipe_config(crtc, crtc_state); |
| 15819 | |
| 15820 | crtc->base.enabled = crtc_state->base.enable; |
| 15821 | crtc->active = crtc_state->base.active; |
| 15822 | |
| 15823 | if (crtc_state->base.active) { |
| 15824 | dev_priv->active_crtcs |= 1 << crtc->pipe; |
| 15825 | |
| 15826 | if (IS_BROADWELL(dev_priv)) { |
| 15827 | pixclk = ilk_pipe_pixel_rate(crtc_state); |
| 15828 | |
| 15829 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ |
| 15830 | if (crtc_state->ips_enabled) |
| 15831 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); |
| 15832 | } else if (IS_VALLEYVIEW(dev_priv) || |
| 15833 | IS_CHERRYVIEW(dev_priv) || |
| 15834 | IS_BROXTON(dev_priv)) |
| 15835 | pixclk = crtc_state->base.adjusted_mode.crtc_clock; |
| 15836 | else |
| 15837 | WARN_ON(dev_priv->display.modeset_calc_cdclk); |
| 15838 | } |
| 15839 | |
| 15840 | dev_priv->min_pixclk[crtc->pipe] = pixclk; |
| 15841 | |
| 15842 | readout_plane_state(crtc); |
| 15843 | |
| 15844 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", |
| 15845 | crtc->base.base.id, |
| 15846 | crtc->active ? "enabled" : "disabled"); |
| 15847 | } |
| 15848 | |
| 15849 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
| 15850 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
| 15851 | |
| 15852 | pll->on = pll->get_hw_state(dev_priv, pll, |
| 15853 | &pll->config.hw_state); |
| 15854 | pll->active = 0; |
| 15855 | pll->config.crtc_mask = 0; |
| 15856 | for_each_intel_crtc(dev, crtc) { |
| 15857 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { |
| 15858 | pll->active++; |
| 15859 | pll->config.crtc_mask |= 1 << crtc->pipe; |
| 15860 | } |
| 15861 | } |
| 15862 | |
| 15863 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
| 15864 | pll->name, pll->config.crtc_mask, pll->on); |
| 15865 | |
| 15866 | if (pll->config.crtc_mask) |
| 15867 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
| 15868 | } |
| 15869 | |
| 15870 | for_each_intel_encoder(dev, encoder) { |
| 15871 | pipe = 0; |
| 15872 | |
| 15873 | if (encoder->get_hw_state(encoder, &pipe)) { |
| 15874 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
| 15875 | encoder->base.crtc = &crtc->base; |
| 15876 | encoder->get_config(encoder, crtc->config); |
| 15877 | } else { |
| 15878 | encoder->base.crtc = NULL; |
| 15879 | } |
| 15880 | |
| 15881 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
| 15882 | encoder->base.base.id, |
| 15883 | encoder->base.name, |
| 15884 | encoder->base.crtc ? "enabled" : "disabled", |
| 15885 | pipe_name(pipe)); |
| 15886 | } |
| 15887 | |
| 15888 | for_each_intel_connector(dev, connector) { |
| 15889 | if (connector->get_hw_state(connector)) { |
| 15890 | connector->base.dpms = DRM_MODE_DPMS_ON; |
| 15891 | connector->base.encoder = &connector->encoder->base; |
| 15892 | } else { |
| 15893 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
| 15894 | connector->base.encoder = NULL; |
| 15895 | } |
| 15896 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", |
| 15897 | connector->base.base.id, |
| 15898 | connector->base.name, |
| 15899 | connector->base.encoder ? "enabled" : "disabled"); |
| 15900 | } |
| 15901 | |
| 15902 | for_each_intel_crtc(dev, crtc) { |
| 15903 | crtc->base.hwmode = crtc->config->base.adjusted_mode; |
| 15904 | |
| 15905 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); |
| 15906 | if (crtc->base.state->active) { |
| 15907 | intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); |
| 15908 | intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); |
| 15909 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); |
| 15910 | |
| 15911 | /* |
| 15912 | * The initial mode needs to be set in order to keep |
| 15913 | * the atomic core happy. It wants a valid mode if the |
| 15914 | * crtc's enabled, so we do the above call. |
| 15915 | * |
| 15916 | * At this point some state updated by the connectors |
| 15917 | * in their ->detect() callback has not run yet, so |
| 15918 | * no recalculation can be done yet. |
| 15919 | * |
| 15920 | * Even if we could do a recalculation and modeset |
| 15921 | * right now it would cause a double modeset if |
| 15922 | * fbdev or userspace chooses a different initial mode. |
| 15923 | * |
| 15924 | * If that happens, someone indicated they wanted a |
| 15925 | * mode change, which means it's safe to do a full |
| 15926 | * recalculation. |
| 15927 | */ |
| 15928 | crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; |
| 15929 | |
| 15930 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); |
| 15931 | update_scanline_offset(crtc); |
| 15932 | } |
| 15933 | } |
| 15934 | } |
| 15935 | |
| 15936 | /* Scan out the current hw modeset state, |
| 15937 | * and sanitizes it to the current state |
| 15938 | */ |
| 15939 | static void |
| 15940 | intel_modeset_setup_hw_state(struct drm_device *dev) |
| 15941 | { |
| 15942 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 15943 | enum pipe pipe; |
| 15944 | struct intel_crtc *crtc; |
| 15945 | struct intel_encoder *encoder; |
| 15946 | int i; |
| 15947 | |
| 15948 | intel_modeset_readout_hw_state(dev); |
| 15949 | |
| 15950 | /* HW state is read out, now we need to sanitize this mess. */ |
| 15951 | for_each_intel_encoder(dev, encoder) { |
| 15952 | intel_sanitize_encoder(encoder); |
| 15953 | } |
| 15954 | |
| 15955 | for_each_pipe(dev_priv, pipe) { |
| 15956 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
| 15957 | intel_sanitize_crtc(crtc); |
| 15958 | intel_dump_pipe_config(crtc, crtc->config, |
| 15959 | "[setup_hw_state]"); |
| 15960 | } |
| 15961 | |
| 15962 | intel_modeset_update_connector_atomic_state(dev); |
| 15963 | |
| 15964 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
| 15965 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
| 15966 | |
| 15967 | if (!pll->on || pll->active) |
| 15968 | continue; |
| 15969 | |
| 15970 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); |
| 15971 | |
| 15972 | pll->disable(dev_priv, pll); |
| 15973 | pll->on = false; |
| 15974 | } |
| 15975 | |
| 15976 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
| 15977 | vlv_wm_get_hw_state(dev); |
| 15978 | else if (IS_GEN9(dev)) |
| 15979 | skl_wm_get_hw_state(dev); |
| 15980 | else if (HAS_PCH_SPLIT(dev)) |
| 15981 | ilk_wm_get_hw_state(dev); |
| 15982 | |
| 15983 | for_each_intel_crtc(dev, crtc) { |
| 15984 | unsigned long put_domains; |
| 15985 | |
| 15986 | put_domains = modeset_get_crtc_power_domains(&crtc->base); |
| 15987 | if (WARN_ON(put_domains)) |
| 15988 | modeset_put_power_domains(dev_priv, put_domains); |
| 15989 | } |
| 15990 | intel_display_set_init_power(dev_priv, false); |
| 15991 | } |
| 15992 | |
| 15993 | void intel_display_resume(struct drm_device *dev) |
| 15994 | { |
| 15995 | struct drm_atomic_state *state = drm_atomic_state_alloc(dev); |
| 15996 | struct intel_connector *conn; |
| 15997 | struct intel_plane *plane; |
| 15998 | struct drm_crtc *crtc; |
| 15999 | int ret; |
| 16000 | |
| 16001 | if (!state) |
| 16002 | return; |
| 16003 | |
| 16004 | state->acquire_ctx = dev->mode_config.acquire_ctx; |
| 16005 | |
| 16006 | /* preserve complete old state, including dpll */ |
| 16007 | intel_atomic_get_shared_dpll_state(state); |
| 16008 | |
| 16009 | for_each_crtc(dev, crtc) { |
| 16010 | struct drm_crtc_state *crtc_state = |
| 16011 | drm_atomic_get_crtc_state(state, crtc); |
| 16012 | |
| 16013 | ret = PTR_ERR_OR_ZERO(crtc_state); |
| 16014 | if (ret) |
| 16015 | goto err; |
| 16016 | |
| 16017 | /* force a restore */ |
| 16018 | crtc_state->mode_changed = true; |
| 16019 | } |
| 16020 | |
| 16021 | for_each_intel_plane(dev, plane) { |
| 16022 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base)); |
| 16023 | if (ret) |
| 16024 | goto err; |
| 16025 | } |
| 16026 | |
| 16027 | for_each_intel_connector(dev, conn) { |
| 16028 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base)); |
| 16029 | if (ret) |
| 16030 | goto err; |
| 16031 | } |
| 16032 | |
| 16033 | intel_modeset_setup_hw_state(dev); |
| 16034 | |
| 16035 | i915_redisable_vga(dev); |
| 16036 | ret = drm_atomic_commit(state); |
| 16037 | if (!ret) |
| 16038 | return; |
| 16039 | |
| 16040 | err: |
| 16041 | DRM_ERROR("Restoring old state failed with %i\n", ret); |
| 16042 | drm_atomic_state_free(state); |
| 16043 | } |
| 16044 | |
| 16045 | void intel_modeset_gem_init(struct drm_device *dev) |
| 16046 | { |
| 16047 | struct drm_crtc *c; |
| 16048 | struct drm_i915_gem_object *obj; |
| 16049 | int ret; |
| 16050 | |
| 16051 | mutex_lock(&dev->struct_mutex); |
| 16052 | intel_init_gt_powersave(dev); |
| 16053 | mutex_unlock(&dev->struct_mutex); |
| 16054 | |
| 16055 | intel_modeset_init_hw(dev); |
| 16056 | |
| 16057 | intel_setup_overlay(dev); |
| 16058 | |
| 16059 | /* |
| 16060 | * Make sure any fbs we allocated at startup are properly |
| 16061 | * pinned & fenced. When we do the allocation it's too early |
| 16062 | * for this. |
| 16063 | */ |
| 16064 | for_each_crtc(dev, c) { |
| 16065 | obj = intel_fb_obj(c->primary->fb); |
| 16066 | if (obj == NULL) |
| 16067 | continue; |
| 16068 | |
| 16069 | mutex_lock(&dev->struct_mutex); |
| 16070 | ret = intel_pin_and_fence_fb_obj(c->primary, |
| 16071 | c->primary->fb, |
| 16072 | c->primary->state); |
| 16073 | mutex_unlock(&dev->struct_mutex); |
| 16074 | if (ret) { |
| 16075 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
| 16076 | to_intel_crtc(c)->pipe); |
| 16077 | drm_framebuffer_unreference(c->primary->fb); |
| 16078 | c->primary->fb = NULL; |
| 16079 | c->primary->crtc = c->primary->state->crtc = NULL; |
| 16080 | update_state_fb(c->primary); |
| 16081 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
| 16082 | } |
| 16083 | } |
| 16084 | |
| 16085 | intel_backlight_register(dev); |
| 16086 | } |
| 16087 | |
| 16088 | void intel_connector_unregister(struct intel_connector *intel_connector) |
| 16089 | { |
| 16090 | struct drm_connector *connector = &intel_connector->base; |
| 16091 | |
| 16092 | intel_panel_destroy_backlight(connector); |
| 16093 | drm_connector_unregister(connector); |
| 16094 | } |
| 16095 | |
| 16096 | void intel_modeset_cleanup(struct drm_device *dev) |
| 16097 | { |
| 16098 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 16099 | struct intel_connector *connector; |
| 16100 | |
| 16101 | intel_disable_gt_powersave(dev); |
| 16102 | |
| 16103 | intel_backlight_unregister(dev); |
| 16104 | |
| 16105 | /* |
| 16106 | * Interrupts and polling as the first thing to avoid creating havoc. |
| 16107 | * Too much stuff here (turning of connectors, ...) would |
| 16108 | * experience fancy races otherwise. |
| 16109 | */ |
| 16110 | intel_irq_uninstall(dev_priv); |
| 16111 | |
| 16112 | /* |
| 16113 | * Due to the hpd irq storm handling the hotplug work can re-arm the |
| 16114 | * poll handlers. Hence disable polling after hpd handling is shut down. |
| 16115 | */ |
| 16116 | drm_kms_helper_poll_fini(dev); |
| 16117 | |
| 16118 | intel_unregister_dsm_handler(); |
| 16119 | |
| 16120 | intel_fbc_disable(dev_priv); |
| 16121 | |
| 16122 | /* flush any delayed tasks or pending work */ |
| 16123 | flush_scheduled_work(); |
| 16124 | |
| 16125 | /* destroy the backlight and sysfs files before encoders/connectors */ |
| 16126 | for_each_intel_connector(dev, connector) |
| 16127 | connector->unregister(connector); |
| 16128 | |
| 16129 | drm_mode_config_cleanup(dev); |
| 16130 | |
| 16131 | intel_cleanup_overlay(dev); |
| 16132 | |
| 16133 | mutex_lock(&dev->struct_mutex); |
| 16134 | intel_cleanup_gt_powersave(dev); |
| 16135 | mutex_unlock(&dev->struct_mutex); |
| 16136 | } |
| 16137 | |
| 16138 | /* |
| 16139 | * Return which encoder is currently attached for connector. |
| 16140 | */ |
| 16141 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
| 16142 | { |
| 16143 | return &intel_attached_encoder(connector)->base; |
| 16144 | } |
| 16145 | |
| 16146 | void intel_connector_attach_encoder(struct intel_connector *connector, |
| 16147 | struct intel_encoder *encoder) |
| 16148 | { |
| 16149 | connector->encoder = encoder; |
| 16150 | drm_mode_connector_attach_encoder(&connector->base, |
| 16151 | &encoder->base); |
| 16152 | } |
| 16153 | |
| 16154 | /* |
| 16155 | * set vga decode state - true == enable VGA decode |
| 16156 | */ |
| 16157 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) |
| 16158 | { |
| 16159 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 16160 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
| 16161 | u16 gmch_ctrl; |
| 16162 | |
| 16163 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
| 16164 | DRM_ERROR("failed to read control word\n"); |
| 16165 | return -EIO; |
| 16166 | } |
| 16167 | |
| 16168 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
| 16169 | return 0; |
| 16170 | |
| 16171 | if (state) |
| 16172 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; |
| 16173 | else |
| 16174 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; |
| 16175 | |
| 16176 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { |
| 16177 | DRM_ERROR("failed to write control word\n"); |
| 16178 | return -EIO; |
| 16179 | } |
| 16180 | |
| 16181 | return 0; |
| 16182 | } |
| 16183 | |
| 16184 | struct intel_display_error_state { |
| 16185 | |
| 16186 | u32 power_well_driver; |
| 16187 | |
| 16188 | int num_transcoders; |
| 16189 | |
| 16190 | struct intel_cursor_error_state { |
| 16191 | u32 control; |
| 16192 | u32 position; |
| 16193 | u32 base; |
| 16194 | u32 size; |
| 16195 | } cursor[I915_MAX_PIPES]; |
| 16196 | |
| 16197 | struct intel_pipe_error_state { |
| 16198 | bool power_domain_on; |
| 16199 | u32 source; |
| 16200 | u32 stat; |
| 16201 | } pipe[I915_MAX_PIPES]; |
| 16202 | |
| 16203 | struct intel_plane_error_state { |
| 16204 | u32 control; |
| 16205 | u32 stride; |
| 16206 | u32 size; |
| 16207 | u32 pos; |
| 16208 | u32 addr; |
| 16209 | u32 surface; |
| 16210 | u32 tile_offset; |
| 16211 | } plane[I915_MAX_PIPES]; |
| 16212 | |
| 16213 | struct intel_transcoder_error_state { |
| 16214 | bool power_domain_on; |
| 16215 | enum transcoder cpu_transcoder; |
| 16216 | |
| 16217 | u32 conf; |
| 16218 | |
| 16219 | u32 htotal; |
| 16220 | u32 hblank; |
| 16221 | u32 hsync; |
| 16222 | u32 vtotal; |
| 16223 | u32 vblank; |
| 16224 | u32 vsync; |
| 16225 | } transcoder[4]; |
| 16226 | }; |
| 16227 | |
| 16228 | struct intel_display_error_state * |
| 16229 | intel_display_capture_error_state(struct drm_device *dev) |
| 16230 | { |
| 16231 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 16232 | struct intel_display_error_state *error; |
| 16233 | int transcoders[] = { |
| 16234 | TRANSCODER_A, |
| 16235 | TRANSCODER_B, |
| 16236 | TRANSCODER_C, |
| 16237 | TRANSCODER_EDP, |
| 16238 | }; |
| 16239 | int i; |
| 16240 | |
| 16241 | if (INTEL_INFO(dev)->num_pipes == 0) |
| 16242 | return NULL; |
| 16243 | |
| 16244 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
| 16245 | if (error == NULL) |
| 16246 | return NULL; |
| 16247 | |
| 16248 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
| 16249 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
| 16250 | |
| 16251 | for_each_pipe(dev_priv, i) { |
| 16252 | error->pipe[i].power_domain_on = |
| 16253 | __intel_display_power_is_enabled(dev_priv, |
| 16254 | POWER_DOMAIN_PIPE(i)); |
| 16255 | if (!error->pipe[i].power_domain_on) |
| 16256 | continue; |
| 16257 | |
| 16258 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
| 16259 | error->cursor[i].position = I915_READ(CURPOS(i)); |
| 16260 | error->cursor[i].base = I915_READ(CURBASE(i)); |
| 16261 | |
| 16262 | error->plane[i].control = I915_READ(DSPCNTR(i)); |
| 16263 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); |
| 16264 | if (INTEL_INFO(dev)->gen <= 3) { |
| 16265 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
| 16266 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
| 16267 | } |
| 16268 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
| 16269 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
| 16270 | if (INTEL_INFO(dev)->gen >= 4) { |
| 16271 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
| 16272 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); |
| 16273 | } |
| 16274 | |
| 16275 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
| 16276 | |
| 16277 | if (HAS_GMCH_DISPLAY(dev)) |
| 16278 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
| 16279 | } |
| 16280 | |
| 16281 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; |
| 16282 | if (HAS_DDI(dev_priv->dev)) |
| 16283 | error->num_transcoders++; /* Account for eDP. */ |
| 16284 | |
| 16285 | for (i = 0; i < error->num_transcoders; i++) { |
| 16286 | enum transcoder cpu_transcoder = transcoders[i]; |
| 16287 | |
| 16288 | error->transcoder[i].power_domain_on = |
| 16289 | __intel_display_power_is_enabled(dev_priv, |
| 16290 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
| 16291 | if (!error->transcoder[i].power_domain_on) |
| 16292 | continue; |
| 16293 | |
| 16294 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
| 16295 | |
| 16296 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); |
| 16297 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); |
| 16298 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); |
| 16299 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); |
| 16300 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); |
| 16301 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); |
| 16302 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); |
| 16303 | } |
| 16304 | |
| 16305 | return error; |
| 16306 | } |
| 16307 | |
| 16308 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
| 16309 | |
| 16310 | void |
| 16311 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
| 16312 | struct drm_device *dev, |
| 16313 | struct intel_display_error_state *error) |
| 16314 | { |
| 16315 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 16316 | int i; |
| 16317 | |
| 16318 | if (!error) |
| 16319 | return; |
| 16320 | |
| 16321 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
| 16322 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
| 16323 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
| 16324 | error->power_well_driver); |
| 16325 | for_each_pipe(dev_priv, i) { |
| 16326 | err_printf(m, "Pipe [%d]:\n", i); |
| 16327 | err_printf(m, " Power: %s\n", |
| 16328 | error->pipe[i].power_domain_on ? "on" : "off"); |
| 16329 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
| 16330 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
| 16331 | |
| 16332 | err_printf(m, "Plane [%d]:\n", i); |
| 16333 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); |
| 16334 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); |
| 16335 | if (INTEL_INFO(dev)->gen <= 3) { |
| 16336 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
| 16337 | err_printf(m, " POS: %08x\n", error->plane[i].pos); |
| 16338 | } |
| 16339 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
| 16340 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
| 16341 | if (INTEL_INFO(dev)->gen >= 4) { |
| 16342 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
| 16343 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); |
| 16344 | } |
| 16345 | |
| 16346 | err_printf(m, "Cursor [%d]:\n", i); |
| 16347 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); |
| 16348 | err_printf(m, " POS: %08x\n", error->cursor[i].position); |
| 16349 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); |
| 16350 | } |
| 16351 | |
| 16352 | for (i = 0; i < error->num_transcoders; i++) { |
| 16353 | err_printf(m, "CPU transcoder: %c\n", |
| 16354 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
| 16355 | err_printf(m, " Power: %s\n", |
| 16356 | error->transcoder[i].power_domain_on ? "on" : "off"); |
| 16357 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
| 16358 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); |
| 16359 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); |
| 16360 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); |
| 16361 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); |
| 16362 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); |
| 16363 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); |
| 16364 | } |
| 16365 | } |
| 16366 | |
| 16367 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file) |
| 16368 | { |
| 16369 | struct intel_crtc *crtc; |
| 16370 | |
| 16371 | for_each_intel_crtc(dev, crtc) { |
| 16372 | struct intel_unpin_work *work; |
| 16373 | |
| 16374 | spin_lock_irq(&dev->event_lock); |
| 16375 | |
| 16376 | work = crtc->unpin_work; |
| 16377 | |
| 16378 | if (work && work->event && |
| 16379 | work->event->base.file_priv == file) { |
| 16380 | kfree(work->event); |
| 16381 | work->event = NULL; |
| 16382 | } |
| 16383 | |
| 16384 | spin_unlock_irq(&dev->event_lock); |
| 16385 | } |
| 16386 | } |