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Linux 3.17-rc1
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
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1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27#include <linux/dmi.h>
28#include <linux/module.h>
29#include <linux/input.h>
30#include <linux/i2c.h>
31#include <linux/kernel.h>
32#include <linux/slab.h>
33#include <linux/vgaarb.h>
34#include <drm/drm_edid.h>
35#include <drm/drmP.h>
36#include "intel_drv.h"
37#include <drm/i915_drm.h>
38#include "i915_drv.h"
39#include "i915_trace.h"
40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
42#include <drm/drm_plane_helper.h>
43#include <drm/drm_rect.h>
44#include <linux/dma_remapping.h>
45
46/* Primary plane formats supported by all gen */
47#define COMMON_PRIMARY_FORMATS \
48 DRM_FORMAT_C8, \
49 DRM_FORMAT_RGB565, \
50 DRM_FORMAT_XRGB8888, \
51 DRM_FORMAT_ARGB8888
52
53/* Primary plane formats for gen <= 3 */
54static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_ARGB1555,
58};
59
60/* Primary plane formats for gen >= 4 */
61static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
69};
70
71/* Cursor formats */
72static const uint32_t intel_cursor_formats[] = {
73 DRM_FORMAT_ARGB8888,
74};
75
76#define DIV_ROUND_CLOSEST_ULL(ll, d) \
77({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
78
79static void intel_increase_pllclock(struct drm_device *dev,
80 enum pipe pipe);
81static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
82
83static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
84 struct intel_crtc_config *pipe_config);
85static void ironlake_pch_clock_get(struct intel_crtc *crtc,
86 struct intel_crtc_config *pipe_config);
87
88static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
89 int x, int y, struct drm_framebuffer *old_fb);
90static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
94static void intel_dp_set_m_n(struct intel_crtc *crtc);
95static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
96static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
97static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
98 struct intel_link_m_n *m_n);
99static void ironlake_set_pipeconf(struct drm_crtc *crtc);
100static void haswell_set_pipeconf(struct drm_crtc *crtc);
101static void intel_set_pipe_csc(struct drm_crtc *crtc);
102static void vlv_prepare_pll(struct intel_crtc *crtc);
103
104static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
105{
106 if (!connector->mst_port)
107 return connector->encoder;
108 else
109 return &connector->mst_port->mst_encoders[pipe]->base;
110}
111
112typedef struct {
113 int min, max;
114} intel_range_t;
115
116typedef struct {
117 int dot_limit;
118 int p2_slow, p2_fast;
119} intel_p2_t;
120
121typedef struct intel_limit intel_limit_t;
122struct intel_limit {
123 intel_range_t dot, vco, n, m, m1, m2, p, p1;
124 intel_p2_t p2;
125};
126
127int
128intel_pch_rawclk(struct drm_device *dev)
129{
130 struct drm_i915_private *dev_priv = dev->dev_private;
131
132 WARN_ON(!HAS_PCH_SPLIT(dev));
133
134 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
135}
136
137static inline u32 /* units of 100MHz */
138intel_fdi_link_freq(struct drm_device *dev)
139{
140 if (IS_GEN5(dev)) {
141 struct drm_i915_private *dev_priv = dev->dev_private;
142 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
143 } else
144 return 27;
145}
146
147static const intel_limit_t intel_limits_i8xx_dac = {
148 .dot = { .min = 25000, .max = 350000 },
149 .vco = { .min = 908000, .max = 1512000 },
150 .n = { .min = 2, .max = 16 },
151 .m = { .min = 96, .max = 140 },
152 .m1 = { .min = 18, .max = 26 },
153 .m2 = { .min = 6, .max = 16 },
154 .p = { .min = 4, .max = 128 },
155 .p1 = { .min = 2, .max = 33 },
156 .p2 = { .dot_limit = 165000,
157 .p2_slow = 4, .p2_fast = 2 },
158};
159
160static const intel_limit_t intel_limits_i8xx_dvo = {
161 .dot = { .min = 25000, .max = 350000 },
162 .vco = { .min = 908000, .max = 1512000 },
163 .n = { .min = 2, .max = 16 },
164 .m = { .min = 96, .max = 140 },
165 .m1 = { .min = 18, .max = 26 },
166 .m2 = { .min = 6, .max = 16 },
167 .p = { .min = 4, .max = 128 },
168 .p1 = { .min = 2, .max = 33 },
169 .p2 = { .dot_limit = 165000,
170 .p2_slow = 4, .p2_fast = 4 },
171};
172
173static const intel_limit_t intel_limits_i8xx_lvds = {
174 .dot = { .min = 25000, .max = 350000 },
175 .vco = { .min = 908000, .max = 1512000 },
176 .n = { .min = 2, .max = 16 },
177 .m = { .min = 96, .max = 140 },
178 .m1 = { .min = 18, .max = 26 },
179 .m2 = { .min = 6, .max = 16 },
180 .p = { .min = 4, .max = 128 },
181 .p1 = { .min = 1, .max = 6 },
182 .p2 = { .dot_limit = 165000,
183 .p2_slow = 14, .p2_fast = 7 },
184};
185
186static const intel_limit_t intel_limits_i9xx_sdvo = {
187 .dot = { .min = 20000, .max = 400000 },
188 .vco = { .min = 1400000, .max = 2800000 },
189 .n = { .min = 1, .max = 6 },
190 .m = { .min = 70, .max = 120 },
191 .m1 = { .min = 8, .max = 18 },
192 .m2 = { .min = 3, .max = 7 },
193 .p = { .min = 5, .max = 80 },
194 .p1 = { .min = 1, .max = 8 },
195 .p2 = { .dot_limit = 200000,
196 .p2_slow = 10, .p2_fast = 5 },
197};
198
199static const intel_limit_t intel_limits_i9xx_lvds = {
200 .dot = { .min = 20000, .max = 400000 },
201 .vco = { .min = 1400000, .max = 2800000 },
202 .n = { .min = 1, .max = 6 },
203 .m = { .min = 70, .max = 120 },
204 .m1 = { .min = 8, .max = 18 },
205 .m2 = { .min = 3, .max = 7 },
206 .p = { .min = 7, .max = 98 },
207 .p1 = { .min = 1, .max = 8 },
208 .p2 = { .dot_limit = 112000,
209 .p2_slow = 14, .p2_fast = 7 },
210};
211
212
213static const intel_limit_t intel_limits_g4x_sdvo = {
214 .dot = { .min = 25000, .max = 270000 },
215 .vco = { .min = 1750000, .max = 3500000},
216 .n = { .min = 1, .max = 4 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 17, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 10, .max = 30 },
221 .p1 = { .min = 1, .max = 3},
222 .p2 = { .dot_limit = 270000,
223 .p2_slow = 10,
224 .p2_fast = 10
225 },
226};
227
228static const intel_limit_t intel_limits_g4x_hdmi = {
229 .dot = { .min = 22000, .max = 400000 },
230 .vco = { .min = 1750000, .max = 3500000},
231 .n = { .min = 1, .max = 4 },
232 .m = { .min = 104, .max = 138 },
233 .m1 = { .min = 16, .max = 23 },
234 .m2 = { .min = 5, .max = 11 },
235 .p = { .min = 5, .max = 80 },
236 .p1 = { .min = 1, .max = 8},
237 .p2 = { .dot_limit = 165000,
238 .p2_slow = 10, .p2_fast = 5 },
239};
240
241static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
242 .dot = { .min = 20000, .max = 115000 },
243 .vco = { .min = 1750000, .max = 3500000 },
244 .n = { .min = 1, .max = 3 },
245 .m = { .min = 104, .max = 138 },
246 .m1 = { .min = 17, .max = 23 },
247 .m2 = { .min = 5, .max = 11 },
248 .p = { .min = 28, .max = 112 },
249 .p1 = { .min = 2, .max = 8 },
250 .p2 = { .dot_limit = 0,
251 .p2_slow = 14, .p2_fast = 14
252 },
253};
254
255static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
256 .dot = { .min = 80000, .max = 224000 },
257 .vco = { .min = 1750000, .max = 3500000 },
258 .n = { .min = 1, .max = 3 },
259 .m = { .min = 104, .max = 138 },
260 .m1 = { .min = 17, .max = 23 },
261 .m2 = { .min = 5, .max = 11 },
262 .p = { .min = 14, .max = 42 },
263 .p1 = { .min = 2, .max = 6 },
264 .p2 = { .dot_limit = 0,
265 .p2_slow = 7, .p2_fast = 7
266 },
267};
268
269static const intel_limit_t intel_limits_pineview_sdvo = {
270 .dot = { .min = 20000, .max = 400000},
271 .vco = { .min = 1700000, .max = 3500000 },
272 /* Pineview's Ncounter is a ring counter */
273 .n = { .min = 3, .max = 6 },
274 .m = { .min = 2, .max = 256 },
275 /* Pineview only has one combined m divider, which we treat as m2. */
276 .m1 = { .min = 0, .max = 0 },
277 .m2 = { .min = 0, .max = 254 },
278 .p = { .min = 5, .max = 80 },
279 .p1 = { .min = 1, .max = 8 },
280 .p2 = { .dot_limit = 200000,
281 .p2_slow = 10, .p2_fast = 5 },
282};
283
284static const intel_limit_t intel_limits_pineview_lvds = {
285 .dot = { .min = 20000, .max = 400000 },
286 .vco = { .min = 1700000, .max = 3500000 },
287 .n = { .min = 3, .max = 6 },
288 .m = { .min = 2, .max = 256 },
289 .m1 = { .min = 0, .max = 0 },
290 .m2 = { .min = 0, .max = 254 },
291 .p = { .min = 7, .max = 112 },
292 .p1 = { .min = 1, .max = 8 },
293 .p2 = { .dot_limit = 112000,
294 .p2_slow = 14, .p2_fast = 14 },
295};
296
297/* Ironlake / Sandybridge
298 *
299 * We calculate clock using (register_value + 2) for N/M1/M2, so here
300 * the range value for them is (actual_value - 2).
301 */
302static const intel_limit_t intel_limits_ironlake_dac = {
303 .dot = { .min = 25000, .max = 350000 },
304 .vco = { .min = 1760000, .max = 3510000 },
305 .n = { .min = 1, .max = 5 },
306 .m = { .min = 79, .max = 127 },
307 .m1 = { .min = 12, .max = 22 },
308 .m2 = { .min = 5, .max = 9 },
309 .p = { .min = 5, .max = 80 },
310 .p1 = { .min = 1, .max = 8 },
311 .p2 = { .dot_limit = 225000,
312 .p2_slow = 10, .p2_fast = 5 },
313};
314
315static const intel_limit_t intel_limits_ironlake_single_lvds = {
316 .dot = { .min = 25000, .max = 350000 },
317 .vco = { .min = 1760000, .max = 3510000 },
318 .n = { .min = 1, .max = 3 },
319 .m = { .min = 79, .max = 118 },
320 .m1 = { .min = 12, .max = 22 },
321 .m2 = { .min = 5, .max = 9 },
322 .p = { .min = 28, .max = 112 },
323 .p1 = { .min = 2, .max = 8 },
324 .p2 = { .dot_limit = 225000,
325 .p2_slow = 14, .p2_fast = 14 },
326};
327
328static const intel_limit_t intel_limits_ironlake_dual_lvds = {
329 .dot = { .min = 25000, .max = 350000 },
330 .vco = { .min = 1760000, .max = 3510000 },
331 .n = { .min = 1, .max = 3 },
332 .m = { .min = 79, .max = 127 },
333 .m1 = { .min = 12, .max = 22 },
334 .m2 = { .min = 5, .max = 9 },
335 .p = { .min = 14, .max = 56 },
336 .p1 = { .min = 2, .max = 8 },
337 .p2 = { .dot_limit = 225000,
338 .p2_slow = 7, .p2_fast = 7 },
339};
340
341/* LVDS 100mhz refclk limits. */
342static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
343 .dot = { .min = 25000, .max = 350000 },
344 .vco = { .min = 1760000, .max = 3510000 },
345 .n = { .min = 1, .max = 2 },
346 .m = { .min = 79, .max = 126 },
347 .m1 = { .min = 12, .max = 22 },
348 .m2 = { .min = 5, .max = 9 },
349 .p = { .min = 28, .max = 112 },
350 .p1 = { .min = 2, .max = 8 },
351 .p2 = { .dot_limit = 225000,
352 .p2_slow = 14, .p2_fast = 14 },
353};
354
355static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
356 .dot = { .min = 25000, .max = 350000 },
357 .vco = { .min = 1760000, .max = 3510000 },
358 .n = { .min = 1, .max = 3 },
359 .m = { .min = 79, .max = 126 },
360 .m1 = { .min = 12, .max = 22 },
361 .m2 = { .min = 5, .max = 9 },
362 .p = { .min = 14, .max = 42 },
363 .p1 = { .min = 2, .max = 6 },
364 .p2 = { .dot_limit = 225000,
365 .p2_slow = 7, .p2_fast = 7 },
366};
367
368static const intel_limit_t intel_limits_vlv = {
369 /*
370 * These are the data rate limits (measured in fast clocks)
371 * since those are the strictest limits we have. The fast
372 * clock and actual rate limits are more relaxed, so checking
373 * them would make no difference.
374 */
375 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
376 .vco = { .min = 4000000, .max = 6000000 },
377 .n = { .min = 1, .max = 7 },
378 .m1 = { .min = 2, .max = 3 },
379 .m2 = { .min = 11, .max = 156 },
380 .p1 = { .min = 2, .max = 3 },
381 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
382};
383
384static const intel_limit_t intel_limits_chv = {
385 /*
386 * These are the data rate limits (measured in fast clocks)
387 * since those are the strictest limits we have. The fast
388 * clock and actual rate limits are more relaxed, so checking
389 * them would make no difference.
390 */
391 .dot = { .min = 25000 * 5, .max = 540000 * 5},
392 .vco = { .min = 4860000, .max = 6700000 },
393 .n = { .min = 1, .max = 1 },
394 .m1 = { .min = 2, .max = 2 },
395 .m2 = { .min = 24 << 22, .max = 175 << 22 },
396 .p1 = { .min = 2, .max = 4 },
397 .p2 = { .p2_slow = 1, .p2_fast = 14 },
398};
399
400static void vlv_clock(int refclk, intel_clock_t *clock)
401{
402 clock->m = clock->m1 * clock->m2;
403 clock->p = clock->p1 * clock->p2;
404 if (WARN_ON(clock->n == 0 || clock->p == 0))
405 return;
406 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
407 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
408}
409
410/**
411 * Returns whether any output on the specified pipe is of the specified type
412 */
413static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
414{
415 struct drm_device *dev = crtc->dev;
416 struct intel_encoder *encoder;
417
418 for_each_encoder_on_crtc(dev, crtc, encoder)
419 if (encoder->type == type)
420 return true;
421
422 return false;
423}
424
425static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
426 int refclk)
427{
428 struct drm_device *dev = crtc->dev;
429 const intel_limit_t *limit;
430
431 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
432 if (intel_is_dual_link_lvds(dev)) {
433 if (refclk == 100000)
434 limit = &intel_limits_ironlake_dual_lvds_100m;
435 else
436 limit = &intel_limits_ironlake_dual_lvds;
437 } else {
438 if (refclk == 100000)
439 limit = &intel_limits_ironlake_single_lvds_100m;
440 else
441 limit = &intel_limits_ironlake_single_lvds;
442 }
443 } else
444 limit = &intel_limits_ironlake_dac;
445
446 return limit;
447}
448
449static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
450{
451 struct drm_device *dev = crtc->dev;
452 const intel_limit_t *limit;
453
454 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
455 if (intel_is_dual_link_lvds(dev))
456 limit = &intel_limits_g4x_dual_channel_lvds;
457 else
458 limit = &intel_limits_g4x_single_channel_lvds;
459 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
460 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
461 limit = &intel_limits_g4x_hdmi;
462 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
463 limit = &intel_limits_g4x_sdvo;
464 } else /* The option is for other outputs */
465 limit = &intel_limits_i9xx_sdvo;
466
467 return limit;
468}
469
470static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
471{
472 struct drm_device *dev = crtc->dev;
473 const intel_limit_t *limit;
474
475 if (HAS_PCH_SPLIT(dev))
476 limit = intel_ironlake_limit(crtc, refclk);
477 else if (IS_G4X(dev)) {
478 limit = intel_g4x_limit(crtc);
479 } else if (IS_PINEVIEW(dev)) {
480 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
481 limit = &intel_limits_pineview_lvds;
482 else
483 limit = &intel_limits_pineview_sdvo;
484 } else if (IS_CHERRYVIEW(dev)) {
485 limit = &intel_limits_chv;
486 } else if (IS_VALLEYVIEW(dev)) {
487 limit = &intel_limits_vlv;
488 } else if (!IS_GEN2(dev)) {
489 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
490 limit = &intel_limits_i9xx_lvds;
491 else
492 limit = &intel_limits_i9xx_sdvo;
493 } else {
494 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
495 limit = &intel_limits_i8xx_lvds;
496 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
497 limit = &intel_limits_i8xx_dvo;
498 else
499 limit = &intel_limits_i8xx_dac;
500 }
501 return limit;
502}
503
504/* m1 is reserved as 0 in Pineview, n is a ring counter */
505static void pineview_clock(int refclk, intel_clock_t *clock)
506{
507 clock->m = clock->m2 + 2;
508 clock->p = clock->p1 * clock->p2;
509 if (WARN_ON(clock->n == 0 || clock->p == 0))
510 return;
511 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
512 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
513}
514
515static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
516{
517 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
518}
519
520static void i9xx_clock(int refclk, intel_clock_t *clock)
521{
522 clock->m = i9xx_dpll_compute_m(clock);
523 clock->p = clock->p1 * clock->p2;
524 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
525 return;
526 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
527 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
528}
529
530static void chv_clock(int refclk, intel_clock_t *clock)
531{
532 clock->m = clock->m1 * clock->m2;
533 clock->p = clock->p1 * clock->p2;
534 if (WARN_ON(clock->n == 0 || clock->p == 0))
535 return;
536 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
537 clock->n << 22);
538 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
539}
540
541#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
542/**
543 * Returns whether the given set of divisors are valid for a given refclk with
544 * the given connectors.
545 */
546
547static bool intel_PLL_is_valid(struct drm_device *dev,
548 const intel_limit_t *limit,
549 const intel_clock_t *clock)
550{
551 if (clock->n < limit->n.min || limit->n.max < clock->n)
552 INTELPllInvalid("n out of range\n");
553 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
554 INTELPllInvalid("p1 out of range\n");
555 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
556 INTELPllInvalid("m2 out of range\n");
557 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
558 INTELPllInvalid("m1 out of range\n");
559
560 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
561 if (clock->m1 <= clock->m2)
562 INTELPllInvalid("m1 <= m2\n");
563
564 if (!IS_VALLEYVIEW(dev)) {
565 if (clock->p < limit->p.min || limit->p.max < clock->p)
566 INTELPllInvalid("p out of range\n");
567 if (clock->m < limit->m.min || limit->m.max < clock->m)
568 INTELPllInvalid("m out of range\n");
569 }
570
571 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
572 INTELPllInvalid("vco out of range\n");
573 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
574 * connector, etc., rather than just a single range.
575 */
576 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
577 INTELPllInvalid("dot out of range\n");
578
579 return true;
580}
581
582static bool
583i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
584 int target, int refclk, intel_clock_t *match_clock,
585 intel_clock_t *best_clock)
586{
587 struct drm_device *dev = crtc->dev;
588 intel_clock_t clock;
589 int err = target;
590
591 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
592 /*
593 * For LVDS just rely on its current settings for dual-channel.
594 * We haven't figured out how to reliably set up different
595 * single/dual channel state, if we even can.
596 */
597 if (intel_is_dual_link_lvds(dev))
598 clock.p2 = limit->p2.p2_fast;
599 else
600 clock.p2 = limit->p2.p2_slow;
601 } else {
602 if (target < limit->p2.dot_limit)
603 clock.p2 = limit->p2.p2_slow;
604 else
605 clock.p2 = limit->p2.p2_fast;
606 }
607
608 memset(best_clock, 0, sizeof(*best_clock));
609
610 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
611 clock.m1++) {
612 for (clock.m2 = limit->m2.min;
613 clock.m2 <= limit->m2.max; clock.m2++) {
614 if (clock.m2 >= clock.m1)
615 break;
616 for (clock.n = limit->n.min;
617 clock.n <= limit->n.max; clock.n++) {
618 for (clock.p1 = limit->p1.min;
619 clock.p1 <= limit->p1.max; clock.p1++) {
620 int this_err;
621
622 i9xx_clock(refclk, &clock);
623 if (!intel_PLL_is_valid(dev, limit,
624 &clock))
625 continue;
626 if (match_clock &&
627 clock.p != match_clock->p)
628 continue;
629
630 this_err = abs(clock.dot - target);
631 if (this_err < err) {
632 *best_clock = clock;
633 err = this_err;
634 }
635 }
636 }
637 }
638 }
639
640 return (err != target);
641}
642
643static bool
644pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
645 int target, int refclk, intel_clock_t *match_clock,
646 intel_clock_t *best_clock)
647{
648 struct drm_device *dev = crtc->dev;
649 intel_clock_t clock;
650 int err = target;
651
652 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
653 /*
654 * For LVDS just rely on its current settings for dual-channel.
655 * We haven't figured out how to reliably set up different
656 * single/dual channel state, if we even can.
657 */
658 if (intel_is_dual_link_lvds(dev))
659 clock.p2 = limit->p2.p2_fast;
660 else
661 clock.p2 = limit->p2.p2_slow;
662 } else {
663 if (target < limit->p2.dot_limit)
664 clock.p2 = limit->p2.p2_slow;
665 else
666 clock.p2 = limit->p2.p2_fast;
667 }
668
669 memset(best_clock, 0, sizeof(*best_clock));
670
671 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
672 clock.m1++) {
673 for (clock.m2 = limit->m2.min;
674 clock.m2 <= limit->m2.max; clock.m2++) {
675 for (clock.n = limit->n.min;
676 clock.n <= limit->n.max; clock.n++) {
677 for (clock.p1 = limit->p1.min;
678 clock.p1 <= limit->p1.max; clock.p1++) {
679 int this_err;
680
681 pineview_clock(refclk, &clock);
682 if (!intel_PLL_is_valid(dev, limit,
683 &clock))
684 continue;
685 if (match_clock &&
686 clock.p != match_clock->p)
687 continue;
688
689 this_err = abs(clock.dot - target);
690 if (this_err < err) {
691 *best_clock = clock;
692 err = this_err;
693 }
694 }
695 }
696 }
697 }
698
699 return (err != target);
700}
701
702static bool
703g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
704 int target, int refclk, intel_clock_t *match_clock,
705 intel_clock_t *best_clock)
706{
707 struct drm_device *dev = crtc->dev;
708 intel_clock_t clock;
709 int max_n;
710 bool found;
711 /* approximately equals target * 0.00585 */
712 int err_most = (target >> 8) + (target >> 9);
713 found = false;
714
715 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
716 if (intel_is_dual_link_lvds(dev))
717 clock.p2 = limit->p2.p2_fast;
718 else
719 clock.p2 = limit->p2.p2_slow;
720 } else {
721 if (target < limit->p2.dot_limit)
722 clock.p2 = limit->p2.p2_slow;
723 else
724 clock.p2 = limit->p2.p2_fast;
725 }
726
727 memset(best_clock, 0, sizeof(*best_clock));
728 max_n = limit->n.max;
729 /* based on hardware requirement, prefer smaller n to precision */
730 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
731 /* based on hardware requirement, prefere larger m1,m2 */
732 for (clock.m1 = limit->m1.max;
733 clock.m1 >= limit->m1.min; clock.m1--) {
734 for (clock.m2 = limit->m2.max;
735 clock.m2 >= limit->m2.min; clock.m2--) {
736 for (clock.p1 = limit->p1.max;
737 clock.p1 >= limit->p1.min; clock.p1--) {
738 int this_err;
739
740 i9xx_clock(refclk, &clock);
741 if (!intel_PLL_is_valid(dev, limit,
742 &clock))
743 continue;
744
745 this_err = abs(clock.dot - target);
746 if (this_err < err_most) {
747 *best_clock = clock;
748 err_most = this_err;
749 max_n = clock.n;
750 found = true;
751 }
752 }
753 }
754 }
755 }
756 return found;
757}
758
759static bool
760vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
761 int target, int refclk, intel_clock_t *match_clock,
762 intel_clock_t *best_clock)
763{
764 struct drm_device *dev = crtc->dev;
765 intel_clock_t clock;
766 unsigned int bestppm = 1000000;
767 /* min update 19.2 MHz */
768 int max_n = min(limit->n.max, refclk / 19200);
769 bool found = false;
770
771 target *= 5; /* fast clock */
772
773 memset(best_clock, 0, sizeof(*best_clock));
774
775 /* based on hardware requirement, prefer smaller n to precision */
776 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
777 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
778 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
779 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
780 clock.p = clock.p1 * clock.p2;
781 /* based on hardware requirement, prefer bigger m1,m2 values */
782 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
783 unsigned int ppm, diff;
784
785 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
786 refclk * clock.m1);
787
788 vlv_clock(refclk, &clock);
789
790 if (!intel_PLL_is_valid(dev, limit,
791 &clock))
792 continue;
793
794 diff = abs(clock.dot - target);
795 ppm = div_u64(1000000ULL * diff, target);
796
797 if (ppm < 100 && clock.p > best_clock->p) {
798 bestppm = 0;
799 *best_clock = clock;
800 found = true;
801 }
802
803 if (bestppm >= 10 && ppm < bestppm - 10) {
804 bestppm = ppm;
805 *best_clock = clock;
806 found = true;
807 }
808 }
809 }
810 }
811 }
812
813 return found;
814}
815
816static bool
817chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
818 int target, int refclk, intel_clock_t *match_clock,
819 intel_clock_t *best_clock)
820{
821 struct drm_device *dev = crtc->dev;
822 intel_clock_t clock;
823 uint64_t m2;
824 int found = false;
825
826 memset(best_clock, 0, sizeof(*best_clock));
827
828 /*
829 * Based on hardware doc, the n always set to 1, and m1 always
830 * set to 2. If requires to support 200Mhz refclk, we need to
831 * revisit this because n may not 1 anymore.
832 */
833 clock.n = 1, clock.m1 = 2;
834 target *= 5; /* fast clock */
835
836 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
837 for (clock.p2 = limit->p2.p2_fast;
838 clock.p2 >= limit->p2.p2_slow;
839 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
840
841 clock.p = clock.p1 * clock.p2;
842
843 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
844 clock.n) << 22, refclk * clock.m1);
845
846 if (m2 > INT_MAX/clock.m1)
847 continue;
848
849 clock.m2 = m2;
850
851 chv_clock(refclk, &clock);
852
853 if (!intel_PLL_is_valid(dev, limit, &clock))
854 continue;
855
856 /* based on hardware requirement, prefer bigger p
857 */
858 if (clock.p > best_clock->p) {
859 *best_clock = clock;
860 found = true;
861 }
862 }
863 }
864
865 return found;
866}
867
868bool intel_crtc_active(struct drm_crtc *crtc)
869{
870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
871
872 /* Be paranoid as we can arrive here with only partial
873 * state retrieved from the hardware during setup.
874 *
875 * We can ditch the adjusted_mode.crtc_clock check as soon
876 * as Haswell has gained clock readout/fastboot support.
877 *
878 * We can ditch the crtc->primary->fb check as soon as we can
879 * properly reconstruct framebuffers.
880 */
881 return intel_crtc->active && crtc->primary->fb &&
882 intel_crtc->config.adjusted_mode.crtc_clock;
883}
884
885enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
886 enum pipe pipe)
887{
888 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
890
891 return intel_crtc->config.cpu_transcoder;
892}
893
894static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
895{
896 struct drm_i915_private *dev_priv = dev->dev_private;
897 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
898
899 frame = I915_READ(frame_reg);
900
901 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
902 WARN(1, "vblank wait timed out\n");
903}
904
905/**
906 * intel_wait_for_vblank - wait for vblank on a given pipe
907 * @dev: drm device
908 * @pipe: pipe to wait for
909 *
910 * Wait for vblank to occur on a given pipe. Needed for various bits of
911 * mode setting code.
912 */
913void intel_wait_for_vblank(struct drm_device *dev, int pipe)
914{
915 struct drm_i915_private *dev_priv = dev->dev_private;
916 int pipestat_reg = PIPESTAT(pipe);
917
918 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
919 g4x_wait_for_vblank(dev, pipe);
920 return;
921 }
922
923 /* Clear existing vblank status. Note this will clear any other
924 * sticky status fields as well.
925 *
926 * This races with i915_driver_irq_handler() with the result
927 * that either function could miss a vblank event. Here it is not
928 * fatal, as we will either wait upon the next vblank interrupt or
929 * timeout. Generally speaking intel_wait_for_vblank() is only
930 * called during modeset at which time the GPU should be idle and
931 * should *not* be performing page flips and thus not waiting on
932 * vblanks...
933 * Currently, the result of us stealing a vblank from the irq
934 * handler is that a single frame will be skipped during swapbuffers.
935 */
936 I915_WRITE(pipestat_reg,
937 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
938
939 /* Wait for vblank interrupt bit to set */
940 if (wait_for(I915_READ(pipestat_reg) &
941 PIPE_VBLANK_INTERRUPT_STATUS,
942 50))
943 DRM_DEBUG_KMS("vblank wait timed out\n");
944}
945
946static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
947{
948 struct drm_i915_private *dev_priv = dev->dev_private;
949 u32 reg = PIPEDSL(pipe);
950 u32 line1, line2;
951 u32 line_mask;
952
953 if (IS_GEN2(dev))
954 line_mask = DSL_LINEMASK_GEN2;
955 else
956 line_mask = DSL_LINEMASK_GEN3;
957
958 line1 = I915_READ(reg) & line_mask;
959 mdelay(5);
960 line2 = I915_READ(reg) & line_mask;
961
962 return line1 == line2;
963}
964
965/*
966 * intel_wait_for_pipe_off - wait for pipe to turn off
967 * @dev: drm device
968 * @pipe: pipe to wait for
969 *
970 * After disabling a pipe, we can't wait for vblank in the usual way,
971 * spinning on the vblank interrupt status bit, since we won't actually
972 * see an interrupt when the pipe is disabled.
973 *
974 * On Gen4 and above:
975 * wait for the pipe register state bit to turn off
976 *
977 * Otherwise:
978 * wait for the display line value to settle (it usually
979 * ends up stopping at the start of the next frame).
980 *
981 */
982void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
983{
984 struct drm_i915_private *dev_priv = dev->dev_private;
985 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
986 pipe);
987
988 if (INTEL_INFO(dev)->gen >= 4) {
989 int reg = PIPECONF(cpu_transcoder);
990
991 /* Wait for the Pipe State to go off */
992 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
993 100))
994 WARN(1, "pipe_off wait timed out\n");
995 } else {
996 /* Wait for the display line to settle */
997 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
998 WARN(1, "pipe_off wait timed out\n");
999 }
1000}
1001
1002/*
1003 * ibx_digital_port_connected - is the specified port connected?
1004 * @dev_priv: i915 private structure
1005 * @port: the port to test
1006 *
1007 * Returns true if @port is connected, false otherwise.
1008 */
1009bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1010 struct intel_digital_port *port)
1011{
1012 u32 bit;
1013
1014 if (HAS_PCH_IBX(dev_priv->dev)) {
1015 switch (port->port) {
1016 case PORT_B:
1017 bit = SDE_PORTB_HOTPLUG;
1018 break;
1019 case PORT_C:
1020 bit = SDE_PORTC_HOTPLUG;
1021 break;
1022 case PORT_D:
1023 bit = SDE_PORTD_HOTPLUG;
1024 break;
1025 default:
1026 return true;
1027 }
1028 } else {
1029 switch (port->port) {
1030 case PORT_B:
1031 bit = SDE_PORTB_HOTPLUG_CPT;
1032 break;
1033 case PORT_C:
1034 bit = SDE_PORTC_HOTPLUG_CPT;
1035 break;
1036 case PORT_D:
1037 bit = SDE_PORTD_HOTPLUG_CPT;
1038 break;
1039 default:
1040 return true;
1041 }
1042 }
1043
1044 return I915_READ(SDEISR) & bit;
1045}
1046
1047static const char *state_string(bool enabled)
1048{
1049 return enabled ? "on" : "off";
1050}
1051
1052/* Only for pre-ILK configs */
1053void assert_pll(struct drm_i915_private *dev_priv,
1054 enum pipe pipe, bool state)
1055{
1056 int reg;
1057 u32 val;
1058 bool cur_state;
1059
1060 reg = DPLL(pipe);
1061 val = I915_READ(reg);
1062 cur_state = !!(val & DPLL_VCO_ENABLE);
1063 WARN(cur_state != state,
1064 "PLL state assertion failure (expected %s, current %s)\n",
1065 state_string(state), state_string(cur_state));
1066}
1067
1068/* XXX: the dsi pll is shared between MIPI DSI ports */
1069static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1070{
1071 u32 val;
1072 bool cur_state;
1073
1074 mutex_lock(&dev_priv->dpio_lock);
1075 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1076 mutex_unlock(&dev_priv->dpio_lock);
1077
1078 cur_state = val & DSI_PLL_VCO_EN;
1079 WARN(cur_state != state,
1080 "DSI PLL state assertion failure (expected %s, current %s)\n",
1081 state_string(state), state_string(cur_state));
1082}
1083#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1084#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1085
1086struct intel_shared_dpll *
1087intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1088{
1089 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1090
1091 if (crtc->config.shared_dpll < 0)
1092 return NULL;
1093
1094 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1095}
1096
1097/* For ILK+ */
1098void assert_shared_dpll(struct drm_i915_private *dev_priv,
1099 struct intel_shared_dpll *pll,
1100 bool state)
1101{
1102 bool cur_state;
1103 struct intel_dpll_hw_state hw_state;
1104
1105 if (WARN (!pll,
1106 "asserting DPLL %s with no DPLL\n", state_string(state)))
1107 return;
1108
1109 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1110 WARN(cur_state != state,
1111 "%s assertion failure (expected %s, current %s)\n",
1112 pll->name, state_string(state), state_string(cur_state));
1113}
1114
1115static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1116 enum pipe pipe, bool state)
1117{
1118 int reg;
1119 u32 val;
1120 bool cur_state;
1121 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1122 pipe);
1123
1124 if (HAS_DDI(dev_priv->dev)) {
1125 /* DDI does not have a specific FDI_TX register */
1126 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1129 } else {
1130 reg = FDI_TX_CTL(pipe);
1131 val = I915_READ(reg);
1132 cur_state = !!(val & FDI_TX_ENABLE);
1133 }
1134 WARN(cur_state != state,
1135 "FDI TX state assertion failure (expected %s, current %s)\n",
1136 state_string(state), state_string(cur_state));
1137}
1138#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1139#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1140
1141static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1142 enum pipe pipe, bool state)
1143{
1144 int reg;
1145 u32 val;
1146 bool cur_state;
1147
1148 reg = FDI_RX_CTL(pipe);
1149 val = I915_READ(reg);
1150 cur_state = !!(val & FDI_RX_ENABLE);
1151 WARN(cur_state != state,
1152 "FDI RX state assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
1154}
1155#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1156#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1157
1158static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1159 enum pipe pipe)
1160{
1161 int reg;
1162 u32 val;
1163
1164 /* ILK FDI PLL is always enabled */
1165 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1166 return;
1167
1168 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1169 if (HAS_DDI(dev_priv->dev))
1170 return;
1171
1172 reg = FDI_TX_CTL(pipe);
1173 val = I915_READ(reg);
1174 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175}
1176
1177void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1178 enum pipe pipe, bool state)
1179{
1180 int reg;
1181 u32 val;
1182 bool cur_state;
1183
1184 reg = FDI_RX_CTL(pipe);
1185 val = I915_READ(reg);
1186 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1187 WARN(cur_state != state,
1188 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1189 state_string(state), state_string(cur_state));
1190}
1191
1192static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1193 enum pipe pipe)
1194{
1195 int pp_reg, lvds_reg;
1196 u32 val;
1197 enum pipe panel_pipe = PIPE_A;
1198 bool locked = true;
1199
1200 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1201 pp_reg = PCH_PP_CONTROL;
1202 lvds_reg = PCH_LVDS;
1203 } else {
1204 pp_reg = PP_CONTROL;
1205 lvds_reg = LVDS;
1206 }
1207
1208 val = I915_READ(pp_reg);
1209 if (!(val & PANEL_POWER_ON) ||
1210 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1211 locked = false;
1212
1213 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1214 panel_pipe = PIPE_B;
1215
1216 WARN(panel_pipe == pipe && locked,
1217 "panel assertion failure, pipe %c regs locked\n",
1218 pipe_name(pipe));
1219}
1220
1221static void assert_cursor(struct drm_i915_private *dev_priv,
1222 enum pipe pipe, bool state)
1223{
1224 struct drm_device *dev = dev_priv->dev;
1225 bool cur_state;
1226
1227 if (IS_845G(dev) || IS_I865G(dev))
1228 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1229 else
1230 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1231
1232 WARN(cur_state != state,
1233 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1234 pipe_name(pipe), state_string(state), state_string(cur_state));
1235}
1236#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1237#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1238
1239void assert_pipe(struct drm_i915_private *dev_priv,
1240 enum pipe pipe, bool state)
1241{
1242 int reg;
1243 u32 val;
1244 bool cur_state;
1245 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1246 pipe);
1247
1248 /* if we need the pipe A quirk it must be always on */
1249 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1250 state = true;
1251
1252 if (!intel_display_power_enabled(dev_priv,
1253 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1254 cur_state = false;
1255 } else {
1256 reg = PIPECONF(cpu_transcoder);
1257 val = I915_READ(reg);
1258 cur_state = !!(val & PIPECONF_ENABLE);
1259 }
1260
1261 WARN(cur_state != state,
1262 "pipe %c assertion failure (expected %s, current %s)\n",
1263 pipe_name(pipe), state_string(state), state_string(cur_state));
1264}
1265
1266static void assert_plane(struct drm_i915_private *dev_priv,
1267 enum plane plane, bool state)
1268{
1269 int reg;
1270 u32 val;
1271 bool cur_state;
1272
1273 reg = DSPCNTR(plane);
1274 val = I915_READ(reg);
1275 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1276 WARN(cur_state != state,
1277 "plane %c assertion failure (expected %s, current %s)\n",
1278 plane_name(plane), state_string(state), state_string(cur_state));
1279}
1280
1281#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1282#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1283
1284static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1285 enum pipe pipe)
1286{
1287 struct drm_device *dev = dev_priv->dev;
1288 int reg, i;
1289 u32 val;
1290 int cur_pipe;
1291
1292 /* Primary planes are fixed to pipes on gen4+ */
1293 if (INTEL_INFO(dev)->gen >= 4) {
1294 reg = DSPCNTR(pipe);
1295 val = I915_READ(reg);
1296 WARN(val & DISPLAY_PLANE_ENABLE,
1297 "plane %c assertion failure, should be disabled but not\n",
1298 plane_name(pipe));
1299 return;
1300 }
1301
1302 /* Need to check both planes against the pipe */
1303 for_each_pipe(i) {
1304 reg = DSPCNTR(i);
1305 val = I915_READ(reg);
1306 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1307 DISPPLANE_SEL_PIPE_SHIFT;
1308 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1309 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1310 plane_name(i), pipe_name(pipe));
1311 }
1312}
1313
1314static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1315 enum pipe pipe)
1316{
1317 struct drm_device *dev = dev_priv->dev;
1318 int reg, sprite;
1319 u32 val;
1320
1321 if (IS_VALLEYVIEW(dev)) {
1322 for_each_sprite(pipe, sprite) {
1323 reg = SPCNTR(pipe, sprite);
1324 val = I915_READ(reg);
1325 WARN(val & SP_ENABLE,
1326 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1327 sprite_name(pipe, sprite), pipe_name(pipe));
1328 }
1329 } else if (INTEL_INFO(dev)->gen >= 7) {
1330 reg = SPRCTL(pipe);
1331 val = I915_READ(reg);
1332 WARN(val & SPRITE_ENABLE,
1333 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1334 plane_name(pipe), pipe_name(pipe));
1335 } else if (INTEL_INFO(dev)->gen >= 5) {
1336 reg = DVSCNTR(pipe);
1337 val = I915_READ(reg);
1338 WARN(val & DVS_ENABLE,
1339 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1340 plane_name(pipe), pipe_name(pipe));
1341 }
1342}
1343
1344static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1345{
1346 u32 val;
1347 bool enabled;
1348
1349 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1350
1351 val = I915_READ(PCH_DREF_CONTROL);
1352 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1353 DREF_SUPERSPREAD_SOURCE_MASK));
1354 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1355}
1356
1357static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1358 enum pipe pipe)
1359{
1360 int reg;
1361 u32 val;
1362 bool enabled;
1363
1364 reg = PCH_TRANSCONF(pipe);
1365 val = I915_READ(reg);
1366 enabled = !!(val & TRANS_ENABLE);
1367 WARN(enabled,
1368 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1369 pipe_name(pipe));
1370}
1371
1372static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1373 enum pipe pipe, u32 port_sel, u32 val)
1374{
1375 if ((val & DP_PORT_EN) == 0)
1376 return false;
1377
1378 if (HAS_PCH_CPT(dev_priv->dev)) {
1379 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1380 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1381 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1382 return false;
1383 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1384 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1385 return false;
1386 } else {
1387 if ((val & DP_PIPE_MASK) != (pipe << 30))
1388 return false;
1389 }
1390 return true;
1391}
1392
1393static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1394 enum pipe pipe, u32 val)
1395{
1396 if ((val & SDVO_ENABLE) == 0)
1397 return false;
1398
1399 if (HAS_PCH_CPT(dev_priv->dev)) {
1400 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1401 return false;
1402 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1403 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1404 return false;
1405 } else {
1406 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1407 return false;
1408 }
1409 return true;
1410}
1411
1412static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1413 enum pipe pipe, u32 val)
1414{
1415 if ((val & LVDS_PORT_EN) == 0)
1416 return false;
1417
1418 if (HAS_PCH_CPT(dev_priv->dev)) {
1419 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1420 return false;
1421 } else {
1422 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1423 return false;
1424 }
1425 return true;
1426}
1427
1428static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1429 enum pipe pipe, u32 val)
1430{
1431 if ((val & ADPA_DAC_ENABLE) == 0)
1432 return false;
1433 if (HAS_PCH_CPT(dev_priv->dev)) {
1434 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1435 return false;
1436 } else {
1437 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1438 return false;
1439 }
1440 return true;
1441}
1442
1443static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1444 enum pipe pipe, int reg, u32 port_sel)
1445{
1446 u32 val = I915_READ(reg);
1447 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1448 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1449 reg, pipe_name(pipe));
1450
1451 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1452 && (val & DP_PIPEB_SELECT),
1453 "IBX PCH dp port still using transcoder B\n");
1454}
1455
1456static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1457 enum pipe pipe, int reg)
1458{
1459 u32 val = I915_READ(reg);
1460 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1461 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1462 reg, pipe_name(pipe));
1463
1464 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1465 && (val & SDVO_PIPE_B_SELECT),
1466 "IBX PCH hdmi port still using transcoder B\n");
1467}
1468
1469static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1470 enum pipe pipe)
1471{
1472 int reg;
1473 u32 val;
1474
1475 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1476 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1477 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1478
1479 reg = PCH_ADPA;
1480 val = I915_READ(reg);
1481 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1482 "PCH VGA enabled on transcoder %c, should be disabled\n",
1483 pipe_name(pipe));
1484
1485 reg = PCH_LVDS;
1486 val = I915_READ(reg);
1487 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1488 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1489 pipe_name(pipe));
1490
1491 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1492 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1493 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1494}
1495
1496static void intel_init_dpio(struct drm_device *dev)
1497{
1498 struct drm_i915_private *dev_priv = dev->dev_private;
1499
1500 if (!IS_VALLEYVIEW(dev))
1501 return;
1502
1503 /*
1504 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1505 * CHV x1 PHY (DP/HDMI D)
1506 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1507 */
1508 if (IS_CHERRYVIEW(dev)) {
1509 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1510 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1511 } else {
1512 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1513 }
1514}
1515
1516static void intel_reset_dpio(struct drm_device *dev)
1517{
1518 struct drm_i915_private *dev_priv = dev->dev_private;
1519
1520 if (IS_CHERRYVIEW(dev)) {
1521 enum dpio_phy phy;
1522 u32 val;
1523
1524 for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
1525 /* Poll for phypwrgood signal */
1526 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
1527 PHY_POWERGOOD(phy), 1))
1528 DRM_ERROR("Display PHY %d is not power up\n", phy);
1529
1530 /*
1531 * Deassert common lane reset for PHY.
1532 *
1533 * This should only be done on init and resume from S3
1534 * with both PLLs disabled, or we risk losing DPIO and
1535 * PLL synchronization.
1536 */
1537 val = I915_READ(DISPLAY_PHY_CONTROL);
1538 I915_WRITE(DISPLAY_PHY_CONTROL,
1539 PHY_COM_LANE_RESET_DEASSERT(phy, val));
1540 }
1541 }
1542}
1543
1544static void vlv_enable_pll(struct intel_crtc *crtc)
1545{
1546 struct drm_device *dev = crtc->base.dev;
1547 struct drm_i915_private *dev_priv = dev->dev_private;
1548 int reg = DPLL(crtc->pipe);
1549 u32 dpll = crtc->config.dpll_hw_state.dpll;
1550
1551 assert_pipe_disabled(dev_priv, crtc->pipe);
1552
1553 /* No really, not for ILK+ */
1554 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1555
1556 /* PLL is protected by panel, make sure we can write it */
1557 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1558 assert_panel_unlocked(dev_priv, crtc->pipe);
1559
1560 I915_WRITE(reg, dpll);
1561 POSTING_READ(reg);
1562 udelay(150);
1563
1564 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1565 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1566
1567 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1568 POSTING_READ(DPLL_MD(crtc->pipe));
1569
1570 /* We do this three times for luck */
1571 I915_WRITE(reg, dpll);
1572 POSTING_READ(reg);
1573 udelay(150); /* wait for warmup */
1574 I915_WRITE(reg, dpll);
1575 POSTING_READ(reg);
1576 udelay(150); /* wait for warmup */
1577 I915_WRITE(reg, dpll);
1578 POSTING_READ(reg);
1579 udelay(150); /* wait for warmup */
1580}
1581
1582static void chv_enable_pll(struct intel_crtc *crtc)
1583{
1584 struct drm_device *dev = crtc->base.dev;
1585 struct drm_i915_private *dev_priv = dev->dev_private;
1586 int pipe = crtc->pipe;
1587 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1588 u32 tmp;
1589
1590 assert_pipe_disabled(dev_priv, crtc->pipe);
1591
1592 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1593
1594 mutex_lock(&dev_priv->dpio_lock);
1595
1596 /* Enable back the 10bit clock to display controller */
1597 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1598 tmp |= DPIO_DCLKP_EN;
1599 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1600
1601 /*
1602 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1603 */
1604 udelay(1);
1605
1606 /* Enable PLL */
1607 I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1608
1609 /* Check PLL is locked */
1610 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1611 DRM_ERROR("PLL %d failed to lock\n", pipe);
1612
1613 /* not sure when this should be written */
1614 I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1615 POSTING_READ(DPLL_MD(pipe));
1616
1617 mutex_unlock(&dev_priv->dpio_lock);
1618}
1619
1620static void i9xx_enable_pll(struct intel_crtc *crtc)
1621{
1622 struct drm_device *dev = crtc->base.dev;
1623 struct drm_i915_private *dev_priv = dev->dev_private;
1624 int reg = DPLL(crtc->pipe);
1625 u32 dpll = crtc->config.dpll_hw_state.dpll;
1626
1627 assert_pipe_disabled(dev_priv, crtc->pipe);
1628
1629 /* No really, not for ILK+ */
1630 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1631
1632 /* PLL is protected by panel, make sure we can write it */
1633 if (IS_MOBILE(dev) && !IS_I830(dev))
1634 assert_panel_unlocked(dev_priv, crtc->pipe);
1635
1636 I915_WRITE(reg, dpll);
1637
1638 /* Wait for the clocks to stabilize. */
1639 POSTING_READ(reg);
1640 udelay(150);
1641
1642 if (INTEL_INFO(dev)->gen >= 4) {
1643 I915_WRITE(DPLL_MD(crtc->pipe),
1644 crtc->config.dpll_hw_state.dpll_md);
1645 } else {
1646 /* The pixel multiplier can only be updated once the
1647 * DPLL is enabled and the clocks are stable.
1648 *
1649 * So write it again.
1650 */
1651 I915_WRITE(reg, dpll);
1652 }
1653
1654 /* We do this three times for luck */
1655 I915_WRITE(reg, dpll);
1656 POSTING_READ(reg);
1657 udelay(150); /* wait for warmup */
1658 I915_WRITE(reg, dpll);
1659 POSTING_READ(reg);
1660 udelay(150); /* wait for warmup */
1661 I915_WRITE(reg, dpll);
1662 POSTING_READ(reg);
1663 udelay(150); /* wait for warmup */
1664}
1665
1666/**
1667 * i9xx_disable_pll - disable a PLL
1668 * @dev_priv: i915 private structure
1669 * @pipe: pipe PLL to disable
1670 *
1671 * Disable the PLL for @pipe, making sure the pipe is off first.
1672 *
1673 * Note! This is for pre-ILK only.
1674 */
1675static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1676{
1677 /* Don't disable pipe A or pipe A PLLs if needed */
1678 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1679 return;
1680
1681 /* Make sure the pipe isn't still relying on us */
1682 assert_pipe_disabled(dev_priv, pipe);
1683
1684 I915_WRITE(DPLL(pipe), 0);
1685 POSTING_READ(DPLL(pipe));
1686}
1687
1688static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1689{
1690 u32 val = 0;
1691
1692 /* Make sure the pipe isn't still relying on us */
1693 assert_pipe_disabled(dev_priv, pipe);
1694
1695 /*
1696 * Leave integrated clock source and reference clock enabled for pipe B.
1697 * The latter is needed for VGA hotplug / manual detection.
1698 */
1699 if (pipe == PIPE_B)
1700 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1701 I915_WRITE(DPLL(pipe), val);
1702 POSTING_READ(DPLL(pipe));
1703
1704}
1705
1706static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1707{
1708 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1709 u32 val;
1710
1711 /* Make sure the pipe isn't still relying on us */
1712 assert_pipe_disabled(dev_priv, pipe);
1713
1714 /* Set PLL en = 0 */
1715 val = DPLL_SSC_REF_CLOCK_CHV;
1716 if (pipe != PIPE_A)
1717 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1718 I915_WRITE(DPLL(pipe), val);
1719 POSTING_READ(DPLL(pipe));
1720
1721 mutex_lock(&dev_priv->dpio_lock);
1722
1723 /* Disable 10bit clock to display controller */
1724 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1725 val &= ~DPIO_DCLKP_EN;
1726 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1727
1728 /* disable left/right clock distribution */
1729 if (pipe != PIPE_B) {
1730 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1731 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1732 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1733 } else {
1734 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1735 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1736 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1737 }
1738
1739 mutex_unlock(&dev_priv->dpio_lock);
1740}
1741
1742void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1743 struct intel_digital_port *dport)
1744{
1745 u32 port_mask;
1746 int dpll_reg;
1747
1748 switch (dport->port) {
1749 case PORT_B:
1750 port_mask = DPLL_PORTB_READY_MASK;
1751 dpll_reg = DPLL(0);
1752 break;
1753 case PORT_C:
1754 port_mask = DPLL_PORTC_READY_MASK;
1755 dpll_reg = DPLL(0);
1756 break;
1757 case PORT_D:
1758 port_mask = DPLL_PORTD_READY_MASK;
1759 dpll_reg = DPIO_PHY_STATUS;
1760 break;
1761 default:
1762 BUG();
1763 }
1764
1765 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1766 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1767 port_name(dport->port), I915_READ(dpll_reg));
1768}
1769
1770static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1771{
1772 struct drm_device *dev = crtc->base.dev;
1773 struct drm_i915_private *dev_priv = dev->dev_private;
1774 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1775
1776 if (WARN_ON(pll == NULL))
1777 return;
1778
1779 WARN_ON(!pll->refcount);
1780 if (pll->active == 0) {
1781 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1782 WARN_ON(pll->on);
1783 assert_shared_dpll_disabled(dev_priv, pll);
1784
1785 pll->mode_set(dev_priv, pll);
1786 }
1787}
1788
1789/**
1790 * intel_enable_shared_dpll - enable PCH PLL
1791 * @dev_priv: i915 private structure
1792 * @pipe: pipe PLL to enable
1793 *
1794 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1795 * drives the transcoder clock.
1796 */
1797static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1798{
1799 struct drm_device *dev = crtc->base.dev;
1800 struct drm_i915_private *dev_priv = dev->dev_private;
1801 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1802
1803 if (WARN_ON(pll == NULL))
1804 return;
1805
1806 if (WARN_ON(pll->refcount == 0))
1807 return;
1808
1809 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1810 pll->name, pll->active, pll->on,
1811 crtc->base.base.id);
1812
1813 if (pll->active++) {
1814 WARN_ON(!pll->on);
1815 assert_shared_dpll_enabled(dev_priv, pll);
1816 return;
1817 }
1818 WARN_ON(pll->on);
1819
1820 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1821
1822 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1823 pll->enable(dev_priv, pll);
1824 pll->on = true;
1825}
1826
1827void intel_disable_shared_dpll(struct intel_crtc *crtc)
1828{
1829 struct drm_device *dev = crtc->base.dev;
1830 struct drm_i915_private *dev_priv = dev->dev_private;
1831 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1832
1833 /* PCH only available on ILK+ */
1834 BUG_ON(INTEL_INFO(dev)->gen < 5);
1835 if (WARN_ON(pll == NULL))
1836 return;
1837
1838 if (WARN_ON(pll->refcount == 0))
1839 return;
1840
1841 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1842 pll->name, pll->active, pll->on,
1843 crtc->base.base.id);
1844
1845 if (WARN_ON(pll->active == 0)) {
1846 assert_shared_dpll_disabled(dev_priv, pll);
1847 return;
1848 }
1849
1850 assert_shared_dpll_enabled(dev_priv, pll);
1851 WARN_ON(!pll->on);
1852 if (--pll->active)
1853 return;
1854
1855 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1856 pll->disable(dev_priv, pll);
1857 pll->on = false;
1858
1859 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1860}
1861
1862static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1863 enum pipe pipe)
1864{
1865 struct drm_device *dev = dev_priv->dev;
1866 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1867 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1868 uint32_t reg, val, pipeconf_val;
1869
1870 /* PCH only available on ILK+ */
1871 BUG_ON(INTEL_INFO(dev)->gen < 5);
1872
1873 /* Make sure PCH DPLL is enabled */
1874 assert_shared_dpll_enabled(dev_priv,
1875 intel_crtc_to_shared_dpll(intel_crtc));
1876
1877 /* FDI must be feeding us bits for PCH ports */
1878 assert_fdi_tx_enabled(dev_priv, pipe);
1879 assert_fdi_rx_enabled(dev_priv, pipe);
1880
1881 if (HAS_PCH_CPT(dev)) {
1882 /* Workaround: Set the timing override bit before enabling the
1883 * pch transcoder. */
1884 reg = TRANS_CHICKEN2(pipe);
1885 val = I915_READ(reg);
1886 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1887 I915_WRITE(reg, val);
1888 }
1889
1890 reg = PCH_TRANSCONF(pipe);
1891 val = I915_READ(reg);
1892 pipeconf_val = I915_READ(PIPECONF(pipe));
1893
1894 if (HAS_PCH_IBX(dev_priv->dev)) {
1895 /*
1896 * make the BPC in transcoder be consistent with
1897 * that in pipeconf reg.
1898 */
1899 val &= ~PIPECONF_BPC_MASK;
1900 val |= pipeconf_val & PIPECONF_BPC_MASK;
1901 }
1902
1903 val &= ~TRANS_INTERLACE_MASK;
1904 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1905 if (HAS_PCH_IBX(dev_priv->dev) &&
1906 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1907 val |= TRANS_LEGACY_INTERLACED_ILK;
1908 else
1909 val |= TRANS_INTERLACED;
1910 else
1911 val |= TRANS_PROGRESSIVE;
1912
1913 I915_WRITE(reg, val | TRANS_ENABLE);
1914 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1915 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1916}
1917
1918static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1919 enum transcoder cpu_transcoder)
1920{
1921 u32 val, pipeconf_val;
1922
1923 /* PCH only available on ILK+ */
1924 BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1925
1926 /* FDI must be feeding us bits for PCH ports */
1927 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1928 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1929
1930 /* Workaround: set timing override bit. */
1931 val = I915_READ(_TRANSA_CHICKEN2);
1932 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1933 I915_WRITE(_TRANSA_CHICKEN2, val);
1934
1935 val = TRANS_ENABLE;
1936 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1937
1938 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1939 PIPECONF_INTERLACED_ILK)
1940 val |= TRANS_INTERLACED;
1941 else
1942 val |= TRANS_PROGRESSIVE;
1943
1944 I915_WRITE(LPT_TRANSCONF, val);
1945 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1946 DRM_ERROR("Failed to enable PCH transcoder\n");
1947}
1948
1949static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1950 enum pipe pipe)
1951{
1952 struct drm_device *dev = dev_priv->dev;
1953 uint32_t reg, val;
1954
1955 /* FDI relies on the transcoder */
1956 assert_fdi_tx_disabled(dev_priv, pipe);
1957 assert_fdi_rx_disabled(dev_priv, pipe);
1958
1959 /* Ports must be off as well */
1960 assert_pch_ports_disabled(dev_priv, pipe);
1961
1962 reg = PCH_TRANSCONF(pipe);
1963 val = I915_READ(reg);
1964 val &= ~TRANS_ENABLE;
1965 I915_WRITE(reg, val);
1966 /* wait for PCH transcoder off, transcoder state */
1967 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1968 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1969
1970 if (!HAS_PCH_IBX(dev)) {
1971 /* Workaround: Clear the timing override chicken bit again. */
1972 reg = TRANS_CHICKEN2(pipe);
1973 val = I915_READ(reg);
1974 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1975 I915_WRITE(reg, val);
1976 }
1977}
1978
1979static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1980{
1981 u32 val;
1982
1983 val = I915_READ(LPT_TRANSCONF);
1984 val &= ~TRANS_ENABLE;
1985 I915_WRITE(LPT_TRANSCONF, val);
1986 /* wait for PCH transcoder off, transcoder state */
1987 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1988 DRM_ERROR("Failed to disable PCH transcoder\n");
1989
1990 /* Workaround: clear timing override bit. */
1991 val = I915_READ(_TRANSA_CHICKEN2);
1992 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1993 I915_WRITE(_TRANSA_CHICKEN2, val);
1994}
1995
1996/**
1997 * intel_enable_pipe - enable a pipe, asserting requirements
1998 * @crtc: crtc responsible for the pipe
1999 *
2000 * Enable @crtc's pipe, making sure that various hardware specific requirements
2001 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2002 */
2003static void intel_enable_pipe(struct intel_crtc *crtc)
2004{
2005 struct drm_device *dev = crtc->base.dev;
2006 struct drm_i915_private *dev_priv = dev->dev_private;
2007 enum pipe pipe = crtc->pipe;
2008 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2009 pipe);
2010 enum pipe pch_transcoder;
2011 int reg;
2012 u32 val;
2013
2014 assert_planes_disabled(dev_priv, pipe);
2015 assert_cursor_disabled(dev_priv, pipe);
2016 assert_sprites_disabled(dev_priv, pipe);
2017
2018 if (HAS_PCH_LPT(dev_priv->dev))
2019 pch_transcoder = TRANSCODER_A;
2020 else
2021 pch_transcoder = pipe;
2022
2023 /*
2024 * A pipe without a PLL won't actually be able to drive bits from
2025 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2026 * need the check.
2027 */
2028 if (!HAS_PCH_SPLIT(dev_priv->dev))
2029 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
2030 assert_dsi_pll_enabled(dev_priv);
2031 else
2032 assert_pll_enabled(dev_priv, pipe);
2033 else {
2034 if (crtc->config.has_pch_encoder) {
2035 /* if driving the PCH, we need FDI enabled */
2036 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2037 assert_fdi_tx_pll_enabled(dev_priv,
2038 (enum pipe) cpu_transcoder);
2039 }
2040 /* FIXME: assert CPU port conditions for SNB+ */
2041 }
2042
2043 reg = PIPECONF(cpu_transcoder);
2044 val = I915_READ(reg);
2045 if (val & PIPECONF_ENABLE) {
2046 WARN_ON(!(pipe == PIPE_A &&
2047 dev_priv->quirks & QUIRK_PIPEA_FORCE));
2048 return;
2049 }
2050
2051 I915_WRITE(reg, val | PIPECONF_ENABLE);
2052 POSTING_READ(reg);
2053}
2054
2055/**
2056 * intel_disable_pipe - disable a pipe, asserting requirements
2057 * @dev_priv: i915 private structure
2058 * @pipe: pipe to disable
2059 *
2060 * Disable @pipe, making sure that various hardware specific requirements
2061 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2062 *
2063 * @pipe should be %PIPE_A or %PIPE_B.
2064 *
2065 * Will wait until the pipe has shut down before returning.
2066 */
2067static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2068 enum pipe pipe)
2069{
2070 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2071 pipe);
2072 int reg;
2073 u32 val;
2074
2075 /*
2076 * Make sure planes won't keep trying to pump pixels to us,
2077 * or we might hang the display.
2078 */
2079 assert_planes_disabled(dev_priv, pipe);
2080 assert_cursor_disabled(dev_priv, pipe);
2081 assert_sprites_disabled(dev_priv, pipe);
2082
2083 /* Don't disable pipe A or pipe A PLLs if needed */
2084 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2085 return;
2086
2087 reg = PIPECONF(cpu_transcoder);
2088 val = I915_READ(reg);
2089 if ((val & PIPECONF_ENABLE) == 0)
2090 return;
2091
2092 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
2093 intel_wait_for_pipe_off(dev_priv->dev, pipe);
2094}
2095
2096/*
2097 * Plane regs are double buffered, going from enabled->disabled needs a
2098 * trigger in order to latch. The display address reg provides this.
2099 */
2100void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2101 enum plane plane)
2102{
2103 struct drm_device *dev = dev_priv->dev;
2104 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2105
2106 I915_WRITE(reg, I915_READ(reg));
2107 POSTING_READ(reg);
2108}
2109
2110/**
2111 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2112 * @dev_priv: i915 private structure
2113 * @plane: plane to enable
2114 * @pipe: pipe being fed
2115 *
2116 * Enable @plane on @pipe, making sure that @pipe is running first.
2117 */
2118static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2119 enum plane plane, enum pipe pipe)
2120{
2121 struct drm_device *dev = dev_priv->dev;
2122 struct intel_crtc *intel_crtc =
2123 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2124 int reg;
2125 u32 val;
2126
2127 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2128 assert_pipe_enabled(dev_priv, pipe);
2129
2130 if (intel_crtc->primary_enabled)
2131 return;
2132
2133 intel_crtc->primary_enabled = true;
2134
2135 reg = DSPCNTR(plane);
2136 val = I915_READ(reg);
2137 WARN_ON(val & DISPLAY_PLANE_ENABLE);
2138
2139 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
2140 intel_flush_primary_plane(dev_priv, plane);
2141
2142 /*
2143 * BDW signals flip done immediately if the plane
2144 * is disabled, even if the plane enable is already
2145 * armed to occur at the next vblank :(
2146 */
2147 if (IS_BROADWELL(dev))
2148 intel_wait_for_vblank(dev, intel_crtc->pipe);
2149}
2150
2151/**
2152 * intel_disable_primary_hw_plane - disable the primary hardware plane
2153 * @dev_priv: i915 private structure
2154 * @plane: plane to disable
2155 * @pipe: pipe consuming the data
2156 *
2157 * Disable @plane; should be an independent operation.
2158 */
2159static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
2160 enum plane plane, enum pipe pipe)
2161{
2162 struct intel_crtc *intel_crtc =
2163 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2164 int reg;
2165 u32 val;
2166
2167 if (!intel_crtc->primary_enabled)
2168 return;
2169
2170 intel_crtc->primary_enabled = false;
2171
2172 reg = DSPCNTR(plane);
2173 val = I915_READ(reg);
2174 WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
2175
2176 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
2177 intel_flush_primary_plane(dev_priv, plane);
2178}
2179
2180static bool need_vtd_wa(struct drm_device *dev)
2181{
2182#ifdef CONFIG_INTEL_IOMMU
2183 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2184 return true;
2185#endif
2186 return false;
2187}
2188
2189static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2190{
2191 int tile_height;
2192
2193 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2194 return ALIGN(height, tile_height);
2195}
2196
2197int
2198intel_pin_and_fence_fb_obj(struct drm_device *dev,
2199 struct drm_i915_gem_object *obj,
2200 struct intel_engine_cs *pipelined)
2201{
2202 struct drm_i915_private *dev_priv = dev->dev_private;
2203 u32 alignment;
2204 int ret;
2205
2206 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2207
2208 switch (obj->tiling_mode) {
2209 case I915_TILING_NONE:
2210 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2211 alignment = 128 * 1024;
2212 else if (INTEL_INFO(dev)->gen >= 4)
2213 alignment = 4 * 1024;
2214 else
2215 alignment = 64 * 1024;
2216 break;
2217 case I915_TILING_X:
2218 /* pin() will align the object as required by fence */
2219 alignment = 0;
2220 break;
2221 case I915_TILING_Y:
2222 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2223 return -EINVAL;
2224 default:
2225 BUG();
2226 }
2227
2228 /* Note that the w/a also requires 64 PTE of padding following the
2229 * bo. We currently fill all unused PTE with the shadow page and so
2230 * we should always have valid PTE following the scanout preventing
2231 * the VT-d warning.
2232 */
2233 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2234 alignment = 256 * 1024;
2235
2236 dev_priv->mm.interruptible = false;
2237 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2238 if (ret)
2239 goto err_interruptible;
2240
2241 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2242 * fence, whereas 965+ only requires a fence if using
2243 * framebuffer compression. For simplicity, we always install
2244 * a fence as the cost is not that onerous.
2245 */
2246 ret = i915_gem_object_get_fence(obj);
2247 if (ret)
2248 goto err_unpin;
2249
2250 i915_gem_object_pin_fence(obj);
2251
2252 dev_priv->mm.interruptible = true;
2253 return 0;
2254
2255err_unpin:
2256 i915_gem_object_unpin_from_display_plane(obj);
2257err_interruptible:
2258 dev_priv->mm.interruptible = true;
2259 return ret;
2260}
2261
2262void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2263{
2264 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2265
2266 i915_gem_object_unpin_fence(obj);
2267 i915_gem_object_unpin_from_display_plane(obj);
2268}
2269
2270/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2271 * is assumed to be a power-of-two. */
2272unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2273 unsigned int tiling_mode,
2274 unsigned int cpp,
2275 unsigned int pitch)
2276{
2277 if (tiling_mode != I915_TILING_NONE) {
2278 unsigned int tile_rows, tiles;
2279
2280 tile_rows = *y / 8;
2281 *y %= 8;
2282
2283 tiles = *x / (512/cpp);
2284 *x %= 512/cpp;
2285
2286 return tile_rows * pitch * 8 + tiles * 4096;
2287 } else {
2288 unsigned int offset;
2289
2290 offset = *y * pitch + *x * cpp;
2291 *y = 0;
2292 *x = (offset & 4095) / cpp;
2293 return offset & -4096;
2294 }
2295}
2296
2297int intel_format_to_fourcc(int format)
2298{
2299 switch (format) {
2300 case DISPPLANE_8BPP:
2301 return DRM_FORMAT_C8;
2302 case DISPPLANE_BGRX555:
2303 return DRM_FORMAT_XRGB1555;
2304 case DISPPLANE_BGRX565:
2305 return DRM_FORMAT_RGB565;
2306 default:
2307 case DISPPLANE_BGRX888:
2308 return DRM_FORMAT_XRGB8888;
2309 case DISPPLANE_RGBX888:
2310 return DRM_FORMAT_XBGR8888;
2311 case DISPPLANE_BGRX101010:
2312 return DRM_FORMAT_XRGB2101010;
2313 case DISPPLANE_RGBX101010:
2314 return DRM_FORMAT_XBGR2101010;
2315 }
2316}
2317
2318static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2319 struct intel_plane_config *plane_config)
2320{
2321 struct drm_device *dev = crtc->base.dev;
2322 struct drm_i915_gem_object *obj = NULL;
2323 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2324 u32 base = plane_config->base;
2325
2326 if (plane_config->size == 0)
2327 return false;
2328
2329 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2330 plane_config->size);
2331 if (!obj)
2332 return false;
2333
2334 if (plane_config->tiled) {
2335 obj->tiling_mode = I915_TILING_X;
2336 obj->stride = crtc->base.primary->fb->pitches[0];
2337 }
2338
2339 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2340 mode_cmd.width = crtc->base.primary->fb->width;
2341 mode_cmd.height = crtc->base.primary->fb->height;
2342 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2343
2344 mutex_lock(&dev->struct_mutex);
2345
2346 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2347 &mode_cmd, obj)) {
2348 DRM_DEBUG_KMS("intel fb init failed\n");
2349 goto out_unref_obj;
2350 }
2351
2352 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2353 mutex_unlock(&dev->struct_mutex);
2354
2355 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2356 return true;
2357
2358out_unref_obj:
2359 drm_gem_object_unreference(&obj->base);
2360 mutex_unlock(&dev->struct_mutex);
2361 return false;
2362}
2363
2364static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2365 struct intel_plane_config *plane_config)
2366{
2367 struct drm_device *dev = intel_crtc->base.dev;
2368 struct drm_crtc *c;
2369 struct intel_crtc *i;
2370 struct drm_i915_gem_object *obj;
2371
2372 if (!intel_crtc->base.primary->fb)
2373 return;
2374
2375 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2376 return;
2377
2378 kfree(intel_crtc->base.primary->fb);
2379 intel_crtc->base.primary->fb = NULL;
2380
2381 /*
2382 * Failed to alloc the obj, check to see if we should share
2383 * an fb with another CRTC instead
2384 */
2385 for_each_crtc(dev, c) {
2386 i = to_intel_crtc(c);
2387
2388 if (c == &intel_crtc->base)
2389 continue;
2390
2391 if (!i->active)
2392 continue;
2393
2394 obj = intel_fb_obj(c->primary->fb);
2395 if (obj == NULL)
2396 continue;
2397
2398 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2399 drm_framebuffer_reference(c->primary->fb);
2400 intel_crtc->base.primary->fb = c->primary->fb;
2401 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2402 break;
2403 }
2404 }
2405}
2406
2407static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2408 struct drm_framebuffer *fb,
2409 int x, int y)
2410{
2411 struct drm_device *dev = crtc->dev;
2412 struct drm_i915_private *dev_priv = dev->dev_private;
2413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2414 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2415 int plane = intel_crtc->plane;
2416 unsigned long linear_offset;
2417 u32 dspcntr;
2418 u32 reg;
2419
2420 reg = DSPCNTR(plane);
2421 dspcntr = I915_READ(reg);
2422 /* Mask out pixel format bits in case we change it */
2423 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2424 switch (fb->pixel_format) {
2425 case DRM_FORMAT_C8:
2426 dspcntr |= DISPPLANE_8BPP;
2427 break;
2428 case DRM_FORMAT_XRGB1555:
2429 case DRM_FORMAT_ARGB1555:
2430 dspcntr |= DISPPLANE_BGRX555;
2431 break;
2432 case DRM_FORMAT_RGB565:
2433 dspcntr |= DISPPLANE_BGRX565;
2434 break;
2435 case DRM_FORMAT_XRGB8888:
2436 case DRM_FORMAT_ARGB8888:
2437 dspcntr |= DISPPLANE_BGRX888;
2438 break;
2439 case DRM_FORMAT_XBGR8888:
2440 case DRM_FORMAT_ABGR8888:
2441 dspcntr |= DISPPLANE_RGBX888;
2442 break;
2443 case DRM_FORMAT_XRGB2101010:
2444 case DRM_FORMAT_ARGB2101010:
2445 dspcntr |= DISPPLANE_BGRX101010;
2446 break;
2447 case DRM_FORMAT_XBGR2101010:
2448 case DRM_FORMAT_ABGR2101010:
2449 dspcntr |= DISPPLANE_RGBX101010;
2450 break;
2451 default:
2452 BUG();
2453 }
2454
2455 if (INTEL_INFO(dev)->gen >= 4) {
2456 if (obj->tiling_mode != I915_TILING_NONE)
2457 dspcntr |= DISPPLANE_TILED;
2458 else
2459 dspcntr &= ~DISPPLANE_TILED;
2460 }
2461
2462 if (IS_G4X(dev))
2463 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2464
2465 I915_WRITE(reg, dspcntr);
2466
2467 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2468
2469 if (INTEL_INFO(dev)->gen >= 4) {
2470 intel_crtc->dspaddr_offset =
2471 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2472 fb->bits_per_pixel / 8,
2473 fb->pitches[0]);
2474 linear_offset -= intel_crtc->dspaddr_offset;
2475 } else {
2476 intel_crtc->dspaddr_offset = linear_offset;
2477 }
2478
2479 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2480 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2481 fb->pitches[0]);
2482 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2483 if (INTEL_INFO(dev)->gen >= 4) {
2484 I915_WRITE(DSPSURF(plane),
2485 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2486 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2487 I915_WRITE(DSPLINOFF(plane), linear_offset);
2488 } else
2489 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2490 POSTING_READ(reg);
2491}
2492
2493static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2494 struct drm_framebuffer *fb,
2495 int x, int y)
2496{
2497 struct drm_device *dev = crtc->dev;
2498 struct drm_i915_private *dev_priv = dev->dev_private;
2499 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2500 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2501 int plane = intel_crtc->plane;
2502 unsigned long linear_offset;
2503 u32 dspcntr;
2504 u32 reg;
2505
2506 reg = DSPCNTR(plane);
2507 dspcntr = I915_READ(reg);
2508 /* Mask out pixel format bits in case we change it */
2509 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2510 switch (fb->pixel_format) {
2511 case DRM_FORMAT_C8:
2512 dspcntr |= DISPPLANE_8BPP;
2513 break;
2514 case DRM_FORMAT_RGB565:
2515 dspcntr |= DISPPLANE_BGRX565;
2516 break;
2517 case DRM_FORMAT_XRGB8888:
2518 case DRM_FORMAT_ARGB8888:
2519 dspcntr |= DISPPLANE_BGRX888;
2520 break;
2521 case DRM_FORMAT_XBGR8888:
2522 case DRM_FORMAT_ABGR8888:
2523 dspcntr |= DISPPLANE_RGBX888;
2524 break;
2525 case DRM_FORMAT_XRGB2101010:
2526 case DRM_FORMAT_ARGB2101010:
2527 dspcntr |= DISPPLANE_BGRX101010;
2528 break;
2529 case DRM_FORMAT_XBGR2101010:
2530 case DRM_FORMAT_ABGR2101010:
2531 dspcntr |= DISPPLANE_RGBX101010;
2532 break;
2533 default:
2534 BUG();
2535 }
2536
2537 if (obj->tiling_mode != I915_TILING_NONE)
2538 dspcntr |= DISPPLANE_TILED;
2539 else
2540 dspcntr &= ~DISPPLANE_TILED;
2541
2542 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2543 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2544 else
2545 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2546
2547 I915_WRITE(reg, dspcntr);
2548
2549 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2550 intel_crtc->dspaddr_offset =
2551 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2552 fb->bits_per_pixel / 8,
2553 fb->pitches[0]);
2554 linear_offset -= intel_crtc->dspaddr_offset;
2555
2556 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2557 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2558 fb->pitches[0]);
2559 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2560 I915_WRITE(DSPSURF(plane),
2561 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2562 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2563 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2564 } else {
2565 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2566 I915_WRITE(DSPLINOFF(plane), linear_offset);
2567 }
2568 POSTING_READ(reg);
2569}
2570
2571/* Assume fb object is pinned & idle & fenced and just update base pointers */
2572static int
2573intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2574 int x, int y, enum mode_set_atomic state)
2575{
2576 struct drm_device *dev = crtc->dev;
2577 struct drm_i915_private *dev_priv = dev->dev_private;
2578
2579 if (dev_priv->display.disable_fbc)
2580 dev_priv->display.disable_fbc(dev);
2581 intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe);
2582
2583 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2584
2585 return 0;
2586}
2587
2588void intel_display_handle_reset(struct drm_device *dev)
2589{
2590 struct drm_i915_private *dev_priv = dev->dev_private;
2591 struct drm_crtc *crtc;
2592
2593 /*
2594 * Flips in the rings have been nuked by the reset,
2595 * so complete all pending flips so that user space
2596 * will get its events and not get stuck.
2597 *
2598 * Also update the base address of all primary
2599 * planes to the the last fb to make sure we're
2600 * showing the correct fb after a reset.
2601 *
2602 * Need to make two loops over the crtcs so that we
2603 * don't try to grab a crtc mutex before the
2604 * pending_flip_queue really got woken up.
2605 */
2606
2607 for_each_crtc(dev, crtc) {
2608 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2609 enum plane plane = intel_crtc->plane;
2610
2611 intel_prepare_page_flip(dev, plane);
2612 intel_finish_page_flip_plane(dev, plane);
2613 }
2614
2615 for_each_crtc(dev, crtc) {
2616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2617
2618 drm_modeset_lock(&crtc->mutex, NULL);
2619 /*
2620 * FIXME: Once we have proper support for primary planes (and
2621 * disabling them without disabling the entire crtc) allow again
2622 * a NULL crtc->primary->fb.
2623 */
2624 if (intel_crtc->active && crtc->primary->fb)
2625 dev_priv->display.update_primary_plane(crtc,
2626 crtc->primary->fb,
2627 crtc->x,
2628 crtc->y);
2629 drm_modeset_unlock(&crtc->mutex);
2630 }
2631}
2632
2633static int
2634intel_finish_fb(struct drm_framebuffer *old_fb)
2635{
2636 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2637 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2638 bool was_interruptible = dev_priv->mm.interruptible;
2639 int ret;
2640
2641 /* Big Hammer, we also need to ensure that any pending
2642 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2643 * current scanout is retired before unpinning the old
2644 * framebuffer.
2645 *
2646 * This should only fail upon a hung GPU, in which case we
2647 * can safely continue.
2648 */
2649 dev_priv->mm.interruptible = false;
2650 ret = i915_gem_object_finish_gpu(obj);
2651 dev_priv->mm.interruptible = was_interruptible;
2652
2653 return ret;
2654}
2655
2656static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2657{
2658 struct drm_device *dev = crtc->dev;
2659 struct drm_i915_private *dev_priv = dev->dev_private;
2660 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2661 unsigned long flags;
2662 bool pending;
2663
2664 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2665 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2666 return false;
2667
2668 spin_lock_irqsave(&dev->event_lock, flags);
2669 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2670 spin_unlock_irqrestore(&dev->event_lock, flags);
2671
2672 return pending;
2673}
2674
2675static int
2676intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2677 struct drm_framebuffer *fb)
2678{
2679 struct drm_device *dev = crtc->dev;
2680 struct drm_i915_private *dev_priv = dev->dev_private;
2681 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2682 enum pipe pipe = intel_crtc->pipe;
2683 struct drm_framebuffer *old_fb = crtc->primary->fb;
2684 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2685 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2686 int ret;
2687
2688 if (intel_crtc_has_pending_flip(crtc)) {
2689 DRM_ERROR("pipe is still busy with an old pageflip\n");
2690 return -EBUSY;
2691 }
2692
2693 /* no fb bound */
2694 if (!fb) {
2695 DRM_ERROR("No FB bound\n");
2696 return 0;
2697 }
2698
2699 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2700 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2701 plane_name(intel_crtc->plane),
2702 INTEL_INFO(dev)->num_pipes);
2703 return -EINVAL;
2704 }
2705
2706 mutex_lock(&dev->struct_mutex);
2707 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2708 if (ret == 0)
2709 i915_gem_track_fb(old_obj, obj,
2710 INTEL_FRONTBUFFER_PRIMARY(pipe));
2711 mutex_unlock(&dev->struct_mutex);
2712 if (ret != 0) {
2713 DRM_ERROR("pin & fence failed\n");
2714 return ret;
2715 }
2716
2717 /*
2718 * Update pipe size and adjust fitter if needed: the reason for this is
2719 * that in compute_mode_changes we check the native mode (not the pfit
2720 * mode) to see if we can flip rather than do a full mode set. In the
2721 * fastboot case, we'll flip, but if we don't update the pipesrc and
2722 * pfit state, we'll end up with a big fb scanned out into the wrong
2723 * sized surface.
2724 *
2725 * To fix this properly, we need to hoist the checks up into
2726 * compute_mode_changes (or above), check the actual pfit state and
2727 * whether the platform allows pfit disable with pipe active, and only
2728 * then update the pipesrc and pfit state, even on the flip path.
2729 */
2730 if (i915.fastboot) {
2731 const struct drm_display_mode *adjusted_mode =
2732 &intel_crtc->config.adjusted_mode;
2733
2734 I915_WRITE(PIPESRC(intel_crtc->pipe),
2735 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2736 (adjusted_mode->crtc_vdisplay - 1));
2737 if (!intel_crtc->config.pch_pfit.enabled &&
2738 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2739 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2740 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2741 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2742 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2743 }
2744 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2745 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2746 }
2747
2748 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2749
2750 if (intel_crtc->active)
2751 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2752
2753 crtc->primary->fb = fb;
2754 crtc->x = x;
2755 crtc->y = y;
2756
2757 if (old_fb) {
2758 if (intel_crtc->active && old_fb != fb)
2759 intel_wait_for_vblank(dev, intel_crtc->pipe);
2760 mutex_lock(&dev->struct_mutex);
2761 intel_unpin_fb_obj(old_obj);
2762 mutex_unlock(&dev->struct_mutex);
2763 }
2764
2765 mutex_lock(&dev->struct_mutex);
2766 intel_update_fbc(dev);
2767 mutex_unlock(&dev->struct_mutex);
2768
2769 return 0;
2770}
2771
2772static void intel_fdi_normal_train(struct drm_crtc *crtc)
2773{
2774 struct drm_device *dev = crtc->dev;
2775 struct drm_i915_private *dev_priv = dev->dev_private;
2776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2777 int pipe = intel_crtc->pipe;
2778 u32 reg, temp;
2779
2780 /* enable normal train */
2781 reg = FDI_TX_CTL(pipe);
2782 temp = I915_READ(reg);
2783 if (IS_IVYBRIDGE(dev)) {
2784 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2785 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2786 } else {
2787 temp &= ~FDI_LINK_TRAIN_NONE;
2788 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2789 }
2790 I915_WRITE(reg, temp);
2791
2792 reg = FDI_RX_CTL(pipe);
2793 temp = I915_READ(reg);
2794 if (HAS_PCH_CPT(dev)) {
2795 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2796 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2797 } else {
2798 temp &= ~FDI_LINK_TRAIN_NONE;
2799 temp |= FDI_LINK_TRAIN_NONE;
2800 }
2801 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2802
2803 /* wait one idle pattern time */
2804 POSTING_READ(reg);
2805 udelay(1000);
2806
2807 /* IVB wants error correction enabled */
2808 if (IS_IVYBRIDGE(dev))
2809 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2810 FDI_FE_ERRC_ENABLE);
2811}
2812
2813static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2814{
2815 return crtc->base.enabled && crtc->active &&
2816 crtc->config.has_pch_encoder;
2817}
2818
2819static void ivb_modeset_global_resources(struct drm_device *dev)
2820{
2821 struct drm_i915_private *dev_priv = dev->dev_private;
2822 struct intel_crtc *pipe_B_crtc =
2823 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2824 struct intel_crtc *pipe_C_crtc =
2825 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2826 uint32_t temp;
2827
2828 /*
2829 * When everything is off disable fdi C so that we could enable fdi B
2830 * with all lanes. Note that we don't care about enabled pipes without
2831 * an enabled pch encoder.
2832 */
2833 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2834 !pipe_has_enabled_pch(pipe_C_crtc)) {
2835 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2836 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2837
2838 temp = I915_READ(SOUTH_CHICKEN1);
2839 temp &= ~FDI_BC_BIFURCATION_SELECT;
2840 DRM_DEBUG_KMS("disabling fdi C rx\n");
2841 I915_WRITE(SOUTH_CHICKEN1, temp);
2842 }
2843}
2844
2845/* The FDI link training functions for ILK/Ibexpeak. */
2846static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2847{
2848 struct drm_device *dev = crtc->dev;
2849 struct drm_i915_private *dev_priv = dev->dev_private;
2850 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2851 int pipe = intel_crtc->pipe;
2852 u32 reg, temp, tries;
2853
2854 /* FDI needs bits from pipe first */
2855 assert_pipe_enabled(dev_priv, pipe);
2856
2857 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2858 for train result */
2859 reg = FDI_RX_IMR(pipe);
2860 temp = I915_READ(reg);
2861 temp &= ~FDI_RX_SYMBOL_LOCK;
2862 temp &= ~FDI_RX_BIT_LOCK;
2863 I915_WRITE(reg, temp);
2864 I915_READ(reg);
2865 udelay(150);
2866
2867 /* enable CPU FDI TX and PCH FDI RX */
2868 reg = FDI_TX_CTL(pipe);
2869 temp = I915_READ(reg);
2870 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2871 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2872 temp &= ~FDI_LINK_TRAIN_NONE;
2873 temp |= FDI_LINK_TRAIN_PATTERN_1;
2874 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2875
2876 reg = FDI_RX_CTL(pipe);
2877 temp = I915_READ(reg);
2878 temp &= ~FDI_LINK_TRAIN_NONE;
2879 temp |= FDI_LINK_TRAIN_PATTERN_1;
2880 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2881
2882 POSTING_READ(reg);
2883 udelay(150);
2884
2885 /* Ironlake workaround, enable clock pointer after FDI enable*/
2886 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2887 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2888 FDI_RX_PHASE_SYNC_POINTER_EN);
2889
2890 reg = FDI_RX_IIR(pipe);
2891 for (tries = 0; tries < 5; tries++) {
2892 temp = I915_READ(reg);
2893 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2894
2895 if ((temp & FDI_RX_BIT_LOCK)) {
2896 DRM_DEBUG_KMS("FDI train 1 done.\n");
2897 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2898 break;
2899 }
2900 }
2901 if (tries == 5)
2902 DRM_ERROR("FDI train 1 fail!\n");
2903
2904 /* Train 2 */
2905 reg = FDI_TX_CTL(pipe);
2906 temp = I915_READ(reg);
2907 temp &= ~FDI_LINK_TRAIN_NONE;
2908 temp |= FDI_LINK_TRAIN_PATTERN_2;
2909 I915_WRITE(reg, temp);
2910
2911 reg = FDI_RX_CTL(pipe);
2912 temp = I915_READ(reg);
2913 temp &= ~FDI_LINK_TRAIN_NONE;
2914 temp |= FDI_LINK_TRAIN_PATTERN_2;
2915 I915_WRITE(reg, temp);
2916
2917 POSTING_READ(reg);
2918 udelay(150);
2919
2920 reg = FDI_RX_IIR(pipe);
2921 for (tries = 0; tries < 5; tries++) {
2922 temp = I915_READ(reg);
2923 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2924
2925 if (temp & FDI_RX_SYMBOL_LOCK) {
2926 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2927 DRM_DEBUG_KMS("FDI train 2 done.\n");
2928 break;
2929 }
2930 }
2931 if (tries == 5)
2932 DRM_ERROR("FDI train 2 fail!\n");
2933
2934 DRM_DEBUG_KMS("FDI train done\n");
2935
2936}
2937
2938static const int snb_b_fdi_train_param[] = {
2939 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2940 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2941 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2942 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2943};
2944
2945/* The FDI link training functions for SNB/Cougarpoint. */
2946static void gen6_fdi_link_train(struct drm_crtc *crtc)
2947{
2948 struct drm_device *dev = crtc->dev;
2949 struct drm_i915_private *dev_priv = dev->dev_private;
2950 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2951 int pipe = intel_crtc->pipe;
2952 u32 reg, temp, i, retry;
2953
2954 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2955 for train result */
2956 reg = FDI_RX_IMR(pipe);
2957 temp = I915_READ(reg);
2958 temp &= ~FDI_RX_SYMBOL_LOCK;
2959 temp &= ~FDI_RX_BIT_LOCK;
2960 I915_WRITE(reg, temp);
2961
2962 POSTING_READ(reg);
2963 udelay(150);
2964
2965 /* enable CPU FDI TX and PCH FDI RX */
2966 reg = FDI_TX_CTL(pipe);
2967 temp = I915_READ(reg);
2968 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2969 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2970 temp &= ~FDI_LINK_TRAIN_NONE;
2971 temp |= FDI_LINK_TRAIN_PATTERN_1;
2972 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2973 /* SNB-B */
2974 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2975 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2976
2977 I915_WRITE(FDI_RX_MISC(pipe),
2978 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2979
2980 reg = FDI_RX_CTL(pipe);
2981 temp = I915_READ(reg);
2982 if (HAS_PCH_CPT(dev)) {
2983 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2984 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2985 } else {
2986 temp &= ~FDI_LINK_TRAIN_NONE;
2987 temp |= FDI_LINK_TRAIN_PATTERN_1;
2988 }
2989 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2990
2991 POSTING_READ(reg);
2992 udelay(150);
2993
2994 for (i = 0; i < 4; i++) {
2995 reg = FDI_TX_CTL(pipe);
2996 temp = I915_READ(reg);
2997 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2998 temp |= snb_b_fdi_train_param[i];
2999 I915_WRITE(reg, temp);
3000
3001 POSTING_READ(reg);
3002 udelay(500);
3003
3004 for (retry = 0; retry < 5; retry++) {
3005 reg = FDI_RX_IIR(pipe);
3006 temp = I915_READ(reg);
3007 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3008 if (temp & FDI_RX_BIT_LOCK) {
3009 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3010 DRM_DEBUG_KMS("FDI train 1 done.\n");
3011 break;
3012 }
3013 udelay(50);
3014 }
3015 if (retry < 5)
3016 break;
3017 }
3018 if (i == 4)
3019 DRM_ERROR("FDI train 1 fail!\n");
3020
3021 /* Train 2 */
3022 reg = FDI_TX_CTL(pipe);
3023 temp = I915_READ(reg);
3024 temp &= ~FDI_LINK_TRAIN_NONE;
3025 temp |= FDI_LINK_TRAIN_PATTERN_2;
3026 if (IS_GEN6(dev)) {
3027 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3028 /* SNB-B */
3029 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3030 }
3031 I915_WRITE(reg, temp);
3032
3033 reg = FDI_RX_CTL(pipe);
3034 temp = I915_READ(reg);
3035 if (HAS_PCH_CPT(dev)) {
3036 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3037 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3038 } else {
3039 temp &= ~FDI_LINK_TRAIN_NONE;
3040 temp |= FDI_LINK_TRAIN_PATTERN_2;
3041 }
3042 I915_WRITE(reg, temp);
3043
3044 POSTING_READ(reg);
3045 udelay(150);
3046
3047 for (i = 0; i < 4; i++) {
3048 reg = FDI_TX_CTL(pipe);
3049 temp = I915_READ(reg);
3050 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3051 temp |= snb_b_fdi_train_param[i];
3052 I915_WRITE(reg, temp);
3053
3054 POSTING_READ(reg);
3055 udelay(500);
3056
3057 for (retry = 0; retry < 5; retry++) {
3058 reg = FDI_RX_IIR(pipe);
3059 temp = I915_READ(reg);
3060 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3061 if (temp & FDI_RX_SYMBOL_LOCK) {
3062 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3063 DRM_DEBUG_KMS("FDI train 2 done.\n");
3064 break;
3065 }
3066 udelay(50);
3067 }
3068 if (retry < 5)
3069 break;
3070 }
3071 if (i == 4)
3072 DRM_ERROR("FDI train 2 fail!\n");
3073
3074 DRM_DEBUG_KMS("FDI train done.\n");
3075}
3076
3077/* Manual link training for Ivy Bridge A0 parts */
3078static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3079{
3080 struct drm_device *dev = crtc->dev;
3081 struct drm_i915_private *dev_priv = dev->dev_private;
3082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3083 int pipe = intel_crtc->pipe;
3084 u32 reg, temp, i, j;
3085
3086 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3087 for train result */
3088 reg = FDI_RX_IMR(pipe);
3089 temp = I915_READ(reg);
3090 temp &= ~FDI_RX_SYMBOL_LOCK;
3091 temp &= ~FDI_RX_BIT_LOCK;
3092 I915_WRITE(reg, temp);
3093
3094 POSTING_READ(reg);
3095 udelay(150);
3096
3097 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3098 I915_READ(FDI_RX_IIR(pipe)));
3099
3100 /* Try each vswing and preemphasis setting twice before moving on */
3101 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3102 /* disable first in case we need to retry */
3103 reg = FDI_TX_CTL(pipe);
3104 temp = I915_READ(reg);
3105 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3106 temp &= ~FDI_TX_ENABLE;
3107 I915_WRITE(reg, temp);
3108
3109 reg = FDI_RX_CTL(pipe);
3110 temp = I915_READ(reg);
3111 temp &= ~FDI_LINK_TRAIN_AUTO;
3112 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3113 temp &= ~FDI_RX_ENABLE;
3114 I915_WRITE(reg, temp);
3115
3116 /* enable CPU FDI TX and PCH FDI RX */
3117 reg = FDI_TX_CTL(pipe);
3118 temp = I915_READ(reg);
3119 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3120 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3121 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3122 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3123 temp |= snb_b_fdi_train_param[j/2];
3124 temp |= FDI_COMPOSITE_SYNC;
3125 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3126
3127 I915_WRITE(FDI_RX_MISC(pipe),
3128 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3129
3130 reg = FDI_RX_CTL(pipe);
3131 temp = I915_READ(reg);
3132 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3133 temp |= FDI_COMPOSITE_SYNC;
3134 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3135
3136 POSTING_READ(reg);
3137 udelay(1); /* should be 0.5us */
3138
3139 for (i = 0; i < 4; i++) {
3140 reg = FDI_RX_IIR(pipe);
3141 temp = I915_READ(reg);
3142 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3143
3144 if (temp & FDI_RX_BIT_LOCK ||
3145 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3146 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3147 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3148 i);
3149 break;
3150 }
3151 udelay(1); /* should be 0.5us */
3152 }
3153 if (i == 4) {
3154 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3155 continue;
3156 }
3157
3158 /* Train 2 */
3159 reg = FDI_TX_CTL(pipe);
3160 temp = I915_READ(reg);
3161 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3162 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3163 I915_WRITE(reg, temp);
3164
3165 reg = FDI_RX_CTL(pipe);
3166 temp = I915_READ(reg);
3167 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3168 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3169 I915_WRITE(reg, temp);
3170
3171 POSTING_READ(reg);
3172 udelay(2); /* should be 1.5us */
3173
3174 for (i = 0; i < 4; i++) {
3175 reg = FDI_RX_IIR(pipe);
3176 temp = I915_READ(reg);
3177 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3178
3179 if (temp & FDI_RX_SYMBOL_LOCK ||
3180 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3181 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3182 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3183 i);
3184 goto train_done;
3185 }
3186 udelay(2); /* should be 1.5us */
3187 }
3188 if (i == 4)
3189 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3190 }
3191
3192train_done:
3193 DRM_DEBUG_KMS("FDI train done.\n");
3194}
3195
3196static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3197{
3198 struct drm_device *dev = intel_crtc->base.dev;
3199 struct drm_i915_private *dev_priv = dev->dev_private;
3200 int pipe = intel_crtc->pipe;
3201 u32 reg, temp;
3202
3203
3204 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3205 reg = FDI_RX_CTL(pipe);
3206 temp = I915_READ(reg);
3207 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3208 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3209 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3210 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3211
3212 POSTING_READ(reg);
3213 udelay(200);
3214
3215 /* Switch from Rawclk to PCDclk */
3216 temp = I915_READ(reg);
3217 I915_WRITE(reg, temp | FDI_PCDCLK);
3218
3219 POSTING_READ(reg);
3220 udelay(200);
3221
3222 /* Enable CPU FDI TX PLL, always on for Ironlake */
3223 reg = FDI_TX_CTL(pipe);
3224 temp = I915_READ(reg);
3225 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3226 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3227
3228 POSTING_READ(reg);
3229 udelay(100);
3230 }
3231}
3232
3233static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3234{
3235 struct drm_device *dev = intel_crtc->base.dev;
3236 struct drm_i915_private *dev_priv = dev->dev_private;
3237 int pipe = intel_crtc->pipe;
3238 u32 reg, temp;
3239
3240 /* Switch from PCDclk to Rawclk */
3241 reg = FDI_RX_CTL(pipe);
3242 temp = I915_READ(reg);
3243 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3244
3245 /* Disable CPU FDI TX PLL */
3246 reg = FDI_TX_CTL(pipe);
3247 temp = I915_READ(reg);
3248 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3249
3250 POSTING_READ(reg);
3251 udelay(100);
3252
3253 reg = FDI_RX_CTL(pipe);
3254 temp = I915_READ(reg);
3255 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3256
3257 /* Wait for the clocks to turn off. */
3258 POSTING_READ(reg);
3259 udelay(100);
3260}
3261
3262static void ironlake_fdi_disable(struct drm_crtc *crtc)
3263{
3264 struct drm_device *dev = crtc->dev;
3265 struct drm_i915_private *dev_priv = dev->dev_private;
3266 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3267 int pipe = intel_crtc->pipe;
3268 u32 reg, temp;
3269
3270 /* disable CPU FDI tx and PCH FDI rx */
3271 reg = FDI_TX_CTL(pipe);
3272 temp = I915_READ(reg);
3273 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3274 POSTING_READ(reg);
3275
3276 reg = FDI_RX_CTL(pipe);
3277 temp = I915_READ(reg);
3278 temp &= ~(0x7 << 16);
3279 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3280 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3281
3282 POSTING_READ(reg);
3283 udelay(100);
3284
3285 /* Ironlake workaround, disable clock pointer after downing FDI */
3286 if (HAS_PCH_IBX(dev))
3287 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3288
3289 /* still set train pattern 1 */
3290 reg = FDI_TX_CTL(pipe);
3291 temp = I915_READ(reg);
3292 temp &= ~FDI_LINK_TRAIN_NONE;
3293 temp |= FDI_LINK_TRAIN_PATTERN_1;
3294 I915_WRITE(reg, temp);
3295
3296 reg = FDI_RX_CTL(pipe);
3297 temp = I915_READ(reg);
3298 if (HAS_PCH_CPT(dev)) {
3299 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3300 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3301 } else {
3302 temp &= ~FDI_LINK_TRAIN_NONE;
3303 temp |= FDI_LINK_TRAIN_PATTERN_1;
3304 }
3305 /* BPC in FDI rx is consistent with that in PIPECONF */
3306 temp &= ~(0x07 << 16);
3307 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3308 I915_WRITE(reg, temp);
3309
3310 POSTING_READ(reg);
3311 udelay(100);
3312}
3313
3314bool intel_has_pending_fb_unpin(struct drm_device *dev)
3315{
3316 struct intel_crtc *crtc;
3317
3318 /* Note that we don't need to be called with mode_config.lock here
3319 * as our list of CRTC objects is static for the lifetime of the
3320 * device and so cannot disappear as we iterate. Similarly, we can
3321 * happily treat the predicates as racy, atomic checks as userspace
3322 * cannot claim and pin a new fb without at least acquring the
3323 * struct_mutex and so serialising with us.
3324 */
3325 for_each_intel_crtc(dev, crtc) {
3326 if (atomic_read(&crtc->unpin_work_count) == 0)
3327 continue;
3328
3329 if (crtc->unpin_work)
3330 intel_wait_for_vblank(dev, crtc->pipe);
3331
3332 return true;
3333 }
3334
3335 return false;
3336}
3337
3338void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3339{
3340 struct drm_device *dev = crtc->dev;
3341 struct drm_i915_private *dev_priv = dev->dev_private;
3342
3343 if (crtc->primary->fb == NULL)
3344 return;
3345
3346 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3347
3348 WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3349 !intel_crtc_has_pending_flip(crtc),
3350 60*HZ) == 0);
3351
3352 mutex_lock(&dev->struct_mutex);
3353 intel_finish_fb(crtc->primary->fb);
3354 mutex_unlock(&dev->struct_mutex);
3355}
3356
3357/* Program iCLKIP clock to the desired frequency */
3358static void lpt_program_iclkip(struct drm_crtc *crtc)
3359{
3360 struct drm_device *dev = crtc->dev;
3361 struct drm_i915_private *dev_priv = dev->dev_private;
3362 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3363 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3364 u32 temp;
3365
3366 mutex_lock(&dev_priv->dpio_lock);
3367
3368 /* It is necessary to ungate the pixclk gate prior to programming
3369 * the divisors, and gate it back when it is done.
3370 */
3371 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3372
3373 /* Disable SSCCTL */
3374 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3375 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3376 SBI_SSCCTL_DISABLE,
3377 SBI_ICLK);
3378
3379 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3380 if (clock == 20000) {
3381 auxdiv = 1;
3382 divsel = 0x41;
3383 phaseinc = 0x20;
3384 } else {
3385 /* The iCLK virtual clock root frequency is in MHz,
3386 * but the adjusted_mode->crtc_clock in in KHz. To get the
3387 * divisors, it is necessary to divide one by another, so we
3388 * convert the virtual clock precision to KHz here for higher
3389 * precision.
3390 */
3391 u32 iclk_virtual_root_freq = 172800 * 1000;
3392 u32 iclk_pi_range = 64;
3393 u32 desired_divisor, msb_divisor_value, pi_value;
3394
3395 desired_divisor = (iclk_virtual_root_freq / clock);
3396 msb_divisor_value = desired_divisor / iclk_pi_range;
3397 pi_value = desired_divisor % iclk_pi_range;
3398
3399 auxdiv = 0;
3400 divsel = msb_divisor_value - 2;
3401 phaseinc = pi_value;
3402 }
3403
3404 /* This should not happen with any sane values */
3405 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3406 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3407 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3408 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3409
3410 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3411 clock,
3412 auxdiv,
3413 divsel,
3414 phasedir,
3415 phaseinc);
3416
3417 /* Program SSCDIVINTPHASE6 */
3418 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3419 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3420 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3421 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3422 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3423 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3424 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3425 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3426
3427 /* Program SSCAUXDIV */
3428 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3429 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3430 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3431 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3432
3433 /* Enable modulator and associated divider */
3434 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3435 temp &= ~SBI_SSCCTL_DISABLE;
3436 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3437
3438 /* Wait for initialization time */
3439 udelay(24);
3440
3441 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3442
3443 mutex_unlock(&dev_priv->dpio_lock);
3444}
3445
3446static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3447 enum pipe pch_transcoder)
3448{
3449 struct drm_device *dev = crtc->base.dev;
3450 struct drm_i915_private *dev_priv = dev->dev_private;
3451 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3452
3453 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3454 I915_READ(HTOTAL(cpu_transcoder)));
3455 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3456 I915_READ(HBLANK(cpu_transcoder)));
3457 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3458 I915_READ(HSYNC(cpu_transcoder)));
3459
3460 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3461 I915_READ(VTOTAL(cpu_transcoder)));
3462 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3463 I915_READ(VBLANK(cpu_transcoder)));
3464 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3465 I915_READ(VSYNC(cpu_transcoder)));
3466 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3467 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3468}
3469
3470static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3471{
3472 struct drm_i915_private *dev_priv = dev->dev_private;
3473 uint32_t temp;
3474
3475 temp = I915_READ(SOUTH_CHICKEN1);
3476 if (temp & FDI_BC_BIFURCATION_SELECT)
3477 return;
3478
3479 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3480 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3481
3482 temp |= FDI_BC_BIFURCATION_SELECT;
3483 DRM_DEBUG_KMS("enabling fdi C rx\n");
3484 I915_WRITE(SOUTH_CHICKEN1, temp);
3485 POSTING_READ(SOUTH_CHICKEN1);
3486}
3487
3488static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3489{
3490 struct drm_device *dev = intel_crtc->base.dev;
3491 struct drm_i915_private *dev_priv = dev->dev_private;
3492
3493 switch (intel_crtc->pipe) {
3494 case PIPE_A:
3495 break;
3496 case PIPE_B:
3497 if (intel_crtc->config.fdi_lanes > 2)
3498 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3499 else
3500 cpt_enable_fdi_bc_bifurcation(dev);
3501
3502 break;
3503 case PIPE_C:
3504 cpt_enable_fdi_bc_bifurcation(dev);
3505
3506 break;
3507 default:
3508 BUG();
3509 }
3510}
3511
3512/*
3513 * Enable PCH resources required for PCH ports:
3514 * - PCH PLLs
3515 * - FDI training & RX/TX
3516 * - update transcoder timings
3517 * - DP transcoding bits
3518 * - transcoder
3519 */
3520static void ironlake_pch_enable(struct drm_crtc *crtc)
3521{
3522 struct drm_device *dev = crtc->dev;
3523 struct drm_i915_private *dev_priv = dev->dev_private;
3524 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3525 int pipe = intel_crtc->pipe;
3526 u32 reg, temp;
3527
3528 assert_pch_transcoder_disabled(dev_priv, pipe);
3529
3530 if (IS_IVYBRIDGE(dev))
3531 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3532
3533 /* Write the TU size bits before fdi link training, so that error
3534 * detection works. */
3535 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3536 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3537
3538 /* For PCH output, training FDI link */
3539 dev_priv->display.fdi_link_train(crtc);
3540
3541 /* We need to program the right clock selection before writing the pixel
3542 * mutliplier into the DPLL. */
3543 if (HAS_PCH_CPT(dev)) {
3544 u32 sel;
3545
3546 temp = I915_READ(PCH_DPLL_SEL);
3547 temp |= TRANS_DPLL_ENABLE(pipe);
3548 sel = TRANS_DPLLB_SEL(pipe);
3549 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3550 temp |= sel;
3551 else
3552 temp &= ~sel;
3553 I915_WRITE(PCH_DPLL_SEL, temp);
3554 }
3555
3556 /* XXX: pch pll's can be enabled any time before we enable the PCH
3557 * transcoder, and we actually should do this to not upset any PCH
3558 * transcoder that already use the clock when we share it.
3559 *
3560 * Note that enable_shared_dpll tries to do the right thing, but
3561 * get_shared_dpll unconditionally resets the pll - we need that to have
3562 * the right LVDS enable sequence. */
3563 intel_enable_shared_dpll(intel_crtc);
3564
3565 /* set transcoder timing, panel must allow it */
3566 assert_panel_unlocked(dev_priv, pipe);
3567 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3568
3569 intel_fdi_normal_train(crtc);
3570
3571 /* For PCH DP, enable TRANS_DP_CTL */
3572 if (HAS_PCH_CPT(dev) &&
3573 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3574 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3575 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3576 reg = TRANS_DP_CTL(pipe);
3577 temp = I915_READ(reg);
3578 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3579 TRANS_DP_SYNC_MASK |
3580 TRANS_DP_BPC_MASK);
3581 temp |= (TRANS_DP_OUTPUT_ENABLE |
3582 TRANS_DP_ENH_FRAMING);
3583 temp |= bpc << 9; /* same format but at 11:9 */
3584
3585 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3586 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3587 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3588 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3589
3590 switch (intel_trans_dp_port_sel(crtc)) {
3591 case PCH_DP_B:
3592 temp |= TRANS_DP_PORT_SEL_B;
3593 break;
3594 case PCH_DP_C:
3595 temp |= TRANS_DP_PORT_SEL_C;
3596 break;
3597 case PCH_DP_D:
3598 temp |= TRANS_DP_PORT_SEL_D;
3599 break;
3600 default:
3601 BUG();
3602 }
3603
3604 I915_WRITE(reg, temp);
3605 }
3606
3607 ironlake_enable_pch_transcoder(dev_priv, pipe);
3608}
3609
3610static void lpt_pch_enable(struct drm_crtc *crtc)
3611{
3612 struct drm_device *dev = crtc->dev;
3613 struct drm_i915_private *dev_priv = dev->dev_private;
3614 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3615 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3616
3617 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3618
3619 lpt_program_iclkip(crtc);
3620
3621 /* Set transcoder timing. */
3622 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3623
3624 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3625}
3626
3627void intel_put_shared_dpll(struct intel_crtc *crtc)
3628{
3629 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3630
3631 if (pll == NULL)
3632 return;
3633
3634 if (pll->refcount == 0) {
3635 WARN(1, "bad %s refcount\n", pll->name);
3636 return;
3637 }
3638
3639 if (--pll->refcount == 0) {
3640 WARN_ON(pll->on);
3641 WARN_ON(pll->active);
3642 }
3643
3644 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3645}
3646
3647struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3648{
3649 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3650 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3651 enum intel_dpll_id i;
3652
3653 if (pll) {
3654 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3655 crtc->base.base.id, pll->name);
3656 intel_put_shared_dpll(crtc);
3657 }
3658
3659 if (HAS_PCH_IBX(dev_priv->dev)) {
3660 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3661 i = (enum intel_dpll_id) crtc->pipe;
3662 pll = &dev_priv->shared_dplls[i];
3663
3664 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3665 crtc->base.base.id, pll->name);
3666
3667 WARN_ON(pll->refcount);
3668
3669 goto found;
3670 }
3671
3672 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3673 pll = &dev_priv->shared_dplls[i];
3674
3675 /* Only want to check enabled timings first */
3676 if (pll->refcount == 0)
3677 continue;
3678
3679 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3680 sizeof(pll->hw_state)) == 0) {
3681 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3682 crtc->base.base.id,
3683 pll->name, pll->refcount, pll->active);
3684
3685 goto found;
3686 }
3687 }
3688
3689 /* Ok no matching timings, maybe there's a free one? */
3690 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3691 pll = &dev_priv->shared_dplls[i];
3692 if (pll->refcount == 0) {
3693 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3694 crtc->base.base.id, pll->name);
3695 goto found;
3696 }
3697 }
3698
3699 return NULL;
3700
3701found:
3702 if (pll->refcount == 0)
3703 pll->hw_state = crtc->config.dpll_hw_state;
3704
3705 crtc->config.shared_dpll = i;
3706 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3707 pipe_name(crtc->pipe));
3708
3709 pll->refcount++;
3710
3711 return pll;
3712}
3713
3714static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3715{
3716 struct drm_i915_private *dev_priv = dev->dev_private;
3717 int dslreg = PIPEDSL(pipe);
3718 u32 temp;
3719
3720 temp = I915_READ(dslreg);
3721 udelay(500);
3722 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3723 if (wait_for(I915_READ(dslreg) != temp, 5))
3724 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3725 }
3726}
3727
3728static void ironlake_pfit_enable(struct intel_crtc *crtc)
3729{
3730 struct drm_device *dev = crtc->base.dev;
3731 struct drm_i915_private *dev_priv = dev->dev_private;
3732 int pipe = crtc->pipe;
3733
3734 if (crtc->config.pch_pfit.enabled) {
3735 /* Force use of hard-coded filter coefficients
3736 * as some pre-programmed values are broken,
3737 * e.g. x201.
3738 */
3739 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3740 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3741 PF_PIPE_SEL_IVB(pipe));
3742 else
3743 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3744 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3745 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3746 }
3747}
3748
3749static void intel_enable_planes(struct drm_crtc *crtc)
3750{
3751 struct drm_device *dev = crtc->dev;
3752 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3753 struct drm_plane *plane;
3754 struct intel_plane *intel_plane;
3755
3756 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3757 intel_plane = to_intel_plane(plane);
3758 if (intel_plane->pipe == pipe)
3759 intel_plane_restore(&intel_plane->base);
3760 }
3761}
3762
3763static void intel_disable_planes(struct drm_crtc *crtc)
3764{
3765 struct drm_device *dev = crtc->dev;
3766 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3767 struct drm_plane *plane;
3768 struct intel_plane *intel_plane;
3769
3770 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3771 intel_plane = to_intel_plane(plane);
3772 if (intel_plane->pipe == pipe)
3773 intel_plane_disable(&intel_plane->base);
3774 }
3775}
3776
3777void hsw_enable_ips(struct intel_crtc *crtc)
3778{
3779 struct drm_device *dev = crtc->base.dev;
3780 struct drm_i915_private *dev_priv = dev->dev_private;
3781
3782 if (!crtc->config.ips_enabled)
3783 return;
3784
3785 /* We can only enable IPS after we enable a plane and wait for a vblank */
3786 intel_wait_for_vblank(dev, crtc->pipe);
3787
3788 assert_plane_enabled(dev_priv, crtc->plane);
3789 if (IS_BROADWELL(dev)) {
3790 mutex_lock(&dev_priv->rps.hw_lock);
3791 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3792 mutex_unlock(&dev_priv->rps.hw_lock);
3793 /* Quoting Art Runyan: "its not safe to expect any particular
3794 * value in IPS_CTL bit 31 after enabling IPS through the
3795 * mailbox." Moreover, the mailbox may return a bogus state,
3796 * so we need to just enable it and continue on.
3797 */
3798 } else {
3799 I915_WRITE(IPS_CTL, IPS_ENABLE);
3800 /* The bit only becomes 1 in the next vblank, so this wait here
3801 * is essentially intel_wait_for_vblank. If we don't have this
3802 * and don't wait for vblanks until the end of crtc_enable, then
3803 * the HW state readout code will complain that the expected
3804 * IPS_CTL value is not the one we read. */
3805 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3806 DRM_ERROR("Timed out waiting for IPS enable\n");
3807 }
3808}
3809
3810void hsw_disable_ips(struct intel_crtc *crtc)
3811{
3812 struct drm_device *dev = crtc->base.dev;
3813 struct drm_i915_private *dev_priv = dev->dev_private;
3814
3815 if (!crtc->config.ips_enabled)
3816 return;
3817
3818 assert_plane_enabled(dev_priv, crtc->plane);
3819 if (IS_BROADWELL(dev)) {
3820 mutex_lock(&dev_priv->rps.hw_lock);
3821 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3822 mutex_unlock(&dev_priv->rps.hw_lock);
3823 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3824 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3825 DRM_ERROR("Timed out waiting for IPS disable\n");
3826 } else {
3827 I915_WRITE(IPS_CTL, 0);
3828 POSTING_READ(IPS_CTL);
3829 }
3830
3831 /* We need to wait for a vblank before we can disable the plane. */
3832 intel_wait_for_vblank(dev, crtc->pipe);
3833}
3834
3835/** Loads the palette/gamma unit for the CRTC with the prepared values */
3836static void intel_crtc_load_lut(struct drm_crtc *crtc)
3837{
3838 struct drm_device *dev = crtc->dev;
3839 struct drm_i915_private *dev_priv = dev->dev_private;
3840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3841 enum pipe pipe = intel_crtc->pipe;
3842 int palreg = PALETTE(pipe);
3843 int i;
3844 bool reenable_ips = false;
3845
3846 /* The clocks have to be on to load the palette. */
3847 if (!crtc->enabled || !intel_crtc->active)
3848 return;
3849
3850 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3851 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3852 assert_dsi_pll_enabled(dev_priv);
3853 else
3854 assert_pll_enabled(dev_priv, pipe);
3855 }
3856
3857 /* use legacy palette for Ironlake */
3858 if (!HAS_GMCH_DISPLAY(dev))
3859 palreg = LGC_PALETTE(pipe);
3860
3861 /* Workaround : Do not read or write the pipe palette/gamma data while
3862 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3863 */
3864 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3865 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3866 GAMMA_MODE_MODE_SPLIT)) {
3867 hsw_disable_ips(intel_crtc);
3868 reenable_ips = true;
3869 }
3870
3871 for (i = 0; i < 256; i++) {
3872 I915_WRITE(palreg + 4 * i,
3873 (intel_crtc->lut_r[i] << 16) |
3874 (intel_crtc->lut_g[i] << 8) |
3875 intel_crtc->lut_b[i]);
3876 }
3877
3878 if (reenable_ips)
3879 hsw_enable_ips(intel_crtc);
3880}
3881
3882static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3883{
3884 if (!enable && intel_crtc->overlay) {
3885 struct drm_device *dev = intel_crtc->base.dev;
3886 struct drm_i915_private *dev_priv = dev->dev_private;
3887
3888 mutex_lock(&dev->struct_mutex);
3889 dev_priv->mm.interruptible = false;
3890 (void) intel_overlay_switch_off(intel_crtc->overlay);
3891 dev_priv->mm.interruptible = true;
3892 mutex_unlock(&dev->struct_mutex);
3893 }
3894
3895 /* Let userspace switch the overlay on again. In most cases userspace
3896 * has to recompute where to put it anyway.
3897 */
3898}
3899
3900static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3901{
3902 struct drm_device *dev = crtc->dev;
3903 struct drm_i915_private *dev_priv = dev->dev_private;
3904 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3905 int pipe = intel_crtc->pipe;
3906 int plane = intel_crtc->plane;
3907
3908 drm_vblank_on(dev, pipe);
3909
3910 intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3911 intel_enable_planes(crtc);
3912 intel_crtc_update_cursor(crtc, true);
3913 intel_crtc_dpms_overlay(intel_crtc, true);
3914
3915 hsw_enable_ips(intel_crtc);
3916
3917 mutex_lock(&dev->struct_mutex);
3918 intel_update_fbc(dev);
3919 mutex_unlock(&dev->struct_mutex);
3920
3921 /*
3922 * FIXME: Once we grow proper nuclear flip support out of this we need
3923 * to compute the mask of flip planes precisely. For the time being
3924 * consider this a flip from a NULL plane.
3925 */
3926 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3927}
3928
3929static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3930{
3931 struct drm_device *dev = crtc->dev;
3932 struct drm_i915_private *dev_priv = dev->dev_private;
3933 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3934 int pipe = intel_crtc->pipe;
3935 int plane = intel_crtc->plane;
3936
3937 intel_crtc_wait_for_pending_flips(crtc);
3938
3939 if (dev_priv->fbc.plane == plane)
3940 intel_disable_fbc(dev);
3941
3942 hsw_disable_ips(intel_crtc);
3943
3944 intel_crtc_dpms_overlay(intel_crtc, false);
3945 intel_crtc_update_cursor(crtc, false);
3946 intel_disable_planes(crtc);
3947 intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3948
3949 /*
3950 * FIXME: Once we grow proper nuclear flip support out of this we need
3951 * to compute the mask of flip planes precisely. For the time being
3952 * consider this a flip to a NULL plane.
3953 */
3954 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3955
3956 drm_vblank_off(dev, pipe);
3957}
3958
3959static void ironlake_crtc_enable(struct drm_crtc *crtc)
3960{
3961 struct drm_device *dev = crtc->dev;
3962 struct drm_i915_private *dev_priv = dev->dev_private;
3963 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3964 struct intel_encoder *encoder;
3965 int pipe = intel_crtc->pipe;
3966 enum plane plane = intel_crtc->plane;
3967
3968 WARN_ON(!crtc->enabled);
3969
3970 if (intel_crtc->active)
3971 return;
3972
3973 if (intel_crtc->config.has_pch_encoder)
3974 intel_prepare_shared_dpll(intel_crtc);
3975
3976 if (intel_crtc->config.has_dp_encoder)
3977 intel_dp_set_m_n(intel_crtc);
3978
3979 intel_set_pipe_timings(intel_crtc);
3980
3981 if (intel_crtc->config.has_pch_encoder) {
3982 intel_cpu_transcoder_set_m_n(intel_crtc,
3983 &intel_crtc->config.fdi_m_n);
3984 }
3985
3986 ironlake_set_pipeconf(crtc);
3987
3988 /* Set up the display plane register */
3989 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
3990 POSTING_READ(DSPCNTR(plane));
3991
3992 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
3993 crtc->x, crtc->y);
3994
3995 intel_crtc->active = true;
3996
3997 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3998 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3999
4000 for_each_encoder_on_crtc(dev, crtc, encoder)
4001 if (encoder->pre_enable)
4002 encoder->pre_enable(encoder);
4003
4004 if (intel_crtc->config.has_pch_encoder) {
4005 /* Note: FDI PLL enabling _must_ be done before we enable the
4006 * cpu pipes, hence this is separate from all the other fdi/pch
4007 * enabling. */
4008 ironlake_fdi_pll_enable(intel_crtc);
4009 } else {
4010 assert_fdi_tx_disabled(dev_priv, pipe);
4011 assert_fdi_rx_disabled(dev_priv, pipe);
4012 }
4013
4014 ironlake_pfit_enable(intel_crtc);
4015
4016 /*
4017 * On ILK+ LUT must be loaded before the pipe is running but with
4018 * clocks enabled
4019 */
4020 intel_crtc_load_lut(crtc);
4021
4022 intel_update_watermarks(crtc);
4023 intel_enable_pipe(intel_crtc);
4024
4025 if (intel_crtc->config.has_pch_encoder)
4026 ironlake_pch_enable(crtc);
4027
4028 for_each_encoder_on_crtc(dev, crtc, encoder)
4029 encoder->enable(encoder);
4030
4031 if (HAS_PCH_CPT(dev))
4032 cpt_verify_modeset(dev, intel_crtc->pipe);
4033
4034 intel_crtc_enable_planes(crtc);
4035}
4036
4037/* IPS only exists on ULT machines and is tied to pipe A. */
4038static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4039{
4040 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4041}
4042
4043/*
4044 * This implements the workaround described in the "notes" section of the mode
4045 * set sequence documentation. When going from no pipes or single pipe to
4046 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4047 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4048 */
4049static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4050{
4051 struct drm_device *dev = crtc->base.dev;
4052 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4053
4054 /* We want to get the other_active_crtc only if there's only 1 other
4055 * active crtc. */
4056 for_each_intel_crtc(dev, crtc_it) {
4057 if (!crtc_it->active || crtc_it == crtc)
4058 continue;
4059
4060 if (other_active_crtc)
4061 return;
4062
4063 other_active_crtc = crtc_it;
4064 }
4065 if (!other_active_crtc)
4066 return;
4067
4068 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4069 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4070}
4071
4072static void haswell_crtc_enable(struct drm_crtc *crtc)
4073{
4074 struct drm_device *dev = crtc->dev;
4075 struct drm_i915_private *dev_priv = dev->dev_private;
4076 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4077 struct intel_encoder *encoder;
4078 int pipe = intel_crtc->pipe;
4079 enum plane plane = intel_crtc->plane;
4080
4081 WARN_ON(!crtc->enabled);
4082
4083 if (intel_crtc->active)
4084 return;
4085
4086 if (intel_crtc_to_shared_dpll(intel_crtc))
4087 intel_enable_shared_dpll(intel_crtc);
4088
4089 if (intel_crtc->config.has_dp_encoder)
4090 intel_dp_set_m_n(intel_crtc);
4091
4092 intel_set_pipe_timings(intel_crtc);
4093
4094 if (intel_crtc->config.has_pch_encoder) {
4095 intel_cpu_transcoder_set_m_n(intel_crtc,
4096 &intel_crtc->config.fdi_m_n);
4097 }
4098
4099 haswell_set_pipeconf(crtc);
4100
4101 intel_set_pipe_csc(crtc);
4102
4103 /* Set up the display plane register */
4104 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
4105 POSTING_READ(DSPCNTR(plane));
4106
4107 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4108 crtc->x, crtc->y);
4109
4110 intel_crtc->active = true;
4111
4112 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4113 for_each_encoder_on_crtc(dev, crtc, encoder)
4114 if (encoder->pre_enable)
4115 encoder->pre_enable(encoder);
4116
4117 if (intel_crtc->config.has_pch_encoder) {
4118 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4119 dev_priv->display.fdi_link_train(crtc);
4120 }
4121
4122 intel_ddi_enable_pipe_clock(intel_crtc);
4123
4124 ironlake_pfit_enable(intel_crtc);
4125
4126 /*
4127 * On ILK+ LUT must be loaded before the pipe is running but with
4128 * clocks enabled
4129 */
4130 intel_crtc_load_lut(crtc);
4131
4132 intel_ddi_set_pipe_settings(crtc);
4133 intel_ddi_enable_transcoder_func(crtc);
4134
4135 intel_update_watermarks(crtc);
4136 intel_enable_pipe(intel_crtc);
4137
4138 if (intel_crtc->config.has_pch_encoder)
4139 lpt_pch_enable(crtc);
4140
4141 if (intel_crtc->config.dp_encoder_is_mst)
4142 intel_ddi_set_vc_payload_alloc(crtc, true);
4143
4144 for_each_encoder_on_crtc(dev, crtc, encoder) {
4145 encoder->enable(encoder);
4146 intel_opregion_notify_encoder(encoder, true);
4147 }
4148
4149 /* If we change the relative order between pipe/planes enabling, we need
4150 * to change the workaround. */
4151 haswell_mode_set_planes_workaround(intel_crtc);
4152 intel_crtc_enable_planes(crtc);
4153}
4154
4155static void ironlake_pfit_disable(struct intel_crtc *crtc)
4156{
4157 struct drm_device *dev = crtc->base.dev;
4158 struct drm_i915_private *dev_priv = dev->dev_private;
4159 int pipe = crtc->pipe;
4160
4161 /* To avoid upsetting the power well on haswell only disable the pfit if
4162 * it's in use. The hw state code will make sure we get this right. */
4163 if (crtc->config.pch_pfit.enabled) {
4164 I915_WRITE(PF_CTL(pipe), 0);
4165 I915_WRITE(PF_WIN_POS(pipe), 0);
4166 I915_WRITE(PF_WIN_SZ(pipe), 0);
4167 }
4168}
4169
4170static void ironlake_crtc_disable(struct drm_crtc *crtc)
4171{
4172 struct drm_device *dev = crtc->dev;
4173 struct drm_i915_private *dev_priv = dev->dev_private;
4174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4175 struct intel_encoder *encoder;
4176 int pipe = intel_crtc->pipe;
4177 u32 reg, temp;
4178
4179 if (!intel_crtc->active)
4180 return;
4181
4182 intel_crtc_disable_planes(crtc);
4183
4184 for_each_encoder_on_crtc(dev, crtc, encoder)
4185 encoder->disable(encoder);
4186
4187 if (intel_crtc->config.has_pch_encoder)
4188 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4189
4190 intel_disable_pipe(dev_priv, pipe);
4191
4192 if (intel_crtc->config.dp_encoder_is_mst)
4193 intel_ddi_set_vc_payload_alloc(crtc, false);
4194
4195 ironlake_pfit_disable(intel_crtc);
4196
4197 for_each_encoder_on_crtc(dev, crtc, encoder)
4198 if (encoder->post_disable)
4199 encoder->post_disable(encoder);
4200
4201 if (intel_crtc->config.has_pch_encoder) {
4202 ironlake_fdi_disable(crtc);
4203
4204 ironlake_disable_pch_transcoder(dev_priv, pipe);
4205 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4206
4207 if (HAS_PCH_CPT(dev)) {
4208 /* disable TRANS_DP_CTL */
4209 reg = TRANS_DP_CTL(pipe);
4210 temp = I915_READ(reg);
4211 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4212 TRANS_DP_PORT_SEL_MASK);
4213 temp |= TRANS_DP_PORT_SEL_NONE;
4214 I915_WRITE(reg, temp);
4215
4216 /* disable DPLL_SEL */
4217 temp = I915_READ(PCH_DPLL_SEL);
4218 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4219 I915_WRITE(PCH_DPLL_SEL, temp);
4220 }
4221
4222 /* disable PCH DPLL */
4223 intel_disable_shared_dpll(intel_crtc);
4224
4225 ironlake_fdi_pll_disable(intel_crtc);
4226 }
4227
4228 intel_crtc->active = false;
4229 intel_update_watermarks(crtc);
4230
4231 mutex_lock(&dev->struct_mutex);
4232 intel_update_fbc(dev);
4233 mutex_unlock(&dev->struct_mutex);
4234}
4235
4236static void haswell_crtc_disable(struct drm_crtc *crtc)
4237{
4238 struct drm_device *dev = crtc->dev;
4239 struct drm_i915_private *dev_priv = dev->dev_private;
4240 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4241 struct intel_encoder *encoder;
4242 int pipe = intel_crtc->pipe;
4243 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4244
4245 if (!intel_crtc->active)
4246 return;
4247
4248 intel_crtc_disable_planes(crtc);
4249
4250 for_each_encoder_on_crtc(dev, crtc, encoder) {
4251 intel_opregion_notify_encoder(encoder, false);
4252 encoder->disable(encoder);
4253 }
4254
4255 if (intel_crtc->config.has_pch_encoder)
4256 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4257 intel_disable_pipe(dev_priv, pipe);
4258
4259 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4260
4261 ironlake_pfit_disable(intel_crtc);
4262
4263 intel_ddi_disable_pipe_clock(intel_crtc);
4264
4265 if (intel_crtc->config.has_pch_encoder) {
4266 lpt_disable_pch_transcoder(dev_priv);
4267 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4268 intel_ddi_fdi_disable(crtc);
4269 }
4270
4271 for_each_encoder_on_crtc(dev, crtc, encoder)
4272 if (encoder->post_disable)
4273 encoder->post_disable(encoder);
4274
4275 intel_crtc->active = false;
4276 intel_update_watermarks(crtc);
4277
4278 mutex_lock(&dev->struct_mutex);
4279 intel_update_fbc(dev);
4280 mutex_unlock(&dev->struct_mutex);
4281
4282 if (intel_crtc_to_shared_dpll(intel_crtc))
4283 intel_disable_shared_dpll(intel_crtc);
4284}
4285
4286static void ironlake_crtc_off(struct drm_crtc *crtc)
4287{
4288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4289 intel_put_shared_dpll(intel_crtc);
4290}
4291
4292
4293static void i9xx_pfit_enable(struct intel_crtc *crtc)
4294{
4295 struct drm_device *dev = crtc->base.dev;
4296 struct drm_i915_private *dev_priv = dev->dev_private;
4297 struct intel_crtc_config *pipe_config = &crtc->config;
4298
4299 if (!crtc->config.gmch_pfit.control)
4300 return;
4301
4302 /*
4303 * The panel fitter should only be adjusted whilst the pipe is disabled,
4304 * according to register description and PRM.
4305 */
4306 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4307 assert_pipe_disabled(dev_priv, crtc->pipe);
4308
4309 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4310 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4311
4312 /* Border color in case we don't scale up to the full screen. Black by
4313 * default, change to something else for debugging. */
4314 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4315}
4316
4317static enum intel_display_power_domain port_to_power_domain(enum port port)
4318{
4319 switch (port) {
4320 case PORT_A:
4321 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4322 case PORT_B:
4323 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4324 case PORT_C:
4325 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4326 case PORT_D:
4327 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4328 default:
4329 WARN_ON_ONCE(1);
4330 return POWER_DOMAIN_PORT_OTHER;
4331 }
4332}
4333
4334#define for_each_power_domain(domain, mask) \
4335 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4336 if ((1 << (domain)) & (mask))
4337
4338enum intel_display_power_domain
4339intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4340{
4341 struct drm_device *dev = intel_encoder->base.dev;
4342 struct intel_digital_port *intel_dig_port;
4343
4344 switch (intel_encoder->type) {
4345 case INTEL_OUTPUT_UNKNOWN:
4346 /* Only DDI platforms should ever use this output type */
4347 WARN_ON_ONCE(!HAS_DDI(dev));
4348 case INTEL_OUTPUT_DISPLAYPORT:
4349 case INTEL_OUTPUT_HDMI:
4350 case INTEL_OUTPUT_EDP:
4351 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4352 return port_to_power_domain(intel_dig_port->port);
4353 case INTEL_OUTPUT_DP_MST:
4354 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4355 return port_to_power_domain(intel_dig_port->port);
4356 case INTEL_OUTPUT_ANALOG:
4357 return POWER_DOMAIN_PORT_CRT;
4358 case INTEL_OUTPUT_DSI:
4359 return POWER_DOMAIN_PORT_DSI;
4360 default:
4361 return POWER_DOMAIN_PORT_OTHER;
4362 }
4363}
4364
4365static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4366{
4367 struct drm_device *dev = crtc->dev;
4368 struct intel_encoder *intel_encoder;
4369 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4370 enum pipe pipe = intel_crtc->pipe;
4371 unsigned long mask;
4372 enum transcoder transcoder;
4373
4374 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4375
4376 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4377 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4378 if (intel_crtc->config.pch_pfit.enabled ||
4379 intel_crtc->config.pch_pfit.force_thru)
4380 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4381
4382 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4383 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4384
4385 return mask;
4386}
4387
4388void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4389 bool enable)
4390{
4391 if (dev_priv->power_domains.init_power_on == enable)
4392 return;
4393
4394 if (enable)
4395 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4396 else
4397 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4398
4399 dev_priv->power_domains.init_power_on = enable;
4400}
4401
4402static void modeset_update_crtc_power_domains(struct drm_device *dev)
4403{
4404 struct drm_i915_private *dev_priv = dev->dev_private;
4405 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4406 struct intel_crtc *crtc;
4407
4408 /*
4409 * First get all needed power domains, then put all unneeded, to avoid
4410 * any unnecessary toggling of the power wells.
4411 */
4412 for_each_intel_crtc(dev, crtc) {
4413 enum intel_display_power_domain domain;
4414
4415 if (!crtc->base.enabled)
4416 continue;
4417
4418 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4419
4420 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4421 intel_display_power_get(dev_priv, domain);
4422 }
4423
4424 for_each_intel_crtc(dev, crtc) {
4425 enum intel_display_power_domain domain;
4426
4427 for_each_power_domain(domain, crtc->enabled_power_domains)
4428 intel_display_power_put(dev_priv, domain);
4429
4430 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4431 }
4432
4433 intel_display_set_init_power(dev_priv, false);
4434}
4435
4436/* returns HPLL frequency in kHz */
4437static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4438{
4439 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4440
4441 /* Obtain SKU information */
4442 mutex_lock(&dev_priv->dpio_lock);
4443 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4444 CCK_FUSE_HPLL_FREQ_MASK;
4445 mutex_unlock(&dev_priv->dpio_lock);
4446
4447 return vco_freq[hpll_freq] * 1000;
4448}
4449
4450static void vlv_update_cdclk(struct drm_device *dev)
4451{
4452 struct drm_i915_private *dev_priv = dev->dev_private;
4453
4454 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4455 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4456 dev_priv->vlv_cdclk_freq);
4457
4458 /*
4459 * Program the gmbus_freq based on the cdclk frequency.
4460 * BSpec erroneously claims we should aim for 4MHz, but
4461 * in fact 1MHz is the correct frequency.
4462 */
4463 I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4464}
4465
4466/* Adjust CDclk dividers to allow high res or save power if possible */
4467static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4468{
4469 struct drm_i915_private *dev_priv = dev->dev_private;
4470 u32 val, cmd;
4471
4472 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4473
4474 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4475 cmd = 2;
4476 else if (cdclk == 266667)
4477 cmd = 1;
4478 else
4479 cmd = 0;
4480
4481 mutex_lock(&dev_priv->rps.hw_lock);
4482 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4483 val &= ~DSPFREQGUAR_MASK;
4484 val |= (cmd << DSPFREQGUAR_SHIFT);
4485 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4486 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4487 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4488 50)) {
4489 DRM_ERROR("timed out waiting for CDclk change\n");
4490 }
4491 mutex_unlock(&dev_priv->rps.hw_lock);
4492
4493 if (cdclk == 400000) {
4494 u32 divider, vco;
4495
4496 vco = valleyview_get_vco(dev_priv);
4497 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4498
4499 mutex_lock(&dev_priv->dpio_lock);
4500 /* adjust cdclk divider */
4501 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4502 val &= ~DISPLAY_FREQUENCY_VALUES;
4503 val |= divider;
4504 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4505
4506 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4507 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4508 50))
4509 DRM_ERROR("timed out waiting for CDclk change\n");
4510 mutex_unlock(&dev_priv->dpio_lock);
4511 }
4512
4513 mutex_lock(&dev_priv->dpio_lock);
4514 /* adjust self-refresh exit latency value */
4515 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4516 val &= ~0x7f;
4517
4518 /*
4519 * For high bandwidth configs, we set a higher latency in the bunit
4520 * so that the core display fetch happens in time to avoid underruns.
4521 */
4522 if (cdclk == 400000)
4523 val |= 4500 / 250; /* 4.5 usec */
4524 else
4525 val |= 3000 / 250; /* 3.0 usec */
4526 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4527 mutex_unlock(&dev_priv->dpio_lock);
4528
4529 vlv_update_cdclk(dev);
4530}
4531
4532static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4533 int max_pixclk)
4534{
4535 int vco = valleyview_get_vco(dev_priv);
4536 int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000;
4537
4538 /*
4539 * Really only a few cases to deal with, as only 4 CDclks are supported:
4540 * 200MHz
4541 * 267MHz
4542 * 320/333MHz (depends on HPLL freq)
4543 * 400MHz
4544 * So we check to see whether we're above 90% of the lower bin and
4545 * adjust if needed.
4546 *
4547 * We seem to get an unstable or solid color picture at 200MHz.
4548 * Not sure what's wrong. For now use 200MHz only when all pipes
4549 * are off.
4550 */
4551 if (max_pixclk > freq_320*9/10)
4552 return 400000;
4553 else if (max_pixclk > 266667*9/10)
4554 return freq_320;
4555 else if (max_pixclk > 0)
4556 return 266667;
4557 else
4558 return 200000;
4559}
4560
4561/* compute the max pixel clock for new configuration */
4562static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4563{
4564 struct drm_device *dev = dev_priv->dev;
4565 struct intel_crtc *intel_crtc;
4566 int max_pixclk = 0;
4567
4568 for_each_intel_crtc(dev, intel_crtc) {
4569 if (intel_crtc->new_enabled)
4570 max_pixclk = max(max_pixclk,
4571 intel_crtc->new_config->adjusted_mode.crtc_clock);
4572 }
4573
4574 return max_pixclk;
4575}
4576
4577static void valleyview_modeset_global_pipes(struct drm_device *dev,
4578 unsigned *prepare_pipes)
4579{
4580 struct drm_i915_private *dev_priv = dev->dev_private;
4581 struct intel_crtc *intel_crtc;
4582 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4583
4584 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4585 dev_priv->vlv_cdclk_freq)
4586 return;
4587
4588 /* disable/enable all currently active pipes while we change cdclk */
4589 for_each_intel_crtc(dev, intel_crtc)
4590 if (intel_crtc->base.enabled)
4591 *prepare_pipes |= (1 << intel_crtc->pipe);
4592}
4593
4594static void valleyview_modeset_global_resources(struct drm_device *dev)
4595{
4596 struct drm_i915_private *dev_priv = dev->dev_private;
4597 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4598 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4599
4600 if (req_cdclk != dev_priv->vlv_cdclk_freq)
4601 valleyview_set_cdclk(dev, req_cdclk);
4602 modeset_update_crtc_power_domains(dev);
4603}
4604
4605static void valleyview_crtc_enable(struct drm_crtc *crtc)
4606{
4607 struct drm_device *dev = crtc->dev;
4608 struct drm_i915_private *dev_priv = dev->dev_private;
4609 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4610 struct intel_encoder *encoder;
4611 int pipe = intel_crtc->pipe;
4612 int plane = intel_crtc->plane;
4613 bool is_dsi;
4614 u32 dspcntr;
4615
4616 WARN_ON(!crtc->enabled);
4617
4618 if (intel_crtc->active)
4619 return;
4620
4621 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4622
4623 if (!is_dsi && !IS_CHERRYVIEW(dev))
4624 vlv_prepare_pll(intel_crtc);
4625
4626 /* Set up the display plane register */
4627 dspcntr = DISPPLANE_GAMMA_ENABLE;
4628
4629 if (intel_crtc->config.has_dp_encoder)
4630 intel_dp_set_m_n(intel_crtc);
4631
4632 intel_set_pipe_timings(intel_crtc);
4633
4634 /* pipesrc and dspsize control the size that is scaled from,
4635 * which should always be the user's requested size.
4636 */
4637 I915_WRITE(DSPSIZE(plane),
4638 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4639 (intel_crtc->config.pipe_src_w - 1));
4640 I915_WRITE(DSPPOS(plane), 0);
4641
4642 i9xx_set_pipeconf(intel_crtc);
4643
4644 I915_WRITE(DSPCNTR(plane), dspcntr);
4645 POSTING_READ(DSPCNTR(plane));
4646
4647 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4648 crtc->x, crtc->y);
4649
4650 intel_crtc->active = true;
4651
4652 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4653
4654 for_each_encoder_on_crtc(dev, crtc, encoder)
4655 if (encoder->pre_pll_enable)
4656 encoder->pre_pll_enable(encoder);
4657
4658 if (!is_dsi) {
4659 if (IS_CHERRYVIEW(dev))
4660 chv_enable_pll(intel_crtc);
4661 else
4662 vlv_enable_pll(intel_crtc);
4663 }
4664
4665 for_each_encoder_on_crtc(dev, crtc, encoder)
4666 if (encoder->pre_enable)
4667 encoder->pre_enable(encoder);
4668
4669 i9xx_pfit_enable(intel_crtc);
4670
4671 intel_crtc_load_lut(crtc);
4672
4673 intel_update_watermarks(crtc);
4674 intel_enable_pipe(intel_crtc);
4675
4676 for_each_encoder_on_crtc(dev, crtc, encoder)
4677 encoder->enable(encoder);
4678
4679 intel_crtc_enable_planes(crtc);
4680
4681 /* Underruns don't raise interrupts, so check manually. */
4682 i9xx_check_fifo_underruns(dev);
4683}
4684
4685static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4686{
4687 struct drm_device *dev = crtc->base.dev;
4688 struct drm_i915_private *dev_priv = dev->dev_private;
4689
4690 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4691 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4692}
4693
4694static void i9xx_crtc_enable(struct drm_crtc *crtc)
4695{
4696 struct drm_device *dev = crtc->dev;
4697 struct drm_i915_private *dev_priv = dev->dev_private;
4698 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4699 struct intel_encoder *encoder;
4700 int pipe = intel_crtc->pipe;
4701 int plane = intel_crtc->plane;
4702 u32 dspcntr;
4703
4704 WARN_ON(!crtc->enabled);
4705
4706 if (intel_crtc->active)
4707 return;
4708
4709 i9xx_set_pll_dividers(intel_crtc);
4710
4711 /* Set up the display plane register */
4712 dspcntr = DISPPLANE_GAMMA_ENABLE;
4713
4714 if (pipe == 0)
4715 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4716 else
4717 dspcntr |= DISPPLANE_SEL_PIPE_B;
4718
4719 if (intel_crtc->config.has_dp_encoder)
4720 intel_dp_set_m_n(intel_crtc);
4721
4722 intel_set_pipe_timings(intel_crtc);
4723
4724 /* pipesrc and dspsize control the size that is scaled from,
4725 * which should always be the user's requested size.
4726 */
4727 I915_WRITE(DSPSIZE(plane),
4728 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4729 (intel_crtc->config.pipe_src_w - 1));
4730 I915_WRITE(DSPPOS(plane), 0);
4731
4732 i9xx_set_pipeconf(intel_crtc);
4733
4734 I915_WRITE(DSPCNTR(plane), dspcntr);
4735 POSTING_READ(DSPCNTR(plane));
4736
4737 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4738 crtc->x, crtc->y);
4739
4740 intel_crtc->active = true;
4741
4742 if (!IS_GEN2(dev))
4743 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4744
4745 for_each_encoder_on_crtc(dev, crtc, encoder)
4746 if (encoder->pre_enable)
4747 encoder->pre_enable(encoder);
4748
4749 i9xx_enable_pll(intel_crtc);
4750
4751 i9xx_pfit_enable(intel_crtc);
4752
4753 intel_crtc_load_lut(crtc);
4754
4755 intel_update_watermarks(crtc);
4756 intel_enable_pipe(intel_crtc);
4757
4758 for_each_encoder_on_crtc(dev, crtc, encoder)
4759 encoder->enable(encoder);
4760
4761 intel_crtc_enable_planes(crtc);
4762
4763 /*
4764 * Gen2 reports pipe underruns whenever all planes are disabled.
4765 * So don't enable underrun reporting before at least some planes
4766 * are enabled.
4767 * FIXME: Need to fix the logic to work when we turn off all planes
4768 * but leave the pipe running.
4769 */
4770 if (IS_GEN2(dev))
4771 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4772
4773 /* Underruns don't raise interrupts, so check manually. */
4774 i9xx_check_fifo_underruns(dev);
4775}
4776
4777static void i9xx_pfit_disable(struct intel_crtc *crtc)
4778{
4779 struct drm_device *dev = crtc->base.dev;
4780 struct drm_i915_private *dev_priv = dev->dev_private;
4781
4782 if (!crtc->config.gmch_pfit.control)
4783 return;
4784
4785 assert_pipe_disabled(dev_priv, crtc->pipe);
4786
4787 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4788 I915_READ(PFIT_CONTROL));
4789 I915_WRITE(PFIT_CONTROL, 0);
4790}
4791
4792static void i9xx_crtc_disable(struct drm_crtc *crtc)
4793{
4794 struct drm_device *dev = crtc->dev;
4795 struct drm_i915_private *dev_priv = dev->dev_private;
4796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4797 struct intel_encoder *encoder;
4798 int pipe = intel_crtc->pipe;
4799
4800 if (!intel_crtc->active)
4801 return;
4802
4803 /*
4804 * Gen2 reports pipe underruns whenever all planes are disabled.
4805 * So diasble underrun reporting before all the planes get disabled.
4806 * FIXME: Need to fix the logic to work when we turn off all planes
4807 * but leave the pipe running.
4808 */
4809 if (IS_GEN2(dev))
4810 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4811
4812 /*
4813 * Vblank time updates from the shadow to live plane control register
4814 * are blocked if the memory self-refresh mode is active at that
4815 * moment. So to make sure the plane gets truly disabled, disable
4816 * first the self-refresh mode. The self-refresh enable bit in turn
4817 * will be checked/applied by the HW only at the next frame start
4818 * event which is after the vblank start event, so we need to have a
4819 * wait-for-vblank between disabling the plane and the pipe.
4820 */
4821 intel_set_memory_cxsr(dev_priv, false);
4822 intel_crtc_disable_planes(crtc);
4823
4824 for_each_encoder_on_crtc(dev, crtc, encoder)
4825 encoder->disable(encoder);
4826
4827 /*
4828 * On gen2 planes are double buffered but the pipe isn't, so we must
4829 * wait for planes to fully turn off before disabling the pipe.
4830 * We also need to wait on all gmch platforms because of the
4831 * self-refresh mode constraint explained above.
4832 */
4833 intel_wait_for_vblank(dev, pipe);
4834
4835 intel_disable_pipe(dev_priv, pipe);
4836
4837 i9xx_pfit_disable(intel_crtc);
4838
4839 for_each_encoder_on_crtc(dev, crtc, encoder)
4840 if (encoder->post_disable)
4841 encoder->post_disable(encoder);
4842
4843 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4844 if (IS_CHERRYVIEW(dev))
4845 chv_disable_pll(dev_priv, pipe);
4846 else if (IS_VALLEYVIEW(dev))
4847 vlv_disable_pll(dev_priv, pipe);
4848 else
4849 i9xx_disable_pll(dev_priv, pipe);
4850 }
4851
4852 if (!IS_GEN2(dev))
4853 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4854
4855 intel_crtc->active = false;
4856 intel_update_watermarks(crtc);
4857
4858 mutex_lock(&dev->struct_mutex);
4859 intel_update_fbc(dev);
4860 mutex_unlock(&dev->struct_mutex);
4861}
4862
4863static void i9xx_crtc_off(struct drm_crtc *crtc)
4864{
4865}
4866
4867static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4868 bool enabled)
4869{
4870 struct drm_device *dev = crtc->dev;
4871 struct drm_i915_master_private *master_priv;
4872 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4873 int pipe = intel_crtc->pipe;
4874
4875 if (!dev->primary->master)
4876 return;
4877
4878 master_priv = dev->primary->master->driver_priv;
4879 if (!master_priv->sarea_priv)
4880 return;
4881
4882 switch (pipe) {
4883 case 0:
4884 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4885 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4886 break;
4887 case 1:
4888 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4889 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4890 break;
4891 default:
4892 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4893 break;
4894 }
4895}
4896
4897/* Master function to enable/disable CRTC and corresponding power wells */
4898void intel_crtc_control(struct drm_crtc *crtc, bool enable)
4899{
4900 struct drm_device *dev = crtc->dev;
4901 struct drm_i915_private *dev_priv = dev->dev_private;
4902 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4903 enum intel_display_power_domain domain;
4904 unsigned long domains;
4905
4906 if (enable) {
4907 if (!intel_crtc->active) {
4908 domains = get_crtc_power_domains(crtc);
4909 for_each_power_domain(domain, domains)
4910 intel_display_power_get(dev_priv, domain);
4911 intel_crtc->enabled_power_domains = domains;
4912
4913 dev_priv->display.crtc_enable(crtc);
4914 }
4915 } else {
4916 if (intel_crtc->active) {
4917 dev_priv->display.crtc_disable(crtc);
4918
4919 domains = intel_crtc->enabled_power_domains;
4920 for_each_power_domain(domain, domains)
4921 intel_display_power_put(dev_priv, domain);
4922 intel_crtc->enabled_power_domains = 0;
4923 }
4924 }
4925}
4926
4927/**
4928 * Sets the power management mode of the pipe and plane.
4929 */
4930void intel_crtc_update_dpms(struct drm_crtc *crtc)
4931{
4932 struct drm_device *dev = crtc->dev;
4933 struct intel_encoder *intel_encoder;
4934 bool enable = false;
4935
4936 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4937 enable |= intel_encoder->connectors_active;
4938
4939 intel_crtc_control(crtc, enable);
4940
4941 intel_crtc_update_sarea(crtc, enable);
4942}
4943
4944static void intel_crtc_disable(struct drm_crtc *crtc)
4945{
4946 struct drm_device *dev = crtc->dev;
4947 struct drm_connector *connector;
4948 struct drm_i915_private *dev_priv = dev->dev_private;
4949 struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
4950 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4951
4952 /* crtc should still be enabled when we disable it. */
4953 WARN_ON(!crtc->enabled);
4954
4955 dev_priv->display.crtc_disable(crtc);
4956 intel_crtc_update_sarea(crtc, false);
4957 dev_priv->display.off(crtc);
4958
4959 if (crtc->primary->fb) {
4960 mutex_lock(&dev->struct_mutex);
4961 intel_unpin_fb_obj(old_obj);
4962 i915_gem_track_fb(old_obj, NULL,
4963 INTEL_FRONTBUFFER_PRIMARY(pipe));
4964 mutex_unlock(&dev->struct_mutex);
4965 crtc->primary->fb = NULL;
4966 }
4967
4968 /* Update computed state. */
4969 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4970 if (!connector->encoder || !connector->encoder->crtc)
4971 continue;
4972
4973 if (connector->encoder->crtc != crtc)
4974 continue;
4975
4976 connector->dpms = DRM_MODE_DPMS_OFF;
4977 to_intel_encoder(connector->encoder)->connectors_active = false;
4978 }
4979}
4980
4981void intel_encoder_destroy(struct drm_encoder *encoder)
4982{
4983 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4984
4985 drm_encoder_cleanup(encoder);
4986 kfree(intel_encoder);
4987}
4988
4989/* Simple dpms helper for encoders with just one connector, no cloning and only
4990 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4991 * state of the entire output pipe. */
4992static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4993{
4994 if (mode == DRM_MODE_DPMS_ON) {
4995 encoder->connectors_active = true;
4996
4997 intel_crtc_update_dpms(encoder->base.crtc);
4998 } else {
4999 encoder->connectors_active = false;
5000
5001 intel_crtc_update_dpms(encoder->base.crtc);
5002 }
5003}
5004
5005/* Cross check the actual hw state with our own modeset state tracking (and it's
5006 * internal consistency). */
5007static void intel_connector_check_state(struct intel_connector *connector)
5008{
5009 if (connector->get_hw_state(connector)) {
5010 struct intel_encoder *encoder = connector->encoder;
5011 struct drm_crtc *crtc;
5012 bool encoder_enabled;
5013 enum pipe pipe;
5014
5015 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5016 connector->base.base.id,
5017 connector->base.name);
5018
5019 /* there is no real hw state for MST connectors */
5020 if (connector->mst_port)
5021 return;
5022
5023 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5024 "wrong connector dpms state\n");
5025 WARN(connector->base.encoder != &encoder->base,
5026 "active connector not linked to encoder\n");
5027
5028 if (encoder) {
5029 WARN(!encoder->connectors_active,
5030 "encoder->connectors_active not set\n");
5031
5032 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5033 WARN(!encoder_enabled, "encoder not enabled\n");
5034 if (WARN_ON(!encoder->base.crtc))
5035 return;
5036
5037 crtc = encoder->base.crtc;
5038
5039 WARN(!crtc->enabled, "crtc not enabled\n");
5040 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5041 WARN(pipe != to_intel_crtc(crtc)->pipe,
5042 "encoder active on the wrong pipe\n");
5043 }
5044 }
5045}
5046
5047/* Even simpler default implementation, if there's really no special case to
5048 * consider. */
5049void intel_connector_dpms(struct drm_connector *connector, int mode)
5050{
5051 /* All the simple cases only support two dpms states. */
5052 if (mode != DRM_MODE_DPMS_ON)
5053 mode = DRM_MODE_DPMS_OFF;
5054
5055 if (mode == connector->dpms)
5056 return;
5057
5058 connector->dpms = mode;
5059
5060 /* Only need to change hw state when actually enabled */
5061 if (connector->encoder)
5062 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5063
5064 intel_modeset_check_state(connector->dev);
5065}
5066
5067/* Simple connector->get_hw_state implementation for encoders that support only
5068 * one connector and no cloning and hence the encoder state determines the state
5069 * of the connector. */
5070bool intel_connector_get_hw_state(struct intel_connector *connector)
5071{
5072 enum pipe pipe = 0;
5073 struct intel_encoder *encoder = connector->encoder;
5074
5075 return encoder->get_hw_state(encoder, &pipe);
5076}
5077
5078static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5079 struct intel_crtc_config *pipe_config)
5080{
5081 struct drm_i915_private *dev_priv = dev->dev_private;
5082 struct intel_crtc *pipe_B_crtc =
5083 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5084
5085 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5086 pipe_name(pipe), pipe_config->fdi_lanes);
5087 if (pipe_config->fdi_lanes > 4) {
5088 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5089 pipe_name(pipe), pipe_config->fdi_lanes);
5090 return false;
5091 }
5092
5093 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5094 if (pipe_config->fdi_lanes > 2) {
5095 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5096 pipe_config->fdi_lanes);
5097 return false;
5098 } else {
5099 return true;
5100 }
5101 }
5102
5103 if (INTEL_INFO(dev)->num_pipes == 2)
5104 return true;
5105
5106 /* Ivybridge 3 pipe is really complicated */
5107 switch (pipe) {
5108 case PIPE_A:
5109 return true;
5110 case PIPE_B:
5111 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5112 pipe_config->fdi_lanes > 2) {
5113 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5114 pipe_name(pipe), pipe_config->fdi_lanes);
5115 return false;
5116 }
5117 return true;
5118 case PIPE_C:
5119 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5120 pipe_B_crtc->config.fdi_lanes <= 2) {
5121 if (pipe_config->fdi_lanes > 2) {
5122 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5123 pipe_name(pipe), pipe_config->fdi_lanes);
5124 return false;
5125 }
5126 } else {
5127 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5128 return false;
5129 }
5130 return true;
5131 default:
5132 BUG();
5133 }
5134}
5135
5136#define RETRY 1
5137static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5138 struct intel_crtc_config *pipe_config)
5139{
5140 struct drm_device *dev = intel_crtc->base.dev;
5141 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5142 int lane, link_bw, fdi_dotclock;
5143 bool setup_ok, needs_recompute = false;
5144
5145retry:
5146 /* FDI is a binary signal running at ~2.7GHz, encoding
5147 * each output octet as 10 bits. The actual frequency
5148 * is stored as a divider into a 100MHz clock, and the
5149 * mode pixel clock is stored in units of 1KHz.
5150 * Hence the bw of each lane in terms of the mode signal
5151 * is:
5152 */
5153 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5154
5155 fdi_dotclock = adjusted_mode->crtc_clock;
5156
5157 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5158 pipe_config->pipe_bpp);
5159
5160 pipe_config->fdi_lanes = lane;
5161
5162 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5163 link_bw, &pipe_config->fdi_m_n);
5164
5165 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5166 intel_crtc->pipe, pipe_config);
5167 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5168 pipe_config->pipe_bpp -= 2*3;
5169 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5170 pipe_config->pipe_bpp);
5171 needs_recompute = true;
5172 pipe_config->bw_constrained = true;
5173
5174 goto retry;
5175 }
5176
5177 if (needs_recompute)
5178 return RETRY;
5179
5180 return setup_ok ? 0 : -EINVAL;
5181}
5182
5183static void hsw_compute_ips_config(struct intel_crtc *crtc,
5184 struct intel_crtc_config *pipe_config)
5185{
5186 pipe_config->ips_enabled = i915.enable_ips &&
5187 hsw_crtc_supports_ips(crtc) &&
5188 pipe_config->pipe_bpp <= 24;
5189}
5190
5191static int intel_crtc_compute_config(struct intel_crtc *crtc,
5192 struct intel_crtc_config *pipe_config)
5193{
5194 struct drm_device *dev = crtc->base.dev;
5195 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5196
5197 /* FIXME should check pixel clock limits on all platforms */
5198 if (INTEL_INFO(dev)->gen < 4) {
5199 struct drm_i915_private *dev_priv = dev->dev_private;
5200 int clock_limit =
5201 dev_priv->display.get_display_clock_speed(dev);
5202
5203 /*
5204 * Enable pixel doubling when the dot clock
5205 * is > 90% of the (display) core speed.
5206 *
5207 * GDG double wide on either pipe,
5208 * otherwise pipe A only.
5209 */
5210 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5211 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5212 clock_limit *= 2;
5213 pipe_config->double_wide = true;
5214 }
5215
5216 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5217 return -EINVAL;
5218 }
5219
5220 /*
5221 * Pipe horizontal size must be even in:
5222 * - DVO ganged mode
5223 * - LVDS dual channel mode
5224 * - Double wide pipe
5225 */
5226 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5227 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5228 pipe_config->pipe_src_w &= ~1;
5229
5230 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5231 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5232 */
5233 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5234 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5235 return -EINVAL;
5236
5237 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5238 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5239 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5240 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5241 * for lvds. */
5242 pipe_config->pipe_bpp = 8*3;
5243 }
5244
5245 if (HAS_IPS(dev))
5246 hsw_compute_ips_config(crtc, pipe_config);
5247
5248 /*
5249 * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5250 * old clock survives for now.
5251 */
5252 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
5253 pipe_config->shared_dpll = crtc->config.shared_dpll;
5254
5255 if (pipe_config->has_pch_encoder)
5256 return ironlake_fdi_compute_config(crtc, pipe_config);
5257
5258 return 0;
5259}
5260
5261static int valleyview_get_display_clock_speed(struct drm_device *dev)
5262{
5263 struct drm_i915_private *dev_priv = dev->dev_private;
5264 int vco = valleyview_get_vco(dev_priv);
5265 u32 val;
5266 int divider;
5267
5268 mutex_lock(&dev_priv->dpio_lock);
5269 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5270 mutex_unlock(&dev_priv->dpio_lock);
5271
5272 divider = val & DISPLAY_FREQUENCY_VALUES;
5273
5274 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5275 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5276 "cdclk change in progress\n");
5277
5278 return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5279}
5280
5281static int i945_get_display_clock_speed(struct drm_device *dev)
5282{
5283 return 400000;
5284}
5285
5286static int i915_get_display_clock_speed(struct drm_device *dev)
5287{
5288 return 333000;
5289}
5290
5291static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5292{
5293 return 200000;
5294}
5295
5296static int pnv_get_display_clock_speed(struct drm_device *dev)
5297{
5298 u16 gcfgc = 0;
5299
5300 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5301
5302 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5303 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5304 return 267000;
5305 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5306 return 333000;
5307 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5308 return 444000;
5309 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5310 return 200000;
5311 default:
5312 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5313 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5314 return 133000;
5315 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5316 return 167000;
5317 }
5318}
5319
5320static int i915gm_get_display_clock_speed(struct drm_device *dev)
5321{
5322 u16 gcfgc = 0;
5323
5324 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5325
5326 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5327 return 133000;
5328 else {
5329 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5330 case GC_DISPLAY_CLOCK_333_MHZ:
5331 return 333000;
5332 default:
5333 case GC_DISPLAY_CLOCK_190_200_MHZ:
5334 return 190000;
5335 }
5336 }
5337}
5338
5339static int i865_get_display_clock_speed(struct drm_device *dev)
5340{
5341 return 266000;
5342}
5343
5344static int i855_get_display_clock_speed(struct drm_device *dev)
5345{
5346 u16 hpllcc = 0;
5347 /* Assume that the hardware is in the high speed state. This
5348 * should be the default.
5349 */
5350 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5351 case GC_CLOCK_133_200:
5352 case GC_CLOCK_100_200:
5353 return 200000;
5354 case GC_CLOCK_166_250:
5355 return 250000;
5356 case GC_CLOCK_100_133:
5357 return 133000;
5358 }
5359
5360 /* Shouldn't happen */
5361 return 0;
5362}
5363
5364static int i830_get_display_clock_speed(struct drm_device *dev)
5365{
5366 return 133000;
5367}
5368
5369static void
5370intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5371{
5372 while (*num > DATA_LINK_M_N_MASK ||
5373 *den > DATA_LINK_M_N_MASK) {
5374 *num >>= 1;
5375 *den >>= 1;
5376 }
5377}
5378
5379static void compute_m_n(unsigned int m, unsigned int n,
5380 uint32_t *ret_m, uint32_t *ret_n)
5381{
5382 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5383 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5384 intel_reduce_m_n_ratio(ret_m, ret_n);
5385}
5386
5387void
5388intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5389 int pixel_clock, int link_clock,
5390 struct intel_link_m_n *m_n)
5391{
5392 m_n->tu = 64;
5393
5394 compute_m_n(bits_per_pixel * pixel_clock,
5395 link_clock * nlanes * 8,
5396 &m_n->gmch_m, &m_n->gmch_n);
5397
5398 compute_m_n(pixel_clock, link_clock,
5399 &m_n->link_m, &m_n->link_n);
5400}
5401
5402static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5403{
5404 if (i915.panel_use_ssc >= 0)
5405 return i915.panel_use_ssc != 0;
5406 return dev_priv->vbt.lvds_use_ssc
5407 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5408}
5409
5410static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5411{
5412 struct drm_device *dev = crtc->dev;
5413 struct drm_i915_private *dev_priv = dev->dev_private;
5414 int refclk;
5415
5416 if (IS_VALLEYVIEW(dev)) {
5417 refclk = 100000;
5418 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5419 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5420 refclk = dev_priv->vbt.lvds_ssc_freq;
5421 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5422 } else if (!IS_GEN2(dev)) {
5423 refclk = 96000;
5424 } else {
5425 refclk = 48000;
5426 }
5427
5428 return refclk;
5429}
5430
5431static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5432{
5433 return (1 << dpll->n) << 16 | dpll->m2;
5434}
5435
5436static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5437{
5438 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5439}
5440
5441static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5442 intel_clock_t *reduced_clock)
5443{
5444 struct drm_device *dev = crtc->base.dev;
5445 u32 fp, fp2 = 0;
5446
5447 if (IS_PINEVIEW(dev)) {
5448 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5449 if (reduced_clock)
5450 fp2 = pnv_dpll_compute_fp(reduced_clock);
5451 } else {
5452 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5453 if (reduced_clock)
5454 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5455 }
5456
5457 crtc->config.dpll_hw_state.fp0 = fp;
5458
5459 crtc->lowfreq_avail = false;
5460 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5461 reduced_clock && i915.powersave) {
5462 crtc->config.dpll_hw_state.fp1 = fp2;
5463 crtc->lowfreq_avail = true;
5464 } else {
5465 crtc->config.dpll_hw_state.fp1 = fp;
5466 }
5467}
5468
5469static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5470 pipe)
5471{
5472 u32 reg_val;
5473
5474 /*
5475 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5476 * and set it to a reasonable value instead.
5477 */
5478 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5479 reg_val &= 0xffffff00;
5480 reg_val |= 0x00000030;
5481 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5482
5483 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5484 reg_val &= 0x8cffffff;
5485 reg_val = 0x8c000000;
5486 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5487
5488 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5489 reg_val &= 0xffffff00;
5490 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5491
5492 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5493 reg_val &= 0x00ffffff;
5494 reg_val |= 0xb0000000;
5495 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5496}
5497
5498static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5499 struct intel_link_m_n *m_n)
5500{
5501 struct drm_device *dev = crtc->base.dev;
5502 struct drm_i915_private *dev_priv = dev->dev_private;
5503 int pipe = crtc->pipe;
5504
5505 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5506 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5507 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5508 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5509}
5510
5511static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5512 struct intel_link_m_n *m_n)
5513{
5514 struct drm_device *dev = crtc->base.dev;
5515 struct drm_i915_private *dev_priv = dev->dev_private;
5516 int pipe = crtc->pipe;
5517 enum transcoder transcoder = crtc->config.cpu_transcoder;
5518
5519 if (INTEL_INFO(dev)->gen >= 5) {
5520 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5521 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5522 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5523 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5524 } else {
5525 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5526 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5527 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5528 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5529 }
5530}
5531
5532static void intel_dp_set_m_n(struct intel_crtc *crtc)
5533{
5534 if (crtc->config.has_pch_encoder)
5535 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5536 else
5537 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5538}
5539
5540static void vlv_update_pll(struct intel_crtc *crtc)
5541{
5542 u32 dpll, dpll_md;
5543
5544 /*
5545 * Enable DPIO clock input. We should never disable the reference
5546 * clock for pipe B, since VGA hotplug / manual detection depends
5547 * on it.
5548 */
5549 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5550 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5551 /* We should never disable this, set it here for state tracking */
5552 if (crtc->pipe == PIPE_B)
5553 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5554 dpll |= DPLL_VCO_ENABLE;
5555 crtc->config.dpll_hw_state.dpll = dpll;
5556
5557 dpll_md = (crtc->config.pixel_multiplier - 1)
5558 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5559 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5560}
5561
5562static void vlv_prepare_pll(struct intel_crtc *crtc)
5563{
5564 struct drm_device *dev = crtc->base.dev;
5565 struct drm_i915_private *dev_priv = dev->dev_private;
5566 int pipe = crtc->pipe;
5567 u32 mdiv;
5568 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5569 u32 coreclk, reg_val;
5570
5571 mutex_lock(&dev_priv->dpio_lock);
5572
5573 bestn = crtc->config.dpll.n;
5574 bestm1 = crtc->config.dpll.m1;
5575 bestm2 = crtc->config.dpll.m2;
5576 bestp1 = crtc->config.dpll.p1;
5577 bestp2 = crtc->config.dpll.p2;
5578
5579 /* See eDP HDMI DPIO driver vbios notes doc */
5580
5581 /* PLL B needs special handling */
5582 if (pipe == PIPE_B)
5583 vlv_pllb_recal_opamp(dev_priv, pipe);
5584
5585 /* Set up Tx target for periodic Rcomp update */
5586 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5587
5588 /* Disable target IRef on PLL */
5589 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5590 reg_val &= 0x00ffffff;
5591 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5592
5593 /* Disable fast lock */
5594 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5595
5596 /* Set idtafcrecal before PLL is enabled */
5597 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5598 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5599 mdiv |= ((bestn << DPIO_N_SHIFT));
5600 mdiv |= (1 << DPIO_K_SHIFT);
5601
5602 /*
5603 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5604 * but we don't support that).
5605 * Note: don't use the DAC post divider as it seems unstable.
5606 */
5607 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5608 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5609
5610 mdiv |= DPIO_ENABLE_CALIBRATION;
5611 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5612
5613 /* Set HBR and RBR LPF coefficients */
5614 if (crtc->config.port_clock == 162000 ||
5615 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5616 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5617 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5618 0x009f0003);
5619 else
5620 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5621 0x00d0000f);
5622
5623 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5624 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5625 /* Use SSC source */
5626 if (pipe == PIPE_A)
5627 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5628 0x0df40000);
5629 else
5630 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5631 0x0df70000);
5632 } else { /* HDMI or VGA */
5633 /* Use bend source */
5634 if (pipe == PIPE_A)
5635 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5636 0x0df70000);
5637 else
5638 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5639 0x0df40000);
5640 }
5641
5642 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5643 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5644 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5645 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5646 coreclk |= 0x01000000;
5647 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5648
5649 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5650 mutex_unlock(&dev_priv->dpio_lock);
5651}
5652
5653static void chv_update_pll(struct intel_crtc *crtc)
5654{
5655 struct drm_device *dev = crtc->base.dev;
5656 struct drm_i915_private *dev_priv = dev->dev_private;
5657 int pipe = crtc->pipe;
5658 int dpll_reg = DPLL(crtc->pipe);
5659 enum dpio_channel port = vlv_pipe_to_channel(pipe);
5660 u32 loopfilter, intcoeff;
5661 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5662 int refclk;
5663
5664 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5665 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5666 DPLL_VCO_ENABLE;
5667 if (pipe != PIPE_A)
5668 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5669
5670 crtc->config.dpll_hw_state.dpll_md =
5671 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5672
5673 bestn = crtc->config.dpll.n;
5674 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5675 bestm1 = crtc->config.dpll.m1;
5676 bestm2 = crtc->config.dpll.m2 >> 22;
5677 bestp1 = crtc->config.dpll.p1;
5678 bestp2 = crtc->config.dpll.p2;
5679
5680 /*
5681 * Enable Refclk and SSC
5682 */
5683 I915_WRITE(dpll_reg,
5684 crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5685
5686 mutex_lock(&dev_priv->dpio_lock);
5687
5688 /* p1 and p2 divider */
5689 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5690 5 << DPIO_CHV_S1_DIV_SHIFT |
5691 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5692 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5693 1 << DPIO_CHV_K_DIV_SHIFT);
5694
5695 /* Feedback post-divider - m2 */
5696 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5697
5698 /* Feedback refclk divider - n and m1 */
5699 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5700 DPIO_CHV_M1_DIV_BY_2 |
5701 1 << DPIO_CHV_N_DIV_SHIFT);
5702
5703 /* M2 fraction division */
5704 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5705
5706 /* M2 fraction division enable */
5707 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5708 DPIO_CHV_FRAC_DIV_EN |
5709 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5710
5711 /* Loop filter */
5712 refclk = i9xx_get_refclk(&crtc->base, 0);
5713 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5714 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5715 if (refclk == 100000)
5716 intcoeff = 11;
5717 else if (refclk == 38400)
5718 intcoeff = 10;
5719 else
5720 intcoeff = 9;
5721 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5722 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5723
5724 /* AFC Recal */
5725 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5726 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5727 DPIO_AFC_RECAL);
5728
5729 mutex_unlock(&dev_priv->dpio_lock);
5730}
5731
5732static void i9xx_update_pll(struct intel_crtc *crtc,
5733 intel_clock_t *reduced_clock,
5734 int num_connectors)
5735{
5736 struct drm_device *dev = crtc->base.dev;
5737 struct drm_i915_private *dev_priv = dev->dev_private;
5738 u32 dpll;
5739 bool is_sdvo;
5740 struct dpll *clock = &crtc->config.dpll;
5741
5742 i9xx_update_pll_dividers(crtc, reduced_clock);
5743
5744 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5745 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5746
5747 dpll = DPLL_VGA_MODE_DIS;
5748
5749 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5750 dpll |= DPLLB_MODE_LVDS;
5751 else
5752 dpll |= DPLLB_MODE_DAC_SERIAL;
5753
5754 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5755 dpll |= (crtc->config.pixel_multiplier - 1)
5756 << SDVO_MULTIPLIER_SHIFT_HIRES;
5757 }
5758
5759 if (is_sdvo)
5760 dpll |= DPLL_SDVO_HIGH_SPEED;
5761
5762 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5763 dpll |= DPLL_SDVO_HIGH_SPEED;
5764
5765 /* compute bitmask from p1 value */
5766 if (IS_PINEVIEW(dev))
5767 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5768 else {
5769 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5770 if (IS_G4X(dev) && reduced_clock)
5771 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5772 }
5773 switch (clock->p2) {
5774 case 5:
5775 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5776 break;
5777 case 7:
5778 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5779 break;
5780 case 10:
5781 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5782 break;
5783 case 14:
5784 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5785 break;
5786 }
5787 if (INTEL_INFO(dev)->gen >= 4)
5788 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5789
5790 if (crtc->config.sdvo_tv_clock)
5791 dpll |= PLL_REF_INPUT_TVCLKINBC;
5792 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5793 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5794 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5795 else
5796 dpll |= PLL_REF_INPUT_DREFCLK;
5797
5798 dpll |= DPLL_VCO_ENABLE;
5799 crtc->config.dpll_hw_state.dpll = dpll;
5800
5801 if (INTEL_INFO(dev)->gen >= 4) {
5802 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5803 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5804 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5805 }
5806}
5807
5808static void i8xx_update_pll(struct intel_crtc *crtc,
5809 intel_clock_t *reduced_clock,
5810 int num_connectors)
5811{
5812 struct drm_device *dev = crtc->base.dev;
5813 struct drm_i915_private *dev_priv = dev->dev_private;
5814 u32 dpll;
5815 struct dpll *clock = &crtc->config.dpll;
5816
5817 i9xx_update_pll_dividers(crtc, reduced_clock);
5818
5819 dpll = DPLL_VGA_MODE_DIS;
5820
5821 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5822 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5823 } else {
5824 if (clock->p1 == 2)
5825 dpll |= PLL_P1_DIVIDE_BY_TWO;
5826 else
5827 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5828 if (clock->p2 == 4)
5829 dpll |= PLL_P2_DIVIDE_BY_4;
5830 }
5831
5832 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5833 dpll |= DPLL_DVO_2X_MODE;
5834
5835 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5836 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5837 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5838 else
5839 dpll |= PLL_REF_INPUT_DREFCLK;
5840
5841 dpll |= DPLL_VCO_ENABLE;
5842 crtc->config.dpll_hw_state.dpll = dpll;
5843}
5844
5845static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5846{
5847 struct drm_device *dev = intel_crtc->base.dev;
5848 struct drm_i915_private *dev_priv = dev->dev_private;
5849 enum pipe pipe = intel_crtc->pipe;
5850 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5851 struct drm_display_mode *adjusted_mode =
5852 &intel_crtc->config.adjusted_mode;
5853 uint32_t crtc_vtotal, crtc_vblank_end;
5854 int vsyncshift = 0;
5855
5856 /* We need to be careful not to changed the adjusted mode, for otherwise
5857 * the hw state checker will get angry at the mismatch. */
5858 crtc_vtotal = adjusted_mode->crtc_vtotal;
5859 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5860
5861 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5862 /* the chip adds 2 halflines automatically */
5863 crtc_vtotal -= 1;
5864 crtc_vblank_end -= 1;
5865
5866 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5867 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5868 else
5869 vsyncshift = adjusted_mode->crtc_hsync_start -
5870 adjusted_mode->crtc_htotal / 2;
5871 if (vsyncshift < 0)
5872 vsyncshift += adjusted_mode->crtc_htotal;
5873 }
5874
5875 if (INTEL_INFO(dev)->gen > 3)
5876 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5877
5878 I915_WRITE(HTOTAL(cpu_transcoder),
5879 (adjusted_mode->crtc_hdisplay - 1) |
5880 ((adjusted_mode->crtc_htotal - 1) << 16));
5881 I915_WRITE(HBLANK(cpu_transcoder),
5882 (adjusted_mode->crtc_hblank_start - 1) |
5883 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5884 I915_WRITE(HSYNC(cpu_transcoder),
5885 (adjusted_mode->crtc_hsync_start - 1) |
5886 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5887
5888 I915_WRITE(VTOTAL(cpu_transcoder),
5889 (adjusted_mode->crtc_vdisplay - 1) |
5890 ((crtc_vtotal - 1) << 16));
5891 I915_WRITE(VBLANK(cpu_transcoder),
5892 (adjusted_mode->crtc_vblank_start - 1) |
5893 ((crtc_vblank_end - 1) << 16));
5894 I915_WRITE(VSYNC(cpu_transcoder),
5895 (adjusted_mode->crtc_vsync_start - 1) |
5896 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5897
5898 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5899 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5900 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5901 * bits. */
5902 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5903 (pipe == PIPE_B || pipe == PIPE_C))
5904 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5905
5906 /* pipesrc controls the size that is scaled from, which should
5907 * always be the user's requested size.
5908 */
5909 I915_WRITE(PIPESRC(pipe),
5910 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5911 (intel_crtc->config.pipe_src_h - 1));
5912}
5913
5914static void intel_get_pipe_timings(struct intel_crtc *crtc,
5915 struct intel_crtc_config *pipe_config)
5916{
5917 struct drm_device *dev = crtc->base.dev;
5918 struct drm_i915_private *dev_priv = dev->dev_private;
5919 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5920 uint32_t tmp;
5921
5922 tmp = I915_READ(HTOTAL(cpu_transcoder));
5923 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5924 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5925 tmp = I915_READ(HBLANK(cpu_transcoder));
5926 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5927 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5928 tmp = I915_READ(HSYNC(cpu_transcoder));
5929 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5930 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5931
5932 tmp = I915_READ(VTOTAL(cpu_transcoder));
5933 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5934 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5935 tmp = I915_READ(VBLANK(cpu_transcoder));
5936 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5937 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5938 tmp = I915_READ(VSYNC(cpu_transcoder));
5939 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5940 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5941
5942 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5943 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5944 pipe_config->adjusted_mode.crtc_vtotal += 1;
5945 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5946 }
5947
5948 tmp = I915_READ(PIPESRC(crtc->pipe));
5949 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5950 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5951
5952 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5953 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5954}
5955
5956void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5957 struct intel_crtc_config *pipe_config)
5958{
5959 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5960 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5961 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5962 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5963
5964 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5965 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5966 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5967 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5968
5969 mode->flags = pipe_config->adjusted_mode.flags;
5970
5971 mode->clock = pipe_config->adjusted_mode.crtc_clock;
5972 mode->flags |= pipe_config->adjusted_mode.flags;
5973}
5974
5975static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5976{
5977 struct drm_device *dev = intel_crtc->base.dev;
5978 struct drm_i915_private *dev_priv = dev->dev_private;
5979 uint32_t pipeconf;
5980
5981 pipeconf = 0;
5982
5983 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5984 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5985 pipeconf |= PIPECONF_ENABLE;
5986
5987 if (intel_crtc->config.double_wide)
5988 pipeconf |= PIPECONF_DOUBLE_WIDE;
5989
5990 /* only g4x and later have fancy bpc/dither controls */
5991 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5992 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5993 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5994 pipeconf |= PIPECONF_DITHER_EN |
5995 PIPECONF_DITHER_TYPE_SP;
5996
5997 switch (intel_crtc->config.pipe_bpp) {
5998 case 18:
5999 pipeconf |= PIPECONF_6BPC;
6000 break;
6001 case 24:
6002 pipeconf |= PIPECONF_8BPC;
6003 break;
6004 case 30:
6005 pipeconf |= PIPECONF_10BPC;
6006 break;
6007 default:
6008 /* Case prevented by intel_choose_pipe_bpp_dither. */
6009 BUG();
6010 }
6011 }
6012
6013 if (HAS_PIPE_CXSR(dev)) {
6014 if (intel_crtc->lowfreq_avail) {
6015 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6016 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6017 } else {
6018 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6019 }
6020 }
6021
6022 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6023 if (INTEL_INFO(dev)->gen < 4 ||
6024 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
6025 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6026 else
6027 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6028 } else
6029 pipeconf |= PIPECONF_PROGRESSIVE;
6030
6031 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6032 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6033
6034 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6035 POSTING_READ(PIPECONF(intel_crtc->pipe));
6036}
6037
6038static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
6039 int x, int y,
6040 struct drm_framebuffer *fb)
6041{
6042 struct drm_device *dev = crtc->dev;
6043 struct drm_i915_private *dev_priv = dev->dev_private;
6044 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6045 int refclk, num_connectors = 0;
6046 intel_clock_t clock, reduced_clock;
6047 bool ok, has_reduced_clock = false;
6048 bool is_lvds = false, is_dsi = false;
6049 struct intel_encoder *encoder;
6050 const intel_limit_t *limit;
6051
6052 for_each_encoder_on_crtc(dev, crtc, encoder) {
6053 switch (encoder->type) {
6054 case INTEL_OUTPUT_LVDS:
6055 is_lvds = true;
6056 break;
6057 case INTEL_OUTPUT_DSI:
6058 is_dsi = true;
6059 break;
6060 }
6061
6062 num_connectors++;
6063 }
6064
6065 if (is_dsi)
6066 return 0;
6067
6068 if (!intel_crtc->config.clock_set) {
6069 refclk = i9xx_get_refclk(crtc, num_connectors);
6070
6071 /*
6072 * Returns a set of divisors for the desired target clock with
6073 * the given refclk, or FALSE. The returned values represent
6074 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6075 * 2) / p1 / p2.
6076 */
6077 limit = intel_limit(crtc, refclk);
6078 ok = dev_priv->display.find_dpll(limit, crtc,
6079 intel_crtc->config.port_clock,
6080 refclk, NULL, &clock);
6081 if (!ok) {
6082 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6083 return -EINVAL;
6084 }
6085
6086 if (is_lvds && dev_priv->lvds_downclock_avail) {
6087 /*
6088 * Ensure we match the reduced clock's P to the target
6089 * clock. If the clocks don't match, we can't switch
6090 * the display clock by using the FP0/FP1. In such case
6091 * we will disable the LVDS downclock feature.
6092 */
6093 has_reduced_clock =
6094 dev_priv->display.find_dpll(limit, crtc,
6095 dev_priv->lvds_downclock,
6096 refclk, &clock,
6097 &reduced_clock);
6098 }
6099 /* Compat-code for transition, will disappear. */
6100 intel_crtc->config.dpll.n = clock.n;
6101 intel_crtc->config.dpll.m1 = clock.m1;
6102 intel_crtc->config.dpll.m2 = clock.m2;
6103 intel_crtc->config.dpll.p1 = clock.p1;
6104 intel_crtc->config.dpll.p2 = clock.p2;
6105 }
6106
6107 if (IS_GEN2(dev)) {
6108 i8xx_update_pll(intel_crtc,
6109 has_reduced_clock ? &reduced_clock : NULL,
6110 num_connectors);
6111 } else if (IS_CHERRYVIEW(dev)) {
6112 chv_update_pll(intel_crtc);
6113 } else if (IS_VALLEYVIEW(dev)) {
6114 vlv_update_pll(intel_crtc);
6115 } else {
6116 i9xx_update_pll(intel_crtc,
6117 has_reduced_clock ? &reduced_clock : NULL,
6118 num_connectors);
6119 }
6120
6121 return 0;
6122}
6123
6124static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6125 struct intel_crtc_config *pipe_config)
6126{
6127 struct drm_device *dev = crtc->base.dev;
6128 struct drm_i915_private *dev_priv = dev->dev_private;
6129 uint32_t tmp;
6130
6131 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6132 return;
6133
6134 tmp = I915_READ(PFIT_CONTROL);
6135 if (!(tmp & PFIT_ENABLE))
6136 return;
6137
6138 /* Check whether the pfit is attached to our pipe. */
6139 if (INTEL_INFO(dev)->gen < 4) {
6140 if (crtc->pipe != PIPE_B)
6141 return;
6142 } else {
6143 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6144 return;
6145 }
6146
6147 pipe_config->gmch_pfit.control = tmp;
6148 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6149 if (INTEL_INFO(dev)->gen < 5)
6150 pipe_config->gmch_pfit.lvds_border_bits =
6151 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6152}
6153
6154static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6155 struct intel_crtc_config *pipe_config)
6156{
6157 struct drm_device *dev = crtc->base.dev;
6158 struct drm_i915_private *dev_priv = dev->dev_private;
6159 int pipe = pipe_config->cpu_transcoder;
6160 intel_clock_t clock;
6161 u32 mdiv;
6162 int refclk = 100000;
6163
6164 /* In case of MIPI DPLL will not even be used */
6165 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6166 return;
6167
6168 mutex_lock(&dev_priv->dpio_lock);
6169 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6170 mutex_unlock(&dev_priv->dpio_lock);
6171
6172 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6173 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6174 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6175 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6176 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6177
6178 vlv_clock(refclk, &clock);
6179
6180 /* clock.dot is the fast clock */
6181 pipe_config->port_clock = clock.dot / 5;
6182}
6183
6184static void i9xx_get_plane_config(struct intel_crtc *crtc,
6185 struct intel_plane_config *plane_config)
6186{
6187 struct drm_device *dev = crtc->base.dev;
6188 struct drm_i915_private *dev_priv = dev->dev_private;
6189 u32 val, base, offset;
6190 int pipe = crtc->pipe, plane = crtc->plane;
6191 int fourcc, pixel_format;
6192 int aligned_height;
6193
6194 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6195 if (!crtc->base.primary->fb) {
6196 DRM_DEBUG_KMS("failed to alloc fb\n");
6197 return;
6198 }
6199
6200 val = I915_READ(DSPCNTR(plane));
6201
6202 if (INTEL_INFO(dev)->gen >= 4)
6203 if (val & DISPPLANE_TILED)
6204 plane_config->tiled = true;
6205
6206 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6207 fourcc = intel_format_to_fourcc(pixel_format);
6208 crtc->base.primary->fb->pixel_format = fourcc;
6209 crtc->base.primary->fb->bits_per_pixel =
6210 drm_format_plane_cpp(fourcc, 0) * 8;
6211
6212 if (INTEL_INFO(dev)->gen >= 4) {
6213 if (plane_config->tiled)
6214 offset = I915_READ(DSPTILEOFF(plane));
6215 else
6216 offset = I915_READ(DSPLINOFF(plane));
6217 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6218 } else {
6219 base = I915_READ(DSPADDR(plane));
6220 }
6221 plane_config->base = base;
6222
6223 val = I915_READ(PIPESRC(pipe));
6224 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6225 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6226
6227 val = I915_READ(DSPSTRIDE(pipe));
6228 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
6229
6230 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6231 plane_config->tiled);
6232
6233 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6234 aligned_height);
6235
6236 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6237 pipe, plane, crtc->base.primary->fb->width,
6238 crtc->base.primary->fb->height,
6239 crtc->base.primary->fb->bits_per_pixel, base,
6240 crtc->base.primary->fb->pitches[0],
6241 plane_config->size);
6242
6243}
6244
6245static void chv_crtc_clock_get(struct intel_crtc *crtc,
6246 struct intel_crtc_config *pipe_config)
6247{
6248 struct drm_device *dev = crtc->base.dev;
6249 struct drm_i915_private *dev_priv = dev->dev_private;
6250 int pipe = pipe_config->cpu_transcoder;
6251 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6252 intel_clock_t clock;
6253 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6254 int refclk = 100000;
6255
6256 mutex_lock(&dev_priv->dpio_lock);
6257 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6258 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6259 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6260 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6261 mutex_unlock(&dev_priv->dpio_lock);
6262
6263 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6264 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6265 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6266 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6267 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6268
6269 chv_clock(refclk, &clock);
6270
6271 /* clock.dot is the fast clock */
6272 pipe_config->port_clock = clock.dot / 5;
6273}
6274
6275static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6276 struct intel_crtc_config *pipe_config)
6277{
6278 struct drm_device *dev = crtc->base.dev;
6279 struct drm_i915_private *dev_priv = dev->dev_private;
6280 uint32_t tmp;
6281
6282 if (!intel_display_power_enabled(dev_priv,
6283 POWER_DOMAIN_PIPE(crtc->pipe)))
6284 return false;
6285
6286 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6287 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6288
6289 tmp = I915_READ(PIPECONF(crtc->pipe));
6290 if (!(tmp & PIPECONF_ENABLE))
6291 return false;
6292
6293 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6294 switch (tmp & PIPECONF_BPC_MASK) {
6295 case PIPECONF_6BPC:
6296 pipe_config->pipe_bpp = 18;
6297 break;
6298 case PIPECONF_8BPC:
6299 pipe_config->pipe_bpp = 24;
6300 break;
6301 case PIPECONF_10BPC:
6302 pipe_config->pipe_bpp = 30;
6303 break;
6304 default:
6305 break;
6306 }
6307 }
6308
6309 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6310 pipe_config->limited_color_range = true;
6311
6312 if (INTEL_INFO(dev)->gen < 4)
6313 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6314
6315 intel_get_pipe_timings(crtc, pipe_config);
6316
6317 i9xx_get_pfit_config(crtc, pipe_config);
6318
6319 if (INTEL_INFO(dev)->gen >= 4) {
6320 tmp = I915_READ(DPLL_MD(crtc->pipe));
6321 pipe_config->pixel_multiplier =
6322 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6323 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6324 pipe_config->dpll_hw_state.dpll_md = tmp;
6325 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6326 tmp = I915_READ(DPLL(crtc->pipe));
6327 pipe_config->pixel_multiplier =
6328 ((tmp & SDVO_MULTIPLIER_MASK)
6329 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6330 } else {
6331 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6332 * port and will be fixed up in the encoder->get_config
6333 * function. */
6334 pipe_config->pixel_multiplier = 1;
6335 }
6336 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6337 if (!IS_VALLEYVIEW(dev)) {
6338 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6339 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6340 } else {
6341 /* Mask out read-only status bits. */
6342 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6343 DPLL_PORTC_READY_MASK |
6344 DPLL_PORTB_READY_MASK);
6345 }
6346
6347 if (IS_CHERRYVIEW(dev))
6348 chv_crtc_clock_get(crtc, pipe_config);
6349 else if (IS_VALLEYVIEW(dev))
6350 vlv_crtc_clock_get(crtc, pipe_config);
6351 else
6352 i9xx_crtc_clock_get(crtc, pipe_config);
6353
6354 return true;
6355}
6356
6357static void ironlake_init_pch_refclk(struct drm_device *dev)
6358{
6359 struct drm_i915_private *dev_priv = dev->dev_private;
6360 struct drm_mode_config *mode_config = &dev->mode_config;
6361 struct intel_encoder *encoder;
6362 u32 val, final;
6363 bool has_lvds = false;
6364 bool has_cpu_edp = false;
6365 bool has_panel = false;
6366 bool has_ck505 = false;
6367 bool can_ssc = false;
6368
6369 /* We need to take the global config into account */
6370 list_for_each_entry(encoder, &mode_config->encoder_list,
6371 base.head) {
6372 switch (encoder->type) {
6373 case INTEL_OUTPUT_LVDS:
6374 has_panel = true;
6375 has_lvds = true;
6376 break;
6377 case INTEL_OUTPUT_EDP:
6378 has_panel = true;
6379 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6380 has_cpu_edp = true;
6381 break;
6382 }
6383 }
6384
6385 if (HAS_PCH_IBX(dev)) {
6386 has_ck505 = dev_priv->vbt.display_clock_mode;
6387 can_ssc = has_ck505;
6388 } else {
6389 has_ck505 = false;
6390 can_ssc = true;
6391 }
6392
6393 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6394 has_panel, has_lvds, has_ck505);
6395
6396 /* Ironlake: try to setup display ref clock before DPLL
6397 * enabling. This is only under driver's control after
6398 * PCH B stepping, previous chipset stepping should be
6399 * ignoring this setting.
6400 */
6401 val = I915_READ(PCH_DREF_CONTROL);
6402
6403 /* As we must carefully and slowly disable/enable each source in turn,
6404 * compute the final state we want first and check if we need to
6405 * make any changes at all.
6406 */
6407 final = val;
6408 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6409 if (has_ck505)
6410 final |= DREF_NONSPREAD_CK505_ENABLE;
6411 else
6412 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6413
6414 final &= ~DREF_SSC_SOURCE_MASK;
6415 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6416 final &= ~DREF_SSC1_ENABLE;
6417
6418 if (has_panel) {
6419 final |= DREF_SSC_SOURCE_ENABLE;
6420
6421 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6422 final |= DREF_SSC1_ENABLE;
6423
6424 if (has_cpu_edp) {
6425 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6426 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6427 else
6428 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6429 } else
6430 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6431 } else {
6432 final |= DREF_SSC_SOURCE_DISABLE;
6433 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6434 }
6435
6436 if (final == val)
6437 return;
6438
6439 /* Always enable nonspread source */
6440 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6441
6442 if (has_ck505)
6443 val |= DREF_NONSPREAD_CK505_ENABLE;
6444 else
6445 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6446
6447 if (has_panel) {
6448 val &= ~DREF_SSC_SOURCE_MASK;
6449 val |= DREF_SSC_SOURCE_ENABLE;
6450
6451 /* SSC must be turned on before enabling the CPU output */
6452 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6453 DRM_DEBUG_KMS("Using SSC on panel\n");
6454 val |= DREF_SSC1_ENABLE;
6455 } else
6456 val &= ~DREF_SSC1_ENABLE;
6457
6458 /* Get SSC going before enabling the outputs */
6459 I915_WRITE(PCH_DREF_CONTROL, val);
6460 POSTING_READ(PCH_DREF_CONTROL);
6461 udelay(200);
6462
6463 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6464
6465 /* Enable CPU source on CPU attached eDP */
6466 if (has_cpu_edp) {
6467 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6468 DRM_DEBUG_KMS("Using SSC on eDP\n");
6469 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6470 } else
6471 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6472 } else
6473 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6474
6475 I915_WRITE(PCH_DREF_CONTROL, val);
6476 POSTING_READ(PCH_DREF_CONTROL);
6477 udelay(200);
6478 } else {
6479 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6480
6481 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6482
6483 /* Turn off CPU output */
6484 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6485
6486 I915_WRITE(PCH_DREF_CONTROL, val);
6487 POSTING_READ(PCH_DREF_CONTROL);
6488 udelay(200);
6489
6490 /* Turn off the SSC source */
6491 val &= ~DREF_SSC_SOURCE_MASK;
6492 val |= DREF_SSC_SOURCE_DISABLE;
6493
6494 /* Turn off SSC1 */
6495 val &= ~DREF_SSC1_ENABLE;
6496
6497 I915_WRITE(PCH_DREF_CONTROL, val);
6498 POSTING_READ(PCH_DREF_CONTROL);
6499 udelay(200);
6500 }
6501
6502 BUG_ON(val != final);
6503}
6504
6505static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6506{
6507 uint32_t tmp;
6508
6509 tmp = I915_READ(SOUTH_CHICKEN2);
6510 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6511 I915_WRITE(SOUTH_CHICKEN2, tmp);
6512
6513 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6514 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6515 DRM_ERROR("FDI mPHY reset assert timeout\n");
6516
6517 tmp = I915_READ(SOUTH_CHICKEN2);
6518 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6519 I915_WRITE(SOUTH_CHICKEN2, tmp);
6520
6521 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6522 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6523 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6524}
6525
6526/* WaMPhyProgramming:hsw */
6527static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6528{
6529 uint32_t tmp;
6530
6531 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6532 tmp &= ~(0xFF << 24);
6533 tmp |= (0x12 << 24);
6534 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6535
6536 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6537 tmp |= (1 << 11);
6538 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6539
6540 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6541 tmp |= (1 << 11);
6542 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6543
6544 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6545 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6546 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6547
6548 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6549 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6550 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6551
6552 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6553 tmp &= ~(7 << 13);
6554 tmp |= (5 << 13);
6555 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6556
6557 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6558 tmp &= ~(7 << 13);
6559 tmp |= (5 << 13);
6560 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6561
6562 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6563 tmp &= ~0xFF;
6564 tmp |= 0x1C;
6565 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6566
6567 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6568 tmp &= ~0xFF;
6569 tmp |= 0x1C;
6570 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6571
6572 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6573 tmp &= ~(0xFF << 16);
6574 tmp |= (0x1C << 16);
6575 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6576
6577 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6578 tmp &= ~(0xFF << 16);
6579 tmp |= (0x1C << 16);
6580 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6581
6582 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6583 tmp |= (1 << 27);
6584 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6585
6586 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6587 tmp |= (1 << 27);
6588 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6589
6590 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6591 tmp &= ~(0xF << 28);
6592 tmp |= (4 << 28);
6593 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6594
6595 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6596 tmp &= ~(0xF << 28);
6597 tmp |= (4 << 28);
6598 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6599}
6600
6601/* Implements 3 different sequences from BSpec chapter "Display iCLK
6602 * Programming" based on the parameters passed:
6603 * - Sequence to enable CLKOUT_DP
6604 * - Sequence to enable CLKOUT_DP without spread
6605 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6606 */
6607static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6608 bool with_fdi)
6609{
6610 struct drm_i915_private *dev_priv = dev->dev_private;
6611 uint32_t reg, tmp;
6612
6613 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6614 with_spread = true;
6615 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6616 with_fdi, "LP PCH doesn't have FDI\n"))
6617 with_fdi = false;
6618
6619 mutex_lock(&dev_priv->dpio_lock);
6620
6621 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6622 tmp &= ~SBI_SSCCTL_DISABLE;
6623 tmp |= SBI_SSCCTL_PATHALT;
6624 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6625
6626 udelay(24);
6627
6628 if (with_spread) {
6629 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6630 tmp &= ~SBI_SSCCTL_PATHALT;
6631 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6632
6633 if (with_fdi) {
6634 lpt_reset_fdi_mphy(dev_priv);
6635 lpt_program_fdi_mphy(dev_priv);
6636 }
6637 }
6638
6639 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6640 SBI_GEN0 : SBI_DBUFF0;
6641 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6642 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6643 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6644
6645 mutex_unlock(&dev_priv->dpio_lock);
6646}
6647
6648/* Sequence to disable CLKOUT_DP */
6649static void lpt_disable_clkout_dp(struct drm_device *dev)
6650{
6651 struct drm_i915_private *dev_priv = dev->dev_private;
6652 uint32_t reg, tmp;
6653
6654 mutex_lock(&dev_priv->dpio_lock);
6655
6656 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6657 SBI_GEN0 : SBI_DBUFF0;
6658 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6659 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6660 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6661
6662 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6663 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6664 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6665 tmp |= SBI_SSCCTL_PATHALT;
6666 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6667 udelay(32);
6668 }
6669 tmp |= SBI_SSCCTL_DISABLE;
6670 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6671 }
6672
6673 mutex_unlock(&dev_priv->dpio_lock);
6674}
6675
6676static void lpt_init_pch_refclk(struct drm_device *dev)
6677{
6678 struct drm_mode_config *mode_config = &dev->mode_config;
6679 struct intel_encoder *encoder;
6680 bool has_vga = false;
6681
6682 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6683 switch (encoder->type) {
6684 case INTEL_OUTPUT_ANALOG:
6685 has_vga = true;
6686 break;
6687 }
6688 }
6689
6690 if (has_vga)
6691 lpt_enable_clkout_dp(dev, true, true);
6692 else
6693 lpt_disable_clkout_dp(dev);
6694}
6695
6696/*
6697 * Initialize reference clocks when the driver loads
6698 */
6699void intel_init_pch_refclk(struct drm_device *dev)
6700{
6701 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6702 ironlake_init_pch_refclk(dev);
6703 else if (HAS_PCH_LPT(dev))
6704 lpt_init_pch_refclk(dev);
6705}
6706
6707static int ironlake_get_refclk(struct drm_crtc *crtc)
6708{
6709 struct drm_device *dev = crtc->dev;
6710 struct drm_i915_private *dev_priv = dev->dev_private;
6711 struct intel_encoder *encoder;
6712 int num_connectors = 0;
6713 bool is_lvds = false;
6714
6715 for_each_encoder_on_crtc(dev, crtc, encoder) {
6716 switch (encoder->type) {
6717 case INTEL_OUTPUT_LVDS:
6718 is_lvds = true;
6719 break;
6720 }
6721 num_connectors++;
6722 }
6723
6724 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6725 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6726 dev_priv->vbt.lvds_ssc_freq);
6727 return dev_priv->vbt.lvds_ssc_freq;
6728 }
6729
6730 return 120000;
6731}
6732
6733static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6734{
6735 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6737 int pipe = intel_crtc->pipe;
6738 uint32_t val;
6739
6740 val = 0;
6741
6742 switch (intel_crtc->config.pipe_bpp) {
6743 case 18:
6744 val |= PIPECONF_6BPC;
6745 break;
6746 case 24:
6747 val |= PIPECONF_8BPC;
6748 break;
6749 case 30:
6750 val |= PIPECONF_10BPC;
6751 break;
6752 case 36:
6753 val |= PIPECONF_12BPC;
6754 break;
6755 default:
6756 /* Case prevented by intel_choose_pipe_bpp_dither. */
6757 BUG();
6758 }
6759
6760 if (intel_crtc->config.dither)
6761 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6762
6763 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6764 val |= PIPECONF_INTERLACED_ILK;
6765 else
6766 val |= PIPECONF_PROGRESSIVE;
6767
6768 if (intel_crtc->config.limited_color_range)
6769 val |= PIPECONF_COLOR_RANGE_SELECT;
6770
6771 I915_WRITE(PIPECONF(pipe), val);
6772 POSTING_READ(PIPECONF(pipe));
6773}
6774
6775/*
6776 * Set up the pipe CSC unit.
6777 *
6778 * Currently only full range RGB to limited range RGB conversion
6779 * is supported, but eventually this should handle various
6780 * RGB<->YCbCr scenarios as well.
6781 */
6782static void intel_set_pipe_csc(struct drm_crtc *crtc)
6783{
6784 struct drm_device *dev = crtc->dev;
6785 struct drm_i915_private *dev_priv = dev->dev_private;
6786 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6787 int pipe = intel_crtc->pipe;
6788 uint16_t coeff = 0x7800; /* 1.0 */
6789
6790 /*
6791 * TODO: Check what kind of values actually come out of the pipe
6792 * with these coeff/postoff values and adjust to get the best
6793 * accuracy. Perhaps we even need to take the bpc value into
6794 * consideration.
6795 */
6796
6797 if (intel_crtc->config.limited_color_range)
6798 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6799
6800 /*
6801 * GY/GU and RY/RU should be the other way around according
6802 * to BSpec, but reality doesn't agree. Just set them up in
6803 * a way that results in the correct picture.
6804 */
6805 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6806 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6807
6808 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6809 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6810
6811 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6812 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6813
6814 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6815 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6816 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6817
6818 if (INTEL_INFO(dev)->gen > 6) {
6819 uint16_t postoff = 0;
6820
6821 if (intel_crtc->config.limited_color_range)
6822 postoff = (16 * (1 << 12) / 255) & 0x1fff;
6823
6824 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6825 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6826 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6827
6828 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6829 } else {
6830 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6831
6832 if (intel_crtc->config.limited_color_range)
6833 mode |= CSC_BLACK_SCREEN_OFFSET;
6834
6835 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6836 }
6837}
6838
6839static void haswell_set_pipeconf(struct drm_crtc *crtc)
6840{
6841 struct drm_device *dev = crtc->dev;
6842 struct drm_i915_private *dev_priv = dev->dev_private;
6843 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6844 enum pipe pipe = intel_crtc->pipe;
6845 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6846 uint32_t val;
6847
6848 val = 0;
6849
6850 if (IS_HASWELL(dev) && intel_crtc->config.dither)
6851 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6852
6853 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6854 val |= PIPECONF_INTERLACED_ILK;
6855 else
6856 val |= PIPECONF_PROGRESSIVE;
6857
6858 I915_WRITE(PIPECONF(cpu_transcoder), val);
6859 POSTING_READ(PIPECONF(cpu_transcoder));
6860
6861 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6862 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6863
6864 if (IS_BROADWELL(dev)) {
6865 val = 0;
6866
6867 switch (intel_crtc->config.pipe_bpp) {
6868 case 18:
6869 val |= PIPEMISC_DITHER_6_BPC;
6870 break;
6871 case 24:
6872 val |= PIPEMISC_DITHER_8_BPC;
6873 break;
6874 case 30:
6875 val |= PIPEMISC_DITHER_10_BPC;
6876 break;
6877 case 36:
6878 val |= PIPEMISC_DITHER_12_BPC;
6879 break;
6880 default:
6881 /* Case prevented by pipe_config_set_bpp. */
6882 BUG();
6883 }
6884
6885 if (intel_crtc->config.dither)
6886 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6887
6888 I915_WRITE(PIPEMISC(pipe), val);
6889 }
6890}
6891
6892static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6893 intel_clock_t *clock,
6894 bool *has_reduced_clock,
6895 intel_clock_t *reduced_clock)
6896{
6897 struct drm_device *dev = crtc->dev;
6898 struct drm_i915_private *dev_priv = dev->dev_private;
6899 struct intel_encoder *intel_encoder;
6900 int refclk;
6901 const intel_limit_t *limit;
6902 bool ret, is_lvds = false;
6903
6904 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6905 switch (intel_encoder->type) {
6906 case INTEL_OUTPUT_LVDS:
6907 is_lvds = true;
6908 break;
6909 }
6910 }
6911
6912 refclk = ironlake_get_refclk(crtc);
6913
6914 /*
6915 * Returns a set of divisors for the desired target clock with the given
6916 * refclk, or FALSE. The returned values represent the clock equation:
6917 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6918 */
6919 limit = intel_limit(crtc, refclk);
6920 ret = dev_priv->display.find_dpll(limit, crtc,
6921 to_intel_crtc(crtc)->config.port_clock,
6922 refclk, NULL, clock);
6923 if (!ret)
6924 return false;
6925
6926 if (is_lvds && dev_priv->lvds_downclock_avail) {
6927 /*
6928 * Ensure we match the reduced clock's P to the target clock.
6929 * If the clocks don't match, we can't switch the display clock
6930 * by using the FP0/FP1. In such case we will disable the LVDS
6931 * downclock feature.
6932 */
6933 *has_reduced_clock =
6934 dev_priv->display.find_dpll(limit, crtc,
6935 dev_priv->lvds_downclock,
6936 refclk, clock,
6937 reduced_clock);
6938 }
6939
6940 return true;
6941}
6942
6943int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6944{
6945 /*
6946 * Account for spread spectrum to avoid
6947 * oversubscribing the link. Max center spread
6948 * is 2.5%; use 5% for safety's sake.
6949 */
6950 u32 bps = target_clock * bpp * 21 / 20;
6951 return DIV_ROUND_UP(bps, link_bw * 8);
6952}
6953
6954static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6955{
6956 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6957}
6958
6959static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6960 u32 *fp,
6961 intel_clock_t *reduced_clock, u32 *fp2)
6962{
6963 struct drm_crtc *crtc = &intel_crtc->base;
6964 struct drm_device *dev = crtc->dev;
6965 struct drm_i915_private *dev_priv = dev->dev_private;
6966 struct intel_encoder *intel_encoder;
6967 uint32_t dpll;
6968 int factor, num_connectors = 0;
6969 bool is_lvds = false, is_sdvo = false;
6970
6971 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6972 switch (intel_encoder->type) {
6973 case INTEL_OUTPUT_LVDS:
6974 is_lvds = true;
6975 break;
6976 case INTEL_OUTPUT_SDVO:
6977 case INTEL_OUTPUT_HDMI:
6978 is_sdvo = true;
6979 break;
6980 }
6981
6982 num_connectors++;
6983 }
6984
6985 /* Enable autotuning of the PLL clock (if permissible) */
6986 factor = 21;
6987 if (is_lvds) {
6988 if ((intel_panel_use_ssc(dev_priv) &&
6989 dev_priv->vbt.lvds_ssc_freq == 100000) ||
6990 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6991 factor = 25;
6992 } else if (intel_crtc->config.sdvo_tv_clock)
6993 factor = 20;
6994
6995 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6996 *fp |= FP_CB_TUNE;
6997
6998 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6999 *fp2 |= FP_CB_TUNE;
7000
7001 dpll = 0;
7002
7003 if (is_lvds)
7004 dpll |= DPLLB_MODE_LVDS;
7005 else
7006 dpll |= DPLLB_MODE_DAC_SERIAL;
7007
7008 dpll |= (intel_crtc->config.pixel_multiplier - 1)
7009 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7010
7011 if (is_sdvo)
7012 dpll |= DPLL_SDVO_HIGH_SPEED;
7013 if (intel_crtc->config.has_dp_encoder)
7014 dpll |= DPLL_SDVO_HIGH_SPEED;
7015
7016 /* compute bitmask from p1 value */
7017 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7018 /* also FPA1 */
7019 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7020
7021 switch (intel_crtc->config.dpll.p2) {
7022 case 5:
7023 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7024 break;
7025 case 7:
7026 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7027 break;
7028 case 10:
7029 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7030 break;
7031 case 14:
7032 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7033 break;
7034 }
7035
7036 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7037 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7038 else
7039 dpll |= PLL_REF_INPUT_DREFCLK;
7040
7041 return dpll | DPLL_VCO_ENABLE;
7042}
7043
7044static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
7045 int x, int y,
7046 struct drm_framebuffer *fb)
7047{
7048 struct drm_device *dev = crtc->dev;
7049 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7050 int num_connectors = 0;
7051 intel_clock_t clock, reduced_clock;
7052 u32 dpll = 0, fp = 0, fp2 = 0;
7053 bool ok, has_reduced_clock = false;
7054 bool is_lvds = false;
7055 struct intel_encoder *encoder;
7056 struct intel_shared_dpll *pll;
7057
7058 for_each_encoder_on_crtc(dev, crtc, encoder) {
7059 switch (encoder->type) {
7060 case INTEL_OUTPUT_LVDS:
7061 is_lvds = true;
7062 break;
7063 }
7064
7065 num_connectors++;
7066 }
7067
7068 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7069 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7070
7071 ok = ironlake_compute_clocks(crtc, &clock,
7072 &has_reduced_clock, &reduced_clock);
7073 if (!ok && !intel_crtc->config.clock_set) {
7074 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7075 return -EINVAL;
7076 }
7077 /* Compat-code for transition, will disappear. */
7078 if (!intel_crtc->config.clock_set) {
7079 intel_crtc->config.dpll.n = clock.n;
7080 intel_crtc->config.dpll.m1 = clock.m1;
7081 intel_crtc->config.dpll.m2 = clock.m2;
7082 intel_crtc->config.dpll.p1 = clock.p1;
7083 intel_crtc->config.dpll.p2 = clock.p2;
7084 }
7085
7086 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7087 if (intel_crtc->config.has_pch_encoder) {
7088 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
7089 if (has_reduced_clock)
7090 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7091
7092 dpll = ironlake_compute_dpll(intel_crtc,
7093 &fp, &reduced_clock,
7094 has_reduced_clock ? &fp2 : NULL);
7095
7096 intel_crtc->config.dpll_hw_state.dpll = dpll;
7097 intel_crtc->config.dpll_hw_state.fp0 = fp;
7098 if (has_reduced_clock)
7099 intel_crtc->config.dpll_hw_state.fp1 = fp2;
7100 else
7101 intel_crtc->config.dpll_hw_state.fp1 = fp;
7102
7103 pll = intel_get_shared_dpll(intel_crtc);
7104 if (pll == NULL) {
7105 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7106 pipe_name(intel_crtc->pipe));
7107 return -EINVAL;
7108 }
7109 } else
7110 intel_put_shared_dpll(intel_crtc);
7111
7112 if (is_lvds && has_reduced_clock && i915.powersave)
7113 intel_crtc->lowfreq_avail = true;
7114 else
7115 intel_crtc->lowfreq_avail = false;
7116
7117 return 0;
7118}
7119
7120static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7121 struct intel_link_m_n *m_n)
7122{
7123 struct drm_device *dev = crtc->base.dev;
7124 struct drm_i915_private *dev_priv = dev->dev_private;
7125 enum pipe pipe = crtc->pipe;
7126
7127 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7128 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7129 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7130 & ~TU_SIZE_MASK;
7131 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7132 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7133 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7134}
7135
7136static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7137 enum transcoder transcoder,
7138 struct intel_link_m_n *m_n)
7139{
7140 struct drm_device *dev = crtc->base.dev;
7141 struct drm_i915_private *dev_priv = dev->dev_private;
7142 enum pipe pipe = crtc->pipe;
7143
7144 if (INTEL_INFO(dev)->gen >= 5) {
7145 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7146 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7147 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7148 & ~TU_SIZE_MASK;
7149 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7150 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7151 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7152 } else {
7153 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7154 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7155 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7156 & ~TU_SIZE_MASK;
7157 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7158 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7159 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7160 }
7161}
7162
7163void intel_dp_get_m_n(struct intel_crtc *crtc,
7164 struct intel_crtc_config *pipe_config)
7165{
7166 if (crtc->config.has_pch_encoder)
7167 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7168 else
7169 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7170 &pipe_config->dp_m_n);
7171}
7172
7173static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7174 struct intel_crtc_config *pipe_config)
7175{
7176 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7177 &pipe_config->fdi_m_n);
7178}
7179
7180static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7181 struct intel_crtc_config *pipe_config)
7182{
7183 struct drm_device *dev = crtc->base.dev;
7184 struct drm_i915_private *dev_priv = dev->dev_private;
7185 uint32_t tmp;
7186
7187 tmp = I915_READ(PF_CTL(crtc->pipe));
7188
7189 if (tmp & PF_ENABLE) {
7190 pipe_config->pch_pfit.enabled = true;
7191 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7192 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7193
7194 /* We currently do not free assignements of panel fitters on
7195 * ivb/hsw (since we don't use the higher upscaling modes which
7196 * differentiates them) so just WARN about this case for now. */
7197 if (IS_GEN7(dev)) {
7198 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7199 PF_PIPE_SEL_IVB(crtc->pipe));
7200 }
7201 }
7202}
7203
7204static void ironlake_get_plane_config(struct intel_crtc *crtc,
7205 struct intel_plane_config *plane_config)
7206{
7207 struct drm_device *dev = crtc->base.dev;
7208 struct drm_i915_private *dev_priv = dev->dev_private;
7209 u32 val, base, offset;
7210 int pipe = crtc->pipe, plane = crtc->plane;
7211 int fourcc, pixel_format;
7212 int aligned_height;
7213
7214 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7215 if (!crtc->base.primary->fb) {
7216 DRM_DEBUG_KMS("failed to alloc fb\n");
7217 return;
7218 }
7219
7220 val = I915_READ(DSPCNTR(plane));
7221
7222 if (INTEL_INFO(dev)->gen >= 4)
7223 if (val & DISPPLANE_TILED)
7224 plane_config->tiled = true;
7225
7226 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7227 fourcc = intel_format_to_fourcc(pixel_format);
7228 crtc->base.primary->fb->pixel_format = fourcc;
7229 crtc->base.primary->fb->bits_per_pixel =
7230 drm_format_plane_cpp(fourcc, 0) * 8;
7231
7232 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7233 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7234 offset = I915_READ(DSPOFFSET(plane));
7235 } else {
7236 if (plane_config->tiled)
7237 offset = I915_READ(DSPTILEOFF(plane));
7238 else
7239 offset = I915_READ(DSPLINOFF(plane));
7240 }
7241 plane_config->base = base;
7242
7243 val = I915_READ(PIPESRC(pipe));
7244 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7245 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7246
7247 val = I915_READ(DSPSTRIDE(pipe));
7248 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
7249
7250 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7251 plane_config->tiled);
7252
7253 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7254 aligned_height);
7255
7256 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7257 pipe, plane, crtc->base.primary->fb->width,
7258 crtc->base.primary->fb->height,
7259 crtc->base.primary->fb->bits_per_pixel, base,
7260 crtc->base.primary->fb->pitches[0],
7261 plane_config->size);
7262}
7263
7264static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7265 struct intel_crtc_config *pipe_config)
7266{
7267 struct drm_device *dev = crtc->base.dev;
7268 struct drm_i915_private *dev_priv = dev->dev_private;
7269 uint32_t tmp;
7270
7271 if (!intel_display_power_enabled(dev_priv,
7272 POWER_DOMAIN_PIPE(crtc->pipe)))
7273 return false;
7274
7275 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7276 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7277
7278 tmp = I915_READ(PIPECONF(crtc->pipe));
7279 if (!(tmp & PIPECONF_ENABLE))
7280 return false;
7281
7282 switch (tmp & PIPECONF_BPC_MASK) {
7283 case PIPECONF_6BPC:
7284 pipe_config->pipe_bpp = 18;
7285 break;
7286 case PIPECONF_8BPC:
7287 pipe_config->pipe_bpp = 24;
7288 break;
7289 case PIPECONF_10BPC:
7290 pipe_config->pipe_bpp = 30;
7291 break;
7292 case PIPECONF_12BPC:
7293 pipe_config->pipe_bpp = 36;
7294 break;
7295 default:
7296 break;
7297 }
7298
7299 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7300 pipe_config->limited_color_range = true;
7301
7302 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7303 struct intel_shared_dpll *pll;
7304
7305 pipe_config->has_pch_encoder = true;
7306
7307 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7308 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7309 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7310
7311 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7312
7313 if (HAS_PCH_IBX(dev_priv->dev)) {
7314 pipe_config->shared_dpll =
7315 (enum intel_dpll_id) crtc->pipe;
7316 } else {
7317 tmp = I915_READ(PCH_DPLL_SEL);
7318 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7319 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7320 else
7321 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7322 }
7323
7324 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7325
7326 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7327 &pipe_config->dpll_hw_state));
7328
7329 tmp = pipe_config->dpll_hw_state.dpll;
7330 pipe_config->pixel_multiplier =
7331 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7332 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7333
7334 ironlake_pch_clock_get(crtc, pipe_config);
7335 } else {
7336 pipe_config->pixel_multiplier = 1;
7337 }
7338
7339 intel_get_pipe_timings(crtc, pipe_config);
7340
7341 ironlake_get_pfit_config(crtc, pipe_config);
7342
7343 return true;
7344}
7345
7346static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7347{
7348 struct drm_device *dev = dev_priv->dev;
7349 struct intel_crtc *crtc;
7350
7351 for_each_intel_crtc(dev, crtc)
7352 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7353 pipe_name(crtc->pipe));
7354
7355 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7356 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7357 WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7358 WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7359 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7360 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7361 "CPU PWM1 enabled\n");
7362 if (IS_HASWELL(dev))
7363 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7364 "CPU PWM2 enabled\n");
7365 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7366 "PCH PWM1 enabled\n");
7367 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7368 "Utility pin enabled\n");
7369 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7370
7371 /*
7372 * In theory we can still leave IRQs enabled, as long as only the HPD
7373 * interrupts remain enabled. We used to check for that, but since it's
7374 * gen-specific and since we only disable LCPLL after we fully disable
7375 * the interrupts, the check below should be enough.
7376 */
7377 WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7378}
7379
7380static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7381{
7382 struct drm_device *dev = dev_priv->dev;
7383
7384 if (IS_HASWELL(dev))
7385 return I915_READ(D_COMP_HSW);
7386 else
7387 return I915_READ(D_COMP_BDW);
7388}
7389
7390static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7391{
7392 struct drm_device *dev = dev_priv->dev;
7393
7394 if (IS_HASWELL(dev)) {
7395 mutex_lock(&dev_priv->rps.hw_lock);
7396 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7397 val))
7398 DRM_ERROR("Failed to write to D_COMP\n");
7399 mutex_unlock(&dev_priv->rps.hw_lock);
7400 } else {
7401 I915_WRITE(D_COMP_BDW, val);
7402 POSTING_READ(D_COMP_BDW);
7403 }
7404}
7405
7406/*
7407 * This function implements pieces of two sequences from BSpec:
7408 * - Sequence for display software to disable LCPLL
7409 * - Sequence for display software to allow package C8+
7410 * The steps implemented here are just the steps that actually touch the LCPLL
7411 * register. Callers should take care of disabling all the display engine
7412 * functions, doing the mode unset, fixing interrupts, etc.
7413 */
7414static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7415 bool switch_to_fclk, bool allow_power_down)
7416{
7417 uint32_t val;
7418
7419 assert_can_disable_lcpll(dev_priv);
7420
7421 val = I915_READ(LCPLL_CTL);
7422
7423 if (switch_to_fclk) {
7424 val |= LCPLL_CD_SOURCE_FCLK;
7425 I915_WRITE(LCPLL_CTL, val);
7426
7427 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7428 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7429 DRM_ERROR("Switching to FCLK failed\n");
7430
7431 val = I915_READ(LCPLL_CTL);
7432 }
7433
7434 val |= LCPLL_PLL_DISABLE;
7435 I915_WRITE(LCPLL_CTL, val);
7436 POSTING_READ(LCPLL_CTL);
7437
7438 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7439 DRM_ERROR("LCPLL still locked\n");
7440
7441 val = hsw_read_dcomp(dev_priv);
7442 val |= D_COMP_COMP_DISABLE;
7443 hsw_write_dcomp(dev_priv, val);
7444 ndelay(100);
7445
7446 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7447 1))
7448 DRM_ERROR("D_COMP RCOMP still in progress\n");
7449
7450 if (allow_power_down) {
7451 val = I915_READ(LCPLL_CTL);
7452 val |= LCPLL_POWER_DOWN_ALLOW;
7453 I915_WRITE(LCPLL_CTL, val);
7454 POSTING_READ(LCPLL_CTL);
7455 }
7456}
7457
7458/*
7459 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7460 * source.
7461 */
7462static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7463{
7464 uint32_t val;
7465 unsigned long irqflags;
7466
7467 val = I915_READ(LCPLL_CTL);
7468
7469 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7470 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7471 return;
7472
7473 /*
7474 * Make sure we're not on PC8 state before disabling PC8, otherwise
7475 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7476 *
7477 * The other problem is that hsw_restore_lcpll() is called as part of
7478 * the runtime PM resume sequence, so we can't just call
7479 * gen6_gt_force_wake_get() because that function calls
7480 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7481 * while we are on the resume sequence. So to solve this problem we have
7482 * to call special forcewake code that doesn't touch runtime PM and
7483 * doesn't enable the forcewake delayed work.
7484 */
7485 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7486 if (dev_priv->uncore.forcewake_count++ == 0)
7487 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7488 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7489
7490 if (val & LCPLL_POWER_DOWN_ALLOW) {
7491 val &= ~LCPLL_POWER_DOWN_ALLOW;
7492 I915_WRITE(LCPLL_CTL, val);
7493 POSTING_READ(LCPLL_CTL);
7494 }
7495
7496 val = hsw_read_dcomp(dev_priv);
7497 val |= D_COMP_COMP_FORCE;
7498 val &= ~D_COMP_COMP_DISABLE;
7499 hsw_write_dcomp(dev_priv, val);
7500
7501 val = I915_READ(LCPLL_CTL);
7502 val &= ~LCPLL_PLL_DISABLE;
7503 I915_WRITE(LCPLL_CTL, val);
7504
7505 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7506 DRM_ERROR("LCPLL not locked yet\n");
7507
7508 if (val & LCPLL_CD_SOURCE_FCLK) {
7509 val = I915_READ(LCPLL_CTL);
7510 val &= ~LCPLL_CD_SOURCE_FCLK;
7511 I915_WRITE(LCPLL_CTL, val);
7512
7513 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7514 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7515 DRM_ERROR("Switching back to LCPLL failed\n");
7516 }
7517
7518 /* See the big comment above. */
7519 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7520 if (--dev_priv->uncore.forcewake_count == 0)
7521 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7522 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7523}
7524
7525/*
7526 * Package states C8 and deeper are really deep PC states that can only be
7527 * reached when all the devices on the system allow it, so even if the graphics
7528 * device allows PC8+, it doesn't mean the system will actually get to these
7529 * states. Our driver only allows PC8+ when going into runtime PM.
7530 *
7531 * The requirements for PC8+ are that all the outputs are disabled, the power
7532 * well is disabled and most interrupts are disabled, and these are also
7533 * requirements for runtime PM. When these conditions are met, we manually do
7534 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7535 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7536 * hang the machine.
7537 *
7538 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7539 * the state of some registers, so when we come back from PC8+ we need to
7540 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7541 * need to take care of the registers kept by RC6. Notice that this happens even
7542 * if we don't put the device in PCI D3 state (which is what currently happens
7543 * because of the runtime PM support).
7544 *
7545 * For more, read "Display Sequences for Package C8" on the hardware
7546 * documentation.
7547 */
7548void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7549{
7550 struct drm_device *dev = dev_priv->dev;
7551 uint32_t val;
7552
7553 DRM_DEBUG_KMS("Enabling package C8+\n");
7554
7555 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7556 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7557 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7558 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7559 }
7560
7561 lpt_disable_clkout_dp(dev);
7562 hsw_disable_lcpll(dev_priv, true, true);
7563}
7564
7565void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7566{
7567 struct drm_device *dev = dev_priv->dev;
7568 uint32_t val;
7569
7570 DRM_DEBUG_KMS("Disabling package C8+\n");
7571
7572 hsw_restore_lcpll(dev_priv);
7573 lpt_init_pch_refclk(dev);
7574
7575 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7576 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7577 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7578 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7579 }
7580
7581 intel_prepare_ddi(dev);
7582}
7583
7584static void snb_modeset_global_resources(struct drm_device *dev)
7585{
7586 modeset_update_crtc_power_domains(dev);
7587}
7588
7589static void haswell_modeset_global_resources(struct drm_device *dev)
7590{
7591 modeset_update_crtc_power_domains(dev);
7592}
7593
7594static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7595 int x, int y,
7596 struct drm_framebuffer *fb)
7597{
7598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7599
7600 if (!intel_ddi_pll_select(intel_crtc))
7601 return -EINVAL;
7602
7603 intel_crtc->lowfreq_avail = false;
7604
7605 return 0;
7606}
7607
7608static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7609 struct intel_crtc_config *pipe_config)
7610{
7611 struct drm_device *dev = crtc->base.dev;
7612 struct drm_i915_private *dev_priv = dev->dev_private;
7613 struct intel_shared_dpll *pll;
7614 enum port port;
7615 uint32_t tmp;
7616
7617 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7618
7619 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7620
7621 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7622
7623 switch (pipe_config->ddi_pll_sel) {
7624 case PORT_CLK_SEL_WRPLL1:
7625 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7626 break;
7627 case PORT_CLK_SEL_WRPLL2:
7628 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7629 break;
7630 }
7631
7632 if (pipe_config->shared_dpll >= 0) {
7633 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7634
7635 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7636 &pipe_config->dpll_hw_state));
7637 }
7638
7639 /*
7640 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7641 * DDI E. So just check whether this pipe is wired to DDI E and whether
7642 * the PCH transcoder is on.
7643 */
7644 if ((port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7645 pipe_config->has_pch_encoder = true;
7646
7647 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7648 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7649 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7650
7651 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7652 }
7653}
7654
7655static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7656 struct intel_crtc_config *pipe_config)
7657{
7658 struct drm_device *dev = crtc->base.dev;
7659 struct drm_i915_private *dev_priv = dev->dev_private;
7660 enum intel_display_power_domain pfit_domain;
7661 uint32_t tmp;
7662
7663 if (!intel_display_power_enabled(dev_priv,
7664 POWER_DOMAIN_PIPE(crtc->pipe)))
7665 return false;
7666
7667 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7668 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7669
7670 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7671 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7672 enum pipe trans_edp_pipe;
7673 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7674 default:
7675 WARN(1, "unknown pipe linked to edp transcoder\n");
7676 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7677 case TRANS_DDI_EDP_INPUT_A_ON:
7678 trans_edp_pipe = PIPE_A;
7679 break;
7680 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7681 trans_edp_pipe = PIPE_B;
7682 break;
7683 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7684 trans_edp_pipe = PIPE_C;
7685 break;
7686 }
7687
7688 if (trans_edp_pipe == crtc->pipe)
7689 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7690 }
7691
7692 if (!intel_display_power_enabled(dev_priv,
7693 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7694 return false;
7695
7696 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7697 if (!(tmp & PIPECONF_ENABLE))
7698 return false;
7699
7700 haswell_get_ddi_port_state(crtc, pipe_config);
7701
7702 intel_get_pipe_timings(crtc, pipe_config);
7703
7704 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7705 if (intel_display_power_enabled(dev_priv, pfit_domain))
7706 ironlake_get_pfit_config(crtc, pipe_config);
7707
7708 if (IS_HASWELL(dev))
7709 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7710 (I915_READ(IPS_CTL) & IPS_ENABLE);
7711
7712 pipe_config->pixel_multiplier = 1;
7713
7714 return true;
7715}
7716
7717static struct {
7718 int clock;
7719 u32 config;
7720} hdmi_audio_clock[] = {
7721 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7722 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7723 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7724 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7725 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7726 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7727 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7728 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7729 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7730 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7731};
7732
7733/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7734static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7735{
7736 int i;
7737
7738 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7739 if (mode->clock == hdmi_audio_clock[i].clock)
7740 break;
7741 }
7742
7743 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7744 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7745 i = 1;
7746 }
7747
7748 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7749 hdmi_audio_clock[i].clock,
7750 hdmi_audio_clock[i].config);
7751
7752 return hdmi_audio_clock[i].config;
7753}
7754
7755static bool intel_eld_uptodate(struct drm_connector *connector,
7756 int reg_eldv, uint32_t bits_eldv,
7757 int reg_elda, uint32_t bits_elda,
7758 int reg_edid)
7759{
7760 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7761 uint8_t *eld = connector->eld;
7762 uint32_t i;
7763
7764 i = I915_READ(reg_eldv);
7765 i &= bits_eldv;
7766
7767 if (!eld[0])
7768 return !i;
7769
7770 if (!i)
7771 return false;
7772
7773 i = I915_READ(reg_elda);
7774 i &= ~bits_elda;
7775 I915_WRITE(reg_elda, i);
7776
7777 for (i = 0; i < eld[2]; i++)
7778 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7779 return false;
7780
7781 return true;
7782}
7783
7784static void g4x_write_eld(struct drm_connector *connector,
7785 struct drm_crtc *crtc,
7786 struct drm_display_mode *mode)
7787{
7788 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7789 uint8_t *eld = connector->eld;
7790 uint32_t eldv;
7791 uint32_t len;
7792 uint32_t i;
7793
7794 i = I915_READ(G4X_AUD_VID_DID);
7795
7796 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7797 eldv = G4X_ELDV_DEVCL_DEVBLC;
7798 else
7799 eldv = G4X_ELDV_DEVCTG;
7800
7801 if (intel_eld_uptodate(connector,
7802 G4X_AUD_CNTL_ST, eldv,
7803 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7804 G4X_HDMIW_HDMIEDID))
7805 return;
7806
7807 i = I915_READ(G4X_AUD_CNTL_ST);
7808 i &= ~(eldv | G4X_ELD_ADDR);
7809 len = (i >> 9) & 0x1f; /* ELD buffer size */
7810 I915_WRITE(G4X_AUD_CNTL_ST, i);
7811
7812 if (!eld[0])
7813 return;
7814
7815 len = min_t(uint8_t, eld[2], len);
7816 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7817 for (i = 0; i < len; i++)
7818 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7819
7820 i = I915_READ(G4X_AUD_CNTL_ST);
7821 i |= eldv;
7822 I915_WRITE(G4X_AUD_CNTL_ST, i);
7823}
7824
7825static void haswell_write_eld(struct drm_connector *connector,
7826 struct drm_crtc *crtc,
7827 struct drm_display_mode *mode)
7828{
7829 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7830 uint8_t *eld = connector->eld;
7831 uint32_t eldv;
7832 uint32_t i;
7833 int len;
7834 int pipe = to_intel_crtc(crtc)->pipe;
7835 int tmp;
7836
7837 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7838 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7839 int aud_config = HSW_AUD_CFG(pipe);
7840 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7841
7842 /* Audio output enable */
7843 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7844 tmp = I915_READ(aud_cntrl_st2);
7845 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7846 I915_WRITE(aud_cntrl_st2, tmp);
7847 POSTING_READ(aud_cntrl_st2);
7848
7849 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7850
7851 /* Set ELD valid state */
7852 tmp = I915_READ(aud_cntrl_st2);
7853 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7854 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7855 I915_WRITE(aud_cntrl_st2, tmp);
7856 tmp = I915_READ(aud_cntrl_st2);
7857 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7858
7859 /* Enable HDMI mode */
7860 tmp = I915_READ(aud_config);
7861 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7862 /* clear N_programing_enable and N_value_index */
7863 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7864 I915_WRITE(aud_config, tmp);
7865
7866 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7867
7868 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7869
7870 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7871 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7872 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7873 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7874 } else {
7875 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7876 }
7877
7878 if (intel_eld_uptodate(connector,
7879 aud_cntrl_st2, eldv,
7880 aud_cntl_st, IBX_ELD_ADDRESS,
7881 hdmiw_hdmiedid))
7882 return;
7883
7884 i = I915_READ(aud_cntrl_st2);
7885 i &= ~eldv;
7886 I915_WRITE(aud_cntrl_st2, i);
7887
7888 if (!eld[0])
7889 return;
7890
7891 i = I915_READ(aud_cntl_st);
7892 i &= ~IBX_ELD_ADDRESS;
7893 I915_WRITE(aud_cntl_st, i);
7894 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7895 DRM_DEBUG_DRIVER("port num:%d\n", i);
7896
7897 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7898 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7899 for (i = 0; i < len; i++)
7900 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7901
7902 i = I915_READ(aud_cntrl_st2);
7903 i |= eldv;
7904 I915_WRITE(aud_cntrl_st2, i);
7905
7906}
7907
7908static void ironlake_write_eld(struct drm_connector *connector,
7909 struct drm_crtc *crtc,
7910 struct drm_display_mode *mode)
7911{
7912 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7913 uint8_t *eld = connector->eld;
7914 uint32_t eldv;
7915 uint32_t i;
7916 int len;
7917 int hdmiw_hdmiedid;
7918 int aud_config;
7919 int aud_cntl_st;
7920 int aud_cntrl_st2;
7921 int pipe = to_intel_crtc(crtc)->pipe;
7922
7923 if (HAS_PCH_IBX(connector->dev)) {
7924 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7925 aud_config = IBX_AUD_CFG(pipe);
7926 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7927 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7928 } else if (IS_VALLEYVIEW(connector->dev)) {
7929 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7930 aud_config = VLV_AUD_CFG(pipe);
7931 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7932 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7933 } else {
7934 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7935 aud_config = CPT_AUD_CFG(pipe);
7936 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7937 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7938 }
7939
7940 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7941
7942 if (IS_VALLEYVIEW(connector->dev)) {
7943 struct intel_encoder *intel_encoder;
7944 struct intel_digital_port *intel_dig_port;
7945
7946 intel_encoder = intel_attached_encoder(connector);
7947 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7948 i = intel_dig_port->port;
7949 } else {
7950 i = I915_READ(aud_cntl_st);
7951 i = (i >> 29) & DIP_PORT_SEL_MASK;
7952 /* DIP_Port_Select, 0x1 = PortB */
7953 }
7954
7955 if (!i) {
7956 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7957 /* operate blindly on all ports */
7958 eldv = IBX_ELD_VALIDB;
7959 eldv |= IBX_ELD_VALIDB << 4;
7960 eldv |= IBX_ELD_VALIDB << 8;
7961 } else {
7962 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7963 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7964 }
7965
7966 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7967 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7968 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7969 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7970 } else {
7971 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7972 }
7973
7974 if (intel_eld_uptodate(connector,
7975 aud_cntrl_st2, eldv,
7976 aud_cntl_st, IBX_ELD_ADDRESS,
7977 hdmiw_hdmiedid))
7978 return;
7979
7980 i = I915_READ(aud_cntrl_st2);
7981 i &= ~eldv;
7982 I915_WRITE(aud_cntrl_st2, i);
7983
7984 if (!eld[0])
7985 return;
7986
7987 i = I915_READ(aud_cntl_st);
7988 i &= ~IBX_ELD_ADDRESS;
7989 I915_WRITE(aud_cntl_st, i);
7990
7991 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7992 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7993 for (i = 0; i < len; i++)
7994 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7995
7996 i = I915_READ(aud_cntrl_st2);
7997 i |= eldv;
7998 I915_WRITE(aud_cntrl_st2, i);
7999}
8000
8001void intel_write_eld(struct drm_encoder *encoder,
8002 struct drm_display_mode *mode)
8003{
8004 struct drm_crtc *crtc = encoder->crtc;
8005 struct drm_connector *connector;
8006 struct drm_device *dev = encoder->dev;
8007 struct drm_i915_private *dev_priv = dev->dev_private;
8008
8009 connector = drm_select_eld(encoder, mode);
8010 if (!connector)
8011 return;
8012
8013 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8014 connector->base.id,
8015 connector->name,
8016 connector->encoder->base.id,
8017 connector->encoder->name);
8018
8019 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
8020
8021 if (dev_priv->display.write_eld)
8022 dev_priv->display.write_eld(connector, crtc, mode);
8023}
8024
8025static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8026{
8027 struct drm_device *dev = crtc->dev;
8028 struct drm_i915_private *dev_priv = dev->dev_private;
8029 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8030 uint32_t cntl;
8031
8032 if (base != intel_crtc->cursor_base) {
8033 /* On these chipsets we can only modify the base whilst
8034 * the cursor is disabled.
8035 */
8036 if (intel_crtc->cursor_cntl) {
8037 I915_WRITE(_CURACNTR, 0);
8038 POSTING_READ(_CURACNTR);
8039 intel_crtc->cursor_cntl = 0;
8040 }
8041
8042 I915_WRITE(_CURABASE, base);
8043 POSTING_READ(_CURABASE);
8044 }
8045
8046 /* XXX width must be 64, stride 256 => 0x00 << 28 */
8047 cntl = 0;
8048 if (base)
8049 cntl = (CURSOR_ENABLE |
8050 CURSOR_GAMMA_ENABLE |
8051 CURSOR_FORMAT_ARGB);
8052 if (intel_crtc->cursor_cntl != cntl) {
8053 I915_WRITE(_CURACNTR, cntl);
8054 POSTING_READ(_CURACNTR);
8055 intel_crtc->cursor_cntl = cntl;
8056 }
8057}
8058
8059static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8060{
8061 struct drm_device *dev = crtc->dev;
8062 struct drm_i915_private *dev_priv = dev->dev_private;
8063 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8064 int pipe = intel_crtc->pipe;
8065 uint32_t cntl;
8066
8067 cntl = 0;
8068 if (base) {
8069 cntl = MCURSOR_GAMMA_ENABLE;
8070 switch (intel_crtc->cursor_width) {
8071 case 64:
8072 cntl |= CURSOR_MODE_64_ARGB_AX;
8073 break;
8074 case 128:
8075 cntl |= CURSOR_MODE_128_ARGB_AX;
8076 break;
8077 case 256:
8078 cntl |= CURSOR_MODE_256_ARGB_AX;
8079 break;
8080 default:
8081 WARN_ON(1);
8082 return;
8083 }
8084 cntl |= pipe << 28; /* Connect to correct pipe */
8085 }
8086 if (intel_crtc->cursor_cntl != cntl) {
8087 I915_WRITE(CURCNTR(pipe), cntl);
8088 POSTING_READ(CURCNTR(pipe));
8089 intel_crtc->cursor_cntl = cntl;
8090 }
8091
8092 /* and commit changes on next vblank */
8093 I915_WRITE(CURBASE(pipe), base);
8094 POSTING_READ(CURBASE(pipe));
8095}
8096
8097static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
8098{
8099 struct drm_device *dev = crtc->dev;
8100 struct drm_i915_private *dev_priv = dev->dev_private;
8101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8102 int pipe = intel_crtc->pipe;
8103 uint32_t cntl;
8104
8105 cntl = 0;
8106 if (base) {
8107 cntl = MCURSOR_GAMMA_ENABLE;
8108 switch (intel_crtc->cursor_width) {
8109 case 64:
8110 cntl |= CURSOR_MODE_64_ARGB_AX;
8111 break;
8112 case 128:
8113 cntl |= CURSOR_MODE_128_ARGB_AX;
8114 break;
8115 case 256:
8116 cntl |= CURSOR_MODE_256_ARGB_AX;
8117 break;
8118 default:
8119 WARN_ON(1);
8120 return;
8121 }
8122 }
8123 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8124 cntl |= CURSOR_PIPE_CSC_ENABLE;
8125
8126 if (intel_crtc->cursor_cntl != cntl) {
8127 I915_WRITE(CURCNTR(pipe), cntl);
8128 POSTING_READ(CURCNTR(pipe));
8129 intel_crtc->cursor_cntl = cntl;
8130 }
8131
8132 /* and commit changes on next vblank */
8133 I915_WRITE(CURBASE(pipe), base);
8134 POSTING_READ(CURBASE(pipe));
8135}
8136
8137/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8138static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8139 bool on)
8140{
8141 struct drm_device *dev = crtc->dev;
8142 struct drm_i915_private *dev_priv = dev->dev_private;
8143 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8144 int pipe = intel_crtc->pipe;
8145 int x = crtc->cursor_x;
8146 int y = crtc->cursor_y;
8147 u32 base = 0, pos = 0;
8148
8149 if (on)
8150 base = intel_crtc->cursor_addr;
8151
8152 if (x >= intel_crtc->config.pipe_src_w)
8153 base = 0;
8154
8155 if (y >= intel_crtc->config.pipe_src_h)
8156 base = 0;
8157
8158 if (x < 0) {
8159 if (x + intel_crtc->cursor_width <= 0)
8160 base = 0;
8161
8162 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8163 x = -x;
8164 }
8165 pos |= x << CURSOR_X_SHIFT;
8166
8167 if (y < 0) {
8168 if (y + intel_crtc->cursor_height <= 0)
8169 base = 0;
8170
8171 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8172 y = -y;
8173 }
8174 pos |= y << CURSOR_Y_SHIFT;
8175
8176 if (base == 0 && intel_crtc->cursor_base == 0)
8177 return;
8178
8179 I915_WRITE(CURPOS(pipe), pos);
8180
8181 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
8182 ivb_update_cursor(crtc, base);
8183 else if (IS_845G(dev) || IS_I865G(dev))
8184 i845_update_cursor(crtc, base);
8185 else
8186 i9xx_update_cursor(crtc, base);
8187 intel_crtc->cursor_base = base;
8188}
8189
8190/*
8191 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8192 *
8193 * Note that the object's reference will be consumed if the update fails. If
8194 * the update succeeds, the reference of the old object (if any) will be
8195 * consumed.
8196 */
8197static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8198 struct drm_i915_gem_object *obj,
8199 uint32_t width, uint32_t height)
8200{
8201 struct drm_device *dev = crtc->dev;
8202 struct drm_i915_private *dev_priv = dev->dev_private;
8203 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8204 enum pipe pipe = intel_crtc->pipe;
8205 unsigned old_width;
8206 uint32_t addr;
8207 int ret;
8208
8209 /* if we want to turn off the cursor ignore width and height */
8210 if (!obj) {
8211 DRM_DEBUG_KMS("cursor off\n");
8212 addr = 0;
8213 obj = NULL;
8214 mutex_lock(&dev->struct_mutex);
8215 goto finish;
8216 }
8217
8218 /* Check for which cursor types we support */
8219 if (!((width == 64 && height == 64) ||
8220 (width == 128 && height == 128 && !IS_GEN2(dev)) ||
8221 (width == 256 && height == 256 && !IS_GEN2(dev)))) {
8222 DRM_DEBUG("Cursor dimension not supported\n");
8223 return -EINVAL;
8224 }
8225
8226 if (obj->base.size < width * height * 4) {
8227 DRM_DEBUG_KMS("buffer is too small\n");
8228 ret = -ENOMEM;
8229 goto fail;
8230 }
8231
8232 /* we only need to pin inside GTT if cursor is non-phy */
8233 mutex_lock(&dev->struct_mutex);
8234 if (!INTEL_INFO(dev)->cursor_needs_physical) {
8235 unsigned alignment;
8236
8237 if (obj->tiling_mode) {
8238 DRM_DEBUG_KMS("cursor cannot be tiled\n");
8239 ret = -EINVAL;
8240 goto fail_locked;
8241 }
8242
8243 /* Note that the w/a also requires 2 PTE of padding following
8244 * the bo. We currently fill all unused PTE with the shadow
8245 * page and so we should always have valid PTE following the
8246 * cursor preventing the VT-d warning.
8247 */
8248 alignment = 0;
8249 if (need_vtd_wa(dev))
8250 alignment = 64*1024;
8251
8252 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8253 if (ret) {
8254 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8255 goto fail_locked;
8256 }
8257
8258 ret = i915_gem_object_put_fence(obj);
8259 if (ret) {
8260 DRM_DEBUG_KMS("failed to release fence for cursor");
8261 goto fail_unpin;
8262 }
8263
8264 addr = i915_gem_obj_ggtt_offset(obj);
8265 } else {
8266 int align = IS_I830(dev) ? 16 * 1024 : 256;
8267 ret = i915_gem_object_attach_phys(obj, align);
8268 if (ret) {
8269 DRM_DEBUG_KMS("failed to attach phys object\n");
8270 goto fail_locked;
8271 }
8272 addr = obj->phys_handle->busaddr;
8273 }
8274
8275 if (IS_GEN2(dev))
8276 I915_WRITE(CURSIZE, (height << 12) | width);
8277
8278 finish:
8279 if (intel_crtc->cursor_bo) {
8280 if (!INTEL_INFO(dev)->cursor_needs_physical)
8281 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8282 }
8283
8284 i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8285 INTEL_FRONTBUFFER_CURSOR(pipe));
8286 mutex_unlock(&dev->struct_mutex);
8287
8288 old_width = intel_crtc->cursor_width;
8289
8290 intel_crtc->cursor_addr = addr;
8291 intel_crtc->cursor_bo = obj;
8292 intel_crtc->cursor_width = width;
8293 intel_crtc->cursor_height = height;
8294
8295 if (intel_crtc->active) {
8296 if (old_width != width)
8297 intel_update_watermarks(crtc);
8298 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8299 }
8300
8301 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8302
8303 return 0;
8304fail_unpin:
8305 i915_gem_object_unpin_from_display_plane(obj);
8306fail_locked:
8307 mutex_unlock(&dev->struct_mutex);
8308fail:
8309 drm_gem_object_unreference_unlocked(&obj->base);
8310 return ret;
8311}
8312
8313static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8314 u16 *blue, uint32_t start, uint32_t size)
8315{
8316 int end = (start + size > 256) ? 256 : start + size, i;
8317 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8318
8319 for (i = start; i < end; i++) {
8320 intel_crtc->lut_r[i] = red[i] >> 8;
8321 intel_crtc->lut_g[i] = green[i] >> 8;
8322 intel_crtc->lut_b[i] = blue[i] >> 8;
8323 }
8324
8325 intel_crtc_load_lut(crtc);
8326}
8327
8328/* VESA 640x480x72Hz mode to set on the pipe */
8329static struct drm_display_mode load_detect_mode = {
8330 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8331 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8332};
8333
8334struct drm_framebuffer *
8335__intel_framebuffer_create(struct drm_device *dev,
8336 struct drm_mode_fb_cmd2 *mode_cmd,
8337 struct drm_i915_gem_object *obj)
8338{
8339 struct intel_framebuffer *intel_fb;
8340 int ret;
8341
8342 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8343 if (!intel_fb) {
8344 drm_gem_object_unreference_unlocked(&obj->base);
8345 return ERR_PTR(-ENOMEM);
8346 }
8347
8348 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8349 if (ret)
8350 goto err;
8351
8352 return &intel_fb->base;
8353err:
8354 drm_gem_object_unreference_unlocked(&obj->base);
8355 kfree(intel_fb);
8356
8357 return ERR_PTR(ret);
8358}
8359
8360static struct drm_framebuffer *
8361intel_framebuffer_create(struct drm_device *dev,
8362 struct drm_mode_fb_cmd2 *mode_cmd,
8363 struct drm_i915_gem_object *obj)
8364{
8365 struct drm_framebuffer *fb;
8366 int ret;
8367
8368 ret = i915_mutex_lock_interruptible(dev);
8369 if (ret)
8370 return ERR_PTR(ret);
8371 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8372 mutex_unlock(&dev->struct_mutex);
8373
8374 return fb;
8375}
8376
8377static u32
8378intel_framebuffer_pitch_for_width(int width, int bpp)
8379{
8380 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8381 return ALIGN(pitch, 64);
8382}
8383
8384static u32
8385intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8386{
8387 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8388 return PAGE_ALIGN(pitch * mode->vdisplay);
8389}
8390
8391static struct drm_framebuffer *
8392intel_framebuffer_create_for_mode(struct drm_device *dev,
8393 struct drm_display_mode *mode,
8394 int depth, int bpp)
8395{
8396 struct drm_i915_gem_object *obj;
8397 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8398
8399 obj = i915_gem_alloc_object(dev,
8400 intel_framebuffer_size_for_mode(mode, bpp));
8401 if (obj == NULL)
8402 return ERR_PTR(-ENOMEM);
8403
8404 mode_cmd.width = mode->hdisplay;
8405 mode_cmd.height = mode->vdisplay;
8406 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8407 bpp);
8408 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8409
8410 return intel_framebuffer_create(dev, &mode_cmd, obj);
8411}
8412
8413static struct drm_framebuffer *
8414mode_fits_in_fbdev(struct drm_device *dev,
8415 struct drm_display_mode *mode)
8416{
8417#ifdef CONFIG_DRM_I915_FBDEV
8418 struct drm_i915_private *dev_priv = dev->dev_private;
8419 struct drm_i915_gem_object *obj;
8420 struct drm_framebuffer *fb;
8421
8422 if (!dev_priv->fbdev)
8423 return NULL;
8424
8425 if (!dev_priv->fbdev->fb)
8426 return NULL;
8427
8428 obj = dev_priv->fbdev->fb->obj;
8429 BUG_ON(!obj);
8430
8431 fb = &dev_priv->fbdev->fb->base;
8432 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8433 fb->bits_per_pixel))
8434 return NULL;
8435
8436 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8437 return NULL;
8438
8439 return fb;
8440#else
8441 return NULL;
8442#endif
8443}
8444
8445bool intel_get_load_detect_pipe(struct drm_connector *connector,
8446 struct drm_display_mode *mode,
8447 struct intel_load_detect_pipe *old,
8448 struct drm_modeset_acquire_ctx *ctx)
8449{
8450 struct intel_crtc *intel_crtc;
8451 struct intel_encoder *intel_encoder =
8452 intel_attached_encoder(connector);
8453 struct drm_crtc *possible_crtc;
8454 struct drm_encoder *encoder = &intel_encoder->base;
8455 struct drm_crtc *crtc = NULL;
8456 struct drm_device *dev = encoder->dev;
8457 struct drm_framebuffer *fb;
8458 struct drm_mode_config *config = &dev->mode_config;
8459 int ret, i = -1;
8460
8461 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8462 connector->base.id, connector->name,
8463 encoder->base.id, encoder->name);
8464
8465 drm_modeset_acquire_init(ctx, 0);
8466
8467retry:
8468 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8469 if (ret)
8470 goto fail_unlock;
8471
8472 /*
8473 * Algorithm gets a little messy:
8474 *
8475 * - if the connector already has an assigned crtc, use it (but make
8476 * sure it's on first)
8477 *
8478 * - try to find the first unused crtc that can drive this connector,
8479 * and use that if we find one
8480 */
8481
8482 /* See if we already have a CRTC for this connector */
8483 if (encoder->crtc) {
8484 crtc = encoder->crtc;
8485
8486 ret = drm_modeset_lock(&crtc->mutex, ctx);
8487 if (ret)
8488 goto fail_unlock;
8489
8490 old->dpms_mode = connector->dpms;
8491 old->load_detect_temp = false;
8492
8493 /* Make sure the crtc and connector are running */
8494 if (connector->dpms != DRM_MODE_DPMS_ON)
8495 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8496
8497 return true;
8498 }
8499
8500 /* Find an unused one (if possible) */
8501 for_each_crtc(dev, possible_crtc) {
8502 i++;
8503 if (!(encoder->possible_crtcs & (1 << i)))
8504 continue;
8505 if (!possible_crtc->enabled) {
8506 crtc = possible_crtc;
8507 break;
8508 }
8509 }
8510
8511 /*
8512 * If we didn't find an unused CRTC, don't use any.
8513 */
8514 if (!crtc) {
8515 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8516 goto fail_unlock;
8517 }
8518
8519 ret = drm_modeset_lock(&crtc->mutex, ctx);
8520 if (ret)
8521 goto fail_unlock;
8522 intel_encoder->new_crtc = to_intel_crtc(crtc);
8523 to_intel_connector(connector)->new_encoder = intel_encoder;
8524
8525 intel_crtc = to_intel_crtc(crtc);
8526 intel_crtc->new_enabled = true;
8527 intel_crtc->new_config = &intel_crtc->config;
8528 old->dpms_mode = connector->dpms;
8529 old->load_detect_temp = true;
8530 old->release_fb = NULL;
8531
8532 if (!mode)
8533 mode = &load_detect_mode;
8534
8535 /* We need a framebuffer large enough to accommodate all accesses
8536 * that the plane may generate whilst we perform load detection.
8537 * We can not rely on the fbcon either being present (we get called
8538 * during its initialisation to detect all boot displays, or it may
8539 * not even exist) or that it is large enough to satisfy the
8540 * requested mode.
8541 */
8542 fb = mode_fits_in_fbdev(dev, mode);
8543 if (fb == NULL) {
8544 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8545 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8546 old->release_fb = fb;
8547 } else
8548 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8549 if (IS_ERR(fb)) {
8550 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8551 goto fail;
8552 }
8553
8554 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8555 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8556 if (old->release_fb)
8557 old->release_fb->funcs->destroy(old->release_fb);
8558 goto fail;
8559 }
8560
8561 /* let the connector get through one full cycle before testing */
8562 intel_wait_for_vblank(dev, intel_crtc->pipe);
8563 return true;
8564
8565 fail:
8566 intel_crtc->new_enabled = crtc->enabled;
8567 if (intel_crtc->new_enabled)
8568 intel_crtc->new_config = &intel_crtc->config;
8569 else
8570 intel_crtc->new_config = NULL;
8571fail_unlock:
8572 if (ret == -EDEADLK) {
8573 drm_modeset_backoff(ctx);
8574 goto retry;
8575 }
8576
8577 drm_modeset_drop_locks(ctx);
8578 drm_modeset_acquire_fini(ctx);
8579
8580 return false;
8581}
8582
8583void intel_release_load_detect_pipe(struct drm_connector *connector,
8584 struct intel_load_detect_pipe *old,
8585 struct drm_modeset_acquire_ctx *ctx)
8586{
8587 struct intel_encoder *intel_encoder =
8588 intel_attached_encoder(connector);
8589 struct drm_encoder *encoder = &intel_encoder->base;
8590 struct drm_crtc *crtc = encoder->crtc;
8591 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8592
8593 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8594 connector->base.id, connector->name,
8595 encoder->base.id, encoder->name);
8596
8597 if (old->load_detect_temp) {
8598 to_intel_connector(connector)->new_encoder = NULL;
8599 intel_encoder->new_crtc = NULL;
8600 intel_crtc->new_enabled = false;
8601 intel_crtc->new_config = NULL;
8602 intel_set_mode(crtc, NULL, 0, 0, NULL);
8603
8604 if (old->release_fb) {
8605 drm_framebuffer_unregister_private(old->release_fb);
8606 drm_framebuffer_unreference(old->release_fb);
8607 }
8608
8609 goto unlock;
8610 return;
8611 }
8612
8613 /* Switch crtc and encoder back off if necessary */
8614 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8615 connector->funcs->dpms(connector, old->dpms_mode);
8616
8617unlock:
8618 drm_modeset_drop_locks(ctx);
8619 drm_modeset_acquire_fini(ctx);
8620}
8621
8622static int i9xx_pll_refclk(struct drm_device *dev,
8623 const struct intel_crtc_config *pipe_config)
8624{
8625 struct drm_i915_private *dev_priv = dev->dev_private;
8626 u32 dpll = pipe_config->dpll_hw_state.dpll;
8627
8628 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8629 return dev_priv->vbt.lvds_ssc_freq;
8630 else if (HAS_PCH_SPLIT(dev))
8631 return 120000;
8632 else if (!IS_GEN2(dev))
8633 return 96000;
8634 else
8635 return 48000;
8636}
8637
8638/* Returns the clock of the currently programmed mode of the given pipe. */
8639static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8640 struct intel_crtc_config *pipe_config)
8641{
8642 struct drm_device *dev = crtc->base.dev;
8643 struct drm_i915_private *dev_priv = dev->dev_private;
8644 int pipe = pipe_config->cpu_transcoder;
8645 u32 dpll = pipe_config->dpll_hw_state.dpll;
8646 u32 fp;
8647 intel_clock_t clock;
8648 int refclk = i9xx_pll_refclk(dev, pipe_config);
8649
8650 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8651 fp = pipe_config->dpll_hw_state.fp0;
8652 else
8653 fp = pipe_config->dpll_hw_state.fp1;
8654
8655 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8656 if (IS_PINEVIEW(dev)) {
8657 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8658 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8659 } else {
8660 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8661 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8662 }
8663
8664 if (!IS_GEN2(dev)) {
8665 if (IS_PINEVIEW(dev))
8666 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8667 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8668 else
8669 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8670 DPLL_FPA01_P1_POST_DIV_SHIFT);
8671
8672 switch (dpll & DPLL_MODE_MASK) {
8673 case DPLLB_MODE_DAC_SERIAL:
8674 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8675 5 : 10;
8676 break;
8677 case DPLLB_MODE_LVDS:
8678 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8679 7 : 14;
8680 break;
8681 default:
8682 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8683 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8684 return;
8685 }
8686
8687 if (IS_PINEVIEW(dev))
8688 pineview_clock(refclk, &clock);
8689 else
8690 i9xx_clock(refclk, &clock);
8691 } else {
8692 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8693 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8694
8695 if (is_lvds) {
8696 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8697 DPLL_FPA01_P1_POST_DIV_SHIFT);
8698
8699 if (lvds & LVDS_CLKB_POWER_UP)
8700 clock.p2 = 7;
8701 else
8702 clock.p2 = 14;
8703 } else {
8704 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8705 clock.p1 = 2;
8706 else {
8707 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8708 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8709 }
8710 if (dpll & PLL_P2_DIVIDE_BY_4)
8711 clock.p2 = 4;
8712 else
8713 clock.p2 = 2;
8714 }
8715
8716 i9xx_clock(refclk, &clock);
8717 }
8718
8719 /*
8720 * This value includes pixel_multiplier. We will use
8721 * port_clock to compute adjusted_mode.crtc_clock in the
8722 * encoder's get_config() function.
8723 */
8724 pipe_config->port_clock = clock.dot;
8725}
8726
8727int intel_dotclock_calculate(int link_freq,
8728 const struct intel_link_m_n *m_n)
8729{
8730 /*
8731 * The calculation for the data clock is:
8732 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8733 * But we want to avoid losing precison if possible, so:
8734 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8735 *
8736 * and the link clock is simpler:
8737 * link_clock = (m * link_clock) / n
8738 */
8739
8740 if (!m_n->link_n)
8741 return 0;
8742
8743 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8744}
8745
8746static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8747 struct intel_crtc_config *pipe_config)
8748{
8749 struct drm_device *dev = crtc->base.dev;
8750
8751 /* read out port_clock from the DPLL */
8752 i9xx_crtc_clock_get(crtc, pipe_config);
8753
8754 /*
8755 * This value does not include pixel_multiplier.
8756 * We will check that port_clock and adjusted_mode.crtc_clock
8757 * agree once we know their relationship in the encoder's
8758 * get_config() function.
8759 */
8760 pipe_config->adjusted_mode.crtc_clock =
8761 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8762 &pipe_config->fdi_m_n);
8763}
8764
8765/** Returns the currently programmed mode of the given pipe. */
8766struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8767 struct drm_crtc *crtc)
8768{
8769 struct drm_i915_private *dev_priv = dev->dev_private;
8770 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8771 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8772 struct drm_display_mode *mode;
8773 struct intel_crtc_config pipe_config;
8774 int htot = I915_READ(HTOTAL(cpu_transcoder));
8775 int hsync = I915_READ(HSYNC(cpu_transcoder));
8776 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8777 int vsync = I915_READ(VSYNC(cpu_transcoder));
8778 enum pipe pipe = intel_crtc->pipe;
8779
8780 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8781 if (!mode)
8782 return NULL;
8783
8784 /*
8785 * Construct a pipe_config sufficient for getting the clock info
8786 * back out of crtc_clock_get.
8787 *
8788 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8789 * to use a real value here instead.
8790 */
8791 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8792 pipe_config.pixel_multiplier = 1;
8793 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8794 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8795 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8796 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8797
8798 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8799 mode->hdisplay = (htot & 0xffff) + 1;
8800 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8801 mode->hsync_start = (hsync & 0xffff) + 1;
8802 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8803 mode->vdisplay = (vtot & 0xffff) + 1;
8804 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8805 mode->vsync_start = (vsync & 0xffff) + 1;
8806 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8807
8808 drm_mode_set_name(mode);
8809
8810 return mode;
8811}
8812
8813static void intel_increase_pllclock(struct drm_device *dev,
8814 enum pipe pipe)
8815{
8816 struct drm_i915_private *dev_priv = dev->dev_private;
8817 int dpll_reg = DPLL(pipe);
8818 int dpll;
8819
8820 if (!HAS_GMCH_DISPLAY(dev))
8821 return;
8822
8823 if (!dev_priv->lvds_downclock_avail)
8824 return;
8825
8826 dpll = I915_READ(dpll_reg);
8827 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8828 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8829
8830 assert_panel_unlocked(dev_priv, pipe);
8831
8832 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8833 I915_WRITE(dpll_reg, dpll);
8834 intel_wait_for_vblank(dev, pipe);
8835
8836 dpll = I915_READ(dpll_reg);
8837 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8838 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8839 }
8840}
8841
8842static void intel_decrease_pllclock(struct drm_crtc *crtc)
8843{
8844 struct drm_device *dev = crtc->dev;
8845 struct drm_i915_private *dev_priv = dev->dev_private;
8846 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8847
8848 if (!HAS_GMCH_DISPLAY(dev))
8849 return;
8850
8851 if (!dev_priv->lvds_downclock_avail)
8852 return;
8853
8854 /*
8855 * Since this is called by a timer, we should never get here in
8856 * the manual case.
8857 */
8858 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8859 int pipe = intel_crtc->pipe;
8860 int dpll_reg = DPLL(pipe);
8861 int dpll;
8862
8863 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8864
8865 assert_panel_unlocked(dev_priv, pipe);
8866
8867 dpll = I915_READ(dpll_reg);
8868 dpll |= DISPLAY_RATE_SELECT_FPA1;
8869 I915_WRITE(dpll_reg, dpll);
8870 intel_wait_for_vblank(dev, pipe);
8871 dpll = I915_READ(dpll_reg);
8872 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8873 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8874 }
8875
8876}
8877
8878void intel_mark_busy(struct drm_device *dev)
8879{
8880 struct drm_i915_private *dev_priv = dev->dev_private;
8881
8882 if (dev_priv->mm.busy)
8883 return;
8884
8885 intel_runtime_pm_get(dev_priv);
8886 i915_update_gfx_val(dev_priv);
8887 dev_priv->mm.busy = true;
8888}
8889
8890void intel_mark_idle(struct drm_device *dev)
8891{
8892 struct drm_i915_private *dev_priv = dev->dev_private;
8893 struct drm_crtc *crtc;
8894
8895 if (!dev_priv->mm.busy)
8896 return;
8897
8898 dev_priv->mm.busy = false;
8899
8900 if (!i915.powersave)
8901 goto out;
8902
8903 for_each_crtc(dev, crtc) {
8904 if (!crtc->primary->fb)
8905 continue;
8906
8907 intel_decrease_pllclock(crtc);
8908 }
8909
8910 if (INTEL_INFO(dev)->gen >= 6)
8911 gen6_rps_idle(dev->dev_private);
8912
8913out:
8914 intel_runtime_pm_put(dev_priv);
8915}
8916
8917
8918/**
8919 * intel_mark_fb_busy - mark given planes as busy
8920 * @dev: DRM device
8921 * @frontbuffer_bits: bits for the affected planes
8922 * @ring: optional ring for asynchronous commands
8923 *
8924 * This function gets called every time the screen contents change. It can be
8925 * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
8926 */
8927static void intel_mark_fb_busy(struct drm_device *dev,
8928 unsigned frontbuffer_bits,
8929 struct intel_engine_cs *ring)
8930{
8931 enum pipe pipe;
8932
8933 if (!i915.powersave)
8934 return;
8935
8936 for_each_pipe(pipe) {
8937 if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)))
8938 continue;
8939
8940 intel_increase_pllclock(dev, pipe);
8941 if (ring && intel_fbc_enabled(dev))
8942 ring->fbc_dirty = true;
8943 }
8944}
8945
8946/**
8947 * intel_fb_obj_invalidate - invalidate frontbuffer object
8948 * @obj: GEM object to invalidate
8949 * @ring: set for asynchronous rendering
8950 *
8951 * This function gets called every time rendering on the given object starts and
8952 * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
8953 * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
8954 * until the rendering completes or a flip on this frontbuffer plane is
8955 * scheduled.
8956 */
8957void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
8958 struct intel_engine_cs *ring)
8959{
8960 struct drm_device *dev = obj->base.dev;
8961 struct drm_i915_private *dev_priv = dev->dev_private;
8962
8963 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
8964
8965 if (!obj->frontbuffer_bits)
8966 return;
8967
8968 if (ring) {
8969 mutex_lock(&dev_priv->fb_tracking.lock);
8970 dev_priv->fb_tracking.busy_bits
8971 |= obj->frontbuffer_bits;
8972 dev_priv->fb_tracking.flip_bits
8973 &= ~obj->frontbuffer_bits;
8974 mutex_unlock(&dev_priv->fb_tracking.lock);
8975 }
8976
8977 intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
8978
8979 intel_edp_psr_invalidate(dev, obj->frontbuffer_bits);
8980}
8981
8982/**
8983 * intel_frontbuffer_flush - flush frontbuffer
8984 * @dev: DRM device
8985 * @frontbuffer_bits: frontbuffer plane tracking bits
8986 *
8987 * This function gets called every time rendering on the given planes has
8988 * completed and frontbuffer caching can be started again. Flushes will get
8989 * delayed if they're blocked by some oustanding asynchronous rendering.
8990 *
8991 * Can be called without any locks held.
8992 */
8993void intel_frontbuffer_flush(struct drm_device *dev,
8994 unsigned frontbuffer_bits)
8995{
8996 struct drm_i915_private *dev_priv = dev->dev_private;
8997
8998 /* Delay flushing when rings are still busy.*/
8999 mutex_lock(&dev_priv->fb_tracking.lock);
9000 frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits;
9001 mutex_unlock(&dev_priv->fb_tracking.lock);
9002
9003 intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
9004
9005 intel_edp_psr_flush(dev, frontbuffer_bits);
9006}
9007
9008/**
9009 * intel_fb_obj_flush - flush frontbuffer object
9010 * @obj: GEM object to flush
9011 * @retire: set when retiring asynchronous rendering
9012 *
9013 * This function gets called every time rendering on the given object has
9014 * completed and frontbuffer caching can be started again. If @retire is true
9015 * then any delayed flushes will be unblocked.
9016 */
9017void intel_fb_obj_flush(struct drm_i915_gem_object *obj,
9018 bool retire)
9019{
9020 struct drm_device *dev = obj->base.dev;
9021 struct drm_i915_private *dev_priv = dev->dev_private;
9022 unsigned frontbuffer_bits;
9023
9024 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9025
9026 if (!obj->frontbuffer_bits)
9027 return;
9028
9029 frontbuffer_bits = obj->frontbuffer_bits;
9030
9031 if (retire) {
9032 mutex_lock(&dev_priv->fb_tracking.lock);
9033 /* Filter out new bits since rendering started. */
9034 frontbuffer_bits &= dev_priv->fb_tracking.busy_bits;
9035
9036 dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits;
9037 mutex_unlock(&dev_priv->fb_tracking.lock);
9038 }
9039
9040 intel_frontbuffer_flush(dev, frontbuffer_bits);
9041}
9042
9043/**
9044 * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
9045 * @dev: DRM device
9046 * @frontbuffer_bits: frontbuffer plane tracking bits
9047 *
9048 * This function gets called after scheduling a flip on @obj. The actual
9049 * frontbuffer flushing will be delayed until completion is signalled with
9050 * intel_frontbuffer_flip_complete. If an invalidate happens in between this
9051 * flush will be cancelled.
9052 *
9053 * Can be called without any locks held.
9054 */
9055void intel_frontbuffer_flip_prepare(struct drm_device *dev,
9056 unsigned frontbuffer_bits)
9057{
9058 struct drm_i915_private *dev_priv = dev->dev_private;
9059
9060 mutex_lock(&dev_priv->fb_tracking.lock);
9061 dev_priv->fb_tracking.flip_bits
9062 |= frontbuffer_bits;
9063 mutex_unlock(&dev_priv->fb_tracking.lock);
9064}
9065
9066/**
9067 * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9068 * @dev: DRM device
9069 * @frontbuffer_bits: frontbuffer plane tracking bits
9070 *
9071 * This function gets called after the flip has been latched and will complete
9072 * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9073 *
9074 * Can be called without any locks held.
9075 */
9076void intel_frontbuffer_flip_complete(struct drm_device *dev,
9077 unsigned frontbuffer_bits)
9078{
9079 struct drm_i915_private *dev_priv = dev->dev_private;
9080
9081 mutex_lock(&dev_priv->fb_tracking.lock);
9082 /* Mask any cancelled flips. */
9083 frontbuffer_bits &= dev_priv->fb_tracking.flip_bits;
9084 dev_priv->fb_tracking.flip_bits &= ~frontbuffer_bits;
9085 mutex_unlock(&dev_priv->fb_tracking.lock);
9086
9087 intel_frontbuffer_flush(dev, frontbuffer_bits);
9088}
9089
9090static void intel_crtc_destroy(struct drm_crtc *crtc)
9091{
9092 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9093 struct drm_device *dev = crtc->dev;
9094 struct intel_unpin_work *work;
9095 unsigned long flags;
9096
9097 spin_lock_irqsave(&dev->event_lock, flags);
9098 work = intel_crtc->unpin_work;
9099 intel_crtc->unpin_work = NULL;
9100 spin_unlock_irqrestore(&dev->event_lock, flags);
9101
9102 if (work) {
9103 cancel_work_sync(&work->work);
9104 kfree(work);
9105 }
9106
9107 drm_crtc_cleanup(crtc);
9108
9109 kfree(intel_crtc);
9110}
9111
9112static void intel_unpin_work_fn(struct work_struct *__work)
9113{
9114 struct intel_unpin_work *work =
9115 container_of(__work, struct intel_unpin_work, work);
9116 struct drm_device *dev = work->crtc->dev;
9117 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9118
9119 mutex_lock(&dev->struct_mutex);
9120 intel_unpin_fb_obj(work->old_fb_obj);
9121 drm_gem_object_unreference(&work->pending_flip_obj->base);
9122 drm_gem_object_unreference(&work->old_fb_obj->base);
9123
9124 intel_update_fbc(dev);
9125 mutex_unlock(&dev->struct_mutex);
9126
9127 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9128
9129 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9130 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9131
9132 kfree(work);
9133}
9134
9135static void do_intel_finish_page_flip(struct drm_device *dev,
9136 struct drm_crtc *crtc)
9137{
9138 struct drm_i915_private *dev_priv = dev->dev_private;
9139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9140 struct intel_unpin_work *work;
9141 unsigned long flags;
9142
9143 /* Ignore early vblank irqs */
9144 if (intel_crtc == NULL)
9145 return;
9146
9147 spin_lock_irqsave(&dev->event_lock, flags);
9148 work = intel_crtc->unpin_work;
9149
9150 /* Ensure we don't miss a work->pending update ... */
9151 smp_rmb();
9152
9153 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9154 spin_unlock_irqrestore(&dev->event_lock, flags);
9155 return;
9156 }
9157
9158 /* and that the unpin work is consistent wrt ->pending. */
9159 smp_rmb();
9160
9161 intel_crtc->unpin_work = NULL;
9162
9163 if (work->event)
9164 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
9165
9166 drm_crtc_vblank_put(crtc);
9167
9168 spin_unlock_irqrestore(&dev->event_lock, flags);
9169
9170 wake_up_all(&dev_priv->pending_flip_queue);
9171
9172 queue_work(dev_priv->wq, &work->work);
9173
9174 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
9175}
9176
9177void intel_finish_page_flip(struct drm_device *dev, int pipe)
9178{
9179 struct drm_i915_private *dev_priv = dev->dev_private;
9180 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9181
9182 do_intel_finish_page_flip(dev, crtc);
9183}
9184
9185void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9186{
9187 struct drm_i915_private *dev_priv = dev->dev_private;
9188 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9189
9190 do_intel_finish_page_flip(dev, crtc);
9191}
9192
9193/* Is 'a' after or equal to 'b'? */
9194static bool g4x_flip_count_after_eq(u32 a, u32 b)
9195{
9196 return !((a - b) & 0x80000000);
9197}
9198
9199static bool page_flip_finished(struct intel_crtc *crtc)
9200{
9201 struct drm_device *dev = crtc->base.dev;
9202 struct drm_i915_private *dev_priv = dev->dev_private;
9203
9204 /*
9205 * The relevant registers doen't exist on pre-ctg.
9206 * As the flip done interrupt doesn't trigger for mmio
9207 * flips on gmch platforms, a flip count check isn't
9208 * really needed there. But since ctg has the registers,
9209 * include it in the check anyway.
9210 */
9211 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9212 return true;
9213
9214 /*
9215 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9216 * used the same base address. In that case the mmio flip might
9217 * have completed, but the CS hasn't even executed the flip yet.
9218 *
9219 * A flip count check isn't enough as the CS might have updated
9220 * the base address just after start of vblank, but before we
9221 * managed to process the interrupt. This means we'd complete the
9222 * CS flip too soon.
9223 *
9224 * Combining both checks should get us a good enough result. It may
9225 * still happen that the CS flip has been executed, but has not
9226 * yet actually completed. But in case the base address is the same
9227 * anyway, we don't really care.
9228 */
9229 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9230 crtc->unpin_work->gtt_offset &&
9231 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9232 crtc->unpin_work->flip_count);
9233}
9234
9235void intel_prepare_page_flip(struct drm_device *dev, int plane)
9236{
9237 struct drm_i915_private *dev_priv = dev->dev_private;
9238 struct intel_crtc *intel_crtc =
9239 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9240 unsigned long flags;
9241
9242 /* NB: An MMIO update of the plane base pointer will also
9243 * generate a page-flip completion irq, i.e. every modeset
9244 * is also accompanied by a spurious intel_prepare_page_flip().
9245 */
9246 spin_lock_irqsave(&dev->event_lock, flags);
9247 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9248 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9249 spin_unlock_irqrestore(&dev->event_lock, flags);
9250}
9251
9252static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9253{
9254 /* Ensure that the work item is consistent when activating it ... */
9255 smp_wmb();
9256 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9257 /* and that it is marked active as soon as the irq could fire. */
9258 smp_wmb();
9259}
9260
9261static int intel_gen2_queue_flip(struct drm_device *dev,
9262 struct drm_crtc *crtc,
9263 struct drm_framebuffer *fb,
9264 struct drm_i915_gem_object *obj,
9265 struct intel_engine_cs *ring,
9266 uint32_t flags)
9267{
9268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9269 u32 flip_mask;
9270 int ret;
9271
9272 ret = intel_ring_begin(ring, 6);
9273 if (ret)
9274 return ret;
9275
9276 /* Can't queue multiple flips, so wait for the previous
9277 * one to finish before executing the next.
9278 */
9279 if (intel_crtc->plane)
9280 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9281 else
9282 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9283 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9284 intel_ring_emit(ring, MI_NOOP);
9285 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9286 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9287 intel_ring_emit(ring, fb->pitches[0]);
9288 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9289 intel_ring_emit(ring, 0); /* aux display base address, unused */
9290
9291 intel_mark_page_flip_active(intel_crtc);
9292 __intel_ring_advance(ring);
9293 return 0;
9294}
9295
9296static int intel_gen3_queue_flip(struct drm_device *dev,
9297 struct drm_crtc *crtc,
9298 struct drm_framebuffer *fb,
9299 struct drm_i915_gem_object *obj,
9300 struct intel_engine_cs *ring,
9301 uint32_t flags)
9302{
9303 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9304 u32 flip_mask;
9305 int ret;
9306
9307 ret = intel_ring_begin(ring, 6);
9308 if (ret)
9309 return ret;
9310
9311 if (intel_crtc->plane)
9312 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9313 else
9314 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9315 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9316 intel_ring_emit(ring, MI_NOOP);
9317 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9318 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9319 intel_ring_emit(ring, fb->pitches[0]);
9320 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9321 intel_ring_emit(ring, MI_NOOP);
9322
9323 intel_mark_page_flip_active(intel_crtc);
9324 __intel_ring_advance(ring);
9325 return 0;
9326}
9327
9328static int intel_gen4_queue_flip(struct drm_device *dev,
9329 struct drm_crtc *crtc,
9330 struct drm_framebuffer *fb,
9331 struct drm_i915_gem_object *obj,
9332 struct intel_engine_cs *ring,
9333 uint32_t flags)
9334{
9335 struct drm_i915_private *dev_priv = dev->dev_private;
9336 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9337 uint32_t pf, pipesrc;
9338 int ret;
9339
9340 ret = intel_ring_begin(ring, 4);
9341 if (ret)
9342 return ret;
9343
9344 /* i965+ uses the linear or tiled offsets from the
9345 * Display Registers (which do not change across a page-flip)
9346 * so we need only reprogram the base address.
9347 */
9348 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9349 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9350 intel_ring_emit(ring, fb->pitches[0]);
9351 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9352 obj->tiling_mode);
9353
9354 /* XXX Enabling the panel-fitter across page-flip is so far
9355 * untested on non-native modes, so ignore it for now.
9356 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9357 */
9358 pf = 0;
9359 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9360 intel_ring_emit(ring, pf | pipesrc);
9361
9362 intel_mark_page_flip_active(intel_crtc);
9363 __intel_ring_advance(ring);
9364 return 0;
9365}
9366
9367static int intel_gen6_queue_flip(struct drm_device *dev,
9368 struct drm_crtc *crtc,
9369 struct drm_framebuffer *fb,
9370 struct drm_i915_gem_object *obj,
9371 struct intel_engine_cs *ring,
9372 uint32_t flags)
9373{
9374 struct drm_i915_private *dev_priv = dev->dev_private;
9375 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9376 uint32_t pf, pipesrc;
9377 int ret;
9378
9379 ret = intel_ring_begin(ring, 4);
9380 if (ret)
9381 return ret;
9382
9383 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9384 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9385 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9386 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9387
9388 /* Contrary to the suggestions in the documentation,
9389 * "Enable Panel Fitter" does not seem to be required when page
9390 * flipping with a non-native mode, and worse causes a normal
9391 * modeset to fail.
9392 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9393 */
9394 pf = 0;
9395 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9396 intel_ring_emit(ring, pf | pipesrc);
9397
9398 intel_mark_page_flip_active(intel_crtc);
9399 __intel_ring_advance(ring);
9400 return 0;
9401}
9402
9403static int intel_gen7_queue_flip(struct drm_device *dev,
9404 struct drm_crtc *crtc,
9405 struct drm_framebuffer *fb,
9406 struct drm_i915_gem_object *obj,
9407 struct intel_engine_cs *ring,
9408 uint32_t flags)
9409{
9410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9411 uint32_t plane_bit = 0;
9412 int len, ret;
9413
9414 switch (intel_crtc->plane) {
9415 case PLANE_A:
9416 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9417 break;
9418 case PLANE_B:
9419 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9420 break;
9421 case PLANE_C:
9422 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9423 break;
9424 default:
9425 WARN_ONCE(1, "unknown plane in flip command\n");
9426 return -ENODEV;
9427 }
9428
9429 len = 4;
9430 if (ring->id == RCS) {
9431 len += 6;
9432 /*
9433 * On Gen 8, SRM is now taking an extra dword to accommodate
9434 * 48bits addresses, and we need a NOOP for the batch size to
9435 * stay even.
9436 */
9437 if (IS_GEN8(dev))
9438 len += 2;
9439 }
9440
9441 /*
9442 * BSpec MI_DISPLAY_FLIP for IVB:
9443 * "The full packet must be contained within the same cache line."
9444 *
9445 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9446 * cacheline, if we ever start emitting more commands before
9447 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9448 * then do the cacheline alignment, and finally emit the
9449 * MI_DISPLAY_FLIP.
9450 */
9451 ret = intel_ring_cacheline_align(ring);
9452 if (ret)
9453 return ret;
9454
9455 ret = intel_ring_begin(ring, len);
9456 if (ret)
9457 return ret;
9458
9459 /* Unmask the flip-done completion message. Note that the bspec says that
9460 * we should do this for both the BCS and RCS, and that we must not unmask
9461 * more than one flip event at any time (or ensure that one flip message
9462 * can be sent by waiting for flip-done prior to queueing new flips).
9463 * Experimentation says that BCS works despite DERRMR masking all
9464 * flip-done completion events and that unmasking all planes at once
9465 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9466 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9467 */
9468 if (ring->id == RCS) {
9469 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9470 intel_ring_emit(ring, DERRMR);
9471 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9472 DERRMR_PIPEB_PRI_FLIP_DONE |
9473 DERRMR_PIPEC_PRI_FLIP_DONE));
9474 if (IS_GEN8(dev))
9475 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9476 MI_SRM_LRM_GLOBAL_GTT);
9477 else
9478 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9479 MI_SRM_LRM_GLOBAL_GTT);
9480 intel_ring_emit(ring, DERRMR);
9481 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9482 if (IS_GEN8(dev)) {
9483 intel_ring_emit(ring, 0);
9484 intel_ring_emit(ring, MI_NOOP);
9485 }
9486 }
9487
9488 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9489 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9490 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9491 intel_ring_emit(ring, (MI_NOOP));
9492
9493 intel_mark_page_flip_active(intel_crtc);
9494 __intel_ring_advance(ring);
9495 return 0;
9496}
9497
9498static bool use_mmio_flip(struct intel_engine_cs *ring,
9499 struct drm_i915_gem_object *obj)
9500{
9501 /*
9502 * This is not being used for older platforms, because
9503 * non-availability of flip done interrupt forces us to use
9504 * CS flips. Older platforms derive flip done using some clever
9505 * tricks involving the flip_pending status bits and vblank irqs.
9506 * So using MMIO flips there would disrupt this mechanism.
9507 */
9508
9509 if (ring == NULL)
9510 return true;
9511
9512 if (INTEL_INFO(ring->dev)->gen < 5)
9513 return false;
9514
9515 if (i915.use_mmio_flip < 0)
9516 return false;
9517 else if (i915.use_mmio_flip > 0)
9518 return true;
9519 else
9520 return ring != obj->ring;
9521}
9522
9523static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9524{
9525 struct drm_device *dev = intel_crtc->base.dev;
9526 struct drm_i915_private *dev_priv = dev->dev_private;
9527 struct intel_framebuffer *intel_fb =
9528 to_intel_framebuffer(intel_crtc->base.primary->fb);
9529 struct drm_i915_gem_object *obj = intel_fb->obj;
9530 u32 dspcntr;
9531 u32 reg;
9532
9533 intel_mark_page_flip_active(intel_crtc);
9534
9535 reg = DSPCNTR(intel_crtc->plane);
9536 dspcntr = I915_READ(reg);
9537
9538 if (INTEL_INFO(dev)->gen >= 4) {
9539 if (obj->tiling_mode != I915_TILING_NONE)
9540 dspcntr |= DISPPLANE_TILED;
9541 else
9542 dspcntr &= ~DISPPLANE_TILED;
9543 }
9544 I915_WRITE(reg, dspcntr);
9545
9546 I915_WRITE(DSPSURF(intel_crtc->plane),
9547 intel_crtc->unpin_work->gtt_offset);
9548 POSTING_READ(DSPSURF(intel_crtc->plane));
9549}
9550
9551static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9552{
9553 struct intel_engine_cs *ring;
9554 int ret;
9555
9556 lockdep_assert_held(&obj->base.dev->struct_mutex);
9557
9558 if (!obj->last_write_seqno)
9559 return 0;
9560
9561 ring = obj->ring;
9562
9563 if (i915_seqno_passed(ring->get_seqno(ring, true),
9564 obj->last_write_seqno))
9565 return 0;
9566
9567 ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9568 if (ret)
9569 return ret;
9570
9571 if (WARN_ON(!ring->irq_get(ring)))
9572 return 0;
9573
9574 return 1;
9575}
9576
9577void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9578{
9579 struct drm_i915_private *dev_priv = to_i915(ring->dev);
9580 struct intel_crtc *intel_crtc;
9581 unsigned long irq_flags;
9582 u32 seqno;
9583
9584 seqno = ring->get_seqno(ring, false);
9585
9586 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9587 for_each_intel_crtc(ring->dev, intel_crtc) {
9588 struct intel_mmio_flip *mmio_flip;
9589
9590 mmio_flip = &intel_crtc->mmio_flip;
9591 if (mmio_flip->seqno == 0)
9592 continue;
9593
9594 if (ring->id != mmio_flip->ring_id)
9595 continue;
9596
9597 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9598 intel_do_mmio_flip(intel_crtc);
9599 mmio_flip->seqno = 0;
9600 ring->irq_put(ring);
9601 }
9602 }
9603 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9604}
9605
9606static int intel_queue_mmio_flip(struct drm_device *dev,
9607 struct drm_crtc *crtc,
9608 struct drm_framebuffer *fb,
9609 struct drm_i915_gem_object *obj,
9610 struct intel_engine_cs *ring,
9611 uint32_t flags)
9612{
9613 struct drm_i915_private *dev_priv = dev->dev_private;
9614 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9615 unsigned long irq_flags;
9616 int ret;
9617
9618 if (WARN_ON(intel_crtc->mmio_flip.seqno))
9619 return -EBUSY;
9620
9621 ret = intel_postpone_flip(obj);
9622 if (ret < 0)
9623 return ret;
9624 if (ret == 0) {
9625 intel_do_mmio_flip(intel_crtc);
9626 return 0;
9627 }
9628
9629 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9630 intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9631 intel_crtc->mmio_flip.ring_id = obj->ring->id;
9632 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9633
9634 /*
9635 * Double check to catch cases where irq fired before
9636 * mmio flip data was ready
9637 */
9638 intel_notify_mmio_flip(obj->ring);
9639 return 0;
9640}
9641
9642static int intel_default_queue_flip(struct drm_device *dev,
9643 struct drm_crtc *crtc,
9644 struct drm_framebuffer *fb,
9645 struct drm_i915_gem_object *obj,
9646 struct intel_engine_cs *ring,
9647 uint32_t flags)
9648{
9649 return -ENODEV;
9650}
9651
9652static int intel_crtc_page_flip(struct drm_crtc *crtc,
9653 struct drm_framebuffer *fb,
9654 struct drm_pending_vblank_event *event,
9655 uint32_t page_flip_flags)
9656{
9657 struct drm_device *dev = crtc->dev;
9658 struct drm_i915_private *dev_priv = dev->dev_private;
9659 struct drm_framebuffer *old_fb = crtc->primary->fb;
9660 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9661 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9662 enum pipe pipe = intel_crtc->pipe;
9663 struct intel_unpin_work *work;
9664 struct intel_engine_cs *ring;
9665 unsigned long flags;
9666 int ret;
9667
9668 /*
9669 * drm_mode_page_flip_ioctl() should already catch this, but double
9670 * check to be safe. In the future we may enable pageflipping from
9671 * a disabled primary plane.
9672 */
9673 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9674 return -EBUSY;
9675
9676 /* Can't change pixel format via MI display flips. */
9677 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9678 return -EINVAL;
9679
9680 /*
9681 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9682 * Note that pitch changes could also affect these register.
9683 */
9684 if (INTEL_INFO(dev)->gen > 3 &&
9685 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9686 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9687 return -EINVAL;
9688
9689 if (i915_terminally_wedged(&dev_priv->gpu_error))
9690 goto out_hang;
9691
9692 work = kzalloc(sizeof(*work), GFP_KERNEL);
9693 if (work == NULL)
9694 return -ENOMEM;
9695
9696 work->event = event;
9697 work->crtc = crtc;
9698 work->old_fb_obj = intel_fb_obj(old_fb);
9699 INIT_WORK(&work->work, intel_unpin_work_fn);
9700
9701 ret = drm_crtc_vblank_get(crtc);
9702 if (ret)
9703 goto free_work;
9704
9705 /* We borrow the event spin lock for protecting unpin_work */
9706 spin_lock_irqsave(&dev->event_lock, flags);
9707 if (intel_crtc->unpin_work) {
9708 spin_unlock_irqrestore(&dev->event_lock, flags);
9709 kfree(work);
9710 drm_crtc_vblank_put(crtc);
9711
9712 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9713 return -EBUSY;
9714 }
9715 intel_crtc->unpin_work = work;
9716 spin_unlock_irqrestore(&dev->event_lock, flags);
9717
9718 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9719 flush_workqueue(dev_priv->wq);
9720
9721 ret = i915_mutex_lock_interruptible(dev);
9722 if (ret)
9723 goto cleanup;
9724
9725 /* Reference the objects for the scheduled work. */
9726 drm_gem_object_reference(&work->old_fb_obj->base);
9727 drm_gem_object_reference(&obj->base);
9728
9729 crtc->primary->fb = fb;
9730
9731 work->pending_flip_obj = obj;
9732
9733 work->enable_stall_check = true;
9734
9735 atomic_inc(&intel_crtc->unpin_work_count);
9736 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9737
9738 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9739 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9740
9741 if (IS_VALLEYVIEW(dev)) {
9742 ring = &dev_priv->ring[BCS];
9743 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9744 /* vlv: DISPLAY_FLIP fails to change tiling */
9745 ring = NULL;
9746 } else if (IS_IVYBRIDGE(dev)) {
9747 ring = &dev_priv->ring[BCS];
9748 } else if (INTEL_INFO(dev)->gen >= 7) {
9749 ring = obj->ring;
9750 if (ring == NULL || ring->id != RCS)
9751 ring = &dev_priv->ring[BCS];
9752 } else {
9753 ring = &dev_priv->ring[RCS];
9754 }
9755
9756 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9757 if (ret)
9758 goto cleanup_pending;
9759
9760 work->gtt_offset =
9761 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9762
9763 if (use_mmio_flip(ring, obj))
9764 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9765 page_flip_flags);
9766 else
9767 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9768 page_flip_flags);
9769 if (ret)
9770 goto cleanup_unpin;
9771
9772 i915_gem_track_fb(work->old_fb_obj, obj,
9773 INTEL_FRONTBUFFER_PRIMARY(pipe));
9774
9775 intel_disable_fbc(dev);
9776 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9777 mutex_unlock(&dev->struct_mutex);
9778
9779 trace_i915_flip_request(intel_crtc->plane, obj);
9780
9781 return 0;
9782
9783cleanup_unpin:
9784 intel_unpin_fb_obj(obj);
9785cleanup_pending:
9786 atomic_dec(&intel_crtc->unpin_work_count);
9787 crtc->primary->fb = old_fb;
9788 drm_gem_object_unreference(&work->old_fb_obj->base);
9789 drm_gem_object_unreference(&obj->base);
9790 mutex_unlock(&dev->struct_mutex);
9791
9792cleanup:
9793 spin_lock_irqsave(&dev->event_lock, flags);
9794 intel_crtc->unpin_work = NULL;
9795 spin_unlock_irqrestore(&dev->event_lock, flags);
9796
9797 drm_crtc_vblank_put(crtc);
9798free_work:
9799 kfree(work);
9800
9801 if (ret == -EIO) {
9802out_hang:
9803 intel_crtc_wait_for_pending_flips(crtc);
9804 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9805 if (ret == 0 && event)
9806 drm_send_vblank_event(dev, pipe, event);
9807 }
9808 return ret;
9809}
9810
9811static struct drm_crtc_helper_funcs intel_helper_funcs = {
9812 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9813 .load_lut = intel_crtc_load_lut,
9814};
9815
9816/**
9817 * intel_modeset_update_staged_output_state
9818 *
9819 * Updates the staged output configuration state, e.g. after we've read out the
9820 * current hw state.
9821 */
9822static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9823{
9824 struct intel_crtc *crtc;
9825 struct intel_encoder *encoder;
9826 struct intel_connector *connector;
9827
9828 list_for_each_entry(connector, &dev->mode_config.connector_list,
9829 base.head) {
9830 connector->new_encoder =
9831 to_intel_encoder(connector->base.encoder);
9832 }
9833
9834 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9835 base.head) {
9836 encoder->new_crtc =
9837 to_intel_crtc(encoder->base.crtc);
9838 }
9839
9840 for_each_intel_crtc(dev, crtc) {
9841 crtc->new_enabled = crtc->base.enabled;
9842
9843 if (crtc->new_enabled)
9844 crtc->new_config = &crtc->config;
9845 else
9846 crtc->new_config = NULL;
9847 }
9848}
9849
9850/**
9851 * intel_modeset_commit_output_state
9852 *
9853 * This function copies the stage display pipe configuration to the real one.
9854 */
9855static void intel_modeset_commit_output_state(struct drm_device *dev)
9856{
9857 struct intel_crtc *crtc;
9858 struct intel_encoder *encoder;
9859 struct intel_connector *connector;
9860
9861 list_for_each_entry(connector, &dev->mode_config.connector_list,
9862 base.head) {
9863 connector->base.encoder = &connector->new_encoder->base;
9864 }
9865
9866 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9867 base.head) {
9868 encoder->base.crtc = &encoder->new_crtc->base;
9869 }
9870
9871 for_each_intel_crtc(dev, crtc) {
9872 crtc->base.enabled = crtc->new_enabled;
9873 }
9874}
9875
9876static void
9877connected_sink_compute_bpp(struct intel_connector *connector,
9878 struct intel_crtc_config *pipe_config)
9879{
9880 int bpp = pipe_config->pipe_bpp;
9881
9882 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9883 connector->base.base.id,
9884 connector->base.name);
9885
9886 /* Don't use an invalid EDID bpc value */
9887 if (connector->base.display_info.bpc &&
9888 connector->base.display_info.bpc * 3 < bpp) {
9889 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9890 bpp, connector->base.display_info.bpc*3);
9891 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9892 }
9893
9894 /* Clamp bpp to 8 on screens without EDID 1.4 */
9895 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9896 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9897 bpp);
9898 pipe_config->pipe_bpp = 24;
9899 }
9900}
9901
9902static int
9903compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9904 struct drm_framebuffer *fb,
9905 struct intel_crtc_config *pipe_config)
9906{
9907 struct drm_device *dev = crtc->base.dev;
9908 struct intel_connector *connector;
9909 int bpp;
9910
9911 switch (fb->pixel_format) {
9912 case DRM_FORMAT_C8:
9913 bpp = 8*3; /* since we go through a colormap */
9914 break;
9915 case DRM_FORMAT_XRGB1555:
9916 case DRM_FORMAT_ARGB1555:
9917 /* checked in intel_framebuffer_init already */
9918 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9919 return -EINVAL;
9920 case DRM_FORMAT_RGB565:
9921 bpp = 6*3; /* min is 18bpp */
9922 break;
9923 case DRM_FORMAT_XBGR8888:
9924 case DRM_FORMAT_ABGR8888:
9925 /* checked in intel_framebuffer_init already */
9926 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9927 return -EINVAL;
9928 case DRM_FORMAT_XRGB8888:
9929 case DRM_FORMAT_ARGB8888:
9930 bpp = 8*3;
9931 break;
9932 case DRM_FORMAT_XRGB2101010:
9933 case DRM_FORMAT_ARGB2101010:
9934 case DRM_FORMAT_XBGR2101010:
9935 case DRM_FORMAT_ABGR2101010:
9936 /* checked in intel_framebuffer_init already */
9937 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9938 return -EINVAL;
9939 bpp = 10*3;
9940 break;
9941 /* TODO: gen4+ supports 16 bpc floating point, too. */
9942 default:
9943 DRM_DEBUG_KMS("unsupported depth\n");
9944 return -EINVAL;
9945 }
9946
9947 pipe_config->pipe_bpp = bpp;
9948
9949 /* Clamp display bpp to EDID value */
9950 list_for_each_entry(connector, &dev->mode_config.connector_list,
9951 base.head) {
9952 if (!connector->new_encoder ||
9953 connector->new_encoder->new_crtc != crtc)
9954 continue;
9955
9956 connected_sink_compute_bpp(connector, pipe_config);
9957 }
9958
9959 return bpp;
9960}
9961
9962static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9963{
9964 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9965 "type: 0x%x flags: 0x%x\n",
9966 mode->crtc_clock,
9967 mode->crtc_hdisplay, mode->crtc_hsync_start,
9968 mode->crtc_hsync_end, mode->crtc_htotal,
9969 mode->crtc_vdisplay, mode->crtc_vsync_start,
9970 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9971}
9972
9973static void intel_dump_pipe_config(struct intel_crtc *crtc,
9974 struct intel_crtc_config *pipe_config,
9975 const char *context)
9976{
9977 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9978 context, pipe_name(crtc->pipe));
9979
9980 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9981 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9982 pipe_config->pipe_bpp, pipe_config->dither);
9983 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9984 pipe_config->has_pch_encoder,
9985 pipe_config->fdi_lanes,
9986 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9987 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9988 pipe_config->fdi_m_n.tu);
9989 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9990 pipe_config->has_dp_encoder,
9991 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9992 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9993 pipe_config->dp_m_n.tu);
9994 DRM_DEBUG_KMS("requested mode:\n");
9995 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9996 DRM_DEBUG_KMS("adjusted mode:\n");
9997 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9998 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9999 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10000 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10001 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10002 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10003 pipe_config->gmch_pfit.control,
10004 pipe_config->gmch_pfit.pgm_ratios,
10005 pipe_config->gmch_pfit.lvds_border_bits);
10006 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10007 pipe_config->pch_pfit.pos,
10008 pipe_config->pch_pfit.size,
10009 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10010 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10011 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10012}
10013
10014static bool encoders_cloneable(const struct intel_encoder *a,
10015 const struct intel_encoder *b)
10016{
10017 /* masks could be asymmetric, so check both ways */
10018 return a == b || (a->cloneable & (1 << b->type) &&
10019 b->cloneable & (1 << a->type));
10020}
10021
10022static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10023 struct intel_encoder *encoder)
10024{
10025 struct drm_device *dev = crtc->base.dev;
10026 struct intel_encoder *source_encoder;
10027
10028 list_for_each_entry(source_encoder,
10029 &dev->mode_config.encoder_list, base.head) {
10030 if (source_encoder->new_crtc != crtc)
10031 continue;
10032
10033 if (!encoders_cloneable(encoder, source_encoder))
10034 return false;
10035 }
10036
10037 return true;
10038}
10039
10040static bool check_encoder_cloning(struct intel_crtc *crtc)
10041{
10042 struct drm_device *dev = crtc->base.dev;
10043 struct intel_encoder *encoder;
10044
10045 list_for_each_entry(encoder,
10046 &dev->mode_config.encoder_list, base.head) {
10047 if (encoder->new_crtc != crtc)
10048 continue;
10049
10050 if (!check_single_encoder_cloning(crtc, encoder))
10051 return false;
10052 }
10053
10054 return true;
10055}
10056
10057static struct intel_crtc_config *
10058intel_modeset_pipe_config(struct drm_crtc *crtc,
10059 struct drm_framebuffer *fb,
10060 struct drm_display_mode *mode)
10061{
10062 struct drm_device *dev = crtc->dev;
10063 struct intel_encoder *encoder;
10064 struct intel_crtc_config *pipe_config;
10065 int plane_bpp, ret = -EINVAL;
10066 bool retry = true;
10067
10068 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10069 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10070 return ERR_PTR(-EINVAL);
10071 }
10072
10073 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10074 if (!pipe_config)
10075 return ERR_PTR(-ENOMEM);
10076
10077 drm_mode_copy(&pipe_config->adjusted_mode, mode);
10078 drm_mode_copy(&pipe_config->requested_mode, mode);
10079
10080 pipe_config->cpu_transcoder =
10081 (enum transcoder) to_intel_crtc(crtc)->pipe;
10082 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10083
10084 /*
10085 * Sanitize sync polarity flags based on requested ones. If neither
10086 * positive or negative polarity is requested, treat this as meaning
10087 * negative polarity.
10088 */
10089 if (!(pipe_config->adjusted_mode.flags &
10090 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10091 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10092
10093 if (!(pipe_config->adjusted_mode.flags &
10094 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10095 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10096
10097 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10098 * plane pixel format and any sink constraints into account. Returns the
10099 * source plane bpp so that dithering can be selected on mismatches
10100 * after encoders and crtc also have had their say. */
10101 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10102 fb, pipe_config);
10103 if (plane_bpp < 0)
10104 goto fail;
10105
10106 /*
10107 * Determine the real pipe dimensions. Note that stereo modes can
10108 * increase the actual pipe size due to the frame doubling and
10109 * insertion of additional space for blanks between the frame. This
10110 * is stored in the crtc timings. We use the requested mode to do this
10111 * computation to clearly distinguish it from the adjusted mode, which
10112 * can be changed by the connectors in the below retry loop.
10113 */
10114 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10115 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10116 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10117
10118encoder_retry:
10119 /* Ensure the port clock defaults are reset when retrying. */
10120 pipe_config->port_clock = 0;
10121 pipe_config->pixel_multiplier = 1;
10122
10123 /* Fill in default crtc timings, allow encoders to overwrite them. */
10124 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10125
10126 /* Pass our mode to the connectors and the CRTC to give them a chance to
10127 * adjust it according to limitations or connector properties, and also
10128 * a chance to reject the mode entirely.
10129 */
10130 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10131 base.head) {
10132
10133 if (&encoder->new_crtc->base != crtc)
10134 continue;
10135
10136 if (!(encoder->compute_config(encoder, pipe_config))) {
10137 DRM_DEBUG_KMS("Encoder config failure\n");
10138 goto fail;
10139 }
10140 }
10141
10142 /* Set default port clock if not overwritten by the encoder. Needs to be
10143 * done afterwards in case the encoder adjusts the mode. */
10144 if (!pipe_config->port_clock)
10145 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10146 * pipe_config->pixel_multiplier;
10147
10148 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10149 if (ret < 0) {
10150 DRM_DEBUG_KMS("CRTC fixup failed\n");
10151 goto fail;
10152 }
10153
10154 if (ret == RETRY) {
10155 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10156 ret = -EINVAL;
10157 goto fail;
10158 }
10159
10160 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10161 retry = false;
10162 goto encoder_retry;
10163 }
10164
10165 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10166 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10167 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10168
10169 return pipe_config;
10170fail:
10171 kfree(pipe_config);
10172 return ERR_PTR(ret);
10173}
10174
10175/* Computes which crtcs are affected and sets the relevant bits in the mask. For
10176 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10177static void
10178intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10179 unsigned *prepare_pipes, unsigned *disable_pipes)
10180{
10181 struct intel_crtc *intel_crtc;
10182 struct drm_device *dev = crtc->dev;
10183 struct intel_encoder *encoder;
10184 struct intel_connector *connector;
10185 struct drm_crtc *tmp_crtc;
10186
10187 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10188
10189 /* Check which crtcs have changed outputs connected to them, these need
10190 * to be part of the prepare_pipes mask. We don't (yet) support global
10191 * modeset across multiple crtcs, so modeset_pipes will only have one
10192 * bit set at most. */
10193 list_for_each_entry(connector, &dev->mode_config.connector_list,
10194 base.head) {
10195 if (connector->base.encoder == &connector->new_encoder->base)
10196 continue;
10197
10198 if (connector->base.encoder) {
10199 tmp_crtc = connector->base.encoder->crtc;
10200
10201 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10202 }
10203
10204 if (connector->new_encoder)
10205 *prepare_pipes |=
10206 1 << connector->new_encoder->new_crtc->pipe;
10207 }
10208
10209 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10210 base.head) {
10211 if (encoder->base.crtc == &encoder->new_crtc->base)
10212 continue;
10213
10214 if (encoder->base.crtc) {
10215 tmp_crtc = encoder->base.crtc;
10216
10217 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10218 }
10219
10220 if (encoder->new_crtc)
10221 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10222 }
10223
10224 /* Check for pipes that will be enabled/disabled ... */
10225 for_each_intel_crtc(dev, intel_crtc) {
10226 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10227 continue;
10228
10229 if (!intel_crtc->new_enabled)
10230 *disable_pipes |= 1 << intel_crtc->pipe;
10231 else
10232 *prepare_pipes |= 1 << intel_crtc->pipe;
10233 }
10234
10235
10236 /* set_mode is also used to update properties on life display pipes. */
10237 intel_crtc = to_intel_crtc(crtc);
10238 if (intel_crtc->new_enabled)
10239 *prepare_pipes |= 1 << intel_crtc->pipe;
10240
10241 /*
10242 * For simplicity do a full modeset on any pipe where the output routing
10243 * changed. We could be more clever, but that would require us to be
10244 * more careful with calling the relevant encoder->mode_set functions.
10245 */
10246 if (*prepare_pipes)
10247 *modeset_pipes = *prepare_pipes;
10248
10249 /* ... and mask these out. */
10250 *modeset_pipes &= ~(*disable_pipes);
10251 *prepare_pipes &= ~(*disable_pipes);
10252
10253 /*
10254 * HACK: We don't (yet) fully support global modesets. intel_set_config
10255 * obies this rule, but the modeset restore mode of
10256 * intel_modeset_setup_hw_state does not.
10257 */
10258 *modeset_pipes &= 1 << intel_crtc->pipe;
10259 *prepare_pipes &= 1 << intel_crtc->pipe;
10260
10261 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10262 *modeset_pipes, *prepare_pipes, *disable_pipes);
10263}
10264
10265static bool intel_crtc_in_use(struct drm_crtc *crtc)
10266{
10267 struct drm_encoder *encoder;
10268 struct drm_device *dev = crtc->dev;
10269
10270 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10271 if (encoder->crtc == crtc)
10272 return true;
10273
10274 return false;
10275}
10276
10277static void
10278intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10279{
10280 struct intel_encoder *intel_encoder;
10281 struct intel_crtc *intel_crtc;
10282 struct drm_connector *connector;
10283
10284 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
10285 base.head) {
10286 if (!intel_encoder->base.crtc)
10287 continue;
10288
10289 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10290
10291 if (prepare_pipes & (1 << intel_crtc->pipe))
10292 intel_encoder->connectors_active = false;
10293 }
10294
10295 intel_modeset_commit_output_state(dev);
10296
10297 /* Double check state. */
10298 for_each_intel_crtc(dev, intel_crtc) {
10299 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10300 WARN_ON(intel_crtc->new_config &&
10301 intel_crtc->new_config != &intel_crtc->config);
10302 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10303 }
10304
10305 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10306 if (!connector->encoder || !connector->encoder->crtc)
10307 continue;
10308
10309 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10310
10311 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10312 struct drm_property *dpms_property =
10313 dev->mode_config.dpms_property;
10314
10315 connector->dpms = DRM_MODE_DPMS_ON;
10316 drm_object_property_set_value(&connector->base,
10317 dpms_property,
10318 DRM_MODE_DPMS_ON);
10319
10320 intel_encoder = to_intel_encoder(connector->encoder);
10321 intel_encoder->connectors_active = true;
10322 }
10323 }
10324
10325}
10326
10327static bool intel_fuzzy_clock_check(int clock1, int clock2)
10328{
10329 int diff;
10330
10331 if (clock1 == clock2)
10332 return true;
10333
10334 if (!clock1 || !clock2)
10335 return false;
10336
10337 diff = abs(clock1 - clock2);
10338
10339 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10340 return true;
10341
10342 return false;
10343}
10344
10345#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10346 list_for_each_entry((intel_crtc), \
10347 &(dev)->mode_config.crtc_list, \
10348 base.head) \
10349 if (mask & (1 <<(intel_crtc)->pipe))
10350
10351static bool
10352intel_pipe_config_compare(struct drm_device *dev,
10353 struct intel_crtc_config *current_config,
10354 struct intel_crtc_config *pipe_config)
10355{
10356#define PIPE_CONF_CHECK_X(name) \
10357 if (current_config->name != pipe_config->name) { \
10358 DRM_ERROR("mismatch in " #name " " \
10359 "(expected 0x%08x, found 0x%08x)\n", \
10360 current_config->name, \
10361 pipe_config->name); \
10362 return false; \
10363 }
10364
10365#define PIPE_CONF_CHECK_I(name) \
10366 if (current_config->name != pipe_config->name) { \
10367 DRM_ERROR("mismatch in " #name " " \
10368 "(expected %i, found %i)\n", \
10369 current_config->name, \
10370 pipe_config->name); \
10371 return false; \
10372 }
10373
10374#define PIPE_CONF_CHECK_FLAGS(name, mask) \
10375 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10376 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10377 "(expected %i, found %i)\n", \
10378 current_config->name & (mask), \
10379 pipe_config->name & (mask)); \
10380 return false; \
10381 }
10382
10383#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10384 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10385 DRM_ERROR("mismatch in " #name " " \
10386 "(expected %i, found %i)\n", \
10387 current_config->name, \
10388 pipe_config->name); \
10389 return false; \
10390 }
10391
10392#define PIPE_CONF_QUIRK(quirk) \
10393 ((current_config->quirks | pipe_config->quirks) & (quirk))
10394
10395 PIPE_CONF_CHECK_I(cpu_transcoder);
10396
10397 PIPE_CONF_CHECK_I(has_pch_encoder);
10398 PIPE_CONF_CHECK_I(fdi_lanes);
10399 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10400 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10401 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10402 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10403 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10404
10405 PIPE_CONF_CHECK_I(has_dp_encoder);
10406 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10407 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10408 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10409 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10410 PIPE_CONF_CHECK_I(dp_m_n.tu);
10411
10412 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10413 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10414 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10415 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10416 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10417 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10418
10419 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10420 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10421 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10422 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10423 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10424 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10425
10426 PIPE_CONF_CHECK_I(pixel_multiplier);
10427 PIPE_CONF_CHECK_I(has_hdmi_sink);
10428 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10429 IS_VALLEYVIEW(dev))
10430 PIPE_CONF_CHECK_I(limited_color_range);
10431
10432 PIPE_CONF_CHECK_I(has_audio);
10433
10434 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10435 DRM_MODE_FLAG_INTERLACE);
10436
10437 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10438 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10439 DRM_MODE_FLAG_PHSYNC);
10440 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10441 DRM_MODE_FLAG_NHSYNC);
10442 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10443 DRM_MODE_FLAG_PVSYNC);
10444 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10445 DRM_MODE_FLAG_NVSYNC);
10446 }
10447
10448 PIPE_CONF_CHECK_I(pipe_src_w);
10449 PIPE_CONF_CHECK_I(pipe_src_h);
10450
10451 /*
10452 * FIXME: BIOS likes to set up a cloned config with lvds+external
10453 * screen. Since we don't yet re-compute the pipe config when moving
10454 * just the lvds port away to another pipe the sw tracking won't match.
10455 *
10456 * Proper atomic modesets with recomputed global state will fix this.
10457 * Until then just don't check gmch state for inherited modes.
10458 */
10459 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10460 PIPE_CONF_CHECK_I(gmch_pfit.control);
10461 /* pfit ratios are autocomputed by the hw on gen4+ */
10462 if (INTEL_INFO(dev)->gen < 4)
10463 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10464 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10465 }
10466
10467 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10468 if (current_config->pch_pfit.enabled) {
10469 PIPE_CONF_CHECK_I(pch_pfit.pos);
10470 PIPE_CONF_CHECK_I(pch_pfit.size);
10471 }
10472
10473 /* BDW+ don't expose a synchronous way to read the state */
10474 if (IS_HASWELL(dev))
10475 PIPE_CONF_CHECK_I(ips_enabled);
10476
10477 PIPE_CONF_CHECK_I(double_wide);
10478
10479 PIPE_CONF_CHECK_X(ddi_pll_sel);
10480
10481 PIPE_CONF_CHECK_I(shared_dpll);
10482 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10483 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10484 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10485 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10486 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10487
10488 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10489 PIPE_CONF_CHECK_I(pipe_bpp);
10490
10491 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10492 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10493
10494#undef PIPE_CONF_CHECK_X
10495#undef PIPE_CONF_CHECK_I
10496#undef PIPE_CONF_CHECK_FLAGS
10497#undef PIPE_CONF_CHECK_CLOCK_FUZZY
10498#undef PIPE_CONF_QUIRK
10499
10500 return true;
10501}
10502
10503static void
10504check_connector_state(struct drm_device *dev)
10505{
10506 struct intel_connector *connector;
10507
10508 list_for_each_entry(connector, &dev->mode_config.connector_list,
10509 base.head) {
10510 /* This also checks the encoder/connector hw state with the
10511 * ->get_hw_state callbacks. */
10512 intel_connector_check_state(connector);
10513
10514 WARN(&connector->new_encoder->base != connector->base.encoder,
10515 "connector's staged encoder doesn't match current encoder\n");
10516 }
10517}
10518
10519static void
10520check_encoder_state(struct drm_device *dev)
10521{
10522 struct intel_encoder *encoder;
10523 struct intel_connector *connector;
10524
10525 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10526 base.head) {
10527 bool enabled = false;
10528 bool active = false;
10529 enum pipe pipe, tracked_pipe;
10530
10531 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10532 encoder->base.base.id,
10533 encoder->base.name);
10534
10535 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10536 "encoder's stage crtc doesn't match current crtc\n");
10537 WARN(encoder->connectors_active && !encoder->base.crtc,
10538 "encoder's active_connectors set, but no crtc\n");
10539
10540 list_for_each_entry(connector, &dev->mode_config.connector_list,
10541 base.head) {
10542 if (connector->base.encoder != &encoder->base)
10543 continue;
10544 enabled = true;
10545 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10546 active = true;
10547 }
10548 /*
10549 * for MST connectors if we unplug the connector is gone
10550 * away but the encoder is still connected to a crtc
10551 * until a modeset happens in response to the hotplug.
10552 */
10553 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10554 continue;
10555
10556 WARN(!!encoder->base.crtc != enabled,
10557 "encoder's enabled state mismatch "
10558 "(expected %i, found %i)\n",
10559 !!encoder->base.crtc, enabled);
10560 WARN(active && !encoder->base.crtc,
10561 "active encoder with no crtc\n");
10562
10563 WARN(encoder->connectors_active != active,
10564 "encoder's computed active state doesn't match tracked active state "
10565 "(expected %i, found %i)\n", active, encoder->connectors_active);
10566
10567 active = encoder->get_hw_state(encoder, &pipe);
10568 WARN(active != encoder->connectors_active,
10569 "encoder's hw state doesn't match sw tracking "
10570 "(expected %i, found %i)\n",
10571 encoder->connectors_active, active);
10572
10573 if (!encoder->base.crtc)
10574 continue;
10575
10576 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10577 WARN(active && pipe != tracked_pipe,
10578 "active encoder's pipe doesn't match"
10579 "(expected %i, found %i)\n",
10580 tracked_pipe, pipe);
10581
10582 }
10583}
10584
10585static void
10586check_crtc_state(struct drm_device *dev)
10587{
10588 struct drm_i915_private *dev_priv = dev->dev_private;
10589 struct intel_crtc *crtc;
10590 struct intel_encoder *encoder;
10591 struct intel_crtc_config pipe_config;
10592
10593 for_each_intel_crtc(dev, crtc) {
10594 bool enabled = false;
10595 bool active = false;
10596
10597 memset(&pipe_config, 0, sizeof(pipe_config));
10598
10599 DRM_DEBUG_KMS("[CRTC:%d]\n",
10600 crtc->base.base.id);
10601
10602 WARN(crtc->active && !crtc->base.enabled,
10603 "active crtc, but not enabled in sw tracking\n");
10604
10605 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10606 base.head) {
10607 if (encoder->base.crtc != &crtc->base)
10608 continue;
10609 enabled = true;
10610 if (encoder->connectors_active)
10611 active = true;
10612 }
10613
10614 WARN(active != crtc->active,
10615 "crtc's computed active state doesn't match tracked active state "
10616 "(expected %i, found %i)\n", active, crtc->active);
10617 WARN(enabled != crtc->base.enabled,
10618 "crtc's computed enabled state doesn't match tracked enabled state "
10619 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10620
10621 active = dev_priv->display.get_pipe_config(crtc,
10622 &pipe_config);
10623
10624 /* hw state is inconsistent with the pipe A quirk */
10625 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10626 active = crtc->active;
10627
10628 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10629 base.head) {
10630 enum pipe pipe;
10631 if (encoder->base.crtc != &crtc->base)
10632 continue;
10633 if (encoder->get_hw_state(encoder, &pipe))
10634 encoder->get_config(encoder, &pipe_config);
10635 }
10636
10637 WARN(crtc->active != active,
10638 "crtc active state doesn't match with hw state "
10639 "(expected %i, found %i)\n", crtc->active, active);
10640
10641 if (active &&
10642 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10643 WARN(1, "pipe state doesn't match!\n");
10644 intel_dump_pipe_config(crtc, &pipe_config,
10645 "[hw state]");
10646 intel_dump_pipe_config(crtc, &crtc->config,
10647 "[sw state]");
10648 }
10649 }
10650}
10651
10652static void
10653check_shared_dpll_state(struct drm_device *dev)
10654{
10655 struct drm_i915_private *dev_priv = dev->dev_private;
10656 struct intel_crtc *crtc;
10657 struct intel_dpll_hw_state dpll_hw_state;
10658 int i;
10659
10660 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10661 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10662 int enabled_crtcs = 0, active_crtcs = 0;
10663 bool active;
10664
10665 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10666
10667 DRM_DEBUG_KMS("%s\n", pll->name);
10668
10669 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10670
10671 WARN(pll->active > pll->refcount,
10672 "more active pll users than references: %i vs %i\n",
10673 pll->active, pll->refcount);
10674 WARN(pll->active && !pll->on,
10675 "pll in active use but not on in sw tracking\n");
10676 WARN(pll->on && !pll->active,
10677 "pll in on but not on in use in sw tracking\n");
10678 WARN(pll->on != active,
10679 "pll on state mismatch (expected %i, found %i)\n",
10680 pll->on, active);
10681
10682 for_each_intel_crtc(dev, crtc) {
10683 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10684 enabled_crtcs++;
10685 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10686 active_crtcs++;
10687 }
10688 WARN(pll->active != active_crtcs,
10689 "pll active crtcs mismatch (expected %i, found %i)\n",
10690 pll->active, active_crtcs);
10691 WARN(pll->refcount != enabled_crtcs,
10692 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10693 pll->refcount, enabled_crtcs);
10694
10695 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10696 sizeof(dpll_hw_state)),
10697 "pll hw state mismatch\n");
10698 }
10699}
10700
10701void
10702intel_modeset_check_state(struct drm_device *dev)
10703{
10704 check_connector_state(dev);
10705 check_encoder_state(dev);
10706 check_crtc_state(dev);
10707 check_shared_dpll_state(dev);
10708}
10709
10710void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10711 int dotclock)
10712{
10713 /*
10714 * FDI already provided one idea for the dotclock.
10715 * Yell if the encoder disagrees.
10716 */
10717 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10718 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10719 pipe_config->adjusted_mode.crtc_clock, dotclock);
10720}
10721
10722static void update_scanline_offset(struct intel_crtc *crtc)
10723{
10724 struct drm_device *dev = crtc->base.dev;
10725
10726 /*
10727 * The scanline counter increments at the leading edge of hsync.
10728 *
10729 * On most platforms it starts counting from vtotal-1 on the
10730 * first active line. That means the scanline counter value is
10731 * always one less than what we would expect. Ie. just after
10732 * start of vblank, which also occurs at start of hsync (on the
10733 * last active line), the scanline counter will read vblank_start-1.
10734 *
10735 * On gen2 the scanline counter starts counting from 1 instead
10736 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10737 * to keep the value positive), instead of adding one.
10738 *
10739 * On HSW+ the behaviour of the scanline counter depends on the output
10740 * type. For DP ports it behaves like most other platforms, but on HDMI
10741 * there's an extra 1 line difference. So we need to add two instead of
10742 * one to the value.
10743 */
10744 if (IS_GEN2(dev)) {
10745 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10746 int vtotal;
10747
10748 vtotal = mode->crtc_vtotal;
10749 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10750 vtotal /= 2;
10751
10752 crtc->scanline_offset = vtotal - 1;
10753 } else if (HAS_DDI(dev) &&
10754 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
10755 crtc->scanline_offset = 2;
10756 } else
10757 crtc->scanline_offset = 1;
10758}
10759
10760static int __intel_set_mode(struct drm_crtc *crtc,
10761 struct drm_display_mode *mode,
10762 int x, int y, struct drm_framebuffer *fb)
10763{
10764 struct drm_device *dev = crtc->dev;
10765 struct drm_i915_private *dev_priv = dev->dev_private;
10766 struct drm_display_mode *saved_mode;
10767 struct intel_crtc_config *pipe_config = NULL;
10768 struct intel_crtc *intel_crtc;
10769 unsigned disable_pipes, prepare_pipes, modeset_pipes;
10770 int ret = 0;
10771
10772 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10773 if (!saved_mode)
10774 return -ENOMEM;
10775
10776 intel_modeset_affected_pipes(crtc, &modeset_pipes,
10777 &prepare_pipes, &disable_pipes);
10778
10779 *saved_mode = crtc->mode;
10780
10781 /* Hack: Because we don't (yet) support global modeset on multiple
10782 * crtcs, we don't keep track of the new mode for more than one crtc.
10783 * Hence simply check whether any bit is set in modeset_pipes in all the
10784 * pieces of code that are not yet converted to deal with mutliple crtcs
10785 * changing their mode at the same time. */
10786 if (modeset_pipes) {
10787 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10788 if (IS_ERR(pipe_config)) {
10789 ret = PTR_ERR(pipe_config);
10790 pipe_config = NULL;
10791
10792 goto out;
10793 }
10794 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10795 "[modeset]");
10796 to_intel_crtc(crtc)->new_config = pipe_config;
10797 }
10798
10799 /*
10800 * See if the config requires any additional preparation, e.g.
10801 * to adjust global state with pipes off. We need to do this
10802 * here so we can get the modeset_pipe updated config for the new
10803 * mode set on this crtc. For other crtcs we need to use the
10804 * adjusted_mode bits in the crtc directly.
10805 */
10806 if (IS_VALLEYVIEW(dev)) {
10807 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10808
10809 /* may have added more to prepare_pipes than we should */
10810 prepare_pipes &= ~disable_pipes;
10811 }
10812
10813 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10814 intel_crtc_disable(&intel_crtc->base);
10815
10816 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10817 if (intel_crtc->base.enabled)
10818 dev_priv->display.crtc_disable(&intel_crtc->base);
10819 }
10820
10821 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10822 * to set it here already despite that we pass it down the callchain.
10823 */
10824 if (modeset_pipes) {
10825 crtc->mode = *mode;
10826 /* mode_set/enable/disable functions rely on a correct pipe
10827 * config. */
10828 to_intel_crtc(crtc)->config = *pipe_config;
10829 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10830
10831 /*
10832 * Calculate and store various constants which
10833 * are later needed by vblank and swap-completion
10834 * timestamping. They are derived from true hwmode.
10835 */
10836 drm_calc_timestamping_constants(crtc,
10837 &pipe_config->adjusted_mode);
10838 }
10839
10840 /* Only after disabling all output pipelines that will be changed can we
10841 * update the the output configuration. */
10842 intel_modeset_update_state(dev, prepare_pipes);
10843
10844 if (dev_priv->display.modeset_global_resources)
10845 dev_priv->display.modeset_global_resources(dev);
10846
10847 /* Set up the DPLL and any encoders state that needs to adjust or depend
10848 * on the DPLL.
10849 */
10850 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10851 struct drm_framebuffer *old_fb = crtc->primary->fb;
10852 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
10853 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10854
10855 mutex_lock(&dev->struct_mutex);
10856 ret = intel_pin_and_fence_fb_obj(dev,
10857 obj,
10858 NULL);
10859 if (ret != 0) {
10860 DRM_ERROR("pin & fence failed\n");
10861 mutex_unlock(&dev->struct_mutex);
10862 goto done;
10863 }
10864 if (old_fb)
10865 intel_unpin_fb_obj(old_obj);
10866 i915_gem_track_fb(old_obj, obj,
10867 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
10868 mutex_unlock(&dev->struct_mutex);
10869
10870 crtc->primary->fb = fb;
10871 crtc->x = x;
10872 crtc->y = y;
10873
10874 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
10875 x, y, fb);
10876 if (ret)
10877 goto done;
10878 }
10879
10880 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10881 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10882 update_scanline_offset(intel_crtc);
10883
10884 dev_priv->display.crtc_enable(&intel_crtc->base);
10885 }
10886
10887 /* FIXME: add subpixel order */
10888done:
10889 if (ret && crtc->enabled)
10890 crtc->mode = *saved_mode;
10891
10892out:
10893 kfree(pipe_config);
10894 kfree(saved_mode);
10895 return ret;
10896}
10897
10898static int intel_set_mode(struct drm_crtc *crtc,
10899 struct drm_display_mode *mode,
10900 int x, int y, struct drm_framebuffer *fb)
10901{
10902 int ret;
10903
10904 ret = __intel_set_mode(crtc, mode, x, y, fb);
10905
10906 if (ret == 0)
10907 intel_modeset_check_state(crtc->dev);
10908
10909 return ret;
10910}
10911
10912void intel_crtc_restore_mode(struct drm_crtc *crtc)
10913{
10914 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10915}
10916
10917#undef for_each_intel_crtc_masked
10918
10919static void intel_set_config_free(struct intel_set_config *config)
10920{
10921 if (!config)
10922 return;
10923
10924 kfree(config->save_connector_encoders);
10925 kfree(config->save_encoder_crtcs);
10926 kfree(config->save_crtc_enabled);
10927 kfree(config);
10928}
10929
10930static int intel_set_config_save_state(struct drm_device *dev,
10931 struct intel_set_config *config)
10932{
10933 struct drm_crtc *crtc;
10934 struct drm_encoder *encoder;
10935 struct drm_connector *connector;
10936 int count;
10937
10938 config->save_crtc_enabled =
10939 kcalloc(dev->mode_config.num_crtc,
10940 sizeof(bool), GFP_KERNEL);
10941 if (!config->save_crtc_enabled)
10942 return -ENOMEM;
10943
10944 config->save_encoder_crtcs =
10945 kcalloc(dev->mode_config.num_encoder,
10946 sizeof(struct drm_crtc *), GFP_KERNEL);
10947 if (!config->save_encoder_crtcs)
10948 return -ENOMEM;
10949
10950 config->save_connector_encoders =
10951 kcalloc(dev->mode_config.num_connector,
10952 sizeof(struct drm_encoder *), GFP_KERNEL);
10953 if (!config->save_connector_encoders)
10954 return -ENOMEM;
10955
10956 /* Copy data. Note that driver private data is not affected.
10957 * Should anything bad happen only the expected state is
10958 * restored, not the drivers personal bookkeeping.
10959 */
10960 count = 0;
10961 for_each_crtc(dev, crtc) {
10962 config->save_crtc_enabled[count++] = crtc->enabled;
10963 }
10964
10965 count = 0;
10966 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10967 config->save_encoder_crtcs[count++] = encoder->crtc;
10968 }
10969
10970 count = 0;
10971 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10972 config->save_connector_encoders[count++] = connector->encoder;
10973 }
10974
10975 return 0;
10976}
10977
10978static void intel_set_config_restore_state(struct drm_device *dev,
10979 struct intel_set_config *config)
10980{
10981 struct intel_crtc *crtc;
10982 struct intel_encoder *encoder;
10983 struct intel_connector *connector;
10984 int count;
10985
10986 count = 0;
10987 for_each_intel_crtc(dev, crtc) {
10988 crtc->new_enabled = config->save_crtc_enabled[count++];
10989
10990 if (crtc->new_enabled)
10991 crtc->new_config = &crtc->config;
10992 else
10993 crtc->new_config = NULL;
10994 }
10995
10996 count = 0;
10997 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10998 encoder->new_crtc =
10999 to_intel_crtc(config->save_encoder_crtcs[count++]);
11000 }
11001
11002 count = 0;
11003 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11004 connector->new_encoder =
11005 to_intel_encoder(config->save_connector_encoders[count++]);
11006 }
11007}
11008
11009static bool
11010is_crtc_connector_off(struct drm_mode_set *set)
11011{
11012 int i;
11013
11014 if (set->num_connectors == 0)
11015 return false;
11016
11017 if (WARN_ON(set->connectors == NULL))
11018 return false;
11019
11020 for (i = 0; i < set->num_connectors; i++)
11021 if (set->connectors[i]->encoder &&
11022 set->connectors[i]->encoder->crtc == set->crtc &&
11023 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11024 return true;
11025
11026 return false;
11027}
11028
11029static void
11030intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11031 struct intel_set_config *config)
11032{
11033
11034 /* We should be able to check here if the fb has the same properties
11035 * and then just flip_or_move it */
11036 if (is_crtc_connector_off(set)) {
11037 config->mode_changed = true;
11038 } else if (set->crtc->primary->fb != set->fb) {
11039 /*
11040 * If we have no fb, we can only flip as long as the crtc is
11041 * active, otherwise we need a full mode set. The crtc may
11042 * be active if we've only disabled the primary plane, or
11043 * in fastboot situations.
11044 */
11045 if (set->crtc->primary->fb == NULL) {
11046 struct intel_crtc *intel_crtc =
11047 to_intel_crtc(set->crtc);
11048
11049 if (intel_crtc->active) {
11050 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11051 config->fb_changed = true;
11052 } else {
11053 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11054 config->mode_changed = true;
11055 }
11056 } else if (set->fb == NULL) {
11057 config->mode_changed = true;
11058 } else if (set->fb->pixel_format !=
11059 set->crtc->primary->fb->pixel_format) {
11060 config->mode_changed = true;
11061 } else {
11062 config->fb_changed = true;
11063 }
11064 }
11065
11066 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11067 config->fb_changed = true;
11068
11069 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11070 DRM_DEBUG_KMS("modes are different, full mode set\n");
11071 drm_mode_debug_printmodeline(&set->crtc->mode);
11072 drm_mode_debug_printmodeline(set->mode);
11073 config->mode_changed = true;
11074 }
11075
11076 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11077 set->crtc->base.id, config->mode_changed, config->fb_changed);
11078}
11079
11080static int
11081intel_modeset_stage_output_state(struct drm_device *dev,
11082 struct drm_mode_set *set,
11083 struct intel_set_config *config)
11084{
11085 struct intel_connector *connector;
11086 struct intel_encoder *encoder;
11087 struct intel_crtc *crtc;
11088 int ro;
11089
11090 /* The upper layers ensure that we either disable a crtc or have a list
11091 * of connectors. For paranoia, double-check this. */
11092 WARN_ON(!set->fb && (set->num_connectors != 0));
11093 WARN_ON(set->fb && (set->num_connectors == 0));
11094
11095 list_for_each_entry(connector, &dev->mode_config.connector_list,
11096 base.head) {
11097 /* Otherwise traverse passed in connector list and get encoders
11098 * for them. */
11099 for (ro = 0; ro < set->num_connectors; ro++) {
11100 if (set->connectors[ro] == &connector->base) {
11101 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11102 break;
11103 }
11104 }
11105
11106 /* If we disable the crtc, disable all its connectors. Also, if
11107 * the connector is on the changing crtc but not on the new
11108 * connector list, disable it. */
11109 if ((!set->fb || ro == set->num_connectors) &&
11110 connector->base.encoder &&
11111 connector->base.encoder->crtc == set->crtc) {
11112 connector->new_encoder = NULL;
11113
11114 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11115 connector->base.base.id,
11116 connector->base.name);
11117 }
11118
11119
11120 if (&connector->new_encoder->base != connector->base.encoder) {
11121 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11122 config->mode_changed = true;
11123 }
11124 }
11125 /* connector->new_encoder is now updated for all connectors. */
11126
11127 /* Update crtc of enabled connectors. */
11128 list_for_each_entry(connector, &dev->mode_config.connector_list,
11129 base.head) {
11130 struct drm_crtc *new_crtc;
11131
11132 if (!connector->new_encoder)
11133 continue;
11134
11135 new_crtc = connector->new_encoder->base.crtc;
11136
11137 for (ro = 0; ro < set->num_connectors; ro++) {
11138 if (set->connectors[ro] == &connector->base)
11139 new_crtc = set->crtc;
11140 }
11141
11142 /* Make sure the new CRTC will work with the encoder */
11143 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11144 new_crtc)) {
11145 return -EINVAL;
11146 }
11147 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11148
11149 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11150 connector->base.base.id,
11151 connector->base.name,
11152 new_crtc->base.id);
11153 }
11154
11155 /* Check for any encoders that needs to be disabled. */
11156 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11157 base.head) {
11158 int num_connectors = 0;
11159 list_for_each_entry(connector,
11160 &dev->mode_config.connector_list,
11161 base.head) {
11162 if (connector->new_encoder == encoder) {
11163 WARN_ON(!connector->new_encoder->new_crtc);
11164 num_connectors++;
11165 }
11166 }
11167
11168 if (num_connectors == 0)
11169 encoder->new_crtc = NULL;
11170 else if (num_connectors > 1)
11171 return -EINVAL;
11172
11173 /* Only now check for crtc changes so we don't miss encoders
11174 * that will be disabled. */
11175 if (&encoder->new_crtc->base != encoder->base.crtc) {
11176 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11177 config->mode_changed = true;
11178 }
11179 }
11180 /* Now we've also updated encoder->new_crtc for all encoders. */
11181 list_for_each_entry(connector, &dev->mode_config.connector_list,
11182 base.head) {
11183 if (connector->new_encoder)
11184 if (connector->new_encoder != connector->encoder)
11185 connector->encoder = connector->new_encoder;
11186 }
11187 for_each_intel_crtc(dev, crtc) {
11188 crtc->new_enabled = false;
11189
11190 list_for_each_entry(encoder,
11191 &dev->mode_config.encoder_list,
11192 base.head) {
11193 if (encoder->new_crtc == crtc) {
11194 crtc->new_enabled = true;
11195 break;
11196 }
11197 }
11198
11199 if (crtc->new_enabled != crtc->base.enabled) {
11200 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11201 crtc->new_enabled ? "en" : "dis");
11202 config->mode_changed = true;
11203 }
11204
11205 if (crtc->new_enabled)
11206 crtc->new_config = &crtc->config;
11207 else
11208 crtc->new_config = NULL;
11209 }
11210
11211 return 0;
11212}
11213
11214static void disable_crtc_nofb(struct intel_crtc *crtc)
11215{
11216 struct drm_device *dev = crtc->base.dev;
11217 struct intel_encoder *encoder;
11218 struct intel_connector *connector;
11219
11220 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11221 pipe_name(crtc->pipe));
11222
11223 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11224 if (connector->new_encoder &&
11225 connector->new_encoder->new_crtc == crtc)
11226 connector->new_encoder = NULL;
11227 }
11228
11229 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11230 if (encoder->new_crtc == crtc)
11231 encoder->new_crtc = NULL;
11232 }
11233
11234 crtc->new_enabled = false;
11235 crtc->new_config = NULL;
11236}
11237
11238static int intel_crtc_set_config(struct drm_mode_set *set)
11239{
11240 struct drm_device *dev;
11241 struct drm_mode_set save_set;
11242 struct intel_set_config *config;
11243 int ret;
11244
11245 BUG_ON(!set);
11246 BUG_ON(!set->crtc);
11247 BUG_ON(!set->crtc->helper_private);
11248
11249 /* Enforce sane interface api - has been abused by the fb helper. */
11250 BUG_ON(!set->mode && set->fb);
11251 BUG_ON(set->fb && set->num_connectors == 0);
11252
11253 if (set->fb) {
11254 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11255 set->crtc->base.id, set->fb->base.id,
11256 (int)set->num_connectors, set->x, set->y);
11257 } else {
11258 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11259 }
11260
11261 dev = set->crtc->dev;
11262
11263 ret = -ENOMEM;
11264 config = kzalloc(sizeof(*config), GFP_KERNEL);
11265 if (!config)
11266 goto out_config;
11267
11268 ret = intel_set_config_save_state(dev, config);
11269 if (ret)
11270 goto out_config;
11271
11272 save_set.crtc = set->crtc;
11273 save_set.mode = &set->crtc->mode;
11274 save_set.x = set->crtc->x;
11275 save_set.y = set->crtc->y;
11276 save_set.fb = set->crtc->primary->fb;
11277
11278 /* Compute whether we need a full modeset, only an fb base update or no
11279 * change at all. In the future we might also check whether only the
11280 * mode changed, e.g. for LVDS where we only change the panel fitter in
11281 * such cases. */
11282 intel_set_config_compute_mode_changes(set, config);
11283
11284 ret = intel_modeset_stage_output_state(dev, set, config);
11285 if (ret)
11286 goto fail;
11287
11288 if (config->mode_changed) {
11289 ret = intel_set_mode(set->crtc, set->mode,
11290 set->x, set->y, set->fb);
11291 } else if (config->fb_changed) {
11292 struct drm_i915_private *dev_priv = dev->dev_private;
11293 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11294
11295 intel_crtc_wait_for_pending_flips(set->crtc);
11296
11297 ret = intel_pipe_set_base(set->crtc,
11298 set->x, set->y, set->fb);
11299
11300 /*
11301 * We need to make sure the primary plane is re-enabled if it
11302 * has previously been turned off.
11303 */
11304 if (!intel_crtc->primary_enabled && ret == 0) {
11305 WARN_ON(!intel_crtc->active);
11306 intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
11307 intel_crtc->pipe);
11308 }
11309
11310 /*
11311 * In the fastboot case this may be our only check of the
11312 * state after boot. It would be better to only do it on
11313 * the first update, but we don't have a nice way of doing that
11314 * (and really, set_config isn't used much for high freq page
11315 * flipping, so increasing its cost here shouldn't be a big
11316 * deal).
11317 */
11318 if (i915.fastboot && ret == 0)
11319 intel_modeset_check_state(set->crtc->dev);
11320 }
11321
11322 if (ret) {
11323 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11324 set->crtc->base.id, ret);
11325fail:
11326 intel_set_config_restore_state(dev, config);
11327
11328 /*
11329 * HACK: if the pipe was on, but we didn't have a framebuffer,
11330 * force the pipe off to avoid oopsing in the modeset code
11331 * due to fb==NULL. This should only happen during boot since
11332 * we don't yet reconstruct the FB from the hardware state.
11333 */
11334 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11335 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11336
11337 /* Try to restore the config */
11338 if (config->mode_changed &&
11339 intel_set_mode(save_set.crtc, save_set.mode,
11340 save_set.x, save_set.y, save_set.fb))
11341 DRM_ERROR("failed to restore config after modeset failure\n");
11342 }
11343
11344out_config:
11345 intel_set_config_free(config);
11346 return ret;
11347}
11348
11349static const struct drm_crtc_funcs intel_crtc_funcs = {
11350 .gamma_set = intel_crtc_gamma_set,
11351 .set_config = intel_crtc_set_config,
11352 .destroy = intel_crtc_destroy,
11353 .page_flip = intel_crtc_page_flip,
11354};
11355
11356static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11357 struct intel_shared_dpll *pll,
11358 struct intel_dpll_hw_state *hw_state)
11359{
11360 uint32_t val;
11361
11362 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
11363 return false;
11364
11365 val = I915_READ(PCH_DPLL(pll->id));
11366 hw_state->dpll = val;
11367 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11368 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11369
11370 return val & DPLL_VCO_ENABLE;
11371}
11372
11373static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11374 struct intel_shared_dpll *pll)
11375{
11376 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11377 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11378}
11379
11380static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11381 struct intel_shared_dpll *pll)
11382{
11383 /* PCH refclock must be enabled first */
11384 ibx_assert_pch_refclk_enabled(dev_priv);
11385
11386 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11387
11388 /* Wait for the clocks to stabilize. */
11389 POSTING_READ(PCH_DPLL(pll->id));
11390 udelay(150);
11391
11392 /* The pixel multiplier can only be updated once the
11393 * DPLL is enabled and the clocks are stable.
11394 *
11395 * So write it again.
11396 */
11397 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11398 POSTING_READ(PCH_DPLL(pll->id));
11399 udelay(200);
11400}
11401
11402static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11403 struct intel_shared_dpll *pll)
11404{
11405 struct drm_device *dev = dev_priv->dev;
11406 struct intel_crtc *crtc;
11407
11408 /* Make sure no transcoder isn't still depending on us. */
11409 for_each_intel_crtc(dev, crtc) {
11410 if (intel_crtc_to_shared_dpll(crtc) == pll)
11411 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11412 }
11413
11414 I915_WRITE(PCH_DPLL(pll->id), 0);
11415 POSTING_READ(PCH_DPLL(pll->id));
11416 udelay(200);
11417}
11418
11419static char *ibx_pch_dpll_names[] = {
11420 "PCH DPLL A",
11421 "PCH DPLL B",
11422};
11423
11424static void ibx_pch_dpll_init(struct drm_device *dev)
11425{
11426 struct drm_i915_private *dev_priv = dev->dev_private;
11427 int i;
11428
11429 dev_priv->num_shared_dpll = 2;
11430
11431 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11432 dev_priv->shared_dplls[i].id = i;
11433 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11434 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11435 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11436 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11437 dev_priv->shared_dplls[i].get_hw_state =
11438 ibx_pch_dpll_get_hw_state;
11439 }
11440}
11441
11442static void intel_shared_dpll_init(struct drm_device *dev)
11443{
11444 struct drm_i915_private *dev_priv = dev->dev_private;
11445
11446 if (HAS_DDI(dev))
11447 intel_ddi_pll_init(dev);
11448 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11449 ibx_pch_dpll_init(dev);
11450 else
11451 dev_priv->num_shared_dpll = 0;
11452
11453 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11454}
11455
11456static int
11457intel_primary_plane_disable(struct drm_plane *plane)
11458{
11459 struct drm_device *dev = plane->dev;
11460 struct drm_i915_private *dev_priv = dev->dev_private;
11461 struct intel_plane *intel_plane = to_intel_plane(plane);
11462 struct intel_crtc *intel_crtc;
11463
11464 if (!plane->fb)
11465 return 0;
11466
11467 BUG_ON(!plane->crtc);
11468
11469 intel_crtc = to_intel_crtc(plane->crtc);
11470
11471 /*
11472 * Even though we checked plane->fb above, it's still possible that
11473 * the primary plane has been implicitly disabled because the crtc
11474 * coordinates given weren't visible, or because we detected
11475 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11476 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11477 * In either case, we need to unpin the FB and let the fb pointer get
11478 * updated, but otherwise we don't need to touch the hardware.
11479 */
11480 if (!intel_crtc->primary_enabled)
11481 goto disable_unpin;
11482
11483 intel_crtc_wait_for_pending_flips(plane->crtc);
11484 intel_disable_primary_hw_plane(dev_priv, intel_plane->plane,
11485 intel_plane->pipe);
11486disable_unpin:
11487 mutex_lock(&dev->struct_mutex);
11488 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11489 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11490 intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11491 mutex_unlock(&dev->struct_mutex);
11492 plane->fb = NULL;
11493
11494 return 0;
11495}
11496
11497static int
11498intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11499 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11500 unsigned int crtc_w, unsigned int crtc_h,
11501 uint32_t src_x, uint32_t src_y,
11502 uint32_t src_w, uint32_t src_h)
11503{
11504 struct drm_device *dev = crtc->dev;
11505 struct drm_i915_private *dev_priv = dev->dev_private;
11506 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11507 struct intel_plane *intel_plane = to_intel_plane(plane);
11508 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11509 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11510 struct drm_rect dest = {
11511 /* integer pixels */
11512 .x1 = crtc_x,
11513 .y1 = crtc_y,
11514 .x2 = crtc_x + crtc_w,
11515 .y2 = crtc_y + crtc_h,
11516 };
11517 struct drm_rect src = {
11518 /* 16.16 fixed point */
11519 .x1 = src_x,
11520 .y1 = src_y,
11521 .x2 = src_x + src_w,
11522 .y2 = src_y + src_h,
11523 };
11524 const struct drm_rect clip = {
11525 /* integer pixels */
11526 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11527 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11528 };
11529 bool visible;
11530 int ret;
11531
11532 ret = drm_plane_helper_check_update(plane, crtc, fb,
11533 &src, &dest, &clip,
11534 DRM_PLANE_HELPER_NO_SCALING,
11535 DRM_PLANE_HELPER_NO_SCALING,
11536 false, true, &visible);
11537
11538 if (ret)
11539 return ret;
11540
11541 /*
11542 * If the CRTC isn't enabled, we're just pinning the framebuffer,
11543 * updating the fb pointer, and returning without touching the
11544 * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to
11545 * turn on the display with all planes setup as desired.
11546 */
11547 if (!crtc->enabled) {
11548 mutex_lock(&dev->struct_mutex);
11549
11550 /*
11551 * If we already called setplane while the crtc was disabled,
11552 * we may have an fb pinned; unpin it.
11553 */
11554 if (plane->fb)
11555 intel_unpin_fb_obj(old_obj);
11556
11557 i915_gem_track_fb(old_obj, obj,
11558 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11559
11560 /* Pin and return without programming hardware */
11561 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11562 mutex_unlock(&dev->struct_mutex);
11563
11564 return ret;
11565 }
11566
11567 intel_crtc_wait_for_pending_flips(crtc);
11568
11569 /*
11570 * If clipping results in a non-visible primary plane, we'll disable
11571 * the primary plane. Note that this is a bit different than what
11572 * happens if userspace explicitly disables the plane by passing fb=0
11573 * because plane->fb still gets set and pinned.
11574 */
11575 if (!visible) {
11576 mutex_lock(&dev->struct_mutex);
11577
11578 /*
11579 * Try to pin the new fb first so that we can bail out if we
11580 * fail.
11581 */
11582 if (plane->fb != fb) {
11583 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11584 if (ret) {
11585 mutex_unlock(&dev->struct_mutex);
11586 return ret;
11587 }
11588 }
11589
11590 i915_gem_track_fb(old_obj, obj,
11591 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11592
11593 if (intel_crtc->primary_enabled)
11594 intel_disable_primary_hw_plane(dev_priv,
11595 intel_plane->plane,
11596 intel_plane->pipe);
11597
11598
11599 if (plane->fb != fb)
11600 if (plane->fb)
11601 intel_unpin_fb_obj(old_obj);
11602
11603 mutex_unlock(&dev->struct_mutex);
11604
11605 return 0;
11606 }
11607
11608 ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb);
11609 if (ret)
11610 return ret;
11611
11612 if (!intel_crtc->primary_enabled)
11613 intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
11614 intel_crtc->pipe);
11615
11616 return 0;
11617}
11618
11619/* Common destruction function for both primary and cursor planes */
11620static void intel_plane_destroy(struct drm_plane *plane)
11621{
11622 struct intel_plane *intel_plane = to_intel_plane(plane);
11623 drm_plane_cleanup(plane);
11624 kfree(intel_plane);
11625}
11626
11627static const struct drm_plane_funcs intel_primary_plane_funcs = {
11628 .update_plane = intel_primary_plane_setplane,
11629 .disable_plane = intel_primary_plane_disable,
11630 .destroy = intel_plane_destroy,
11631};
11632
11633static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11634 int pipe)
11635{
11636 struct intel_plane *primary;
11637 const uint32_t *intel_primary_formats;
11638 int num_formats;
11639
11640 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11641 if (primary == NULL)
11642 return NULL;
11643
11644 primary->can_scale = false;
11645 primary->max_downscale = 1;
11646 primary->pipe = pipe;
11647 primary->plane = pipe;
11648 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11649 primary->plane = !pipe;
11650
11651 if (INTEL_INFO(dev)->gen <= 3) {
11652 intel_primary_formats = intel_primary_formats_gen2;
11653 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11654 } else {
11655 intel_primary_formats = intel_primary_formats_gen4;
11656 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11657 }
11658
11659 drm_universal_plane_init(dev, &primary->base, 0,
11660 &intel_primary_plane_funcs,
11661 intel_primary_formats, num_formats,
11662 DRM_PLANE_TYPE_PRIMARY);
11663 return &primary->base;
11664}
11665
11666static int
11667intel_cursor_plane_disable(struct drm_plane *plane)
11668{
11669 if (!plane->fb)
11670 return 0;
11671
11672 BUG_ON(!plane->crtc);
11673
11674 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11675}
11676
11677static int
11678intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11679 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11680 unsigned int crtc_w, unsigned int crtc_h,
11681 uint32_t src_x, uint32_t src_y,
11682 uint32_t src_w, uint32_t src_h)
11683{
11684 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11685 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11686 struct drm_i915_gem_object *obj = intel_fb->obj;
11687 struct drm_rect dest = {
11688 /* integer pixels */
11689 .x1 = crtc_x,
11690 .y1 = crtc_y,
11691 .x2 = crtc_x + crtc_w,
11692 .y2 = crtc_y + crtc_h,
11693 };
11694 struct drm_rect src = {
11695 /* 16.16 fixed point */
11696 .x1 = src_x,
11697 .y1 = src_y,
11698 .x2 = src_x + src_w,
11699 .y2 = src_y + src_h,
11700 };
11701 const struct drm_rect clip = {
11702 /* integer pixels */
11703 .x2 = intel_crtc->config.pipe_src_w,
11704 .y2 = intel_crtc->config.pipe_src_h,
11705 };
11706 bool visible;
11707 int ret;
11708
11709 ret = drm_plane_helper_check_update(plane, crtc, fb,
11710 &src, &dest, &clip,
11711 DRM_PLANE_HELPER_NO_SCALING,
11712 DRM_PLANE_HELPER_NO_SCALING,
11713 true, true, &visible);
11714 if (ret)
11715 return ret;
11716
11717 crtc->cursor_x = crtc_x;
11718 crtc->cursor_y = crtc_y;
11719 if (fb != crtc->cursor->fb) {
11720 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11721 } else {
11722 intel_crtc_update_cursor(crtc, visible);
11723 return 0;
11724 }
11725}
11726static const struct drm_plane_funcs intel_cursor_plane_funcs = {
11727 .update_plane = intel_cursor_plane_update,
11728 .disable_plane = intel_cursor_plane_disable,
11729 .destroy = intel_plane_destroy,
11730};
11731
11732static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
11733 int pipe)
11734{
11735 struct intel_plane *cursor;
11736
11737 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
11738 if (cursor == NULL)
11739 return NULL;
11740
11741 cursor->can_scale = false;
11742 cursor->max_downscale = 1;
11743 cursor->pipe = pipe;
11744 cursor->plane = pipe;
11745
11746 drm_universal_plane_init(dev, &cursor->base, 0,
11747 &intel_cursor_plane_funcs,
11748 intel_cursor_formats,
11749 ARRAY_SIZE(intel_cursor_formats),
11750 DRM_PLANE_TYPE_CURSOR);
11751 return &cursor->base;
11752}
11753
11754static void intel_crtc_init(struct drm_device *dev, int pipe)
11755{
11756 struct drm_i915_private *dev_priv = dev->dev_private;
11757 struct intel_crtc *intel_crtc;
11758 struct drm_plane *primary = NULL;
11759 struct drm_plane *cursor = NULL;
11760 int i, ret;
11761
11762 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
11763 if (intel_crtc == NULL)
11764 return;
11765
11766 primary = intel_primary_plane_create(dev, pipe);
11767 if (!primary)
11768 goto fail;
11769
11770 cursor = intel_cursor_plane_create(dev, pipe);
11771 if (!cursor)
11772 goto fail;
11773
11774 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
11775 cursor, &intel_crtc_funcs);
11776 if (ret)
11777 goto fail;
11778
11779 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
11780 for (i = 0; i < 256; i++) {
11781 intel_crtc->lut_r[i] = i;
11782 intel_crtc->lut_g[i] = i;
11783 intel_crtc->lut_b[i] = i;
11784 }
11785
11786 /*
11787 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
11788 * is hooked to pipe B. Hence we want plane A feeding pipe B.
11789 */
11790 intel_crtc->pipe = pipe;
11791 intel_crtc->plane = pipe;
11792 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
11793 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
11794 intel_crtc->plane = !pipe;
11795 }
11796
11797 intel_crtc->cursor_base = ~0;
11798 intel_crtc->cursor_cntl = ~0;
11799
11800 init_waitqueue_head(&intel_crtc->vbl_wait);
11801
11802 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
11803 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
11804 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
11805 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
11806
11807 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
11808
11809 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
11810 return;
11811
11812fail:
11813 if (primary)
11814 drm_plane_cleanup(primary);
11815 if (cursor)
11816 drm_plane_cleanup(cursor);
11817 kfree(intel_crtc);
11818}
11819
11820enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
11821{
11822 struct drm_encoder *encoder = connector->base.encoder;
11823 struct drm_device *dev = connector->base.dev;
11824
11825 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
11826
11827 if (!encoder)
11828 return INVALID_PIPE;
11829
11830 return to_intel_crtc(encoder->crtc)->pipe;
11831}
11832
11833int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
11834 struct drm_file *file)
11835{
11836 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
11837 struct drm_crtc *drmmode_crtc;
11838 struct intel_crtc *crtc;
11839
11840 if (!drm_core_check_feature(dev, DRIVER_MODESET))
11841 return -ENODEV;
11842
11843 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
11844
11845 if (!drmmode_crtc) {
11846 DRM_ERROR("no such CRTC id\n");
11847 return -ENOENT;
11848 }
11849
11850 crtc = to_intel_crtc(drmmode_crtc);
11851 pipe_from_crtc_id->pipe = crtc->pipe;
11852
11853 return 0;
11854}
11855
11856static int intel_encoder_clones(struct intel_encoder *encoder)
11857{
11858 struct drm_device *dev = encoder->base.dev;
11859 struct intel_encoder *source_encoder;
11860 int index_mask = 0;
11861 int entry = 0;
11862
11863 list_for_each_entry(source_encoder,
11864 &dev->mode_config.encoder_list, base.head) {
11865 if (encoders_cloneable(encoder, source_encoder))
11866 index_mask |= (1 << entry);
11867
11868 entry++;
11869 }
11870
11871 return index_mask;
11872}
11873
11874static bool has_edp_a(struct drm_device *dev)
11875{
11876 struct drm_i915_private *dev_priv = dev->dev_private;
11877
11878 if (!IS_MOBILE(dev))
11879 return false;
11880
11881 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
11882 return false;
11883
11884 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
11885 return false;
11886
11887 return true;
11888}
11889
11890const char *intel_output_name(int output)
11891{
11892 static const char *names[] = {
11893 [INTEL_OUTPUT_UNUSED] = "Unused",
11894 [INTEL_OUTPUT_ANALOG] = "Analog",
11895 [INTEL_OUTPUT_DVO] = "DVO",
11896 [INTEL_OUTPUT_SDVO] = "SDVO",
11897 [INTEL_OUTPUT_LVDS] = "LVDS",
11898 [INTEL_OUTPUT_TVOUT] = "TV",
11899 [INTEL_OUTPUT_HDMI] = "HDMI",
11900 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
11901 [INTEL_OUTPUT_EDP] = "eDP",
11902 [INTEL_OUTPUT_DSI] = "DSI",
11903 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
11904 };
11905
11906 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
11907 return "Invalid";
11908
11909 return names[output];
11910}
11911
11912static bool intel_crt_present(struct drm_device *dev)
11913{
11914 struct drm_i915_private *dev_priv = dev->dev_private;
11915
11916 if (IS_ULT(dev))
11917 return false;
11918
11919 if (IS_CHERRYVIEW(dev))
11920 return false;
11921
11922 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
11923 return false;
11924
11925 return true;
11926}
11927
11928static void intel_setup_outputs(struct drm_device *dev)
11929{
11930 struct drm_i915_private *dev_priv = dev->dev_private;
11931 struct intel_encoder *encoder;
11932 bool dpd_is_edp = false;
11933
11934 intel_lvds_init(dev);
11935
11936 if (intel_crt_present(dev))
11937 intel_crt_init(dev);
11938
11939 if (HAS_DDI(dev)) {
11940 int found;
11941
11942 /* Haswell uses DDI functions to detect digital outputs */
11943 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
11944 /* DDI A only supports eDP */
11945 if (found)
11946 intel_ddi_init(dev, PORT_A);
11947
11948 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
11949 * register */
11950 found = I915_READ(SFUSE_STRAP);
11951
11952 if (found & SFUSE_STRAP_DDIB_DETECTED)
11953 intel_ddi_init(dev, PORT_B);
11954 if (found & SFUSE_STRAP_DDIC_DETECTED)
11955 intel_ddi_init(dev, PORT_C);
11956 if (found & SFUSE_STRAP_DDID_DETECTED)
11957 intel_ddi_init(dev, PORT_D);
11958 } else if (HAS_PCH_SPLIT(dev)) {
11959 int found;
11960 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
11961
11962 if (has_edp_a(dev))
11963 intel_dp_init(dev, DP_A, PORT_A);
11964
11965 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
11966 /* PCH SDVOB multiplex with HDMIB */
11967 found = intel_sdvo_init(dev, PCH_SDVOB, true);
11968 if (!found)
11969 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
11970 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
11971 intel_dp_init(dev, PCH_DP_B, PORT_B);
11972 }
11973
11974 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
11975 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
11976
11977 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
11978 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
11979
11980 if (I915_READ(PCH_DP_C) & DP_DETECTED)
11981 intel_dp_init(dev, PCH_DP_C, PORT_C);
11982
11983 if (I915_READ(PCH_DP_D) & DP_DETECTED)
11984 intel_dp_init(dev, PCH_DP_D, PORT_D);
11985 } else if (IS_VALLEYVIEW(dev)) {
11986 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
11987 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
11988 PORT_B);
11989 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
11990 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
11991 }
11992
11993 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
11994 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
11995 PORT_C);
11996 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
11997 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
11998 }
11999
12000 if (IS_CHERRYVIEW(dev)) {
12001 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
12002 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12003 PORT_D);
12004 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12005 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12006 }
12007 }
12008
12009 intel_dsi_init(dev);
12010 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12011 bool found = false;
12012
12013 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12014 DRM_DEBUG_KMS("probing SDVOB\n");
12015 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12016 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12017 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12018 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12019 }
12020
12021 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12022 intel_dp_init(dev, DP_B, PORT_B);
12023 }
12024
12025 /* Before G4X SDVOC doesn't have its own detect register */
12026
12027 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12028 DRM_DEBUG_KMS("probing SDVOC\n");
12029 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12030 }
12031
12032 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12033
12034 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12035 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12036 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12037 }
12038 if (SUPPORTS_INTEGRATED_DP(dev))
12039 intel_dp_init(dev, DP_C, PORT_C);
12040 }
12041
12042 if (SUPPORTS_INTEGRATED_DP(dev) &&
12043 (I915_READ(DP_D) & DP_DETECTED))
12044 intel_dp_init(dev, DP_D, PORT_D);
12045 } else if (IS_GEN2(dev))
12046 intel_dvo_init(dev);
12047
12048 if (SUPPORTS_TV(dev))
12049 intel_tv_init(dev);
12050
12051 intel_edp_psr_init(dev);
12052
12053 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
12054 encoder->base.possible_crtcs = encoder->crtc_mask;
12055 encoder->base.possible_clones =
12056 intel_encoder_clones(encoder);
12057 }
12058
12059 intel_init_pch_refclk(dev);
12060
12061 drm_helper_move_panel_connectors_to_head(dev);
12062}
12063
12064static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12065{
12066 struct drm_device *dev = fb->dev;
12067 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12068
12069 drm_framebuffer_cleanup(fb);
12070 mutex_lock(&dev->struct_mutex);
12071 WARN_ON(!intel_fb->obj->framebuffer_references--);
12072 drm_gem_object_unreference(&intel_fb->obj->base);
12073 mutex_unlock(&dev->struct_mutex);
12074 kfree(intel_fb);
12075}
12076
12077static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12078 struct drm_file *file,
12079 unsigned int *handle)
12080{
12081 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12082 struct drm_i915_gem_object *obj = intel_fb->obj;
12083
12084 return drm_gem_handle_create(file, &obj->base, handle);
12085}
12086
12087static const struct drm_framebuffer_funcs intel_fb_funcs = {
12088 .destroy = intel_user_framebuffer_destroy,
12089 .create_handle = intel_user_framebuffer_create_handle,
12090};
12091
12092static int intel_framebuffer_init(struct drm_device *dev,
12093 struct intel_framebuffer *intel_fb,
12094 struct drm_mode_fb_cmd2 *mode_cmd,
12095 struct drm_i915_gem_object *obj)
12096{
12097 int aligned_height;
12098 int pitch_limit;
12099 int ret;
12100
12101 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12102
12103 if (obj->tiling_mode == I915_TILING_Y) {
12104 DRM_DEBUG("hardware does not support tiling Y\n");
12105 return -EINVAL;
12106 }
12107
12108 if (mode_cmd->pitches[0] & 63) {
12109 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12110 mode_cmd->pitches[0]);
12111 return -EINVAL;
12112 }
12113
12114 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12115 pitch_limit = 32*1024;
12116 } else if (INTEL_INFO(dev)->gen >= 4) {
12117 if (obj->tiling_mode)
12118 pitch_limit = 16*1024;
12119 else
12120 pitch_limit = 32*1024;
12121 } else if (INTEL_INFO(dev)->gen >= 3) {
12122 if (obj->tiling_mode)
12123 pitch_limit = 8*1024;
12124 else
12125 pitch_limit = 16*1024;
12126 } else
12127 /* XXX DSPC is limited to 4k tiled */
12128 pitch_limit = 8*1024;
12129
12130 if (mode_cmd->pitches[0] > pitch_limit) {
12131 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12132 obj->tiling_mode ? "tiled" : "linear",
12133 mode_cmd->pitches[0], pitch_limit);
12134 return -EINVAL;
12135 }
12136
12137 if (obj->tiling_mode != I915_TILING_NONE &&
12138 mode_cmd->pitches[0] != obj->stride) {
12139 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12140 mode_cmd->pitches[0], obj->stride);
12141 return -EINVAL;
12142 }
12143
12144 /* Reject formats not supported by any plane early. */
12145 switch (mode_cmd->pixel_format) {
12146 case DRM_FORMAT_C8:
12147 case DRM_FORMAT_RGB565:
12148 case DRM_FORMAT_XRGB8888:
12149 case DRM_FORMAT_ARGB8888:
12150 break;
12151 case DRM_FORMAT_XRGB1555:
12152 case DRM_FORMAT_ARGB1555:
12153 if (INTEL_INFO(dev)->gen > 3) {
12154 DRM_DEBUG("unsupported pixel format: %s\n",
12155 drm_get_format_name(mode_cmd->pixel_format));
12156 return -EINVAL;
12157 }
12158 break;
12159 case DRM_FORMAT_XBGR8888:
12160 case DRM_FORMAT_ABGR8888:
12161 case DRM_FORMAT_XRGB2101010:
12162 case DRM_FORMAT_ARGB2101010:
12163 case DRM_FORMAT_XBGR2101010:
12164 case DRM_FORMAT_ABGR2101010:
12165 if (INTEL_INFO(dev)->gen < 4) {
12166 DRM_DEBUG("unsupported pixel format: %s\n",
12167 drm_get_format_name(mode_cmd->pixel_format));
12168 return -EINVAL;
12169 }
12170 break;
12171 case DRM_FORMAT_YUYV:
12172 case DRM_FORMAT_UYVY:
12173 case DRM_FORMAT_YVYU:
12174 case DRM_FORMAT_VYUY:
12175 if (INTEL_INFO(dev)->gen < 5) {
12176 DRM_DEBUG("unsupported pixel format: %s\n",
12177 drm_get_format_name(mode_cmd->pixel_format));
12178 return -EINVAL;
12179 }
12180 break;
12181 default:
12182 DRM_DEBUG("unsupported pixel format: %s\n",
12183 drm_get_format_name(mode_cmd->pixel_format));
12184 return -EINVAL;
12185 }
12186
12187 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12188 if (mode_cmd->offsets[0] != 0)
12189 return -EINVAL;
12190
12191 aligned_height = intel_align_height(dev, mode_cmd->height,
12192 obj->tiling_mode);
12193 /* FIXME drm helper for size checks (especially planar formats)? */
12194 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12195 return -EINVAL;
12196
12197 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12198 intel_fb->obj = obj;
12199 intel_fb->obj->framebuffer_references++;
12200
12201 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12202 if (ret) {
12203 DRM_ERROR("framebuffer init failed %d\n", ret);
12204 return ret;
12205 }
12206
12207 return 0;
12208}
12209
12210static struct drm_framebuffer *
12211intel_user_framebuffer_create(struct drm_device *dev,
12212 struct drm_file *filp,
12213 struct drm_mode_fb_cmd2 *mode_cmd)
12214{
12215 struct drm_i915_gem_object *obj;
12216
12217 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12218 mode_cmd->handles[0]));
12219 if (&obj->base == NULL)
12220 return ERR_PTR(-ENOENT);
12221
12222 return intel_framebuffer_create(dev, mode_cmd, obj);
12223}
12224
12225#ifndef CONFIG_DRM_I915_FBDEV
12226static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12227{
12228}
12229#endif
12230
12231static const struct drm_mode_config_funcs intel_mode_funcs = {
12232 .fb_create = intel_user_framebuffer_create,
12233 .output_poll_changed = intel_fbdev_output_poll_changed,
12234};
12235
12236/* Set up chip specific display functions */
12237static void intel_init_display(struct drm_device *dev)
12238{
12239 struct drm_i915_private *dev_priv = dev->dev_private;
12240
12241 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12242 dev_priv->display.find_dpll = g4x_find_best_dpll;
12243 else if (IS_CHERRYVIEW(dev))
12244 dev_priv->display.find_dpll = chv_find_best_dpll;
12245 else if (IS_VALLEYVIEW(dev))
12246 dev_priv->display.find_dpll = vlv_find_best_dpll;
12247 else if (IS_PINEVIEW(dev))
12248 dev_priv->display.find_dpll = pnv_find_best_dpll;
12249 else
12250 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12251
12252 if (HAS_DDI(dev)) {
12253 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12254 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12255 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
12256 dev_priv->display.crtc_enable = haswell_crtc_enable;
12257 dev_priv->display.crtc_disable = haswell_crtc_disable;
12258 dev_priv->display.off = ironlake_crtc_off;
12259 dev_priv->display.update_primary_plane =
12260 ironlake_update_primary_plane;
12261 } else if (HAS_PCH_SPLIT(dev)) {
12262 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12263 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12264 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
12265 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12266 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12267 dev_priv->display.off = ironlake_crtc_off;
12268 dev_priv->display.update_primary_plane =
12269 ironlake_update_primary_plane;
12270 } else if (IS_VALLEYVIEW(dev)) {
12271 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12272 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12273 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12274 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12275 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12276 dev_priv->display.off = i9xx_crtc_off;
12277 dev_priv->display.update_primary_plane =
12278 i9xx_update_primary_plane;
12279 } else {
12280 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12281 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12282 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12283 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12284 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12285 dev_priv->display.off = i9xx_crtc_off;
12286 dev_priv->display.update_primary_plane =
12287 i9xx_update_primary_plane;
12288 }
12289
12290 /* Returns the core display clock speed */
12291 if (IS_VALLEYVIEW(dev))
12292 dev_priv->display.get_display_clock_speed =
12293 valleyview_get_display_clock_speed;
12294 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12295 dev_priv->display.get_display_clock_speed =
12296 i945_get_display_clock_speed;
12297 else if (IS_I915G(dev))
12298 dev_priv->display.get_display_clock_speed =
12299 i915_get_display_clock_speed;
12300 else if (IS_I945GM(dev) || IS_845G(dev))
12301 dev_priv->display.get_display_clock_speed =
12302 i9xx_misc_get_display_clock_speed;
12303 else if (IS_PINEVIEW(dev))
12304 dev_priv->display.get_display_clock_speed =
12305 pnv_get_display_clock_speed;
12306 else if (IS_I915GM(dev))
12307 dev_priv->display.get_display_clock_speed =
12308 i915gm_get_display_clock_speed;
12309 else if (IS_I865G(dev))
12310 dev_priv->display.get_display_clock_speed =
12311 i865_get_display_clock_speed;
12312 else if (IS_I85X(dev))
12313 dev_priv->display.get_display_clock_speed =
12314 i855_get_display_clock_speed;
12315 else /* 852, 830 */
12316 dev_priv->display.get_display_clock_speed =
12317 i830_get_display_clock_speed;
12318
12319 if (HAS_PCH_SPLIT(dev)) {
12320 if (IS_GEN5(dev)) {
12321 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12322 dev_priv->display.write_eld = ironlake_write_eld;
12323 } else if (IS_GEN6(dev)) {
12324 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12325 dev_priv->display.write_eld = ironlake_write_eld;
12326 dev_priv->display.modeset_global_resources =
12327 snb_modeset_global_resources;
12328 } else if (IS_IVYBRIDGE(dev)) {
12329 /* FIXME: detect B0+ stepping and use auto training */
12330 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12331 dev_priv->display.write_eld = ironlake_write_eld;
12332 dev_priv->display.modeset_global_resources =
12333 ivb_modeset_global_resources;
12334 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
12335 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12336 dev_priv->display.write_eld = haswell_write_eld;
12337 dev_priv->display.modeset_global_resources =
12338 haswell_modeset_global_resources;
12339 }
12340 } else if (IS_G4X(dev)) {
12341 dev_priv->display.write_eld = g4x_write_eld;
12342 } else if (IS_VALLEYVIEW(dev)) {
12343 dev_priv->display.modeset_global_resources =
12344 valleyview_modeset_global_resources;
12345 dev_priv->display.write_eld = ironlake_write_eld;
12346 }
12347
12348 /* Default just returns -ENODEV to indicate unsupported */
12349 dev_priv->display.queue_flip = intel_default_queue_flip;
12350
12351 switch (INTEL_INFO(dev)->gen) {
12352 case 2:
12353 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12354 break;
12355
12356 case 3:
12357 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12358 break;
12359
12360 case 4:
12361 case 5:
12362 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12363 break;
12364
12365 case 6:
12366 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12367 break;
12368 case 7:
12369 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12370 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12371 break;
12372 }
12373
12374 intel_panel_init_backlight_funcs(dev);
12375}
12376
12377/*
12378 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12379 * resume, or other times. This quirk makes sure that's the case for
12380 * affected systems.
12381 */
12382static void quirk_pipea_force(struct drm_device *dev)
12383{
12384 struct drm_i915_private *dev_priv = dev->dev_private;
12385
12386 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12387 DRM_INFO("applying pipe a force quirk\n");
12388}
12389
12390/*
12391 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12392 */
12393static void quirk_ssc_force_disable(struct drm_device *dev)
12394{
12395 struct drm_i915_private *dev_priv = dev->dev_private;
12396 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12397 DRM_INFO("applying lvds SSC disable quirk\n");
12398}
12399
12400/*
12401 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12402 * brightness value
12403 */
12404static void quirk_invert_brightness(struct drm_device *dev)
12405{
12406 struct drm_i915_private *dev_priv = dev->dev_private;
12407 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12408 DRM_INFO("applying inverted panel brightness quirk\n");
12409}
12410
12411/* Some VBT's incorrectly indicate no backlight is present */
12412static void quirk_backlight_present(struct drm_device *dev)
12413{
12414 struct drm_i915_private *dev_priv = dev->dev_private;
12415 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12416 DRM_INFO("applying backlight present quirk\n");
12417}
12418
12419struct intel_quirk {
12420 int device;
12421 int subsystem_vendor;
12422 int subsystem_device;
12423 void (*hook)(struct drm_device *dev);
12424};
12425
12426/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12427struct intel_dmi_quirk {
12428 void (*hook)(struct drm_device *dev);
12429 const struct dmi_system_id (*dmi_id_list)[];
12430};
12431
12432static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12433{
12434 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12435 return 1;
12436}
12437
12438static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12439 {
12440 .dmi_id_list = &(const struct dmi_system_id[]) {
12441 {
12442 .callback = intel_dmi_reverse_brightness,
12443 .ident = "NCR Corporation",
12444 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12445 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12446 },
12447 },
12448 { } /* terminating entry */
12449 },
12450 .hook = quirk_invert_brightness,
12451 },
12452};
12453
12454static struct intel_quirk intel_quirks[] = {
12455 /* HP Mini needs pipe A force quirk (LP: #322104) */
12456 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12457
12458 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12459 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12460
12461 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12462 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12463
12464 /* Lenovo U160 cannot use SSC on LVDS */
12465 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12466
12467 /* Sony Vaio Y cannot use SSC on LVDS */
12468 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12469
12470 /* Acer Aspire 5734Z must invert backlight brightness */
12471 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12472
12473 /* Acer/eMachines G725 */
12474 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12475
12476 /* Acer/eMachines e725 */
12477 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12478
12479 /* Acer/Packard Bell NCL20 */
12480 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12481
12482 /* Acer Aspire 4736Z */
12483 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12484
12485 /* Acer Aspire 5336 */
12486 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12487
12488 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12489 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12490
12491 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12492 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12493
12494 /* HP Chromebook 14 (Celeron 2955U) */
12495 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12496};
12497
12498static void intel_init_quirks(struct drm_device *dev)
12499{
12500 struct pci_dev *d = dev->pdev;
12501 int i;
12502
12503 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12504 struct intel_quirk *q = &intel_quirks[i];
12505
12506 if (d->device == q->device &&
12507 (d->subsystem_vendor == q->subsystem_vendor ||
12508 q->subsystem_vendor == PCI_ANY_ID) &&
12509 (d->subsystem_device == q->subsystem_device ||
12510 q->subsystem_device == PCI_ANY_ID))
12511 q->hook(dev);
12512 }
12513 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12514 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12515 intel_dmi_quirks[i].hook(dev);
12516 }
12517}
12518
12519/* Disable the VGA plane that we never use */
12520static void i915_disable_vga(struct drm_device *dev)
12521{
12522 struct drm_i915_private *dev_priv = dev->dev_private;
12523 u8 sr1;
12524 u32 vga_reg = i915_vgacntrl_reg(dev);
12525
12526 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12527 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12528 outb(SR01, VGA_SR_INDEX);
12529 sr1 = inb(VGA_SR_DATA);
12530 outb(sr1 | 1<<5, VGA_SR_DATA);
12531 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12532 udelay(300);
12533
12534 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
12535 POSTING_READ(vga_reg);
12536}
12537
12538void intel_modeset_init_hw(struct drm_device *dev)
12539{
12540 intel_prepare_ddi(dev);
12541
12542 if (IS_VALLEYVIEW(dev))
12543 vlv_update_cdclk(dev);
12544
12545 intel_init_clock_gating(dev);
12546
12547 intel_reset_dpio(dev);
12548
12549 intel_enable_gt_powersave(dev);
12550}
12551
12552void intel_modeset_suspend_hw(struct drm_device *dev)
12553{
12554 intel_suspend_hw(dev);
12555}
12556
12557void intel_modeset_init(struct drm_device *dev)
12558{
12559 struct drm_i915_private *dev_priv = dev->dev_private;
12560 int sprite, ret;
12561 enum pipe pipe;
12562 struct intel_crtc *crtc;
12563
12564 drm_mode_config_init(dev);
12565
12566 dev->mode_config.min_width = 0;
12567 dev->mode_config.min_height = 0;
12568
12569 dev->mode_config.preferred_depth = 24;
12570 dev->mode_config.prefer_shadow = 1;
12571
12572 dev->mode_config.funcs = &intel_mode_funcs;
12573
12574 intel_init_quirks(dev);
12575
12576 intel_init_pm(dev);
12577
12578 if (INTEL_INFO(dev)->num_pipes == 0)
12579 return;
12580
12581 intel_init_display(dev);
12582
12583 if (IS_GEN2(dev)) {
12584 dev->mode_config.max_width = 2048;
12585 dev->mode_config.max_height = 2048;
12586 } else if (IS_GEN3(dev)) {
12587 dev->mode_config.max_width = 4096;
12588 dev->mode_config.max_height = 4096;
12589 } else {
12590 dev->mode_config.max_width = 8192;
12591 dev->mode_config.max_height = 8192;
12592 }
12593
12594 if (IS_GEN2(dev)) {
12595 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12596 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12597 } else {
12598 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12599 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12600 }
12601
12602 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12603
12604 DRM_DEBUG_KMS("%d display pipe%s available.\n",
12605 INTEL_INFO(dev)->num_pipes,
12606 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12607
12608 for_each_pipe(pipe) {
12609 intel_crtc_init(dev, pipe);
12610 for_each_sprite(pipe, sprite) {
12611 ret = intel_plane_init(dev, pipe, sprite);
12612 if (ret)
12613 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12614 pipe_name(pipe), sprite_name(pipe, sprite), ret);
12615 }
12616 }
12617
12618 intel_init_dpio(dev);
12619 intel_reset_dpio(dev);
12620
12621 intel_shared_dpll_init(dev);
12622
12623 /* Just disable it once at startup */
12624 i915_disable_vga(dev);
12625 intel_setup_outputs(dev);
12626
12627 /* Just in case the BIOS is doing something questionable. */
12628 intel_disable_fbc(dev);
12629
12630 drm_modeset_lock_all(dev);
12631 intel_modeset_setup_hw_state(dev, false);
12632 drm_modeset_unlock_all(dev);
12633
12634 for_each_intel_crtc(dev, crtc) {
12635 if (!crtc->active)
12636 continue;
12637
12638 /*
12639 * Note that reserving the BIOS fb up front prevents us
12640 * from stuffing other stolen allocations like the ring
12641 * on top. This prevents some ugliness at boot time, and
12642 * can even allow for smooth boot transitions if the BIOS
12643 * fb is large enough for the active pipe configuration.
12644 */
12645 if (dev_priv->display.get_plane_config) {
12646 dev_priv->display.get_plane_config(crtc,
12647 &crtc->plane_config);
12648 /*
12649 * If the fb is shared between multiple heads, we'll
12650 * just get the first one.
12651 */
12652 intel_find_plane_obj(crtc, &crtc->plane_config);
12653 }
12654 }
12655}
12656
12657static void intel_enable_pipe_a(struct drm_device *dev)
12658{
12659 struct intel_connector *connector;
12660 struct drm_connector *crt = NULL;
12661 struct intel_load_detect_pipe load_detect_temp;
12662 struct drm_modeset_acquire_ctx ctx;
12663
12664 /* We can't just switch on the pipe A, we need to set things up with a
12665 * proper mode and output configuration. As a gross hack, enable pipe A
12666 * by enabling the load detect pipe once. */
12667 list_for_each_entry(connector,
12668 &dev->mode_config.connector_list,
12669 base.head) {
12670 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12671 crt = &connector->base;
12672 break;
12673 }
12674 }
12675
12676 if (!crt)
12677 return;
12678
12679 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, &ctx))
12680 intel_release_load_detect_pipe(crt, &load_detect_temp, &ctx);
12681
12682
12683}
12684
12685static bool
12686intel_check_plane_mapping(struct intel_crtc *crtc)
12687{
12688 struct drm_device *dev = crtc->base.dev;
12689 struct drm_i915_private *dev_priv = dev->dev_private;
12690 u32 reg, val;
12691
12692 if (INTEL_INFO(dev)->num_pipes == 1)
12693 return true;
12694
12695 reg = DSPCNTR(!crtc->plane);
12696 val = I915_READ(reg);
12697
12698 if ((val & DISPLAY_PLANE_ENABLE) &&
12699 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12700 return false;
12701
12702 return true;
12703}
12704
12705static void intel_sanitize_crtc(struct intel_crtc *crtc)
12706{
12707 struct drm_device *dev = crtc->base.dev;
12708 struct drm_i915_private *dev_priv = dev->dev_private;
12709 u32 reg;
12710
12711 /* Clear any frame start delays used for debugging left by the BIOS */
12712 reg = PIPECONF(crtc->config.cpu_transcoder);
12713 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12714
12715 /* restore vblank interrupts to correct state */
12716 if (crtc->active)
12717 drm_vblank_on(dev, crtc->pipe);
12718 else
12719 drm_vblank_off(dev, crtc->pipe);
12720
12721 /* We need to sanitize the plane -> pipe mapping first because this will
12722 * disable the crtc (and hence change the state) if it is wrong. Note
12723 * that gen4+ has a fixed plane -> pipe mapping. */
12724 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
12725 struct intel_connector *connector;
12726 bool plane;
12727
12728 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12729 crtc->base.base.id);
12730
12731 /* Pipe has the wrong plane attached and the plane is active.
12732 * Temporarily change the plane mapping and disable everything
12733 * ... */
12734 plane = crtc->plane;
12735 crtc->plane = !plane;
12736 crtc->primary_enabled = true;
12737 dev_priv->display.crtc_disable(&crtc->base);
12738 crtc->plane = plane;
12739
12740 /* ... and break all links. */
12741 list_for_each_entry(connector, &dev->mode_config.connector_list,
12742 base.head) {
12743 if (connector->encoder->base.crtc != &crtc->base)
12744 continue;
12745
12746 connector->base.dpms = DRM_MODE_DPMS_OFF;
12747 connector->base.encoder = NULL;
12748 }
12749 /* multiple connectors may have the same encoder:
12750 * handle them and break crtc link separately */
12751 list_for_each_entry(connector, &dev->mode_config.connector_list,
12752 base.head)
12753 if (connector->encoder->base.crtc == &crtc->base) {
12754 connector->encoder->base.crtc = NULL;
12755 connector->encoder->connectors_active = false;
12756 }
12757
12758 WARN_ON(crtc->active);
12759 crtc->base.enabled = false;
12760 }
12761
12762 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
12763 crtc->pipe == PIPE_A && !crtc->active) {
12764 /* BIOS forgot to enable pipe A, this mostly happens after
12765 * resume. Force-enable the pipe to fix this, the update_dpms
12766 * call below we restore the pipe to the right state, but leave
12767 * the required bits on. */
12768 intel_enable_pipe_a(dev);
12769 }
12770
12771 /* Adjust the state of the output pipe according to whether we
12772 * have active connectors/encoders. */
12773 intel_crtc_update_dpms(&crtc->base);
12774
12775 if (crtc->active != crtc->base.enabled) {
12776 struct intel_encoder *encoder;
12777
12778 /* This can happen either due to bugs in the get_hw_state
12779 * functions or because the pipe is force-enabled due to the
12780 * pipe A quirk. */
12781 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12782 crtc->base.base.id,
12783 crtc->base.enabled ? "enabled" : "disabled",
12784 crtc->active ? "enabled" : "disabled");
12785
12786 crtc->base.enabled = crtc->active;
12787
12788 /* Because we only establish the connector -> encoder ->
12789 * crtc links if something is active, this means the
12790 * crtc is now deactivated. Break the links. connector
12791 * -> encoder links are only establish when things are
12792 * actually up, hence no need to break them. */
12793 WARN_ON(crtc->active);
12794
12795 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
12796 WARN_ON(encoder->connectors_active);
12797 encoder->base.crtc = NULL;
12798 }
12799 }
12800
12801 if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) {
12802 /*
12803 * We start out with underrun reporting disabled to avoid races.
12804 * For correct bookkeeping mark this on active crtcs.
12805 *
12806 * Also on gmch platforms we dont have any hardware bits to
12807 * disable the underrun reporting. Which means we need to start
12808 * out with underrun reporting disabled also on inactive pipes,
12809 * since otherwise we'll complain about the garbage we read when
12810 * e.g. coming up after runtime pm.
12811 *
12812 * No protection against concurrent access is required - at
12813 * worst a fifo underrun happens which also sets this to false.
12814 */
12815 crtc->cpu_fifo_underrun_disabled = true;
12816 crtc->pch_fifo_underrun_disabled = true;
12817
12818 update_scanline_offset(crtc);
12819 }
12820}
12821
12822static void intel_sanitize_encoder(struct intel_encoder *encoder)
12823{
12824 struct intel_connector *connector;
12825 struct drm_device *dev = encoder->base.dev;
12826
12827 /* We need to check both for a crtc link (meaning that the
12828 * encoder is active and trying to read from a pipe) and the
12829 * pipe itself being active. */
12830 bool has_active_crtc = encoder->base.crtc &&
12831 to_intel_crtc(encoder->base.crtc)->active;
12832
12833 if (encoder->connectors_active && !has_active_crtc) {
12834 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
12835 encoder->base.base.id,
12836 encoder->base.name);
12837
12838 /* Connector is active, but has no active pipe. This is
12839 * fallout from our resume register restoring. Disable
12840 * the encoder manually again. */
12841 if (encoder->base.crtc) {
12842 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
12843 encoder->base.base.id,
12844 encoder->base.name);
12845 encoder->disable(encoder);
12846 if (encoder->post_disable)
12847 encoder->post_disable(encoder);
12848 }
12849 encoder->base.crtc = NULL;
12850 encoder->connectors_active = false;
12851
12852 /* Inconsistent output/port/pipe state happens presumably due to
12853 * a bug in one of the get_hw_state functions. Or someplace else
12854 * in our code, like the register restore mess on resume. Clamp
12855 * things to off as a safer default. */
12856 list_for_each_entry(connector,
12857 &dev->mode_config.connector_list,
12858 base.head) {
12859 if (connector->encoder != encoder)
12860 continue;
12861 connector->base.dpms = DRM_MODE_DPMS_OFF;
12862 connector->base.encoder = NULL;
12863 }
12864 }
12865 /* Enabled encoders without active connectors will be fixed in
12866 * the crtc fixup. */
12867}
12868
12869void i915_redisable_vga_power_on(struct drm_device *dev)
12870{
12871 struct drm_i915_private *dev_priv = dev->dev_private;
12872 u32 vga_reg = i915_vgacntrl_reg(dev);
12873
12874 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
12875 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
12876 i915_disable_vga(dev);
12877 }
12878}
12879
12880void i915_redisable_vga(struct drm_device *dev)
12881{
12882 struct drm_i915_private *dev_priv = dev->dev_private;
12883
12884 /* This function can be called both from intel_modeset_setup_hw_state or
12885 * at a very early point in our resume sequence, where the power well
12886 * structures are not yet restored. Since this function is at a very
12887 * paranoid "someone might have enabled VGA while we were not looking"
12888 * level, just check if the power well is enabled instead of trying to
12889 * follow the "don't touch the power well if we don't need it" policy
12890 * the rest of the driver uses. */
12891 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
12892 return;
12893
12894 i915_redisable_vga_power_on(dev);
12895}
12896
12897static bool primary_get_hw_state(struct intel_crtc *crtc)
12898{
12899 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
12900
12901 if (!crtc->active)
12902 return false;
12903
12904 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
12905}
12906
12907static void intel_modeset_readout_hw_state(struct drm_device *dev)
12908{
12909 struct drm_i915_private *dev_priv = dev->dev_private;
12910 enum pipe pipe;
12911 struct intel_crtc *crtc;
12912 struct intel_encoder *encoder;
12913 struct intel_connector *connector;
12914 int i;
12915
12916 for_each_intel_crtc(dev, crtc) {
12917 memset(&crtc->config, 0, sizeof(crtc->config));
12918
12919 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
12920
12921 crtc->active = dev_priv->display.get_pipe_config(crtc,
12922 &crtc->config);
12923
12924 crtc->base.enabled = crtc->active;
12925 crtc->primary_enabled = primary_get_hw_state(crtc);
12926
12927 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
12928 crtc->base.base.id,
12929 crtc->active ? "enabled" : "disabled");
12930 }
12931
12932 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12933 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12934
12935 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
12936 pll->active = 0;
12937 for_each_intel_crtc(dev, crtc) {
12938 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12939 pll->active++;
12940 }
12941 pll->refcount = pll->active;
12942
12943 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
12944 pll->name, pll->refcount, pll->on);
12945
12946 if (pll->refcount)
12947 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
12948 }
12949
12950 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12951 base.head) {
12952 pipe = 0;
12953
12954 if (encoder->get_hw_state(encoder, &pipe)) {
12955 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12956 encoder->base.crtc = &crtc->base;
12957 encoder->get_config(encoder, &crtc->config);
12958 } else {
12959 encoder->base.crtc = NULL;
12960 }
12961
12962 encoder->connectors_active = false;
12963 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
12964 encoder->base.base.id,
12965 encoder->base.name,
12966 encoder->base.crtc ? "enabled" : "disabled",
12967 pipe_name(pipe));
12968 }
12969
12970 list_for_each_entry(connector, &dev->mode_config.connector_list,
12971 base.head) {
12972 if (connector->get_hw_state(connector)) {
12973 connector->base.dpms = DRM_MODE_DPMS_ON;
12974 connector->encoder->connectors_active = true;
12975 connector->base.encoder = &connector->encoder->base;
12976 } else {
12977 connector->base.dpms = DRM_MODE_DPMS_OFF;
12978 connector->base.encoder = NULL;
12979 }
12980 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
12981 connector->base.base.id,
12982 connector->base.name,
12983 connector->base.encoder ? "enabled" : "disabled");
12984 }
12985}
12986
12987/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
12988 * and i915 state tracking structures. */
12989void intel_modeset_setup_hw_state(struct drm_device *dev,
12990 bool force_restore)
12991{
12992 struct drm_i915_private *dev_priv = dev->dev_private;
12993 enum pipe pipe;
12994 struct intel_crtc *crtc;
12995 struct intel_encoder *encoder;
12996 int i;
12997
12998 intel_modeset_readout_hw_state(dev);
12999
13000 /*
13001 * Now that we have the config, copy it to each CRTC struct
13002 * Note that this could go away if we move to using crtc_config
13003 * checking everywhere.
13004 */
13005 for_each_intel_crtc(dev, crtc) {
13006 if (crtc->active && i915.fastboot) {
13007 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13008 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13009 crtc->base.base.id);
13010 drm_mode_debug_printmodeline(&crtc->base.mode);
13011 }
13012 }
13013
13014 /* HW state is read out, now we need to sanitize this mess. */
13015 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
13016 base.head) {
13017 intel_sanitize_encoder(encoder);
13018 }
13019
13020 for_each_pipe(pipe) {
13021 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13022 intel_sanitize_crtc(crtc);
13023 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13024 }
13025
13026 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13027 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13028
13029 if (!pll->on || pll->active)
13030 continue;
13031
13032 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13033
13034 pll->disable(dev_priv, pll);
13035 pll->on = false;
13036 }
13037
13038 if (HAS_PCH_SPLIT(dev))
13039 ilk_wm_get_hw_state(dev);
13040
13041 if (force_restore) {
13042 i915_redisable_vga(dev);
13043
13044 /*
13045 * We need to use raw interfaces for restoring state to avoid
13046 * checking (bogus) intermediate states.
13047 */
13048 for_each_pipe(pipe) {
13049 struct drm_crtc *crtc =
13050 dev_priv->pipe_to_crtc_mapping[pipe];
13051
13052 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13053 crtc->primary->fb);
13054 }
13055 } else {
13056 intel_modeset_update_staged_output_state(dev);
13057 }
13058
13059 intel_modeset_check_state(dev);
13060}
13061
13062void intel_modeset_gem_init(struct drm_device *dev)
13063{
13064 struct drm_crtc *c;
13065 struct drm_i915_gem_object *obj;
13066
13067 mutex_lock(&dev->struct_mutex);
13068 intel_init_gt_powersave(dev);
13069 mutex_unlock(&dev->struct_mutex);
13070
13071 intel_modeset_init_hw(dev);
13072
13073 intel_setup_overlay(dev);
13074
13075 /*
13076 * Make sure any fbs we allocated at startup are properly
13077 * pinned & fenced. When we do the allocation it's too early
13078 * for this.
13079 */
13080 mutex_lock(&dev->struct_mutex);
13081 for_each_crtc(dev, c) {
13082 obj = intel_fb_obj(c->primary->fb);
13083 if (obj == NULL)
13084 continue;
13085
13086 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
13087 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13088 to_intel_crtc(c)->pipe);
13089 drm_framebuffer_unreference(c->primary->fb);
13090 c->primary->fb = NULL;
13091 }
13092 }
13093 mutex_unlock(&dev->struct_mutex);
13094}
13095
13096void intel_connector_unregister(struct intel_connector *intel_connector)
13097{
13098 struct drm_connector *connector = &intel_connector->base;
13099
13100 intel_panel_destroy_backlight(connector);
13101 drm_connector_unregister(connector);
13102}
13103
13104void intel_modeset_cleanup(struct drm_device *dev)
13105{
13106 struct drm_i915_private *dev_priv = dev->dev_private;
13107 struct drm_connector *connector;
13108
13109 /*
13110 * Interrupts and polling as the first thing to avoid creating havoc.
13111 * Too much stuff here (turning of rps, connectors, ...) would
13112 * experience fancy races otherwise.
13113 */
13114 drm_irq_uninstall(dev);
13115 cancel_work_sync(&dev_priv->hotplug_work);
13116 dev_priv->pm._irqs_disabled = true;
13117
13118 /*
13119 * Due to the hpd irq storm handling the hotplug work can re-arm the
13120 * poll handlers. Hence disable polling after hpd handling is shut down.
13121 */
13122 drm_kms_helper_poll_fini(dev);
13123
13124 mutex_lock(&dev->struct_mutex);
13125
13126 intel_unregister_dsm_handler();
13127
13128 intel_disable_fbc(dev);
13129
13130 intel_disable_gt_powersave(dev);
13131
13132 ironlake_teardown_rc6(dev);
13133
13134 mutex_unlock(&dev->struct_mutex);
13135
13136 /* flush any delayed tasks or pending work */
13137 flush_scheduled_work();
13138
13139 /* destroy the backlight and sysfs files before encoders/connectors */
13140 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13141 struct intel_connector *intel_connector;
13142
13143 intel_connector = to_intel_connector(connector);
13144 intel_connector->unregister(intel_connector);
13145 }
13146
13147 drm_mode_config_cleanup(dev);
13148
13149 intel_cleanup_overlay(dev);
13150
13151 mutex_lock(&dev->struct_mutex);
13152 intel_cleanup_gt_powersave(dev);
13153 mutex_unlock(&dev->struct_mutex);
13154}
13155
13156/*
13157 * Return which encoder is currently attached for connector.
13158 */
13159struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13160{
13161 return &intel_attached_encoder(connector)->base;
13162}
13163
13164void intel_connector_attach_encoder(struct intel_connector *connector,
13165 struct intel_encoder *encoder)
13166{
13167 connector->encoder = encoder;
13168 drm_mode_connector_attach_encoder(&connector->base,
13169 &encoder->base);
13170}
13171
13172/*
13173 * set vga decode state - true == enable VGA decode
13174 */
13175int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13176{
13177 struct drm_i915_private *dev_priv = dev->dev_private;
13178 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13179 u16 gmch_ctrl;
13180
13181 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13182 DRM_ERROR("failed to read control word\n");
13183 return -EIO;
13184 }
13185
13186 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13187 return 0;
13188
13189 if (state)
13190 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13191 else
13192 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13193
13194 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13195 DRM_ERROR("failed to write control word\n");
13196 return -EIO;
13197 }
13198
13199 return 0;
13200}
13201
13202struct intel_display_error_state {
13203
13204 u32 power_well_driver;
13205
13206 int num_transcoders;
13207
13208 struct intel_cursor_error_state {
13209 u32 control;
13210 u32 position;
13211 u32 base;
13212 u32 size;
13213 } cursor[I915_MAX_PIPES];
13214
13215 struct intel_pipe_error_state {
13216 bool power_domain_on;
13217 u32 source;
13218 u32 stat;
13219 } pipe[I915_MAX_PIPES];
13220
13221 struct intel_plane_error_state {
13222 u32 control;
13223 u32 stride;
13224 u32 size;
13225 u32 pos;
13226 u32 addr;
13227 u32 surface;
13228 u32 tile_offset;
13229 } plane[I915_MAX_PIPES];
13230
13231 struct intel_transcoder_error_state {
13232 bool power_domain_on;
13233 enum transcoder cpu_transcoder;
13234
13235 u32 conf;
13236
13237 u32 htotal;
13238 u32 hblank;
13239 u32 hsync;
13240 u32 vtotal;
13241 u32 vblank;
13242 u32 vsync;
13243 } transcoder[4];
13244};
13245
13246struct intel_display_error_state *
13247intel_display_capture_error_state(struct drm_device *dev)
13248{
13249 struct drm_i915_private *dev_priv = dev->dev_private;
13250 struct intel_display_error_state *error;
13251 int transcoders[] = {
13252 TRANSCODER_A,
13253 TRANSCODER_B,
13254 TRANSCODER_C,
13255 TRANSCODER_EDP,
13256 };
13257 int i;
13258
13259 if (INTEL_INFO(dev)->num_pipes == 0)
13260 return NULL;
13261
13262 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13263 if (error == NULL)
13264 return NULL;
13265
13266 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13267 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13268
13269 for_each_pipe(i) {
13270 error->pipe[i].power_domain_on =
13271 intel_display_power_enabled_unlocked(dev_priv,
13272 POWER_DOMAIN_PIPE(i));
13273 if (!error->pipe[i].power_domain_on)
13274 continue;
13275
13276 error->cursor[i].control = I915_READ(CURCNTR(i));
13277 error->cursor[i].position = I915_READ(CURPOS(i));
13278 error->cursor[i].base = I915_READ(CURBASE(i));
13279
13280 error->plane[i].control = I915_READ(DSPCNTR(i));
13281 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13282 if (INTEL_INFO(dev)->gen <= 3) {
13283 error->plane[i].size = I915_READ(DSPSIZE(i));
13284 error->plane[i].pos = I915_READ(DSPPOS(i));
13285 }
13286 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13287 error->plane[i].addr = I915_READ(DSPADDR(i));
13288 if (INTEL_INFO(dev)->gen >= 4) {
13289 error->plane[i].surface = I915_READ(DSPSURF(i));
13290 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13291 }
13292
13293 error->pipe[i].source = I915_READ(PIPESRC(i));
13294
13295 if (HAS_GMCH_DISPLAY(dev))
13296 error->pipe[i].stat = I915_READ(PIPESTAT(i));
13297 }
13298
13299 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13300 if (HAS_DDI(dev_priv->dev))
13301 error->num_transcoders++; /* Account for eDP. */
13302
13303 for (i = 0; i < error->num_transcoders; i++) {
13304 enum transcoder cpu_transcoder = transcoders[i];
13305
13306 error->transcoder[i].power_domain_on =
13307 intel_display_power_enabled_unlocked(dev_priv,
13308 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13309 if (!error->transcoder[i].power_domain_on)
13310 continue;
13311
13312 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13313
13314 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13315 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13316 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13317 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13318 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13319 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13320 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13321 }
13322
13323 return error;
13324}
13325
13326#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13327
13328void
13329intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13330 struct drm_device *dev,
13331 struct intel_display_error_state *error)
13332{
13333 int i;
13334
13335 if (!error)
13336 return;
13337
13338 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13339 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13340 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13341 error->power_well_driver);
13342 for_each_pipe(i) {
13343 err_printf(m, "Pipe [%d]:\n", i);
13344 err_printf(m, " Power: %s\n",
13345 error->pipe[i].power_domain_on ? "on" : "off");
13346 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
13347 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
13348
13349 err_printf(m, "Plane [%d]:\n", i);
13350 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13351 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
13352 if (INTEL_INFO(dev)->gen <= 3) {
13353 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13354 err_printf(m, " POS: %08x\n", error->plane[i].pos);
13355 }
13356 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13357 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
13358 if (INTEL_INFO(dev)->gen >= 4) {
13359 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13360 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
13361 }
13362
13363 err_printf(m, "Cursor [%d]:\n", i);
13364 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13365 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13366 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
13367 }
13368
13369 for (i = 0; i < error->num_transcoders; i++) {
13370 err_printf(m, "CPU transcoder: %c\n",
13371 transcoder_name(error->transcoder[i].cpu_transcoder));
13372 err_printf(m, " Power: %s\n",
13373 error->transcoder[i].power_domain_on ? "on" : "off");
13374 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13375 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13376 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13377 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13378 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13379 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13380 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13381 }
13382}
Linux kernel - Deliverables
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