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drm/i915: Restore lost DPLL register write on gen2-4
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
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1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27#include <linux/dmi.h>
28#include <linux/module.h>
29#include <linux/input.h>
30#include <linux/i2c.h>
31#include <linux/kernel.h>
32#include <linux/slab.h>
33#include <linux/vgaarb.h>
34#include <drm/drm_edid.h>
35#include <drm/drmP.h>
36#include "intel_drv.h"
37#include <drm/i915_drm.h>
38#include "i915_drv.h"
39#include "i915_trace.h"
40#include <drm/drm_atomic.h>
41#include <drm/drm_atomic_helper.h>
42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
46#include <linux/dma_remapping.h>
47
48/* Primary plane formats for gen <= 3 */
49static const uint32_t i8xx_primary_formats[] = {
50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
52 DRM_FORMAT_XRGB1555,
53 DRM_FORMAT_XRGB8888,
54};
55
56/* Primary plane formats for gen >= 4 */
57static const uint32_t i965_primary_formats[] = {
58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64};
65
66static const uint32_t skl_primary_formats[] = {
67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
70 DRM_FORMAT_XBGR8888,
71 DRM_FORMAT_ARGB8888,
72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
74 DRM_FORMAT_XBGR2101010,
75};
76
77/* Cursor formats */
78static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80};
81
82static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
83
84static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
85 struct intel_crtc_state *pipe_config);
86static void ironlake_pch_clock_get(struct intel_crtc *crtc,
87 struct intel_crtc_state *pipe_config);
88
89static int intel_framebuffer_init(struct drm_device *dev,
90 struct intel_framebuffer *ifb,
91 struct drm_mode_fb_cmd2 *mode_cmd,
92 struct drm_i915_gem_object *obj);
93static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
94static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
95static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
96 struct intel_link_m_n *m_n,
97 struct intel_link_m_n *m2_n2);
98static void ironlake_set_pipeconf(struct drm_crtc *crtc);
99static void haswell_set_pipeconf(struct drm_crtc *crtc);
100static void intel_set_pipe_csc(struct drm_crtc *crtc);
101static void vlv_prepare_pll(struct intel_crtc *crtc,
102 const struct intel_crtc_state *pipe_config);
103static void chv_prepare_pll(struct intel_crtc *crtc,
104 const struct intel_crtc_state *pipe_config);
105static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
106static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
107static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
108 struct intel_crtc_state *crtc_state);
109static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
110 int num_connectors);
111static void intel_modeset_setup_hw_state(struct drm_device *dev);
112
113typedef struct {
114 int min, max;
115} intel_range_t;
116
117typedef struct {
118 int dot_limit;
119 int p2_slow, p2_fast;
120} intel_p2_t;
121
122typedef struct intel_limit intel_limit_t;
123struct intel_limit {
124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
125 intel_p2_t p2;
126};
127
128int
129intel_pch_rawclk(struct drm_device *dev)
130{
131 struct drm_i915_private *dev_priv = dev->dev_private;
132
133 WARN_ON(!HAS_PCH_SPLIT(dev));
134
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
136}
137
138static inline u32 /* units of 100MHz */
139intel_fdi_link_freq(struct drm_device *dev)
140{
141 if (IS_GEN5(dev)) {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
144 } else
145 return 27;
146}
147
148static const intel_limit_t intel_limits_i8xx_dac = {
149 .dot = { .min = 25000, .max = 350000 },
150 .vco = { .min = 908000, .max = 1512000 },
151 .n = { .min = 2, .max = 16 },
152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
159};
160
161static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
163 .vco = { .min = 908000, .max = 1512000 },
164 .n = { .min = 2, .max = 16 },
165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
172};
173
174static const intel_limit_t intel_limits_i8xx_lvds = {
175 .dot = { .min = 25000, .max = 350000 },
176 .vco = { .min = 908000, .max = 1512000 },
177 .n = { .min = 2, .max = 16 },
178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
185};
186
187static const intel_limit_t intel_limits_i9xx_sdvo = {
188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
198};
199
200static const intel_limit_t intel_limits_i9xx_lvds = {
201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
211};
212
213
214static const intel_limit_t intel_limits_g4x_sdvo = {
215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
224 .p2_slow = 10,
225 .p2_fast = 10
226 },
227};
228
229static const intel_limit_t intel_limits_g4x_hdmi = {
230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
240};
241
242static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
253 },
254};
255
256static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
267 },
268};
269
270static const intel_limit_t intel_limits_pineview_sdvo = {
271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
283};
284
285static const intel_limit_t intel_limits_pineview_lvds = {
286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
296};
297
298/* Ironlake / Sandybridge
299 *
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
302 */
303static const intel_limit_t intel_limits_ironlake_dac = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
314};
315
316static const intel_limit_t intel_limits_ironlake_single_lvds = {
317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
327};
328
329static const intel_limit_t intel_limits_ironlake_dual_lvds = {
330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
340};
341
342/* LVDS 100mhz refclk limits. */
343static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
351 .p1 = { .min = 2, .max = 8 },
352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
354};
355
356static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
364 .p1 = { .min = 2, .max = 6 },
365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
367};
368
369static const intel_limit_t intel_limits_vlv = {
370 /*
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
375 */
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
381 .p1 = { .min = 2, .max = 3 },
382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
383};
384
385static const intel_limit_t intel_limits_chv = {
386 /*
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
391 */
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
393 .vco = { .min = 4800000, .max = 6480000 },
394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
399};
400
401static const intel_limit_t intel_limits_bxt = {
402 /* FIXME: find real dot limits */
403 .dot = { .min = 0, .max = INT_MAX },
404 .vco = { .min = 4800000, .max = 6700000 },
405 .n = { .min = 1, .max = 1 },
406 .m1 = { .min = 2, .max = 2 },
407 /* FIXME: find real m2 limits */
408 .m2 = { .min = 2 << 22, .max = 255 << 22 },
409 .p1 = { .min = 2, .max = 4 },
410 .p2 = { .p2_slow = 1, .p2_fast = 20 },
411};
412
413static bool
414needs_modeset(struct drm_crtc_state *state)
415{
416 return drm_atomic_crtc_needs_modeset(state);
417}
418
419/**
420 * Returns whether any output on the specified pipe is of the specified type
421 */
422bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
423{
424 struct drm_device *dev = crtc->base.dev;
425 struct intel_encoder *encoder;
426
427 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
428 if (encoder->type == type)
429 return true;
430
431 return false;
432}
433
434/**
435 * Returns whether any output on the specified pipe will have the specified
436 * type after a staged modeset is complete, i.e., the same as
437 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
438 * encoder->crtc.
439 */
440static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
441 int type)
442{
443 struct drm_atomic_state *state = crtc_state->base.state;
444 struct drm_connector *connector;
445 struct drm_connector_state *connector_state;
446 struct intel_encoder *encoder;
447 int i, num_connectors = 0;
448
449 for_each_connector_in_state(state, connector, connector_state, i) {
450 if (connector_state->crtc != crtc_state->base.crtc)
451 continue;
452
453 num_connectors++;
454
455 encoder = to_intel_encoder(connector_state->best_encoder);
456 if (encoder->type == type)
457 return true;
458 }
459
460 WARN_ON(num_connectors == 0);
461
462 return false;
463}
464
465static const intel_limit_t *
466intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
467{
468 struct drm_device *dev = crtc_state->base.crtc->dev;
469 const intel_limit_t *limit;
470
471 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
472 if (intel_is_dual_link_lvds(dev)) {
473 if (refclk == 100000)
474 limit = &intel_limits_ironlake_dual_lvds_100m;
475 else
476 limit = &intel_limits_ironlake_dual_lvds;
477 } else {
478 if (refclk == 100000)
479 limit = &intel_limits_ironlake_single_lvds_100m;
480 else
481 limit = &intel_limits_ironlake_single_lvds;
482 }
483 } else
484 limit = &intel_limits_ironlake_dac;
485
486 return limit;
487}
488
489static const intel_limit_t *
490intel_g4x_limit(struct intel_crtc_state *crtc_state)
491{
492 struct drm_device *dev = crtc_state->base.crtc->dev;
493 const intel_limit_t *limit;
494
495 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
496 if (intel_is_dual_link_lvds(dev))
497 limit = &intel_limits_g4x_dual_channel_lvds;
498 else
499 limit = &intel_limits_g4x_single_channel_lvds;
500 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
501 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
502 limit = &intel_limits_g4x_hdmi;
503 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
504 limit = &intel_limits_g4x_sdvo;
505 } else /* The option is for other outputs */
506 limit = &intel_limits_i9xx_sdvo;
507
508 return limit;
509}
510
511static const intel_limit_t *
512intel_limit(struct intel_crtc_state *crtc_state, int refclk)
513{
514 struct drm_device *dev = crtc_state->base.crtc->dev;
515 const intel_limit_t *limit;
516
517 if (IS_BROXTON(dev))
518 limit = &intel_limits_bxt;
519 else if (HAS_PCH_SPLIT(dev))
520 limit = intel_ironlake_limit(crtc_state, refclk);
521 else if (IS_G4X(dev)) {
522 limit = intel_g4x_limit(crtc_state);
523 } else if (IS_PINEVIEW(dev)) {
524 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
525 limit = &intel_limits_pineview_lvds;
526 else
527 limit = &intel_limits_pineview_sdvo;
528 } else if (IS_CHERRYVIEW(dev)) {
529 limit = &intel_limits_chv;
530 } else if (IS_VALLEYVIEW(dev)) {
531 limit = &intel_limits_vlv;
532 } else if (!IS_GEN2(dev)) {
533 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
534 limit = &intel_limits_i9xx_lvds;
535 else
536 limit = &intel_limits_i9xx_sdvo;
537 } else {
538 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
539 limit = &intel_limits_i8xx_lvds;
540 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
541 limit = &intel_limits_i8xx_dvo;
542 else
543 limit = &intel_limits_i8xx_dac;
544 }
545 return limit;
546}
547
548/*
549 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
550 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
551 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
552 * The helpers' return value is the rate of the clock that is fed to the
553 * display engine's pipe which can be the above fast dot clock rate or a
554 * divided-down version of it.
555 */
556/* m1 is reserved as 0 in Pineview, n is a ring counter */
557static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
558{
559 clock->m = clock->m2 + 2;
560 clock->p = clock->p1 * clock->p2;
561 if (WARN_ON(clock->n == 0 || clock->p == 0))
562 return 0;
563 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
564 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
565
566 return clock->dot;
567}
568
569static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
570{
571 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
572}
573
574static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
575{
576 clock->m = i9xx_dpll_compute_m(clock);
577 clock->p = clock->p1 * clock->p2;
578 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
579 return 0;
580 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
581 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
582
583 return clock->dot;
584}
585
586static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
587{
588 clock->m = clock->m1 * clock->m2;
589 clock->p = clock->p1 * clock->p2;
590 if (WARN_ON(clock->n == 0 || clock->p == 0))
591 return 0;
592 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
593 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
594
595 return clock->dot / 5;
596}
597
598int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
599{
600 clock->m = clock->m1 * clock->m2;
601 clock->p = clock->p1 * clock->p2;
602 if (WARN_ON(clock->n == 0 || clock->p == 0))
603 return 0;
604 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
605 clock->n << 22);
606 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
607
608 return clock->dot / 5;
609}
610
611#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
612/**
613 * Returns whether the given set of divisors are valid for a given refclk with
614 * the given connectors.
615 */
616
617static bool intel_PLL_is_valid(struct drm_device *dev,
618 const intel_limit_t *limit,
619 const intel_clock_t *clock)
620{
621 if (clock->n < limit->n.min || limit->n.max < clock->n)
622 INTELPllInvalid("n out of range\n");
623 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
624 INTELPllInvalid("p1 out of range\n");
625 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
626 INTELPllInvalid("m2 out of range\n");
627 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
628 INTELPllInvalid("m1 out of range\n");
629
630 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
631 if (clock->m1 <= clock->m2)
632 INTELPllInvalid("m1 <= m2\n");
633
634 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
635 if (clock->p < limit->p.min || limit->p.max < clock->p)
636 INTELPllInvalid("p out of range\n");
637 if (clock->m < limit->m.min || limit->m.max < clock->m)
638 INTELPllInvalid("m out of range\n");
639 }
640
641 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
642 INTELPllInvalid("vco out of range\n");
643 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
644 * connector, etc., rather than just a single range.
645 */
646 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
647 INTELPllInvalid("dot out of range\n");
648
649 return true;
650}
651
652static int
653i9xx_select_p2_div(const intel_limit_t *limit,
654 const struct intel_crtc_state *crtc_state,
655 int target)
656{
657 struct drm_device *dev = crtc_state->base.crtc->dev;
658
659 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
660 /*
661 * For LVDS just rely on its current settings for dual-channel.
662 * We haven't figured out how to reliably set up different
663 * single/dual channel state, if we even can.
664 */
665 if (intel_is_dual_link_lvds(dev))
666 return limit->p2.p2_fast;
667 else
668 return limit->p2.p2_slow;
669 } else {
670 if (target < limit->p2.dot_limit)
671 return limit->p2.p2_slow;
672 else
673 return limit->p2.p2_fast;
674 }
675}
676
677static bool
678i9xx_find_best_dpll(const intel_limit_t *limit,
679 struct intel_crtc_state *crtc_state,
680 int target, int refclk, intel_clock_t *match_clock,
681 intel_clock_t *best_clock)
682{
683 struct drm_device *dev = crtc_state->base.crtc->dev;
684 intel_clock_t clock;
685 int err = target;
686
687 memset(best_clock, 0, sizeof(*best_clock));
688
689 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
690
691 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
692 clock.m1++) {
693 for (clock.m2 = limit->m2.min;
694 clock.m2 <= limit->m2.max; clock.m2++) {
695 if (clock.m2 >= clock.m1)
696 break;
697 for (clock.n = limit->n.min;
698 clock.n <= limit->n.max; clock.n++) {
699 for (clock.p1 = limit->p1.min;
700 clock.p1 <= limit->p1.max; clock.p1++) {
701 int this_err;
702
703 i9xx_calc_dpll_params(refclk, &clock);
704 if (!intel_PLL_is_valid(dev, limit,
705 &clock))
706 continue;
707 if (match_clock &&
708 clock.p != match_clock->p)
709 continue;
710
711 this_err = abs(clock.dot - target);
712 if (this_err < err) {
713 *best_clock = clock;
714 err = this_err;
715 }
716 }
717 }
718 }
719 }
720
721 return (err != target);
722}
723
724static bool
725pnv_find_best_dpll(const intel_limit_t *limit,
726 struct intel_crtc_state *crtc_state,
727 int target, int refclk, intel_clock_t *match_clock,
728 intel_clock_t *best_clock)
729{
730 struct drm_device *dev = crtc_state->base.crtc->dev;
731 intel_clock_t clock;
732 int err = target;
733
734 memset(best_clock, 0, sizeof(*best_clock));
735
736 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
737
738 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
739 clock.m1++) {
740 for (clock.m2 = limit->m2.min;
741 clock.m2 <= limit->m2.max; clock.m2++) {
742 for (clock.n = limit->n.min;
743 clock.n <= limit->n.max; clock.n++) {
744 for (clock.p1 = limit->p1.min;
745 clock.p1 <= limit->p1.max; clock.p1++) {
746 int this_err;
747
748 pnv_calc_dpll_params(refclk, &clock);
749 if (!intel_PLL_is_valid(dev, limit,
750 &clock))
751 continue;
752 if (match_clock &&
753 clock.p != match_clock->p)
754 continue;
755
756 this_err = abs(clock.dot - target);
757 if (this_err < err) {
758 *best_clock = clock;
759 err = this_err;
760 }
761 }
762 }
763 }
764 }
765
766 return (err != target);
767}
768
769static bool
770g4x_find_best_dpll(const intel_limit_t *limit,
771 struct intel_crtc_state *crtc_state,
772 int target, int refclk, intel_clock_t *match_clock,
773 intel_clock_t *best_clock)
774{
775 struct drm_device *dev = crtc_state->base.crtc->dev;
776 intel_clock_t clock;
777 int max_n;
778 bool found = false;
779 /* approximately equals target * 0.00585 */
780 int err_most = (target >> 8) + (target >> 9);
781
782 memset(best_clock, 0, sizeof(*best_clock));
783
784 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
785
786 max_n = limit->n.max;
787 /* based on hardware requirement, prefer smaller n to precision */
788 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
789 /* based on hardware requirement, prefere larger m1,m2 */
790 for (clock.m1 = limit->m1.max;
791 clock.m1 >= limit->m1.min; clock.m1--) {
792 for (clock.m2 = limit->m2.max;
793 clock.m2 >= limit->m2.min; clock.m2--) {
794 for (clock.p1 = limit->p1.max;
795 clock.p1 >= limit->p1.min; clock.p1--) {
796 int this_err;
797
798 i9xx_calc_dpll_params(refclk, &clock);
799 if (!intel_PLL_is_valid(dev, limit,
800 &clock))
801 continue;
802
803 this_err = abs(clock.dot - target);
804 if (this_err < err_most) {
805 *best_clock = clock;
806 err_most = this_err;
807 max_n = clock.n;
808 found = true;
809 }
810 }
811 }
812 }
813 }
814 return found;
815}
816
817/*
818 * Check if the calculated PLL configuration is more optimal compared to the
819 * best configuration and error found so far. Return the calculated error.
820 */
821static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
822 const intel_clock_t *calculated_clock,
823 const intel_clock_t *best_clock,
824 unsigned int best_error_ppm,
825 unsigned int *error_ppm)
826{
827 /*
828 * For CHV ignore the error and consider only the P value.
829 * Prefer a bigger P value based on HW requirements.
830 */
831 if (IS_CHERRYVIEW(dev)) {
832 *error_ppm = 0;
833
834 return calculated_clock->p > best_clock->p;
835 }
836
837 if (WARN_ON_ONCE(!target_freq))
838 return false;
839
840 *error_ppm = div_u64(1000000ULL *
841 abs(target_freq - calculated_clock->dot),
842 target_freq);
843 /*
844 * Prefer a better P value over a better (smaller) error if the error
845 * is small. Ensure this preference for future configurations too by
846 * setting the error to 0.
847 */
848 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
849 *error_ppm = 0;
850
851 return true;
852 }
853
854 return *error_ppm + 10 < best_error_ppm;
855}
856
857static bool
858vlv_find_best_dpll(const intel_limit_t *limit,
859 struct intel_crtc_state *crtc_state,
860 int target, int refclk, intel_clock_t *match_clock,
861 intel_clock_t *best_clock)
862{
863 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
864 struct drm_device *dev = crtc->base.dev;
865 intel_clock_t clock;
866 unsigned int bestppm = 1000000;
867 /* min update 19.2 MHz */
868 int max_n = min(limit->n.max, refclk / 19200);
869 bool found = false;
870
871 target *= 5; /* fast clock */
872
873 memset(best_clock, 0, sizeof(*best_clock));
874
875 /* based on hardware requirement, prefer smaller n to precision */
876 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
877 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
878 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
879 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
880 clock.p = clock.p1 * clock.p2;
881 /* based on hardware requirement, prefer bigger m1,m2 values */
882 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
883 unsigned int ppm;
884
885 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
886 refclk * clock.m1);
887
888 vlv_calc_dpll_params(refclk, &clock);
889
890 if (!intel_PLL_is_valid(dev, limit,
891 &clock))
892 continue;
893
894 if (!vlv_PLL_is_optimal(dev, target,
895 &clock,
896 best_clock,
897 bestppm, &ppm))
898 continue;
899
900 *best_clock = clock;
901 bestppm = ppm;
902 found = true;
903 }
904 }
905 }
906 }
907
908 return found;
909}
910
911static bool
912chv_find_best_dpll(const intel_limit_t *limit,
913 struct intel_crtc_state *crtc_state,
914 int target, int refclk, intel_clock_t *match_clock,
915 intel_clock_t *best_clock)
916{
917 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
918 struct drm_device *dev = crtc->base.dev;
919 unsigned int best_error_ppm;
920 intel_clock_t clock;
921 uint64_t m2;
922 int found = false;
923
924 memset(best_clock, 0, sizeof(*best_clock));
925 best_error_ppm = 1000000;
926
927 /*
928 * Based on hardware doc, the n always set to 1, and m1 always
929 * set to 2. If requires to support 200Mhz refclk, we need to
930 * revisit this because n may not 1 anymore.
931 */
932 clock.n = 1, clock.m1 = 2;
933 target *= 5; /* fast clock */
934
935 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
936 for (clock.p2 = limit->p2.p2_fast;
937 clock.p2 >= limit->p2.p2_slow;
938 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
939 unsigned int error_ppm;
940
941 clock.p = clock.p1 * clock.p2;
942
943 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
944 clock.n) << 22, refclk * clock.m1);
945
946 if (m2 > INT_MAX/clock.m1)
947 continue;
948
949 clock.m2 = m2;
950
951 chv_calc_dpll_params(refclk, &clock);
952
953 if (!intel_PLL_is_valid(dev, limit, &clock))
954 continue;
955
956 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
957 best_error_ppm, &error_ppm))
958 continue;
959
960 *best_clock = clock;
961 best_error_ppm = error_ppm;
962 found = true;
963 }
964 }
965
966 return found;
967}
968
969bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
970 intel_clock_t *best_clock)
971{
972 int refclk = i9xx_get_refclk(crtc_state, 0);
973
974 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
975 target_clock, refclk, NULL, best_clock);
976}
977
978bool intel_crtc_active(struct drm_crtc *crtc)
979{
980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
981
982 /* Be paranoid as we can arrive here with only partial
983 * state retrieved from the hardware during setup.
984 *
985 * We can ditch the adjusted_mode.crtc_clock check as soon
986 * as Haswell has gained clock readout/fastboot support.
987 *
988 * We can ditch the crtc->primary->fb check as soon as we can
989 * properly reconstruct framebuffers.
990 *
991 * FIXME: The intel_crtc->active here should be switched to
992 * crtc->state->active once we have proper CRTC states wired up
993 * for atomic.
994 */
995 return intel_crtc->active && crtc->primary->state->fb &&
996 intel_crtc->config->base.adjusted_mode.crtc_clock;
997}
998
999enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1000 enum pipe pipe)
1001{
1002 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1004
1005 return intel_crtc->config->cpu_transcoder;
1006}
1007
1008static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1009{
1010 struct drm_i915_private *dev_priv = dev->dev_private;
1011 u32 reg = PIPEDSL(pipe);
1012 u32 line1, line2;
1013 u32 line_mask;
1014
1015 if (IS_GEN2(dev))
1016 line_mask = DSL_LINEMASK_GEN2;
1017 else
1018 line_mask = DSL_LINEMASK_GEN3;
1019
1020 line1 = I915_READ(reg) & line_mask;
1021 msleep(5);
1022 line2 = I915_READ(reg) & line_mask;
1023
1024 return line1 == line2;
1025}
1026
1027/*
1028 * intel_wait_for_pipe_off - wait for pipe to turn off
1029 * @crtc: crtc whose pipe to wait for
1030 *
1031 * After disabling a pipe, we can't wait for vblank in the usual way,
1032 * spinning on the vblank interrupt status bit, since we won't actually
1033 * see an interrupt when the pipe is disabled.
1034 *
1035 * On Gen4 and above:
1036 * wait for the pipe register state bit to turn off
1037 *
1038 * Otherwise:
1039 * wait for the display line value to settle (it usually
1040 * ends up stopping at the start of the next frame).
1041 *
1042 */
1043static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1044{
1045 struct drm_device *dev = crtc->base.dev;
1046 struct drm_i915_private *dev_priv = dev->dev_private;
1047 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1048 enum pipe pipe = crtc->pipe;
1049
1050 if (INTEL_INFO(dev)->gen >= 4) {
1051 int reg = PIPECONF(cpu_transcoder);
1052
1053 /* Wait for the Pipe State to go off */
1054 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1055 100))
1056 WARN(1, "pipe_off wait timed out\n");
1057 } else {
1058 /* Wait for the display line to settle */
1059 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1060 WARN(1, "pipe_off wait timed out\n");
1061 }
1062}
1063
1064/*
1065 * ibx_digital_port_connected - is the specified port connected?
1066 * @dev_priv: i915 private structure
1067 * @port: the port to test
1068 *
1069 * Returns true if @port is connected, false otherwise.
1070 */
1071bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1072 struct intel_digital_port *port)
1073{
1074 u32 bit;
1075
1076 if (HAS_PCH_IBX(dev_priv->dev)) {
1077 switch (port->port) {
1078 case PORT_B:
1079 bit = SDE_PORTB_HOTPLUG;
1080 break;
1081 case PORT_C:
1082 bit = SDE_PORTC_HOTPLUG;
1083 break;
1084 case PORT_D:
1085 bit = SDE_PORTD_HOTPLUG;
1086 break;
1087 default:
1088 return true;
1089 }
1090 } else {
1091 switch (port->port) {
1092 case PORT_B:
1093 bit = SDE_PORTB_HOTPLUG_CPT;
1094 break;
1095 case PORT_C:
1096 bit = SDE_PORTC_HOTPLUG_CPT;
1097 break;
1098 case PORT_D:
1099 bit = SDE_PORTD_HOTPLUG_CPT;
1100 break;
1101 case PORT_E:
1102 bit = SDE_PORTE_HOTPLUG_SPT;
1103 break;
1104 default:
1105 return true;
1106 }
1107 }
1108
1109 return I915_READ(SDEISR) & bit;
1110}
1111
1112static const char *state_string(bool enabled)
1113{
1114 return enabled ? "on" : "off";
1115}
1116
1117/* Only for pre-ILK configs */
1118void assert_pll(struct drm_i915_private *dev_priv,
1119 enum pipe pipe, bool state)
1120{
1121 int reg;
1122 u32 val;
1123 bool cur_state;
1124
1125 reg = DPLL(pipe);
1126 val = I915_READ(reg);
1127 cur_state = !!(val & DPLL_VCO_ENABLE);
1128 I915_STATE_WARN(cur_state != state,
1129 "PLL state assertion failure (expected %s, current %s)\n",
1130 state_string(state), state_string(cur_state));
1131}
1132
1133/* XXX: the dsi pll is shared between MIPI DSI ports */
1134static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1135{
1136 u32 val;
1137 bool cur_state;
1138
1139 mutex_lock(&dev_priv->sb_lock);
1140 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1141 mutex_unlock(&dev_priv->sb_lock);
1142
1143 cur_state = val & DSI_PLL_VCO_EN;
1144 I915_STATE_WARN(cur_state != state,
1145 "DSI PLL state assertion failure (expected %s, current %s)\n",
1146 state_string(state), state_string(cur_state));
1147}
1148#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1149#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1150
1151struct intel_shared_dpll *
1152intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1153{
1154 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1155
1156 if (crtc->config->shared_dpll < 0)
1157 return NULL;
1158
1159 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1160}
1161
1162/* For ILK+ */
1163void assert_shared_dpll(struct drm_i915_private *dev_priv,
1164 struct intel_shared_dpll *pll,
1165 bool state)
1166{
1167 bool cur_state;
1168 struct intel_dpll_hw_state hw_state;
1169
1170 if (WARN (!pll,
1171 "asserting DPLL %s with no DPLL\n", state_string(state)))
1172 return;
1173
1174 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1175 I915_STATE_WARN(cur_state != state,
1176 "%s assertion failure (expected %s, current %s)\n",
1177 pll->name, state_string(state), state_string(cur_state));
1178}
1179
1180static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1181 enum pipe pipe, bool state)
1182{
1183 int reg;
1184 u32 val;
1185 bool cur_state;
1186 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1187 pipe);
1188
1189 if (HAS_DDI(dev_priv->dev)) {
1190 /* DDI does not have a specific FDI_TX register */
1191 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1192 val = I915_READ(reg);
1193 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1194 } else {
1195 reg = FDI_TX_CTL(pipe);
1196 val = I915_READ(reg);
1197 cur_state = !!(val & FDI_TX_ENABLE);
1198 }
1199 I915_STATE_WARN(cur_state != state,
1200 "FDI TX state assertion failure (expected %s, current %s)\n",
1201 state_string(state), state_string(cur_state));
1202}
1203#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1204#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1205
1206static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1207 enum pipe pipe, bool state)
1208{
1209 int reg;
1210 u32 val;
1211 bool cur_state;
1212
1213 reg = FDI_RX_CTL(pipe);
1214 val = I915_READ(reg);
1215 cur_state = !!(val & FDI_RX_ENABLE);
1216 I915_STATE_WARN(cur_state != state,
1217 "FDI RX state assertion failure (expected %s, current %s)\n",
1218 state_string(state), state_string(cur_state));
1219}
1220#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1221#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1222
1223static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1224 enum pipe pipe)
1225{
1226 int reg;
1227 u32 val;
1228
1229 /* ILK FDI PLL is always enabled */
1230 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1231 return;
1232
1233 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1234 if (HAS_DDI(dev_priv->dev))
1235 return;
1236
1237 reg = FDI_TX_CTL(pipe);
1238 val = I915_READ(reg);
1239 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1240}
1241
1242void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1243 enum pipe pipe, bool state)
1244{
1245 int reg;
1246 u32 val;
1247 bool cur_state;
1248
1249 reg = FDI_RX_CTL(pipe);
1250 val = I915_READ(reg);
1251 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1252 I915_STATE_WARN(cur_state != state,
1253 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1254 state_string(state), state_string(cur_state));
1255}
1256
1257void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1258 enum pipe pipe)
1259{
1260 struct drm_device *dev = dev_priv->dev;
1261 int pp_reg;
1262 u32 val;
1263 enum pipe panel_pipe = PIPE_A;
1264 bool locked = true;
1265
1266 if (WARN_ON(HAS_DDI(dev)))
1267 return;
1268
1269 if (HAS_PCH_SPLIT(dev)) {
1270 u32 port_sel;
1271
1272 pp_reg = PCH_PP_CONTROL;
1273 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1274
1275 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1276 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1277 panel_pipe = PIPE_B;
1278 /* XXX: else fix for eDP */
1279 } else if (IS_VALLEYVIEW(dev)) {
1280 /* presumably write lock depends on pipe, not port select */
1281 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1282 panel_pipe = pipe;
1283 } else {
1284 pp_reg = PP_CONTROL;
1285 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1286 panel_pipe = PIPE_B;
1287 }
1288
1289 val = I915_READ(pp_reg);
1290 if (!(val & PANEL_POWER_ON) ||
1291 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1292 locked = false;
1293
1294 I915_STATE_WARN(panel_pipe == pipe && locked,
1295 "panel assertion failure, pipe %c regs locked\n",
1296 pipe_name(pipe));
1297}
1298
1299static void assert_cursor(struct drm_i915_private *dev_priv,
1300 enum pipe pipe, bool state)
1301{
1302 struct drm_device *dev = dev_priv->dev;
1303 bool cur_state;
1304
1305 if (IS_845G(dev) || IS_I865G(dev))
1306 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1307 else
1308 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1309
1310 I915_STATE_WARN(cur_state != state,
1311 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1312 pipe_name(pipe), state_string(state), state_string(cur_state));
1313}
1314#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1315#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1316
1317void assert_pipe(struct drm_i915_private *dev_priv,
1318 enum pipe pipe, bool state)
1319{
1320 int reg;
1321 u32 val;
1322 bool cur_state;
1323 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1324 pipe);
1325
1326 /* if we need the pipe quirk it must be always on */
1327 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1328 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1329 state = true;
1330
1331 if (!intel_display_power_is_enabled(dev_priv,
1332 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1333 cur_state = false;
1334 } else {
1335 reg = PIPECONF(cpu_transcoder);
1336 val = I915_READ(reg);
1337 cur_state = !!(val & PIPECONF_ENABLE);
1338 }
1339
1340 I915_STATE_WARN(cur_state != state,
1341 "pipe %c assertion failure (expected %s, current %s)\n",
1342 pipe_name(pipe), state_string(state), state_string(cur_state));
1343}
1344
1345static void assert_plane(struct drm_i915_private *dev_priv,
1346 enum plane plane, bool state)
1347{
1348 int reg;
1349 u32 val;
1350 bool cur_state;
1351
1352 reg = DSPCNTR(plane);
1353 val = I915_READ(reg);
1354 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1355 I915_STATE_WARN(cur_state != state,
1356 "plane %c assertion failure (expected %s, current %s)\n",
1357 plane_name(plane), state_string(state), state_string(cur_state));
1358}
1359
1360#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1361#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1362
1363static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1364 enum pipe pipe)
1365{
1366 struct drm_device *dev = dev_priv->dev;
1367 int reg, i;
1368 u32 val;
1369 int cur_pipe;
1370
1371 /* Primary planes are fixed to pipes on gen4+ */
1372 if (INTEL_INFO(dev)->gen >= 4) {
1373 reg = DSPCNTR(pipe);
1374 val = I915_READ(reg);
1375 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1376 "plane %c assertion failure, should be disabled but not\n",
1377 plane_name(pipe));
1378 return;
1379 }
1380
1381 /* Need to check both planes against the pipe */
1382 for_each_pipe(dev_priv, i) {
1383 reg = DSPCNTR(i);
1384 val = I915_READ(reg);
1385 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1386 DISPPLANE_SEL_PIPE_SHIFT;
1387 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1388 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1389 plane_name(i), pipe_name(pipe));
1390 }
1391}
1392
1393static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1394 enum pipe pipe)
1395{
1396 struct drm_device *dev = dev_priv->dev;
1397 int reg, sprite;
1398 u32 val;
1399
1400 if (INTEL_INFO(dev)->gen >= 9) {
1401 for_each_sprite(dev_priv, pipe, sprite) {
1402 val = I915_READ(PLANE_CTL(pipe, sprite));
1403 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1404 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1405 sprite, pipe_name(pipe));
1406 }
1407 } else if (IS_VALLEYVIEW(dev)) {
1408 for_each_sprite(dev_priv, pipe, sprite) {
1409 reg = SPCNTR(pipe, sprite);
1410 val = I915_READ(reg);
1411 I915_STATE_WARN(val & SP_ENABLE,
1412 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1413 sprite_name(pipe, sprite), pipe_name(pipe));
1414 }
1415 } else if (INTEL_INFO(dev)->gen >= 7) {
1416 reg = SPRCTL(pipe);
1417 val = I915_READ(reg);
1418 I915_STATE_WARN(val & SPRITE_ENABLE,
1419 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1420 plane_name(pipe), pipe_name(pipe));
1421 } else if (INTEL_INFO(dev)->gen >= 5) {
1422 reg = DVSCNTR(pipe);
1423 val = I915_READ(reg);
1424 I915_STATE_WARN(val & DVS_ENABLE,
1425 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1426 plane_name(pipe), pipe_name(pipe));
1427 }
1428}
1429
1430static void assert_vblank_disabled(struct drm_crtc *crtc)
1431{
1432 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1433 drm_crtc_vblank_put(crtc);
1434}
1435
1436static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1437{
1438 u32 val;
1439 bool enabled;
1440
1441 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1442
1443 val = I915_READ(PCH_DREF_CONTROL);
1444 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1445 DREF_SUPERSPREAD_SOURCE_MASK));
1446 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1447}
1448
1449static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1450 enum pipe pipe)
1451{
1452 int reg;
1453 u32 val;
1454 bool enabled;
1455
1456 reg = PCH_TRANSCONF(pipe);
1457 val = I915_READ(reg);
1458 enabled = !!(val & TRANS_ENABLE);
1459 I915_STATE_WARN(enabled,
1460 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1461 pipe_name(pipe));
1462}
1463
1464static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1465 enum pipe pipe, u32 port_sel, u32 val)
1466{
1467 if ((val & DP_PORT_EN) == 0)
1468 return false;
1469
1470 if (HAS_PCH_CPT(dev_priv->dev)) {
1471 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1472 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1473 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1474 return false;
1475 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1476 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1477 return false;
1478 } else {
1479 if ((val & DP_PIPE_MASK) != (pipe << 30))
1480 return false;
1481 }
1482 return true;
1483}
1484
1485static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1486 enum pipe pipe, u32 val)
1487{
1488 if ((val & SDVO_ENABLE) == 0)
1489 return false;
1490
1491 if (HAS_PCH_CPT(dev_priv->dev)) {
1492 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1493 return false;
1494 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1495 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1496 return false;
1497 } else {
1498 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1499 return false;
1500 }
1501 return true;
1502}
1503
1504static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1505 enum pipe pipe, u32 val)
1506{
1507 if ((val & LVDS_PORT_EN) == 0)
1508 return false;
1509
1510 if (HAS_PCH_CPT(dev_priv->dev)) {
1511 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1512 return false;
1513 } else {
1514 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1515 return false;
1516 }
1517 return true;
1518}
1519
1520static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1521 enum pipe pipe, u32 val)
1522{
1523 if ((val & ADPA_DAC_ENABLE) == 0)
1524 return false;
1525 if (HAS_PCH_CPT(dev_priv->dev)) {
1526 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1527 return false;
1528 } else {
1529 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1530 return false;
1531 }
1532 return true;
1533}
1534
1535static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1536 enum pipe pipe, int reg, u32 port_sel)
1537{
1538 u32 val = I915_READ(reg);
1539 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1540 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1541 reg, pipe_name(pipe));
1542
1543 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1544 && (val & DP_PIPEB_SELECT),
1545 "IBX PCH dp port still using transcoder B\n");
1546}
1547
1548static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1549 enum pipe pipe, int reg)
1550{
1551 u32 val = I915_READ(reg);
1552 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1553 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1554 reg, pipe_name(pipe));
1555
1556 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1557 && (val & SDVO_PIPE_B_SELECT),
1558 "IBX PCH hdmi port still using transcoder B\n");
1559}
1560
1561static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1562 enum pipe pipe)
1563{
1564 int reg;
1565 u32 val;
1566
1567 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1568 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1569 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1570
1571 reg = PCH_ADPA;
1572 val = I915_READ(reg);
1573 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1574 "PCH VGA enabled on transcoder %c, should be disabled\n",
1575 pipe_name(pipe));
1576
1577 reg = PCH_LVDS;
1578 val = I915_READ(reg);
1579 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1580 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1581 pipe_name(pipe));
1582
1583 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1584 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1585 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1586}
1587
1588static void intel_init_dpio(struct drm_device *dev)
1589{
1590 struct drm_i915_private *dev_priv = dev->dev_private;
1591
1592 if (!IS_VALLEYVIEW(dev))
1593 return;
1594
1595 /*
1596 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1597 * CHV x1 PHY (DP/HDMI D)
1598 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1599 */
1600 if (IS_CHERRYVIEW(dev)) {
1601 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1602 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1603 } else {
1604 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1605 }
1606}
1607
1608static void vlv_enable_pll(struct intel_crtc *crtc,
1609 const struct intel_crtc_state *pipe_config)
1610{
1611 struct drm_device *dev = crtc->base.dev;
1612 struct drm_i915_private *dev_priv = dev->dev_private;
1613 int reg = DPLL(crtc->pipe);
1614 u32 dpll = pipe_config->dpll_hw_state.dpll;
1615
1616 assert_pipe_disabled(dev_priv, crtc->pipe);
1617
1618 /* No really, not for ILK+ */
1619 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1620
1621 /* PLL is protected by panel, make sure we can write it */
1622 if (IS_MOBILE(dev_priv->dev))
1623 assert_panel_unlocked(dev_priv, crtc->pipe);
1624
1625 I915_WRITE(reg, dpll);
1626 POSTING_READ(reg);
1627 udelay(150);
1628
1629 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1630 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1631
1632 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1633 POSTING_READ(DPLL_MD(crtc->pipe));
1634
1635 /* We do this three times for luck */
1636 I915_WRITE(reg, dpll);
1637 POSTING_READ(reg);
1638 udelay(150); /* wait for warmup */
1639 I915_WRITE(reg, dpll);
1640 POSTING_READ(reg);
1641 udelay(150); /* wait for warmup */
1642 I915_WRITE(reg, dpll);
1643 POSTING_READ(reg);
1644 udelay(150); /* wait for warmup */
1645}
1646
1647static void chv_enable_pll(struct intel_crtc *crtc,
1648 const struct intel_crtc_state *pipe_config)
1649{
1650 struct drm_device *dev = crtc->base.dev;
1651 struct drm_i915_private *dev_priv = dev->dev_private;
1652 int pipe = crtc->pipe;
1653 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1654 u32 tmp;
1655
1656 assert_pipe_disabled(dev_priv, crtc->pipe);
1657
1658 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1659
1660 mutex_lock(&dev_priv->sb_lock);
1661
1662 /* Enable back the 10bit clock to display controller */
1663 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1664 tmp |= DPIO_DCLKP_EN;
1665 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1666
1667 mutex_unlock(&dev_priv->sb_lock);
1668
1669 /*
1670 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1671 */
1672 udelay(1);
1673
1674 /* Enable PLL */
1675 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1676
1677 /* Check PLL is locked */
1678 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1679 DRM_ERROR("PLL %d failed to lock\n", pipe);
1680
1681 /* not sure when this should be written */
1682 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1683 POSTING_READ(DPLL_MD(pipe));
1684}
1685
1686static int intel_num_dvo_pipes(struct drm_device *dev)
1687{
1688 struct intel_crtc *crtc;
1689 int count = 0;
1690
1691 for_each_intel_crtc(dev, crtc)
1692 count += crtc->base.state->active &&
1693 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1694
1695 return count;
1696}
1697
1698static void i9xx_enable_pll(struct intel_crtc *crtc)
1699{
1700 struct drm_device *dev = crtc->base.dev;
1701 struct drm_i915_private *dev_priv = dev->dev_private;
1702 int reg = DPLL(crtc->pipe);
1703 u32 dpll = crtc->config->dpll_hw_state.dpll;
1704
1705 assert_pipe_disabled(dev_priv, crtc->pipe);
1706
1707 /* No really, not for ILK+ */
1708 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1709
1710 /* PLL is protected by panel, make sure we can write it */
1711 if (IS_MOBILE(dev) && !IS_I830(dev))
1712 assert_panel_unlocked(dev_priv, crtc->pipe);
1713
1714 /* Enable DVO 2x clock on both PLLs if necessary */
1715 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1716 /*
1717 * It appears to be important that we don't enable this
1718 * for the current pipe before otherwise configuring the
1719 * PLL. No idea how this should be handled if multiple
1720 * DVO outputs are enabled simultaneosly.
1721 */
1722 dpll |= DPLL_DVO_2X_MODE;
1723 I915_WRITE(DPLL(!crtc->pipe),
1724 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1725 }
1726
1727 I915_WRITE(reg, dpll);
1728
1729 /* Wait for the clocks to stabilize. */
1730 POSTING_READ(reg);
1731 udelay(150);
1732
1733 if (INTEL_INFO(dev)->gen >= 4) {
1734 I915_WRITE(DPLL_MD(crtc->pipe),
1735 crtc->config->dpll_hw_state.dpll_md);
1736 } else {
1737 /* The pixel multiplier can only be updated once the
1738 * DPLL is enabled and the clocks are stable.
1739 *
1740 * So write it again.
1741 */
1742 I915_WRITE(reg, dpll);
1743 }
1744
1745 /* We do this three times for luck */
1746 I915_WRITE(reg, dpll);
1747 POSTING_READ(reg);
1748 udelay(150); /* wait for warmup */
1749 I915_WRITE(reg, dpll);
1750 POSTING_READ(reg);
1751 udelay(150); /* wait for warmup */
1752 I915_WRITE(reg, dpll);
1753 POSTING_READ(reg);
1754 udelay(150); /* wait for warmup */
1755}
1756
1757/**
1758 * i9xx_disable_pll - disable a PLL
1759 * @dev_priv: i915 private structure
1760 * @pipe: pipe PLL to disable
1761 *
1762 * Disable the PLL for @pipe, making sure the pipe is off first.
1763 *
1764 * Note! This is for pre-ILK only.
1765 */
1766static void i9xx_disable_pll(struct intel_crtc *crtc)
1767{
1768 struct drm_device *dev = crtc->base.dev;
1769 struct drm_i915_private *dev_priv = dev->dev_private;
1770 enum pipe pipe = crtc->pipe;
1771
1772 /* Disable DVO 2x clock on both PLLs if necessary */
1773 if (IS_I830(dev) &&
1774 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1775 !intel_num_dvo_pipes(dev)) {
1776 I915_WRITE(DPLL(PIPE_B),
1777 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1778 I915_WRITE(DPLL(PIPE_A),
1779 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1780 }
1781
1782 /* Don't disable pipe or pipe PLLs if needed */
1783 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1784 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1785 return;
1786
1787 /* Make sure the pipe isn't still relying on us */
1788 assert_pipe_disabled(dev_priv, pipe);
1789
1790 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1791 POSTING_READ(DPLL(pipe));
1792}
1793
1794static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1795{
1796 u32 val;
1797
1798 /* Make sure the pipe isn't still relying on us */
1799 assert_pipe_disabled(dev_priv, pipe);
1800
1801 /*
1802 * Leave integrated clock source and reference clock enabled for pipe B.
1803 * The latter is needed for VGA hotplug / manual detection.
1804 */
1805 val = DPLL_VGA_MODE_DIS;
1806 if (pipe == PIPE_B)
1807 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1808 I915_WRITE(DPLL(pipe), val);
1809 POSTING_READ(DPLL(pipe));
1810
1811}
1812
1813static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1814{
1815 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1816 u32 val;
1817
1818 /* Make sure the pipe isn't still relying on us */
1819 assert_pipe_disabled(dev_priv, pipe);
1820
1821 /* Set PLL en = 0 */
1822 val = DPLL_SSC_REF_CLK_CHV |
1823 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1824 if (pipe != PIPE_A)
1825 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1826 I915_WRITE(DPLL(pipe), val);
1827 POSTING_READ(DPLL(pipe));
1828
1829 mutex_lock(&dev_priv->sb_lock);
1830
1831 /* Disable 10bit clock to display controller */
1832 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1833 val &= ~DPIO_DCLKP_EN;
1834 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1835
1836 /* disable left/right clock distribution */
1837 if (pipe != PIPE_B) {
1838 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1839 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1840 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1841 } else {
1842 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1843 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1844 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1845 }
1846
1847 mutex_unlock(&dev_priv->sb_lock);
1848}
1849
1850void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1851 struct intel_digital_port *dport,
1852 unsigned int expected_mask)
1853{
1854 u32 port_mask;
1855 int dpll_reg;
1856
1857 switch (dport->port) {
1858 case PORT_B:
1859 port_mask = DPLL_PORTB_READY_MASK;
1860 dpll_reg = DPLL(0);
1861 break;
1862 case PORT_C:
1863 port_mask = DPLL_PORTC_READY_MASK;
1864 dpll_reg = DPLL(0);
1865 expected_mask <<= 4;
1866 break;
1867 case PORT_D:
1868 port_mask = DPLL_PORTD_READY_MASK;
1869 dpll_reg = DPIO_PHY_STATUS;
1870 break;
1871 default:
1872 BUG();
1873 }
1874
1875 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1876 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1877 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1878}
1879
1880static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1881{
1882 struct drm_device *dev = crtc->base.dev;
1883 struct drm_i915_private *dev_priv = dev->dev_private;
1884 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1885
1886 if (WARN_ON(pll == NULL))
1887 return;
1888
1889 WARN_ON(!pll->config.crtc_mask);
1890 if (pll->active == 0) {
1891 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1892 WARN_ON(pll->on);
1893 assert_shared_dpll_disabled(dev_priv, pll);
1894
1895 pll->mode_set(dev_priv, pll);
1896 }
1897}
1898
1899/**
1900 * intel_enable_shared_dpll - enable PCH PLL
1901 * @dev_priv: i915 private structure
1902 * @pipe: pipe PLL to enable
1903 *
1904 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1905 * drives the transcoder clock.
1906 */
1907static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1908{
1909 struct drm_device *dev = crtc->base.dev;
1910 struct drm_i915_private *dev_priv = dev->dev_private;
1911 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1912
1913 if (WARN_ON(pll == NULL))
1914 return;
1915
1916 if (WARN_ON(pll->config.crtc_mask == 0))
1917 return;
1918
1919 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1920 pll->name, pll->active, pll->on,
1921 crtc->base.base.id);
1922
1923 if (pll->active++) {
1924 WARN_ON(!pll->on);
1925 assert_shared_dpll_enabled(dev_priv, pll);
1926 return;
1927 }
1928 WARN_ON(pll->on);
1929
1930 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1931
1932 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1933 pll->enable(dev_priv, pll);
1934 pll->on = true;
1935}
1936
1937static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1938{
1939 struct drm_device *dev = crtc->base.dev;
1940 struct drm_i915_private *dev_priv = dev->dev_private;
1941 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1942
1943 /* PCH only available on ILK+ */
1944 if (INTEL_INFO(dev)->gen < 5)
1945 return;
1946
1947 if (pll == NULL)
1948 return;
1949
1950 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1951 return;
1952
1953 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1954 pll->name, pll->active, pll->on,
1955 crtc->base.base.id);
1956
1957 if (WARN_ON(pll->active == 0)) {
1958 assert_shared_dpll_disabled(dev_priv, pll);
1959 return;
1960 }
1961
1962 assert_shared_dpll_enabled(dev_priv, pll);
1963 WARN_ON(!pll->on);
1964 if (--pll->active)
1965 return;
1966
1967 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1968 pll->disable(dev_priv, pll);
1969 pll->on = false;
1970
1971 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1972}
1973
1974static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1975 enum pipe pipe)
1976{
1977 struct drm_device *dev = dev_priv->dev;
1978 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1979 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1980 uint32_t reg, val, pipeconf_val;
1981
1982 /* PCH only available on ILK+ */
1983 BUG_ON(!HAS_PCH_SPLIT(dev));
1984
1985 /* Make sure PCH DPLL is enabled */
1986 assert_shared_dpll_enabled(dev_priv,
1987 intel_crtc_to_shared_dpll(intel_crtc));
1988
1989 /* FDI must be feeding us bits for PCH ports */
1990 assert_fdi_tx_enabled(dev_priv, pipe);
1991 assert_fdi_rx_enabled(dev_priv, pipe);
1992
1993 if (HAS_PCH_CPT(dev)) {
1994 /* Workaround: Set the timing override bit before enabling the
1995 * pch transcoder. */
1996 reg = TRANS_CHICKEN2(pipe);
1997 val = I915_READ(reg);
1998 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1999 I915_WRITE(reg, val);
2000 }
2001
2002 reg = PCH_TRANSCONF(pipe);
2003 val = I915_READ(reg);
2004 pipeconf_val = I915_READ(PIPECONF(pipe));
2005
2006 if (HAS_PCH_IBX(dev_priv->dev)) {
2007 /*
2008 * Make the BPC in transcoder be consistent with
2009 * that in pipeconf reg. For HDMI we must use 8bpc
2010 * here for both 8bpc and 12bpc.
2011 */
2012 val &= ~PIPECONF_BPC_MASK;
2013 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2014 val |= PIPECONF_8BPC;
2015 else
2016 val |= pipeconf_val & PIPECONF_BPC_MASK;
2017 }
2018
2019 val &= ~TRANS_INTERLACE_MASK;
2020 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2021 if (HAS_PCH_IBX(dev_priv->dev) &&
2022 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2023 val |= TRANS_LEGACY_INTERLACED_ILK;
2024 else
2025 val |= TRANS_INTERLACED;
2026 else
2027 val |= TRANS_PROGRESSIVE;
2028
2029 I915_WRITE(reg, val | TRANS_ENABLE);
2030 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2031 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2032}
2033
2034static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2035 enum transcoder cpu_transcoder)
2036{
2037 u32 val, pipeconf_val;
2038
2039 /* PCH only available on ILK+ */
2040 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2041
2042 /* FDI must be feeding us bits for PCH ports */
2043 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2044 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2045
2046 /* Workaround: set timing override bit. */
2047 val = I915_READ(_TRANSA_CHICKEN2);
2048 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2049 I915_WRITE(_TRANSA_CHICKEN2, val);
2050
2051 val = TRANS_ENABLE;
2052 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2053
2054 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2055 PIPECONF_INTERLACED_ILK)
2056 val |= TRANS_INTERLACED;
2057 else
2058 val |= TRANS_PROGRESSIVE;
2059
2060 I915_WRITE(LPT_TRANSCONF, val);
2061 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2062 DRM_ERROR("Failed to enable PCH transcoder\n");
2063}
2064
2065static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2066 enum pipe pipe)
2067{
2068 struct drm_device *dev = dev_priv->dev;
2069 uint32_t reg, val;
2070
2071 /* FDI relies on the transcoder */
2072 assert_fdi_tx_disabled(dev_priv, pipe);
2073 assert_fdi_rx_disabled(dev_priv, pipe);
2074
2075 /* Ports must be off as well */
2076 assert_pch_ports_disabled(dev_priv, pipe);
2077
2078 reg = PCH_TRANSCONF(pipe);
2079 val = I915_READ(reg);
2080 val &= ~TRANS_ENABLE;
2081 I915_WRITE(reg, val);
2082 /* wait for PCH transcoder off, transcoder state */
2083 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2084 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2085
2086 if (!HAS_PCH_IBX(dev)) {
2087 /* Workaround: Clear the timing override chicken bit again. */
2088 reg = TRANS_CHICKEN2(pipe);
2089 val = I915_READ(reg);
2090 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2091 I915_WRITE(reg, val);
2092 }
2093}
2094
2095static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2096{
2097 u32 val;
2098
2099 val = I915_READ(LPT_TRANSCONF);
2100 val &= ~TRANS_ENABLE;
2101 I915_WRITE(LPT_TRANSCONF, val);
2102 /* wait for PCH transcoder off, transcoder state */
2103 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2104 DRM_ERROR("Failed to disable PCH transcoder\n");
2105
2106 /* Workaround: clear timing override bit. */
2107 val = I915_READ(_TRANSA_CHICKEN2);
2108 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2109 I915_WRITE(_TRANSA_CHICKEN2, val);
2110}
2111
2112/**
2113 * intel_enable_pipe - enable a pipe, asserting requirements
2114 * @crtc: crtc responsible for the pipe
2115 *
2116 * Enable @crtc's pipe, making sure that various hardware specific requirements
2117 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2118 */
2119static void intel_enable_pipe(struct intel_crtc *crtc)
2120{
2121 struct drm_device *dev = crtc->base.dev;
2122 struct drm_i915_private *dev_priv = dev->dev_private;
2123 enum pipe pipe = crtc->pipe;
2124 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2125 pipe);
2126 enum pipe pch_transcoder;
2127 int reg;
2128 u32 val;
2129
2130 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2131
2132 assert_planes_disabled(dev_priv, pipe);
2133 assert_cursor_disabled(dev_priv, pipe);
2134 assert_sprites_disabled(dev_priv, pipe);
2135
2136 if (HAS_PCH_LPT(dev_priv->dev))
2137 pch_transcoder = TRANSCODER_A;
2138 else
2139 pch_transcoder = pipe;
2140
2141 /*
2142 * A pipe without a PLL won't actually be able to drive bits from
2143 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2144 * need the check.
2145 */
2146 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2147 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2148 assert_dsi_pll_enabled(dev_priv);
2149 else
2150 assert_pll_enabled(dev_priv, pipe);
2151 else {
2152 if (crtc->config->has_pch_encoder) {
2153 /* if driving the PCH, we need FDI enabled */
2154 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2155 assert_fdi_tx_pll_enabled(dev_priv,
2156 (enum pipe) cpu_transcoder);
2157 }
2158 /* FIXME: assert CPU port conditions for SNB+ */
2159 }
2160
2161 reg = PIPECONF(cpu_transcoder);
2162 val = I915_READ(reg);
2163 if (val & PIPECONF_ENABLE) {
2164 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2165 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2166 return;
2167 }
2168
2169 I915_WRITE(reg, val | PIPECONF_ENABLE);
2170 POSTING_READ(reg);
2171}
2172
2173/**
2174 * intel_disable_pipe - disable a pipe, asserting requirements
2175 * @crtc: crtc whose pipes is to be disabled
2176 *
2177 * Disable the pipe of @crtc, making sure that various hardware
2178 * specific requirements are met, if applicable, e.g. plane
2179 * disabled, panel fitter off, etc.
2180 *
2181 * Will wait until the pipe has shut down before returning.
2182 */
2183static void intel_disable_pipe(struct intel_crtc *crtc)
2184{
2185 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2186 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2187 enum pipe pipe = crtc->pipe;
2188 int reg;
2189 u32 val;
2190
2191 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2192
2193 /*
2194 * Make sure planes won't keep trying to pump pixels to us,
2195 * or we might hang the display.
2196 */
2197 assert_planes_disabled(dev_priv, pipe);
2198 assert_cursor_disabled(dev_priv, pipe);
2199 assert_sprites_disabled(dev_priv, pipe);
2200
2201 reg = PIPECONF(cpu_transcoder);
2202 val = I915_READ(reg);
2203 if ((val & PIPECONF_ENABLE) == 0)
2204 return;
2205
2206 /*
2207 * Double wide has implications for planes
2208 * so best keep it disabled when not needed.
2209 */
2210 if (crtc->config->double_wide)
2211 val &= ~PIPECONF_DOUBLE_WIDE;
2212
2213 /* Don't disable pipe or pipe PLLs if needed */
2214 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2215 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2216 val &= ~PIPECONF_ENABLE;
2217
2218 I915_WRITE(reg, val);
2219 if ((val & PIPECONF_ENABLE) == 0)
2220 intel_wait_for_pipe_off(crtc);
2221}
2222
2223static bool need_vtd_wa(struct drm_device *dev)
2224{
2225#ifdef CONFIG_INTEL_IOMMU
2226 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2227 return true;
2228#endif
2229 return false;
2230}
2231
2232unsigned int
2233intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2234 uint64_t fb_format_modifier)
2235{
2236 unsigned int tile_height;
2237 uint32_t pixel_bytes;
2238
2239 switch (fb_format_modifier) {
2240 case DRM_FORMAT_MOD_NONE:
2241 tile_height = 1;
2242 break;
2243 case I915_FORMAT_MOD_X_TILED:
2244 tile_height = IS_GEN2(dev) ? 16 : 8;
2245 break;
2246 case I915_FORMAT_MOD_Y_TILED:
2247 tile_height = 32;
2248 break;
2249 case I915_FORMAT_MOD_Yf_TILED:
2250 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2251 switch (pixel_bytes) {
2252 default:
2253 case 1:
2254 tile_height = 64;
2255 break;
2256 case 2:
2257 case 4:
2258 tile_height = 32;
2259 break;
2260 case 8:
2261 tile_height = 16;
2262 break;
2263 case 16:
2264 WARN_ONCE(1,
2265 "128-bit pixels are not supported for display!");
2266 tile_height = 16;
2267 break;
2268 }
2269 break;
2270 default:
2271 MISSING_CASE(fb_format_modifier);
2272 tile_height = 1;
2273 break;
2274 }
2275
2276 return tile_height;
2277}
2278
2279unsigned int
2280intel_fb_align_height(struct drm_device *dev, unsigned int height,
2281 uint32_t pixel_format, uint64_t fb_format_modifier)
2282{
2283 return ALIGN(height, intel_tile_height(dev, pixel_format,
2284 fb_format_modifier));
2285}
2286
2287static int
2288intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2289 const struct drm_plane_state *plane_state)
2290{
2291 struct intel_rotation_info *info = &view->rotation_info;
2292 unsigned int tile_height, tile_pitch;
2293
2294 *view = i915_ggtt_view_normal;
2295
2296 if (!plane_state)
2297 return 0;
2298
2299 if (!intel_rotation_90_or_270(plane_state->rotation))
2300 return 0;
2301
2302 *view = i915_ggtt_view_rotated;
2303
2304 info->height = fb->height;
2305 info->pixel_format = fb->pixel_format;
2306 info->pitch = fb->pitches[0];
2307 info->fb_modifier = fb->modifier[0];
2308
2309 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2310 fb->modifier[0]);
2311 tile_pitch = PAGE_SIZE / tile_height;
2312 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2313 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2314 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2315
2316 return 0;
2317}
2318
2319static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2320{
2321 if (INTEL_INFO(dev_priv)->gen >= 9)
2322 return 256 * 1024;
2323 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2324 IS_VALLEYVIEW(dev_priv))
2325 return 128 * 1024;
2326 else if (INTEL_INFO(dev_priv)->gen >= 4)
2327 return 4 * 1024;
2328 else
2329 return 0;
2330}
2331
2332int
2333intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2334 struct drm_framebuffer *fb,
2335 const struct drm_plane_state *plane_state,
2336 struct intel_engine_cs *pipelined,
2337 struct drm_i915_gem_request **pipelined_request)
2338{
2339 struct drm_device *dev = fb->dev;
2340 struct drm_i915_private *dev_priv = dev->dev_private;
2341 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2342 struct i915_ggtt_view view;
2343 u32 alignment;
2344 int ret;
2345
2346 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2347
2348 switch (fb->modifier[0]) {
2349 case DRM_FORMAT_MOD_NONE:
2350 alignment = intel_linear_alignment(dev_priv);
2351 break;
2352 case I915_FORMAT_MOD_X_TILED:
2353 if (INTEL_INFO(dev)->gen >= 9)
2354 alignment = 256 * 1024;
2355 else {
2356 /* pin() will align the object as required by fence */
2357 alignment = 0;
2358 }
2359 break;
2360 case I915_FORMAT_MOD_Y_TILED:
2361 case I915_FORMAT_MOD_Yf_TILED:
2362 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2363 "Y tiling bo slipped through, driver bug!\n"))
2364 return -EINVAL;
2365 alignment = 1 * 1024 * 1024;
2366 break;
2367 default:
2368 MISSING_CASE(fb->modifier[0]);
2369 return -EINVAL;
2370 }
2371
2372 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2373 if (ret)
2374 return ret;
2375
2376 /* Note that the w/a also requires 64 PTE of padding following the
2377 * bo. We currently fill all unused PTE with the shadow page and so
2378 * we should always have valid PTE following the scanout preventing
2379 * the VT-d warning.
2380 */
2381 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2382 alignment = 256 * 1024;
2383
2384 /*
2385 * Global gtt pte registers are special registers which actually forward
2386 * writes to a chunk of system memory. Which means that there is no risk
2387 * that the register values disappear as soon as we call
2388 * intel_runtime_pm_put(), so it is correct to wrap only the
2389 * pin/unpin/fence and not more.
2390 */
2391 intel_runtime_pm_get(dev_priv);
2392
2393 dev_priv->mm.interruptible = false;
2394 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2395 pipelined_request, &view);
2396 if (ret)
2397 goto err_interruptible;
2398
2399 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2400 * fence, whereas 965+ only requires a fence if using
2401 * framebuffer compression. For simplicity, we always install
2402 * a fence as the cost is not that onerous.
2403 */
2404 ret = i915_gem_object_get_fence(obj);
2405 if (ret == -EDEADLK) {
2406 /*
2407 * -EDEADLK means there are no free fences
2408 * no pending flips.
2409 *
2410 * This is propagated to atomic, but it uses
2411 * -EDEADLK to force a locking recovery, so
2412 * change the returned error to -EBUSY.
2413 */
2414 ret = -EBUSY;
2415 goto err_unpin;
2416 } else if (ret)
2417 goto err_unpin;
2418
2419 i915_gem_object_pin_fence(obj);
2420
2421 dev_priv->mm.interruptible = true;
2422 intel_runtime_pm_put(dev_priv);
2423 return 0;
2424
2425err_unpin:
2426 i915_gem_object_unpin_from_display_plane(obj, &view);
2427err_interruptible:
2428 dev_priv->mm.interruptible = true;
2429 intel_runtime_pm_put(dev_priv);
2430 return ret;
2431}
2432
2433static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2434 const struct drm_plane_state *plane_state)
2435{
2436 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2437 struct i915_ggtt_view view;
2438 int ret;
2439
2440 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2441
2442 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2443 WARN_ONCE(ret, "Couldn't get view from plane state!");
2444
2445 i915_gem_object_unpin_fence(obj);
2446 i915_gem_object_unpin_from_display_plane(obj, &view);
2447}
2448
2449/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2450 * is assumed to be a power-of-two. */
2451unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2452 int *x, int *y,
2453 unsigned int tiling_mode,
2454 unsigned int cpp,
2455 unsigned int pitch)
2456{
2457 if (tiling_mode != I915_TILING_NONE) {
2458 unsigned int tile_rows, tiles;
2459
2460 tile_rows = *y / 8;
2461 *y %= 8;
2462
2463 tiles = *x / (512/cpp);
2464 *x %= 512/cpp;
2465
2466 return tile_rows * pitch * 8 + tiles * 4096;
2467 } else {
2468 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2469 unsigned int offset;
2470
2471 offset = *y * pitch + *x * cpp;
2472 *y = (offset & alignment) / pitch;
2473 *x = ((offset & alignment) - *y * pitch) / cpp;
2474 return offset & ~alignment;
2475 }
2476}
2477
2478static int i9xx_format_to_fourcc(int format)
2479{
2480 switch (format) {
2481 case DISPPLANE_8BPP:
2482 return DRM_FORMAT_C8;
2483 case DISPPLANE_BGRX555:
2484 return DRM_FORMAT_XRGB1555;
2485 case DISPPLANE_BGRX565:
2486 return DRM_FORMAT_RGB565;
2487 default:
2488 case DISPPLANE_BGRX888:
2489 return DRM_FORMAT_XRGB8888;
2490 case DISPPLANE_RGBX888:
2491 return DRM_FORMAT_XBGR8888;
2492 case DISPPLANE_BGRX101010:
2493 return DRM_FORMAT_XRGB2101010;
2494 case DISPPLANE_RGBX101010:
2495 return DRM_FORMAT_XBGR2101010;
2496 }
2497}
2498
2499static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2500{
2501 switch (format) {
2502 case PLANE_CTL_FORMAT_RGB_565:
2503 return DRM_FORMAT_RGB565;
2504 default:
2505 case PLANE_CTL_FORMAT_XRGB_8888:
2506 if (rgb_order) {
2507 if (alpha)
2508 return DRM_FORMAT_ABGR8888;
2509 else
2510 return DRM_FORMAT_XBGR8888;
2511 } else {
2512 if (alpha)
2513 return DRM_FORMAT_ARGB8888;
2514 else
2515 return DRM_FORMAT_XRGB8888;
2516 }
2517 case PLANE_CTL_FORMAT_XRGB_2101010:
2518 if (rgb_order)
2519 return DRM_FORMAT_XBGR2101010;
2520 else
2521 return DRM_FORMAT_XRGB2101010;
2522 }
2523}
2524
2525static bool
2526intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2527 struct intel_initial_plane_config *plane_config)
2528{
2529 struct drm_device *dev = crtc->base.dev;
2530 struct drm_i915_gem_object *obj = NULL;
2531 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2532 struct drm_framebuffer *fb = &plane_config->fb->base;
2533 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2534 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2535 PAGE_SIZE);
2536
2537 size_aligned -= base_aligned;
2538
2539 if (plane_config->size == 0)
2540 return false;
2541
2542 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2543 base_aligned,
2544 base_aligned,
2545 size_aligned);
2546 if (!obj)
2547 return false;
2548
2549 obj->tiling_mode = plane_config->tiling;
2550 if (obj->tiling_mode == I915_TILING_X)
2551 obj->stride = fb->pitches[0];
2552
2553 mode_cmd.pixel_format = fb->pixel_format;
2554 mode_cmd.width = fb->width;
2555 mode_cmd.height = fb->height;
2556 mode_cmd.pitches[0] = fb->pitches[0];
2557 mode_cmd.modifier[0] = fb->modifier[0];
2558 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2559
2560 mutex_lock(&dev->struct_mutex);
2561 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2562 &mode_cmd, obj)) {
2563 DRM_DEBUG_KMS("intel fb init failed\n");
2564 goto out_unref_obj;
2565 }
2566 mutex_unlock(&dev->struct_mutex);
2567
2568 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2569 return true;
2570
2571out_unref_obj:
2572 drm_gem_object_unreference(&obj->base);
2573 mutex_unlock(&dev->struct_mutex);
2574 return false;
2575}
2576
2577/* Update plane->state->fb to match plane->fb after driver-internal updates */
2578static void
2579update_state_fb(struct drm_plane *plane)
2580{
2581 if (plane->fb == plane->state->fb)
2582 return;
2583
2584 if (plane->state->fb)
2585 drm_framebuffer_unreference(plane->state->fb);
2586 plane->state->fb = plane->fb;
2587 if (plane->state->fb)
2588 drm_framebuffer_reference(plane->state->fb);
2589}
2590
2591static void
2592intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2593 struct intel_initial_plane_config *plane_config)
2594{
2595 struct drm_device *dev = intel_crtc->base.dev;
2596 struct drm_i915_private *dev_priv = dev->dev_private;
2597 struct drm_crtc *c;
2598 struct intel_crtc *i;
2599 struct drm_i915_gem_object *obj;
2600 struct drm_plane *primary = intel_crtc->base.primary;
2601 struct drm_plane_state *plane_state = primary->state;
2602 struct drm_framebuffer *fb;
2603
2604 if (!plane_config->fb)
2605 return;
2606
2607 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2608 fb = &plane_config->fb->base;
2609 goto valid_fb;
2610 }
2611
2612 kfree(plane_config->fb);
2613
2614 /*
2615 * Failed to alloc the obj, check to see if we should share
2616 * an fb with another CRTC instead
2617 */
2618 for_each_crtc(dev, c) {
2619 i = to_intel_crtc(c);
2620
2621 if (c == &intel_crtc->base)
2622 continue;
2623
2624 if (!i->active)
2625 continue;
2626
2627 fb = c->primary->fb;
2628 if (!fb)
2629 continue;
2630
2631 obj = intel_fb_obj(fb);
2632 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2633 drm_framebuffer_reference(fb);
2634 goto valid_fb;
2635 }
2636 }
2637
2638 return;
2639
2640valid_fb:
2641 plane_state->src_x = plane_state->src_y = 0;
2642 plane_state->src_w = fb->width << 16;
2643 plane_state->src_h = fb->height << 16;
2644
2645 plane_state->crtc_x = plane_state->src_y = 0;
2646 plane_state->crtc_w = fb->width;
2647 plane_state->crtc_h = fb->height;
2648
2649 obj = intel_fb_obj(fb);
2650 if (obj->tiling_mode != I915_TILING_NONE)
2651 dev_priv->preserve_bios_swizzle = true;
2652
2653 drm_framebuffer_reference(fb);
2654 primary->fb = primary->state->fb = fb;
2655 primary->crtc = primary->state->crtc = &intel_crtc->base;
2656 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2657 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2658}
2659
2660static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2661 struct drm_framebuffer *fb,
2662 int x, int y)
2663{
2664 struct drm_device *dev = crtc->dev;
2665 struct drm_i915_private *dev_priv = dev->dev_private;
2666 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2667 struct drm_plane *primary = crtc->primary;
2668 bool visible = to_intel_plane_state(primary->state)->visible;
2669 struct drm_i915_gem_object *obj;
2670 int plane = intel_crtc->plane;
2671 unsigned long linear_offset;
2672 u32 dspcntr;
2673 u32 reg = DSPCNTR(plane);
2674 int pixel_size;
2675
2676 if (!visible || !fb) {
2677 I915_WRITE(reg, 0);
2678 if (INTEL_INFO(dev)->gen >= 4)
2679 I915_WRITE(DSPSURF(plane), 0);
2680 else
2681 I915_WRITE(DSPADDR(plane), 0);
2682 POSTING_READ(reg);
2683 return;
2684 }
2685
2686 obj = intel_fb_obj(fb);
2687 if (WARN_ON(obj == NULL))
2688 return;
2689
2690 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2691
2692 dspcntr = DISPPLANE_GAMMA_ENABLE;
2693
2694 dspcntr |= DISPLAY_PLANE_ENABLE;
2695
2696 if (INTEL_INFO(dev)->gen < 4) {
2697 if (intel_crtc->pipe == PIPE_B)
2698 dspcntr |= DISPPLANE_SEL_PIPE_B;
2699
2700 /* pipesrc and dspsize control the size that is scaled from,
2701 * which should always be the user's requested size.
2702 */
2703 I915_WRITE(DSPSIZE(plane),
2704 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2705 (intel_crtc->config->pipe_src_w - 1));
2706 I915_WRITE(DSPPOS(plane), 0);
2707 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2708 I915_WRITE(PRIMSIZE(plane),
2709 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2710 (intel_crtc->config->pipe_src_w - 1));
2711 I915_WRITE(PRIMPOS(plane), 0);
2712 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2713 }
2714
2715 switch (fb->pixel_format) {
2716 case DRM_FORMAT_C8:
2717 dspcntr |= DISPPLANE_8BPP;
2718 break;
2719 case DRM_FORMAT_XRGB1555:
2720 dspcntr |= DISPPLANE_BGRX555;
2721 break;
2722 case DRM_FORMAT_RGB565:
2723 dspcntr |= DISPPLANE_BGRX565;
2724 break;
2725 case DRM_FORMAT_XRGB8888:
2726 dspcntr |= DISPPLANE_BGRX888;
2727 break;
2728 case DRM_FORMAT_XBGR8888:
2729 dspcntr |= DISPPLANE_RGBX888;
2730 break;
2731 case DRM_FORMAT_XRGB2101010:
2732 dspcntr |= DISPPLANE_BGRX101010;
2733 break;
2734 case DRM_FORMAT_XBGR2101010:
2735 dspcntr |= DISPPLANE_RGBX101010;
2736 break;
2737 default:
2738 BUG();
2739 }
2740
2741 if (INTEL_INFO(dev)->gen >= 4 &&
2742 obj->tiling_mode != I915_TILING_NONE)
2743 dspcntr |= DISPPLANE_TILED;
2744
2745 if (IS_G4X(dev))
2746 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2747
2748 linear_offset = y * fb->pitches[0] + x * pixel_size;
2749
2750 if (INTEL_INFO(dev)->gen >= 4) {
2751 intel_crtc->dspaddr_offset =
2752 intel_gen4_compute_page_offset(dev_priv,
2753 &x, &y, obj->tiling_mode,
2754 pixel_size,
2755 fb->pitches[0]);
2756 linear_offset -= intel_crtc->dspaddr_offset;
2757 } else {
2758 intel_crtc->dspaddr_offset = linear_offset;
2759 }
2760
2761 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2762 dspcntr |= DISPPLANE_ROTATE_180;
2763
2764 x += (intel_crtc->config->pipe_src_w - 1);
2765 y += (intel_crtc->config->pipe_src_h - 1);
2766
2767 /* Finding the last pixel of the last line of the display
2768 data and adding to linear_offset*/
2769 linear_offset +=
2770 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2771 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2772 }
2773
2774 I915_WRITE(reg, dspcntr);
2775
2776 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2777 if (INTEL_INFO(dev)->gen >= 4) {
2778 I915_WRITE(DSPSURF(plane),
2779 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2780 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2781 I915_WRITE(DSPLINOFF(plane), linear_offset);
2782 } else
2783 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2784 POSTING_READ(reg);
2785}
2786
2787static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2788 struct drm_framebuffer *fb,
2789 int x, int y)
2790{
2791 struct drm_device *dev = crtc->dev;
2792 struct drm_i915_private *dev_priv = dev->dev_private;
2793 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2794 struct drm_plane *primary = crtc->primary;
2795 bool visible = to_intel_plane_state(primary->state)->visible;
2796 struct drm_i915_gem_object *obj;
2797 int plane = intel_crtc->plane;
2798 unsigned long linear_offset;
2799 u32 dspcntr;
2800 u32 reg = DSPCNTR(plane);
2801 int pixel_size;
2802
2803 if (!visible || !fb) {
2804 I915_WRITE(reg, 0);
2805 I915_WRITE(DSPSURF(plane), 0);
2806 POSTING_READ(reg);
2807 return;
2808 }
2809
2810 obj = intel_fb_obj(fb);
2811 if (WARN_ON(obj == NULL))
2812 return;
2813
2814 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2815
2816 dspcntr = DISPPLANE_GAMMA_ENABLE;
2817
2818 dspcntr |= DISPLAY_PLANE_ENABLE;
2819
2820 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2821 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2822
2823 switch (fb->pixel_format) {
2824 case DRM_FORMAT_C8:
2825 dspcntr |= DISPPLANE_8BPP;
2826 break;
2827 case DRM_FORMAT_RGB565:
2828 dspcntr |= DISPPLANE_BGRX565;
2829 break;
2830 case DRM_FORMAT_XRGB8888:
2831 dspcntr |= DISPPLANE_BGRX888;
2832 break;
2833 case DRM_FORMAT_XBGR8888:
2834 dspcntr |= DISPPLANE_RGBX888;
2835 break;
2836 case DRM_FORMAT_XRGB2101010:
2837 dspcntr |= DISPPLANE_BGRX101010;
2838 break;
2839 case DRM_FORMAT_XBGR2101010:
2840 dspcntr |= DISPPLANE_RGBX101010;
2841 break;
2842 default:
2843 BUG();
2844 }
2845
2846 if (obj->tiling_mode != I915_TILING_NONE)
2847 dspcntr |= DISPPLANE_TILED;
2848
2849 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2850 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2851
2852 linear_offset = y * fb->pitches[0] + x * pixel_size;
2853 intel_crtc->dspaddr_offset =
2854 intel_gen4_compute_page_offset(dev_priv,
2855 &x, &y, obj->tiling_mode,
2856 pixel_size,
2857 fb->pitches[0]);
2858 linear_offset -= intel_crtc->dspaddr_offset;
2859 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2860 dspcntr |= DISPPLANE_ROTATE_180;
2861
2862 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2863 x += (intel_crtc->config->pipe_src_w - 1);
2864 y += (intel_crtc->config->pipe_src_h - 1);
2865
2866 /* Finding the last pixel of the last line of the display
2867 data and adding to linear_offset*/
2868 linear_offset +=
2869 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2870 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2871 }
2872 }
2873
2874 I915_WRITE(reg, dspcntr);
2875
2876 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2877 I915_WRITE(DSPSURF(plane),
2878 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2879 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2880 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2881 } else {
2882 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2883 I915_WRITE(DSPLINOFF(plane), linear_offset);
2884 }
2885 POSTING_READ(reg);
2886}
2887
2888u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2889 uint32_t pixel_format)
2890{
2891 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2892
2893 /*
2894 * The stride is either expressed as a multiple of 64 bytes
2895 * chunks for linear buffers or in number of tiles for tiled
2896 * buffers.
2897 */
2898 switch (fb_modifier) {
2899 case DRM_FORMAT_MOD_NONE:
2900 return 64;
2901 case I915_FORMAT_MOD_X_TILED:
2902 if (INTEL_INFO(dev)->gen == 2)
2903 return 128;
2904 return 512;
2905 case I915_FORMAT_MOD_Y_TILED:
2906 /* No need to check for old gens and Y tiling since this is
2907 * about the display engine and those will be blocked before
2908 * we get here.
2909 */
2910 return 128;
2911 case I915_FORMAT_MOD_Yf_TILED:
2912 if (bits_per_pixel == 8)
2913 return 64;
2914 else
2915 return 128;
2916 default:
2917 MISSING_CASE(fb_modifier);
2918 return 64;
2919 }
2920}
2921
2922unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2923 struct drm_i915_gem_object *obj)
2924{
2925 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2926
2927 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2928 view = &i915_ggtt_view_rotated;
2929
2930 return i915_gem_obj_ggtt_offset_view(obj, view);
2931}
2932
2933static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2934{
2935 struct drm_device *dev = intel_crtc->base.dev;
2936 struct drm_i915_private *dev_priv = dev->dev_private;
2937
2938 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2939 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2940 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2941 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2942 intel_crtc->base.base.id, intel_crtc->pipe, id);
2943}
2944
2945/*
2946 * This function detaches (aka. unbinds) unused scalers in hardware
2947 */
2948static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2949{
2950 struct intel_crtc_scaler_state *scaler_state;
2951 int i;
2952
2953 scaler_state = &intel_crtc->config->scaler_state;
2954
2955 /* loop through and disable scalers that aren't in use */
2956 for (i = 0; i < intel_crtc->num_scalers; i++) {
2957 if (!scaler_state->scalers[i].in_use)
2958 skl_detach_scaler(intel_crtc, i);
2959 }
2960}
2961
2962u32 skl_plane_ctl_format(uint32_t pixel_format)
2963{
2964 switch (pixel_format) {
2965 case DRM_FORMAT_C8:
2966 return PLANE_CTL_FORMAT_INDEXED;
2967 case DRM_FORMAT_RGB565:
2968 return PLANE_CTL_FORMAT_RGB_565;
2969 case DRM_FORMAT_XBGR8888:
2970 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2971 case DRM_FORMAT_XRGB8888:
2972 return PLANE_CTL_FORMAT_XRGB_8888;
2973 /*
2974 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2975 * to be already pre-multiplied. We need to add a knob (or a different
2976 * DRM_FORMAT) for user-space to configure that.
2977 */
2978 case DRM_FORMAT_ABGR8888:
2979 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2980 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2981 case DRM_FORMAT_ARGB8888:
2982 return PLANE_CTL_FORMAT_XRGB_8888 |
2983 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2984 case DRM_FORMAT_XRGB2101010:
2985 return PLANE_CTL_FORMAT_XRGB_2101010;
2986 case DRM_FORMAT_XBGR2101010:
2987 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2988 case DRM_FORMAT_YUYV:
2989 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2990 case DRM_FORMAT_YVYU:
2991 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2992 case DRM_FORMAT_UYVY:
2993 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2994 case DRM_FORMAT_VYUY:
2995 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2996 default:
2997 MISSING_CASE(pixel_format);
2998 }
2999
3000 return 0;
3001}
3002
3003u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3004{
3005 switch (fb_modifier) {
3006 case DRM_FORMAT_MOD_NONE:
3007 break;
3008 case I915_FORMAT_MOD_X_TILED:
3009 return PLANE_CTL_TILED_X;
3010 case I915_FORMAT_MOD_Y_TILED:
3011 return PLANE_CTL_TILED_Y;
3012 case I915_FORMAT_MOD_Yf_TILED:
3013 return PLANE_CTL_TILED_YF;
3014 default:
3015 MISSING_CASE(fb_modifier);
3016 }
3017
3018 return 0;
3019}
3020
3021u32 skl_plane_ctl_rotation(unsigned int rotation)
3022{
3023 switch (rotation) {
3024 case BIT(DRM_ROTATE_0):
3025 break;
3026 /*
3027 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3028 * while i915 HW rotation is clockwise, thats why this swapping.
3029 */
3030 case BIT(DRM_ROTATE_90):
3031 return PLANE_CTL_ROTATE_270;
3032 case BIT(DRM_ROTATE_180):
3033 return PLANE_CTL_ROTATE_180;
3034 case BIT(DRM_ROTATE_270):
3035 return PLANE_CTL_ROTATE_90;
3036 default:
3037 MISSING_CASE(rotation);
3038 }
3039
3040 return 0;
3041}
3042
3043static void skylake_update_primary_plane(struct drm_crtc *crtc,
3044 struct drm_framebuffer *fb,
3045 int x, int y)
3046{
3047 struct drm_device *dev = crtc->dev;
3048 struct drm_i915_private *dev_priv = dev->dev_private;
3049 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3050 struct drm_plane *plane = crtc->primary;
3051 bool visible = to_intel_plane_state(plane->state)->visible;
3052 struct drm_i915_gem_object *obj;
3053 int pipe = intel_crtc->pipe;
3054 u32 plane_ctl, stride_div, stride;
3055 u32 tile_height, plane_offset, plane_size;
3056 unsigned int rotation;
3057 int x_offset, y_offset;
3058 unsigned long surf_addr;
3059 struct intel_crtc_state *crtc_state = intel_crtc->config;
3060 struct intel_plane_state *plane_state;
3061 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3062 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3063 int scaler_id = -1;
3064
3065 plane_state = to_intel_plane_state(plane->state);
3066
3067 if (!visible || !fb) {
3068 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3069 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3070 POSTING_READ(PLANE_CTL(pipe, 0));
3071 return;
3072 }
3073
3074 plane_ctl = PLANE_CTL_ENABLE |
3075 PLANE_CTL_PIPE_GAMMA_ENABLE |
3076 PLANE_CTL_PIPE_CSC_ENABLE;
3077
3078 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3079 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3080 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3081
3082 rotation = plane->state->rotation;
3083 plane_ctl |= skl_plane_ctl_rotation(rotation);
3084
3085 obj = intel_fb_obj(fb);
3086 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3087 fb->pixel_format);
3088 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3089
3090 /*
3091 * FIXME: intel_plane_state->src, dst aren't set when transitional
3092 * update_plane helpers are called from legacy paths.
3093 * Once full atomic crtc is available, below check can be avoided.
3094 */
3095 if (drm_rect_width(&plane_state->src)) {
3096 scaler_id = plane_state->scaler_id;
3097 src_x = plane_state->src.x1 >> 16;
3098 src_y = plane_state->src.y1 >> 16;
3099 src_w = drm_rect_width(&plane_state->src) >> 16;
3100 src_h = drm_rect_height(&plane_state->src) >> 16;
3101 dst_x = plane_state->dst.x1;
3102 dst_y = plane_state->dst.y1;
3103 dst_w = drm_rect_width(&plane_state->dst);
3104 dst_h = drm_rect_height(&plane_state->dst);
3105
3106 WARN_ON(x != src_x || y != src_y);
3107 } else {
3108 src_w = intel_crtc->config->pipe_src_w;
3109 src_h = intel_crtc->config->pipe_src_h;
3110 }
3111
3112 if (intel_rotation_90_or_270(rotation)) {
3113 /* stride = Surface height in tiles */
3114 tile_height = intel_tile_height(dev, fb->pixel_format,
3115 fb->modifier[0]);
3116 stride = DIV_ROUND_UP(fb->height, tile_height);
3117 x_offset = stride * tile_height - y - src_h;
3118 y_offset = x;
3119 plane_size = (src_w - 1) << 16 | (src_h - 1);
3120 } else {
3121 stride = fb->pitches[0] / stride_div;
3122 x_offset = x;
3123 y_offset = y;
3124 plane_size = (src_h - 1) << 16 | (src_w - 1);
3125 }
3126 plane_offset = y_offset << 16 | x_offset;
3127
3128 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3129 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3130 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3131 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3132
3133 if (scaler_id >= 0) {
3134 uint32_t ps_ctrl = 0;
3135
3136 WARN_ON(!dst_w || !dst_h);
3137 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3138 crtc_state->scaler_state.scalers[scaler_id].mode;
3139 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3140 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3141 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3142 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3143 I915_WRITE(PLANE_POS(pipe, 0), 0);
3144 } else {
3145 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3146 }
3147
3148 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3149
3150 POSTING_READ(PLANE_SURF(pipe, 0));
3151}
3152
3153/* Assume fb object is pinned & idle & fenced and just update base pointers */
3154static int
3155intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3156 int x, int y, enum mode_set_atomic state)
3157{
3158 struct drm_device *dev = crtc->dev;
3159 struct drm_i915_private *dev_priv = dev->dev_private;
3160
3161 if (dev_priv->fbc.disable_fbc)
3162 dev_priv->fbc.disable_fbc(dev_priv);
3163
3164 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3165
3166 return 0;
3167}
3168
3169static void intel_complete_page_flips(struct drm_device *dev)
3170{
3171 struct drm_crtc *crtc;
3172
3173 for_each_crtc(dev, crtc) {
3174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3175 enum plane plane = intel_crtc->plane;
3176
3177 intel_prepare_page_flip(dev, plane);
3178 intel_finish_page_flip_plane(dev, plane);
3179 }
3180}
3181
3182static void intel_update_primary_planes(struct drm_device *dev)
3183{
3184 struct drm_i915_private *dev_priv = dev->dev_private;
3185 struct drm_crtc *crtc;
3186
3187 for_each_crtc(dev, crtc) {
3188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3189
3190 drm_modeset_lock(&crtc->mutex, NULL);
3191 /*
3192 * FIXME: Once we have proper support for primary planes (and
3193 * disabling them without disabling the entire crtc) allow again
3194 * a NULL crtc->primary->fb.
3195 */
3196 if (intel_crtc->active && crtc->primary->fb)
3197 dev_priv->display.update_primary_plane(crtc,
3198 crtc->primary->fb,
3199 crtc->x,
3200 crtc->y);
3201 drm_modeset_unlock(&crtc->mutex);
3202 }
3203}
3204
3205void intel_prepare_reset(struct drm_device *dev)
3206{
3207 /* no reset support for gen2 */
3208 if (IS_GEN2(dev))
3209 return;
3210
3211 /* reset doesn't touch the display */
3212 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3213 return;
3214
3215 drm_modeset_lock_all(dev);
3216 /*
3217 * Disabling the crtcs gracefully seems nicer. Also the
3218 * g33 docs say we should at least disable all the planes.
3219 */
3220 intel_display_suspend(dev);
3221}
3222
3223void intel_finish_reset(struct drm_device *dev)
3224{
3225 struct drm_i915_private *dev_priv = to_i915(dev);
3226
3227 /*
3228 * Flips in the rings will be nuked by the reset,
3229 * so complete all pending flips so that user space
3230 * will get its events and not get stuck.
3231 */
3232 intel_complete_page_flips(dev);
3233
3234 /* no reset support for gen2 */
3235 if (IS_GEN2(dev))
3236 return;
3237
3238 /* reset doesn't touch the display */
3239 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3240 /*
3241 * Flips in the rings have been nuked by the reset,
3242 * so update the base address of all primary
3243 * planes to the the last fb to make sure we're
3244 * showing the correct fb after a reset.
3245 */
3246 intel_update_primary_planes(dev);
3247 return;
3248 }
3249
3250 /*
3251 * The display has been reset as well,
3252 * so need a full re-initialization.
3253 */
3254 intel_runtime_pm_disable_interrupts(dev_priv);
3255 intel_runtime_pm_enable_interrupts(dev_priv);
3256
3257 intel_modeset_init_hw(dev);
3258
3259 spin_lock_irq(&dev_priv->irq_lock);
3260 if (dev_priv->display.hpd_irq_setup)
3261 dev_priv->display.hpd_irq_setup(dev);
3262 spin_unlock_irq(&dev_priv->irq_lock);
3263
3264 intel_display_resume(dev);
3265
3266 intel_hpd_init(dev_priv);
3267
3268 drm_modeset_unlock_all(dev);
3269}
3270
3271static void
3272intel_finish_fb(struct drm_framebuffer *old_fb)
3273{
3274 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3275 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3276 bool was_interruptible = dev_priv->mm.interruptible;
3277 int ret;
3278
3279 /* Big Hammer, we also need to ensure that any pending
3280 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3281 * current scanout is retired before unpinning the old
3282 * framebuffer. Note that we rely on userspace rendering
3283 * into the buffer attached to the pipe they are waiting
3284 * on. If not, userspace generates a GPU hang with IPEHR
3285 * point to the MI_WAIT_FOR_EVENT.
3286 *
3287 * This should only fail upon a hung GPU, in which case we
3288 * can safely continue.
3289 */
3290 dev_priv->mm.interruptible = false;
3291 ret = i915_gem_object_wait_rendering(obj, true);
3292 dev_priv->mm.interruptible = was_interruptible;
3293
3294 WARN_ON(ret);
3295}
3296
3297static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3298{
3299 struct drm_device *dev = crtc->dev;
3300 struct drm_i915_private *dev_priv = dev->dev_private;
3301 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3302 bool pending;
3303
3304 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3305 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3306 return false;
3307
3308 spin_lock_irq(&dev->event_lock);
3309 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3310 spin_unlock_irq(&dev->event_lock);
3311
3312 return pending;
3313}
3314
3315static void intel_update_pipe_size(struct intel_crtc *crtc)
3316{
3317 struct drm_device *dev = crtc->base.dev;
3318 struct drm_i915_private *dev_priv = dev->dev_private;
3319 const struct drm_display_mode *adjusted_mode;
3320
3321 if (!i915.fastboot)
3322 return;
3323
3324 /*
3325 * Update pipe size and adjust fitter if needed: the reason for this is
3326 * that in compute_mode_changes we check the native mode (not the pfit
3327 * mode) to see if we can flip rather than do a full mode set. In the
3328 * fastboot case, we'll flip, but if we don't update the pipesrc and
3329 * pfit state, we'll end up with a big fb scanned out into the wrong
3330 * sized surface.
3331 *
3332 * To fix this properly, we need to hoist the checks up into
3333 * compute_mode_changes (or above), check the actual pfit state and
3334 * whether the platform allows pfit disable with pipe active, and only
3335 * then update the pipesrc and pfit state, even on the flip path.
3336 */
3337
3338 adjusted_mode = &crtc->config->base.adjusted_mode;
3339
3340 I915_WRITE(PIPESRC(crtc->pipe),
3341 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3342 (adjusted_mode->crtc_vdisplay - 1));
3343 if (!crtc->config->pch_pfit.enabled &&
3344 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3345 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3346 I915_WRITE(PF_CTL(crtc->pipe), 0);
3347 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3348 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3349 }
3350 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3351 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3352}
3353
3354static void intel_fdi_normal_train(struct drm_crtc *crtc)
3355{
3356 struct drm_device *dev = crtc->dev;
3357 struct drm_i915_private *dev_priv = dev->dev_private;
3358 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3359 int pipe = intel_crtc->pipe;
3360 u32 reg, temp;
3361
3362 /* enable normal train */
3363 reg = FDI_TX_CTL(pipe);
3364 temp = I915_READ(reg);
3365 if (IS_IVYBRIDGE(dev)) {
3366 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3367 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3368 } else {
3369 temp &= ~FDI_LINK_TRAIN_NONE;
3370 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3371 }
3372 I915_WRITE(reg, temp);
3373
3374 reg = FDI_RX_CTL(pipe);
3375 temp = I915_READ(reg);
3376 if (HAS_PCH_CPT(dev)) {
3377 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3378 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3379 } else {
3380 temp &= ~FDI_LINK_TRAIN_NONE;
3381 temp |= FDI_LINK_TRAIN_NONE;
3382 }
3383 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3384
3385 /* wait one idle pattern time */
3386 POSTING_READ(reg);
3387 udelay(1000);
3388
3389 /* IVB wants error correction enabled */
3390 if (IS_IVYBRIDGE(dev))
3391 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3392 FDI_FE_ERRC_ENABLE);
3393}
3394
3395/* The FDI link training functions for ILK/Ibexpeak. */
3396static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3397{
3398 struct drm_device *dev = crtc->dev;
3399 struct drm_i915_private *dev_priv = dev->dev_private;
3400 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3401 int pipe = intel_crtc->pipe;
3402 u32 reg, temp, tries;
3403
3404 /* FDI needs bits from pipe first */
3405 assert_pipe_enabled(dev_priv, pipe);
3406
3407 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3408 for train result */
3409 reg = FDI_RX_IMR(pipe);
3410 temp = I915_READ(reg);
3411 temp &= ~FDI_RX_SYMBOL_LOCK;
3412 temp &= ~FDI_RX_BIT_LOCK;
3413 I915_WRITE(reg, temp);
3414 I915_READ(reg);
3415 udelay(150);
3416
3417 /* enable CPU FDI TX and PCH FDI RX */
3418 reg = FDI_TX_CTL(pipe);
3419 temp = I915_READ(reg);
3420 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3421 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3422 temp &= ~FDI_LINK_TRAIN_NONE;
3423 temp |= FDI_LINK_TRAIN_PATTERN_1;
3424 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3425
3426 reg = FDI_RX_CTL(pipe);
3427 temp = I915_READ(reg);
3428 temp &= ~FDI_LINK_TRAIN_NONE;
3429 temp |= FDI_LINK_TRAIN_PATTERN_1;
3430 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3431
3432 POSTING_READ(reg);
3433 udelay(150);
3434
3435 /* Ironlake workaround, enable clock pointer after FDI enable*/
3436 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3437 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3438 FDI_RX_PHASE_SYNC_POINTER_EN);
3439
3440 reg = FDI_RX_IIR(pipe);
3441 for (tries = 0; tries < 5; tries++) {
3442 temp = I915_READ(reg);
3443 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3444
3445 if ((temp & FDI_RX_BIT_LOCK)) {
3446 DRM_DEBUG_KMS("FDI train 1 done.\n");
3447 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3448 break;
3449 }
3450 }
3451 if (tries == 5)
3452 DRM_ERROR("FDI train 1 fail!\n");
3453
3454 /* Train 2 */
3455 reg = FDI_TX_CTL(pipe);
3456 temp = I915_READ(reg);
3457 temp &= ~FDI_LINK_TRAIN_NONE;
3458 temp |= FDI_LINK_TRAIN_PATTERN_2;
3459 I915_WRITE(reg, temp);
3460
3461 reg = FDI_RX_CTL(pipe);
3462 temp = I915_READ(reg);
3463 temp &= ~FDI_LINK_TRAIN_NONE;
3464 temp |= FDI_LINK_TRAIN_PATTERN_2;
3465 I915_WRITE(reg, temp);
3466
3467 POSTING_READ(reg);
3468 udelay(150);
3469
3470 reg = FDI_RX_IIR(pipe);
3471 for (tries = 0; tries < 5; tries++) {
3472 temp = I915_READ(reg);
3473 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3474
3475 if (temp & FDI_RX_SYMBOL_LOCK) {
3476 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3477 DRM_DEBUG_KMS("FDI train 2 done.\n");
3478 break;
3479 }
3480 }
3481 if (tries == 5)
3482 DRM_ERROR("FDI train 2 fail!\n");
3483
3484 DRM_DEBUG_KMS("FDI train done\n");
3485
3486}
3487
3488static const int snb_b_fdi_train_param[] = {
3489 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3490 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3491 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3492 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3493};
3494
3495/* The FDI link training functions for SNB/Cougarpoint. */
3496static void gen6_fdi_link_train(struct drm_crtc *crtc)
3497{
3498 struct drm_device *dev = crtc->dev;
3499 struct drm_i915_private *dev_priv = dev->dev_private;
3500 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3501 int pipe = intel_crtc->pipe;
3502 u32 reg, temp, i, retry;
3503
3504 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3505 for train result */
3506 reg = FDI_RX_IMR(pipe);
3507 temp = I915_READ(reg);
3508 temp &= ~FDI_RX_SYMBOL_LOCK;
3509 temp &= ~FDI_RX_BIT_LOCK;
3510 I915_WRITE(reg, temp);
3511
3512 POSTING_READ(reg);
3513 udelay(150);
3514
3515 /* enable CPU FDI TX and PCH FDI RX */
3516 reg = FDI_TX_CTL(pipe);
3517 temp = I915_READ(reg);
3518 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3519 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3520 temp &= ~FDI_LINK_TRAIN_NONE;
3521 temp |= FDI_LINK_TRAIN_PATTERN_1;
3522 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3523 /* SNB-B */
3524 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3525 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3526
3527 I915_WRITE(FDI_RX_MISC(pipe),
3528 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3529
3530 reg = FDI_RX_CTL(pipe);
3531 temp = I915_READ(reg);
3532 if (HAS_PCH_CPT(dev)) {
3533 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3534 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3535 } else {
3536 temp &= ~FDI_LINK_TRAIN_NONE;
3537 temp |= FDI_LINK_TRAIN_PATTERN_1;
3538 }
3539 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3540
3541 POSTING_READ(reg);
3542 udelay(150);
3543
3544 for (i = 0; i < 4; i++) {
3545 reg = FDI_TX_CTL(pipe);
3546 temp = I915_READ(reg);
3547 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3548 temp |= snb_b_fdi_train_param[i];
3549 I915_WRITE(reg, temp);
3550
3551 POSTING_READ(reg);
3552 udelay(500);
3553
3554 for (retry = 0; retry < 5; retry++) {
3555 reg = FDI_RX_IIR(pipe);
3556 temp = I915_READ(reg);
3557 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3558 if (temp & FDI_RX_BIT_LOCK) {
3559 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3560 DRM_DEBUG_KMS("FDI train 1 done.\n");
3561 break;
3562 }
3563 udelay(50);
3564 }
3565 if (retry < 5)
3566 break;
3567 }
3568 if (i == 4)
3569 DRM_ERROR("FDI train 1 fail!\n");
3570
3571 /* Train 2 */
3572 reg = FDI_TX_CTL(pipe);
3573 temp = I915_READ(reg);
3574 temp &= ~FDI_LINK_TRAIN_NONE;
3575 temp |= FDI_LINK_TRAIN_PATTERN_2;
3576 if (IS_GEN6(dev)) {
3577 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3578 /* SNB-B */
3579 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3580 }
3581 I915_WRITE(reg, temp);
3582
3583 reg = FDI_RX_CTL(pipe);
3584 temp = I915_READ(reg);
3585 if (HAS_PCH_CPT(dev)) {
3586 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3587 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3588 } else {
3589 temp &= ~FDI_LINK_TRAIN_NONE;
3590 temp |= FDI_LINK_TRAIN_PATTERN_2;
3591 }
3592 I915_WRITE(reg, temp);
3593
3594 POSTING_READ(reg);
3595 udelay(150);
3596
3597 for (i = 0; i < 4; i++) {
3598 reg = FDI_TX_CTL(pipe);
3599 temp = I915_READ(reg);
3600 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3601 temp |= snb_b_fdi_train_param[i];
3602 I915_WRITE(reg, temp);
3603
3604 POSTING_READ(reg);
3605 udelay(500);
3606
3607 for (retry = 0; retry < 5; retry++) {
3608 reg = FDI_RX_IIR(pipe);
3609 temp = I915_READ(reg);
3610 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3611 if (temp & FDI_RX_SYMBOL_LOCK) {
3612 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3613 DRM_DEBUG_KMS("FDI train 2 done.\n");
3614 break;
3615 }
3616 udelay(50);
3617 }
3618 if (retry < 5)
3619 break;
3620 }
3621 if (i == 4)
3622 DRM_ERROR("FDI train 2 fail!\n");
3623
3624 DRM_DEBUG_KMS("FDI train done.\n");
3625}
3626
3627/* Manual link training for Ivy Bridge A0 parts */
3628static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3629{
3630 struct drm_device *dev = crtc->dev;
3631 struct drm_i915_private *dev_priv = dev->dev_private;
3632 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3633 int pipe = intel_crtc->pipe;
3634 u32 reg, temp, i, j;
3635
3636 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3637 for train result */
3638 reg = FDI_RX_IMR(pipe);
3639 temp = I915_READ(reg);
3640 temp &= ~FDI_RX_SYMBOL_LOCK;
3641 temp &= ~FDI_RX_BIT_LOCK;
3642 I915_WRITE(reg, temp);
3643
3644 POSTING_READ(reg);
3645 udelay(150);
3646
3647 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3648 I915_READ(FDI_RX_IIR(pipe)));
3649
3650 /* Try each vswing and preemphasis setting twice before moving on */
3651 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3652 /* disable first in case we need to retry */
3653 reg = FDI_TX_CTL(pipe);
3654 temp = I915_READ(reg);
3655 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3656 temp &= ~FDI_TX_ENABLE;
3657 I915_WRITE(reg, temp);
3658
3659 reg = FDI_RX_CTL(pipe);
3660 temp = I915_READ(reg);
3661 temp &= ~FDI_LINK_TRAIN_AUTO;
3662 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3663 temp &= ~FDI_RX_ENABLE;
3664 I915_WRITE(reg, temp);
3665
3666 /* enable CPU FDI TX and PCH FDI RX */
3667 reg = FDI_TX_CTL(pipe);
3668 temp = I915_READ(reg);
3669 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3670 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3671 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3672 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3673 temp |= snb_b_fdi_train_param[j/2];
3674 temp |= FDI_COMPOSITE_SYNC;
3675 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3676
3677 I915_WRITE(FDI_RX_MISC(pipe),
3678 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3679
3680 reg = FDI_RX_CTL(pipe);
3681 temp = I915_READ(reg);
3682 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3683 temp |= FDI_COMPOSITE_SYNC;
3684 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3685
3686 POSTING_READ(reg);
3687 udelay(1); /* should be 0.5us */
3688
3689 for (i = 0; i < 4; i++) {
3690 reg = FDI_RX_IIR(pipe);
3691 temp = I915_READ(reg);
3692 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3693
3694 if (temp & FDI_RX_BIT_LOCK ||
3695 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3696 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3697 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3698 i);
3699 break;
3700 }
3701 udelay(1); /* should be 0.5us */
3702 }
3703 if (i == 4) {
3704 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3705 continue;
3706 }
3707
3708 /* Train 2 */
3709 reg = FDI_TX_CTL(pipe);
3710 temp = I915_READ(reg);
3711 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3712 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3713 I915_WRITE(reg, temp);
3714
3715 reg = FDI_RX_CTL(pipe);
3716 temp = I915_READ(reg);
3717 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3718 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3719 I915_WRITE(reg, temp);
3720
3721 POSTING_READ(reg);
3722 udelay(2); /* should be 1.5us */
3723
3724 for (i = 0; i < 4; i++) {
3725 reg = FDI_RX_IIR(pipe);
3726 temp = I915_READ(reg);
3727 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3728
3729 if (temp & FDI_RX_SYMBOL_LOCK ||
3730 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3731 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3732 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3733 i);
3734 goto train_done;
3735 }
3736 udelay(2); /* should be 1.5us */
3737 }
3738 if (i == 4)
3739 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3740 }
3741
3742train_done:
3743 DRM_DEBUG_KMS("FDI train done.\n");
3744}
3745
3746static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3747{
3748 struct drm_device *dev = intel_crtc->base.dev;
3749 struct drm_i915_private *dev_priv = dev->dev_private;
3750 int pipe = intel_crtc->pipe;
3751 u32 reg, temp;
3752
3753
3754 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3755 reg = FDI_RX_CTL(pipe);
3756 temp = I915_READ(reg);
3757 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3758 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3759 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3760 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3761
3762 POSTING_READ(reg);
3763 udelay(200);
3764
3765 /* Switch from Rawclk to PCDclk */
3766 temp = I915_READ(reg);
3767 I915_WRITE(reg, temp | FDI_PCDCLK);
3768
3769 POSTING_READ(reg);
3770 udelay(200);
3771
3772 /* Enable CPU FDI TX PLL, always on for Ironlake */
3773 reg = FDI_TX_CTL(pipe);
3774 temp = I915_READ(reg);
3775 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3776 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3777
3778 POSTING_READ(reg);
3779 udelay(100);
3780 }
3781}
3782
3783static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3784{
3785 struct drm_device *dev = intel_crtc->base.dev;
3786 struct drm_i915_private *dev_priv = dev->dev_private;
3787 int pipe = intel_crtc->pipe;
3788 u32 reg, temp;
3789
3790 /* Switch from PCDclk to Rawclk */
3791 reg = FDI_RX_CTL(pipe);
3792 temp = I915_READ(reg);
3793 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3794
3795 /* Disable CPU FDI TX PLL */
3796 reg = FDI_TX_CTL(pipe);
3797 temp = I915_READ(reg);
3798 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3799
3800 POSTING_READ(reg);
3801 udelay(100);
3802
3803 reg = FDI_RX_CTL(pipe);
3804 temp = I915_READ(reg);
3805 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3806
3807 /* Wait for the clocks to turn off. */
3808 POSTING_READ(reg);
3809 udelay(100);
3810}
3811
3812static void ironlake_fdi_disable(struct drm_crtc *crtc)
3813{
3814 struct drm_device *dev = crtc->dev;
3815 struct drm_i915_private *dev_priv = dev->dev_private;
3816 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3817 int pipe = intel_crtc->pipe;
3818 u32 reg, temp;
3819
3820 /* disable CPU FDI tx and PCH FDI rx */
3821 reg = FDI_TX_CTL(pipe);
3822 temp = I915_READ(reg);
3823 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3824 POSTING_READ(reg);
3825
3826 reg = FDI_RX_CTL(pipe);
3827 temp = I915_READ(reg);
3828 temp &= ~(0x7 << 16);
3829 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3830 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3831
3832 POSTING_READ(reg);
3833 udelay(100);
3834
3835 /* Ironlake workaround, disable clock pointer after downing FDI */
3836 if (HAS_PCH_IBX(dev))
3837 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3838
3839 /* still set train pattern 1 */
3840 reg = FDI_TX_CTL(pipe);
3841 temp = I915_READ(reg);
3842 temp &= ~FDI_LINK_TRAIN_NONE;
3843 temp |= FDI_LINK_TRAIN_PATTERN_1;
3844 I915_WRITE(reg, temp);
3845
3846 reg = FDI_RX_CTL(pipe);
3847 temp = I915_READ(reg);
3848 if (HAS_PCH_CPT(dev)) {
3849 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3850 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3851 } else {
3852 temp &= ~FDI_LINK_TRAIN_NONE;
3853 temp |= FDI_LINK_TRAIN_PATTERN_1;
3854 }
3855 /* BPC in FDI rx is consistent with that in PIPECONF */
3856 temp &= ~(0x07 << 16);
3857 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3858 I915_WRITE(reg, temp);
3859
3860 POSTING_READ(reg);
3861 udelay(100);
3862}
3863
3864bool intel_has_pending_fb_unpin(struct drm_device *dev)
3865{
3866 struct intel_crtc *crtc;
3867
3868 /* Note that we don't need to be called with mode_config.lock here
3869 * as our list of CRTC objects is static for the lifetime of the
3870 * device and so cannot disappear as we iterate. Similarly, we can
3871 * happily treat the predicates as racy, atomic checks as userspace
3872 * cannot claim and pin a new fb without at least acquring the
3873 * struct_mutex and so serialising with us.
3874 */
3875 for_each_intel_crtc(dev, crtc) {
3876 if (atomic_read(&crtc->unpin_work_count) == 0)
3877 continue;
3878
3879 if (crtc->unpin_work)
3880 intel_wait_for_vblank(dev, crtc->pipe);
3881
3882 return true;
3883 }
3884
3885 return false;
3886}
3887
3888static void page_flip_completed(struct intel_crtc *intel_crtc)
3889{
3890 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3891 struct intel_unpin_work *work = intel_crtc->unpin_work;
3892
3893 /* ensure that the unpin work is consistent wrt ->pending. */
3894 smp_rmb();
3895 intel_crtc->unpin_work = NULL;
3896
3897 if (work->event)
3898 drm_send_vblank_event(intel_crtc->base.dev,
3899 intel_crtc->pipe,
3900 work->event);
3901
3902 drm_crtc_vblank_put(&intel_crtc->base);
3903
3904 wake_up_all(&dev_priv->pending_flip_queue);
3905 queue_work(dev_priv->wq, &work->work);
3906
3907 trace_i915_flip_complete(intel_crtc->plane,
3908 work->pending_flip_obj);
3909}
3910
3911void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3912{
3913 struct drm_device *dev = crtc->dev;
3914 struct drm_i915_private *dev_priv = dev->dev_private;
3915
3916 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3917 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3918 !intel_crtc_has_pending_flip(crtc),
3919 60*HZ) == 0)) {
3920 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3921
3922 spin_lock_irq(&dev->event_lock);
3923 if (intel_crtc->unpin_work) {
3924 WARN_ONCE(1, "Removing stuck page flip\n");
3925 page_flip_completed(intel_crtc);
3926 }
3927 spin_unlock_irq(&dev->event_lock);
3928 }
3929
3930 if (crtc->primary->fb) {
3931 mutex_lock(&dev->struct_mutex);
3932 intel_finish_fb(crtc->primary->fb);
3933 mutex_unlock(&dev->struct_mutex);
3934 }
3935}
3936
3937/* Program iCLKIP clock to the desired frequency */
3938static void lpt_program_iclkip(struct drm_crtc *crtc)
3939{
3940 struct drm_device *dev = crtc->dev;
3941 struct drm_i915_private *dev_priv = dev->dev_private;
3942 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3943 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3944 u32 temp;
3945
3946 mutex_lock(&dev_priv->sb_lock);
3947
3948 /* It is necessary to ungate the pixclk gate prior to programming
3949 * the divisors, and gate it back when it is done.
3950 */
3951 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3952
3953 /* Disable SSCCTL */
3954 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3955 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3956 SBI_SSCCTL_DISABLE,
3957 SBI_ICLK);
3958
3959 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3960 if (clock == 20000) {
3961 auxdiv = 1;
3962 divsel = 0x41;
3963 phaseinc = 0x20;
3964 } else {
3965 /* The iCLK virtual clock root frequency is in MHz,
3966 * but the adjusted_mode->crtc_clock in in KHz. To get the
3967 * divisors, it is necessary to divide one by another, so we
3968 * convert the virtual clock precision to KHz here for higher
3969 * precision.
3970 */
3971 u32 iclk_virtual_root_freq = 172800 * 1000;
3972 u32 iclk_pi_range = 64;
3973 u32 desired_divisor, msb_divisor_value, pi_value;
3974
3975 desired_divisor = (iclk_virtual_root_freq / clock);
3976 msb_divisor_value = desired_divisor / iclk_pi_range;
3977 pi_value = desired_divisor % iclk_pi_range;
3978
3979 auxdiv = 0;
3980 divsel = msb_divisor_value - 2;
3981 phaseinc = pi_value;
3982 }
3983
3984 /* This should not happen with any sane values */
3985 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3986 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3987 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3988 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3989
3990 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3991 clock,
3992 auxdiv,
3993 divsel,
3994 phasedir,
3995 phaseinc);
3996
3997 /* Program SSCDIVINTPHASE6 */
3998 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3999 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4000 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4001 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4002 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4003 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4004 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4005 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4006
4007 /* Program SSCAUXDIV */
4008 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4009 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4010 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4011 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4012
4013 /* Enable modulator and associated divider */
4014 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4015 temp &= ~SBI_SSCCTL_DISABLE;
4016 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4017
4018 /* Wait for initialization time */
4019 udelay(24);
4020
4021 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4022
4023 mutex_unlock(&dev_priv->sb_lock);
4024}
4025
4026static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4027 enum pipe pch_transcoder)
4028{
4029 struct drm_device *dev = crtc->base.dev;
4030 struct drm_i915_private *dev_priv = dev->dev_private;
4031 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4032
4033 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4034 I915_READ(HTOTAL(cpu_transcoder)));
4035 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4036 I915_READ(HBLANK(cpu_transcoder)));
4037 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4038 I915_READ(HSYNC(cpu_transcoder)));
4039
4040 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4041 I915_READ(VTOTAL(cpu_transcoder)));
4042 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4043 I915_READ(VBLANK(cpu_transcoder)));
4044 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4045 I915_READ(VSYNC(cpu_transcoder)));
4046 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4047 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4048}
4049
4050static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4051{
4052 struct drm_i915_private *dev_priv = dev->dev_private;
4053 uint32_t temp;
4054
4055 temp = I915_READ(SOUTH_CHICKEN1);
4056 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4057 return;
4058
4059 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4060 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4061
4062 temp &= ~FDI_BC_BIFURCATION_SELECT;
4063 if (enable)
4064 temp |= FDI_BC_BIFURCATION_SELECT;
4065
4066 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4067 I915_WRITE(SOUTH_CHICKEN1, temp);
4068 POSTING_READ(SOUTH_CHICKEN1);
4069}
4070
4071static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4072{
4073 struct drm_device *dev = intel_crtc->base.dev;
4074
4075 switch (intel_crtc->pipe) {
4076 case PIPE_A:
4077 break;
4078 case PIPE_B:
4079 if (intel_crtc->config->fdi_lanes > 2)
4080 cpt_set_fdi_bc_bifurcation(dev, false);
4081 else
4082 cpt_set_fdi_bc_bifurcation(dev, true);
4083
4084 break;
4085 case PIPE_C:
4086 cpt_set_fdi_bc_bifurcation(dev, true);
4087
4088 break;
4089 default:
4090 BUG();
4091 }
4092}
4093
4094/*
4095 * Enable PCH resources required for PCH ports:
4096 * - PCH PLLs
4097 * - FDI training & RX/TX
4098 * - update transcoder timings
4099 * - DP transcoding bits
4100 * - transcoder
4101 */
4102static void ironlake_pch_enable(struct drm_crtc *crtc)
4103{
4104 struct drm_device *dev = crtc->dev;
4105 struct drm_i915_private *dev_priv = dev->dev_private;
4106 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4107 int pipe = intel_crtc->pipe;
4108 u32 reg, temp;
4109
4110 assert_pch_transcoder_disabled(dev_priv, pipe);
4111
4112 if (IS_IVYBRIDGE(dev))
4113 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4114
4115 /* Write the TU size bits before fdi link training, so that error
4116 * detection works. */
4117 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4118 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4119
4120 /* For PCH output, training FDI link */
4121 dev_priv->display.fdi_link_train(crtc);
4122
4123 /* We need to program the right clock selection before writing the pixel
4124 * mutliplier into the DPLL. */
4125 if (HAS_PCH_CPT(dev)) {
4126 u32 sel;
4127
4128 temp = I915_READ(PCH_DPLL_SEL);
4129 temp |= TRANS_DPLL_ENABLE(pipe);
4130 sel = TRANS_DPLLB_SEL(pipe);
4131 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4132 temp |= sel;
4133 else
4134 temp &= ~sel;
4135 I915_WRITE(PCH_DPLL_SEL, temp);
4136 }
4137
4138 /* XXX: pch pll's can be enabled any time before we enable the PCH
4139 * transcoder, and we actually should do this to not upset any PCH
4140 * transcoder that already use the clock when we share it.
4141 *
4142 * Note that enable_shared_dpll tries to do the right thing, but
4143 * get_shared_dpll unconditionally resets the pll - we need that to have
4144 * the right LVDS enable sequence. */
4145 intel_enable_shared_dpll(intel_crtc);
4146
4147 /* set transcoder timing, panel must allow it */
4148 assert_panel_unlocked(dev_priv, pipe);
4149 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4150
4151 intel_fdi_normal_train(crtc);
4152
4153 /* For PCH DP, enable TRANS_DP_CTL */
4154 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4155 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4156 reg = TRANS_DP_CTL(pipe);
4157 temp = I915_READ(reg);
4158 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4159 TRANS_DP_SYNC_MASK |
4160 TRANS_DP_BPC_MASK);
4161 temp |= TRANS_DP_OUTPUT_ENABLE;
4162 temp |= bpc << 9; /* same format but at 11:9 */
4163
4164 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4165 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4166 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4167 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4168
4169 switch (intel_trans_dp_port_sel(crtc)) {
4170 case PCH_DP_B:
4171 temp |= TRANS_DP_PORT_SEL_B;
4172 break;
4173 case PCH_DP_C:
4174 temp |= TRANS_DP_PORT_SEL_C;
4175 break;
4176 case PCH_DP_D:
4177 temp |= TRANS_DP_PORT_SEL_D;
4178 break;
4179 default:
4180 BUG();
4181 }
4182
4183 I915_WRITE(reg, temp);
4184 }
4185
4186 ironlake_enable_pch_transcoder(dev_priv, pipe);
4187}
4188
4189static void lpt_pch_enable(struct drm_crtc *crtc)
4190{
4191 struct drm_device *dev = crtc->dev;
4192 struct drm_i915_private *dev_priv = dev->dev_private;
4193 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4194 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4195
4196 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4197
4198 lpt_program_iclkip(crtc);
4199
4200 /* Set transcoder timing. */
4201 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4202
4203 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4204}
4205
4206struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4207 struct intel_crtc_state *crtc_state)
4208{
4209 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4210 struct intel_shared_dpll *pll;
4211 struct intel_shared_dpll_config *shared_dpll;
4212 enum intel_dpll_id i;
4213
4214 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4215
4216 if (HAS_PCH_IBX(dev_priv->dev)) {
4217 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4218 i = (enum intel_dpll_id) crtc->pipe;
4219 pll = &dev_priv->shared_dplls[i];
4220
4221 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4222 crtc->base.base.id, pll->name);
4223
4224 WARN_ON(shared_dpll[i].crtc_mask);
4225
4226 goto found;
4227 }
4228
4229 if (IS_BROXTON(dev_priv->dev)) {
4230 /* PLL is attached to port in bxt */
4231 struct intel_encoder *encoder;
4232 struct intel_digital_port *intel_dig_port;
4233
4234 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4235 if (WARN_ON(!encoder))
4236 return NULL;
4237
4238 intel_dig_port = enc_to_dig_port(&encoder->base);
4239 /* 1:1 mapping between ports and PLLs */
4240 i = (enum intel_dpll_id)intel_dig_port->port;
4241 pll = &dev_priv->shared_dplls[i];
4242 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4243 crtc->base.base.id, pll->name);
4244 WARN_ON(shared_dpll[i].crtc_mask);
4245
4246 goto found;
4247 }
4248
4249 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4250 pll = &dev_priv->shared_dplls[i];
4251
4252 /* Only want to check enabled timings first */
4253 if (shared_dpll[i].crtc_mask == 0)
4254 continue;
4255
4256 if (memcmp(&crtc_state->dpll_hw_state,
4257 &shared_dpll[i].hw_state,
4258 sizeof(crtc_state->dpll_hw_state)) == 0) {
4259 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4260 crtc->base.base.id, pll->name,
4261 shared_dpll[i].crtc_mask,
4262 pll->active);
4263 goto found;
4264 }
4265 }
4266
4267 /* Ok no matching timings, maybe there's a free one? */
4268 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4269 pll = &dev_priv->shared_dplls[i];
4270 if (shared_dpll[i].crtc_mask == 0) {
4271 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4272 crtc->base.base.id, pll->name);
4273 goto found;
4274 }
4275 }
4276
4277 return NULL;
4278
4279found:
4280 if (shared_dpll[i].crtc_mask == 0)
4281 shared_dpll[i].hw_state =
4282 crtc_state->dpll_hw_state;
4283
4284 crtc_state->shared_dpll = i;
4285 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4286 pipe_name(crtc->pipe));
4287
4288 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4289
4290 return pll;
4291}
4292
4293static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4294{
4295 struct drm_i915_private *dev_priv = to_i915(state->dev);
4296 struct intel_shared_dpll_config *shared_dpll;
4297 struct intel_shared_dpll *pll;
4298 enum intel_dpll_id i;
4299
4300 if (!to_intel_atomic_state(state)->dpll_set)
4301 return;
4302
4303 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4304 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4305 pll = &dev_priv->shared_dplls[i];
4306 pll->config = shared_dpll[i];
4307 }
4308}
4309
4310static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4311{
4312 struct drm_i915_private *dev_priv = dev->dev_private;
4313 int dslreg = PIPEDSL(pipe);
4314 u32 temp;
4315
4316 temp = I915_READ(dslreg);
4317 udelay(500);
4318 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4319 if (wait_for(I915_READ(dslreg) != temp, 5))
4320 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4321 }
4322}
4323
4324static int
4325skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4326 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4327 int src_w, int src_h, int dst_w, int dst_h)
4328{
4329 struct intel_crtc_scaler_state *scaler_state =
4330 &crtc_state->scaler_state;
4331 struct intel_crtc *intel_crtc =
4332 to_intel_crtc(crtc_state->base.crtc);
4333 int need_scaling;
4334
4335 need_scaling = intel_rotation_90_or_270(rotation) ?
4336 (src_h != dst_w || src_w != dst_h):
4337 (src_w != dst_w || src_h != dst_h);
4338
4339 /*
4340 * if plane is being disabled or scaler is no more required or force detach
4341 * - free scaler binded to this plane/crtc
4342 * - in order to do this, update crtc->scaler_usage
4343 *
4344 * Here scaler state in crtc_state is set free so that
4345 * scaler can be assigned to other user. Actual register
4346 * update to free the scaler is done in plane/panel-fit programming.
4347 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4348 */
4349 if (force_detach || !need_scaling) {
4350 if (*scaler_id >= 0) {
4351 scaler_state->scaler_users &= ~(1 << scaler_user);
4352 scaler_state->scalers[*scaler_id].in_use = 0;
4353
4354 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4355 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4356 intel_crtc->pipe, scaler_user, *scaler_id,
4357 scaler_state->scaler_users);
4358 *scaler_id = -1;
4359 }
4360 return 0;
4361 }
4362
4363 /* range checks */
4364 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4365 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4366
4367 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4368 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4369 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4370 "size is out of scaler range\n",
4371 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4372 return -EINVAL;
4373 }
4374
4375 /* mark this plane as a scaler user in crtc_state */
4376 scaler_state->scaler_users |= (1 << scaler_user);
4377 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4378 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4379 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4380 scaler_state->scaler_users);
4381
4382 return 0;
4383}
4384
4385/**
4386 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4387 *
4388 * @state: crtc's scaler state
4389 *
4390 * Return
4391 * 0 - scaler_usage updated successfully
4392 * error - requested scaling cannot be supported or other error condition
4393 */
4394int skl_update_scaler_crtc(struct intel_crtc_state *state)
4395{
4396 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4397 struct drm_display_mode *adjusted_mode =
4398 &state->base.adjusted_mode;
4399
4400 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4401 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4402
4403 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4404 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4405 state->pipe_src_w, state->pipe_src_h,
4406 adjusted_mode->hdisplay, adjusted_mode->vdisplay);
4407}
4408
4409/**
4410 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4411 *
4412 * @state: crtc's scaler state
4413 * @plane_state: atomic plane state to update
4414 *
4415 * Return
4416 * 0 - scaler_usage updated successfully
4417 * error - requested scaling cannot be supported or other error condition
4418 */
4419static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4420 struct intel_plane_state *plane_state)
4421{
4422
4423 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4424 struct intel_plane *intel_plane =
4425 to_intel_plane(plane_state->base.plane);
4426 struct drm_framebuffer *fb = plane_state->base.fb;
4427 int ret;
4428
4429 bool force_detach = !fb || !plane_state->visible;
4430
4431 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4432 intel_plane->base.base.id, intel_crtc->pipe,
4433 drm_plane_index(&intel_plane->base));
4434
4435 ret = skl_update_scaler(crtc_state, force_detach,
4436 drm_plane_index(&intel_plane->base),
4437 &plane_state->scaler_id,
4438 plane_state->base.rotation,
4439 drm_rect_width(&plane_state->src) >> 16,
4440 drm_rect_height(&plane_state->src) >> 16,
4441 drm_rect_width(&plane_state->dst),
4442 drm_rect_height(&plane_state->dst));
4443
4444 if (ret || plane_state->scaler_id < 0)
4445 return ret;
4446
4447 /* check colorkey */
4448 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4449 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4450 intel_plane->base.base.id);
4451 return -EINVAL;
4452 }
4453
4454 /* Check src format */
4455 switch (fb->pixel_format) {
4456 case DRM_FORMAT_RGB565:
4457 case DRM_FORMAT_XBGR8888:
4458 case DRM_FORMAT_XRGB8888:
4459 case DRM_FORMAT_ABGR8888:
4460 case DRM_FORMAT_ARGB8888:
4461 case DRM_FORMAT_XRGB2101010:
4462 case DRM_FORMAT_XBGR2101010:
4463 case DRM_FORMAT_YUYV:
4464 case DRM_FORMAT_YVYU:
4465 case DRM_FORMAT_UYVY:
4466 case DRM_FORMAT_VYUY:
4467 break;
4468 default:
4469 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4470 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4471 return -EINVAL;
4472 }
4473
4474 return 0;
4475}
4476
4477static void skylake_scaler_disable(struct intel_crtc *crtc)
4478{
4479 int i;
4480
4481 for (i = 0; i < crtc->num_scalers; i++)
4482 skl_detach_scaler(crtc, i);
4483}
4484
4485static void skylake_pfit_enable(struct intel_crtc *crtc)
4486{
4487 struct drm_device *dev = crtc->base.dev;
4488 struct drm_i915_private *dev_priv = dev->dev_private;
4489 int pipe = crtc->pipe;
4490 struct intel_crtc_scaler_state *scaler_state =
4491 &crtc->config->scaler_state;
4492
4493 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4494
4495 if (crtc->config->pch_pfit.enabled) {
4496 int id;
4497
4498 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4499 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4500 return;
4501 }
4502
4503 id = scaler_state->scaler_id;
4504 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4505 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4506 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4507 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4508
4509 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4510 }
4511}
4512
4513static void ironlake_pfit_enable(struct intel_crtc *crtc)
4514{
4515 struct drm_device *dev = crtc->base.dev;
4516 struct drm_i915_private *dev_priv = dev->dev_private;
4517 int pipe = crtc->pipe;
4518
4519 if (crtc->config->pch_pfit.enabled) {
4520 /* Force use of hard-coded filter coefficients
4521 * as some pre-programmed values are broken,
4522 * e.g. x201.
4523 */
4524 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4525 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4526 PF_PIPE_SEL_IVB(pipe));
4527 else
4528 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4529 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4530 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4531 }
4532}
4533
4534void hsw_enable_ips(struct intel_crtc *crtc)
4535{
4536 struct drm_device *dev = crtc->base.dev;
4537 struct drm_i915_private *dev_priv = dev->dev_private;
4538
4539 if (!crtc->config->ips_enabled)
4540 return;
4541
4542 /* We can only enable IPS after we enable a plane and wait for a vblank */
4543 intel_wait_for_vblank(dev, crtc->pipe);
4544
4545 assert_plane_enabled(dev_priv, crtc->plane);
4546 if (IS_BROADWELL(dev)) {
4547 mutex_lock(&dev_priv->rps.hw_lock);
4548 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4549 mutex_unlock(&dev_priv->rps.hw_lock);
4550 /* Quoting Art Runyan: "its not safe to expect any particular
4551 * value in IPS_CTL bit 31 after enabling IPS through the
4552 * mailbox." Moreover, the mailbox may return a bogus state,
4553 * so we need to just enable it and continue on.
4554 */
4555 } else {
4556 I915_WRITE(IPS_CTL, IPS_ENABLE);
4557 /* The bit only becomes 1 in the next vblank, so this wait here
4558 * is essentially intel_wait_for_vblank. If we don't have this
4559 * and don't wait for vblanks until the end of crtc_enable, then
4560 * the HW state readout code will complain that the expected
4561 * IPS_CTL value is not the one we read. */
4562 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4563 DRM_ERROR("Timed out waiting for IPS enable\n");
4564 }
4565}
4566
4567void hsw_disable_ips(struct intel_crtc *crtc)
4568{
4569 struct drm_device *dev = crtc->base.dev;
4570 struct drm_i915_private *dev_priv = dev->dev_private;
4571
4572 if (!crtc->config->ips_enabled)
4573 return;
4574
4575 assert_plane_enabled(dev_priv, crtc->plane);
4576 if (IS_BROADWELL(dev)) {
4577 mutex_lock(&dev_priv->rps.hw_lock);
4578 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4579 mutex_unlock(&dev_priv->rps.hw_lock);
4580 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4581 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4582 DRM_ERROR("Timed out waiting for IPS disable\n");
4583 } else {
4584 I915_WRITE(IPS_CTL, 0);
4585 POSTING_READ(IPS_CTL);
4586 }
4587
4588 /* We need to wait for a vblank before we can disable the plane. */
4589 intel_wait_for_vblank(dev, crtc->pipe);
4590}
4591
4592/** Loads the palette/gamma unit for the CRTC with the prepared values */
4593static void intel_crtc_load_lut(struct drm_crtc *crtc)
4594{
4595 struct drm_device *dev = crtc->dev;
4596 struct drm_i915_private *dev_priv = dev->dev_private;
4597 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4598 enum pipe pipe = intel_crtc->pipe;
4599 int palreg = PALETTE(pipe);
4600 int i;
4601 bool reenable_ips = false;
4602
4603 /* The clocks have to be on to load the palette. */
4604 if (!crtc->state->active)
4605 return;
4606
4607 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4608 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4609 assert_dsi_pll_enabled(dev_priv);
4610 else
4611 assert_pll_enabled(dev_priv, pipe);
4612 }
4613
4614 /* use legacy palette for Ironlake */
4615 if (!HAS_GMCH_DISPLAY(dev))
4616 palreg = LGC_PALETTE(pipe);
4617
4618 /* Workaround : Do not read or write the pipe palette/gamma data while
4619 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4620 */
4621 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4622 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4623 GAMMA_MODE_MODE_SPLIT)) {
4624 hsw_disable_ips(intel_crtc);
4625 reenable_ips = true;
4626 }
4627
4628 for (i = 0; i < 256; i++) {
4629 I915_WRITE(palreg + 4 * i,
4630 (intel_crtc->lut_r[i] << 16) |
4631 (intel_crtc->lut_g[i] << 8) |
4632 intel_crtc->lut_b[i]);
4633 }
4634
4635 if (reenable_ips)
4636 hsw_enable_ips(intel_crtc);
4637}
4638
4639static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4640{
4641 if (intel_crtc->overlay) {
4642 struct drm_device *dev = intel_crtc->base.dev;
4643 struct drm_i915_private *dev_priv = dev->dev_private;
4644
4645 mutex_lock(&dev->struct_mutex);
4646 dev_priv->mm.interruptible = false;
4647 (void) intel_overlay_switch_off(intel_crtc->overlay);
4648 dev_priv->mm.interruptible = true;
4649 mutex_unlock(&dev->struct_mutex);
4650 }
4651
4652 /* Let userspace switch the overlay on again. In most cases userspace
4653 * has to recompute where to put it anyway.
4654 */
4655}
4656
4657/**
4658 * intel_post_enable_primary - Perform operations after enabling primary plane
4659 * @crtc: the CRTC whose primary plane was just enabled
4660 *
4661 * Performs potentially sleeping operations that must be done after the primary
4662 * plane is enabled, such as updating FBC and IPS. Note that this may be
4663 * called due to an explicit primary plane update, or due to an implicit
4664 * re-enable that is caused when a sprite plane is updated to no longer
4665 * completely hide the primary plane.
4666 */
4667static void
4668intel_post_enable_primary(struct drm_crtc *crtc)
4669{
4670 struct drm_device *dev = crtc->dev;
4671 struct drm_i915_private *dev_priv = dev->dev_private;
4672 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4673 int pipe = intel_crtc->pipe;
4674
4675 /*
4676 * BDW signals flip done immediately if the plane
4677 * is disabled, even if the plane enable is already
4678 * armed to occur at the next vblank :(
4679 */
4680 if (IS_BROADWELL(dev))
4681 intel_wait_for_vblank(dev, pipe);
4682
4683 /*
4684 * FIXME IPS should be fine as long as one plane is
4685 * enabled, but in practice it seems to have problems
4686 * when going from primary only to sprite only and vice
4687 * versa.
4688 */
4689 hsw_enable_ips(intel_crtc);
4690
4691 /*
4692 * Gen2 reports pipe underruns whenever all planes are disabled.
4693 * So don't enable underrun reporting before at least some planes
4694 * are enabled.
4695 * FIXME: Need to fix the logic to work when we turn off all planes
4696 * but leave the pipe running.
4697 */
4698 if (IS_GEN2(dev))
4699 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4700
4701 /* Underruns don't raise interrupts, so check manually. */
4702 if (HAS_GMCH_DISPLAY(dev))
4703 i9xx_check_fifo_underruns(dev_priv);
4704}
4705
4706/**
4707 * intel_pre_disable_primary - Perform operations before disabling primary plane
4708 * @crtc: the CRTC whose primary plane is to be disabled
4709 *
4710 * Performs potentially sleeping operations that must be done before the
4711 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4712 * be called due to an explicit primary plane update, or due to an implicit
4713 * disable that is caused when a sprite plane completely hides the primary
4714 * plane.
4715 */
4716static void
4717intel_pre_disable_primary(struct drm_crtc *crtc)
4718{
4719 struct drm_device *dev = crtc->dev;
4720 struct drm_i915_private *dev_priv = dev->dev_private;
4721 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4722 int pipe = intel_crtc->pipe;
4723
4724 /*
4725 * Gen2 reports pipe underruns whenever all planes are disabled.
4726 * So diasble underrun reporting before all the planes get disabled.
4727 * FIXME: Need to fix the logic to work when we turn off all planes
4728 * but leave the pipe running.
4729 */
4730 if (IS_GEN2(dev))
4731 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4732
4733 /*
4734 * Vblank time updates from the shadow to live plane control register
4735 * are blocked if the memory self-refresh mode is active at that
4736 * moment. So to make sure the plane gets truly disabled, disable
4737 * first the self-refresh mode. The self-refresh enable bit in turn
4738 * will be checked/applied by the HW only at the next frame start
4739 * event which is after the vblank start event, so we need to have a
4740 * wait-for-vblank between disabling the plane and the pipe.
4741 */
4742 if (HAS_GMCH_DISPLAY(dev)) {
4743 intel_set_memory_cxsr(dev_priv, false);
4744 dev_priv->wm.vlv.cxsr = false;
4745 intel_wait_for_vblank(dev, pipe);
4746 }
4747
4748 /*
4749 * FIXME IPS should be fine as long as one plane is
4750 * enabled, but in practice it seems to have problems
4751 * when going from primary only to sprite only and vice
4752 * versa.
4753 */
4754 hsw_disable_ips(intel_crtc);
4755}
4756
4757static void intel_post_plane_update(struct intel_crtc *crtc)
4758{
4759 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4760 struct drm_device *dev = crtc->base.dev;
4761 struct drm_i915_private *dev_priv = dev->dev_private;
4762 struct drm_plane *plane;
4763
4764 if (atomic->wait_vblank)
4765 intel_wait_for_vblank(dev, crtc->pipe);
4766
4767 intel_frontbuffer_flip(dev, atomic->fb_bits);
4768
4769 if (atomic->disable_cxsr)
4770 crtc->wm.cxsr_allowed = true;
4771
4772 if (crtc->atomic.update_wm_post)
4773 intel_update_watermarks(&crtc->base);
4774
4775 if (atomic->update_fbc)
4776 intel_fbc_update(dev_priv);
4777
4778 if (atomic->post_enable_primary)
4779 intel_post_enable_primary(&crtc->base);
4780
4781 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4782 intel_update_sprite_watermarks(plane, &crtc->base,
4783 0, 0, 0, false, false);
4784
4785 memset(atomic, 0, sizeof(*atomic));
4786}
4787
4788static void intel_pre_plane_update(struct intel_crtc *crtc)
4789{
4790 struct drm_device *dev = crtc->base.dev;
4791 struct drm_i915_private *dev_priv = dev->dev_private;
4792 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4793 struct drm_plane *p;
4794
4795 /* Track fb's for any planes being disabled */
4796 drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4797 struct intel_plane *plane = to_intel_plane(p);
4798
4799 mutex_lock(&dev->struct_mutex);
4800 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4801 plane->frontbuffer_bit);
4802 mutex_unlock(&dev->struct_mutex);
4803 }
4804
4805 if (atomic->wait_for_flips)
4806 intel_crtc_wait_for_pending_flips(&crtc->base);
4807
4808 if (atomic->disable_fbc)
4809 intel_fbc_disable_crtc(crtc);
4810
4811 if (crtc->atomic.disable_ips)
4812 hsw_disable_ips(crtc);
4813
4814 if (atomic->pre_disable_primary)
4815 intel_pre_disable_primary(&crtc->base);
4816
4817 if (atomic->disable_cxsr) {
4818 crtc->wm.cxsr_allowed = false;
4819 intel_set_memory_cxsr(dev_priv, false);
4820 }
4821}
4822
4823static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4824{
4825 struct drm_device *dev = crtc->dev;
4826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4827 struct drm_plane *p;
4828 int pipe = intel_crtc->pipe;
4829
4830 intel_crtc_dpms_overlay_disable(intel_crtc);
4831
4832 drm_for_each_plane_mask(p, dev, plane_mask)
4833 to_intel_plane(p)->disable_plane(p, crtc);
4834
4835 /*
4836 * FIXME: Once we grow proper nuclear flip support out of this we need
4837 * to compute the mask of flip planes precisely. For the time being
4838 * consider this a flip to a NULL plane.
4839 */
4840 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4841}
4842
4843static void ironlake_crtc_enable(struct drm_crtc *crtc)
4844{
4845 struct drm_device *dev = crtc->dev;
4846 struct drm_i915_private *dev_priv = dev->dev_private;
4847 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4848 struct intel_encoder *encoder;
4849 int pipe = intel_crtc->pipe;
4850
4851 if (WARN_ON(intel_crtc->active))
4852 return;
4853
4854 if (intel_crtc->config->has_pch_encoder)
4855 intel_prepare_shared_dpll(intel_crtc);
4856
4857 if (intel_crtc->config->has_dp_encoder)
4858 intel_dp_set_m_n(intel_crtc, M1_N1);
4859
4860 intel_set_pipe_timings(intel_crtc);
4861
4862 if (intel_crtc->config->has_pch_encoder) {
4863 intel_cpu_transcoder_set_m_n(intel_crtc,
4864 &intel_crtc->config->fdi_m_n, NULL);
4865 }
4866
4867 ironlake_set_pipeconf(crtc);
4868
4869 intel_crtc->active = true;
4870
4871 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4872 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4873
4874 for_each_encoder_on_crtc(dev, crtc, encoder)
4875 if (encoder->pre_enable)
4876 encoder->pre_enable(encoder);
4877
4878 if (intel_crtc->config->has_pch_encoder) {
4879 /* Note: FDI PLL enabling _must_ be done before we enable the
4880 * cpu pipes, hence this is separate from all the other fdi/pch
4881 * enabling. */
4882 ironlake_fdi_pll_enable(intel_crtc);
4883 } else {
4884 assert_fdi_tx_disabled(dev_priv, pipe);
4885 assert_fdi_rx_disabled(dev_priv, pipe);
4886 }
4887
4888 ironlake_pfit_enable(intel_crtc);
4889
4890 /*
4891 * On ILK+ LUT must be loaded before the pipe is running but with
4892 * clocks enabled
4893 */
4894 intel_crtc_load_lut(crtc);
4895
4896 intel_update_watermarks(crtc);
4897 intel_enable_pipe(intel_crtc);
4898
4899 if (intel_crtc->config->has_pch_encoder)
4900 ironlake_pch_enable(crtc);
4901
4902 assert_vblank_disabled(crtc);
4903 drm_crtc_vblank_on(crtc);
4904
4905 for_each_encoder_on_crtc(dev, crtc, encoder)
4906 encoder->enable(encoder);
4907
4908 if (HAS_PCH_CPT(dev))
4909 cpt_verify_modeset(dev, intel_crtc->pipe);
4910}
4911
4912/* IPS only exists on ULT machines and is tied to pipe A. */
4913static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4914{
4915 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4916}
4917
4918static void haswell_crtc_enable(struct drm_crtc *crtc)
4919{
4920 struct drm_device *dev = crtc->dev;
4921 struct drm_i915_private *dev_priv = dev->dev_private;
4922 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4923 struct intel_encoder *encoder;
4924 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4925 struct intel_crtc_state *pipe_config =
4926 to_intel_crtc_state(crtc->state);
4927
4928 if (WARN_ON(intel_crtc->active))
4929 return;
4930
4931 if (intel_crtc_to_shared_dpll(intel_crtc))
4932 intel_enable_shared_dpll(intel_crtc);
4933
4934 if (intel_crtc->config->has_dp_encoder)
4935 intel_dp_set_m_n(intel_crtc, M1_N1);
4936
4937 intel_set_pipe_timings(intel_crtc);
4938
4939 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4940 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4941 intel_crtc->config->pixel_multiplier - 1);
4942 }
4943
4944 if (intel_crtc->config->has_pch_encoder) {
4945 intel_cpu_transcoder_set_m_n(intel_crtc,
4946 &intel_crtc->config->fdi_m_n, NULL);
4947 }
4948
4949 haswell_set_pipeconf(crtc);
4950
4951 intel_set_pipe_csc(crtc);
4952
4953 intel_crtc->active = true;
4954
4955 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4956 for_each_encoder_on_crtc(dev, crtc, encoder)
4957 if (encoder->pre_enable)
4958 encoder->pre_enable(encoder);
4959
4960 if (intel_crtc->config->has_pch_encoder) {
4961 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4962 true);
4963 dev_priv->display.fdi_link_train(crtc);
4964 }
4965
4966 intel_ddi_enable_pipe_clock(intel_crtc);
4967
4968 if (INTEL_INFO(dev)->gen == 9)
4969 skylake_pfit_enable(intel_crtc);
4970 else if (INTEL_INFO(dev)->gen < 9)
4971 ironlake_pfit_enable(intel_crtc);
4972 else
4973 MISSING_CASE(INTEL_INFO(dev)->gen);
4974
4975 /*
4976 * On ILK+ LUT must be loaded before the pipe is running but with
4977 * clocks enabled
4978 */
4979 intel_crtc_load_lut(crtc);
4980
4981 intel_ddi_set_pipe_settings(crtc);
4982 intel_ddi_enable_transcoder_func(crtc);
4983
4984 intel_update_watermarks(crtc);
4985 intel_enable_pipe(intel_crtc);
4986
4987 if (intel_crtc->config->has_pch_encoder)
4988 lpt_pch_enable(crtc);
4989
4990 if (intel_crtc->config->dp_encoder_is_mst)
4991 intel_ddi_set_vc_payload_alloc(crtc, true);
4992
4993 assert_vblank_disabled(crtc);
4994 drm_crtc_vblank_on(crtc);
4995
4996 for_each_encoder_on_crtc(dev, crtc, encoder) {
4997 encoder->enable(encoder);
4998 intel_opregion_notify_encoder(encoder, true);
4999 }
5000
5001 /* If we change the relative order between pipe/planes enabling, we need
5002 * to change the workaround. */
5003 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5004 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5005 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5006 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5007 }
5008}
5009
5010static void ironlake_pfit_disable(struct intel_crtc *crtc)
5011{
5012 struct drm_device *dev = crtc->base.dev;
5013 struct drm_i915_private *dev_priv = dev->dev_private;
5014 int pipe = crtc->pipe;
5015
5016 /* To avoid upsetting the power well on haswell only disable the pfit if
5017 * it's in use. The hw state code will make sure we get this right. */
5018 if (crtc->config->pch_pfit.enabled) {
5019 I915_WRITE(PF_CTL(pipe), 0);
5020 I915_WRITE(PF_WIN_POS(pipe), 0);
5021 I915_WRITE(PF_WIN_SZ(pipe), 0);
5022 }
5023}
5024
5025static void ironlake_crtc_disable(struct drm_crtc *crtc)
5026{
5027 struct drm_device *dev = crtc->dev;
5028 struct drm_i915_private *dev_priv = dev->dev_private;
5029 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5030 struct intel_encoder *encoder;
5031 int pipe = intel_crtc->pipe;
5032 u32 reg, temp;
5033
5034 for_each_encoder_on_crtc(dev, crtc, encoder)
5035 encoder->disable(encoder);
5036
5037 drm_crtc_vblank_off(crtc);
5038 assert_vblank_disabled(crtc);
5039
5040 if (intel_crtc->config->has_pch_encoder)
5041 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5042
5043 intel_disable_pipe(intel_crtc);
5044
5045 ironlake_pfit_disable(intel_crtc);
5046
5047 if (intel_crtc->config->has_pch_encoder)
5048 ironlake_fdi_disable(crtc);
5049
5050 for_each_encoder_on_crtc(dev, crtc, encoder)
5051 if (encoder->post_disable)
5052 encoder->post_disable(encoder);
5053
5054 if (intel_crtc->config->has_pch_encoder) {
5055 ironlake_disable_pch_transcoder(dev_priv, pipe);
5056
5057 if (HAS_PCH_CPT(dev)) {
5058 /* disable TRANS_DP_CTL */
5059 reg = TRANS_DP_CTL(pipe);
5060 temp = I915_READ(reg);
5061 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5062 TRANS_DP_PORT_SEL_MASK);
5063 temp |= TRANS_DP_PORT_SEL_NONE;
5064 I915_WRITE(reg, temp);
5065
5066 /* disable DPLL_SEL */
5067 temp = I915_READ(PCH_DPLL_SEL);
5068 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5069 I915_WRITE(PCH_DPLL_SEL, temp);
5070 }
5071
5072 ironlake_fdi_pll_disable(intel_crtc);
5073 }
5074
5075 intel_crtc->active = false;
5076 intel_update_watermarks(crtc);
5077}
5078
5079static void haswell_crtc_disable(struct drm_crtc *crtc)
5080{
5081 struct drm_device *dev = crtc->dev;
5082 struct drm_i915_private *dev_priv = dev->dev_private;
5083 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5084 struct intel_encoder *encoder;
5085 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5086
5087 for_each_encoder_on_crtc(dev, crtc, encoder) {
5088 intel_opregion_notify_encoder(encoder, false);
5089 encoder->disable(encoder);
5090 }
5091
5092 drm_crtc_vblank_off(crtc);
5093 assert_vblank_disabled(crtc);
5094
5095 if (intel_crtc->config->has_pch_encoder)
5096 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5097 false);
5098 intel_disable_pipe(intel_crtc);
5099
5100 if (intel_crtc->config->dp_encoder_is_mst)
5101 intel_ddi_set_vc_payload_alloc(crtc, false);
5102
5103 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5104
5105 if (INTEL_INFO(dev)->gen == 9)
5106 skylake_scaler_disable(intel_crtc);
5107 else if (INTEL_INFO(dev)->gen < 9)
5108 ironlake_pfit_disable(intel_crtc);
5109 else
5110 MISSING_CASE(INTEL_INFO(dev)->gen);
5111
5112 intel_ddi_disable_pipe_clock(intel_crtc);
5113
5114 if (intel_crtc->config->has_pch_encoder) {
5115 lpt_disable_pch_transcoder(dev_priv);
5116 intel_ddi_fdi_disable(crtc);
5117 }
5118
5119 for_each_encoder_on_crtc(dev, crtc, encoder)
5120 if (encoder->post_disable)
5121 encoder->post_disable(encoder);
5122
5123 intel_crtc->active = false;
5124 intel_update_watermarks(crtc);
5125}
5126
5127static void i9xx_pfit_enable(struct intel_crtc *crtc)
5128{
5129 struct drm_device *dev = crtc->base.dev;
5130 struct drm_i915_private *dev_priv = dev->dev_private;
5131 struct intel_crtc_state *pipe_config = crtc->config;
5132
5133 if (!pipe_config->gmch_pfit.control)
5134 return;
5135
5136 /*
5137 * The panel fitter should only be adjusted whilst the pipe is disabled,
5138 * according to register description and PRM.
5139 */
5140 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5141 assert_pipe_disabled(dev_priv, crtc->pipe);
5142
5143 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5144 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5145
5146 /* Border color in case we don't scale up to the full screen. Black by
5147 * default, change to something else for debugging. */
5148 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5149}
5150
5151static enum intel_display_power_domain port_to_power_domain(enum port port)
5152{
5153 switch (port) {
5154 case PORT_A:
5155 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5156 case PORT_B:
5157 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5158 case PORT_C:
5159 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5160 case PORT_D:
5161 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5162 case PORT_E:
5163 return POWER_DOMAIN_PORT_DDI_E_2_LANES;
5164 default:
5165 WARN_ON_ONCE(1);
5166 return POWER_DOMAIN_PORT_OTHER;
5167 }
5168}
5169
5170#define for_each_power_domain(domain, mask) \
5171 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5172 if ((1 << (domain)) & (mask))
5173
5174enum intel_display_power_domain
5175intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5176{
5177 struct drm_device *dev = intel_encoder->base.dev;
5178 struct intel_digital_port *intel_dig_port;
5179
5180 switch (intel_encoder->type) {
5181 case INTEL_OUTPUT_UNKNOWN:
5182 /* Only DDI platforms should ever use this output type */
5183 WARN_ON_ONCE(!HAS_DDI(dev));
5184 case INTEL_OUTPUT_DISPLAYPORT:
5185 case INTEL_OUTPUT_HDMI:
5186 case INTEL_OUTPUT_EDP:
5187 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5188 return port_to_power_domain(intel_dig_port->port);
5189 case INTEL_OUTPUT_DP_MST:
5190 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5191 return port_to_power_domain(intel_dig_port->port);
5192 case INTEL_OUTPUT_ANALOG:
5193 return POWER_DOMAIN_PORT_CRT;
5194 case INTEL_OUTPUT_DSI:
5195 return POWER_DOMAIN_PORT_DSI;
5196 default:
5197 return POWER_DOMAIN_PORT_OTHER;
5198 }
5199}
5200
5201static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5202{
5203 struct drm_device *dev = crtc->dev;
5204 struct intel_encoder *intel_encoder;
5205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5206 enum pipe pipe = intel_crtc->pipe;
5207 unsigned long mask;
5208 enum transcoder transcoder;
5209
5210 if (!crtc->state->active)
5211 return 0;
5212
5213 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5214
5215 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5216 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5217 if (intel_crtc->config->pch_pfit.enabled ||
5218 intel_crtc->config->pch_pfit.force_thru)
5219 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5220
5221 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5222 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5223
5224 return mask;
5225}
5226
5227static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5228{
5229 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5230 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5231 enum intel_display_power_domain domain;
5232 unsigned long domains, new_domains, old_domains;
5233
5234 old_domains = intel_crtc->enabled_power_domains;
5235 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5236
5237 domains = new_domains & ~old_domains;
5238
5239 for_each_power_domain(domain, domains)
5240 intel_display_power_get(dev_priv, domain);
5241
5242 return old_domains & ~new_domains;
5243}
5244
5245static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5246 unsigned long domains)
5247{
5248 enum intel_display_power_domain domain;
5249
5250 for_each_power_domain(domain, domains)
5251 intel_display_power_put(dev_priv, domain);
5252}
5253
5254static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5255{
5256 struct drm_device *dev = state->dev;
5257 struct drm_i915_private *dev_priv = dev->dev_private;
5258 unsigned long put_domains[I915_MAX_PIPES] = {};
5259 struct drm_crtc_state *crtc_state;
5260 struct drm_crtc *crtc;
5261 int i;
5262
5263 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5264 if (needs_modeset(crtc->state))
5265 put_domains[to_intel_crtc(crtc)->pipe] =
5266 modeset_get_crtc_power_domains(crtc);
5267 }
5268
5269 if (dev_priv->display.modeset_commit_cdclk) {
5270 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5271
5272 if (cdclk != dev_priv->cdclk_freq &&
5273 !WARN_ON(!state->allow_modeset))
5274 dev_priv->display.modeset_commit_cdclk(state);
5275 }
5276
5277 for (i = 0; i < I915_MAX_PIPES; i++)
5278 if (put_domains[i])
5279 modeset_put_power_domains(dev_priv, put_domains[i]);
5280}
5281
5282static void intel_update_max_cdclk(struct drm_device *dev)
5283{
5284 struct drm_i915_private *dev_priv = dev->dev_private;
5285
5286 if (IS_SKYLAKE(dev)) {
5287 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5288
5289 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5290 dev_priv->max_cdclk_freq = 675000;
5291 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5292 dev_priv->max_cdclk_freq = 540000;
5293 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5294 dev_priv->max_cdclk_freq = 450000;
5295 else
5296 dev_priv->max_cdclk_freq = 337500;
5297 } else if (IS_BROADWELL(dev)) {
5298 /*
5299 * FIXME with extra cooling we can allow
5300 * 540 MHz for ULX and 675 Mhz for ULT.
5301 * How can we know if extra cooling is
5302 * available? PCI ID, VTB, something else?
5303 */
5304 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5305 dev_priv->max_cdclk_freq = 450000;
5306 else if (IS_BDW_ULX(dev))
5307 dev_priv->max_cdclk_freq = 450000;
5308 else if (IS_BDW_ULT(dev))
5309 dev_priv->max_cdclk_freq = 540000;
5310 else
5311 dev_priv->max_cdclk_freq = 675000;
5312 } else if (IS_CHERRYVIEW(dev)) {
5313 dev_priv->max_cdclk_freq = 320000;
5314 } else if (IS_VALLEYVIEW(dev)) {
5315 dev_priv->max_cdclk_freq = 400000;
5316 } else {
5317 /* otherwise assume cdclk is fixed */
5318 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5319 }
5320
5321 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5322 dev_priv->max_cdclk_freq);
5323}
5324
5325static void intel_update_cdclk(struct drm_device *dev)
5326{
5327 struct drm_i915_private *dev_priv = dev->dev_private;
5328
5329 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5330 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5331 dev_priv->cdclk_freq);
5332
5333 /*
5334 * Program the gmbus_freq based on the cdclk frequency.
5335 * BSpec erroneously claims we should aim for 4MHz, but
5336 * in fact 1MHz is the correct frequency.
5337 */
5338 if (IS_VALLEYVIEW(dev)) {
5339 /*
5340 * Program the gmbus_freq based on the cdclk frequency.
5341 * BSpec erroneously claims we should aim for 4MHz, but
5342 * in fact 1MHz is the correct frequency.
5343 */
5344 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5345 }
5346
5347 if (dev_priv->max_cdclk_freq == 0)
5348 intel_update_max_cdclk(dev);
5349}
5350
5351static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5352{
5353 struct drm_i915_private *dev_priv = dev->dev_private;
5354 uint32_t divider;
5355 uint32_t ratio;
5356 uint32_t current_freq;
5357 int ret;
5358
5359 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5360 switch (frequency) {
5361 case 144000:
5362 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5363 ratio = BXT_DE_PLL_RATIO(60);
5364 break;
5365 case 288000:
5366 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5367 ratio = BXT_DE_PLL_RATIO(60);
5368 break;
5369 case 384000:
5370 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5371 ratio = BXT_DE_PLL_RATIO(60);
5372 break;
5373 case 576000:
5374 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5375 ratio = BXT_DE_PLL_RATIO(60);
5376 break;
5377 case 624000:
5378 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5379 ratio = BXT_DE_PLL_RATIO(65);
5380 break;
5381 case 19200:
5382 /*
5383 * Bypass frequency with DE PLL disabled. Init ratio, divider
5384 * to suppress GCC warning.
5385 */
5386 ratio = 0;
5387 divider = 0;
5388 break;
5389 default:
5390 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5391
5392 return;
5393 }
5394
5395 mutex_lock(&dev_priv->rps.hw_lock);
5396 /* Inform power controller of upcoming frequency change */
5397 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5398 0x80000000);
5399 mutex_unlock(&dev_priv->rps.hw_lock);
5400
5401 if (ret) {
5402 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5403 ret, frequency);
5404 return;
5405 }
5406
5407 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5408 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5409 current_freq = current_freq * 500 + 1000;
5410
5411 /*
5412 * DE PLL has to be disabled when
5413 * - setting to 19.2MHz (bypass, PLL isn't used)
5414 * - before setting to 624MHz (PLL needs toggling)
5415 * - before setting to any frequency from 624MHz (PLL needs toggling)
5416 */
5417 if (frequency == 19200 || frequency == 624000 ||
5418 current_freq == 624000) {
5419 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5420 /* Timeout 200us */
5421 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5422 1))
5423 DRM_ERROR("timout waiting for DE PLL unlock\n");
5424 }
5425
5426 if (frequency != 19200) {
5427 uint32_t val;
5428
5429 val = I915_READ(BXT_DE_PLL_CTL);
5430 val &= ~BXT_DE_PLL_RATIO_MASK;
5431 val |= ratio;
5432 I915_WRITE(BXT_DE_PLL_CTL, val);
5433
5434 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5435 /* Timeout 200us */
5436 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5437 DRM_ERROR("timeout waiting for DE PLL lock\n");
5438
5439 val = I915_READ(CDCLK_CTL);
5440 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5441 val |= divider;
5442 /*
5443 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5444 * enable otherwise.
5445 */
5446 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5447 if (frequency >= 500000)
5448 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5449
5450 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5451 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5452 val |= (frequency - 1000) / 500;
5453 I915_WRITE(CDCLK_CTL, val);
5454 }
5455
5456 mutex_lock(&dev_priv->rps.hw_lock);
5457 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5458 DIV_ROUND_UP(frequency, 25000));
5459 mutex_unlock(&dev_priv->rps.hw_lock);
5460
5461 if (ret) {
5462 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5463 ret, frequency);
5464 return;
5465 }
5466
5467 intel_update_cdclk(dev);
5468}
5469
5470void broxton_init_cdclk(struct drm_device *dev)
5471{
5472 struct drm_i915_private *dev_priv = dev->dev_private;
5473 uint32_t val;
5474
5475 /*
5476 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5477 * or else the reset will hang because there is no PCH to respond.
5478 * Move the handshake programming to initialization sequence.
5479 * Previously was left up to BIOS.
5480 */
5481 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5482 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5483 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5484
5485 /* Enable PG1 for cdclk */
5486 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5487
5488 /* check if cd clock is enabled */
5489 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5490 DRM_DEBUG_KMS("Display already initialized\n");
5491 return;
5492 }
5493
5494 /*
5495 * FIXME:
5496 * - The initial CDCLK needs to be read from VBT.
5497 * Need to make this change after VBT has changes for BXT.
5498 * - check if setting the max (or any) cdclk freq is really necessary
5499 * here, it belongs to modeset time
5500 */
5501 broxton_set_cdclk(dev, 624000);
5502
5503 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5504 POSTING_READ(DBUF_CTL);
5505
5506 udelay(10);
5507
5508 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5509 DRM_ERROR("DBuf power enable timeout!\n");
5510}
5511
5512void broxton_uninit_cdclk(struct drm_device *dev)
5513{
5514 struct drm_i915_private *dev_priv = dev->dev_private;
5515
5516 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5517 POSTING_READ(DBUF_CTL);
5518
5519 udelay(10);
5520
5521 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5522 DRM_ERROR("DBuf power disable timeout!\n");
5523
5524 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5525 broxton_set_cdclk(dev, 19200);
5526
5527 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5528}
5529
5530static const struct skl_cdclk_entry {
5531 unsigned int freq;
5532 unsigned int vco;
5533} skl_cdclk_frequencies[] = {
5534 { .freq = 308570, .vco = 8640 },
5535 { .freq = 337500, .vco = 8100 },
5536 { .freq = 432000, .vco = 8640 },
5537 { .freq = 450000, .vco = 8100 },
5538 { .freq = 540000, .vco = 8100 },
5539 { .freq = 617140, .vco = 8640 },
5540 { .freq = 675000, .vco = 8100 },
5541};
5542
5543static unsigned int skl_cdclk_decimal(unsigned int freq)
5544{
5545 return (freq - 1000) / 500;
5546}
5547
5548static unsigned int skl_cdclk_get_vco(unsigned int freq)
5549{
5550 unsigned int i;
5551
5552 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5553 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5554
5555 if (e->freq == freq)
5556 return e->vco;
5557 }
5558
5559 return 8100;
5560}
5561
5562static void
5563skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5564{
5565 unsigned int min_freq;
5566 u32 val;
5567
5568 /* select the minimum CDCLK before enabling DPLL 0 */
5569 val = I915_READ(CDCLK_CTL);
5570 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5571 val |= CDCLK_FREQ_337_308;
5572
5573 if (required_vco == 8640)
5574 min_freq = 308570;
5575 else
5576 min_freq = 337500;
5577
5578 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5579
5580 I915_WRITE(CDCLK_CTL, val);
5581 POSTING_READ(CDCLK_CTL);
5582
5583 /*
5584 * We always enable DPLL0 with the lowest link rate possible, but still
5585 * taking into account the VCO required to operate the eDP panel at the
5586 * desired frequency. The usual DP link rates operate with a VCO of
5587 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5588 * The modeset code is responsible for the selection of the exact link
5589 * rate later on, with the constraint of choosing a frequency that
5590 * works with required_vco.
5591 */
5592 val = I915_READ(DPLL_CTRL1);
5593
5594 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5595 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5596 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5597 if (required_vco == 8640)
5598 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5599 SKL_DPLL0);
5600 else
5601 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5602 SKL_DPLL0);
5603
5604 I915_WRITE(DPLL_CTRL1, val);
5605 POSTING_READ(DPLL_CTRL1);
5606
5607 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5608
5609 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5610 DRM_ERROR("DPLL0 not locked\n");
5611}
5612
5613static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5614{
5615 int ret;
5616 u32 val;
5617
5618 /* inform PCU we want to change CDCLK */
5619 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5620 mutex_lock(&dev_priv->rps.hw_lock);
5621 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5622 mutex_unlock(&dev_priv->rps.hw_lock);
5623
5624 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5625}
5626
5627static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5628{
5629 unsigned int i;
5630
5631 for (i = 0; i < 15; i++) {
5632 if (skl_cdclk_pcu_ready(dev_priv))
5633 return true;
5634 udelay(10);
5635 }
5636
5637 return false;
5638}
5639
5640static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5641{
5642 struct drm_device *dev = dev_priv->dev;
5643 u32 freq_select, pcu_ack;
5644
5645 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5646
5647 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5648 DRM_ERROR("failed to inform PCU about cdclk change\n");
5649 return;
5650 }
5651
5652 /* set CDCLK_CTL */
5653 switch(freq) {
5654 case 450000:
5655 case 432000:
5656 freq_select = CDCLK_FREQ_450_432;
5657 pcu_ack = 1;
5658 break;
5659 case 540000:
5660 freq_select = CDCLK_FREQ_540;
5661 pcu_ack = 2;
5662 break;
5663 case 308570:
5664 case 337500:
5665 default:
5666 freq_select = CDCLK_FREQ_337_308;
5667 pcu_ack = 0;
5668 break;
5669 case 617140:
5670 case 675000:
5671 freq_select = CDCLK_FREQ_675_617;
5672 pcu_ack = 3;
5673 break;
5674 }
5675
5676 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5677 POSTING_READ(CDCLK_CTL);
5678
5679 /* inform PCU of the change */
5680 mutex_lock(&dev_priv->rps.hw_lock);
5681 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5682 mutex_unlock(&dev_priv->rps.hw_lock);
5683
5684 intel_update_cdclk(dev);
5685}
5686
5687void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5688{
5689 /* disable DBUF power */
5690 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5691 POSTING_READ(DBUF_CTL);
5692
5693 udelay(10);
5694
5695 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5696 DRM_ERROR("DBuf power disable timeout\n");
5697
5698 /* disable DPLL0 */
5699 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5700 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5701 DRM_ERROR("Couldn't disable DPLL0\n");
5702
5703 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5704}
5705
5706void skl_init_cdclk(struct drm_i915_private *dev_priv)
5707{
5708 u32 val;
5709 unsigned int required_vco;
5710
5711 /* enable PCH reset handshake */
5712 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5713 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5714
5715 /* enable PG1 and Misc I/O */
5716 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5717
5718 /* DPLL0 not enabled (happens on early BIOS versions) */
5719 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5720 /* enable DPLL0 */
5721 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5722 skl_dpll0_enable(dev_priv, required_vco);
5723 }
5724
5725 /* set CDCLK to the frequency the BIOS chose */
5726 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5727
5728 /* enable DBUF power */
5729 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5730 POSTING_READ(DBUF_CTL);
5731
5732 udelay(10);
5733
5734 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5735 DRM_ERROR("DBuf power enable timeout\n");
5736}
5737
5738/* returns HPLL frequency in kHz */
5739static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5740{
5741 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5742
5743 /* Obtain SKU information */
5744 mutex_lock(&dev_priv->sb_lock);
5745 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5746 CCK_FUSE_HPLL_FREQ_MASK;
5747 mutex_unlock(&dev_priv->sb_lock);
5748
5749 return vco_freq[hpll_freq] * 1000;
5750}
5751
5752/* Adjust CDclk dividers to allow high res or save power if possible */
5753static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5754{
5755 struct drm_i915_private *dev_priv = dev->dev_private;
5756 u32 val, cmd;
5757
5758 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5759 != dev_priv->cdclk_freq);
5760
5761 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5762 cmd = 2;
5763 else if (cdclk == 266667)
5764 cmd = 1;
5765 else
5766 cmd = 0;
5767
5768 mutex_lock(&dev_priv->rps.hw_lock);
5769 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5770 val &= ~DSPFREQGUAR_MASK;
5771 val |= (cmd << DSPFREQGUAR_SHIFT);
5772 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5773 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5774 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5775 50)) {
5776 DRM_ERROR("timed out waiting for CDclk change\n");
5777 }
5778 mutex_unlock(&dev_priv->rps.hw_lock);
5779
5780 mutex_lock(&dev_priv->sb_lock);
5781
5782 if (cdclk == 400000) {
5783 u32 divider;
5784
5785 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5786
5787 /* adjust cdclk divider */
5788 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5789 val &= ~DISPLAY_FREQUENCY_VALUES;
5790 val |= divider;
5791 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5792
5793 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5794 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5795 50))
5796 DRM_ERROR("timed out waiting for CDclk change\n");
5797 }
5798
5799 /* adjust self-refresh exit latency value */
5800 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5801 val &= ~0x7f;
5802
5803 /*
5804 * For high bandwidth configs, we set a higher latency in the bunit
5805 * so that the core display fetch happens in time to avoid underruns.
5806 */
5807 if (cdclk == 400000)
5808 val |= 4500 / 250; /* 4.5 usec */
5809 else
5810 val |= 3000 / 250; /* 3.0 usec */
5811 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5812
5813 mutex_unlock(&dev_priv->sb_lock);
5814
5815 intel_update_cdclk(dev);
5816}
5817
5818static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5819{
5820 struct drm_i915_private *dev_priv = dev->dev_private;
5821 u32 val, cmd;
5822
5823 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5824 != dev_priv->cdclk_freq);
5825
5826 switch (cdclk) {
5827 case 333333:
5828 case 320000:
5829 case 266667:
5830 case 200000:
5831 break;
5832 default:
5833 MISSING_CASE(cdclk);
5834 return;
5835 }
5836
5837 /*
5838 * Specs are full of misinformation, but testing on actual
5839 * hardware has shown that we just need to write the desired
5840 * CCK divider into the Punit register.
5841 */
5842 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5843
5844 mutex_lock(&dev_priv->rps.hw_lock);
5845 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5846 val &= ~DSPFREQGUAR_MASK_CHV;
5847 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5848 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5849 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5850 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5851 50)) {
5852 DRM_ERROR("timed out waiting for CDclk change\n");
5853 }
5854 mutex_unlock(&dev_priv->rps.hw_lock);
5855
5856 intel_update_cdclk(dev);
5857}
5858
5859static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5860 int max_pixclk)
5861{
5862 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5863 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5864
5865 /*
5866 * Really only a few cases to deal with, as only 4 CDclks are supported:
5867 * 200MHz
5868 * 267MHz
5869 * 320/333MHz (depends on HPLL freq)
5870 * 400MHz (VLV only)
5871 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5872 * of the lower bin and adjust if needed.
5873 *
5874 * We seem to get an unstable or solid color picture at 200MHz.
5875 * Not sure what's wrong. For now use 200MHz only when all pipes
5876 * are off.
5877 */
5878 if (!IS_CHERRYVIEW(dev_priv) &&
5879 max_pixclk > freq_320*limit/100)
5880 return 400000;
5881 else if (max_pixclk > 266667*limit/100)
5882 return freq_320;
5883 else if (max_pixclk > 0)
5884 return 266667;
5885 else
5886 return 200000;
5887}
5888
5889static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5890 int max_pixclk)
5891{
5892 /*
5893 * FIXME:
5894 * - remove the guardband, it's not needed on BXT
5895 * - set 19.2MHz bypass frequency if there are no active pipes
5896 */
5897 if (max_pixclk > 576000*9/10)
5898 return 624000;
5899 else if (max_pixclk > 384000*9/10)
5900 return 576000;
5901 else if (max_pixclk > 288000*9/10)
5902 return 384000;
5903 else if (max_pixclk > 144000*9/10)
5904 return 288000;
5905 else
5906 return 144000;
5907}
5908
5909/* Compute the max pixel clock for new configuration. Uses atomic state if
5910 * that's non-NULL, look at current state otherwise. */
5911static int intel_mode_max_pixclk(struct drm_device *dev,
5912 struct drm_atomic_state *state)
5913{
5914 struct intel_crtc *intel_crtc;
5915 struct intel_crtc_state *crtc_state;
5916 int max_pixclk = 0;
5917
5918 for_each_intel_crtc(dev, intel_crtc) {
5919 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5920 if (IS_ERR(crtc_state))
5921 return PTR_ERR(crtc_state);
5922
5923 if (!crtc_state->base.enable)
5924 continue;
5925
5926 max_pixclk = max(max_pixclk,
5927 crtc_state->base.adjusted_mode.crtc_clock);
5928 }
5929
5930 return max_pixclk;
5931}
5932
5933static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5934{
5935 struct drm_device *dev = state->dev;
5936 struct drm_i915_private *dev_priv = dev->dev_private;
5937 int max_pixclk = intel_mode_max_pixclk(dev, state);
5938
5939 if (max_pixclk < 0)
5940 return max_pixclk;
5941
5942 to_intel_atomic_state(state)->cdclk =
5943 valleyview_calc_cdclk(dev_priv, max_pixclk);
5944
5945 return 0;
5946}
5947
5948static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5949{
5950 struct drm_device *dev = state->dev;
5951 struct drm_i915_private *dev_priv = dev->dev_private;
5952 int max_pixclk = intel_mode_max_pixclk(dev, state);
5953
5954 if (max_pixclk < 0)
5955 return max_pixclk;
5956
5957 to_intel_atomic_state(state)->cdclk =
5958 broxton_calc_cdclk(dev_priv, max_pixclk);
5959
5960 return 0;
5961}
5962
5963static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5964{
5965 unsigned int credits, default_credits;
5966
5967 if (IS_CHERRYVIEW(dev_priv))
5968 default_credits = PFI_CREDIT(12);
5969 else
5970 default_credits = PFI_CREDIT(8);
5971
5972 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5973 /* CHV suggested value is 31 or 63 */
5974 if (IS_CHERRYVIEW(dev_priv))
5975 credits = PFI_CREDIT_63;
5976 else
5977 credits = PFI_CREDIT(15);
5978 } else {
5979 credits = default_credits;
5980 }
5981
5982 /*
5983 * WA - write default credits before re-programming
5984 * FIXME: should we also set the resend bit here?
5985 */
5986 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5987 default_credits);
5988
5989 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5990 credits | PFI_CREDIT_RESEND);
5991
5992 /*
5993 * FIXME is this guaranteed to clear
5994 * immediately or should we poll for it?
5995 */
5996 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5997}
5998
5999static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6000{
6001 struct drm_device *dev = old_state->dev;
6002 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
6003 struct drm_i915_private *dev_priv = dev->dev_private;
6004
6005 /*
6006 * FIXME: We can end up here with all power domains off, yet
6007 * with a CDCLK frequency other than the minimum. To account
6008 * for this take the PIPE-A power domain, which covers the HW
6009 * blocks needed for the following programming. This can be
6010 * removed once it's guaranteed that we get here either with
6011 * the minimum CDCLK set, or the required power domains
6012 * enabled.
6013 */
6014 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6015
6016 if (IS_CHERRYVIEW(dev))
6017 cherryview_set_cdclk(dev, req_cdclk);
6018 else
6019 valleyview_set_cdclk(dev, req_cdclk);
6020
6021 vlv_program_pfi_credits(dev_priv);
6022
6023 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6024}
6025
6026static void valleyview_crtc_enable(struct drm_crtc *crtc)
6027{
6028 struct drm_device *dev = crtc->dev;
6029 struct drm_i915_private *dev_priv = to_i915(dev);
6030 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6031 struct intel_encoder *encoder;
6032 int pipe = intel_crtc->pipe;
6033 bool is_dsi;
6034
6035 if (WARN_ON(intel_crtc->active))
6036 return;
6037
6038 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6039
6040 if (!is_dsi) {
6041 if (IS_CHERRYVIEW(dev))
6042 chv_prepare_pll(intel_crtc, intel_crtc->config);
6043 else
6044 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6045 }
6046
6047 if (intel_crtc->config->has_dp_encoder)
6048 intel_dp_set_m_n(intel_crtc, M1_N1);
6049
6050 intel_set_pipe_timings(intel_crtc);
6051
6052 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6053 struct drm_i915_private *dev_priv = dev->dev_private;
6054
6055 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6056 I915_WRITE(CHV_CANVAS(pipe), 0);
6057 }
6058
6059 i9xx_set_pipeconf(intel_crtc);
6060
6061 intel_crtc->active = true;
6062
6063 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6064
6065 for_each_encoder_on_crtc(dev, crtc, encoder)
6066 if (encoder->pre_pll_enable)
6067 encoder->pre_pll_enable(encoder);
6068
6069 if (!is_dsi) {
6070 if (IS_CHERRYVIEW(dev))
6071 chv_enable_pll(intel_crtc, intel_crtc->config);
6072 else
6073 vlv_enable_pll(intel_crtc, intel_crtc->config);
6074 }
6075
6076 for_each_encoder_on_crtc(dev, crtc, encoder)
6077 if (encoder->pre_enable)
6078 encoder->pre_enable(encoder);
6079
6080 i9xx_pfit_enable(intel_crtc);
6081
6082 intel_crtc_load_lut(crtc);
6083
6084 intel_enable_pipe(intel_crtc);
6085
6086 assert_vblank_disabled(crtc);
6087 drm_crtc_vblank_on(crtc);
6088
6089 for_each_encoder_on_crtc(dev, crtc, encoder)
6090 encoder->enable(encoder);
6091}
6092
6093static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6094{
6095 struct drm_device *dev = crtc->base.dev;
6096 struct drm_i915_private *dev_priv = dev->dev_private;
6097
6098 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6099 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6100}
6101
6102static void i9xx_crtc_enable(struct drm_crtc *crtc)
6103{
6104 struct drm_device *dev = crtc->dev;
6105 struct drm_i915_private *dev_priv = to_i915(dev);
6106 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6107 struct intel_encoder *encoder;
6108 int pipe = intel_crtc->pipe;
6109
6110 if (WARN_ON(intel_crtc->active))
6111 return;
6112
6113 i9xx_set_pll_dividers(intel_crtc);
6114
6115 if (intel_crtc->config->has_dp_encoder)
6116 intel_dp_set_m_n(intel_crtc, M1_N1);
6117
6118 intel_set_pipe_timings(intel_crtc);
6119
6120 i9xx_set_pipeconf(intel_crtc);
6121
6122 intel_crtc->active = true;
6123
6124 if (!IS_GEN2(dev))
6125 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6126
6127 for_each_encoder_on_crtc(dev, crtc, encoder)
6128 if (encoder->pre_enable)
6129 encoder->pre_enable(encoder);
6130
6131 i9xx_enable_pll(intel_crtc);
6132
6133 i9xx_pfit_enable(intel_crtc);
6134
6135 intel_crtc_load_lut(crtc);
6136
6137 intel_update_watermarks(crtc);
6138 intel_enable_pipe(intel_crtc);
6139
6140 assert_vblank_disabled(crtc);
6141 drm_crtc_vblank_on(crtc);
6142
6143 for_each_encoder_on_crtc(dev, crtc, encoder)
6144 encoder->enable(encoder);
6145}
6146
6147static void i9xx_pfit_disable(struct intel_crtc *crtc)
6148{
6149 struct drm_device *dev = crtc->base.dev;
6150 struct drm_i915_private *dev_priv = dev->dev_private;
6151
6152 if (!crtc->config->gmch_pfit.control)
6153 return;
6154
6155 assert_pipe_disabled(dev_priv, crtc->pipe);
6156
6157 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6158 I915_READ(PFIT_CONTROL));
6159 I915_WRITE(PFIT_CONTROL, 0);
6160}
6161
6162static void i9xx_crtc_disable(struct drm_crtc *crtc)
6163{
6164 struct drm_device *dev = crtc->dev;
6165 struct drm_i915_private *dev_priv = dev->dev_private;
6166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6167 struct intel_encoder *encoder;
6168 int pipe = intel_crtc->pipe;
6169
6170 /*
6171 * On gen2 planes are double buffered but the pipe isn't, so we must
6172 * wait for planes to fully turn off before disabling the pipe.
6173 * We also need to wait on all gmch platforms because of the
6174 * self-refresh mode constraint explained above.
6175 */
6176 intel_wait_for_vblank(dev, pipe);
6177
6178 for_each_encoder_on_crtc(dev, crtc, encoder)
6179 encoder->disable(encoder);
6180
6181 drm_crtc_vblank_off(crtc);
6182 assert_vblank_disabled(crtc);
6183
6184 intel_disable_pipe(intel_crtc);
6185
6186 i9xx_pfit_disable(intel_crtc);
6187
6188 for_each_encoder_on_crtc(dev, crtc, encoder)
6189 if (encoder->post_disable)
6190 encoder->post_disable(encoder);
6191
6192 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6193 if (IS_CHERRYVIEW(dev))
6194 chv_disable_pll(dev_priv, pipe);
6195 else if (IS_VALLEYVIEW(dev))
6196 vlv_disable_pll(dev_priv, pipe);
6197 else
6198 i9xx_disable_pll(intel_crtc);
6199 }
6200
6201 if (!IS_GEN2(dev))
6202 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6203
6204 intel_crtc->active = false;
6205 intel_update_watermarks(crtc);
6206}
6207
6208static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6209{
6210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6211 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6212 enum intel_display_power_domain domain;
6213 unsigned long domains;
6214
6215 if (!intel_crtc->active)
6216 return;
6217
6218 if (to_intel_plane_state(crtc->primary->state)->visible) {
6219 intel_crtc_wait_for_pending_flips(crtc);
6220 intel_pre_disable_primary(crtc);
6221 }
6222
6223 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6224 dev_priv->display.crtc_disable(crtc);
6225 intel_disable_shared_dpll(intel_crtc);
6226
6227 domains = intel_crtc->enabled_power_domains;
6228 for_each_power_domain(domain, domains)
6229 intel_display_power_put(dev_priv, domain);
6230 intel_crtc->enabled_power_domains = 0;
6231}
6232
6233/*
6234 * turn all crtc's off, but do not adjust state
6235 * This has to be paired with a call to intel_modeset_setup_hw_state.
6236 */
6237int intel_display_suspend(struct drm_device *dev)
6238{
6239 struct drm_mode_config *config = &dev->mode_config;
6240 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6241 struct drm_atomic_state *state;
6242 struct drm_crtc *crtc;
6243 unsigned crtc_mask = 0;
6244 int ret = 0;
6245
6246 if (WARN_ON(!ctx))
6247 return 0;
6248
6249 lockdep_assert_held(&ctx->ww_ctx);
6250 state = drm_atomic_state_alloc(dev);
6251 if (WARN_ON(!state))
6252 return -ENOMEM;
6253
6254 state->acquire_ctx = ctx;
6255 state->allow_modeset = true;
6256
6257 for_each_crtc(dev, crtc) {
6258 struct drm_crtc_state *crtc_state =
6259 drm_atomic_get_crtc_state(state, crtc);
6260
6261 ret = PTR_ERR_OR_ZERO(crtc_state);
6262 if (ret)
6263 goto free;
6264
6265 if (!crtc_state->active)
6266 continue;
6267
6268 crtc_state->active = false;
6269 crtc_mask |= 1 << drm_crtc_index(crtc);
6270 }
6271
6272 if (crtc_mask) {
6273 ret = drm_atomic_commit(state);
6274
6275 if (!ret) {
6276 for_each_crtc(dev, crtc)
6277 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6278 crtc->state->active = true;
6279
6280 return ret;
6281 }
6282 }
6283
6284free:
6285 if (ret)
6286 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6287 drm_atomic_state_free(state);
6288 return ret;
6289}
6290
6291void intel_encoder_destroy(struct drm_encoder *encoder)
6292{
6293 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6294
6295 drm_encoder_cleanup(encoder);
6296 kfree(intel_encoder);
6297}
6298
6299/* Cross check the actual hw state with our own modeset state tracking (and it's
6300 * internal consistency). */
6301static void intel_connector_check_state(struct intel_connector *connector)
6302{
6303 struct drm_crtc *crtc = connector->base.state->crtc;
6304
6305 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6306 connector->base.base.id,
6307 connector->base.name);
6308
6309 if (connector->get_hw_state(connector)) {
6310 struct intel_encoder *encoder = connector->encoder;
6311 struct drm_connector_state *conn_state = connector->base.state;
6312
6313 I915_STATE_WARN(!crtc,
6314 "connector enabled without attached crtc\n");
6315
6316 if (!crtc)
6317 return;
6318
6319 I915_STATE_WARN(!crtc->state->active,
6320 "connector is active, but attached crtc isn't\n");
6321
6322 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6323 return;
6324
6325 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6326 "atomic encoder doesn't match attached encoder\n");
6327
6328 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6329 "attached encoder crtc differs from connector crtc\n");
6330 } else {
6331 I915_STATE_WARN(crtc && crtc->state->active,
6332 "attached crtc is active, but connector isn't\n");
6333 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6334 "best encoder set without crtc!\n");
6335 }
6336}
6337
6338int intel_connector_init(struct intel_connector *connector)
6339{
6340 struct drm_connector_state *connector_state;
6341
6342 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6343 if (!connector_state)
6344 return -ENOMEM;
6345
6346 connector->base.state = connector_state;
6347 return 0;
6348}
6349
6350struct intel_connector *intel_connector_alloc(void)
6351{
6352 struct intel_connector *connector;
6353
6354 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6355 if (!connector)
6356 return NULL;
6357
6358 if (intel_connector_init(connector) < 0) {
6359 kfree(connector);
6360 return NULL;
6361 }
6362
6363 return connector;
6364}
6365
6366/* Simple connector->get_hw_state implementation for encoders that support only
6367 * one connector and no cloning and hence the encoder state determines the state
6368 * of the connector. */
6369bool intel_connector_get_hw_state(struct intel_connector *connector)
6370{
6371 enum pipe pipe = 0;
6372 struct intel_encoder *encoder = connector->encoder;
6373
6374 return encoder->get_hw_state(encoder, &pipe);
6375}
6376
6377static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6378{
6379 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6380 return crtc_state->fdi_lanes;
6381
6382 return 0;
6383}
6384
6385static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6386 struct intel_crtc_state *pipe_config)
6387{
6388 struct drm_atomic_state *state = pipe_config->base.state;
6389 struct intel_crtc *other_crtc;
6390 struct intel_crtc_state *other_crtc_state;
6391
6392 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6393 pipe_name(pipe), pipe_config->fdi_lanes);
6394 if (pipe_config->fdi_lanes > 4) {
6395 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6396 pipe_name(pipe), pipe_config->fdi_lanes);
6397 return -EINVAL;
6398 }
6399
6400 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6401 if (pipe_config->fdi_lanes > 2) {
6402 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6403 pipe_config->fdi_lanes);
6404 return -EINVAL;
6405 } else {
6406 return 0;
6407 }
6408 }
6409
6410 if (INTEL_INFO(dev)->num_pipes == 2)
6411 return 0;
6412
6413 /* Ivybridge 3 pipe is really complicated */
6414 switch (pipe) {
6415 case PIPE_A:
6416 return 0;
6417 case PIPE_B:
6418 if (pipe_config->fdi_lanes <= 2)
6419 return 0;
6420
6421 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6422 other_crtc_state =
6423 intel_atomic_get_crtc_state(state, other_crtc);
6424 if (IS_ERR(other_crtc_state))
6425 return PTR_ERR(other_crtc_state);
6426
6427 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6428 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6429 pipe_name(pipe), pipe_config->fdi_lanes);
6430 return -EINVAL;
6431 }
6432 return 0;
6433 case PIPE_C:
6434 if (pipe_config->fdi_lanes > 2) {
6435 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6436 pipe_name(pipe), pipe_config->fdi_lanes);
6437 return -EINVAL;
6438 }
6439
6440 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6441 other_crtc_state =
6442 intel_atomic_get_crtc_state(state, other_crtc);
6443 if (IS_ERR(other_crtc_state))
6444 return PTR_ERR(other_crtc_state);
6445
6446 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6447 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6448 return -EINVAL;
6449 }
6450 return 0;
6451 default:
6452 BUG();
6453 }
6454}
6455
6456#define RETRY 1
6457static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6458 struct intel_crtc_state *pipe_config)
6459{
6460 struct drm_device *dev = intel_crtc->base.dev;
6461 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6462 int lane, link_bw, fdi_dotclock, ret;
6463 bool needs_recompute = false;
6464
6465retry:
6466 /* FDI is a binary signal running at ~2.7GHz, encoding
6467 * each output octet as 10 bits. The actual frequency
6468 * is stored as a divider into a 100MHz clock, and the
6469 * mode pixel clock is stored in units of 1KHz.
6470 * Hence the bw of each lane in terms of the mode signal
6471 * is:
6472 */
6473 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6474
6475 fdi_dotclock = adjusted_mode->crtc_clock;
6476
6477 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6478 pipe_config->pipe_bpp);
6479
6480 pipe_config->fdi_lanes = lane;
6481
6482 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6483 link_bw, &pipe_config->fdi_m_n);
6484
6485 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6486 intel_crtc->pipe, pipe_config);
6487 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6488 pipe_config->pipe_bpp -= 2*3;
6489 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6490 pipe_config->pipe_bpp);
6491 needs_recompute = true;
6492 pipe_config->bw_constrained = true;
6493
6494 goto retry;
6495 }
6496
6497 if (needs_recompute)
6498 return RETRY;
6499
6500 return ret;
6501}
6502
6503static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6504 struct intel_crtc_state *pipe_config)
6505{
6506 if (pipe_config->pipe_bpp > 24)
6507 return false;
6508
6509 /* HSW can handle pixel rate up to cdclk? */
6510 if (IS_HASWELL(dev_priv->dev))
6511 return true;
6512
6513 /*
6514 * We compare against max which means we must take
6515 * the increased cdclk requirement into account when
6516 * calculating the new cdclk.
6517 *
6518 * Should measure whether using a lower cdclk w/o IPS
6519 */
6520 return ilk_pipe_pixel_rate(pipe_config) <=
6521 dev_priv->max_cdclk_freq * 95 / 100;
6522}
6523
6524static void hsw_compute_ips_config(struct intel_crtc *crtc,
6525 struct intel_crtc_state *pipe_config)
6526{
6527 struct drm_device *dev = crtc->base.dev;
6528 struct drm_i915_private *dev_priv = dev->dev_private;
6529
6530 pipe_config->ips_enabled = i915.enable_ips &&
6531 hsw_crtc_supports_ips(crtc) &&
6532 pipe_config_supports_ips(dev_priv, pipe_config);
6533}
6534
6535static int intel_crtc_compute_config(struct intel_crtc *crtc,
6536 struct intel_crtc_state *pipe_config)
6537{
6538 struct drm_device *dev = crtc->base.dev;
6539 struct drm_i915_private *dev_priv = dev->dev_private;
6540 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6541
6542 /* FIXME should check pixel clock limits on all platforms */
6543 if (INTEL_INFO(dev)->gen < 4) {
6544 int clock_limit = dev_priv->max_cdclk_freq;
6545
6546 /*
6547 * Enable pixel doubling when the dot clock
6548 * is > 90% of the (display) core speed.
6549 *
6550 * GDG double wide on either pipe,
6551 * otherwise pipe A only.
6552 */
6553 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6554 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6555 clock_limit *= 2;
6556 pipe_config->double_wide = true;
6557 }
6558
6559 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6560 return -EINVAL;
6561 }
6562
6563 /*
6564 * Pipe horizontal size must be even in:
6565 * - DVO ganged mode
6566 * - LVDS dual channel mode
6567 * - Double wide pipe
6568 */
6569 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6570 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6571 pipe_config->pipe_src_w &= ~1;
6572
6573 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6574 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6575 */
6576 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6577 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6578 return -EINVAL;
6579
6580 if (HAS_IPS(dev))
6581 hsw_compute_ips_config(crtc, pipe_config);
6582
6583 if (pipe_config->has_pch_encoder)
6584 return ironlake_fdi_compute_config(crtc, pipe_config);
6585
6586 return 0;
6587}
6588
6589static int skylake_get_display_clock_speed(struct drm_device *dev)
6590{
6591 struct drm_i915_private *dev_priv = to_i915(dev);
6592 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6593 uint32_t cdctl = I915_READ(CDCLK_CTL);
6594 uint32_t linkrate;
6595
6596 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6597 return 24000; /* 24MHz is the cd freq with NSSC ref */
6598
6599 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6600 return 540000;
6601
6602 linkrate = (I915_READ(DPLL_CTRL1) &
6603 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6604
6605 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6606 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6607 /* vco 8640 */
6608 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6609 case CDCLK_FREQ_450_432:
6610 return 432000;
6611 case CDCLK_FREQ_337_308:
6612 return 308570;
6613 case CDCLK_FREQ_675_617:
6614 return 617140;
6615 default:
6616 WARN(1, "Unknown cd freq selection\n");
6617 }
6618 } else {
6619 /* vco 8100 */
6620 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6621 case CDCLK_FREQ_450_432:
6622 return 450000;
6623 case CDCLK_FREQ_337_308:
6624 return 337500;
6625 case CDCLK_FREQ_675_617:
6626 return 675000;
6627 default:
6628 WARN(1, "Unknown cd freq selection\n");
6629 }
6630 }
6631
6632 /* error case, do as if DPLL0 isn't enabled */
6633 return 24000;
6634}
6635
6636static int broxton_get_display_clock_speed(struct drm_device *dev)
6637{
6638 struct drm_i915_private *dev_priv = to_i915(dev);
6639 uint32_t cdctl = I915_READ(CDCLK_CTL);
6640 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6641 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6642 int cdclk;
6643
6644 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6645 return 19200;
6646
6647 cdclk = 19200 * pll_ratio / 2;
6648
6649 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6650 case BXT_CDCLK_CD2X_DIV_SEL_1:
6651 return cdclk; /* 576MHz or 624MHz */
6652 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6653 return cdclk * 2 / 3; /* 384MHz */
6654 case BXT_CDCLK_CD2X_DIV_SEL_2:
6655 return cdclk / 2; /* 288MHz */
6656 case BXT_CDCLK_CD2X_DIV_SEL_4:
6657 return cdclk / 4; /* 144MHz */
6658 }
6659
6660 /* error case, do as if DE PLL isn't enabled */
6661 return 19200;
6662}
6663
6664static int broadwell_get_display_clock_speed(struct drm_device *dev)
6665{
6666 struct drm_i915_private *dev_priv = dev->dev_private;
6667 uint32_t lcpll = I915_READ(LCPLL_CTL);
6668 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6669
6670 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6671 return 800000;
6672 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6673 return 450000;
6674 else if (freq == LCPLL_CLK_FREQ_450)
6675 return 450000;
6676 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6677 return 540000;
6678 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6679 return 337500;
6680 else
6681 return 675000;
6682}
6683
6684static int haswell_get_display_clock_speed(struct drm_device *dev)
6685{
6686 struct drm_i915_private *dev_priv = dev->dev_private;
6687 uint32_t lcpll = I915_READ(LCPLL_CTL);
6688 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6689
6690 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6691 return 800000;
6692 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6693 return 450000;
6694 else if (freq == LCPLL_CLK_FREQ_450)
6695 return 450000;
6696 else if (IS_HSW_ULT(dev))
6697 return 337500;
6698 else
6699 return 540000;
6700}
6701
6702static int valleyview_get_display_clock_speed(struct drm_device *dev)
6703{
6704 struct drm_i915_private *dev_priv = dev->dev_private;
6705 u32 val;
6706 int divider;
6707
6708 if (dev_priv->hpll_freq == 0)
6709 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6710
6711 mutex_lock(&dev_priv->sb_lock);
6712 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6713 mutex_unlock(&dev_priv->sb_lock);
6714
6715 divider = val & DISPLAY_FREQUENCY_VALUES;
6716
6717 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6718 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6719 "cdclk change in progress\n");
6720
6721 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6722}
6723
6724static int ilk_get_display_clock_speed(struct drm_device *dev)
6725{
6726 return 450000;
6727}
6728
6729static int i945_get_display_clock_speed(struct drm_device *dev)
6730{
6731 return 400000;
6732}
6733
6734static int i915_get_display_clock_speed(struct drm_device *dev)
6735{
6736 return 333333;
6737}
6738
6739static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6740{
6741 return 200000;
6742}
6743
6744static int pnv_get_display_clock_speed(struct drm_device *dev)
6745{
6746 u16 gcfgc = 0;
6747
6748 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6749
6750 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6751 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6752 return 266667;
6753 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6754 return 333333;
6755 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6756 return 444444;
6757 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6758 return 200000;
6759 default:
6760 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6761 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6762 return 133333;
6763 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6764 return 166667;
6765 }
6766}
6767
6768static int i915gm_get_display_clock_speed(struct drm_device *dev)
6769{
6770 u16 gcfgc = 0;
6771
6772 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6773
6774 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6775 return 133333;
6776 else {
6777 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6778 case GC_DISPLAY_CLOCK_333_MHZ:
6779 return 333333;
6780 default:
6781 case GC_DISPLAY_CLOCK_190_200_MHZ:
6782 return 190000;
6783 }
6784 }
6785}
6786
6787static int i865_get_display_clock_speed(struct drm_device *dev)
6788{
6789 return 266667;
6790}
6791
6792static int i85x_get_display_clock_speed(struct drm_device *dev)
6793{
6794 u16 hpllcc = 0;
6795
6796 /*
6797 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6798 * encoding is different :(
6799 * FIXME is this the right way to detect 852GM/852GMV?
6800 */
6801 if (dev->pdev->revision == 0x1)
6802 return 133333;
6803
6804 pci_bus_read_config_word(dev->pdev->bus,
6805 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6806
6807 /* Assume that the hardware is in the high speed state. This
6808 * should be the default.
6809 */
6810 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6811 case GC_CLOCK_133_200:
6812 case GC_CLOCK_133_200_2:
6813 case GC_CLOCK_100_200:
6814 return 200000;
6815 case GC_CLOCK_166_250:
6816 return 250000;
6817 case GC_CLOCK_100_133:
6818 return 133333;
6819 case GC_CLOCK_133_266:
6820 case GC_CLOCK_133_266_2:
6821 case GC_CLOCK_166_266:
6822 return 266667;
6823 }
6824
6825 /* Shouldn't happen */
6826 return 0;
6827}
6828
6829static int i830_get_display_clock_speed(struct drm_device *dev)
6830{
6831 return 133333;
6832}
6833
6834static unsigned int intel_hpll_vco(struct drm_device *dev)
6835{
6836 struct drm_i915_private *dev_priv = dev->dev_private;
6837 static const unsigned int blb_vco[8] = {
6838 [0] = 3200000,
6839 [1] = 4000000,
6840 [2] = 5333333,
6841 [3] = 4800000,
6842 [4] = 6400000,
6843 };
6844 static const unsigned int pnv_vco[8] = {
6845 [0] = 3200000,
6846 [1] = 4000000,
6847 [2] = 5333333,
6848 [3] = 4800000,
6849 [4] = 2666667,
6850 };
6851 static const unsigned int cl_vco[8] = {
6852 [0] = 3200000,
6853 [1] = 4000000,
6854 [2] = 5333333,
6855 [3] = 6400000,
6856 [4] = 3333333,
6857 [5] = 3566667,
6858 [6] = 4266667,
6859 };
6860 static const unsigned int elk_vco[8] = {
6861 [0] = 3200000,
6862 [1] = 4000000,
6863 [2] = 5333333,
6864 [3] = 4800000,
6865 };
6866 static const unsigned int ctg_vco[8] = {
6867 [0] = 3200000,
6868 [1] = 4000000,
6869 [2] = 5333333,
6870 [3] = 6400000,
6871 [4] = 2666667,
6872 [5] = 4266667,
6873 };
6874 const unsigned int *vco_table;
6875 unsigned int vco;
6876 uint8_t tmp = 0;
6877
6878 /* FIXME other chipsets? */
6879 if (IS_GM45(dev))
6880 vco_table = ctg_vco;
6881 else if (IS_G4X(dev))
6882 vco_table = elk_vco;
6883 else if (IS_CRESTLINE(dev))
6884 vco_table = cl_vco;
6885 else if (IS_PINEVIEW(dev))
6886 vco_table = pnv_vco;
6887 else if (IS_G33(dev))
6888 vco_table = blb_vco;
6889 else
6890 return 0;
6891
6892 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6893
6894 vco = vco_table[tmp & 0x7];
6895 if (vco == 0)
6896 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6897 else
6898 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6899
6900 return vco;
6901}
6902
6903static int gm45_get_display_clock_speed(struct drm_device *dev)
6904{
6905 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6906 uint16_t tmp = 0;
6907
6908 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6909
6910 cdclk_sel = (tmp >> 12) & 0x1;
6911
6912 switch (vco) {
6913 case 2666667:
6914 case 4000000:
6915 case 5333333:
6916 return cdclk_sel ? 333333 : 222222;
6917 case 3200000:
6918 return cdclk_sel ? 320000 : 228571;
6919 default:
6920 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6921 return 222222;
6922 }
6923}
6924
6925static int i965gm_get_display_clock_speed(struct drm_device *dev)
6926{
6927 static const uint8_t div_3200[] = { 16, 10, 8 };
6928 static const uint8_t div_4000[] = { 20, 12, 10 };
6929 static const uint8_t div_5333[] = { 24, 16, 14 };
6930 const uint8_t *div_table;
6931 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6932 uint16_t tmp = 0;
6933
6934 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6935
6936 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6937
6938 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6939 goto fail;
6940
6941 switch (vco) {
6942 case 3200000:
6943 div_table = div_3200;
6944 break;
6945 case 4000000:
6946 div_table = div_4000;
6947 break;
6948 case 5333333:
6949 div_table = div_5333;
6950 break;
6951 default:
6952 goto fail;
6953 }
6954
6955 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6956
6957fail:
6958 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6959 return 200000;
6960}
6961
6962static int g33_get_display_clock_speed(struct drm_device *dev)
6963{
6964 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6965 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6966 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6967 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6968 const uint8_t *div_table;
6969 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6970 uint16_t tmp = 0;
6971
6972 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6973
6974 cdclk_sel = (tmp >> 4) & 0x7;
6975
6976 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6977 goto fail;
6978
6979 switch (vco) {
6980 case 3200000:
6981 div_table = div_3200;
6982 break;
6983 case 4000000:
6984 div_table = div_4000;
6985 break;
6986 case 4800000:
6987 div_table = div_4800;
6988 break;
6989 case 5333333:
6990 div_table = div_5333;
6991 break;
6992 default:
6993 goto fail;
6994 }
6995
6996 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6997
6998fail:
6999 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7000 return 190476;
7001}
7002
7003static void
7004intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7005{
7006 while (*num > DATA_LINK_M_N_MASK ||
7007 *den > DATA_LINK_M_N_MASK) {
7008 *num >>= 1;
7009 *den >>= 1;
7010 }
7011}
7012
7013static void compute_m_n(unsigned int m, unsigned int n,
7014 uint32_t *ret_m, uint32_t *ret_n)
7015{
7016 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7017 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7018 intel_reduce_m_n_ratio(ret_m, ret_n);
7019}
7020
7021void
7022intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7023 int pixel_clock, int link_clock,
7024 struct intel_link_m_n *m_n)
7025{
7026 m_n->tu = 64;
7027
7028 compute_m_n(bits_per_pixel * pixel_clock,
7029 link_clock * nlanes * 8,
7030 &m_n->gmch_m, &m_n->gmch_n);
7031
7032 compute_m_n(pixel_clock, link_clock,
7033 &m_n->link_m, &m_n->link_n);
7034}
7035
7036static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7037{
7038 if (i915.panel_use_ssc >= 0)
7039 return i915.panel_use_ssc != 0;
7040 return dev_priv->vbt.lvds_use_ssc
7041 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7042}
7043
7044static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7045 int num_connectors)
7046{
7047 struct drm_device *dev = crtc_state->base.crtc->dev;
7048 struct drm_i915_private *dev_priv = dev->dev_private;
7049 int refclk;
7050
7051 WARN_ON(!crtc_state->base.state);
7052
7053 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7054 refclk = 100000;
7055 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7056 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7057 refclk = dev_priv->vbt.lvds_ssc_freq;
7058 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7059 } else if (!IS_GEN2(dev)) {
7060 refclk = 96000;
7061 } else {
7062 refclk = 48000;
7063 }
7064
7065 return refclk;
7066}
7067
7068static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7069{
7070 return (1 << dpll->n) << 16 | dpll->m2;
7071}
7072
7073static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7074{
7075 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7076}
7077
7078static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7079 struct intel_crtc_state *crtc_state,
7080 intel_clock_t *reduced_clock)
7081{
7082 struct drm_device *dev = crtc->base.dev;
7083 u32 fp, fp2 = 0;
7084
7085 if (IS_PINEVIEW(dev)) {
7086 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7087 if (reduced_clock)
7088 fp2 = pnv_dpll_compute_fp(reduced_clock);
7089 } else {
7090 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7091 if (reduced_clock)
7092 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7093 }
7094
7095 crtc_state->dpll_hw_state.fp0 = fp;
7096
7097 crtc->lowfreq_avail = false;
7098 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7099 reduced_clock) {
7100 crtc_state->dpll_hw_state.fp1 = fp2;
7101 crtc->lowfreq_avail = true;
7102 } else {
7103 crtc_state->dpll_hw_state.fp1 = fp;
7104 }
7105}
7106
7107static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7108 pipe)
7109{
7110 u32 reg_val;
7111
7112 /*
7113 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7114 * and set it to a reasonable value instead.
7115 */
7116 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7117 reg_val &= 0xffffff00;
7118 reg_val |= 0x00000030;
7119 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7120
7121 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7122 reg_val &= 0x8cffffff;
7123 reg_val = 0x8c000000;
7124 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7125
7126 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7127 reg_val &= 0xffffff00;
7128 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7129
7130 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7131 reg_val &= 0x00ffffff;
7132 reg_val |= 0xb0000000;
7133 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7134}
7135
7136static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7137 struct intel_link_m_n *m_n)
7138{
7139 struct drm_device *dev = crtc->base.dev;
7140 struct drm_i915_private *dev_priv = dev->dev_private;
7141 int pipe = crtc->pipe;
7142
7143 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7144 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7145 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7146 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7147}
7148
7149static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7150 struct intel_link_m_n *m_n,
7151 struct intel_link_m_n *m2_n2)
7152{
7153 struct drm_device *dev = crtc->base.dev;
7154 struct drm_i915_private *dev_priv = dev->dev_private;
7155 int pipe = crtc->pipe;
7156 enum transcoder transcoder = crtc->config->cpu_transcoder;
7157
7158 if (INTEL_INFO(dev)->gen >= 5) {
7159 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7160 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7161 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7162 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7163 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7164 * for gen < 8) and if DRRS is supported (to make sure the
7165 * registers are not unnecessarily accessed).
7166 */
7167 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7168 crtc->config->has_drrs) {
7169 I915_WRITE(PIPE_DATA_M2(transcoder),
7170 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7171 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7172 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7173 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7174 }
7175 } else {
7176 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7177 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7178 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7179 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7180 }
7181}
7182
7183void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7184{
7185 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7186
7187 if (m_n == M1_N1) {
7188 dp_m_n = &crtc->config->dp_m_n;
7189 dp_m2_n2 = &crtc->config->dp_m2_n2;
7190 } else if (m_n == M2_N2) {
7191
7192 /*
7193 * M2_N2 registers are not supported. Hence m2_n2 divider value
7194 * needs to be programmed into M1_N1.
7195 */
7196 dp_m_n = &crtc->config->dp_m2_n2;
7197 } else {
7198 DRM_ERROR("Unsupported divider value\n");
7199 return;
7200 }
7201
7202 if (crtc->config->has_pch_encoder)
7203 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7204 else
7205 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7206}
7207
7208static void vlv_compute_dpll(struct intel_crtc *crtc,
7209 struct intel_crtc_state *pipe_config)
7210{
7211 u32 dpll, dpll_md;
7212
7213 /*
7214 * Enable DPIO clock input. We should never disable the reference
7215 * clock for pipe B, since VGA hotplug / manual detection depends
7216 * on it.
7217 */
7218 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7219 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7220 /* We should never disable this, set it here for state tracking */
7221 if (crtc->pipe == PIPE_B)
7222 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7223 dpll |= DPLL_VCO_ENABLE;
7224 pipe_config->dpll_hw_state.dpll = dpll;
7225
7226 dpll_md = (pipe_config->pixel_multiplier - 1)
7227 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7228 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7229}
7230
7231static void vlv_prepare_pll(struct intel_crtc *crtc,
7232 const struct intel_crtc_state *pipe_config)
7233{
7234 struct drm_device *dev = crtc->base.dev;
7235 struct drm_i915_private *dev_priv = dev->dev_private;
7236 int pipe = crtc->pipe;
7237 u32 mdiv;
7238 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7239 u32 coreclk, reg_val;
7240
7241 mutex_lock(&dev_priv->sb_lock);
7242
7243 bestn = pipe_config->dpll.n;
7244 bestm1 = pipe_config->dpll.m1;
7245 bestm2 = pipe_config->dpll.m2;
7246 bestp1 = pipe_config->dpll.p1;
7247 bestp2 = pipe_config->dpll.p2;
7248
7249 /* See eDP HDMI DPIO driver vbios notes doc */
7250
7251 /* PLL B needs special handling */
7252 if (pipe == PIPE_B)
7253 vlv_pllb_recal_opamp(dev_priv, pipe);
7254
7255 /* Set up Tx target for periodic Rcomp update */
7256 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7257
7258 /* Disable target IRef on PLL */
7259 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7260 reg_val &= 0x00ffffff;
7261 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7262
7263 /* Disable fast lock */
7264 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7265
7266 /* Set idtafcrecal before PLL is enabled */
7267 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7268 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7269 mdiv |= ((bestn << DPIO_N_SHIFT));
7270 mdiv |= (1 << DPIO_K_SHIFT);
7271
7272 /*
7273 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7274 * but we don't support that).
7275 * Note: don't use the DAC post divider as it seems unstable.
7276 */
7277 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7278 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7279
7280 mdiv |= DPIO_ENABLE_CALIBRATION;
7281 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7282
7283 /* Set HBR and RBR LPF coefficients */
7284 if (pipe_config->port_clock == 162000 ||
7285 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7286 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7287 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7288 0x009f0003);
7289 else
7290 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7291 0x00d0000f);
7292
7293 if (pipe_config->has_dp_encoder) {
7294 /* Use SSC source */
7295 if (pipe == PIPE_A)
7296 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7297 0x0df40000);
7298 else
7299 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7300 0x0df70000);
7301 } else { /* HDMI or VGA */
7302 /* Use bend source */
7303 if (pipe == PIPE_A)
7304 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7305 0x0df70000);
7306 else
7307 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7308 0x0df40000);
7309 }
7310
7311 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7312 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7313 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7314 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7315 coreclk |= 0x01000000;
7316 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7317
7318 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7319 mutex_unlock(&dev_priv->sb_lock);
7320}
7321
7322static void chv_compute_dpll(struct intel_crtc *crtc,
7323 struct intel_crtc_state *pipe_config)
7324{
7325 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7326 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7327 DPLL_VCO_ENABLE;
7328 if (crtc->pipe != PIPE_A)
7329 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7330
7331 pipe_config->dpll_hw_state.dpll_md =
7332 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7333}
7334
7335static void chv_prepare_pll(struct intel_crtc *crtc,
7336 const struct intel_crtc_state *pipe_config)
7337{
7338 struct drm_device *dev = crtc->base.dev;
7339 struct drm_i915_private *dev_priv = dev->dev_private;
7340 int pipe = crtc->pipe;
7341 int dpll_reg = DPLL(crtc->pipe);
7342 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7343 u32 loopfilter, tribuf_calcntr;
7344 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7345 u32 dpio_val;
7346 int vco;
7347
7348 bestn = pipe_config->dpll.n;
7349 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7350 bestm1 = pipe_config->dpll.m1;
7351 bestm2 = pipe_config->dpll.m2 >> 22;
7352 bestp1 = pipe_config->dpll.p1;
7353 bestp2 = pipe_config->dpll.p2;
7354 vco = pipe_config->dpll.vco;
7355 dpio_val = 0;
7356 loopfilter = 0;
7357
7358 /*
7359 * Enable Refclk and SSC
7360 */
7361 I915_WRITE(dpll_reg,
7362 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7363
7364 mutex_lock(&dev_priv->sb_lock);
7365
7366 /* p1 and p2 divider */
7367 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7368 5 << DPIO_CHV_S1_DIV_SHIFT |
7369 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7370 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7371 1 << DPIO_CHV_K_DIV_SHIFT);
7372
7373 /* Feedback post-divider - m2 */
7374 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7375
7376 /* Feedback refclk divider - n and m1 */
7377 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7378 DPIO_CHV_M1_DIV_BY_2 |
7379 1 << DPIO_CHV_N_DIV_SHIFT);
7380
7381 /* M2 fraction division */
7382 if (bestm2_frac)
7383 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7384
7385 /* M2 fraction division enable */
7386 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7387 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7388 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7389 if (bestm2_frac)
7390 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7391 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7392
7393 /* Program digital lock detect threshold */
7394 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7395 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7396 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7397 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7398 if (!bestm2_frac)
7399 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7400 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7401
7402 /* Loop filter */
7403 if (vco == 5400000) {
7404 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7405 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7406 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7407 tribuf_calcntr = 0x9;
7408 } else if (vco <= 6200000) {
7409 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7410 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7411 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7412 tribuf_calcntr = 0x9;
7413 } else if (vco <= 6480000) {
7414 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7415 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7416 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7417 tribuf_calcntr = 0x8;
7418 } else {
7419 /* Not supported. Apply the same limits as in the max case */
7420 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7421 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7422 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7423 tribuf_calcntr = 0;
7424 }
7425 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7426
7427 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7428 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7429 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7430 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7431
7432 /* AFC Recal */
7433 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7434 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7435 DPIO_AFC_RECAL);
7436
7437 mutex_unlock(&dev_priv->sb_lock);
7438}
7439
7440/**
7441 * vlv_force_pll_on - forcibly enable just the PLL
7442 * @dev_priv: i915 private structure
7443 * @pipe: pipe PLL to enable
7444 * @dpll: PLL configuration
7445 *
7446 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7447 * in cases where we need the PLL enabled even when @pipe is not going to
7448 * be enabled.
7449 */
7450void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7451 const struct dpll *dpll)
7452{
7453 struct intel_crtc *crtc =
7454 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7455 struct intel_crtc_state pipe_config = {
7456 .base.crtc = &crtc->base,
7457 .pixel_multiplier = 1,
7458 .dpll = *dpll,
7459 };
7460
7461 if (IS_CHERRYVIEW(dev)) {
7462 chv_compute_dpll(crtc, &pipe_config);
7463 chv_prepare_pll(crtc, &pipe_config);
7464 chv_enable_pll(crtc, &pipe_config);
7465 } else {
7466 vlv_compute_dpll(crtc, &pipe_config);
7467 vlv_prepare_pll(crtc, &pipe_config);
7468 vlv_enable_pll(crtc, &pipe_config);
7469 }
7470}
7471
7472/**
7473 * vlv_force_pll_off - forcibly disable just the PLL
7474 * @dev_priv: i915 private structure
7475 * @pipe: pipe PLL to disable
7476 *
7477 * Disable the PLL for @pipe. To be used in cases where we need
7478 * the PLL enabled even when @pipe is not going to be enabled.
7479 */
7480void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7481{
7482 if (IS_CHERRYVIEW(dev))
7483 chv_disable_pll(to_i915(dev), pipe);
7484 else
7485 vlv_disable_pll(to_i915(dev), pipe);
7486}
7487
7488static void i9xx_compute_dpll(struct intel_crtc *crtc,
7489 struct intel_crtc_state *crtc_state,
7490 intel_clock_t *reduced_clock,
7491 int num_connectors)
7492{
7493 struct drm_device *dev = crtc->base.dev;
7494 struct drm_i915_private *dev_priv = dev->dev_private;
7495 u32 dpll;
7496 bool is_sdvo;
7497 struct dpll *clock = &crtc_state->dpll;
7498
7499 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7500
7501 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7502 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7503
7504 dpll = DPLL_VGA_MODE_DIS;
7505
7506 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7507 dpll |= DPLLB_MODE_LVDS;
7508 else
7509 dpll |= DPLLB_MODE_DAC_SERIAL;
7510
7511 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7512 dpll |= (crtc_state->pixel_multiplier - 1)
7513 << SDVO_MULTIPLIER_SHIFT_HIRES;
7514 }
7515
7516 if (is_sdvo)
7517 dpll |= DPLL_SDVO_HIGH_SPEED;
7518
7519 if (crtc_state->has_dp_encoder)
7520 dpll |= DPLL_SDVO_HIGH_SPEED;
7521
7522 /* compute bitmask from p1 value */
7523 if (IS_PINEVIEW(dev))
7524 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7525 else {
7526 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7527 if (IS_G4X(dev) && reduced_clock)
7528 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7529 }
7530 switch (clock->p2) {
7531 case 5:
7532 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7533 break;
7534 case 7:
7535 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7536 break;
7537 case 10:
7538 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7539 break;
7540 case 14:
7541 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7542 break;
7543 }
7544 if (INTEL_INFO(dev)->gen >= 4)
7545 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7546
7547 if (crtc_state->sdvo_tv_clock)
7548 dpll |= PLL_REF_INPUT_TVCLKINBC;
7549 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7550 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7551 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7552 else
7553 dpll |= PLL_REF_INPUT_DREFCLK;
7554
7555 dpll |= DPLL_VCO_ENABLE;
7556 crtc_state->dpll_hw_state.dpll = dpll;
7557
7558 if (INTEL_INFO(dev)->gen >= 4) {
7559 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7560 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7561 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7562 }
7563}
7564
7565static void i8xx_compute_dpll(struct intel_crtc *crtc,
7566 struct intel_crtc_state *crtc_state,
7567 intel_clock_t *reduced_clock,
7568 int num_connectors)
7569{
7570 struct drm_device *dev = crtc->base.dev;
7571 struct drm_i915_private *dev_priv = dev->dev_private;
7572 u32 dpll;
7573 struct dpll *clock = &crtc_state->dpll;
7574
7575 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7576
7577 dpll = DPLL_VGA_MODE_DIS;
7578
7579 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7580 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7581 } else {
7582 if (clock->p1 == 2)
7583 dpll |= PLL_P1_DIVIDE_BY_TWO;
7584 else
7585 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7586 if (clock->p2 == 4)
7587 dpll |= PLL_P2_DIVIDE_BY_4;
7588 }
7589
7590 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7591 dpll |= DPLL_DVO_2X_MODE;
7592
7593 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7594 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7595 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7596 else
7597 dpll |= PLL_REF_INPUT_DREFCLK;
7598
7599 dpll |= DPLL_VCO_ENABLE;
7600 crtc_state->dpll_hw_state.dpll = dpll;
7601}
7602
7603static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7604{
7605 struct drm_device *dev = intel_crtc->base.dev;
7606 struct drm_i915_private *dev_priv = dev->dev_private;
7607 enum pipe pipe = intel_crtc->pipe;
7608 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7609 struct drm_display_mode *adjusted_mode =
7610 &intel_crtc->config->base.adjusted_mode;
7611 uint32_t crtc_vtotal, crtc_vblank_end;
7612 int vsyncshift = 0;
7613
7614 /* We need to be careful not to changed the adjusted mode, for otherwise
7615 * the hw state checker will get angry at the mismatch. */
7616 crtc_vtotal = adjusted_mode->crtc_vtotal;
7617 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7618
7619 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7620 /* the chip adds 2 halflines automatically */
7621 crtc_vtotal -= 1;
7622 crtc_vblank_end -= 1;
7623
7624 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7625 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7626 else
7627 vsyncshift = adjusted_mode->crtc_hsync_start -
7628 adjusted_mode->crtc_htotal / 2;
7629 if (vsyncshift < 0)
7630 vsyncshift += adjusted_mode->crtc_htotal;
7631 }
7632
7633 if (INTEL_INFO(dev)->gen > 3)
7634 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7635
7636 I915_WRITE(HTOTAL(cpu_transcoder),
7637 (adjusted_mode->crtc_hdisplay - 1) |
7638 ((adjusted_mode->crtc_htotal - 1) << 16));
7639 I915_WRITE(HBLANK(cpu_transcoder),
7640 (adjusted_mode->crtc_hblank_start - 1) |
7641 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7642 I915_WRITE(HSYNC(cpu_transcoder),
7643 (adjusted_mode->crtc_hsync_start - 1) |
7644 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7645
7646 I915_WRITE(VTOTAL(cpu_transcoder),
7647 (adjusted_mode->crtc_vdisplay - 1) |
7648 ((crtc_vtotal - 1) << 16));
7649 I915_WRITE(VBLANK(cpu_transcoder),
7650 (adjusted_mode->crtc_vblank_start - 1) |
7651 ((crtc_vblank_end - 1) << 16));
7652 I915_WRITE(VSYNC(cpu_transcoder),
7653 (adjusted_mode->crtc_vsync_start - 1) |
7654 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7655
7656 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7657 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7658 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7659 * bits. */
7660 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7661 (pipe == PIPE_B || pipe == PIPE_C))
7662 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7663
7664 /* pipesrc controls the size that is scaled from, which should
7665 * always be the user's requested size.
7666 */
7667 I915_WRITE(PIPESRC(pipe),
7668 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7669 (intel_crtc->config->pipe_src_h - 1));
7670}
7671
7672static void intel_get_pipe_timings(struct intel_crtc *crtc,
7673 struct intel_crtc_state *pipe_config)
7674{
7675 struct drm_device *dev = crtc->base.dev;
7676 struct drm_i915_private *dev_priv = dev->dev_private;
7677 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7678 uint32_t tmp;
7679
7680 tmp = I915_READ(HTOTAL(cpu_transcoder));
7681 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7682 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7683 tmp = I915_READ(HBLANK(cpu_transcoder));
7684 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7685 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7686 tmp = I915_READ(HSYNC(cpu_transcoder));
7687 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7688 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7689
7690 tmp = I915_READ(VTOTAL(cpu_transcoder));
7691 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7692 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7693 tmp = I915_READ(VBLANK(cpu_transcoder));
7694 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7695 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7696 tmp = I915_READ(VSYNC(cpu_transcoder));
7697 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7698 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7699
7700 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7701 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7702 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7703 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7704 }
7705
7706 tmp = I915_READ(PIPESRC(crtc->pipe));
7707 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7708 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7709
7710 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7711 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7712}
7713
7714void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7715 struct intel_crtc_state *pipe_config)
7716{
7717 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7718 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7719 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7720 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7721
7722 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7723 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7724 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7725 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7726
7727 mode->flags = pipe_config->base.adjusted_mode.flags;
7728 mode->type = DRM_MODE_TYPE_DRIVER;
7729
7730 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7731 mode->flags |= pipe_config->base.adjusted_mode.flags;
7732
7733 mode->hsync = drm_mode_hsync(mode);
7734 mode->vrefresh = drm_mode_vrefresh(mode);
7735 drm_mode_set_name(mode);
7736}
7737
7738static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7739{
7740 struct drm_device *dev = intel_crtc->base.dev;
7741 struct drm_i915_private *dev_priv = dev->dev_private;
7742 uint32_t pipeconf;
7743
7744 pipeconf = 0;
7745
7746 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7747 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7748 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7749
7750 if (intel_crtc->config->double_wide)
7751 pipeconf |= PIPECONF_DOUBLE_WIDE;
7752
7753 /* only g4x and later have fancy bpc/dither controls */
7754 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7755 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7756 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7757 pipeconf |= PIPECONF_DITHER_EN |
7758 PIPECONF_DITHER_TYPE_SP;
7759
7760 switch (intel_crtc->config->pipe_bpp) {
7761 case 18:
7762 pipeconf |= PIPECONF_6BPC;
7763 break;
7764 case 24:
7765 pipeconf |= PIPECONF_8BPC;
7766 break;
7767 case 30:
7768 pipeconf |= PIPECONF_10BPC;
7769 break;
7770 default:
7771 /* Case prevented by intel_choose_pipe_bpp_dither. */
7772 BUG();
7773 }
7774 }
7775
7776 if (HAS_PIPE_CXSR(dev)) {
7777 if (intel_crtc->lowfreq_avail) {
7778 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7779 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7780 } else {
7781 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7782 }
7783 }
7784
7785 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7786 if (INTEL_INFO(dev)->gen < 4 ||
7787 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7788 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7789 else
7790 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7791 } else
7792 pipeconf |= PIPECONF_PROGRESSIVE;
7793
7794 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7795 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7796
7797 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7798 POSTING_READ(PIPECONF(intel_crtc->pipe));
7799}
7800
7801static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7802 struct intel_crtc_state *crtc_state)
7803{
7804 struct drm_device *dev = crtc->base.dev;
7805 struct drm_i915_private *dev_priv = dev->dev_private;
7806 int refclk, num_connectors = 0;
7807 intel_clock_t clock;
7808 bool ok;
7809 bool is_dsi = false;
7810 struct intel_encoder *encoder;
7811 const intel_limit_t *limit;
7812 struct drm_atomic_state *state = crtc_state->base.state;
7813 struct drm_connector *connector;
7814 struct drm_connector_state *connector_state;
7815 int i;
7816
7817 memset(&crtc_state->dpll_hw_state, 0,
7818 sizeof(crtc_state->dpll_hw_state));
7819
7820 for_each_connector_in_state(state, connector, connector_state, i) {
7821 if (connector_state->crtc != &crtc->base)
7822 continue;
7823
7824 encoder = to_intel_encoder(connector_state->best_encoder);
7825
7826 switch (encoder->type) {
7827 case INTEL_OUTPUT_DSI:
7828 is_dsi = true;
7829 break;
7830 default:
7831 break;
7832 }
7833
7834 num_connectors++;
7835 }
7836
7837 if (is_dsi)
7838 return 0;
7839
7840 if (!crtc_state->clock_set) {
7841 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7842
7843 /*
7844 * Returns a set of divisors for the desired target clock with
7845 * the given refclk, or FALSE. The returned values represent
7846 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7847 * 2) / p1 / p2.
7848 */
7849 limit = intel_limit(crtc_state, refclk);
7850 ok = dev_priv->display.find_dpll(limit, crtc_state,
7851 crtc_state->port_clock,
7852 refclk, NULL, &clock);
7853 if (!ok) {
7854 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7855 return -EINVAL;
7856 }
7857
7858 /* Compat-code for transition, will disappear. */
7859 crtc_state->dpll.n = clock.n;
7860 crtc_state->dpll.m1 = clock.m1;
7861 crtc_state->dpll.m2 = clock.m2;
7862 crtc_state->dpll.p1 = clock.p1;
7863 crtc_state->dpll.p2 = clock.p2;
7864 }
7865
7866 if (IS_GEN2(dev)) {
7867 i8xx_compute_dpll(crtc, crtc_state, NULL,
7868 num_connectors);
7869 } else if (IS_CHERRYVIEW(dev)) {
7870 chv_compute_dpll(crtc, crtc_state);
7871 } else if (IS_VALLEYVIEW(dev)) {
7872 vlv_compute_dpll(crtc, crtc_state);
7873 } else {
7874 i9xx_compute_dpll(crtc, crtc_state, NULL,
7875 num_connectors);
7876 }
7877
7878 return 0;
7879}
7880
7881static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7882 struct intel_crtc_state *pipe_config)
7883{
7884 struct drm_device *dev = crtc->base.dev;
7885 struct drm_i915_private *dev_priv = dev->dev_private;
7886 uint32_t tmp;
7887
7888 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7889 return;
7890
7891 tmp = I915_READ(PFIT_CONTROL);
7892 if (!(tmp & PFIT_ENABLE))
7893 return;
7894
7895 /* Check whether the pfit is attached to our pipe. */
7896 if (INTEL_INFO(dev)->gen < 4) {
7897 if (crtc->pipe != PIPE_B)
7898 return;
7899 } else {
7900 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7901 return;
7902 }
7903
7904 pipe_config->gmch_pfit.control = tmp;
7905 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7906 if (INTEL_INFO(dev)->gen < 5)
7907 pipe_config->gmch_pfit.lvds_border_bits =
7908 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7909}
7910
7911static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7912 struct intel_crtc_state *pipe_config)
7913{
7914 struct drm_device *dev = crtc->base.dev;
7915 struct drm_i915_private *dev_priv = dev->dev_private;
7916 int pipe = pipe_config->cpu_transcoder;
7917 intel_clock_t clock;
7918 u32 mdiv;
7919 int refclk = 100000;
7920
7921 /* In case of MIPI DPLL will not even be used */
7922 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7923 return;
7924
7925 mutex_lock(&dev_priv->sb_lock);
7926 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7927 mutex_unlock(&dev_priv->sb_lock);
7928
7929 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7930 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7931 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7932 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7933 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7934
7935 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7936}
7937
7938static void
7939i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7940 struct intel_initial_plane_config *plane_config)
7941{
7942 struct drm_device *dev = crtc->base.dev;
7943 struct drm_i915_private *dev_priv = dev->dev_private;
7944 u32 val, base, offset;
7945 int pipe = crtc->pipe, plane = crtc->plane;
7946 int fourcc, pixel_format;
7947 unsigned int aligned_height;
7948 struct drm_framebuffer *fb;
7949 struct intel_framebuffer *intel_fb;
7950
7951 val = I915_READ(DSPCNTR(plane));
7952 if (!(val & DISPLAY_PLANE_ENABLE))
7953 return;
7954
7955 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7956 if (!intel_fb) {
7957 DRM_DEBUG_KMS("failed to alloc fb\n");
7958 return;
7959 }
7960
7961 fb = &intel_fb->base;
7962
7963 if (INTEL_INFO(dev)->gen >= 4) {
7964 if (val & DISPPLANE_TILED) {
7965 plane_config->tiling = I915_TILING_X;
7966 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7967 }
7968 }
7969
7970 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7971 fourcc = i9xx_format_to_fourcc(pixel_format);
7972 fb->pixel_format = fourcc;
7973 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7974
7975 if (INTEL_INFO(dev)->gen >= 4) {
7976 if (plane_config->tiling)
7977 offset = I915_READ(DSPTILEOFF(plane));
7978 else
7979 offset = I915_READ(DSPLINOFF(plane));
7980 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7981 } else {
7982 base = I915_READ(DSPADDR(plane));
7983 }
7984 plane_config->base = base;
7985
7986 val = I915_READ(PIPESRC(pipe));
7987 fb->width = ((val >> 16) & 0xfff) + 1;
7988 fb->height = ((val >> 0) & 0xfff) + 1;
7989
7990 val = I915_READ(DSPSTRIDE(pipe));
7991 fb->pitches[0] = val & 0xffffffc0;
7992
7993 aligned_height = intel_fb_align_height(dev, fb->height,
7994 fb->pixel_format,
7995 fb->modifier[0]);
7996
7997 plane_config->size = fb->pitches[0] * aligned_height;
7998
7999 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8000 pipe_name(pipe), plane, fb->width, fb->height,
8001 fb->bits_per_pixel, base, fb->pitches[0],
8002 plane_config->size);
8003
8004 plane_config->fb = intel_fb;
8005}
8006
8007static void chv_crtc_clock_get(struct intel_crtc *crtc,
8008 struct intel_crtc_state *pipe_config)
8009{
8010 struct drm_device *dev = crtc->base.dev;
8011 struct drm_i915_private *dev_priv = dev->dev_private;
8012 int pipe = pipe_config->cpu_transcoder;
8013 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8014 intel_clock_t clock;
8015 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8016 int refclk = 100000;
8017
8018 mutex_lock(&dev_priv->sb_lock);
8019 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8020 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8021 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8022 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8023 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8024 mutex_unlock(&dev_priv->sb_lock);
8025
8026 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8027 clock.m2 = (pll_dw0 & 0xff) << 22;
8028 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8029 clock.m2 |= pll_dw2 & 0x3fffff;
8030 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8031 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8032 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8033
8034 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8035}
8036
8037static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8038 struct intel_crtc_state *pipe_config)
8039{
8040 struct drm_device *dev = crtc->base.dev;
8041 struct drm_i915_private *dev_priv = dev->dev_private;
8042 uint32_t tmp;
8043
8044 if (!intel_display_power_is_enabled(dev_priv,
8045 POWER_DOMAIN_PIPE(crtc->pipe)))
8046 return false;
8047
8048 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8049 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8050
8051 tmp = I915_READ(PIPECONF(crtc->pipe));
8052 if (!(tmp & PIPECONF_ENABLE))
8053 return false;
8054
8055 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8056 switch (tmp & PIPECONF_BPC_MASK) {
8057 case PIPECONF_6BPC:
8058 pipe_config->pipe_bpp = 18;
8059 break;
8060 case PIPECONF_8BPC:
8061 pipe_config->pipe_bpp = 24;
8062 break;
8063 case PIPECONF_10BPC:
8064 pipe_config->pipe_bpp = 30;
8065 break;
8066 default:
8067 break;
8068 }
8069 }
8070
8071 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8072 pipe_config->limited_color_range = true;
8073
8074 if (INTEL_INFO(dev)->gen < 4)
8075 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8076
8077 intel_get_pipe_timings(crtc, pipe_config);
8078
8079 i9xx_get_pfit_config(crtc, pipe_config);
8080
8081 if (INTEL_INFO(dev)->gen >= 4) {
8082 tmp = I915_READ(DPLL_MD(crtc->pipe));
8083 pipe_config->pixel_multiplier =
8084 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8085 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8086 pipe_config->dpll_hw_state.dpll_md = tmp;
8087 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8088 tmp = I915_READ(DPLL(crtc->pipe));
8089 pipe_config->pixel_multiplier =
8090 ((tmp & SDVO_MULTIPLIER_MASK)
8091 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8092 } else {
8093 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8094 * port and will be fixed up in the encoder->get_config
8095 * function. */
8096 pipe_config->pixel_multiplier = 1;
8097 }
8098 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8099 if (!IS_VALLEYVIEW(dev)) {
8100 /*
8101 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8102 * on 830. Filter it out here so that we don't
8103 * report errors due to that.
8104 */
8105 if (IS_I830(dev))
8106 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8107
8108 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8109 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8110 } else {
8111 /* Mask out read-only status bits. */
8112 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8113 DPLL_PORTC_READY_MASK |
8114 DPLL_PORTB_READY_MASK);
8115 }
8116
8117 if (IS_CHERRYVIEW(dev))
8118 chv_crtc_clock_get(crtc, pipe_config);
8119 else if (IS_VALLEYVIEW(dev))
8120 vlv_crtc_clock_get(crtc, pipe_config);
8121 else
8122 i9xx_crtc_clock_get(crtc, pipe_config);
8123
8124 return true;
8125}
8126
8127static void ironlake_init_pch_refclk(struct drm_device *dev)
8128{
8129 struct drm_i915_private *dev_priv = dev->dev_private;
8130 struct intel_encoder *encoder;
8131 u32 val, final;
8132 bool has_lvds = false;
8133 bool has_cpu_edp = false;
8134 bool has_panel = false;
8135 bool has_ck505 = false;
8136 bool can_ssc = false;
8137
8138 /* We need to take the global config into account */
8139 for_each_intel_encoder(dev, encoder) {
8140 switch (encoder->type) {
8141 case INTEL_OUTPUT_LVDS:
8142 has_panel = true;
8143 has_lvds = true;
8144 break;
8145 case INTEL_OUTPUT_EDP:
8146 has_panel = true;
8147 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8148 has_cpu_edp = true;
8149 break;
8150 default:
8151 break;
8152 }
8153 }
8154
8155 if (HAS_PCH_IBX(dev)) {
8156 has_ck505 = dev_priv->vbt.display_clock_mode;
8157 can_ssc = has_ck505;
8158 } else {
8159 has_ck505 = false;
8160 can_ssc = true;
8161 }
8162
8163 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8164 has_panel, has_lvds, has_ck505);
8165
8166 /* Ironlake: try to setup display ref clock before DPLL
8167 * enabling. This is only under driver's control after
8168 * PCH B stepping, previous chipset stepping should be
8169 * ignoring this setting.
8170 */
8171 val = I915_READ(PCH_DREF_CONTROL);
8172
8173 /* As we must carefully and slowly disable/enable each source in turn,
8174 * compute the final state we want first and check if we need to
8175 * make any changes at all.
8176 */
8177 final = val;
8178 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8179 if (has_ck505)
8180 final |= DREF_NONSPREAD_CK505_ENABLE;
8181 else
8182 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8183
8184 final &= ~DREF_SSC_SOURCE_MASK;
8185 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8186 final &= ~DREF_SSC1_ENABLE;
8187
8188 if (has_panel) {
8189 final |= DREF_SSC_SOURCE_ENABLE;
8190
8191 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8192 final |= DREF_SSC1_ENABLE;
8193
8194 if (has_cpu_edp) {
8195 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8196 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8197 else
8198 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8199 } else
8200 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8201 } else {
8202 final |= DREF_SSC_SOURCE_DISABLE;
8203 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8204 }
8205
8206 if (final == val)
8207 return;
8208
8209 /* Always enable nonspread source */
8210 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8211
8212 if (has_ck505)
8213 val |= DREF_NONSPREAD_CK505_ENABLE;
8214 else
8215 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8216
8217 if (has_panel) {
8218 val &= ~DREF_SSC_SOURCE_MASK;
8219 val |= DREF_SSC_SOURCE_ENABLE;
8220
8221 /* SSC must be turned on before enabling the CPU output */
8222 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8223 DRM_DEBUG_KMS("Using SSC on panel\n");
8224 val |= DREF_SSC1_ENABLE;
8225 } else
8226 val &= ~DREF_SSC1_ENABLE;
8227
8228 /* Get SSC going before enabling the outputs */
8229 I915_WRITE(PCH_DREF_CONTROL, val);
8230 POSTING_READ(PCH_DREF_CONTROL);
8231 udelay(200);
8232
8233 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8234
8235 /* Enable CPU source on CPU attached eDP */
8236 if (has_cpu_edp) {
8237 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8238 DRM_DEBUG_KMS("Using SSC on eDP\n");
8239 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8240 } else
8241 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8242 } else
8243 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8244
8245 I915_WRITE(PCH_DREF_CONTROL, val);
8246 POSTING_READ(PCH_DREF_CONTROL);
8247 udelay(200);
8248 } else {
8249 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8250
8251 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8252
8253 /* Turn off CPU output */
8254 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8255
8256 I915_WRITE(PCH_DREF_CONTROL, val);
8257 POSTING_READ(PCH_DREF_CONTROL);
8258 udelay(200);
8259
8260 /* Turn off the SSC source */
8261 val &= ~DREF_SSC_SOURCE_MASK;
8262 val |= DREF_SSC_SOURCE_DISABLE;
8263
8264 /* Turn off SSC1 */
8265 val &= ~DREF_SSC1_ENABLE;
8266
8267 I915_WRITE(PCH_DREF_CONTROL, val);
8268 POSTING_READ(PCH_DREF_CONTROL);
8269 udelay(200);
8270 }
8271
8272 BUG_ON(val != final);
8273}
8274
8275static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8276{
8277 uint32_t tmp;
8278
8279 tmp = I915_READ(SOUTH_CHICKEN2);
8280 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8281 I915_WRITE(SOUTH_CHICKEN2, tmp);
8282
8283 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8284 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8285 DRM_ERROR("FDI mPHY reset assert timeout\n");
8286
8287 tmp = I915_READ(SOUTH_CHICKEN2);
8288 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8289 I915_WRITE(SOUTH_CHICKEN2, tmp);
8290
8291 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8292 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8293 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8294}
8295
8296/* WaMPhyProgramming:hsw */
8297static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8298{
8299 uint32_t tmp;
8300
8301 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8302 tmp &= ~(0xFF << 24);
8303 tmp |= (0x12 << 24);
8304 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8305
8306 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8307 tmp |= (1 << 11);
8308 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8309
8310 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8311 tmp |= (1 << 11);
8312 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8313
8314 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8315 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8316 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8317
8318 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8319 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8320 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8321
8322 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8323 tmp &= ~(7 << 13);
8324 tmp |= (5 << 13);
8325 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8326
8327 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8328 tmp &= ~(7 << 13);
8329 tmp |= (5 << 13);
8330 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8331
8332 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8333 tmp &= ~0xFF;
8334 tmp |= 0x1C;
8335 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8336
8337 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8338 tmp &= ~0xFF;
8339 tmp |= 0x1C;
8340 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8341
8342 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8343 tmp &= ~(0xFF << 16);
8344 tmp |= (0x1C << 16);
8345 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8346
8347 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8348 tmp &= ~(0xFF << 16);
8349 tmp |= (0x1C << 16);
8350 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8351
8352 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8353 tmp |= (1 << 27);
8354 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8355
8356 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8357 tmp |= (1 << 27);
8358 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8359
8360 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8361 tmp &= ~(0xF << 28);
8362 tmp |= (4 << 28);
8363 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8364
8365 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8366 tmp &= ~(0xF << 28);
8367 tmp |= (4 << 28);
8368 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8369}
8370
8371/* Implements 3 different sequences from BSpec chapter "Display iCLK
8372 * Programming" based on the parameters passed:
8373 * - Sequence to enable CLKOUT_DP
8374 * - Sequence to enable CLKOUT_DP without spread
8375 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8376 */
8377static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8378 bool with_fdi)
8379{
8380 struct drm_i915_private *dev_priv = dev->dev_private;
8381 uint32_t reg, tmp;
8382
8383 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8384 with_spread = true;
8385 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8386 with_fdi, "LP PCH doesn't have FDI\n"))
8387 with_fdi = false;
8388
8389 mutex_lock(&dev_priv->sb_lock);
8390
8391 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8392 tmp &= ~SBI_SSCCTL_DISABLE;
8393 tmp |= SBI_SSCCTL_PATHALT;
8394 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8395
8396 udelay(24);
8397
8398 if (with_spread) {
8399 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8400 tmp &= ~SBI_SSCCTL_PATHALT;
8401 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8402
8403 if (with_fdi) {
8404 lpt_reset_fdi_mphy(dev_priv);
8405 lpt_program_fdi_mphy(dev_priv);
8406 }
8407 }
8408
8409 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8410 SBI_GEN0 : SBI_DBUFF0;
8411 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8412 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8413 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8414
8415 mutex_unlock(&dev_priv->sb_lock);
8416}
8417
8418/* Sequence to disable CLKOUT_DP */
8419static void lpt_disable_clkout_dp(struct drm_device *dev)
8420{
8421 struct drm_i915_private *dev_priv = dev->dev_private;
8422 uint32_t reg, tmp;
8423
8424 mutex_lock(&dev_priv->sb_lock);
8425
8426 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8427 SBI_GEN0 : SBI_DBUFF0;
8428 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8429 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8430 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8431
8432 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8433 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8434 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8435 tmp |= SBI_SSCCTL_PATHALT;
8436 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8437 udelay(32);
8438 }
8439 tmp |= SBI_SSCCTL_DISABLE;
8440 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8441 }
8442
8443 mutex_unlock(&dev_priv->sb_lock);
8444}
8445
8446static void lpt_init_pch_refclk(struct drm_device *dev)
8447{
8448 struct intel_encoder *encoder;
8449 bool has_vga = false;
8450
8451 for_each_intel_encoder(dev, encoder) {
8452 switch (encoder->type) {
8453 case INTEL_OUTPUT_ANALOG:
8454 has_vga = true;
8455 break;
8456 default:
8457 break;
8458 }
8459 }
8460
8461 if (has_vga)
8462 lpt_enable_clkout_dp(dev, true, true);
8463 else
8464 lpt_disable_clkout_dp(dev);
8465}
8466
8467/*
8468 * Initialize reference clocks when the driver loads
8469 */
8470void intel_init_pch_refclk(struct drm_device *dev)
8471{
8472 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8473 ironlake_init_pch_refclk(dev);
8474 else if (HAS_PCH_LPT(dev))
8475 lpt_init_pch_refclk(dev);
8476}
8477
8478static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8479{
8480 struct drm_device *dev = crtc_state->base.crtc->dev;
8481 struct drm_i915_private *dev_priv = dev->dev_private;
8482 struct drm_atomic_state *state = crtc_state->base.state;
8483 struct drm_connector *connector;
8484 struct drm_connector_state *connector_state;
8485 struct intel_encoder *encoder;
8486 int num_connectors = 0, i;
8487 bool is_lvds = false;
8488
8489 for_each_connector_in_state(state, connector, connector_state, i) {
8490 if (connector_state->crtc != crtc_state->base.crtc)
8491 continue;
8492
8493 encoder = to_intel_encoder(connector_state->best_encoder);
8494
8495 switch (encoder->type) {
8496 case INTEL_OUTPUT_LVDS:
8497 is_lvds = true;
8498 break;
8499 default:
8500 break;
8501 }
8502 num_connectors++;
8503 }
8504
8505 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8506 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8507 dev_priv->vbt.lvds_ssc_freq);
8508 return dev_priv->vbt.lvds_ssc_freq;
8509 }
8510
8511 return 120000;
8512}
8513
8514static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8515{
8516 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8517 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8518 int pipe = intel_crtc->pipe;
8519 uint32_t val;
8520
8521 val = 0;
8522
8523 switch (intel_crtc->config->pipe_bpp) {
8524 case 18:
8525 val |= PIPECONF_6BPC;
8526 break;
8527 case 24:
8528 val |= PIPECONF_8BPC;
8529 break;
8530 case 30:
8531 val |= PIPECONF_10BPC;
8532 break;
8533 case 36:
8534 val |= PIPECONF_12BPC;
8535 break;
8536 default:
8537 /* Case prevented by intel_choose_pipe_bpp_dither. */
8538 BUG();
8539 }
8540
8541 if (intel_crtc->config->dither)
8542 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8543
8544 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8545 val |= PIPECONF_INTERLACED_ILK;
8546 else
8547 val |= PIPECONF_PROGRESSIVE;
8548
8549 if (intel_crtc->config->limited_color_range)
8550 val |= PIPECONF_COLOR_RANGE_SELECT;
8551
8552 I915_WRITE(PIPECONF(pipe), val);
8553 POSTING_READ(PIPECONF(pipe));
8554}
8555
8556/*
8557 * Set up the pipe CSC unit.
8558 *
8559 * Currently only full range RGB to limited range RGB conversion
8560 * is supported, but eventually this should handle various
8561 * RGB<->YCbCr scenarios as well.
8562 */
8563static void intel_set_pipe_csc(struct drm_crtc *crtc)
8564{
8565 struct drm_device *dev = crtc->dev;
8566 struct drm_i915_private *dev_priv = dev->dev_private;
8567 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8568 int pipe = intel_crtc->pipe;
8569 uint16_t coeff = 0x7800; /* 1.0 */
8570
8571 /*
8572 * TODO: Check what kind of values actually come out of the pipe
8573 * with these coeff/postoff values and adjust to get the best
8574 * accuracy. Perhaps we even need to take the bpc value into
8575 * consideration.
8576 */
8577
8578 if (intel_crtc->config->limited_color_range)
8579 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8580
8581 /*
8582 * GY/GU and RY/RU should be the other way around according
8583 * to BSpec, but reality doesn't agree. Just set them up in
8584 * a way that results in the correct picture.
8585 */
8586 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8587 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8588
8589 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8590 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8591
8592 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8593 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8594
8595 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8596 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8597 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8598
8599 if (INTEL_INFO(dev)->gen > 6) {
8600 uint16_t postoff = 0;
8601
8602 if (intel_crtc->config->limited_color_range)
8603 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8604
8605 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8606 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8607 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8608
8609 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8610 } else {
8611 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8612
8613 if (intel_crtc->config->limited_color_range)
8614 mode |= CSC_BLACK_SCREEN_OFFSET;
8615
8616 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8617 }
8618}
8619
8620static void haswell_set_pipeconf(struct drm_crtc *crtc)
8621{
8622 struct drm_device *dev = crtc->dev;
8623 struct drm_i915_private *dev_priv = dev->dev_private;
8624 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8625 enum pipe pipe = intel_crtc->pipe;
8626 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8627 uint32_t val;
8628
8629 val = 0;
8630
8631 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8632 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8633
8634 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8635 val |= PIPECONF_INTERLACED_ILK;
8636 else
8637 val |= PIPECONF_PROGRESSIVE;
8638
8639 I915_WRITE(PIPECONF(cpu_transcoder), val);
8640 POSTING_READ(PIPECONF(cpu_transcoder));
8641
8642 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8643 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8644
8645 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8646 val = 0;
8647
8648 switch (intel_crtc->config->pipe_bpp) {
8649 case 18:
8650 val |= PIPEMISC_DITHER_6_BPC;
8651 break;
8652 case 24:
8653 val |= PIPEMISC_DITHER_8_BPC;
8654 break;
8655 case 30:
8656 val |= PIPEMISC_DITHER_10_BPC;
8657 break;
8658 case 36:
8659 val |= PIPEMISC_DITHER_12_BPC;
8660 break;
8661 default:
8662 /* Case prevented by pipe_config_set_bpp. */
8663 BUG();
8664 }
8665
8666 if (intel_crtc->config->dither)
8667 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8668
8669 I915_WRITE(PIPEMISC(pipe), val);
8670 }
8671}
8672
8673static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8674 struct intel_crtc_state *crtc_state,
8675 intel_clock_t *clock,
8676 bool *has_reduced_clock,
8677 intel_clock_t *reduced_clock)
8678{
8679 struct drm_device *dev = crtc->dev;
8680 struct drm_i915_private *dev_priv = dev->dev_private;
8681 int refclk;
8682 const intel_limit_t *limit;
8683 bool ret;
8684
8685 refclk = ironlake_get_refclk(crtc_state);
8686
8687 /*
8688 * Returns a set of divisors for the desired target clock with the given
8689 * refclk, or FALSE. The returned values represent the clock equation:
8690 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8691 */
8692 limit = intel_limit(crtc_state, refclk);
8693 ret = dev_priv->display.find_dpll(limit, crtc_state,
8694 crtc_state->port_clock,
8695 refclk, NULL, clock);
8696 if (!ret)
8697 return false;
8698
8699 return true;
8700}
8701
8702int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8703{
8704 /*
8705 * Account for spread spectrum to avoid
8706 * oversubscribing the link. Max center spread
8707 * is 2.5%; use 5% for safety's sake.
8708 */
8709 u32 bps = target_clock * bpp * 21 / 20;
8710 return DIV_ROUND_UP(bps, link_bw * 8);
8711}
8712
8713static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8714{
8715 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8716}
8717
8718static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8719 struct intel_crtc_state *crtc_state,
8720 u32 *fp,
8721 intel_clock_t *reduced_clock, u32 *fp2)
8722{
8723 struct drm_crtc *crtc = &intel_crtc->base;
8724 struct drm_device *dev = crtc->dev;
8725 struct drm_i915_private *dev_priv = dev->dev_private;
8726 struct drm_atomic_state *state = crtc_state->base.state;
8727 struct drm_connector *connector;
8728 struct drm_connector_state *connector_state;
8729 struct intel_encoder *encoder;
8730 uint32_t dpll;
8731 int factor, num_connectors = 0, i;
8732 bool is_lvds = false, is_sdvo = false;
8733
8734 for_each_connector_in_state(state, connector, connector_state, i) {
8735 if (connector_state->crtc != crtc_state->base.crtc)
8736 continue;
8737
8738 encoder = to_intel_encoder(connector_state->best_encoder);
8739
8740 switch (encoder->type) {
8741 case INTEL_OUTPUT_LVDS:
8742 is_lvds = true;
8743 break;
8744 case INTEL_OUTPUT_SDVO:
8745 case INTEL_OUTPUT_HDMI:
8746 is_sdvo = true;
8747 break;
8748 default:
8749 break;
8750 }
8751
8752 num_connectors++;
8753 }
8754
8755 /* Enable autotuning of the PLL clock (if permissible) */
8756 factor = 21;
8757 if (is_lvds) {
8758 if ((intel_panel_use_ssc(dev_priv) &&
8759 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8760 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8761 factor = 25;
8762 } else if (crtc_state->sdvo_tv_clock)
8763 factor = 20;
8764
8765 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8766 *fp |= FP_CB_TUNE;
8767
8768 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8769 *fp2 |= FP_CB_TUNE;
8770
8771 dpll = 0;
8772
8773 if (is_lvds)
8774 dpll |= DPLLB_MODE_LVDS;
8775 else
8776 dpll |= DPLLB_MODE_DAC_SERIAL;
8777
8778 dpll |= (crtc_state->pixel_multiplier - 1)
8779 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8780
8781 if (is_sdvo)
8782 dpll |= DPLL_SDVO_HIGH_SPEED;
8783 if (crtc_state->has_dp_encoder)
8784 dpll |= DPLL_SDVO_HIGH_SPEED;
8785
8786 /* compute bitmask from p1 value */
8787 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8788 /* also FPA1 */
8789 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8790
8791 switch (crtc_state->dpll.p2) {
8792 case 5:
8793 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8794 break;
8795 case 7:
8796 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8797 break;
8798 case 10:
8799 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8800 break;
8801 case 14:
8802 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8803 break;
8804 }
8805
8806 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8807 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8808 else
8809 dpll |= PLL_REF_INPUT_DREFCLK;
8810
8811 return dpll | DPLL_VCO_ENABLE;
8812}
8813
8814static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8815 struct intel_crtc_state *crtc_state)
8816{
8817 struct drm_device *dev = crtc->base.dev;
8818 intel_clock_t clock, reduced_clock;
8819 u32 dpll = 0, fp = 0, fp2 = 0;
8820 bool ok, has_reduced_clock = false;
8821 bool is_lvds = false;
8822 struct intel_shared_dpll *pll;
8823
8824 memset(&crtc_state->dpll_hw_state, 0,
8825 sizeof(crtc_state->dpll_hw_state));
8826
8827 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8828
8829 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8830 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8831
8832 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8833 &has_reduced_clock, &reduced_clock);
8834 if (!ok && !crtc_state->clock_set) {
8835 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8836 return -EINVAL;
8837 }
8838 /* Compat-code for transition, will disappear. */
8839 if (!crtc_state->clock_set) {
8840 crtc_state->dpll.n = clock.n;
8841 crtc_state->dpll.m1 = clock.m1;
8842 crtc_state->dpll.m2 = clock.m2;
8843 crtc_state->dpll.p1 = clock.p1;
8844 crtc_state->dpll.p2 = clock.p2;
8845 }
8846
8847 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8848 if (crtc_state->has_pch_encoder) {
8849 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8850 if (has_reduced_clock)
8851 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8852
8853 dpll = ironlake_compute_dpll(crtc, crtc_state,
8854 &fp, &reduced_clock,
8855 has_reduced_clock ? &fp2 : NULL);
8856
8857 crtc_state->dpll_hw_state.dpll = dpll;
8858 crtc_state->dpll_hw_state.fp0 = fp;
8859 if (has_reduced_clock)
8860 crtc_state->dpll_hw_state.fp1 = fp2;
8861 else
8862 crtc_state->dpll_hw_state.fp1 = fp;
8863
8864 pll = intel_get_shared_dpll(crtc, crtc_state);
8865 if (pll == NULL) {
8866 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8867 pipe_name(crtc->pipe));
8868 return -EINVAL;
8869 }
8870 }
8871
8872 if (is_lvds && has_reduced_clock)
8873 crtc->lowfreq_avail = true;
8874 else
8875 crtc->lowfreq_avail = false;
8876
8877 return 0;
8878}
8879
8880static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8881 struct intel_link_m_n *m_n)
8882{
8883 struct drm_device *dev = crtc->base.dev;
8884 struct drm_i915_private *dev_priv = dev->dev_private;
8885 enum pipe pipe = crtc->pipe;
8886
8887 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8888 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8889 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8890 & ~TU_SIZE_MASK;
8891 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8892 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8893 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8894}
8895
8896static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8897 enum transcoder transcoder,
8898 struct intel_link_m_n *m_n,
8899 struct intel_link_m_n *m2_n2)
8900{
8901 struct drm_device *dev = crtc->base.dev;
8902 struct drm_i915_private *dev_priv = dev->dev_private;
8903 enum pipe pipe = crtc->pipe;
8904
8905 if (INTEL_INFO(dev)->gen >= 5) {
8906 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8907 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8908 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8909 & ~TU_SIZE_MASK;
8910 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8911 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8912 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8913 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8914 * gen < 8) and if DRRS is supported (to make sure the
8915 * registers are not unnecessarily read).
8916 */
8917 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8918 crtc->config->has_drrs) {
8919 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8920 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8921 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8922 & ~TU_SIZE_MASK;
8923 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8924 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8925 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8926 }
8927 } else {
8928 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8929 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8930 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8931 & ~TU_SIZE_MASK;
8932 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8933 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8934 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8935 }
8936}
8937
8938void intel_dp_get_m_n(struct intel_crtc *crtc,
8939 struct intel_crtc_state *pipe_config)
8940{
8941 if (pipe_config->has_pch_encoder)
8942 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8943 else
8944 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8945 &pipe_config->dp_m_n,
8946 &pipe_config->dp_m2_n2);
8947}
8948
8949static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8950 struct intel_crtc_state *pipe_config)
8951{
8952 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8953 &pipe_config->fdi_m_n, NULL);
8954}
8955
8956static void skylake_get_pfit_config(struct intel_crtc *crtc,
8957 struct intel_crtc_state *pipe_config)
8958{
8959 struct drm_device *dev = crtc->base.dev;
8960 struct drm_i915_private *dev_priv = dev->dev_private;
8961 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8962 uint32_t ps_ctrl = 0;
8963 int id = -1;
8964 int i;
8965
8966 /* find scaler attached to this pipe */
8967 for (i = 0; i < crtc->num_scalers; i++) {
8968 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8969 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8970 id = i;
8971 pipe_config->pch_pfit.enabled = true;
8972 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8973 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8974 break;
8975 }
8976 }
8977
8978 scaler_state->scaler_id = id;
8979 if (id >= 0) {
8980 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8981 } else {
8982 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8983 }
8984}
8985
8986static void
8987skylake_get_initial_plane_config(struct intel_crtc *crtc,
8988 struct intel_initial_plane_config *plane_config)
8989{
8990 struct drm_device *dev = crtc->base.dev;
8991 struct drm_i915_private *dev_priv = dev->dev_private;
8992 u32 val, base, offset, stride_mult, tiling;
8993 int pipe = crtc->pipe;
8994 int fourcc, pixel_format;
8995 unsigned int aligned_height;
8996 struct drm_framebuffer *fb;
8997 struct intel_framebuffer *intel_fb;
8998
8999 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9000 if (!intel_fb) {
9001 DRM_DEBUG_KMS("failed to alloc fb\n");
9002 return;
9003 }
9004
9005 fb = &intel_fb->base;
9006
9007 val = I915_READ(PLANE_CTL(pipe, 0));
9008 if (!(val & PLANE_CTL_ENABLE))
9009 goto error;
9010
9011 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9012 fourcc = skl_format_to_fourcc(pixel_format,
9013 val & PLANE_CTL_ORDER_RGBX,
9014 val & PLANE_CTL_ALPHA_MASK);
9015 fb->pixel_format = fourcc;
9016 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9017
9018 tiling = val & PLANE_CTL_TILED_MASK;
9019 switch (tiling) {
9020 case PLANE_CTL_TILED_LINEAR:
9021 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9022 break;
9023 case PLANE_CTL_TILED_X:
9024 plane_config->tiling = I915_TILING_X;
9025 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9026 break;
9027 case PLANE_CTL_TILED_Y:
9028 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9029 break;
9030 case PLANE_CTL_TILED_YF:
9031 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9032 break;
9033 default:
9034 MISSING_CASE(tiling);
9035 goto error;
9036 }
9037
9038 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9039 plane_config->base = base;
9040
9041 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9042
9043 val = I915_READ(PLANE_SIZE(pipe, 0));
9044 fb->height = ((val >> 16) & 0xfff) + 1;
9045 fb->width = ((val >> 0) & 0x1fff) + 1;
9046
9047 val = I915_READ(PLANE_STRIDE(pipe, 0));
9048 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9049 fb->pixel_format);
9050 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9051
9052 aligned_height = intel_fb_align_height(dev, fb->height,
9053 fb->pixel_format,
9054 fb->modifier[0]);
9055
9056 plane_config->size = fb->pitches[0] * aligned_height;
9057
9058 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9059 pipe_name(pipe), fb->width, fb->height,
9060 fb->bits_per_pixel, base, fb->pitches[0],
9061 plane_config->size);
9062
9063 plane_config->fb = intel_fb;
9064 return;
9065
9066error:
9067 kfree(fb);
9068}
9069
9070static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9071 struct intel_crtc_state *pipe_config)
9072{
9073 struct drm_device *dev = crtc->base.dev;
9074 struct drm_i915_private *dev_priv = dev->dev_private;
9075 uint32_t tmp;
9076
9077 tmp = I915_READ(PF_CTL(crtc->pipe));
9078
9079 if (tmp & PF_ENABLE) {
9080 pipe_config->pch_pfit.enabled = true;
9081 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9082 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9083
9084 /* We currently do not free assignements of panel fitters on
9085 * ivb/hsw (since we don't use the higher upscaling modes which
9086 * differentiates them) so just WARN about this case for now. */
9087 if (IS_GEN7(dev)) {
9088 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9089 PF_PIPE_SEL_IVB(crtc->pipe));
9090 }
9091 }
9092}
9093
9094static void
9095ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9096 struct intel_initial_plane_config *plane_config)
9097{
9098 struct drm_device *dev = crtc->base.dev;
9099 struct drm_i915_private *dev_priv = dev->dev_private;
9100 u32 val, base, offset;
9101 int pipe = crtc->pipe;
9102 int fourcc, pixel_format;
9103 unsigned int aligned_height;
9104 struct drm_framebuffer *fb;
9105 struct intel_framebuffer *intel_fb;
9106
9107 val = I915_READ(DSPCNTR(pipe));
9108 if (!(val & DISPLAY_PLANE_ENABLE))
9109 return;
9110
9111 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9112 if (!intel_fb) {
9113 DRM_DEBUG_KMS("failed to alloc fb\n");
9114 return;
9115 }
9116
9117 fb = &intel_fb->base;
9118
9119 if (INTEL_INFO(dev)->gen >= 4) {
9120 if (val & DISPPLANE_TILED) {
9121 plane_config->tiling = I915_TILING_X;
9122 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9123 }
9124 }
9125
9126 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9127 fourcc = i9xx_format_to_fourcc(pixel_format);
9128 fb->pixel_format = fourcc;
9129 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9130
9131 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9132 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9133 offset = I915_READ(DSPOFFSET(pipe));
9134 } else {
9135 if (plane_config->tiling)
9136 offset = I915_READ(DSPTILEOFF(pipe));
9137 else
9138 offset = I915_READ(DSPLINOFF(pipe));
9139 }
9140 plane_config->base = base;
9141
9142 val = I915_READ(PIPESRC(pipe));
9143 fb->width = ((val >> 16) & 0xfff) + 1;
9144 fb->height = ((val >> 0) & 0xfff) + 1;
9145
9146 val = I915_READ(DSPSTRIDE(pipe));
9147 fb->pitches[0] = val & 0xffffffc0;
9148
9149 aligned_height = intel_fb_align_height(dev, fb->height,
9150 fb->pixel_format,
9151 fb->modifier[0]);
9152
9153 plane_config->size = fb->pitches[0] * aligned_height;
9154
9155 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9156 pipe_name(pipe), fb->width, fb->height,
9157 fb->bits_per_pixel, base, fb->pitches[0],
9158 plane_config->size);
9159
9160 plane_config->fb = intel_fb;
9161}
9162
9163static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9164 struct intel_crtc_state *pipe_config)
9165{
9166 struct drm_device *dev = crtc->base.dev;
9167 struct drm_i915_private *dev_priv = dev->dev_private;
9168 uint32_t tmp;
9169
9170 if (!intel_display_power_is_enabled(dev_priv,
9171 POWER_DOMAIN_PIPE(crtc->pipe)))
9172 return false;
9173
9174 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9175 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9176
9177 tmp = I915_READ(PIPECONF(crtc->pipe));
9178 if (!(tmp & PIPECONF_ENABLE))
9179 return false;
9180
9181 switch (tmp & PIPECONF_BPC_MASK) {
9182 case PIPECONF_6BPC:
9183 pipe_config->pipe_bpp = 18;
9184 break;
9185 case PIPECONF_8BPC:
9186 pipe_config->pipe_bpp = 24;
9187 break;
9188 case PIPECONF_10BPC:
9189 pipe_config->pipe_bpp = 30;
9190 break;
9191 case PIPECONF_12BPC:
9192 pipe_config->pipe_bpp = 36;
9193 break;
9194 default:
9195 break;
9196 }
9197
9198 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9199 pipe_config->limited_color_range = true;
9200
9201 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9202 struct intel_shared_dpll *pll;
9203
9204 pipe_config->has_pch_encoder = true;
9205
9206 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9207 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9208 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9209
9210 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9211
9212 if (HAS_PCH_IBX(dev_priv->dev)) {
9213 pipe_config->shared_dpll =
9214 (enum intel_dpll_id) crtc->pipe;
9215 } else {
9216 tmp = I915_READ(PCH_DPLL_SEL);
9217 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9218 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9219 else
9220 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9221 }
9222
9223 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9224
9225 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9226 &pipe_config->dpll_hw_state));
9227
9228 tmp = pipe_config->dpll_hw_state.dpll;
9229 pipe_config->pixel_multiplier =
9230 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9231 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9232
9233 ironlake_pch_clock_get(crtc, pipe_config);
9234 } else {
9235 pipe_config->pixel_multiplier = 1;
9236 }
9237
9238 intel_get_pipe_timings(crtc, pipe_config);
9239
9240 ironlake_get_pfit_config(crtc, pipe_config);
9241
9242 return true;
9243}
9244
9245static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9246{
9247 struct drm_device *dev = dev_priv->dev;
9248 struct intel_crtc *crtc;
9249
9250 for_each_intel_crtc(dev, crtc)
9251 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9252 pipe_name(crtc->pipe));
9253
9254 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9255 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9256 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9257 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9258 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9259 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9260 "CPU PWM1 enabled\n");
9261 if (IS_HASWELL(dev))
9262 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9263 "CPU PWM2 enabled\n");
9264 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9265 "PCH PWM1 enabled\n");
9266 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9267 "Utility pin enabled\n");
9268 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9269
9270 /*
9271 * In theory we can still leave IRQs enabled, as long as only the HPD
9272 * interrupts remain enabled. We used to check for that, but since it's
9273 * gen-specific and since we only disable LCPLL after we fully disable
9274 * the interrupts, the check below should be enough.
9275 */
9276 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9277}
9278
9279static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9280{
9281 struct drm_device *dev = dev_priv->dev;
9282
9283 if (IS_HASWELL(dev))
9284 return I915_READ(D_COMP_HSW);
9285 else
9286 return I915_READ(D_COMP_BDW);
9287}
9288
9289static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9290{
9291 struct drm_device *dev = dev_priv->dev;
9292
9293 if (IS_HASWELL(dev)) {
9294 mutex_lock(&dev_priv->rps.hw_lock);
9295 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9296 val))
9297 DRM_ERROR("Failed to write to D_COMP\n");
9298 mutex_unlock(&dev_priv->rps.hw_lock);
9299 } else {
9300 I915_WRITE(D_COMP_BDW, val);
9301 POSTING_READ(D_COMP_BDW);
9302 }
9303}
9304
9305/*
9306 * This function implements pieces of two sequences from BSpec:
9307 * - Sequence for display software to disable LCPLL
9308 * - Sequence for display software to allow package C8+
9309 * The steps implemented here are just the steps that actually touch the LCPLL
9310 * register. Callers should take care of disabling all the display engine
9311 * functions, doing the mode unset, fixing interrupts, etc.
9312 */
9313static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9314 bool switch_to_fclk, bool allow_power_down)
9315{
9316 uint32_t val;
9317
9318 assert_can_disable_lcpll(dev_priv);
9319
9320 val = I915_READ(LCPLL_CTL);
9321
9322 if (switch_to_fclk) {
9323 val |= LCPLL_CD_SOURCE_FCLK;
9324 I915_WRITE(LCPLL_CTL, val);
9325
9326 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9327 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9328 DRM_ERROR("Switching to FCLK failed\n");
9329
9330 val = I915_READ(LCPLL_CTL);
9331 }
9332
9333 val |= LCPLL_PLL_DISABLE;
9334 I915_WRITE(LCPLL_CTL, val);
9335 POSTING_READ(LCPLL_CTL);
9336
9337 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9338 DRM_ERROR("LCPLL still locked\n");
9339
9340 val = hsw_read_dcomp(dev_priv);
9341 val |= D_COMP_COMP_DISABLE;
9342 hsw_write_dcomp(dev_priv, val);
9343 ndelay(100);
9344
9345 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9346 1))
9347 DRM_ERROR("D_COMP RCOMP still in progress\n");
9348
9349 if (allow_power_down) {
9350 val = I915_READ(LCPLL_CTL);
9351 val |= LCPLL_POWER_DOWN_ALLOW;
9352 I915_WRITE(LCPLL_CTL, val);
9353 POSTING_READ(LCPLL_CTL);
9354 }
9355}
9356
9357/*
9358 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9359 * source.
9360 */
9361static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9362{
9363 uint32_t val;
9364
9365 val = I915_READ(LCPLL_CTL);
9366
9367 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9368 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9369 return;
9370
9371 /*
9372 * Make sure we're not on PC8 state before disabling PC8, otherwise
9373 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9374 */
9375 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9376
9377 if (val & LCPLL_POWER_DOWN_ALLOW) {
9378 val &= ~LCPLL_POWER_DOWN_ALLOW;
9379 I915_WRITE(LCPLL_CTL, val);
9380 POSTING_READ(LCPLL_CTL);
9381 }
9382
9383 val = hsw_read_dcomp(dev_priv);
9384 val |= D_COMP_COMP_FORCE;
9385 val &= ~D_COMP_COMP_DISABLE;
9386 hsw_write_dcomp(dev_priv, val);
9387
9388 val = I915_READ(LCPLL_CTL);
9389 val &= ~LCPLL_PLL_DISABLE;
9390 I915_WRITE(LCPLL_CTL, val);
9391
9392 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9393 DRM_ERROR("LCPLL not locked yet\n");
9394
9395 if (val & LCPLL_CD_SOURCE_FCLK) {
9396 val = I915_READ(LCPLL_CTL);
9397 val &= ~LCPLL_CD_SOURCE_FCLK;
9398 I915_WRITE(LCPLL_CTL, val);
9399
9400 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9401 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9402 DRM_ERROR("Switching back to LCPLL failed\n");
9403 }
9404
9405 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9406 intel_update_cdclk(dev_priv->dev);
9407}
9408
9409/*
9410 * Package states C8 and deeper are really deep PC states that can only be
9411 * reached when all the devices on the system allow it, so even if the graphics
9412 * device allows PC8+, it doesn't mean the system will actually get to these
9413 * states. Our driver only allows PC8+ when going into runtime PM.
9414 *
9415 * The requirements for PC8+ are that all the outputs are disabled, the power
9416 * well is disabled and most interrupts are disabled, and these are also
9417 * requirements for runtime PM. When these conditions are met, we manually do
9418 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9419 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9420 * hang the machine.
9421 *
9422 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9423 * the state of some registers, so when we come back from PC8+ we need to
9424 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9425 * need to take care of the registers kept by RC6. Notice that this happens even
9426 * if we don't put the device in PCI D3 state (which is what currently happens
9427 * because of the runtime PM support).
9428 *
9429 * For more, read "Display Sequences for Package C8" on the hardware
9430 * documentation.
9431 */
9432void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9433{
9434 struct drm_device *dev = dev_priv->dev;
9435 uint32_t val;
9436
9437 DRM_DEBUG_KMS("Enabling package C8+\n");
9438
9439 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9440 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9441 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9442 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9443 }
9444
9445 lpt_disable_clkout_dp(dev);
9446 hsw_disable_lcpll(dev_priv, true, true);
9447}
9448
9449void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9450{
9451 struct drm_device *dev = dev_priv->dev;
9452 uint32_t val;
9453
9454 DRM_DEBUG_KMS("Disabling package C8+\n");
9455
9456 hsw_restore_lcpll(dev_priv);
9457 lpt_init_pch_refclk(dev);
9458
9459 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9460 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9461 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9462 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9463 }
9464
9465 intel_prepare_ddi(dev);
9466}
9467
9468static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9469{
9470 struct drm_device *dev = old_state->dev;
9471 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9472
9473 broxton_set_cdclk(dev, req_cdclk);
9474}
9475
9476/* compute the max rate for new configuration */
9477static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9478{
9479 struct intel_crtc *intel_crtc;
9480 struct intel_crtc_state *crtc_state;
9481 int max_pixel_rate = 0;
9482
9483 for_each_intel_crtc(state->dev, intel_crtc) {
9484 int pixel_rate;
9485
9486 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9487 if (IS_ERR(crtc_state))
9488 return PTR_ERR(crtc_state);
9489
9490 if (!crtc_state->base.enable)
9491 continue;
9492
9493 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9494
9495 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9496 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9497 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9498
9499 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9500 }
9501
9502 return max_pixel_rate;
9503}
9504
9505static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9506{
9507 struct drm_i915_private *dev_priv = dev->dev_private;
9508 uint32_t val, data;
9509 int ret;
9510
9511 if (WARN((I915_READ(LCPLL_CTL) &
9512 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9513 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9514 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9515 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9516 "trying to change cdclk frequency with cdclk not enabled\n"))
9517 return;
9518
9519 mutex_lock(&dev_priv->rps.hw_lock);
9520 ret = sandybridge_pcode_write(dev_priv,
9521 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9522 mutex_unlock(&dev_priv->rps.hw_lock);
9523 if (ret) {
9524 DRM_ERROR("failed to inform pcode about cdclk change\n");
9525 return;
9526 }
9527
9528 val = I915_READ(LCPLL_CTL);
9529 val |= LCPLL_CD_SOURCE_FCLK;
9530 I915_WRITE(LCPLL_CTL, val);
9531
9532 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9533 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9534 DRM_ERROR("Switching to FCLK failed\n");
9535
9536 val = I915_READ(LCPLL_CTL);
9537 val &= ~LCPLL_CLK_FREQ_MASK;
9538
9539 switch (cdclk) {
9540 case 450000:
9541 val |= LCPLL_CLK_FREQ_450;
9542 data = 0;
9543 break;
9544 case 540000:
9545 val |= LCPLL_CLK_FREQ_54O_BDW;
9546 data = 1;
9547 break;
9548 case 337500:
9549 val |= LCPLL_CLK_FREQ_337_5_BDW;
9550 data = 2;
9551 break;
9552 case 675000:
9553 val |= LCPLL_CLK_FREQ_675_BDW;
9554 data = 3;
9555 break;
9556 default:
9557 WARN(1, "invalid cdclk frequency\n");
9558 return;
9559 }
9560
9561 I915_WRITE(LCPLL_CTL, val);
9562
9563 val = I915_READ(LCPLL_CTL);
9564 val &= ~LCPLL_CD_SOURCE_FCLK;
9565 I915_WRITE(LCPLL_CTL, val);
9566
9567 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9568 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9569 DRM_ERROR("Switching back to LCPLL failed\n");
9570
9571 mutex_lock(&dev_priv->rps.hw_lock);
9572 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9573 mutex_unlock(&dev_priv->rps.hw_lock);
9574
9575 intel_update_cdclk(dev);
9576
9577 WARN(cdclk != dev_priv->cdclk_freq,
9578 "cdclk requested %d kHz but got %d kHz\n",
9579 cdclk, dev_priv->cdclk_freq);
9580}
9581
9582static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9583{
9584 struct drm_i915_private *dev_priv = to_i915(state->dev);
9585 int max_pixclk = ilk_max_pixel_rate(state);
9586 int cdclk;
9587
9588 /*
9589 * FIXME should also account for plane ratio
9590 * once 64bpp pixel formats are supported.
9591 */
9592 if (max_pixclk > 540000)
9593 cdclk = 675000;
9594 else if (max_pixclk > 450000)
9595 cdclk = 540000;
9596 else if (max_pixclk > 337500)
9597 cdclk = 450000;
9598 else
9599 cdclk = 337500;
9600
9601 /*
9602 * FIXME move the cdclk caclulation to
9603 * compute_config() so we can fail gracegully.
9604 */
9605 if (cdclk > dev_priv->max_cdclk_freq) {
9606 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9607 cdclk, dev_priv->max_cdclk_freq);
9608 cdclk = dev_priv->max_cdclk_freq;
9609 }
9610
9611 to_intel_atomic_state(state)->cdclk = cdclk;
9612
9613 return 0;
9614}
9615
9616static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9617{
9618 struct drm_device *dev = old_state->dev;
9619 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9620
9621 broadwell_set_cdclk(dev, req_cdclk);
9622}
9623
9624static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9625 struct intel_crtc_state *crtc_state)
9626{
9627 if (!intel_ddi_pll_select(crtc, crtc_state))
9628 return -EINVAL;
9629
9630 crtc->lowfreq_avail = false;
9631
9632 return 0;
9633}
9634
9635static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9636 enum port port,
9637 struct intel_crtc_state *pipe_config)
9638{
9639 switch (port) {
9640 case PORT_A:
9641 pipe_config->ddi_pll_sel = SKL_DPLL0;
9642 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9643 break;
9644 case PORT_B:
9645 pipe_config->ddi_pll_sel = SKL_DPLL1;
9646 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9647 break;
9648 case PORT_C:
9649 pipe_config->ddi_pll_sel = SKL_DPLL2;
9650 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9651 break;
9652 default:
9653 DRM_ERROR("Incorrect port type\n");
9654 }
9655}
9656
9657static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9658 enum port port,
9659 struct intel_crtc_state *pipe_config)
9660{
9661 u32 temp, dpll_ctl1;
9662
9663 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9664 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9665
9666 switch (pipe_config->ddi_pll_sel) {
9667 case SKL_DPLL0:
9668 /*
9669 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9670 * of the shared DPLL framework and thus needs to be read out
9671 * separately
9672 */
9673 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9674 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9675 break;
9676 case SKL_DPLL1:
9677 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9678 break;
9679 case SKL_DPLL2:
9680 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9681 break;
9682 case SKL_DPLL3:
9683 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9684 break;
9685 }
9686}
9687
9688static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9689 enum port port,
9690 struct intel_crtc_state *pipe_config)
9691{
9692 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9693
9694 switch (pipe_config->ddi_pll_sel) {
9695 case PORT_CLK_SEL_WRPLL1:
9696 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9697 break;
9698 case PORT_CLK_SEL_WRPLL2:
9699 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9700 break;
9701 }
9702}
9703
9704static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9705 struct intel_crtc_state *pipe_config)
9706{
9707 struct drm_device *dev = crtc->base.dev;
9708 struct drm_i915_private *dev_priv = dev->dev_private;
9709 struct intel_shared_dpll *pll;
9710 enum port port;
9711 uint32_t tmp;
9712
9713 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9714
9715 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9716
9717 if (IS_SKYLAKE(dev))
9718 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9719 else if (IS_BROXTON(dev))
9720 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9721 else
9722 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9723
9724 if (pipe_config->shared_dpll >= 0) {
9725 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9726
9727 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9728 &pipe_config->dpll_hw_state));
9729 }
9730
9731 /*
9732 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9733 * DDI E. So just check whether this pipe is wired to DDI E and whether
9734 * the PCH transcoder is on.
9735 */
9736 if (INTEL_INFO(dev)->gen < 9 &&
9737 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9738 pipe_config->has_pch_encoder = true;
9739
9740 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9741 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9742 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9743
9744 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9745 }
9746}
9747
9748static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9749 struct intel_crtc_state *pipe_config)
9750{
9751 struct drm_device *dev = crtc->base.dev;
9752 struct drm_i915_private *dev_priv = dev->dev_private;
9753 enum intel_display_power_domain pfit_domain;
9754 uint32_t tmp;
9755
9756 if (!intel_display_power_is_enabled(dev_priv,
9757 POWER_DOMAIN_PIPE(crtc->pipe)))
9758 return false;
9759
9760 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9761 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9762
9763 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9764 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9765 enum pipe trans_edp_pipe;
9766 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9767 default:
9768 WARN(1, "unknown pipe linked to edp transcoder\n");
9769 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9770 case TRANS_DDI_EDP_INPUT_A_ON:
9771 trans_edp_pipe = PIPE_A;
9772 break;
9773 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9774 trans_edp_pipe = PIPE_B;
9775 break;
9776 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9777 trans_edp_pipe = PIPE_C;
9778 break;
9779 }
9780
9781 if (trans_edp_pipe == crtc->pipe)
9782 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9783 }
9784
9785 if (!intel_display_power_is_enabled(dev_priv,
9786 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9787 return false;
9788
9789 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9790 if (!(tmp & PIPECONF_ENABLE))
9791 return false;
9792
9793 haswell_get_ddi_port_state(crtc, pipe_config);
9794
9795 intel_get_pipe_timings(crtc, pipe_config);
9796
9797 if (INTEL_INFO(dev)->gen >= 9) {
9798 skl_init_scalers(dev, crtc, pipe_config);
9799 }
9800
9801 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9802
9803 if (INTEL_INFO(dev)->gen >= 9) {
9804 pipe_config->scaler_state.scaler_id = -1;
9805 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9806 }
9807
9808 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9809 if (INTEL_INFO(dev)->gen == 9)
9810 skylake_get_pfit_config(crtc, pipe_config);
9811 else if (INTEL_INFO(dev)->gen < 9)
9812 ironlake_get_pfit_config(crtc, pipe_config);
9813 else
9814 MISSING_CASE(INTEL_INFO(dev)->gen);
9815 }
9816
9817 if (IS_HASWELL(dev))
9818 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9819 (I915_READ(IPS_CTL) & IPS_ENABLE);
9820
9821 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9822 pipe_config->pixel_multiplier =
9823 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9824 } else {
9825 pipe_config->pixel_multiplier = 1;
9826 }
9827
9828 return true;
9829}
9830
9831static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9832{
9833 struct drm_device *dev = crtc->dev;
9834 struct drm_i915_private *dev_priv = dev->dev_private;
9835 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9836 uint32_t cntl = 0, size = 0;
9837
9838 if (base) {
9839 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9840 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9841 unsigned int stride = roundup_pow_of_two(width) * 4;
9842
9843 switch (stride) {
9844 default:
9845 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9846 width, stride);
9847 stride = 256;
9848 /* fallthrough */
9849 case 256:
9850 case 512:
9851 case 1024:
9852 case 2048:
9853 break;
9854 }
9855
9856 cntl |= CURSOR_ENABLE |
9857 CURSOR_GAMMA_ENABLE |
9858 CURSOR_FORMAT_ARGB |
9859 CURSOR_STRIDE(stride);
9860
9861 size = (height << 12) | width;
9862 }
9863
9864 if (intel_crtc->cursor_cntl != 0 &&
9865 (intel_crtc->cursor_base != base ||
9866 intel_crtc->cursor_size != size ||
9867 intel_crtc->cursor_cntl != cntl)) {
9868 /* On these chipsets we can only modify the base/size/stride
9869 * whilst the cursor is disabled.
9870 */
9871 I915_WRITE(_CURACNTR, 0);
9872 POSTING_READ(_CURACNTR);
9873 intel_crtc->cursor_cntl = 0;
9874 }
9875
9876 if (intel_crtc->cursor_base != base) {
9877 I915_WRITE(_CURABASE, base);
9878 intel_crtc->cursor_base = base;
9879 }
9880
9881 if (intel_crtc->cursor_size != size) {
9882 I915_WRITE(CURSIZE, size);
9883 intel_crtc->cursor_size = size;
9884 }
9885
9886 if (intel_crtc->cursor_cntl != cntl) {
9887 I915_WRITE(_CURACNTR, cntl);
9888 POSTING_READ(_CURACNTR);
9889 intel_crtc->cursor_cntl = cntl;
9890 }
9891}
9892
9893static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9894{
9895 struct drm_device *dev = crtc->dev;
9896 struct drm_i915_private *dev_priv = dev->dev_private;
9897 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9898 int pipe = intel_crtc->pipe;
9899 uint32_t cntl;
9900
9901 cntl = 0;
9902 if (base) {
9903 cntl = MCURSOR_GAMMA_ENABLE;
9904 switch (intel_crtc->base.cursor->state->crtc_w) {
9905 case 64:
9906 cntl |= CURSOR_MODE_64_ARGB_AX;
9907 break;
9908 case 128:
9909 cntl |= CURSOR_MODE_128_ARGB_AX;
9910 break;
9911 case 256:
9912 cntl |= CURSOR_MODE_256_ARGB_AX;
9913 break;
9914 default:
9915 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9916 return;
9917 }
9918 cntl |= pipe << 28; /* Connect to correct pipe */
9919
9920 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9921 cntl |= CURSOR_PIPE_CSC_ENABLE;
9922 }
9923
9924 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9925 cntl |= CURSOR_ROTATE_180;
9926
9927 if (intel_crtc->cursor_cntl != cntl) {
9928 I915_WRITE(CURCNTR(pipe), cntl);
9929 POSTING_READ(CURCNTR(pipe));
9930 intel_crtc->cursor_cntl = cntl;
9931 }
9932
9933 /* and commit changes on next vblank */
9934 I915_WRITE(CURBASE(pipe), base);
9935 POSTING_READ(CURBASE(pipe));
9936
9937 intel_crtc->cursor_base = base;
9938}
9939
9940/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9941static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9942 bool on)
9943{
9944 struct drm_device *dev = crtc->dev;
9945 struct drm_i915_private *dev_priv = dev->dev_private;
9946 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9947 int pipe = intel_crtc->pipe;
9948 int x = crtc->cursor_x;
9949 int y = crtc->cursor_y;
9950 u32 base = 0, pos = 0;
9951
9952 if (on)
9953 base = intel_crtc->cursor_addr;
9954
9955 if (x >= intel_crtc->config->pipe_src_w)
9956 base = 0;
9957
9958 if (y >= intel_crtc->config->pipe_src_h)
9959 base = 0;
9960
9961 if (x < 0) {
9962 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
9963 base = 0;
9964
9965 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9966 x = -x;
9967 }
9968 pos |= x << CURSOR_X_SHIFT;
9969
9970 if (y < 0) {
9971 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
9972 base = 0;
9973
9974 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9975 y = -y;
9976 }
9977 pos |= y << CURSOR_Y_SHIFT;
9978
9979 if (base == 0 && intel_crtc->cursor_base == 0)
9980 return;
9981
9982 I915_WRITE(CURPOS(pipe), pos);
9983
9984 /* ILK+ do this automagically */
9985 if (HAS_GMCH_DISPLAY(dev) &&
9986 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9987 base += (intel_crtc->base.cursor->state->crtc_h *
9988 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
9989 }
9990
9991 if (IS_845G(dev) || IS_I865G(dev))
9992 i845_update_cursor(crtc, base);
9993 else
9994 i9xx_update_cursor(crtc, base);
9995}
9996
9997static bool cursor_size_ok(struct drm_device *dev,
9998 uint32_t width, uint32_t height)
9999{
10000 if (width == 0 || height == 0)
10001 return false;
10002
10003 /*
10004 * 845g/865g are special in that they are only limited by
10005 * the width of their cursors, the height is arbitrary up to
10006 * the precision of the register. Everything else requires
10007 * square cursors, limited to a few power-of-two sizes.
10008 */
10009 if (IS_845G(dev) || IS_I865G(dev)) {
10010 if ((width & 63) != 0)
10011 return false;
10012
10013 if (width > (IS_845G(dev) ? 64 : 512))
10014 return false;
10015
10016 if (height > 1023)
10017 return false;
10018 } else {
10019 switch (width | height) {
10020 case 256:
10021 case 128:
10022 if (IS_GEN2(dev))
10023 return false;
10024 case 64:
10025 break;
10026 default:
10027 return false;
10028 }
10029 }
10030
10031 return true;
10032}
10033
10034static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10035 u16 *blue, uint32_t start, uint32_t size)
10036{
10037 int end = (start + size > 256) ? 256 : start + size, i;
10038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10039
10040 for (i = start; i < end; i++) {
10041 intel_crtc->lut_r[i] = red[i] >> 8;
10042 intel_crtc->lut_g[i] = green[i] >> 8;
10043 intel_crtc->lut_b[i] = blue[i] >> 8;
10044 }
10045
10046 intel_crtc_load_lut(crtc);
10047}
10048
10049/* VESA 640x480x72Hz mode to set on the pipe */
10050static struct drm_display_mode load_detect_mode = {
10051 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10052 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10053};
10054
10055struct drm_framebuffer *
10056__intel_framebuffer_create(struct drm_device *dev,
10057 struct drm_mode_fb_cmd2 *mode_cmd,
10058 struct drm_i915_gem_object *obj)
10059{
10060 struct intel_framebuffer *intel_fb;
10061 int ret;
10062
10063 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10064 if (!intel_fb) {
10065 drm_gem_object_unreference(&obj->base);
10066 return ERR_PTR(-ENOMEM);
10067 }
10068
10069 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10070 if (ret)
10071 goto err;
10072
10073 return &intel_fb->base;
10074err:
10075 drm_gem_object_unreference(&obj->base);
10076 kfree(intel_fb);
10077
10078 return ERR_PTR(ret);
10079}
10080
10081static struct drm_framebuffer *
10082intel_framebuffer_create(struct drm_device *dev,
10083 struct drm_mode_fb_cmd2 *mode_cmd,
10084 struct drm_i915_gem_object *obj)
10085{
10086 struct drm_framebuffer *fb;
10087 int ret;
10088
10089 ret = i915_mutex_lock_interruptible(dev);
10090 if (ret)
10091 return ERR_PTR(ret);
10092 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10093 mutex_unlock(&dev->struct_mutex);
10094
10095 return fb;
10096}
10097
10098static u32
10099intel_framebuffer_pitch_for_width(int width, int bpp)
10100{
10101 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10102 return ALIGN(pitch, 64);
10103}
10104
10105static u32
10106intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10107{
10108 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10109 return PAGE_ALIGN(pitch * mode->vdisplay);
10110}
10111
10112static struct drm_framebuffer *
10113intel_framebuffer_create_for_mode(struct drm_device *dev,
10114 struct drm_display_mode *mode,
10115 int depth, int bpp)
10116{
10117 struct drm_i915_gem_object *obj;
10118 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10119
10120 obj = i915_gem_alloc_object(dev,
10121 intel_framebuffer_size_for_mode(mode, bpp));
10122 if (obj == NULL)
10123 return ERR_PTR(-ENOMEM);
10124
10125 mode_cmd.width = mode->hdisplay;
10126 mode_cmd.height = mode->vdisplay;
10127 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10128 bpp);
10129 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10130
10131 return intel_framebuffer_create(dev, &mode_cmd, obj);
10132}
10133
10134static struct drm_framebuffer *
10135mode_fits_in_fbdev(struct drm_device *dev,
10136 struct drm_display_mode *mode)
10137{
10138#ifdef CONFIG_DRM_FBDEV_EMULATION
10139 struct drm_i915_private *dev_priv = dev->dev_private;
10140 struct drm_i915_gem_object *obj;
10141 struct drm_framebuffer *fb;
10142
10143 if (!dev_priv->fbdev)
10144 return NULL;
10145
10146 if (!dev_priv->fbdev->fb)
10147 return NULL;
10148
10149 obj = dev_priv->fbdev->fb->obj;
10150 BUG_ON(!obj);
10151
10152 fb = &dev_priv->fbdev->fb->base;
10153 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10154 fb->bits_per_pixel))
10155 return NULL;
10156
10157 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10158 return NULL;
10159
10160 return fb;
10161#else
10162 return NULL;
10163#endif
10164}
10165
10166static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10167 struct drm_crtc *crtc,
10168 struct drm_display_mode *mode,
10169 struct drm_framebuffer *fb,
10170 int x, int y)
10171{
10172 struct drm_plane_state *plane_state;
10173 int hdisplay, vdisplay;
10174 int ret;
10175
10176 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10177 if (IS_ERR(plane_state))
10178 return PTR_ERR(plane_state);
10179
10180 if (mode)
10181 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10182 else
10183 hdisplay = vdisplay = 0;
10184
10185 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10186 if (ret)
10187 return ret;
10188 drm_atomic_set_fb_for_plane(plane_state, fb);
10189 plane_state->crtc_x = 0;
10190 plane_state->crtc_y = 0;
10191 plane_state->crtc_w = hdisplay;
10192 plane_state->crtc_h = vdisplay;
10193 plane_state->src_x = x << 16;
10194 plane_state->src_y = y << 16;
10195 plane_state->src_w = hdisplay << 16;
10196 plane_state->src_h = vdisplay << 16;
10197
10198 return 0;
10199}
10200
10201bool intel_get_load_detect_pipe(struct drm_connector *connector,
10202 struct drm_display_mode *mode,
10203 struct intel_load_detect_pipe *old,
10204 struct drm_modeset_acquire_ctx *ctx)
10205{
10206 struct intel_crtc *intel_crtc;
10207 struct intel_encoder *intel_encoder =
10208 intel_attached_encoder(connector);
10209 struct drm_crtc *possible_crtc;
10210 struct drm_encoder *encoder = &intel_encoder->base;
10211 struct drm_crtc *crtc = NULL;
10212 struct drm_device *dev = encoder->dev;
10213 struct drm_framebuffer *fb;
10214 struct drm_mode_config *config = &dev->mode_config;
10215 struct drm_atomic_state *state = NULL;
10216 struct drm_connector_state *connector_state;
10217 struct intel_crtc_state *crtc_state;
10218 int ret, i = -1;
10219
10220 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10221 connector->base.id, connector->name,
10222 encoder->base.id, encoder->name);
10223
10224retry:
10225 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10226 if (ret)
10227 goto fail;
10228
10229 /*
10230 * Algorithm gets a little messy:
10231 *
10232 * - if the connector already has an assigned crtc, use it (but make
10233 * sure it's on first)
10234 *
10235 * - try to find the first unused crtc that can drive this connector,
10236 * and use that if we find one
10237 */
10238
10239 /* See if we already have a CRTC for this connector */
10240 if (encoder->crtc) {
10241 crtc = encoder->crtc;
10242
10243 ret = drm_modeset_lock(&crtc->mutex, ctx);
10244 if (ret)
10245 goto fail;
10246 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10247 if (ret)
10248 goto fail;
10249
10250 old->dpms_mode = connector->dpms;
10251 old->load_detect_temp = false;
10252
10253 /* Make sure the crtc and connector are running */
10254 if (connector->dpms != DRM_MODE_DPMS_ON)
10255 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10256
10257 return true;
10258 }
10259
10260 /* Find an unused one (if possible) */
10261 for_each_crtc(dev, possible_crtc) {
10262 i++;
10263 if (!(encoder->possible_crtcs & (1 << i)))
10264 continue;
10265 if (possible_crtc->state->enable)
10266 continue;
10267
10268 crtc = possible_crtc;
10269 break;
10270 }
10271
10272 /*
10273 * If we didn't find an unused CRTC, don't use any.
10274 */
10275 if (!crtc) {
10276 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10277 goto fail;
10278 }
10279
10280 ret = drm_modeset_lock(&crtc->mutex, ctx);
10281 if (ret)
10282 goto fail;
10283 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10284 if (ret)
10285 goto fail;
10286
10287 intel_crtc = to_intel_crtc(crtc);
10288 old->dpms_mode = connector->dpms;
10289 old->load_detect_temp = true;
10290 old->release_fb = NULL;
10291
10292 state = drm_atomic_state_alloc(dev);
10293 if (!state)
10294 return false;
10295
10296 state->acquire_ctx = ctx;
10297
10298 connector_state = drm_atomic_get_connector_state(state, connector);
10299 if (IS_ERR(connector_state)) {
10300 ret = PTR_ERR(connector_state);
10301 goto fail;
10302 }
10303
10304 connector_state->crtc = crtc;
10305 connector_state->best_encoder = &intel_encoder->base;
10306
10307 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10308 if (IS_ERR(crtc_state)) {
10309 ret = PTR_ERR(crtc_state);
10310 goto fail;
10311 }
10312
10313 crtc_state->base.active = crtc_state->base.enable = true;
10314
10315 if (!mode)
10316 mode = &load_detect_mode;
10317
10318 /* We need a framebuffer large enough to accommodate all accesses
10319 * that the plane may generate whilst we perform load detection.
10320 * We can not rely on the fbcon either being present (we get called
10321 * during its initialisation to detect all boot displays, or it may
10322 * not even exist) or that it is large enough to satisfy the
10323 * requested mode.
10324 */
10325 fb = mode_fits_in_fbdev(dev, mode);
10326 if (fb == NULL) {
10327 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10328 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10329 old->release_fb = fb;
10330 } else
10331 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10332 if (IS_ERR(fb)) {
10333 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10334 goto fail;
10335 }
10336
10337 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10338 if (ret)
10339 goto fail;
10340
10341 drm_mode_copy(&crtc_state->base.mode, mode);
10342
10343 if (drm_atomic_commit(state)) {
10344 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10345 if (old->release_fb)
10346 old->release_fb->funcs->destroy(old->release_fb);
10347 goto fail;
10348 }
10349 crtc->primary->crtc = crtc;
10350
10351 /* let the connector get through one full cycle before testing */
10352 intel_wait_for_vblank(dev, intel_crtc->pipe);
10353 return true;
10354
10355fail:
10356 drm_atomic_state_free(state);
10357 state = NULL;
10358
10359 if (ret == -EDEADLK) {
10360 drm_modeset_backoff(ctx);
10361 goto retry;
10362 }
10363
10364 return false;
10365}
10366
10367void intel_release_load_detect_pipe(struct drm_connector *connector,
10368 struct intel_load_detect_pipe *old,
10369 struct drm_modeset_acquire_ctx *ctx)
10370{
10371 struct drm_device *dev = connector->dev;
10372 struct intel_encoder *intel_encoder =
10373 intel_attached_encoder(connector);
10374 struct drm_encoder *encoder = &intel_encoder->base;
10375 struct drm_crtc *crtc = encoder->crtc;
10376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10377 struct drm_atomic_state *state;
10378 struct drm_connector_state *connector_state;
10379 struct intel_crtc_state *crtc_state;
10380 int ret;
10381
10382 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10383 connector->base.id, connector->name,
10384 encoder->base.id, encoder->name);
10385
10386 if (old->load_detect_temp) {
10387 state = drm_atomic_state_alloc(dev);
10388 if (!state)
10389 goto fail;
10390
10391 state->acquire_ctx = ctx;
10392
10393 connector_state = drm_atomic_get_connector_state(state, connector);
10394 if (IS_ERR(connector_state))
10395 goto fail;
10396
10397 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10398 if (IS_ERR(crtc_state))
10399 goto fail;
10400
10401 connector_state->best_encoder = NULL;
10402 connector_state->crtc = NULL;
10403
10404 crtc_state->base.enable = crtc_state->base.active = false;
10405
10406 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10407 0, 0);
10408 if (ret)
10409 goto fail;
10410
10411 ret = drm_atomic_commit(state);
10412 if (ret)
10413 goto fail;
10414
10415 if (old->release_fb) {
10416 drm_framebuffer_unregister_private(old->release_fb);
10417 drm_framebuffer_unreference(old->release_fb);
10418 }
10419
10420 return;
10421 }
10422
10423 /* Switch crtc and encoder back off if necessary */
10424 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10425 connector->funcs->dpms(connector, old->dpms_mode);
10426
10427 return;
10428fail:
10429 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10430 drm_atomic_state_free(state);
10431}
10432
10433static int i9xx_pll_refclk(struct drm_device *dev,
10434 const struct intel_crtc_state *pipe_config)
10435{
10436 struct drm_i915_private *dev_priv = dev->dev_private;
10437 u32 dpll = pipe_config->dpll_hw_state.dpll;
10438
10439 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10440 return dev_priv->vbt.lvds_ssc_freq;
10441 else if (HAS_PCH_SPLIT(dev))
10442 return 120000;
10443 else if (!IS_GEN2(dev))
10444 return 96000;
10445 else
10446 return 48000;
10447}
10448
10449/* Returns the clock of the currently programmed mode of the given pipe. */
10450static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10451 struct intel_crtc_state *pipe_config)
10452{
10453 struct drm_device *dev = crtc->base.dev;
10454 struct drm_i915_private *dev_priv = dev->dev_private;
10455 int pipe = pipe_config->cpu_transcoder;
10456 u32 dpll = pipe_config->dpll_hw_state.dpll;
10457 u32 fp;
10458 intel_clock_t clock;
10459 int port_clock;
10460 int refclk = i9xx_pll_refclk(dev, pipe_config);
10461
10462 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10463 fp = pipe_config->dpll_hw_state.fp0;
10464 else
10465 fp = pipe_config->dpll_hw_state.fp1;
10466
10467 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10468 if (IS_PINEVIEW(dev)) {
10469 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10470 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10471 } else {
10472 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10473 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10474 }
10475
10476 if (!IS_GEN2(dev)) {
10477 if (IS_PINEVIEW(dev))
10478 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10479 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10480 else
10481 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10482 DPLL_FPA01_P1_POST_DIV_SHIFT);
10483
10484 switch (dpll & DPLL_MODE_MASK) {
10485 case DPLLB_MODE_DAC_SERIAL:
10486 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10487 5 : 10;
10488 break;
10489 case DPLLB_MODE_LVDS:
10490 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10491 7 : 14;
10492 break;
10493 default:
10494 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10495 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10496 return;
10497 }
10498
10499 if (IS_PINEVIEW(dev))
10500 port_clock = pnv_calc_dpll_params(refclk, &clock);
10501 else
10502 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10503 } else {
10504 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10505 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10506
10507 if (is_lvds) {
10508 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10509 DPLL_FPA01_P1_POST_DIV_SHIFT);
10510
10511 if (lvds & LVDS_CLKB_POWER_UP)
10512 clock.p2 = 7;
10513 else
10514 clock.p2 = 14;
10515 } else {
10516 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10517 clock.p1 = 2;
10518 else {
10519 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10520 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10521 }
10522 if (dpll & PLL_P2_DIVIDE_BY_4)
10523 clock.p2 = 4;
10524 else
10525 clock.p2 = 2;
10526 }
10527
10528 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10529 }
10530
10531 /*
10532 * This value includes pixel_multiplier. We will use
10533 * port_clock to compute adjusted_mode.crtc_clock in the
10534 * encoder's get_config() function.
10535 */
10536 pipe_config->port_clock = port_clock;
10537}
10538
10539int intel_dotclock_calculate(int link_freq,
10540 const struct intel_link_m_n *m_n)
10541{
10542 /*
10543 * The calculation for the data clock is:
10544 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10545 * But we want to avoid losing precison if possible, so:
10546 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10547 *
10548 * and the link clock is simpler:
10549 * link_clock = (m * link_clock) / n
10550 */
10551
10552 if (!m_n->link_n)
10553 return 0;
10554
10555 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10556}
10557
10558static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10559 struct intel_crtc_state *pipe_config)
10560{
10561 struct drm_device *dev = crtc->base.dev;
10562
10563 /* read out port_clock from the DPLL */
10564 i9xx_crtc_clock_get(crtc, pipe_config);
10565
10566 /*
10567 * This value does not include pixel_multiplier.
10568 * We will check that port_clock and adjusted_mode.crtc_clock
10569 * agree once we know their relationship in the encoder's
10570 * get_config() function.
10571 */
10572 pipe_config->base.adjusted_mode.crtc_clock =
10573 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10574 &pipe_config->fdi_m_n);
10575}
10576
10577/** Returns the currently programmed mode of the given pipe. */
10578struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10579 struct drm_crtc *crtc)
10580{
10581 struct drm_i915_private *dev_priv = dev->dev_private;
10582 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10583 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10584 struct drm_display_mode *mode;
10585 struct intel_crtc_state pipe_config;
10586 int htot = I915_READ(HTOTAL(cpu_transcoder));
10587 int hsync = I915_READ(HSYNC(cpu_transcoder));
10588 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10589 int vsync = I915_READ(VSYNC(cpu_transcoder));
10590 enum pipe pipe = intel_crtc->pipe;
10591
10592 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10593 if (!mode)
10594 return NULL;
10595
10596 /*
10597 * Construct a pipe_config sufficient for getting the clock info
10598 * back out of crtc_clock_get.
10599 *
10600 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10601 * to use a real value here instead.
10602 */
10603 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10604 pipe_config.pixel_multiplier = 1;
10605 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10606 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10607 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10608 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10609
10610 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10611 mode->hdisplay = (htot & 0xffff) + 1;
10612 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10613 mode->hsync_start = (hsync & 0xffff) + 1;
10614 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10615 mode->vdisplay = (vtot & 0xffff) + 1;
10616 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10617 mode->vsync_start = (vsync & 0xffff) + 1;
10618 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10619
10620 drm_mode_set_name(mode);
10621
10622 return mode;
10623}
10624
10625void intel_mark_busy(struct drm_device *dev)
10626{
10627 struct drm_i915_private *dev_priv = dev->dev_private;
10628
10629 if (dev_priv->mm.busy)
10630 return;
10631
10632 intel_runtime_pm_get(dev_priv);
10633 i915_update_gfx_val(dev_priv);
10634 if (INTEL_INFO(dev)->gen >= 6)
10635 gen6_rps_busy(dev_priv);
10636 dev_priv->mm.busy = true;
10637}
10638
10639void intel_mark_idle(struct drm_device *dev)
10640{
10641 struct drm_i915_private *dev_priv = dev->dev_private;
10642
10643 if (!dev_priv->mm.busy)
10644 return;
10645
10646 dev_priv->mm.busy = false;
10647
10648 if (INTEL_INFO(dev)->gen >= 6)
10649 gen6_rps_idle(dev->dev_private);
10650
10651 intel_runtime_pm_put(dev_priv);
10652}
10653
10654static void intel_crtc_destroy(struct drm_crtc *crtc)
10655{
10656 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10657 struct drm_device *dev = crtc->dev;
10658 struct intel_unpin_work *work;
10659
10660 spin_lock_irq(&dev->event_lock);
10661 work = intel_crtc->unpin_work;
10662 intel_crtc->unpin_work = NULL;
10663 spin_unlock_irq(&dev->event_lock);
10664
10665 if (work) {
10666 cancel_work_sync(&work->work);
10667 kfree(work);
10668 }
10669
10670 drm_crtc_cleanup(crtc);
10671
10672 kfree(intel_crtc);
10673}
10674
10675static void intel_unpin_work_fn(struct work_struct *__work)
10676{
10677 struct intel_unpin_work *work =
10678 container_of(__work, struct intel_unpin_work, work);
10679 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10680 struct drm_device *dev = crtc->base.dev;
10681 struct drm_plane *primary = crtc->base.primary;
10682
10683 mutex_lock(&dev->struct_mutex);
10684 intel_unpin_fb_obj(work->old_fb, primary->state);
10685 drm_gem_object_unreference(&work->pending_flip_obj->base);
10686
10687 if (work->flip_queued_req)
10688 i915_gem_request_assign(&work->flip_queued_req, NULL);
10689 mutex_unlock(&dev->struct_mutex);
10690
10691 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10692 drm_framebuffer_unreference(work->old_fb);
10693
10694 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10695 atomic_dec(&crtc->unpin_work_count);
10696
10697 kfree(work);
10698}
10699
10700static void do_intel_finish_page_flip(struct drm_device *dev,
10701 struct drm_crtc *crtc)
10702{
10703 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10704 struct intel_unpin_work *work;
10705 unsigned long flags;
10706
10707 /* Ignore early vblank irqs */
10708 if (intel_crtc == NULL)
10709 return;
10710
10711 /*
10712 * This is called both by irq handlers and the reset code (to complete
10713 * lost pageflips) so needs the full irqsave spinlocks.
10714 */
10715 spin_lock_irqsave(&dev->event_lock, flags);
10716 work = intel_crtc->unpin_work;
10717
10718 /* Ensure we don't miss a work->pending update ... */
10719 smp_rmb();
10720
10721 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10722 spin_unlock_irqrestore(&dev->event_lock, flags);
10723 return;
10724 }
10725
10726 page_flip_completed(intel_crtc);
10727
10728 spin_unlock_irqrestore(&dev->event_lock, flags);
10729}
10730
10731void intel_finish_page_flip(struct drm_device *dev, int pipe)
10732{
10733 struct drm_i915_private *dev_priv = dev->dev_private;
10734 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10735
10736 do_intel_finish_page_flip(dev, crtc);
10737}
10738
10739void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10740{
10741 struct drm_i915_private *dev_priv = dev->dev_private;
10742 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10743
10744 do_intel_finish_page_flip(dev, crtc);
10745}
10746
10747/* Is 'a' after or equal to 'b'? */
10748static bool g4x_flip_count_after_eq(u32 a, u32 b)
10749{
10750 return !((a - b) & 0x80000000);
10751}
10752
10753static bool page_flip_finished(struct intel_crtc *crtc)
10754{
10755 struct drm_device *dev = crtc->base.dev;
10756 struct drm_i915_private *dev_priv = dev->dev_private;
10757
10758 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10759 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10760 return true;
10761
10762 /*
10763 * The relevant registers doen't exist on pre-ctg.
10764 * As the flip done interrupt doesn't trigger for mmio
10765 * flips on gmch platforms, a flip count check isn't
10766 * really needed there. But since ctg has the registers,
10767 * include it in the check anyway.
10768 */
10769 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10770 return true;
10771
10772 /*
10773 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10774 * used the same base address. In that case the mmio flip might
10775 * have completed, but the CS hasn't even executed the flip yet.
10776 *
10777 * A flip count check isn't enough as the CS might have updated
10778 * the base address just after start of vblank, but before we
10779 * managed to process the interrupt. This means we'd complete the
10780 * CS flip too soon.
10781 *
10782 * Combining both checks should get us a good enough result. It may
10783 * still happen that the CS flip has been executed, but has not
10784 * yet actually completed. But in case the base address is the same
10785 * anyway, we don't really care.
10786 */
10787 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10788 crtc->unpin_work->gtt_offset &&
10789 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10790 crtc->unpin_work->flip_count);
10791}
10792
10793void intel_prepare_page_flip(struct drm_device *dev, int plane)
10794{
10795 struct drm_i915_private *dev_priv = dev->dev_private;
10796 struct intel_crtc *intel_crtc =
10797 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10798 unsigned long flags;
10799
10800
10801 /*
10802 * This is called both by irq handlers and the reset code (to complete
10803 * lost pageflips) so needs the full irqsave spinlocks.
10804 *
10805 * NB: An MMIO update of the plane base pointer will also
10806 * generate a page-flip completion irq, i.e. every modeset
10807 * is also accompanied by a spurious intel_prepare_page_flip().
10808 */
10809 spin_lock_irqsave(&dev->event_lock, flags);
10810 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10811 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10812 spin_unlock_irqrestore(&dev->event_lock, flags);
10813}
10814
10815static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10816{
10817 /* Ensure that the work item is consistent when activating it ... */
10818 smp_wmb();
10819 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10820 /* and that it is marked active as soon as the irq could fire. */
10821 smp_wmb();
10822}
10823
10824static int intel_gen2_queue_flip(struct drm_device *dev,
10825 struct drm_crtc *crtc,
10826 struct drm_framebuffer *fb,
10827 struct drm_i915_gem_object *obj,
10828 struct drm_i915_gem_request *req,
10829 uint32_t flags)
10830{
10831 struct intel_engine_cs *ring = req->ring;
10832 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10833 u32 flip_mask;
10834 int ret;
10835
10836 ret = intel_ring_begin(req, 6);
10837 if (ret)
10838 return ret;
10839
10840 /* Can't queue multiple flips, so wait for the previous
10841 * one to finish before executing the next.
10842 */
10843 if (intel_crtc->plane)
10844 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10845 else
10846 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10847 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10848 intel_ring_emit(ring, MI_NOOP);
10849 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10850 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10851 intel_ring_emit(ring, fb->pitches[0]);
10852 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10853 intel_ring_emit(ring, 0); /* aux display base address, unused */
10854
10855 intel_mark_page_flip_active(intel_crtc);
10856 return 0;
10857}
10858
10859static int intel_gen3_queue_flip(struct drm_device *dev,
10860 struct drm_crtc *crtc,
10861 struct drm_framebuffer *fb,
10862 struct drm_i915_gem_object *obj,
10863 struct drm_i915_gem_request *req,
10864 uint32_t flags)
10865{
10866 struct intel_engine_cs *ring = req->ring;
10867 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10868 u32 flip_mask;
10869 int ret;
10870
10871 ret = intel_ring_begin(req, 6);
10872 if (ret)
10873 return ret;
10874
10875 if (intel_crtc->plane)
10876 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10877 else
10878 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10879 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10880 intel_ring_emit(ring, MI_NOOP);
10881 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10882 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10883 intel_ring_emit(ring, fb->pitches[0]);
10884 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10885 intel_ring_emit(ring, MI_NOOP);
10886
10887 intel_mark_page_flip_active(intel_crtc);
10888 return 0;
10889}
10890
10891static int intel_gen4_queue_flip(struct drm_device *dev,
10892 struct drm_crtc *crtc,
10893 struct drm_framebuffer *fb,
10894 struct drm_i915_gem_object *obj,
10895 struct drm_i915_gem_request *req,
10896 uint32_t flags)
10897{
10898 struct intel_engine_cs *ring = req->ring;
10899 struct drm_i915_private *dev_priv = dev->dev_private;
10900 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10901 uint32_t pf, pipesrc;
10902 int ret;
10903
10904 ret = intel_ring_begin(req, 4);
10905 if (ret)
10906 return ret;
10907
10908 /* i965+ uses the linear or tiled offsets from the
10909 * Display Registers (which do not change across a page-flip)
10910 * so we need only reprogram the base address.
10911 */
10912 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10913 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10914 intel_ring_emit(ring, fb->pitches[0]);
10915 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10916 obj->tiling_mode);
10917
10918 /* XXX Enabling the panel-fitter across page-flip is so far
10919 * untested on non-native modes, so ignore it for now.
10920 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10921 */
10922 pf = 0;
10923 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10924 intel_ring_emit(ring, pf | pipesrc);
10925
10926 intel_mark_page_flip_active(intel_crtc);
10927 return 0;
10928}
10929
10930static int intel_gen6_queue_flip(struct drm_device *dev,
10931 struct drm_crtc *crtc,
10932 struct drm_framebuffer *fb,
10933 struct drm_i915_gem_object *obj,
10934 struct drm_i915_gem_request *req,
10935 uint32_t flags)
10936{
10937 struct intel_engine_cs *ring = req->ring;
10938 struct drm_i915_private *dev_priv = dev->dev_private;
10939 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10940 uint32_t pf, pipesrc;
10941 int ret;
10942
10943 ret = intel_ring_begin(req, 4);
10944 if (ret)
10945 return ret;
10946
10947 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10948 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10949 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10950 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10951
10952 /* Contrary to the suggestions in the documentation,
10953 * "Enable Panel Fitter" does not seem to be required when page
10954 * flipping with a non-native mode, and worse causes a normal
10955 * modeset to fail.
10956 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10957 */
10958 pf = 0;
10959 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10960 intel_ring_emit(ring, pf | pipesrc);
10961
10962 intel_mark_page_flip_active(intel_crtc);
10963 return 0;
10964}
10965
10966static int intel_gen7_queue_flip(struct drm_device *dev,
10967 struct drm_crtc *crtc,
10968 struct drm_framebuffer *fb,
10969 struct drm_i915_gem_object *obj,
10970 struct drm_i915_gem_request *req,
10971 uint32_t flags)
10972{
10973 struct intel_engine_cs *ring = req->ring;
10974 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10975 uint32_t plane_bit = 0;
10976 int len, ret;
10977
10978 switch (intel_crtc->plane) {
10979 case PLANE_A:
10980 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10981 break;
10982 case PLANE_B:
10983 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10984 break;
10985 case PLANE_C:
10986 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10987 break;
10988 default:
10989 WARN_ONCE(1, "unknown plane in flip command\n");
10990 return -ENODEV;
10991 }
10992
10993 len = 4;
10994 if (ring->id == RCS) {
10995 len += 6;
10996 /*
10997 * On Gen 8, SRM is now taking an extra dword to accommodate
10998 * 48bits addresses, and we need a NOOP for the batch size to
10999 * stay even.
11000 */
11001 if (IS_GEN8(dev))
11002 len += 2;
11003 }
11004
11005 /*
11006 * BSpec MI_DISPLAY_FLIP for IVB:
11007 * "The full packet must be contained within the same cache line."
11008 *
11009 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11010 * cacheline, if we ever start emitting more commands before
11011 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11012 * then do the cacheline alignment, and finally emit the
11013 * MI_DISPLAY_FLIP.
11014 */
11015 ret = intel_ring_cacheline_align(req);
11016 if (ret)
11017 return ret;
11018
11019 ret = intel_ring_begin(req, len);
11020 if (ret)
11021 return ret;
11022
11023 /* Unmask the flip-done completion message. Note that the bspec says that
11024 * we should do this for both the BCS and RCS, and that we must not unmask
11025 * more than one flip event at any time (or ensure that one flip message
11026 * can be sent by waiting for flip-done prior to queueing new flips).
11027 * Experimentation says that BCS works despite DERRMR masking all
11028 * flip-done completion events and that unmasking all planes at once
11029 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11030 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11031 */
11032 if (ring->id == RCS) {
11033 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11034 intel_ring_emit(ring, DERRMR);
11035 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11036 DERRMR_PIPEB_PRI_FLIP_DONE |
11037 DERRMR_PIPEC_PRI_FLIP_DONE));
11038 if (IS_GEN8(dev))
11039 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11040 MI_SRM_LRM_GLOBAL_GTT);
11041 else
11042 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11043 MI_SRM_LRM_GLOBAL_GTT);
11044 intel_ring_emit(ring, DERRMR);
11045 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11046 if (IS_GEN8(dev)) {
11047 intel_ring_emit(ring, 0);
11048 intel_ring_emit(ring, MI_NOOP);
11049 }
11050 }
11051
11052 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11053 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11054 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11055 intel_ring_emit(ring, (MI_NOOP));
11056
11057 intel_mark_page_flip_active(intel_crtc);
11058 return 0;
11059}
11060
11061static bool use_mmio_flip(struct intel_engine_cs *ring,
11062 struct drm_i915_gem_object *obj)
11063{
11064 /*
11065 * This is not being used for older platforms, because
11066 * non-availability of flip done interrupt forces us to use
11067 * CS flips. Older platforms derive flip done using some clever
11068 * tricks involving the flip_pending status bits and vblank irqs.
11069 * So using MMIO flips there would disrupt this mechanism.
11070 */
11071
11072 if (ring == NULL)
11073 return true;
11074
11075 if (INTEL_INFO(ring->dev)->gen < 5)
11076 return false;
11077
11078 if (i915.use_mmio_flip < 0)
11079 return false;
11080 else if (i915.use_mmio_flip > 0)
11081 return true;
11082 else if (i915.enable_execlists)
11083 return true;
11084 else
11085 return ring != i915_gem_request_get_ring(obj->last_write_req);
11086}
11087
11088static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11089{
11090 struct drm_device *dev = intel_crtc->base.dev;
11091 struct drm_i915_private *dev_priv = dev->dev_private;
11092 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11093 const enum pipe pipe = intel_crtc->pipe;
11094 u32 ctl, stride;
11095
11096 ctl = I915_READ(PLANE_CTL(pipe, 0));
11097 ctl &= ~PLANE_CTL_TILED_MASK;
11098 switch (fb->modifier[0]) {
11099 case DRM_FORMAT_MOD_NONE:
11100 break;
11101 case I915_FORMAT_MOD_X_TILED:
11102 ctl |= PLANE_CTL_TILED_X;
11103 break;
11104 case I915_FORMAT_MOD_Y_TILED:
11105 ctl |= PLANE_CTL_TILED_Y;
11106 break;
11107 case I915_FORMAT_MOD_Yf_TILED:
11108 ctl |= PLANE_CTL_TILED_YF;
11109 break;
11110 default:
11111 MISSING_CASE(fb->modifier[0]);
11112 }
11113
11114 /*
11115 * The stride is either expressed as a multiple of 64 bytes chunks for
11116 * linear buffers or in number of tiles for tiled buffers.
11117 */
11118 stride = fb->pitches[0] /
11119 intel_fb_stride_alignment(dev, fb->modifier[0],
11120 fb->pixel_format);
11121
11122 /*
11123 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11124 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11125 */
11126 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11127 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11128
11129 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11130 POSTING_READ(PLANE_SURF(pipe, 0));
11131}
11132
11133static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
11134{
11135 struct drm_device *dev = intel_crtc->base.dev;
11136 struct drm_i915_private *dev_priv = dev->dev_private;
11137 struct intel_framebuffer *intel_fb =
11138 to_intel_framebuffer(intel_crtc->base.primary->fb);
11139 struct drm_i915_gem_object *obj = intel_fb->obj;
11140 u32 dspcntr;
11141 u32 reg;
11142
11143 reg = DSPCNTR(intel_crtc->plane);
11144 dspcntr = I915_READ(reg);
11145
11146 if (obj->tiling_mode != I915_TILING_NONE)
11147 dspcntr |= DISPPLANE_TILED;
11148 else
11149 dspcntr &= ~DISPPLANE_TILED;
11150
11151 I915_WRITE(reg, dspcntr);
11152
11153 I915_WRITE(DSPSURF(intel_crtc->plane),
11154 intel_crtc->unpin_work->gtt_offset);
11155 POSTING_READ(DSPSURF(intel_crtc->plane));
11156
11157}
11158
11159/*
11160 * XXX: This is the temporary way to update the plane registers until we get
11161 * around to using the usual plane update functions for MMIO flips
11162 */
11163static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11164{
11165 struct drm_device *dev = intel_crtc->base.dev;
11166 u32 start_vbl_count;
11167
11168 intel_mark_page_flip_active(intel_crtc);
11169
11170 intel_pipe_update_start(intel_crtc, &start_vbl_count);
11171
11172 if (INTEL_INFO(dev)->gen >= 9)
11173 skl_do_mmio_flip(intel_crtc);
11174 else
11175 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11176 ilk_do_mmio_flip(intel_crtc);
11177
11178 intel_pipe_update_end(intel_crtc, start_vbl_count);
11179}
11180
11181static void intel_mmio_flip_work_func(struct work_struct *work)
11182{
11183 struct intel_mmio_flip *mmio_flip =
11184 container_of(work, struct intel_mmio_flip, work);
11185
11186 if (mmio_flip->req)
11187 WARN_ON(__i915_wait_request(mmio_flip->req,
11188 mmio_flip->crtc->reset_counter,
11189 false, NULL,
11190 &mmio_flip->i915->rps.mmioflips));
11191
11192 intel_do_mmio_flip(mmio_flip->crtc);
11193
11194 i915_gem_request_unreference__unlocked(mmio_flip->req);
11195 kfree(mmio_flip);
11196}
11197
11198static int intel_queue_mmio_flip(struct drm_device *dev,
11199 struct drm_crtc *crtc,
11200 struct drm_framebuffer *fb,
11201 struct drm_i915_gem_object *obj,
11202 struct intel_engine_cs *ring,
11203 uint32_t flags)
11204{
11205 struct intel_mmio_flip *mmio_flip;
11206
11207 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11208 if (mmio_flip == NULL)
11209 return -ENOMEM;
11210
11211 mmio_flip->i915 = to_i915(dev);
11212 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11213 mmio_flip->crtc = to_intel_crtc(crtc);
11214
11215 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11216 schedule_work(&mmio_flip->work);
11217
11218 return 0;
11219}
11220
11221static int intel_default_queue_flip(struct drm_device *dev,
11222 struct drm_crtc *crtc,
11223 struct drm_framebuffer *fb,
11224 struct drm_i915_gem_object *obj,
11225 struct drm_i915_gem_request *req,
11226 uint32_t flags)
11227{
11228 return -ENODEV;
11229}
11230
11231static bool __intel_pageflip_stall_check(struct drm_device *dev,
11232 struct drm_crtc *crtc)
11233{
11234 struct drm_i915_private *dev_priv = dev->dev_private;
11235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11236 struct intel_unpin_work *work = intel_crtc->unpin_work;
11237 u32 addr;
11238
11239 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11240 return true;
11241
11242 if (!work->enable_stall_check)
11243 return false;
11244
11245 if (work->flip_ready_vblank == 0) {
11246 if (work->flip_queued_req &&
11247 !i915_gem_request_completed(work->flip_queued_req, true))
11248 return false;
11249
11250 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11251 }
11252
11253 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11254 return false;
11255
11256 /* Potential stall - if we see that the flip has happened,
11257 * assume a missed interrupt. */
11258 if (INTEL_INFO(dev)->gen >= 4)
11259 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11260 else
11261 addr = I915_READ(DSPADDR(intel_crtc->plane));
11262
11263 /* There is a potential issue here with a false positive after a flip
11264 * to the same address. We could address this by checking for a
11265 * non-incrementing frame counter.
11266 */
11267 return addr == work->gtt_offset;
11268}
11269
11270void intel_check_page_flip(struct drm_device *dev, int pipe)
11271{
11272 struct drm_i915_private *dev_priv = dev->dev_private;
11273 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11275 struct intel_unpin_work *work;
11276
11277 WARN_ON(!in_interrupt());
11278
11279 if (crtc == NULL)
11280 return;
11281
11282 spin_lock(&dev->event_lock);
11283 work = intel_crtc->unpin_work;
11284 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11285 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11286 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11287 page_flip_completed(intel_crtc);
11288 work = NULL;
11289 }
11290 if (work != NULL &&
11291 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11292 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11293 spin_unlock(&dev->event_lock);
11294}
11295
11296static int intel_crtc_page_flip(struct drm_crtc *crtc,
11297 struct drm_framebuffer *fb,
11298 struct drm_pending_vblank_event *event,
11299 uint32_t page_flip_flags)
11300{
11301 struct drm_device *dev = crtc->dev;
11302 struct drm_i915_private *dev_priv = dev->dev_private;
11303 struct drm_framebuffer *old_fb = crtc->primary->fb;
11304 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11306 struct drm_plane *primary = crtc->primary;
11307 enum pipe pipe = intel_crtc->pipe;
11308 struct intel_unpin_work *work;
11309 struct intel_engine_cs *ring;
11310 bool mmio_flip;
11311 struct drm_i915_gem_request *request = NULL;
11312 int ret;
11313
11314 /*
11315 * drm_mode_page_flip_ioctl() should already catch this, but double
11316 * check to be safe. In the future we may enable pageflipping from
11317 * a disabled primary plane.
11318 */
11319 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11320 return -EBUSY;
11321
11322 /* Can't change pixel format via MI display flips. */
11323 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11324 return -EINVAL;
11325
11326 /*
11327 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11328 * Note that pitch changes could also affect these register.
11329 */
11330 if (INTEL_INFO(dev)->gen > 3 &&
11331 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11332 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11333 return -EINVAL;
11334
11335 if (i915_terminally_wedged(&dev_priv->gpu_error))
11336 goto out_hang;
11337
11338 work = kzalloc(sizeof(*work), GFP_KERNEL);
11339 if (work == NULL)
11340 return -ENOMEM;
11341
11342 work->event = event;
11343 work->crtc = crtc;
11344 work->old_fb = old_fb;
11345 INIT_WORK(&work->work, intel_unpin_work_fn);
11346
11347 ret = drm_crtc_vblank_get(crtc);
11348 if (ret)
11349 goto free_work;
11350
11351 /* We borrow the event spin lock for protecting unpin_work */
11352 spin_lock_irq(&dev->event_lock);
11353 if (intel_crtc->unpin_work) {
11354 /* Before declaring the flip queue wedged, check if
11355 * the hardware completed the operation behind our backs.
11356 */
11357 if (__intel_pageflip_stall_check(dev, crtc)) {
11358 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11359 page_flip_completed(intel_crtc);
11360 } else {
11361 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11362 spin_unlock_irq(&dev->event_lock);
11363
11364 drm_crtc_vblank_put(crtc);
11365 kfree(work);
11366 return -EBUSY;
11367 }
11368 }
11369 intel_crtc->unpin_work = work;
11370 spin_unlock_irq(&dev->event_lock);
11371
11372 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11373 flush_workqueue(dev_priv->wq);
11374
11375 /* Reference the objects for the scheduled work. */
11376 drm_framebuffer_reference(work->old_fb);
11377 drm_gem_object_reference(&obj->base);
11378
11379 crtc->primary->fb = fb;
11380 update_state_fb(crtc->primary);
11381
11382 work->pending_flip_obj = obj;
11383
11384 ret = i915_mutex_lock_interruptible(dev);
11385 if (ret)
11386 goto cleanup;
11387
11388 atomic_inc(&intel_crtc->unpin_work_count);
11389 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11390
11391 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11392 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11393
11394 if (IS_VALLEYVIEW(dev)) {
11395 ring = &dev_priv->ring[BCS];
11396 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11397 /* vlv: DISPLAY_FLIP fails to change tiling */
11398 ring = NULL;
11399 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11400 ring = &dev_priv->ring[BCS];
11401 } else if (INTEL_INFO(dev)->gen >= 7) {
11402 ring = i915_gem_request_get_ring(obj->last_write_req);
11403 if (ring == NULL || ring->id != RCS)
11404 ring = &dev_priv->ring[BCS];
11405 } else {
11406 ring = &dev_priv->ring[RCS];
11407 }
11408
11409 mmio_flip = use_mmio_flip(ring, obj);
11410
11411 /* When using CS flips, we want to emit semaphores between rings.
11412 * However, when using mmio flips we will create a task to do the
11413 * synchronisation, so all we want here is to pin the framebuffer
11414 * into the display plane and skip any waits.
11415 */
11416 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11417 crtc->primary->state,
11418 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
11419 if (ret)
11420 goto cleanup_pending;
11421
11422 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11423 + intel_crtc->dspaddr_offset;
11424
11425 if (mmio_flip) {
11426 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11427 page_flip_flags);
11428 if (ret)
11429 goto cleanup_unpin;
11430
11431 i915_gem_request_assign(&work->flip_queued_req,
11432 obj->last_write_req);
11433 } else {
11434 if (!request) {
11435 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11436 if (ret)
11437 goto cleanup_unpin;
11438 }
11439
11440 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11441 page_flip_flags);
11442 if (ret)
11443 goto cleanup_unpin;
11444
11445 i915_gem_request_assign(&work->flip_queued_req, request);
11446 }
11447
11448 if (request)
11449 i915_add_request_no_flush(request);
11450
11451 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11452 work->enable_stall_check = true;
11453
11454 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11455 to_intel_plane(primary)->frontbuffer_bit);
11456 mutex_unlock(&dev->struct_mutex);
11457
11458 intel_fbc_disable_crtc(intel_crtc);
11459 intel_frontbuffer_flip_prepare(dev,
11460 to_intel_plane(primary)->frontbuffer_bit);
11461
11462 trace_i915_flip_request(intel_crtc->plane, obj);
11463
11464 return 0;
11465
11466cleanup_unpin:
11467 intel_unpin_fb_obj(fb, crtc->primary->state);
11468cleanup_pending:
11469 if (request)
11470 i915_gem_request_cancel(request);
11471 atomic_dec(&intel_crtc->unpin_work_count);
11472 mutex_unlock(&dev->struct_mutex);
11473cleanup:
11474 crtc->primary->fb = old_fb;
11475 update_state_fb(crtc->primary);
11476
11477 drm_gem_object_unreference_unlocked(&obj->base);
11478 drm_framebuffer_unreference(work->old_fb);
11479
11480 spin_lock_irq(&dev->event_lock);
11481 intel_crtc->unpin_work = NULL;
11482 spin_unlock_irq(&dev->event_lock);
11483
11484 drm_crtc_vblank_put(crtc);
11485free_work:
11486 kfree(work);
11487
11488 if (ret == -EIO) {
11489 struct drm_atomic_state *state;
11490 struct drm_plane_state *plane_state;
11491
11492out_hang:
11493 state = drm_atomic_state_alloc(dev);
11494 if (!state)
11495 return -ENOMEM;
11496 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11497
11498retry:
11499 plane_state = drm_atomic_get_plane_state(state, primary);
11500 ret = PTR_ERR_OR_ZERO(plane_state);
11501 if (!ret) {
11502 drm_atomic_set_fb_for_plane(plane_state, fb);
11503
11504 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11505 if (!ret)
11506 ret = drm_atomic_commit(state);
11507 }
11508
11509 if (ret == -EDEADLK) {
11510 drm_modeset_backoff(state->acquire_ctx);
11511 drm_atomic_state_clear(state);
11512 goto retry;
11513 }
11514
11515 if (ret)
11516 drm_atomic_state_free(state);
11517
11518 if (ret == 0 && event) {
11519 spin_lock_irq(&dev->event_lock);
11520 drm_send_vblank_event(dev, pipe, event);
11521 spin_unlock_irq(&dev->event_lock);
11522 }
11523 }
11524 return ret;
11525}
11526
11527
11528/**
11529 * intel_wm_need_update - Check whether watermarks need updating
11530 * @plane: drm plane
11531 * @state: new plane state
11532 *
11533 * Check current plane state versus the new one to determine whether
11534 * watermarks need to be recalculated.
11535 *
11536 * Returns true or false.
11537 */
11538static bool intel_wm_need_update(struct drm_plane *plane,
11539 struct drm_plane_state *state)
11540{
11541 /* Update watermarks on tiling changes. */
11542 if (!plane->state->fb || !state->fb ||
11543 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11544 plane->state->rotation != state->rotation)
11545 return true;
11546
11547 if (plane->state->crtc_w != state->crtc_w)
11548 return true;
11549
11550 return false;
11551}
11552
11553int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11554 struct drm_plane_state *plane_state)
11555{
11556 struct drm_crtc *crtc = crtc_state->crtc;
11557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11558 struct drm_plane *plane = plane_state->plane;
11559 struct drm_device *dev = crtc->dev;
11560 struct drm_i915_private *dev_priv = dev->dev_private;
11561 struct intel_plane_state *old_plane_state =
11562 to_intel_plane_state(plane->state);
11563 int idx = intel_crtc->base.base.id, ret;
11564 int i = drm_plane_index(plane);
11565 bool mode_changed = needs_modeset(crtc_state);
11566 bool was_crtc_enabled = crtc->state->active;
11567 bool is_crtc_enabled = crtc_state->active;
11568
11569 bool turn_off, turn_on, visible, was_visible;
11570 struct drm_framebuffer *fb = plane_state->fb;
11571
11572 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11573 plane->type != DRM_PLANE_TYPE_CURSOR) {
11574 ret = skl_update_scaler_plane(
11575 to_intel_crtc_state(crtc_state),
11576 to_intel_plane_state(plane_state));
11577 if (ret)
11578 return ret;
11579 }
11580
11581 /*
11582 * Disabling a plane is always okay; we just need to update
11583 * fb tracking in a special way since cleanup_fb() won't
11584 * get called by the plane helpers.
11585 */
11586 if (old_plane_state->base.fb && !fb)
11587 intel_crtc->atomic.disabled_planes |= 1 << i;
11588
11589 was_visible = old_plane_state->visible;
11590 visible = to_intel_plane_state(plane_state)->visible;
11591
11592 if (!was_crtc_enabled && WARN_ON(was_visible))
11593 was_visible = false;
11594
11595 if (!is_crtc_enabled && WARN_ON(visible))
11596 visible = false;
11597
11598 if (!was_visible && !visible)
11599 return 0;
11600
11601 turn_off = was_visible && (!visible || mode_changed);
11602 turn_on = visible && (!was_visible || mode_changed);
11603
11604 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11605 plane->base.id, fb ? fb->base.id : -1);
11606
11607 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11608 plane->base.id, was_visible, visible,
11609 turn_off, turn_on, mode_changed);
11610
11611 if (turn_on) {
11612 intel_crtc->atomic.update_wm_pre = true;
11613 /* must disable cxsr around plane enable/disable */
11614 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11615 intel_crtc->atomic.disable_cxsr = true;
11616 /* to potentially re-enable cxsr */
11617 intel_crtc->atomic.wait_vblank = true;
11618 intel_crtc->atomic.update_wm_post = true;
11619 }
11620 } else if (turn_off) {
11621 intel_crtc->atomic.update_wm_post = true;
11622 /* must disable cxsr around plane enable/disable */
11623 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11624 if (is_crtc_enabled)
11625 intel_crtc->atomic.wait_vblank = true;
11626 intel_crtc->atomic.disable_cxsr = true;
11627 }
11628 } else if (intel_wm_need_update(plane, plane_state)) {
11629 intel_crtc->atomic.update_wm_pre = true;
11630 }
11631
11632 if (visible)
11633 intel_crtc->atomic.fb_bits |=
11634 to_intel_plane(plane)->frontbuffer_bit;
11635
11636 switch (plane->type) {
11637 case DRM_PLANE_TYPE_PRIMARY:
11638 intel_crtc->atomic.wait_for_flips = true;
11639 intel_crtc->atomic.pre_disable_primary = turn_off;
11640 intel_crtc->atomic.post_enable_primary = turn_on;
11641
11642 if (turn_off) {
11643 /*
11644 * FIXME: Actually if we will still have any other
11645 * plane enabled on the pipe we could let IPS enabled
11646 * still, but for now lets consider that when we make
11647 * primary invisible by setting DSPCNTR to 0 on
11648 * update_primary_plane function IPS needs to be
11649 * disable.
11650 */
11651 intel_crtc->atomic.disable_ips = true;
11652
11653 intel_crtc->atomic.disable_fbc = true;
11654 }
11655
11656 /*
11657 * FBC does not work on some platforms for rotated
11658 * planes, so disable it when rotation is not 0 and
11659 * update it when rotation is set back to 0.
11660 *
11661 * FIXME: This is redundant with the fbc update done in
11662 * the primary plane enable function except that that
11663 * one is done too late. We eventually need to unify
11664 * this.
11665 */
11666
11667 if (visible &&
11668 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11669 dev_priv->fbc.crtc == intel_crtc &&
11670 plane_state->rotation != BIT(DRM_ROTATE_0))
11671 intel_crtc->atomic.disable_fbc = true;
11672
11673 /*
11674 * BDW signals flip done immediately if the plane
11675 * is disabled, even if the plane enable is already
11676 * armed to occur at the next vblank :(
11677 */
11678 if (turn_on && IS_BROADWELL(dev))
11679 intel_crtc->atomic.wait_vblank = true;
11680
11681 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11682 break;
11683 case DRM_PLANE_TYPE_CURSOR:
11684 break;
11685 case DRM_PLANE_TYPE_OVERLAY:
11686 if (turn_off && !mode_changed) {
11687 intel_crtc->atomic.wait_vblank = true;
11688 intel_crtc->atomic.update_sprite_watermarks |=
11689 1 << i;
11690 }
11691 }
11692 return 0;
11693}
11694
11695static bool encoders_cloneable(const struct intel_encoder *a,
11696 const struct intel_encoder *b)
11697{
11698 /* masks could be asymmetric, so check both ways */
11699 return a == b || (a->cloneable & (1 << b->type) &&
11700 b->cloneable & (1 << a->type));
11701}
11702
11703static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11704 struct intel_crtc *crtc,
11705 struct intel_encoder *encoder)
11706{
11707 struct intel_encoder *source_encoder;
11708 struct drm_connector *connector;
11709 struct drm_connector_state *connector_state;
11710 int i;
11711
11712 for_each_connector_in_state(state, connector, connector_state, i) {
11713 if (connector_state->crtc != &crtc->base)
11714 continue;
11715
11716 source_encoder =
11717 to_intel_encoder(connector_state->best_encoder);
11718 if (!encoders_cloneable(encoder, source_encoder))
11719 return false;
11720 }
11721
11722 return true;
11723}
11724
11725static bool check_encoder_cloning(struct drm_atomic_state *state,
11726 struct intel_crtc *crtc)
11727{
11728 struct intel_encoder *encoder;
11729 struct drm_connector *connector;
11730 struct drm_connector_state *connector_state;
11731 int i;
11732
11733 for_each_connector_in_state(state, connector, connector_state, i) {
11734 if (connector_state->crtc != &crtc->base)
11735 continue;
11736
11737 encoder = to_intel_encoder(connector_state->best_encoder);
11738 if (!check_single_encoder_cloning(state, crtc, encoder))
11739 return false;
11740 }
11741
11742 return true;
11743}
11744
11745static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11746 struct drm_crtc_state *crtc_state)
11747{
11748 struct drm_device *dev = crtc->dev;
11749 struct drm_i915_private *dev_priv = dev->dev_private;
11750 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11751 struct intel_crtc_state *pipe_config =
11752 to_intel_crtc_state(crtc_state);
11753 struct drm_atomic_state *state = crtc_state->state;
11754 int ret;
11755 bool mode_changed = needs_modeset(crtc_state);
11756
11757 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11758 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11759 return -EINVAL;
11760 }
11761
11762 if (mode_changed && !crtc_state->active)
11763 intel_crtc->atomic.update_wm_post = true;
11764
11765 if (mode_changed && crtc_state->enable &&
11766 dev_priv->display.crtc_compute_clock &&
11767 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11768 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11769 pipe_config);
11770 if (ret)
11771 return ret;
11772 }
11773
11774 ret = 0;
11775 if (INTEL_INFO(dev)->gen >= 9) {
11776 if (mode_changed)
11777 ret = skl_update_scaler_crtc(pipe_config);
11778
11779 if (!ret)
11780 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11781 pipe_config);
11782 }
11783
11784 return ret;
11785}
11786
11787static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11788 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11789 .load_lut = intel_crtc_load_lut,
11790 .atomic_begin = intel_begin_crtc_commit,
11791 .atomic_flush = intel_finish_crtc_commit,
11792 .atomic_check = intel_crtc_atomic_check,
11793};
11794
11795static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11796{
11797 struct intel_connector *connector;
11798
11799 for_each_intel_connector(dev, connector) {
11800 if (connector->base.encoder) {
11801 connector->base.state->best_encoder =
11802 connector->base.encoder;
11803 connector->base.state->crtc =
11804 connector->base.encoder->crtc;
11805 } else {
11806 connector->base.state->best_encoder = NULL;
11807 connector->base.state->crtc = NULL;
11808 }
11809 }
11810}
11811
11812static void
11813connected_sink_compute_bpp(struct intel_connector *connector,
11814 struct intel_crtc_state *pipe_config)
11815{
11816 int bpp = pipe_config->pipe_bpp;
11817
11818 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11819 connector->base.base.id,
11820 connector->base.name);
11821
11822 /* Don't use an invalid EDID bpc value */
11823 if (connector->base.display_info.bpc &&
11824 connector->base.display_info.bpc * 3 < bpp) {
11825 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11826 bpp, connector->base.display_info.bpc*3);
11827 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11828 }
11829
11830 /* Clamp bpp to 8 on screens without EDID 1.4 */
11831 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11832 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11833 bpp);
11834 pipe_config->pipe_bpp = 24;
11835 }
11836}
11837
11838static int
11839compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11840 struct intel_crtc_state *pipe_config)
11841{
11842 struct drm_device *dev = crtc->base.dev;
11843 struct drm_atomic_state *state;
11844 struct drm_connector *connector;
11845 struct drm_connector_state *connector_state;
11846 int bpp, i;
11847
11848 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11849 bpp = 10*3;
11850 else if (INTEL_INFO(dev)->gen >= 5)
11851 bpp = 12*3;
11852 else
11853 bpp = 8*3;
11854
11855
11856 pipe_config->pipe_bpp = bpp;
11857
11858 state = pipe_config->base.state;
11859
11860 /* Clamp display bpp to EDID value */
11861 for_each_connector_in_state(state, connector, connector_state, i) {
11862 if (connector_state->crtc != &crtc->base)
11863 continue;
11864
11865 connected_sink_compute_bpp(to_intel_connector(connector),
11866 pipe_config);
11867 }
11868
11869 return bpp;
11870}
11871
11872static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11873{
11874 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11875 "type: 0x%x flags: 0x%x\n",
11876 mode->crtc_clock,
11877 mode->crtc_hdisplay, mode->crtc_hsync_start,
11878 mode->crtc_hsync_end, mode->crtc_htotal,
11879 mode->crtc_vdisplay, mode->crtc_vsync_start,
11880 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11881}
11882
11883static void intel_dump_pipe_config(struct intel_crtc *crtc,
11884 struct intel_crtc_state *pipe_config,
11885 const char *context)
11886{
11887 struct drm_device *dev = crtc->base.dev;
11888 struct drm_plane *plane;
11889 struct intel_plane *intel_plane;
11890 struct intel_plane_state *state;
11891 struct drm_framebuffer *fb;
11892
11893 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11894 context, pipe_config, pipe_name(crtc->pipe));
11895
11896 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11897 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11898 pipe_config->pipe_bpp, pipe_config->dither);
11899 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11900 pipe_config->has_pch_encoder,
11901 pipe_config->fdi_lanes,
11902 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11903 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11904 pipe_config->fdi_m_n.tu);
11905 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11906 pipe_config->has_dp_encoder,
11907 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11908 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11909 pipe_config->dp_m_n.tu);
11910
11911 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11912 pipe_config->has_dp_encoder,
11913 pipe_config->dp_m2_n2.gmch_m,
11914 pipe_config->dp_m2_n2.gmch_n,
11915 pipe_config->dp_m2_n2.link_m,
11916 pipe_config->dp_m2_n2.link_n,
11917 pipe_config->dp_m2_n2.tu);
11918
11919 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11920 pipe_config->has_audio,
11921 pipe_config->has_infoframe);
11922
11923 DRM_DEBUG_KMS("requested mode:\n");
11924 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11925 DRM_DEBUG_KMS("adjusted mode:\n");
11926 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11927 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11928 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11929 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11930 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11931 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11932 crtc->num_scalers,
11933 pipe_config->scaler_state.scaler_users,
11934 pipe_config->scaler_state.scaler_id);
11935 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11936 pipe_config->gmch_pfit.control,
11937 pipe_config->gmch_pfit.pgm_ratios,
11938 pipe_config->gmch_pfit.lvds_border_bits);
11939 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11940 pipe_config->pch_pfit.pos,
11941 pipe_config->pch_pfit.size,
11942 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11943 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11944 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11945
11946 if (IS_BROXTON(dev)) {
11947 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
11948 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11949 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
11950 pipe_config->ddi_pll_sel,
11951 pipe_config->dpll_hw_state.ebb0,
11952 pipe_config->dpll_hw_state.ebb4,
11953 pipe_config->dpll_hw_state.pll0,
11954 pipe_config->dpll_hw_state.pll1,
11955 pipe_config->dpll_hw_state.pll2,
11956 pipe_config->dpll_hw_state.pll3,
11957 pipe_config->dpll_hw_state.pll6,
11958 pipe_config->dpll_hw_state.pll8,
11959 pipe_config->dpll_hw_state.pll9,
11960 pipe_config->dpll_hw_state.pll10,
11961 pipe_config->dpll_hw_state.pcsdw12);
11962 } else if (IS_SKYLAKE(dev)) {
11963 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11964 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11965 pipe_config->ddi_pll_sel,
11966 pipe_config->dpll_hw_state.ctrl1,
11967 pipe_config->dpll_hw_state.cfgcr1,
11968 pipe_config->dpll_hw_state.cfgcr2);
11969 } else if (HAS_DDI(dev)) {
11970 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11971 pipe_config->ddi_pll_sel,
11972 pipe_config->dpll_hw_state.wrpll);
11973 } else {
11974 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11975 "fp0: 0x%x, fp1: 0x%x\n",
11976 pipe_config->dpll_hw_state.dpll,
11977 pipe_config->dpll_hw_state.dpll_md,
11978 pipe_config->dpll_hw_state.fp0,
11979 pipe_config->dpll_hw_state.fp1);
11980 }
11981
11982 DRM_DEBUG_KMS("planes on this crtc\n");
11983 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11984 intel_plane = to_intel_plane(plane);
11985 if (intel_plane->pipe != crtc->pipe)
11986 continue;
11987
11988 state = to_intel_plane_state(plane->state);
11989 fb = state->base.fb;
11990 if (!fb) {
11991 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11992 "disabled, scaler_id = %d\n",
11993 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11994 plane->base.id, intel_plane->pipe,
11995 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11996 drm_plane_index(plane), state->scaler_id);
11997 continue;
11998 }
11999
12000 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12001 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12002 plane->base.id, intel_plane->pipe,
12003 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12004 drm_plane_index(plane));
12005 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12006 fb->base.id, fb->width, fb->height, fb->pixel_format);
12007 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12008 state->scaler_id,
12009 state->src.x1 >> 16, state->src.y1 >> 16,
12010 drm_rect_width(&state->src) >> 16,
12011 drm_rect_height(&state->src) >> 16,
12012 state->dst.x1, state->dst.y1,
12013 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12014 }
12015}
12016
12017static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12018{
12019 struct drm_device *dev = state->dev;
12020 struct intel_encoder *encoder;
12021 struct drm_connector *connector;
12022 struct drm_connector_state *connector_state;
12023 unsigned int used_ports = 0;
12024 int i;
12025
12026 /*
12027 * Walk the connector list instead of the encoder
12028 * list to detect the problem on ddi platforms
12029 * where there's just one encoder per digital port.
12030 */
12031 for_each_connector_in_state(state, connector, connector_state, i) {
12032 if (!connector_state->best_encoder)
12033 continue;
12034
12035 encoder = to_intel_encoder(connector_state->best_encoder);
12036
12037 WARN_ON(!connector_state->crtc);
12038
12039 switch (encoder->type) {
12040 unsigned int port_mask;
12041 case INTEL_OUTPUT_UNKNOWN:
12042 if (WARN_ON(!HAS_DDI(dev)))
12043 break;
12044 case INTEL_OUTPUT_DISPLAYPORT:
12045 case INTEL_OUTPUT_HDMI:
12046 case INTEL_OUTPUT_EDP:
12047 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12048
12049 /* the same port mustn't appear more than once */
12050 if (used_ports & port_mask)
12051 return false;
12052
12053 used_ports |= port_mask;
12054 default:
12055 break;
12056 }
12057 }
12058
12059 return true;
12060}
12061
12062static void
12063clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12064{
12065 struct drm_crtc_state tmp_state;
12066 struct intel_crtc_scaler_state scaler_state;
12067 struct intel_dpll_hw_state dpll_hw_state;
12068 enum intel_dpll_id shared_dpll;
12069 uint32_t ddi_pll_sel;
12070 bool force_thru;
12071
12072 /* FIXME: before the switch to atomic started, a new pipe_config was
12073 * kzalloc'd. Code that depends on any field being zero should be
12074 * fixed, so that the crtc_state can be safely duplicated. For now,
12075 * only fields that are know to not cause problems are preserved. */
12076
12077 tmp_state = crtc_state->base;
12078 scaler_state = crtc_state->scaler_state;
12079 shared_dpll = crtc_state->shared_dpll;
12080 dpll_hw_state = crtc_state->dpll_hw_state;
12081 ddi_pll_sel = crtc_state->ddi_pll_sel;
12082 force_thru = crtc_state->pch_pfit.force_thru;
12083
12084 memset(crtc_state, 0, sizeof *crtc_state);
12085
12086 crtc_state->base = tmp_state;
12087 crtc_state->scaler_state = scaler_state;
12088 crtc_state->shared_dpll = shared_dpll;
12089 crtc_state->dpll_hw_state = dpll_hw_state;
12090 crtc_state->ddi_pll_sel = ddi_pll_sel;
12091 crtc_state->pch_pfit.force_thru = force_thru;
12092}
12093
12094static int
12095intel_modeset_pipe_config(struct drm_crtc *crtc,
12096 struct intel_crtc_state *pipe_config)
12097{
12098 struct drm_atomic_state *state = pipe_config->base.state;
12099 struct intel_encoder *encoder;
12100 struct drm_connector *connector;
12101 struct drm_connector_state *connector_state;
12102 int base_bpp, ret = -EINVAL;
12103 int i;
12104 bool retry = true;
12105
12106 clear_intel_crtc_state(pipe_config);
12107
12108 pipe_config->cpu_transcoder =
12109 (enum transcoder) to_intel_crtc(crtc)->pipe;
12110
12111 /*
12112 * Sanitize sync polarity flags based on requested ones. If neither
12113 * positive or negative polarity is requested, treat this as meaning
12114 * negative polarity.
12115 */
12116 if (!(pipe_config->base.adjusted_mode.flags &
12117 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12118 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12119
12120 if (!(pipe_config->base.adjusted_mode.flags &
12121 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12122 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12123
12124 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12125 * plane pixel format and any sink constraints into account. Returns the
12126 * source plane bpp so that dithering can be selected on mismatches
12127 * after encoders and crtc also have had their say. */
12128 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12129 pipe_config);
12130 if (base_bpp < 0)
12131 goto fail;
12132
12133 /*
12134 * Determine the real pipe dimensions. Note that stereo modes can
12135 * increase the actual pipe size due to the frame doubling and
12136 * insertion of additional space for blanks between the frame. This
12137 * is stored in the crtc timings. We use the requested mode to do this
12138 * computation to clearly distinguish it from the adjusted mode, which
12139 * can be changed by the connectors in the below retry loop.
12140 */
12141 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12142 &pipe_config->pipe_src_w,
12143 &pipe_config->pipe_src_h);
12144
12145encoder_retry:
12146 /* Ensure the port clock defaults are reset when retrying. */
12147 pipe_config->port_clock = 0;
12148 pipe_config->pixel_multiplier = 1;
12149
12150 /* Fill in default crtc timings, allow encoders to overwrite them. */
12151 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12152 CRTC_STEREO_DOUBLE);
12153
12154 /* Pass our mode to the connectors and the CRTC to give them a chance to
12155 * adjust it according to limitations or connector properties, and also
12156 * a chance to reject the mode entirely.
12157 */
12158 for_each_connector_in_state(state, connector, connector_state, i) {
12159 if (connector_state->crtc != crtc)
12160 continue;
12161
12162 encoder = to_intel_encoder(connector_state->best_encoder);
12163
12164 if (!(encoder->compute_config(encoder, pipe_config))) {
12165 DRM_DEBUG_KMS("Encoder config failure\n");
12166 goto fail;
12167 }
12168 }
12169
12170 /* Set default port clock if not overwritten by the encoder. Needs to be
12171 * done afterwards in case the encoder adjusts the mode. */
12172 if (!pipe_config->port_clock)
12173 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12174 * pipe_config->pixel_multiplier;
12175
12176 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12177 if (ret < 0) {
12178 DRM_DEBUG_KMS("CRTC fixup failed\n");
12179 goto fail;
12180 }
12181
12182 if (ret == RETRY) {
12183 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12184 ret = -EINVAL;
12185 goto fail;
12186 }
12187
12188 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12189 retry = false;
12190 goto encoder_retry;
12191 }
12192
12193 /* Dithering seems to not pass-through bits correctly when it should, so
12194 * only enable it on 6bpc panels. */
12195 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12196 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
12197 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12198
12199fail:
12200 return ret;
12201}
12202
12203static void
12204intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12205{
12206 struct drm_crtc *crtc;
12207 struct drm_crtc_state *crtc_state;
12208 int i;
12209
12210 /* Double check state. */
12211 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12212 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12213
12214 /* Update hwmode for vblank functions */
12215 if (crtc->state->active)
12216 crtc->hwmode = crtc->state->adjusted_mode;
12217 else
12218 crtc->hwmode.crtc_clock = 0;
12219 }
12220}
12221
12222static bool intel_fuzzy_clock_check(int clock1, int clock2)
12223{
12224 int diff;
12225
12226 if (clock1 == clock2)
12227 return true;
12228
12229 if (!clock1 || !clock2)
12230 return false;
12231
12232 diff = abs(clock1 - clock2);
12233
12234 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12235 return true;
12236
12237 return false;
12238}
12239
12240#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12241 list_for_each_entry((intel_crtc), \
12242 &(dev)->mode_config.crtc_list, \
12243 base.head) \
12244 if (mask & (1 <<(intel_crtc)->pipe))
12245
12246
12247static bool
12248intel_compare_m_n(unsigned int m, unsigned int n,
12249 unsigned int m2, unsigned int n2,
12250 bool exact)
12251{
12252 if (m == m2 && n == n2)
12253 return true;
12254
12255 if (exact || !m || !n || !m2 || !n2)
12256 return false;
12257
12258 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12259
12260 if (m > m2) {
12261 while (m > m2) {
12262 m2 <<= 1;
12263 n2 <<= 1;
12264 }
12265 } else if (m < m2) {
12266 while (m < m2) {
12267 m <<= 1;
12268 n <<= 1;
12269 }
12270 }
12271
12272 return m == m2 && n == n2;
12273}
12274
12275static bool
12276intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12277 struct intel_link_m_n *m2_n2,
12278 bool adjust)
12279{
12280 if (m_n->tu == m2_n2->tu &&
12281 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12282 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12283 intel_compare_m_n(m_n->link_m, m_n->link_n,
12284 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12285 if (adjust)
12286 *m2_n2 = *m_n;
12287
12288 return true;
12289 }
12290
12291 return false;
12292}
12293
12294static bool
12295intel_pipe_config_compare(struct drm_device *dev,
12296 struct intel_crtc_state *current_config,
12297 struct intel_crtc_state *pipe_config,
12298 bool adjust)
12299{
12300 bool ret = true;
12301
12302#define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12303 do { \
12304 if (!adjust) \
12305 DRM_ERROR(fmt, ##__VA_ARGS__); \
12306 else \
12307 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12308 } while (0)
12309
12310#define PIPE_CONF_CHECK_X(name) \
12311 if (current_config->name != pipe_config->name) { \
12312 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12313 "(expected 0x%08x, found 0x%08x)\n", \
12314 current_config->name, \
12315 pipe_config->name); \
12316 ret = false; \
12317 }
12318
12319#define PIPE_CONF_CHECK_I(name) \
12320 if (current_config->name != pipe_config->name) { \
12321 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12322 "(expected %i, found %i)\n", \
12323 current_config->name, \
12324 pipe_config->name); \
12325 ret = false; \
12326 }
12327
12328#define PIPE_CONF_CHECK_M_N(name) \
12329 if (!intel_compare_link_m_n(&current_config->name, \
12330 &pipe_config->name,\
12331 adjust)) { \
12332 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12333 "(expected tu %i gmch %i/%i link %i/%i, " \
12334 "found tu %i, gmch %i/%i link %i/%i)\n", \
12335 current_config->name.tu, \
12336 current_config->name.gmch_m, \
12337 current_config->name.gmch_n, \
12338 current_config->name.link_m, \
12339 current_config->name.link_n, \
12340 pipe_config->name.tu, \
12341 pipe_config->name.gmch_m, \
12342 pipe_config->name.gmch_n, \
12343 pipe_config->name.link_m, \
12344 pipe_config->name.link_n); \
12345 ret = false; \
12346 }
12347
12348#define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12349 if (!intel_compare_link_m_n(&current_config->name, \
12350 &pipe_config->name, adjust) && \
12351 !intel_compare_link_m_n(&current_config->alt_name, \
12352 &pipe_config->name, adjust)) { \
12353 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12354 "(expected tu %i gmch %i/%i link %i/%i, " \
12355 "or tu %i gmch %i/%i link %i/%i, " \
12356 "found tu %i, gmch %i/%i link %i/%i)\n", \
12357 current_config->name.tu, \
12358 current_config->name.gmch_m, \
12359 current_config->name.gmch_n, \
12360 current_config->name.link_m, \
12361 current_config->name.link_n, \
12362 current_config->alt_name.tu, \
12363 current_config->alt_name.gmch_m, \
12364 current_config->alt_name.gmch_n, \
12365 current_config->alt_name.link_m, \
12366 current_config->alt_name.link_n, \
12367 pipe_config->name.tu, \
12368 pipe_config->name.gmch_m, \
12369 pipe_config->name.gmch_n, \
12370 pipe_config->name.link_m, \
12371 pipe_config->name.link_n); \
12372 ret = false; \
12373 }
12374
12375/* This is required for BDW+ where there is only one set of registers for
12376 * switching between high and low RR.
12377 * This macro can be used whenever a comparison has to be made between one
12378 * hw state and multiple sw state variables.
12379 */
12380#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12381 if ((current_config->name != pipe_config->name) && \
12382 (current_config->alt_name != pipe_config->name)) { \
12383 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12384 "(expected %i or %i, found %i)\n", \
12385 current_config->name, \
12386 current_config->alt_name, \
12387 pipe_config->name); \
12388 ret = false; \
12389 }
12390
12391#define PIPE_CONF_CHECK_FLAGS(name, mask) \
12392 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12393 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12394 "(expected %i, found %i)\n", \
12395 current_config->name & (mask), \
12396 pipe_config->name & (mask)); \
12397 ret = false; \
12398 }
12399
12400#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12401 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12402 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12403 "(expected %i, found %i)\n", \
12404 current_config->name, \
12405 pipe_config->name); \
12406 ret = false; \
12407 }
12408
12409#define PIPE_CONF_QUIRK(quirk) \
12410 ((current_config->quirks | pipe_config->quirks) & (quirk))
12411
12412 PIPE_CONF_CHECK_I(cpu_transcoder);
12413
12414 PIPE_CONF_CHECK_I(has_pch_encoder);
12415 PIPE_CONF_CHECK_I(fdi_lanes);
12416 PIPE_CONF_CHECK_M_N(fdi_m_n);
12417
12418 PIPE_CONF_CHECK_I(has_dp_encoder);
12419
12420 if (INTEL_INFO(dev)->gen < 8) {
12421 PIPE_CONF_CHECK_M_N(dp_m_n);
12422
12423 PIPE_CONF_CHECK_I(has_drrs);
12424 if (current_config->has_drrs)
12425 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12426 } else
12427 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12428
12429 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12430 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12431 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12432 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12433 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12434 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12435
12436 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12437 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12438 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12439 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12440 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12441 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12442
12443 PIPE_CONF_CHECK_I(pixel_multiplier);
12444 PIPE_CONF_CHECK_I(has_hdmi_sink);
12445 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12446 IS_VALLEYVIEW(dev))
12447 PIPE_CONF_CHECK_I(limited_color_range);
12448 PIPE_CONF_CHECK_I(has_infoframe);
12449
12450 PIPE_CONF_CHECK_I(has_audio);
12451
12452 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12453 DRM_MODE_FLAG_INTERLACE);
12454
12455 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12456 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12457 DRM_MODE_FLAG_PHSYNC);
12458 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12459 DRM_MODE_FLAG_NHSYNC);
12460 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12461 DRM_MODE_FLAG_PVSYNC);
12462 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12463 DRM_MODE_FLAG_NVSYNC);
12464 }
12465
12466 PIPE_CONF_CHECK_I(pipe_src_w);
12467 PIPE_CONF_CHECK_I(pipe_src_h);
12468
12469 PIPE_CONF_CHECK_I(gmch_pfit.control);
12470 /* pfit ratios are autocomputed by the hw on gen4+ */
12471 if (INTEL_INFO(dev)->gen < 4)
12472 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12473 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12474
12475 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12476 if (current_config->pch_pfit.enabled) {
12477 PIPE_CONF_CHECK_I(pch_pfit.pos);
12478 PIPE_CONF_CHECK_I(pch_pfit.size);
12479 }
12480
12481 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12482
12483 /* BDW+ don't expose a synchronous way to read the state */
12484 if (IS_HASWELL(dev))
12485 PIPE_CONF_CHECK_I(ips_enabled);
12486
12487 PIPE_CONF_CHECK_I(double_wide);
12488
12489 PIPE_CONF_CHECK_X(ddi_pll_sel);
12490
12491 PIPE_CONF_CHECK_I(shared_dpll);
12492 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12493 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12494 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12495 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12496 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12497 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12498 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12499 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12500
12501 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12502 PIPE_CONF_CHECK_I(pipe_bpp);
12503
12504 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12505 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12506
12507#undef PIPE_CONF_CHECK_X
12508#undef PIPE_CONF_CHECK_I
12509#undef PIPE_CONF_CHECK_I_ALT
12510#undef PIPE_CONF_CHECK_FLAGS
12511#undef PIPE_CONF_CHECK_CLOCK_FUZZY
12512#undef PIPE_CONF_QUIRK
12513#undef INTEL_ERR_OR_DBG_KMS
12514
12515 return ret;
12516}
12517
12518static void check_wm_state(struct drm_device *dev)
12519{
12520 struct drm_i915_private *dev_priv = dev->dev_private;
12521 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12522 struct intel_crtc *intel_crtc;
12523 int plane;
12524
12525 if (INTEL_INFO(dev)->gen < 9)
12526 return;
12527
12528 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12529 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12530
12531 for_each_intel_crtc(dev, intel_crtc) {
12532 struct skl_ddb_entry *hw_entry, *sw_entry;
12533 const enum pipe pipe = intel_crtc->pipe;
12534
12535 if (!intel_crtc->active)
12536 continue;
12537
12538 /* planes */
12539 for_each_plane(dev_priv, pipe, plane) {
12540 hw_entry = &hw_ddb.plane[pipe][plane];
12541 sw_entry = &sw_ddb->plane[pipe][plane];
12542
12543 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12544 continue;
12545
12546 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12547 "(expected (%u,%u), found (%u,%u))\n",
12548 pipe_name(pipe), plane + 1,
12549 sw_entry->start, sw_entry->end,
12550 hw_entry->start, hw_entry->end);
12551 }
12552
12553 /* cursor */
12554 hw_entry = &hw_ddb.cursor[pipe];
12555 sw_entry = &sw_ddb->cursor[pipe];
12556
12557 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12558 continue;
12559
12560 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12561 "(expected (%u,%u), found (%u,%u))\n",
12562 pipe_name(pipe),
12563 sw_entry->start, sw_entry->end,
12564 hw_entry->start, hw_entry->end);
12565 }
12566}
12567
12568static void
12569check_connector_state(struct drm_device *dev,
12570 struct drm_atomic_state *old_state)
12571{
12572 struct drm_connector_state *old_conn_state;
12573 struct drm_connector *connector;
12574 int i;
12575
12576 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12577 struct drm_encoder *encoder = connector->encoder;
12578 struct drm_connector_state *state = connector->state;
12579
12580 /* This also checks the encoder/connector hw state with the
12581 * ->get_hw_state callbacks. */
12582 intel_connector_check_state(to_intel_connector(connector));
12583
12584 I915_STATE_WARN(state->best_encoder != encoder,
12585 "connector's atomic encoder doesn't match legacy encoder\n");
12586 }
12587}
12588
12589static void
12590check_encoder_state(struct drm_device *dev)
12591{
12592 struct intel_encoder *encoder;
12593 struct intel_connector *connector;
12594
12595 for_each_intel_encoder(dev, encoder) {
12596 bool enabled = false;
12597 enum pipe pipe;
12598
12599 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12600 encoder->base.base.id,
12601 encoder->base.name);
12602
12603 for_each_intel_connector(dev, connector) {
12604 if (connector->base.state->best_encoder != &encoder->base)
12605 continue;
12606 enabled = true;
12607
12608 I915_STATE_WARN(connector->base.state->crtc !=
12609 encoder->base.crtc,
12610 "connector's crtc doesn't match encoder crtc\n");
12611 }
12612
12613 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12614 "encoder's enabled state mismatch "
12615 "(expected %i, found %i)\n",
12616 !!encoder->base.crtc, enabled);
12617
12618 if (!encoder->base.crtc) {
12619 bool active;
12620
12621 active = encoder->get_hw_state(encoder, &pipe);
12622 I915_STATE_WARN(active,
12623 "encoder detached but still enabled on pipe %c.\n",
12624 pipe_name(pipe));
12625 }
12626 }
12627}
12628
12629static void
12630check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12631{
12632 struct drm_i915_private *dev_priv = dev->dev_private;
12633 struct intel_encoder *encoder;
12634 struct drm_crtc_state *old_crtc_state;
12635 struct drm_crtc *crtc;
12636 int i;
12637
12638 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12639 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12640 struct intel_crtc_state *pipe_config, *sw_config;
12641 bool active;
12642
12643 if (!needs_modeset(crtc->state))
12644 continue;
12645
12646 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12647 pipe_config = to_intel_crtc_state(old_crtc_state);
12648 memset(pipe_config, 0, sizeof(*pipe_config));
12649 pipe_config->base.crtc = crtc;
12650 pipe_config->base.state = old_state;
12651
12652 DRM_DEBUG_KMS("[CRTC:%d]\n",
12653 crtc->base.id);
12654
12655 active = dev_priv->display.get_pipe_config(intel_crtc,
12656 pipe_config);
12657
12658 /* hw state is inconsistent with the pipe quirk */
12659 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12660 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12661 active = crtc->state->active;
12662
12663 I915_STATE_WARN(crtc->state->active != active,
12664 "crtc active state doesn't match with hw state "
12665 "(expected %i, found %i)\n", crtc->state->active, active);
12666
12667 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12668 "transitional active state does not match atomic hw state "
12669 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12670
12671 for_each_encoder_on_crtc(dev, crtc, encoder) {
12672 enum pipe pipe;
12673
12674 active = encoder->get_hw_state(encoder, &pipe);
12675 I915_STATE_WARN(active != crtc->state->active,
12676 "[ENCODER:%i] active %i with crtc active %i\n",
12677 encoder->base.base.id, active, crtc->state->active);
12678
12679 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12680 "Encoder connected to wrong pipe %c\n",
12681 pipe_name(pipe));
12682
12683 if (active)
12684 encoder->get_config(encoder, pipe_config);
12685 }
12686
12687 if (!crtc->state->active)
12688 continue;
12689
12690 sw_config = to_intel_crtc_state(crtc->state);
12691 if (!intel_pipe_config_compare(dev, sw_config,
12692 pipe_config, false)) {
12693 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12694 intel_dump_pipe_config(intel_crtc, pipe_config,
12695 "[hw state]");
12696 intel_dump_pipe_config(intel_crtc, sw_config,
12697 "[sw state]");
12698 }
12699 }
12700}
12701
12702static void
12703check_shared_dpll_state(struct drm_device *dev)
12704{
12705 struct drm_i915_private *dev_priv = dev->dev_private;
12706 struct intel_crtc *crtc;
12707 struct intel_dpll_hw_state dpll_hw_state;
12708 int i;
12709
12710 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12711 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12712 int enabled_crtcs = 0, active_crtcs = 0;
12713 bool active;
12714
12715 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12716
12717 DRM_DEBUG_KMS("%s\n", pll->name);
12718
12719 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12720
12721 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12722 "more active pll users than references: %i vs %i\n",
12723 pll->active, hweight32(pll->config.crtc_mask));
12724 I915_STATE_WARN(pll->active && !pll->on,
12725 "pll in active use but not on in sw tracking\n");
12726 I915_STATE_WARN(pll->on && !pll->active,
12727 "pll in on but not on in use in sw tracking\n");
12728 I915_STATE_WARN(pll->on != active,
12729 "pll on state mismatch (expected %i, found %i)\n",
12730 pll->on, active);
12731
12732 for_each_intel_crtc(dev, crtc) {
12733 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12734 enabled_crtcs++;
12735 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12736 active_crtcs++;
12737 }
12738 I915_STATE_WARN(pll->active != active_crtcs,
12739 "pll active crtcs mismatch (expected %i, found %i)\n",
12740 pll->active, active_crtcs);
12741 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12742 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12743 hweight32(pll->config.crtc_mask), enabled_crtcs);
12744
12745 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12746 sizeof(dpll_hw_state)),
12747 "pll hw state mismatch\n");
12748 }
12749}
12750
12751static void
12752intel_modeset_check_state(struct drm_device *dev,
12753 struct drm_atomic_state *old_state)
12754{
12755 check_wm_state(dev);
12756 check_connector_state(dev, old_state);
12757 check_encoder_state(dev);
12758 check_crtc_state(dev, old_state);
12759 check_shared_dpll_state(dev);
12760}
12761
12762void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12763 int dotclock)
12764{
12765 /*
12766 * FDI already provided one idea for the dotclock.
12767 * Yell if the encoder disagrees.
12768 */
12769 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12770 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12771 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12772}
12773
12774static void update_scanline_offset(struct intel_crtc *crtc)
12775{
12776 struct drm_device *dev = crtc->base.dev;
12777
12778 /*
12779 * The scanline counter increments at the leading edge of hsync.
12780 *
12781 * On most platforms it starts counting from vtotal-1 on the
12782 * first active line. That means the scanline counter value is
12783 * always one less than what we would expect. Ie. just after
12784 * start of vblank, which also occurs at start of hsync (on the
12785 * last active line), the scanline counter will read vblank_start-1.
12786 *
12787 * On gen2 the scanline counter starts counting from 1 instead
12788 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12789 * to keep the value positive), instead of adding one.
12790 *
12791 * On HSW+ the behaviour of the scanline counter depends on the output
12792 * type. For DP ports it behaves like most other platforms, but on HDMI
12793 * there's an extra 1 line difference. So we need to add two instead of
12794 * one to the value.
12795 */
12796 if (IS_GEN2(dev)) {
12797 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12798 int vtotal;
12799
12800 vtotal = mode->crtc_vtotal;
12801 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12802 vtotal /= 2;
12803
12804 crtc->scanline_offset = vtotal - 1;
12805 } else if (HAS_DDI(dev) &&
12806 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12807 crtc->scanline_offset = 2;
12808 } else
12809 crtc->scanline_offset = 1;
12810}
12811
12812static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12813{
12814 struct drm_device *dev = state->dev;
12815 struct drm_i915_private *dev_priv = to_i915(dev);
12816 struct intel_shared_dpll_config *shared_dpll = NULL;
12817 struct intel_crtc *intel_crtc;
12818 struct intel_crtc_state *intel_crtc_state;
12819 struct drm_crtc *crtc;
12820 struct drm_crtc_state *crtc_state;
12821 int i;
12822
12823 if (!dev_priv->display.crtc_compute_clock)
12824 return;
12825
12826 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12827 int dpll;
12828
12829 intel_crtc = to_intel_crtc(crtc);
12830 intel_crtc_state = to_intel_crtc_state(crtc_state);
12831 dpll = intel_crtc_state->shared_dpll;
12832
12833 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
12834 continue;
12835
12836 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12837
12838 if (!shared_dpll)
12839 shared_dpll = intel_atomic_get_shared_dpll_state(state);
12840
12841 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12842 }
12843}
12844
12845/*
12846 * This implements the workaround described in the "notes" section of the mode
12847 * set sequence documentation. When going from no pipes or single pipe to
12848 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12849 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12850 */
12851static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12852{
12853 struct drm_crtc_state *crtc_state;
12854 struct intel_crtc *intel_crtc;
12855 struct drm_crtc *crtc;
12856 struct intel_crtc_state *first_crtc_state = NULL;
12857 struct intel_crtc_state *other_crtc_state = NULL;
12858 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12859 int i;
12860
12861 /* look at all crtc's that are going to be enabled in during modeset */
12862 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12863 intel_crtc = to_intel_crtc(crtc);
12864
12865 if (!crtc_state->active || !needs_modeset(crtc_state))
12866 continue;
12867
12868 if (first_crtc_state) {
12869 other_crtc_state = to_intel_crtc_state(crtc_state);
12870 break;
12871 } else {
12872 first_crtc_state = to_intel_crtc_state(crtc_state);
12873 first_pipe = intel_crtc->pipe;
12874 }
12875 }
12876
12877 /* No workaround needed? */
12878 if (!first_crtc_state)
12879 return 0;
12880
12881 /* w/a possibly needed, check how many crtc's are already enabled. */
12882 for_each_intel_crtc(state->dev, intel_crtc) {
12883 struct intel_crtc_state *pipe_config;
12884
12885 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12886 if (IS_ERR(pipe_config))
12887 return PTR_ERR(pipe_config);
12888
12889 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12890
12891 if (!pipe_config->base.active ||
12892 needs_modeset(&pipe_config->base))
12893 continue;
12894
12895 /* 2 or more enabled crtcs means no need for w/a */
12896 if (enabled_pipe != INVALID_PIPE)
12897 return 0;
12898
12899 enabled_pipe = intel_crtc->pipe;
12900 }
12901
12902 if (enabled_pipe != INVALID_PIPE)
12903 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12904 else if (other_crtc_state)
12905 other_crtc_state->hsw_workaround_pipe = first_pipe;
12906
12907 return 0;
12908}
12909
12910static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12911{
12912 struct drm_crtc *crtc;
12913 struct drm_crtc_state *crtc_state;
12914 int ret = 0;
12915
12916 /* add all active pipes to the state */
12917 for_each_crtc(state->dev, crtc) {
12918 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12919 if (IS_ERR(crtc_state))
12920 return PTR_ERR(crtc_state);
12921
12922 if (!crtc_state->active || needs_modeset(crtc_state))
12923 continue;
12924
12925 crtc_state->mode_changed = true;
12926
12927 ret = drm_atomic_add_affected_connectors(state, crtc);
12928 if (ret)
12929 break;
12930
12931 ret = drm_atomic_add_affected_planes(state, crtc);
12932 if (ret)
12933 break;
12934 }
12935
12936 return ret;
12937}
12938
12939
12940static int intel_modeset_checks(struct drm_atomic_state *state)
12941{
12942 struct drm_device *dev = state->dev;
12943 struct drm_i915_private *dev_priv = dev->dev_private;
12944 int ret;
12945
12946 if (!check_digital_port_conflicts(state)) {
12947 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12948 return -EINVAL;
12949 }
12950
12951 /*
12952 * See if the config requires any additional preparation, e.g.
12953 * to adjust global state with pipes off. We need to do this
12954 * here so we can get the modeset_pipe updated config for the new
12955 * mode set on this crtc. For other crtcs we need to use the
12956 * adjusted_mode bits in the crtc directly.
12957 */
12958 if (dev_priv->display.modeset_calc_cdclk) {
12959 unsigned int cdclk;
12960
12961 ret = dev_priv->display.modeset_calc_cdclk(state);
12962
12963 cdclk = to_intel_atomic_state(state)->cdclk;
12964 if (!ret && cdclk != dev_priv->cdclk_freq)
12965 ret = intel_modeset_all_pipes(state);
12966
12967 if (ret < 0)
12968 return ret;
12969 } else
12970 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
12971
12972 intel_modeset_clear_plls(state);
12973
12974 if (IS_HASWELL(dev))
12975 return haswell_mode_set_planes_workaround(state);
12976
12977 return 0;
12978}
12979
12980/**
12981 * intel_atomic_check - validate state object
12982 * @dev: drm device
12983 * @state: state to validate
12984 */
12985static int intel_atomic_check(struct drm_device *dev,
12986 struct drm_atomic_state *state)
12987{
12988 struct drm_crtc *crtc;
12989 struct drm_crtc_state *crtc_state;
12990 int ret, i;
12991 bool any_ms = false;
12992
12993 ret = drm_atomic_helper_check_modeset(dev, state);
12994 if (ret)
12995 return ret;
12996
12997 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12998 struct intel_crtc_state *pipe_config =
12999 to_intel_crtc_state(crtc_state);
13000
13001 /* Catch I915_MODE_FLAG_INHERITED */
13002 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13003 crtc_state->mode_changed = true;
13004
13005 if (!crtc_state->enable) {
13006 if (needs_modeset(crtc_state))
13007 any_ms = true;
13008 continue;
13009 }
13010
13011 if (!needs_modeset(crtc_state))
13012 continue;
13013
13014 /* FIXME: For only active_changed we shouldn't need to do any
13015 * state recomputation at all. */
13016
13017 ret = drm_atomic_add_affected_connectors(state, crtc);
13018 if (ret)
13019 return ret;
13020
13021 ret = intel_modeset_pipe_config(crtc, pipe_config);
13022 if (ret)
13023 return ret;
13024
13025 if (i915.fastboot &&
13026 intel_pipe_config_compare(state->dev,
13027 to_intel_crtc_state(crtc->state),
13028 pipe_config, true)) {
13029 crtc_state->mode_changed = false;
13030 }
13031
13032 if (needs_modeset(crtc_state)) {
13033 any_ms = true;
13034
13035 ret = drm_atomic_add_affected_planes(state, crtc);
13036 if (ret)
13037 return ret;
13038 }
13039
13040 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13041 needs_modeset(crtc_state) ?
13042 "[modeset]" : "[fastset]");
13043 }
13044
13045 if (any_ms) {
13046 ret = intel_modeset_checks(state);
13047
13048 if (ret)
13049 return ret;
13050 } else
13051 to_intel_atomic_state(state)->cdclk =
13052 to_i915(state->dev)->cdclk_freq;
13053
13054 return drm_atomic_helper_check_planes(state->dev, state);
13055}
13056
13057/**
13058 * intel_atomic_commit - commit validated state object
13059 * @dev: DRM device
13060 * @state: the top-level driver state object
13061 * @async: asynchronous commit
13062 *
13063 * This function commits a top-level state object that has been validated
13064 * with drm_atomic_helper_check().
13065 *
13066 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13067 * we can only handle plane-related operations and do not yet support
13068 * asynchronous commit.
13069 *
13070 * RETURNS
13071 * Zero for success or -errno.
13072 */
13073static int intel_atomic_commit(struct drm_device *dev,
13074 struct drm_atomic_state *state,
13075 bool async)
13076{
13077 struct drm_i915_private *dev_priv = dev->dev_private;
13078 struct drm_crtc *crtc;
13079 struct drm_crtc_state *crtc_state;
13080 int ret = 0;
13081 int i;
13082 bool any_ms = false;
13083
13084 if (async) {
13085 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13086 return -EINVAL;
13087 }
13088
13089 ret = drm_atomic_helper_prepare_planes(dev, state);
13090 if (ret)
13091 return ret;
13092
13093 drm_atomic_helper_swap_state(dev, state);
13094
13095 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13096 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13097
13098 if (!needs_modeset(crtc->state))
13099 continue;
13100
13101 any_ms = true;
13102 intel_pre_plane_update(intel_crtc);
13103
13104 if (crtc_state->active) {
13105 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13106 dev_priv->display.crtc_disable(crtc);
13107 intel_crtc->active = false;
13108 intel_disable_shared_dpll(intel_crtc);
13109 }
13110 }
13111
13112 /* Only after disabling all output pipelines that will be changed can we
13113 * update the the output configuration. */
13114 intel_modeset_update_crtc_state(state);
13115
13116 if (any_ms) {
13117 intel_shared_dpll_commit(state);
13118
13119 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13120 modeset_update_crtc_power_domains(state);
13121 }
13122
13123 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13124 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13125 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13126 bool modeset = needs_modeset(crtc->state);
13127
13128 if (modeset && crtc->state->active) {
13129 update_scanline_offset(to_intel_crtc(crtc));
13130 dev_priv->display.crtc_enable(crtc);
13131 }
13132
13133 if (!modeset)
13134 intel_pre_plane_update(intel_crtc);
13135
13136 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13137 intel_post_plane_update(intel_crtc);
13138 }
13139
13140 /* FIXME: add subpixel order */
13141
13142 drm_atomic_helper_wait_for_vblanks(dev, state);
13143 drm_atomic_helper_cleanup_planes(dev, state);
13144
13145 if (any_ms)
13146 intel_modeset_check_state(dev, state);
13147
13148 drm_atomic_state_free(state);
13149
13150 return 0;
13151}
13152
13153void intel_crtc_restore_mode(struct drm_crtc *crtc)
13154{
13155 struct drm_device *dev = crtc->dev;
13156 struct drm_atomic_state *state;
13157 struct drm_crtc_state *crtc_state;
13158 int ret;
13159
13160 state = drm_atomic_state_alloc(dev);
13161 if (!state) {
13162 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13163 crtc->base.id);
13164 return;
13165 }
13166
13167 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13168
13169retry:
13170 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13171 ret = PTR_ERR_OR_ZERO(crtc_state);
13172 if (!ret) {
13173 if (!crtc_state->active)
13174 goto out;
13175
13176 crtc_state->mode_changed = true;
13177 ret = drm_atomic_commit(state);
13178 }
13179
13180 if (ret == -EDEADLK) {
13181 drm_atomic_state_clear(state);
13182 drm_modeset_backoff(state->acquire_ctx);
13183 goto retry;
13184 }
13185
13186 if (ret)
13187out:
13188 drm_atomic_state_free(state);
13189}
13190
13191#undef for_each_intel_crtc_masked
13192
13193static const struct drm_crtc_funcs intel_crtc_funcs = {
13194 .gamma_set = intel_crtc_gamma_set,
13195 .set_config = drm_atomic_helper_set_config,
13196 .destroy = intel_crtc_destroy,
13197 .page_flip = intel_crtc_page_flip,
13198 .atomic_duplicate_state = intel_crtc_duplicate_state,
13199 .atomic_destroy_state = intel_crtc_destroy_state,
13200};
13201
13202static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13203 struct intel_shared_dpll *pll,
13204 struct intel_dpll_hw_state *hw_state)
13205{
13206 uint32_t val;
13207
13208 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13209 return false;
13210
13211 val = I915_READ(PCH_DPLL(pll->id));
13212 hw_state->dpll = val;
13213 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13214 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13215
13216 return val & DPLL_VCO_ENABLE;
13217}
13218
13219static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13220 struct intel_shared_dpll *pll)
13221{
13222 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13223 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13224}
13225
13226static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13227 struct intel_shared_dpll *pll)
13228{
13229 /* PCH refclock must be enabled first */
13230 ibx_assert_pch_refclk_enabled(dev_priv);
13231
13232 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13233
13234 /* Wait for the clocks to stabilize. */
13235 POSTING_READ(PCH_DPLL(pll->id));
13236 udelay(150);
13237
13238 /* The pixel multiplier can only be updated once the
13239 * DPLL is enabled and the clocks are stable.
13240 *
13241 * So write it again.
13242 */
13243 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13244 POSTING_READ(PCH_DPLL(pll->id));
13245 udelay(200);
13246}
13247
13248static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13249 struct intel_shared_dpll *pll)
13250{
13251 struct drm_device *dev = dev_priv->dev;
13252 struct intel_crtc *crtc;
13253
13254 /* Make sure no transcoder isn't still depending on us. */
13255 for_each_intel_crtc(dev, crtc) {
13256 if (intel_crtc_to_shared_dpll(crtc) == pll)
13257 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13258 }
13259
13260 I915_WRITE(PCH_DPLL(pll->id), 0);
13261 POSTING_READ(PCH_DPLL(pll->id));
13262 udelay(200);
13263}
13264
13265static char *ibx_pch_dpll_names[] = {
13266 "PCH DPLL A",
13267 "PCH DPLL B",
13268};
13269
13270static void ibx_pch_dpll_init(struct drm_device *dev)
13271{
13272 struct drm_i915_private *dev_priv = dev->dev_private;
13273 int i;
13274
13275 dev_priv->num_shared_dpll = 2;
13276
13277 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13278 dev_priv->shared_dplls[i].id = i;
13279 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13280 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13281 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13282 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13283 dev_priv->shared_dplls[i].get_hw_state =
13284 ibx_pch_dpll_get_hw_state;
13285 }
13286}
13287
13288static void intel_shared_dpll_init(struct drm_device *dev)
13289{
13290 struct drm_i915_private *dev_priv = dev->dev_private;
13291
13292 intel_update_cdclk(dev);
13293
13294 if (HAS_DDI(dev))
13295 intel_ddi_pll_init(dev);
13296 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13297 ibx_pch_dpll_init(dev);
13298 else
13299 dev_priv->num_shared_dpll = 0;
13300
13301 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13302}
13303
13304/**
13305 * intel_prepare_plane_fb - Prepare fb for usage on plane
13306 * @plane: drm plane to prepare for
13307 * @fb: framebuffer to prepare for presentation
13308 *
13309 * Prepares a framebuffer for usage on a display plane. Generally this
13310 * involves pinning the underlying object and updating the frontbuffer tracking
13311 * bits. Some older platforms need special physical address handling for
13312 * cursor planes.
13313 *
13314 * Returns 0 on success, negative error code on failure.
13315 */
13316int
13317intel_prepare_plane_fb(struct drm_plane *plane,
13318 struct drm_framebuffer *fb,
13319 const struct drm_plane_state *new_state)
13320{
13321 struct drm_device *dev = plane->dev;
13322 struct intel_plane *intel_plane = to_intel_plane(plane);
13323 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13324 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13325 int ret = 0;
13326
13327 if (!obj)
13328 return 0;
13329
13330 mutex_lock(&dev->struct_mutex);
13331
13332 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13333 INTEL_INFO(dev)->cursor_needs_physical) {
13334 int align = IS_I830(dev) ? 16 * 1024 : 256;
13335 ret = i915_gem_object_attach_phys(obj, align);
13336 if (ret)
13337 DRM_DEBUG_KMS("failed to attach phys object\n");
13338 } else {
13339 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
13340 }
13341
13342 if (ret == 0)
13343 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13344
13345 mutex_unlock(&dev->struct_mutex);
13346
13347 return ret;
13348}
13349
13350/**
13351 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13352 * @plane: drm plane to clean up for
13353 * @fb: old framebuffer that was on plane
13354 *
13355 * Cleans up a framebuffer that has just been removed from a plane.
13356 */
13357void
13358intel_cleanup_plane_fb(struct drm_plane *plane,
13359 struct drm_framebuffer *fb,
13360 const struct drm_plane_state *old_state)
13361{
13362 struct drm_device *dev = plane->dev;
13363 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13364
13365 if (WARN_ON(!obj))
13366 return;
13367
13368 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13369 !INTEL_INFO(dev)->cursor_needs_physical) {
13370 mutex_lock(&dev->struct_mutex);
13371 intel_unpin_fb_obj(fb, old_state);
13372 mutex_unlock(&dev->struct_mutex);
13373 }
13374}
13375
13376int
13377skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13378{
13379 int max_scale;
13380 struct drm_device *dev;
13381 struct drm_i915_private *dev_priv;
13382 int crtc_clock, cdclk;
13383
13384 if (!intel_crtc || !crtc_state)
13385 return DRM_PLANE_HELPER_NO_SCALING;
13386
13387 dev = intel_crtc->base.dev;
13388 dev_priv = dev->dev_private;
13389 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13390 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13391
13392 if (!crtc_clock || !cdclk)
13393 return DRM_PLANE_HELPER_NO_SCALING;
13394
13395 /*
13396 * skl max scale is lower of:
13397 * close to 3 but not 3, -1 is for that purpose
13398 * or
13399 * cdclk/crtc_clock
13400 */
13401 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13402
13403 return max_scale;
13404}
13405
13406static int
13407intel_check_primary_plane(struct drm_plane *plane,
13408 struct intel_crtc_state *crtc_state,
13409 struct intel_plane_state *state)
13410{
13411 struct drm_crtc *crtc = state->base.crtc;
13412 struct drm_framebuffer *fb = state->base.fb;
13413 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13414 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13415 bool can_position = false;
13416
13417 /* use scaler when colorkey is not required */
13418 if (INTEL_INFO(plane->dev)->gen >= 9 &&
13419 state->ckey.flags == I915_SET_COLORKEY_NONE) {
13420 min_scale = 1;
13421 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13422 can_position = true;
13423 }
13424
13425 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13426 &state->dst, &state->clip,
13427 min_scale, max_scale,
13428 can_position, true,
13429 &state->visible);
13430}
13431
13432static void
13433intel_commit_primary_plane(struct drm_plane *plane,
13434 struct intel_plane_state *state)
13435{
13436 struct drm_crtc *crtc = state->base.crtc;
13437 struct drm_framebuffer *fb = state->base.fb;
13438 struct drm_device *dev = plane->dev;
13439 struct drm_i915_private *dev_priv = dev->dev_private;
13440 struct intel_crtc *intel_crtc;
13441 struct drm_rect *src = &state->src;
13442
13443 crtc = crtc ? crtc : plane->crtc;
13444 intel_crtc = to_intel_crtc(crtc);
13445
13446 plane->fb = fb;
13447 crtc->x = src->x1 >> 16;
13448 crtc->y = src->y1 >> 16;
13449
13450 if (!crtc->state->active)
13451 return;
13452
13453 if (state->visible)
13454 /* FIXME: kill this fastboot hack */
13455 intel_update_pipe_size(intel_crtc);
13456
13457 dev_priv->display.update_primary_plane(crtc, fb, crtc->x, crtc->y);
13458}
13459
13460static void
13461intel_disable_primary_plane(struct drm_plane *plane,
13462 struct drm_crtc *crtc)
13463{
13464 struct drm_device *dev = plane->dev;
13465 struct drm_i915_private *dev_priv = dev->dev_private;
13466
13467 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13468}
13469
13470static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13471 struct drm_crtc_state *old_crtc_state)
13472{
13473 struct drm_device *dev = crtc->dev;
13474 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13475
13476 if (intel_crtc->atomic.update_wm_pre)
13477 intel_update_watermarks(crtc);
13478
13479 /* Perform vblank evasion around commit operation */
13480 if (crtc->state->active)
13481 intel_pipe_update_start(intel_crtc, &intel_crtc->start_vbl_count);
13482
13483 if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
13484 skl_detach_scalers(intel_crtc);
13485}
13486
13487static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13488 struct drm_crtc_state *old_crtc_state)
13489{
13490 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13491
13492 if (crtc->state->active)
13493 intel_pipe_update_end(intel_crtc, intel_crtc->start_vbl_count);
13494}
13495
13496/**
13497 * intel_plane_destroy - destroy a plane
13498 * @plane: plane to destroy
13499 *
13500 * Common destruction function for all types of planes (primary, cursor,
13501 * sprite).
13502 */
13503void intel_plane_destroy(struct drm_plane *plane)
13504{
13505 struct intel_plane *intel_plane = to_intel_plane(plane);
13506 drm_plane_cleanup(plane);
13507 kfree(intel_plane);
13508}
13509
13510const struct drm_plane_funcs intel_plane_funcs = {
13511 .update_plane = drm_atomic_helper_update_plane,
13512 .disable_plane = drm_atomic_helper_disable_plane,
13513 .destroy = intel_plane_destroy,
13514 .set_property = drm_atomic_helper_plane_set_property,
13515 .atomic_get_property = intel_plane_atomic_get_property,
13516 .atomic_set_property = intel_plane_atomic_set_property,
13517 .atomic_duplicate_state = intel_plane_duplicate_state,
13518 .atomic_destroy_state = intel_plane_destroy_state,
13519
13520};
13521
13522static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13523 int pipe)
13524{
13525 struct intel_plane *primary;
13526 struct intel_plane_state *state;
13527 const uint32_t *intel_primary_formats;
13528 unsigned int num_formats;
13529
13530 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13531 if (primary == NULL)
13532 return NULL;
13533
13534 state = intel_create_plane_state(&primary->base);
13535 if (!state) {
13536 kfree(primary);
13537 return NULL;
13538 }
13539 primary->base.state = &state->base;
13540
13541 primary->can_scale = false;
13542 primary->max_downscale = 1;
13543 if (INTEL_INFO(dev)->gen >= 9) {
13544 primary->can_scale = true;
13545 state->scaler_id = -1;
13546 }
13547 primary->pipe = pipe;
13548 primary->plane = pipe;
13549 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13550 primary->check_plane = intel_check_primary_plane;
13551 primary->commit_plane = intel_commit_primary_plane;
13552 primary->disable_plane = intel_disable_primary_plane;
13553 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13554 primary->plane = !pipe;
13555
13556 if (INTEL_INFO(dev)->gen >= 9) {
13557 intel_primary_formats = skl_primary_formats;
13558 num_formats = ARRAY_SIZE(skl_primary_formats);
13559 } else if (INTEL_INFO(dev)->gen >= 4) {
13560 intel_primary_formats = i965_primary_formats;
13561 num_formats = ARRAY_SIZE(i965_primary_formats);
13562 } else {
13563 intel_primary_formats = i8xx_primary_formats;
13564 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13565 }
13566
13567 drm_universal_plane_init(dev, &primary->base, 0,
13568 &intel_plane_funcs,
13569 intel_primary_formats, num_formats,
13570 DRM_PLANE_TYPE_PRIMARY);
13571
13572 if (INTEL_INFO(dev)->gen >= 4)
13573 intel_create_rotation_property(dev, primary);
13574
13575 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13576
13577 return &primary->base;
13578}
13579
13580void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13581{
13582 if (!dev->mode_config.rotation_property) {
13583 unsigned long flags = BIT(DRM_ROTATE_0) |
13584 BIT(DRM_ROTATE_180);
13585
13586 if (INTEL_INFO(dev)->gen >= 9)
13587 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13588
13589 dev->mode_config.rotation_property =
13590 drm_mode_create_rotation_property(dev, flags);
13591 }
13592 if (dev->mode_config.rotation_property)
13593 drm_object_attach_property(&plane->base.base,
13594 dev->mode_config.rotation_property,
13595 plane->base.state->rotation);
13596}
13597
13598static int
13599intel_check_cursor_plane(struct drm_plane *plane,
13600 struct intel_crtc_state *crtc_state,
13601 struct intel_plane_state *state)
13602{
13603 struct drm_crtc *crtc = crtc_state->base.crtc;
13604 struct drm_framebuffer *fb = state->base.fb;
13605 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13606 unsigned stride;
13607 int ret;
13608
13609 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13610 &state->dst, &state->clip,
13611 DRM_PLANE_HELPER_NO_SCALING,
13612 DRM_PLANE_HELPER_NO_SCALING,
13613 true, true, &state->visible);
13614 if (ret)
13615 return ret;
13616
13617 /* if we want to turn off the cursor ignore width and height */
13618 if (!obj)
13619 return 0;
13620
13621 /* Check for which cursor types we support */
13622 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13623 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13624 state->base.crtc_w, state->base.crtc_h);
13625 return -EINVAL;
13626 }
13627
13628 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13629 if (obj->base.size < stride * state->base.crtc_h) {
13630 DRM_DEBUG_KMS("buffer is too small\n");
13631 return -ENOMEM;
13632 }
13633
13634 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13635 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13636 return -EINVAL;
13637 }
13638
13639 return 0;
13640}
13641
13642static void
13643intel_disable_cursor_plane(struct drm_plane *plane,
13644 struct drm_crtc *crtc)
13645{
13646 intel_crtc_update_cursor(crtc, false);
13647}
13648
13649static void
13650intel_commit_cursor_plane(struct drm_plane *plane,
13651 struct intel_plane_state *state)
13652{
13653 struct drm_crtc *crtc = state->base.crtc;
13654 struct drm_device *dev = plane->dev;
13655 struct intel_crtc *intel_crtc;
13656 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13657 uint32_t addr;
13658
13659 crtc = crtc ? crtc : plane->crtc;
13660 intel_crtc = to_intel_crtc(crtc);
13661
13662 plane->fb = state->base.fb;
13663 crtc->cursor_x = state->base.crtc_x;
13664 crtc->cursor_y = state->base.crtc_y;
13665
13666 if (intel_crtc->cursor_bo == obj)
13667 goto update;
13668
13669 if (!obj)
13670 addr = 0;
13671 else if (!INTEL_INFO(dev)->cursor_needs_physical)
13672 addr = i915_gem_obj_ggtt_offset(obj);
13673 else
13674 addr = obj->phys_handle->busaddr;
13675
13676 intel_crtc->cursor_addr = addr;
13677 intel_crtc->cursor_bo = obj;
13678
13679update:
13680 if (crtc->state->active)
13681 intel_crtc_update_cursor(crtc, state->visible);
13682}
13683
13684static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13685 int pipe)
13686{
13687 struct intel_plane *cursor;
13688 struct intel_plane_state *state;
13689
13690 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13691 if (cursor == NULL)
13692 return NULL;
13693
13694 state = intel_create_plane_state(&cursor->base);
13695 if (!state) {
13696 kfree(cursor);
13697 return NULL;
13698 }
13699 cursor->base.state = &state->base;
13700
13701 cursor->can_scale = false;
13702 cursor->max_downscale = 1;
13703 cursor->pipe = pipe;
13704 cursor->plane = pipe;
13705 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13706 cursor->check_plane = intel_check_cursor_plane;
13707 cursor->commit_plane = intel_commit_cursor_plane;
13708 cursor->disable_plane = intel_disable_cursor_plane;
13709
13710 drm_universal_plane_init(dev, &cursor->base, 0,
13711 &intel_plane_funcs,
13712 intel_cursor_formats,
13713 ARRAY_SIZE(intel_cursor_formats),
13714 DRM_PLANE_TYPE_CURSOR);
13715
13716 if (INTEL_INFO(dev)->gen >= 4) {
13717 if (!dev->mode_config.rotation_property)
13718 dev->mode_config.rotation_property =
13719 drm_mode_create_rotation_property(dev,
13720 BIT(DRM_ROTATE_0) |
13721 BIT(DRM_ROTATE_180));
13722 if (dev->mode_config.rotation_property)
13723 drm_object_attach_property(&cursor->base.base,
13724 dev->mode_config.rotation_property,
13725 state->base.rotation);
13726 }
13727
13728 if (INTEL_INFO(dev)->gen >=9)
13729 state->scaler_id = -1;
13730
13731 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13732
13733 return &cursor->base;
13734}
13735
13736static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13737 struct intel_crtc_state *crtc_state)
13738{
13739 int i;
13740 struct intel_scaler *intel_scaler;
13741 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13742
13743 for (i = 0; i < intel_crtc->num_scalers; i++) {
13744 intel_scaler = &scaler_state->scalers[i];
13745 intel_scaler->in_use = 0;
13746 intel_scaler->mode = PS_SCALER_MODE_DYN;
13747 }
13748
13749 scaler_state->scaler_id = -1;
13750}
13751
13752static void intel_crtc_init(struct drm_device *dev, int pipe)
13753{
13754 struct drm_i915_private *dev_priv = dev->dev_private;
13755 struct intel_crtc *intel_crtc;
13756 struct intel_crtc_state *crtc_state = NULL;
13757 struct drm_plane *primary = NULL;
13758 struct drm_plane *cursor = NULL;
13759 int i, ret;
13760
13761 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13762 if (intel_crtc == NULL)
13763 return;
13764
13765 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13766 if (!crtc_state)
13767 goto fail;
13768 intel_crtc->config = crtc_state;
13769 intel_crtc->base.state = &crtc_state->base;
13770 crtc_state->base.crtc = &intel_crtc->base;
13771
13772 /* initialize shared scalers */
13773 if (INTEL_INFO(dev)->gen >= 9) {
13774 if (pipe == PIPE_C)
13775 intel_crtc->num_scalers = 1;
13776 else
13777 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13778
13779 skl_init_scalers(dev, intel_crtc, crtc_state);
13780 }
13781
13782 primary = intel_primary_plane_create(dev, pipe);
13783 if (!primary)
13784 goto fail;
13785
13786 cursor = intel_cursor_plane_create(dev, pipe);
13787 if (!cursor)
13788 goto fail;
13789
13790 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13791 cursor, &intel_crtc_funcs);
13792 if (ret)
13793 goto fail;
13794
13795 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13796 for (i = 0; i < 256; i++) {
13797 intel_crtc->lut_r[i] = i;
13798 intel_crtc->lut_g[i] = i;
13799 intel_crtc->lut_b[i] = i;
13800 }
13801
13802 /*
13803 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13804 * is hooked to pipe B. Hence we want plane A feeding pipe B.
13805 */
13806 intel_crtc->pipe = pipe;
13807 intel_crtc->plane = pipe;
13808 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13809 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13810 intel_crtc->plane = !pipe;
13811 }
13812
13813 intel_crtc->cursor_base = ~0;
13814 intel_crtc->cursor_cntl = ~0;
13815 intel_crtc->cursor_size = ~0;
13816
13817 intel_crtc->wm.cxsr_allowed = true;
13818
13819 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13820 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13821 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13822 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13823
13824 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13825
13826 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13827 return;
13828
13829fail:
13830 if (primary)
13831 drm_plane_cleanup(primary);
13832 if (cursor)
13833 drm_plane_cleanup(cursor);
13834 kfree(crtc_state);
13835 kfree(intel_crtc);
13836}
13837
13838enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13839{
13840 struct drm_encoder *encoder = connector->base.encoder;
13841 struct drm_device *dev = connector->base.dev;
13842
13843 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13844
13845 if (!encoder || WARN_ON(!encoder->crtc))
13846 return INVALID_PIPE;
13847
13848 return to_intel_crtc(encoder->crtc)->pipe;
13849}
13850
13851int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13852 struct drm_file *file)
13853{
13854 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13855 struct drm_crtc *drmmode_crtc;
13856 struct intel_crtc *crtc;
13857
13858 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13859
13860 if (!drmmode_crtc) {
13861 DRM_ERROR("no such CRTC id\n");
13862 return -ENOENT;
13863 }
13864
13865 crtc = to_intel_crtc(drmmode_crtc);
13866 pipe_from_crtc_id->pipe = crtc->pipe;
13867
13868 return 0;
13869}
13870
13871static int intel_encoder_clones(struct intel_encoder *encoder)
13872{
13873 struct drm_device *dev = encoder->base.dev;
13874 struct intel_encoder *source_encoder;
13875 int index_mask = 0;
13876 int entry = 0;
13877
13878 for_each_intel_encoder(dev, source_encoder) {
13879 if (encoders_cloneable(encoder, source_encoder))
13880 index_mask |= (1 << entry);
13881
13882 entry++;
13883 }
13884
13885 return index_mask;
13886}
13887
13888static bool has_edp_a(struct drm_device *dev)
13889{
13890 struct drm_i915_private *dev_priv = dev->dev_private;
13891
13892 if (!IS_MOBILE(dev))
13893 return false;
13894
13895 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13896 return false;
13897
13898 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13899 return false;
13900
13901 return true;
13902}
13903
13904static bool intel_crt_present(struct drm_device *dev)
13905{
13906 struct drm_i915_private *dev_priv = dev->dev_private;
13907
13908 if (INTEL_INFO(dev)->gen >= 9)
13909 return false;
13910
13911 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13912 return false;
13913
13914 if (IS_CHERRYVIEW(dev))
13915 return false;
13916
13917 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13918 return false;
13919
13920 return true;
13921}
13922
13923static void intel_setup_outputs(struct drm_device *dev)
13924{
13925 struct drm_i915_private *dev_priv = dev->dev_private;
13926 struct intel_encoder *encoder;
13927 bool dpd_is_edp = false;
13928
13929 intel_lvds_init(dev);
13930
13931 if (intel_crt_present(dev))
13932 intel_crt_init(dev);
13933
13934 if (IS_BROXTON(dev)) {
13935 /*
13936 * FIXME: Broxton doesn't support port detection via the
13937 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13938 * detect the ports.
13939 */
13940 intel_ddi_init(dev, PORT_A);
13941 intel_ddi_init(dev, PORT_B);
13942 intel_ddi_init(dev, PORT_C);
13943 } else if (HAS_DDI(dev)) {
13944 int found;
13945
13946 /*
13947 * Haswell uses DDI functions to detect digital outputs.
13948 * On SKL pre-D0 the strap isn't connected, so we assume
13949 * it's there.
13950 */
13951 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
13952 /* WaIgnoreDDIAStrap: skl */
13953 if (found || IS_SKYLAKE(dev))
13954 intel_ddi_init(dev, PORT_A);
13955
13956 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13957 * register */
13958 found = I915_READ(SFUSE_STRAP);
13959
13960 if (found & SFUSE_STRAP_DDIB_DETECTED)
13961 intel_ddi_init(dev, PORT_B);
13962 if (found & SFUSE_STRAP_DDIC_DETECTED)
13963 intel_ddi_init(dev, PORT_C);
13964 if (found & SFUSE_STRAP_DDID_DETECTED)
13965 intel_ddi_init(dev, PORT_D);
13966 /*
13967 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
13968 */
13969 if (IS_SKYLAKE(dev) &&
13970 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
13971 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
13972 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
13973 intel_ddi_init(dev, PORT_E);
13974
13975 } else if (HAS_PCH_SPLIT(dev)) {
13976 int found;
13977 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
13978
13979 if (has_edp_a(dev))
13980 intel_dp_init(dev, DP_A, PORT_A);
13981
13982 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13983 /* PCH SDVOB multiplex with HDMIB */
13984 found = intel_sdvo_init(dev, PCH_SDVOB, true);
13985 if (!found)
13986 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
13987 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13988 intel_dp_init(dev, PCH_DP_B, PORT_B);
13989 }
13990
13991 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13992 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
13993
13994 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13995 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
13996
13997 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13998 intel_dp_init(dev, PCH_DP_C, PORT_C);
13999
14000 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14001 intel_dp_init(dev, PCH_DP_D, PORT_D);
14002 } else if (IS_VALLEYVIEW(dev)) {
14003 /*
14004 * The DP_DETECTED bit is the latched state of the DDC
14005 * SDA pin at boot. However since eDP doesn't require DDC
14006 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14007 * eDP ports may have been muxed to an alternate function.
14008 * Thus we can't rely on the DP_DETECTED bit alone to detect
14009 * eDP ports. Consult the VBT as well as DP_DETECTED to
14010 * detect eDP ports.
14011 */
14012 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14013 !intel_dp_is_edp(dev, PORT_B))
14014 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14015 PORT_B);
14016 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14017 intel_dp_is_edp(dev, PORT_B))
14018 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
14019
14020 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14021 !intel_dp_is_edp(dev, PORT_C))
14022 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14023 PORT_C);
14024 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14025 intel_dp_is_edp(dev, PORT_C))
14026 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
14027
14028 if (IS_CHERRYVIEW(dev)) {
14029 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
14030 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14031 PORT_D);
14032 /* eDP not supported on port D, so don't check VBT */
14033 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14034 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
14035 }
14036
14037 intel_dsi_init(dev);
14038 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14039 bool found = false;
14040
14041 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14042 DRM_DEBUG_KMS("probing SDVOB\n");
14043 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14044 if (!found && IS_G4X(dev)) {
14045 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14046 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14047 }
14048
14049 if (!found && IS_G4X(dev))
14050 intel_dp_init(dev, DP_B, PORT_B);
14051 }
14052
14053 /* Before G4X SDVOC doesn't have its own detect register */
14054
14055 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14056 DRM_DEBUG_KMS("probing SDVOC\n");
14057 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14058 }
14059
14060 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14061
14062 if (IS_G4X(dev)) {
14063 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14064 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14065 }
14066 if (IS_G4X(dev))
14067 intel_dp_init(dev, DP_C, PORT_C);
14068 }
14069
14070 if (IS_G4X(dev) &&
14071 (I915_READ(DP_D) & DP_DETECTED))
14072 intel_dp_init(dev, DP_D, PORT_D);
14073 } else if (IS_GEN2(dev))
14074 intel_dvo_init(dev);
14075
14076 if (SUPPORTS_TV(dev))
14077 intel_tv_init(dev);
14078
14079 intel_psr_init(dev);
14080
14081 for_each_intel_encoder(dev, encoder) {
14082 encoder->base.possible_crtcs = encoder->crtc_mask;
14083 encoder->base.possible_clones =
14084 intel_encoder_clones(encoder);
14085 }
14086
14087 intel_init_pch_refclk(dev);
14088
14089 drm_helper_move_panel_connectors_to_head(dev);
14090}
14091
14092static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14093{
14094 struct drm_device *dev = fb->dev;
14095 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14096
14097 drm_framebuffer_cleanup(fb);
14098 mutex_lock(&dev->struct_mutex);
14099 WARN_ON(!intel_fb->obj->framebuffer_references--);
14100 drm_gem_object_unreference(&intel_fb->obj->base);
14101 mutex_unlock(&dev->struct_mutex);
14102 kfree(intel_fb);
14103}
14104
14105static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14106 struct drm_file *file,
14107 unsigned int *handle)
14108{
14109 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14110 struct drm_i915_gem_object *obj = intel_fb->obj;
14111
14112 return drm_gem_handle_create(file, &obj->base, handle);
14113}
14114
14115static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14116 struct drm_file *file,
14117 unsigned flags, unsigned color,
14118 struct drm_clip_rect *clips,
14119 unsigned num_clips)
14120{
14121 struct drm_device *dev = fb->dev;
14122 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14123 struct drm_i915_gem_object *obj = intel_fb->obj;
14124
14125 mutex_lock(&dev->struct_mutex);
14126 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14127 mutex_unlock(&dev->struct_mutex);
14128
14129 return 0;
14130}
14131
14132static const struct drm_framebuffer_funcs intel_fb_funcs = {
14133 .destroy = intel_user_framebuffer_destroy,
14134 .create_handle = intel_user_framebuffer_create_handle,
14135 .dirty = intel_user_framebuffer_dirty,
14136};
14137
14138static
14139u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14140 uint32_t pixel_format)
14141{
14142 u32 gen = INTEL_INFO(dev)->gen;
14143
14144 if (gen >= 9) {
14145 /* "The stride in bytes must not exceed the of the size of 8K
14146 * pixels and 32K bytes."
14147 */
14148 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14149 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14150 return 32*1024;
14151 } else if (gen >= 4) {
14152 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14153 return 16*1024;
14154 else
14155 return 32*1024;
14156 } else if (gen >= 3) {
14157 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14158 return 8*1024;
14159 else
14160 return 16*1024;
14161 } else {
14162 /* XXX DSPC is limited to 4k tiled */
14163 return 8*1024;
14164 }
14165}
14166
14167static int intel_framebuffer_init(struct drm_device *dev,
14168 struct intel_framebuffer *intel_fb,
14169 struct drm_mode_fb_cmd2 *mode_cmd,
14170 struct drm_i915_gem_object *obj)
14171{
14172 unsigned int aligned_height;
14173 int ret;
14174 u32 pitch_limit, stride_alignment;
14175
14176 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14177
14178 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14179 /* Enforce that fb modifier and tiling mode match, but only for
14180 * X-tiled. This is needed for FBC. */
14181 if (!!(obj->tiling_mode == I915_TILING_X) !=
14182 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14183 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14184 return -EINVAL;
14185 }
14186 } else {
14187 if (obj->tiling_mode == I915_TILING_X)
14188 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14189 else if (obj->tiling_mode == I915_TILING_Y) {
14190 DRM_DEBUG("No Y tiling for legacy addfb\n");
14191 return -EINVAL;
14192 }
14193 }
14194
14195 /* Passed in modifier sanity checking. */
14196 switch (mode_cmd->modifier[0]) {
14197 case I915_FORMAT_MOD_Y_TILED:
14198 case I915_FORMAT_MOD_Yf_TILED:
14199 if (INTEL_INFO(dev)->gen < 9) {
14200 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14201 mode_cmd->modifier[0]);
14202 return -EINVAL;
14203 }
14204 case DRM_FORMAT_MOD_NONE:
14205 case I915_FORMAT_MOD_X_TILED:
14206 break;
14207 default:
14208 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14209 mode_cmd->modifier[0]);
14210 return -EINVAL;
14211 }
14212
14213 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14214 mode_cmd->pixel_format);
14215 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14216 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14217 mode_cmd->pitches[0], stride_alignment);
14218 return -EINVAL;
14219 }
14220
14221 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14222 mode_cmd->pixel_format);
14223 if (mode_cmd->pitches[0] > pitch_limit) {
14224 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14225 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14226 "tiled" : "linear",
14227 mode_cmd->pitches[0], pitch_limit);
14228 return -EINVAL;
14229 }
14230
14231 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14232 mode_cmd->pitches[0] != obj->stride) {
14233 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14234 mode_cmd->pitches[0], obj->stride);
14235 return -EINVAL;
14236 }
14237
14238 /* Reject formats not supported by any plane early. */
14239 switch (mode_cmd->pixel_format) {
14240 case DRM_FORMAT_C8:
14241 case DRM_FORMAT_RGB565:
14242 case DRM_FORMAT_XRGB8888:
14243 case DRM_FORMAT_ARGB8888:
14244 break;
14245 case DRM_FORMAT_XRGB1555:
14246 if (INTEL_INFO(dev)->gen > 3) {
14247 DRM_DEBUG("unsupported pixel format: %s\n",
14248 drm_get_format_name(mode_cmd->pixel_format));
14249 return -EINVAL;
14250 }
14251 break;
14252 case DRM_FORMAT_ABGR8888:
14253 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14254 DRM_DEBUG("unsupported pixel format: %s\n",
14255 drm_get_format_name(mode_cmd->pixel_format));
14256 return -EINVAL;
14257 }
14258 break;
14259 case DRM_FORMAT_XBGR8888:
14260 case DRM_FORMAT_XRGB2101010:
14261 case DRM_FORMAT_XBGR2101010:
14262 if (INTEL_INFO(dev)->gen < 4) {
14263 DRM_DEBUG("unsupported pixel format: %s\n",
14264 drm_get_format_name(mode_cmd->pixel_format));
14265 return -EINVAL;
14266 }
14267 break;
14268 case DRM_FORMAT_ABGR2101010:
14269 if (!IS_VALLEYVIEW(dev)) {
14270 DRM_DEBUG("unsupported pixel format: %s\n",
14271 drm_get_format_name(mode_cmd->pixel_format));
14272 return -EINVAL;
14273 }
14274 break;
14275 case DRM_FORMAT_YUYV:
14276 case DRM_FORMAT_UYVY:
14277 case DRM_FORMAT_YVYU:
14278 case DRM_FORMAT_VYUY:
14279 if (INTEL_INFO(dev)->gen < 5) {
14280 DRM_DEBUG("unsupported pixel format: %s\n",
14281 drm_get_format_name(mode_cmd->pixel_format));
14282 return -EINVAL;
14283 }
14284 break;
14285 default:
14286 DRM_DEBUG("unsupported pixel format: %s\n",
14287 drm_get_format_name(mode_cmd->pixel_format));
14288 return -EINVAL;
14289 }
14290
14291 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14292 if (mode_cmd->offsets[0] != 0)
14293 return -EINVAL;
14294
14295 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14296 mode_cmd->pixel_format,
14297 mode_cmd->modifier[0]);
14298 /* FIXME drm helper for size checks (especially planar formats)? */
14299 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14300 return -EINVAL;
14301
14302 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14303 intel_fb->obj = obj;
14304 intel_fb->obj->framebuffer_references++;
14305
14306 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14307 if (ret) {
14308 DRM_ERROR("framebuffer init failed %d\n", ret);
14309 return ret;
14310 }
14311
14312 return 0;
14313}
14314
14315static struct drm_framebuffer *
14316intel_user_framebuffer_create(struct drm_device *dev,
14317 struct drm_file *filp,
14318 struct drm_mode_fb_cmd2 *mode_cmd)
14319{
14320 struct drm_i915_gem_object *obj;
14321
14322 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14323 mode_cmd->handles[0]));
14324 if (&obj->base == NULL)
14325 return ERR_PTR(-ENOENT);
14326
14327 return intel_framebuffer_create(dev, mode_cmd, obj);
14328}
14329
14330#ifndef CONFIG_DRM_FBDEV_EMULATION
14331static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14332{
14333}
14334#endif
14335
14336static const struct drm_mode_config_funcs intel_mode_funcs = {
14337 .fb_create = intel_user_framebuffer_create,
14338 .output_poll_changed = intel_fbdev_output_poll_changed,
14339 .atomic_check = intel_atomic_check,
14340 .atomic_commit = intel_atomic_commit,
14341 .atomic_state_alloc = intel_atomic_state_alloc,
14342 .atomic_state_clear = intel_atomic_state_clear,
14343};
14344
14345/* Set up chip specific display functions */
14346static void intel_init_display(struct drm_device *dev)
14347{
14348 struct drm_i915_private *dev_priv = dev->dev_private;
14349
14350 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14351 dev_priv->display.find_dpll = g4x_find_best_dpll;
14352 else if (IS_CHERRYVIEW(dev))
14353 dev_priv->display.find_dpll = chv_find_best_dpll;
14354 else if (IS_VALLEYVIEW(dev))
14355 dev_priv->display.find_dpll = vlv_find_best_dpll;
14356 else if (IS_PINEVIEW(dev))
14357 dev_priv->display.find_dpll = pnv_find_best_dpll;
14358 else
14359 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14360
14361 if (INTEL_INFO(dev)->gen >= 9) {
14362 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14363 dev_priv->display.get_initial_plane_config =
14364 skylake_get_initial_plane_config;
14365 dev_priv->display.crtc_compute_clock =
14366 haswell_crtc_compute_clock;
14367 dev_priv->display.crtc_enable = haswell_crtc_enable;
14368 dev_priv->display.crtc_disable = haswell_crtc_disable;
14369 dev_priv->display.update_primary_plane =
14370 skylake_update_primary_plane;
14371 } else if (HAS_DDI(dev)) {
14372 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14373 dev_priv->display.get_initial_plane_config =
14374 ironlake_get_initial_plane_config;
14375 dev_priv->display.crtc_compute_clock =
14376 haswell_crtc_compute_clock;
14377 dev_priv->display.crtc_enable = haswell_crtc_enable;
14378 dev_priv->display.crtc_disable = haswell_crtc_disable;
14379 dev_priv->display.update_primary_plane =
14380 ironlake_update_primary_plane;
14381 } else if (HAS_PCH_SPLIT(dev)) {
14382 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14383 dev_priv->display.get_initial_plane_config =
14384 ironlake_get_initial_plane_config;
14385 dev_priv->display.crtc_compute_clock =
14386 ironlake_crtc_compute_clock;
14387 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14388 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14389 dev_priv->display.update_primary_plane =
14390 ironlake_update_primary_plane;
14391 } else if (IS_VALLEYVIEW(dev)) {
14392 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14393 dev_priv->display.get_initial_plane_config =
14394 i9xx_get_initial_plane_config;
14395 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14396 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14397 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14398 dev_priv->display.update_primary_plane =
14399 i9xx_update_primary_plane;
14400 } else {
14401 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14402 dev_priv->display.get_initial_plane_config =
14403 i9xx_get_initial_plane_config;
14404 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14405 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14406 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14407 dev_priv->display.update_primary_plane =
14408 i9xx_update_primary_plane;
14409 }
14410
14411 /* Returns the core display clock speed */
14412 if (IS_SKYLAKE(dev))
14413 dev_priv->display.get_display_clock_speed =
14414 skylake_get_display_clock_speed;
14415 else if (IS_BROXTON(dev))
14416 dev_priv->display.get_display_clock_speed =
14417 broxton_get_display_clock_speed;
14418 else if (IS_BROADWELL(dev))
14419 dev_priv->display.get_display_clock_speed =
14420 broadwell_get_display_clock_speed;
14421 else if (IS_HASWELL(dev))
14422 dev_priv->display.get_display_clock_speed =
14423 haswell_get_display_clock_speed;
14424 else if (IS_VALLEYVIEW(dev))
14425 dev_priv->display.get_display_clock_speed =
14426 valleyview_get_display_clock_speed;
14427 else if (IS_GEN5(dev))
14428 dev_priv->display.get_display_clock_speed =
14429 ilk_get_display_clock_speed;
14430 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14431 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14432 dev_priv->display.get_display_clock_speed =
14433 i945_get_display_clock_speed;
14434 else if (IS_GM45(dev))
14435 dev_priv->display.get_display_clock_speed =
14436 gm45_get_display_clock_speed;
14437 else if (IS_CRESTLINE(dev))
14438 dev_priv->display.get_display_clock_speed =
14439 i965gm_get_display_clock_speed;
14440 else if (IS_PINEVIEW(dev))
14441 dev_priv->display.get_display_clock_speed =
14442 pnv_get_display_clock_speed;
14443 else if (IS_G33(dev) || IS_G4X(dev))
14444 dev_priv->display.get_display_clock_speed =
14445 g33_get_display_clock_speed;
14446 else if (IS_I915G(dev))
14447 dev_priv->display.get_display_clock_speed =
14448 i915_get_display_clock_speed;
14449 else if (IS_I945GM(dev) || IS_845G(dev))
14450 dev_priv->display.get_display_clock_speed =
14451 i9xx_misc_get_display_clock_speed;
14452 else if (IS_PINEVIEW(dev))
14453 dev_priv->display.get_display_clock_speed =
14454 pnv_get_display_clock_speed;
14455 else if (IS_I915GM(dev))
14456 dev_priv->display.get_display_clock_speed =
14457 i915gm_get_display_clock_speed;
14458 else if (IS_I865G(dev))
14459 dev_priv->display.get_display_clock_speed =
14460 i865_get_display_clock_speed;
14461 else if (IS_I85X(dev))
14462 dev_priv->display.get_display_clock_speed =
14463 i85x_get_display_clock_speed;
14464 else { /* 830 */
14465 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14466 dev_priv->display.get_display_clock_speed =
14467 i830_get_display_clock_speed;
14468 }
14469
14470 if (IS_GEN5(dev)) {
14471 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14472 } else if (IS_GEN6(dev)) {
14473 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14474 } else if (IS_IVYBRIDGE(dev)) {
14475 /* FIXME: detect B0+ stepping and use auto training */
14476 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14477 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14478 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14479 if (IS_BROADWELL(dev)) {
14480 dev_priv->display.modeset_commit_cdclk =
14481 broadwell_modeset_commit_cdclk;
14482 dev_priv->display.modeset_calc_cdclk =
14483 broadwell_modeset_calc_cdclk;
14484 }
14485 } else if (IS_VALLEYVIEW(dev)) {
14486 dev_priv->display.modeset_commit_cdclk =
14487 valleyview_modeset_commit_cdclk;
14488 dev_priv->display.modeset_calc_cdclk =
14489 valleyview_modeset_calc_cdclk;
14490 } else if (IS_BROXTON(dev)) {
14491 dev_priv->display.modeset_commit_cdclk =
14492 broxton_modeset_commit_cdclk;
14493 dev_priv->display.modeset_calc_cdclk =
14494 broxton_modeset_calc_cdclk;
14495 }
14496
14497 switch (INTEL_INFO(dev)->gen) {
14498 case 2:
14499 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14500 break;
14501
14502 case 3:
14503 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14504 break;
14505
14506 case 4:
14507 case 5:
14508 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14509 break;
14510
14511 case 6:
14512 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14513 break;
14514 case 7:
14515 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14516 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14517 break;
14518 case 9:
14519 /* Drop through - unsupported since execlist only. */
14520 default:
14521 /* Default just returns -ENODEV to indicate unsupported */
14522 dev_priv->display.queue_flip = intel_default_queue_flip;
14523 }
14524
14525 intel_panel_init_backlight_funcs(dev);
14526
14527 mutex_init(&dev_priv->pps_mutex);
14528}
14529
14530/*
14531 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14532 * resume, or other times. This quirk makes sure that's the case for
14533 * affected systems.
14534 */
14535static void quirk_pipea_force(struct drm_device *dev)
14536{
14537 struct drm_i915_private *dev_priv = dev->dev_private;
14538
14539 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14540 DRM_INFO("applying pipe a force quirk\n");
14541}
14542
14543static void quirk_pipeb_force(struct drm_device *dev)
14544{
14545 struct drm_i915_private *dev_priv = dev->dev_private;
14546
14547 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14548 DRM_INFO("applying pipe b force quirk\n");
14549}
14550
14551/*
14552 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14553 */
14554static void quirk_ssc_force_disable(struct drm_device *dev)
14555{
14556 struct drm_i915_private *dev_priv = dev->dev_private;
14557 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14558 DRM_INFO("applying lvds SSC disable quirk\n");
14559}
14560
14561/*
14562 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14563 * brightness value
14564 */
14565static void quirk_invert_brightness(struct drm_device *dev)
14566{
14567 struct drm_i915_private *dev_priv = dev->dev_private;
14568 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14569 DRM_INFO("applying inverted panel brightness quirk\n");
14570}
14571
14572/* Some VBT's incorrectly indicate no backlight is present */
14573static void quirk_backlight_present(struct drm_device *dev)
14574{
14575 struct drm_i915_private *dev_priv = dev->dev_private;
14576 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14577 DRM_INFO("applying backlight present quirk\n");
14578}
14579
14580struct intel_quirk {
14581 int device;
14582 int subsystem_vendor;
14583 int subsystem_device;
14584 void (*hook)(struct drm_device *dev);
14585};
14586
14587/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14588struct intel_dmi_quirk {
14589 void (*hook)(struct drm_device *dev);
14590 const struct dmi_system_id (*dmi_id_list)[];
14591};
14592
14593static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14594{
14595 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14596 return 1;
14597}
14598
14599static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14600 {
14601 .dmi_id_list = &(const struct dmi_system_id[]) {
14602 {
14603 .callback = intel_dmi_reverse_brightness,
14604 .ident = "NCR Corporation",
14605 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14606 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14607 },
14608 },
14609 { } /* terminating entry */
14610 },
14611 .hook = quirk_invert_brightness,
14612 },
14613};
14614
14615static struct intel_quirk intel_quirks[] = {
14616 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14617 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14618
14619 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14620 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14621
14622 /* 830 needs to leave pipe A & dpll A up */
14623 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14624
14625 /* 830 needs to leave pipe B & dpll B up */
14626 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14627
14628 /* Lenovo U160 cannot use SSC on LVDS */
14629 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14630
14631 /* Sony Vaio Y cannot use SSC on LVDS */
14632 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14633
14634 /* Acer Aspire 5734Z must invert backlight brightness */
14635 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14636
14637 /* Acer/eMachines G725 */
14638 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14639
14640 /* Acer/eMachines e725 */
14641 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14642
14643 /* Acer/Packard Bell NCL20 */
14644 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14645
14646 /* Acer Aspire 4736Z */
14647 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14648
14649 /* Acer Aspire 5336 */
14650 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14651
14652 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14653 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14654
14655 /* Acer C720 Chromebook (Core i3 4005U) */
14656 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14657
14658 /* Apple Macbook 2,1 (Core 2 T7400) */
14659 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14660
14661 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14662 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14663
14664 /* HP Chromebook 14 (Celeron 2955U) */
14665 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14666
14667 /* Dell Chromebook 11 */
14668 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14669};
14670
14671static void intel_init_quirks(struct drm_device *dev)
14672{
14673 struct pci_dev *d = dev->pdev;
14674 int i;
14675
14676 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14677 struct intel_quirk *q = &intel_quirks[i];
14678
14679 if (d->device == q->device &&
14680 (d->subsystem_vendor == q->subsystem_vendor ||
14681 q->subsystem_vendor == PCI_ANY_ID) &&
14682 (d->subsystem_device == q->subsystem_device ||
14683 q->subsystem_device == PCI_ANY_ID))
14684 q->hook(dev);
14685 }
14686 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14687 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14688 intel_dmi_quirks[i].hook(dev);
14689 }
14690}
14691
14692/* Disable the VGA plane that we never use */
14693static void i915_disable_vga(struct drm_device *dev)
14694{
14695 struct drm_i915_private *dev_priv = dev->dev_private;
14696 u8 sr1;
14697 u32 vga_reg = i915_vgacntrl_reg(dev);
14698
14699 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14700 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14701 outb(SR01, VGA_SR_INDEX);
14702 sr1 = inb(VGA_SR_DATA);
14703 outb(sr1 | 1<<5, VGA_SR_DATA);
14704 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14705 udelay(300);
14706
14707 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14708 POSTING_READ(vga_reg);
14709}
14710
14711void intel_modeset_init_hw(struct drm_device *dev)
14712{
14713 intel_update_cdclk(dev);
14714 intel_prepare_ddi(dev);
14715 intel_init_clock_gating(dev);
14716 intel_enable_gt_powersave(dev);
14717}
14718
14719void intel_modeset_init(struct drm_device *dev)
14720{
14721 struct drm_i915_private *dev_priv = dev->dev_private;
14722 int sprite, ret;
14723 enum pipe pipe;
14724 struct intel_crtc *crtc;
14725
14726 drm_mode_config_init(dev);
14727
14728 dev->mode_config.min_width = 0;
14729 dev->mode_config.min_height = 0;
14730
14731 dev->mode_config.preferred_depth = 24;
14732 dev->mode_config.prefer_shadow = 1;
14733
14734 dev->mode_config.allow_fb_modifiers = true;
14735
14736 dev->mode_config.funcs = &intel_mode_funcs;
14737
14738 intel_init_quirks(dev);
14739
14740 intel_init_pm(dev);
14741
14742 if (INTEL_INFO(dev)->num_pipes == 0)
14743 return;
14744
14745 /*
14746 * There may be no VBT; and if the BIOS enabled SSC we can
14747 * just keep using it to avoid unnecessary flicker. Whereas if the
14748 * BIOS isn't using it, don't assume it will work even if the VBT
14749 * indicates as much.
14750 */
14751 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
14752 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14753 DREF_SSC1_ENABLE);
14754
14755 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14756 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14757 bios_lvds_use_ssc ? "en" : "dis",
14758 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14759 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14760 }
14761 }
14762
14763 intel_init_display(dev);
14764 intel_init_audio(dev);
14765
14766 if (IS_GEN2(dev)) {
14767 dev->mode_config.max_width = 2048;
14768 dev->mode_config.max_height = 2048;
14769 } else if (IS_GEN3(dev)) {
14770 dev->mode_config.max_width = 4096;
14771 dev->mode_config.max_height = 4096;
14772 } else {
14773 dev->mode_config.max_width = 8192;
14774 dev->mode_config.max_height = 8192;
14775 }
14776
14777 if (IS_845G(dev) || IS_I865G(dev)) {
14778 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14779 dev->mode_config.cursor_height = 1023;
14780 } else if (IS_GEN2(dev)) {
14781 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14782 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14783 } else {
14784 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14785 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14786 }
14787
14788 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14789
14790 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14791 INTEL_INFO(dev)->num_pipes,
14792 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14793
14794 for_each_pipe(dev_priv, pipe) {
14795 intel_crtc_init(dev, pipe);
14796 for_each_sprite(dev_priv, pipe, sprite) {
14797 ret = intel_plane_init(dev, pipe, sprite);
14798 if (ret)
14799 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14800 pipe_name(pipe), sprite_name(pipe, sprite), ret);
14801 }
14802 }
14803
14804 intel_init_dpio(dev);
14805
14806 intel_shared_dpll_init(dev);
14807
14808 /* Just disable it once at startup */
14809 i915_disable_vga(dev);
14810 intel_setup_outputs(dev);
14811
14812 /* Just in case the BIOS is doing something questionable. */
14813 intel_fbc_disable(dev_priv);
14814
14815 drm_modeset_lock_all(dev);
14816 intel_modeset_setup_hw_state(dev);
14817 drm_modeset_unlock_all(dev);
14818
14819 for_each_intel_crtc(dev, crtc) {
14820 struct intel_initial_plane_config plane_config = {};
14821
14822 if (!crtc->active)
14823 continue;
14824
14825 /*
14826 * Note that reserving the BIOS fb up front prevents us
14827 * from stuffing other stolen allocations like the ring
14828 * on top. This prevents some ugliness at boot time, and
14829 * can even allow for smooth boot transitions if the BIOS
14830 * fb is large enough for the active pipe configuration.
14831 */
14832 dev_priv->display.get_initial_plane_config(crtc,
14833 &plane_config);
14834
14835 /*
14836 * If the fb is shared between multiple heads, we'll
14837 * just get the first one.
14838 */
14839 intel_find_initial_plane_obj(crtc, &plane_config);
14840 }
14841}
14842
14843static void intel_enable_pipe_a(struct drm_device *dev)
14844{
14845 struct intel_connector *connector;
14846 struct drm_connector *crt = NULL;
14847 struct intel_load_detect_pipe load_detect_temp;
14848 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14849
14850 /* We can't just switch on the pipe A, we need to set things up with a
14851 * proper mode and output configuration. As a gross hack, enable pipe A
14852 * by enabling the load detect pipe once. */
14853 for_each_intel_connector(dev, connector) {
14854 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14855 crt = &connector->base;
14856 break;
14857 }
14858 }
14859
14860 if (!crt)
14861 return;
14862
14863 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14864 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14865}
14866
14867static bool
14868intel_check_plane_mapping(struct intel_crtc *crtc)
14869{
14870 struct drm_device *dev = crtc->base.dev;
14871 struct drm_i915_private *dev_priv = dev->dev_private;
14872 u32 reg, val;
14873
14874 if (INTEL_INFO(dev)->num_pipes == 1)
14875 return true;
14876
14877 reg = DSPCNTR(!crtc->plane);
14878 val = I915_READ(reg);
14879
14880 if ((val & DISPLAY_PLANE_ENABLE) &&
14881 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14882 return false;
14883
14884 return true;
14885}
14886
14887static void intel_sanitize_crtc(struct intel_crtc *crtc)
14888{
14889 struct drm_device *dev = crtc->base.dev;
14890 struct drm_i915_private *dev_priv = dev->dev_private;
14891 struct intel_encoder *encoder;
14892 u32 reg;
14893 bool enable;
14894
14895 /* Clear any frame start delays used for debugging left by the BIOS */
14896 reg = PIPECONF(crtc->config->cpu_transcoder);
14897 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14898
14899 /* restore vblank interrupts to correct state */
14900 drm_crtc_vblank_reset(&crtc->base);
14901 if (crtc->active) {
14902 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
14903 update_scanline_offset(crtc);
14904 drm_crtc_vblank_on(&crtc->base);
14905 }
14906
14907 /* We need to sanitize the plane -> pipe mapping first because this will
14908 * disable the crtc (and hence change the state) if it is wrong. Note
14909 * that gen4+ has a fixed plane -> pipe mapping. */
14910 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
14911 bool plane;
14912
14913 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14914 crtc->base.base.id);
14915
14916 /* Pipe has the wrong plane attached and the plane is active.
14917 * Temporarily change the plane mapping and disable everything
14918 * ... */
14919 plane = crtc->plane;
14920 to_intel_plane_state(crtc->base.primary->state)->visible = true;
14921 crtc->plane = !plane;
14922 intel_crtc_disable_noatomic(&crtc->base);
14923 crtc->plane = plane;
14924 }
14925
14926 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14927 crtc->pipe == PIPE_A && !crtc->active) {
14928 /* BIOS forgot to enable pipe A, this mostly happens after
14929 * resume. Force-enable the pipe to fix this, the update_dpms
14930 * call below we restore the pipe to the right state, but leave
14931 * the required bits on. */
14932 intel_enable_pipe_a(dev);
14933 }
14934
14935 /* Adjust the state of the output pipe according to whether we
14936 * have active connectors/encoders. */
14937 enable = false;
14938 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14939 enable = true;
14940 break;
14941 }
14942
14943 if (!enable)
14944 intel_crtc_disable_noatomic(&crtc->base);
14945
14946 if (crtc->active != crtc->base.state->active) {
14947
14948 /* This can happen either due to bugs in the get_hw_state
14949 * functions or because of calls to intel_crtc_disable_noatomic,
14950 * or because the pipe is force-enabled due to the
14951 * pipe A quirk. */
14952 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14953 crtc->base.base.id,
14954 crtc->base.state->enable ? "enabled" : "disabled",
14955 crtc->active ? "enabled" : "disabled");
14956
14957 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
14958 crtc->base.state->active = crtc->active;
14959 crtc->base.enabled = crtc->active;
14960
14961 /* Because we only establish the connector -> encoder ->
14962 * crtc links if something is active, this means the
14963 * crtc is now deactivated. Break the links. connector
14964 * -> encoder links are only establish when things are
14965 * actually up, hence no need to break them. */
14966 WARN_ON(crtc->active);
14967
14968 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14969 encoder->base.crtc = NULL;
14970 }
14971
14972 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
14973 /*
14974 * We start out with underrun reporting disabled to avoid races.
14975 * For correct bookkeeping mark this on active crtcs.
14976 *
14977 * Also on gmch platforms we dont have any hardware bits to
14978 * disable the underrun reporting. Which means we need to start
14979 * out with underrun reporting disabled also on inactive pipes,
14980 * since otherwise we'll complain about the garbage we read when
14981 * e.g. coming up after runtime pm.
14982 *
14983 * No protection against concurrent access is required - at
14984 * worst a fifo underrun happens which also sets this to false.
14985 */
14986 crtc->cpu_fifo_underrun_disabled = true;
14987 crtc->pch_fifo_underrun_disabled = true;
14988 }
14989}
14990
14991static void intel_sanitize_encoder(struct intel_encoder *encoder)
14992{
14993 struct intel_connector *connector;
14994 struct drm_device *dev = encoder->base.dev;
14995 bool active = false;
14996
14997 /* We need to check both for a crtc link (meaning that the
14998 * encoder is active and trying to read from a pipe) and the
14999 * pipe itself being active. */
15000 bool has_active_crtc = encoder->base.crtc &&
15001 to_intel_crtc(encoder->base.crtc)->active;
15002
15003 for_each_intel_connector(dev, connector) {
15004 if (connector->base.encoder != &encoder->base)
15005 continue;
15006
15007 active = true;
15008 break;
15009 }
15010
15011 if (active && !has_active_crtc) {
15012 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15013 encoder->base.base.id,
15014 encoder->base.name);
15015
15016 /* Connector is active, but has no active pipe. This is
15017 * fallout from our resume register restoring. Disable
15018 * the encoder manually again. */
15019 if (encoder->base.crtc) {
15020 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15021 encoder->base.base.id,
15022 encoder->base.name);
15023 encoder->disable(encoder);
15024 if (encoder->post_disable)
15025 encoder->post_disable(encoder);
15026 }
15027 encoder->base.crtc = NULL;
15028
15029 /* Inconsistent output/port/pipe state happens presumably due to
15030 * a bug in one of the get_hw_state functions. Or someplace else
15031 * in our code, like the register restore mess on resume. Clamp
15032 * things to off as a safer default. */
15033 for_each_intel_connector(dev, connector) {
15034 if (connector->encoder != encoder)
15035 continue;
15036 connector->base.dpms = DRM_MODE_DPMS_OFF;
15037 connector->base.encoder = NULL;
15038 }
15039 }
15040 /* Enabled encoders without active connectors will be fixed in
15041 * the crtc fixup. */
15042}
15043
15044void i915_redisable_vga_power_on(struct drm_device *dev)
15045{
15046 struct drm_i915_private *dev_priv = dev->dev_private;
15047 u32 vga_reg = i915_vgacntrl_reg(dev);
15048
15049 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15050 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15051 i915_disable_vga(dev);
15052 }
15053}
15054
15055void i915_redisable_vga(struct drm_device *dev)
15056{
15057 struct drm_i915_private *dev_priv = dev->dev_private;
15058
15059 /* This function can be called both from intel_modeset_setup_hw_state or
15060 * at a very early point in our resume sequence, where the power well
15061 * structures are not yet restored. Since this function is at a very
15062 * paranoid "someone might have enabled VGA while we were not looking"
15063 * level, just check if the power well is enabled instead of trying to
15064 * follow the "don't touch the power well if we don't need it" policy
15065 * the rest of the driver uses. */
15066 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15067 return;
15068
15069 i915_redisable_vga_power_on(dev);
15070}
15071
15072static bool primary_get_hw_state(struct intel_crtc *crtc)
15073{
15074 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15075
15076 return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE);
15077}
15078
15079static void readout_plane_state(struct intel_crtc *crtc,
15080 struct intel_crtc_state *crtc_state)
15081{
15082 struct intel_plane *p;
15083 struct intel_plane_state *plane_state;
15084 bool active = crtc_state->base.active;
15085
15086 for_each_intel_plane(crtc->base.dev, p) {
15087 if (crtc->pipe != p->pipe)
15088 continue;
15089
15090 plane_state = to_intel_plane_state(p->base.state);
15091
15092 if (p->base.type == DRM_PLANE_TYPE_PRIMARY) {
15093 plane_state->visible = primary_get_hw_state(crtc);
15094 if (plane_state->visible)
15095 crtc->base.state->plane_mask |=
15096 1 << drm_plane_index(&p->base);
15097 } else {
15098 if (active)
15099 p->disable_plane(&p->base, &crtc->base);
15100
15101 plane_state->visible = false;
15102 }
15103 }
15104}
15105
15106static void intel_modeset_readout_hw_state(struct drm_device *dev)
15107{
15108 struct drm_i915_private *dev_priv = dev->dev_private;
15109 enum pipe pipe;
15110 struct intel_crtc *crtc;
15111 struct intel_encoder *encoder;
15112 struct intel_connector *connector;
15113 int i;
15114
15115 for_each_intel_crtc(dev, crtc) {
15116 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15117 memset(crtc->config, 0, sizeof(*crtc->config));
15118 crtc->config->base.crtc = &crtc->base;
15119
15120 crtc->active = dev_priv->display.get_pipe_config(crtc,
15121 crtc->config);
15122
15123 crtc->base.state->active = crtc->active;
15124 crtc->base.enabled = crtc->active;
15125
15126 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15127 if (crtc->base.state->active) {
15128 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15129 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15130 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15131
15132 /*
15133 * The initial mode needs to be set in order to keep
15134 * the atomic core happy. It wants a valid mode if the
15135 * crtc's enabled, so we do the above call.
15136 *
15137 * At this point some state updated by the connectors
15138 * in their ->detect() callback has not run yet, so
15139 * no recalculation can be done yet.
15140 *
15141 * Even if we could do a recalculation and modeset
15142 * right now it would cause a double modeset if
15143 * fbdev or userspace chooses a different initial mode.
15144 *
15145 * If that happens, someone indicated they wanted a
15146 * mode change, which means it's safe to do a full
15147 * recalculation.
15148 */
15149 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15150 }
15151
15152 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15153 readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
15154
15155 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15156 crtc->base.base.id,
15157 crtc->active ? "enabled" : "disabled");
15158 }
15159
15160 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15161 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15162
15163 pll->on = pll->get_hw_state(dev_priv, pll,
15164 &pll->config.hw_state);
15165 pll->active = 0;
15166 pll->config.crtc_mask = 0;
15167 for_each_intel_crtc(dev, crtc) {
15168 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15169 pll->active++;
15170 pll->config.crtc_mask |= 1 << crtc->pipe;
15171 }
15172 }
15173
15174 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15175 pll->name, pll->config.crtc_mask, pll->on);
15176
15177 if (pll->config.crtc_mask)
15178 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15179 }
15180
15181 for_each_intel_encoder(dev, encoder) {
15182 pipe = 0;
15183
15184 if (encoder->get_hw_state(encoder, &pipe)) {
15185 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15186 encoder->base.crtc = &crtc->base;
15187 encoder->get_config(encoder, crtc->config);
15188 } else {
15189 encoder->base.crtc = NULL;
15190 }
15191
15192 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15193 encoder->base.base.id,
15194 encoder->base.name,
15195 encoder->base.crtc ? "enabled" : "disabled",
15196 pipe_name(pipe));
15197 }
15198
15199 for_each_intel_connector(dev, connector) {
15200 if (connector->get_hw_state(connector)) {
15201 connector->base.dpms = DRM_MODE_DPMS_ON;
15202 connector->base.encoder = &connector->encoder->base;
15203 } else {
15204 connector->base.dpms = DRM_MODE_DPMS_OFF;
15205 connector->base.encoder = NULL;
15206 }
15207 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15208 connector->base.base.id,
15209 connector->base.name,
15210 connector->base.encoder ? "enabled" : "disabled");
15211 }
15212}
15213
15214/* Scan out the current hw modeset state,
15215 * and sanitizes it to the current state
15216 */
15217static void
15218intel_modeset_setup_hw_state(struct drm_device *dev)
15219{
15220 struct drm_i915_private *dev_priv = dev->dev_private;
15221 enum pipe pipe;
15222 struct intel_crtc *crtc;
15223 struct intel_encoder *encoder;
15224 int i;
15225
15226 intel_modeset_readout_hw_state(dev);
15227
15228 /* HW state is read out, now we need to sanitize this mess. */
15229 for_each_intel_encoder(dev, encoder) {
15230 intel_sanitize_encoder(encoder);
15231 }
15232
15233 for_each_pipe(dev_priv, pipe) {
15234 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15235 intel_sanitize_crtc(crtc);
15236 intel_dump_pipe_config(crtc, crtc->config,
15237 "[setup_hw_state]");
15238 }
15239
15240 intel_modeset_update_connector_atomic_state(dev);
15241
15242 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15243 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15244
15245 if (!pll->on || pll->active)
15246 continue;
15247
15248 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15249
15250 pll->disable(dev_priv, pll);
15251 pll->on = false;
15252 }
15253
15254 if (IS_VALLEYVIEW(dev))
15255 vlv_wm_get_hw_state(dev);
15256 else if (IS_GEN9(dev))
15257 skl_wm_get_hw_state(dev);
15258 else if (HAS_PCH_SPLIT(dev))
15259 ilk_wm_get_hw_state(dev);
15260
15261 for_each_intel_crtc(dev, crtc) {
15262 unsigned long put_domains;
15263
15264 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15265 if (WARN_ON(put_domains))
15266 modeset_put_power_domains(dev_priv, put_domains);
15267 }
15268 intel_display_set_init_power(dev_priv, false);
15269}
15270
15271void intel_display_resume(struct drm_device *dev)
15272{
15273 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15274 struct intel_connector *conn;
15275 struct intel_plane *plane;
15276 struct drm_crtc *crtc;
15277 int ret;
15278
15279 if (!state)
15280 return;
15281
15282 state->acquire_ctx = dev->mode_config.acquire_ctx;
15283
15284 /* preserve complete old state, including dpll */
15285 intel_atomic_get_shared_dpll_state(state);
15286
15287 for_each_crtc(dev, crtc) {
15288 struct drm_crtc_state *crtc_state =
15289 drm_atomic_get_crtc_state(state, crtc);
15290
15291 ret = PTR_ERR_OR_ZERO(crtc_state);
15292 if (ret)
15293 goto err;
15294
15295 /* force a restore */
15296 crtc_state->mode_changed = true;
15297 }
15298
15299 for_each_intel_plane(dev, plane) {
15300 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15301 if (ret)
15302 goto err;
15303 }
15304
15305 for_each_intel_connector(dev, conn) {
15306 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15307 if (ret)
15308 goto err;
15309 }
15310
15311 intel_modeset_setup_hw_state(dev);
15312
15313 i915_redisable_vga(dev);
15314 ret = drm_atomic_commit(state);
15315 if (!ret)
15316 return;
15317
15318err:
15319 DRM_ERROR("Restoring old state failed with %i\n", ret);
15320 drm_atomic_state_free(state);
15321}
15322
15323void intel_modeset_gem_init(struct drm_device *dev)
15324{
15325 struct drm_crtc *c;
15326 struct drm_i915_gem_object *obj;
15327 int ret;
15328
15329 mutex_lock(&dev->struct_mutex);
15330 intel_init_gt_powersave(dev);
15331 mutex_unlock(&dev->struct_mutex);
15332
15333 intel_modeset_init_hw(dev);
15334
15335 intel_setup_overlay(dev);
15336
15337 /*
15338 * Make sure any fbs we allocated at startup are properly
15339 * pinned & fenced. When we do the allocation it's too early
15340 * for this.
15341 */
15342 for_each_crtc(dev, c) {
15343 obj = intel_fb_obj(c->primary->fb);
15344 if (obj == NULL)
15345 continue;
15346
15347 mutex_lock(&dev->struct_mutex);
15348 ret = intel_pin_and_fence_fb_obj(c->primary,
15349 c->primary->fb,
15350 c->primary->state,
15351 NULL, NULL);
15352 mutex_unlock(&dev->struct_mutex);
15353 if (ret) {
15354 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15355 to_intel_crtc(c)->pipe);
15356 drm_framebuffer_unreference(c->primary->fb);
15357 c->primary->fb = NULL;
15358 c->primary->crtc = c->primary->state->crtc = NULL;
15359 update_state_fb(c->primary);
15360 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15361 }
15362 }
15363
15364 intel_backlight_register(dev);
15365}
15366
15367void intel_connector_unregister(struct intel_connector *intel_connector)
15368{
15369 struct drm_connector *connector = &intel_connector->base;
15370
15371 intel_panel_destroy_backlight(connector);
15372 drm_connector_unregister(connector);
15373}
15374
15375void intel_modeset_cleanup(struct drm_device *dev)
15376{
15377 struct drm_i915_private *dev_priv = dev->dev_private;
15378 struct drm_connector *connector;
15379
15380 intel_disable_gt_powersave(dev);
15381
15382 intel_backlight_unregister(dev);
15383
15384 /*
15385 * Interrupts and polling as the first thing to avoid creating havoc.
15386 * Too much stuff here (turning of connectors, ...) would
15387 * experience fancy races otherwise.
15388 */
15389 intel_irq_uninstall(dev_priv);
15390
15391 /*
15392 * Due to the hpd irq storm handling the hotplug work can re-arm the
15393 * poll handlers. Hence disable polling after hpd handling is shut down.
15394 */
15395 drm_kms_helper_poll_fini(dev);
15396
15397 intel_unregister_dsm_handler();
15398
15399 intel_fbc_disable(dev_priv);
15400
15401 /* flush any delayed tasks or pending work */
15402 flush_scheduled_work();
15403
15404 /* destroy the backlight and sysfs files before encoders/connectors */
15405 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15406 struct intel_connector *intel_connector;
15407
15408 intel_connector = to_intel_connector(connector);
15409 intel_connector->unregister(intel_connector);
15410 }
15411
15412 drm_mode_config_cleanup(dev);
15413
15414 intel_cleanup_overlay(dev);
15415
15416 mutex_lock(&dev->struct_mutex);
15417 intel_cleanup_gt_powersave(dev);
15418 mutex_unlock(&dev->struct_mutex);
15419}
15420
15421/*
15422 * Return which encoder is currently attached for connector.
15423 */
15424struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15425{
15426 return &intel_attached_encoder(connector)->base;
15427}
15428
15429void intel_connector_attach_encoder(struct intel_connector *connector,
15430 struct intel_encoder *encoder)
15431{
15432 connector->encoder = encoder;
15433 drm_mode_connector_attach_encoder(&connector->base,
15434 &encoder->base);
15435}
15436
15437/*
15438 * set vga decode state - true == enable VGA decode
15439 */
15440int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15441{
15442 struct drm_i915_private *dev_priv = dev->dev_private;
15443 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15444 u16 gmch_ctrl;
15445
15446 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15447 DRM_ERROR("failed to read control word\n");
15448 return -EIO;
15449 }
15450
15451 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15452 return 0;
15453
15454 if (state)
15455 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15456 else
15457 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15458
15459 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15460 DRM_ERROR("failed to write control word\n");
15461 return -EIO;
15462 }
15463
15464 return 0;
15465}
15466
15467struct intel_display_error_state {
15468
15469 u32 power_well_driver;
15470
15471 int num_transcoders;
15472
15473 struct intel_cursor_error_state {
15474 u32 control;
15475 u32 position;
15476 u32 base;
15477 u32 size;
15478 } cursor[I915_MAX_PIPES];
15479
15480 struct intel_pipe_error_state {
15481 bool power_domain_on;
15482 u32 source;
15483 u32 stat;
15484 } pipe[I915_MAX_PIPES];
15485
15486 struct intel_plane_error_state {
15487 u32 control;
15488 u32 stride;
15489 u32 size;
15490 u32 pos;
15491 u32 addr;
15492 u32 surface;
15493 u32 tile_offset;
15494 } plane[I915_MAX_PIPES];
15495
15496 struct intel_transcoder_error_state {
15497 bool power_domain_on;
15498 enum transcoder cpu_transcoder;
15499
15500 u32 conf;
15501
15502 u32 htotal;
15503 u32 hblank;
15504 u32 hsync;
15505 u32 vtotal;
15506 u32 vblank;
15507 u32 vsync;
15508 } transcoder[4];
15509};
15510
15511struct intel_display_error_state *
15512intel_display_capture_error_state(struct drm_device *dev)
15513{
15514 struct drm_i915_private *dev_priv = dev->dev_private;
15515 struct intel_display_error_state *error;
15516 int transcoders[] = {
15517 TRANSCODER_A,
15518 TRANSCODER_B,
15519 TRANSCODER_C,
15520 TRANSCODER_EDP,
15521 };
15522 int i;
15523
15524 if (INTEL_INFO(dev)->num_pipes == 0)
15525 return NULL;
15526
15527 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15528 if (error == NULL)
15529 return NULL;
15530
15531 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15532 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15533
15534 for_each_pipe(dev_priv, i) {
15535 error->pipe[i].power_domain_on =
15536 __intel_display_power_is_enabled(dev_priv,
15537 POWER_DOMAIN_PIPE(i));
15538 if (!error->pipe[i].power_domain_on)
15539 continue;
15540
15541 error->cursor[i].control = I915_READ(CURCNTR(i));
15542 error->cursor[i].position = I915_READ(CURPOS(i));
15543 error->cursor[i].base = I915_READ(CURBASE(i));
15544
15545 error->plane[i].control = I915_READ(DSPCNTR(i));
15546 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15547 if (INTEL_INFO(dev)->gen <= 3) {
15548 error->plane[i].size = I915_READ(DSPSIZE(i));
15549 error->plane[i].pos = I915_READ(DSPPOS(i));
15550 }
15551 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15552 error->plane[i].addr = I915_READ(DSPADDR(i));
15553 if (INTEL_INFO(dev)->gen >= 4) {
15554 error->plane[i].surface = I915_READ(DSPSURF(i));
15555 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15556 }
15557
15558 error->pipe[i].source = I915_READ(PIPESRC(i));
15559
15560 if (HAS_GMCH_DISPLAY(dev))
15561 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15562 }
15563
15564 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15565 if (HAS_DDI(dev_priv->dev))
15566 error->num_transcoders++; /* Account for eDP. */
15567
15568 for (i = 0; i < error->num_transcoders; i++) {
15569 enum transcoder cpu_transcoder = transcoders[i];
15570
15571 error->transcoder[i].power_domain_on =
15572 __intel_display_power_is_enabled(dev_priv,
15573 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15574 if (!error->transcoder[i].power_domain_on)
15575 continue;
15576
15577 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15578
15579 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15580 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15581 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15582 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15583 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15584 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15585 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15586 }
15587
15588 return error;
15589}
15590
15591#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15592
15593void
15594intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15595 struct drm_device *dev,
15596 struct intel_display_error_state *error)
15597{
15598 struct drm_i915_private *dev_priv = dev->dev_private;
15599 int i;
15600
15601 if (!error)
15602 return;
15603
15604 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15605 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15606 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15607 error->power_well_driver);
15608 for_each_pipe(dev_priv, i) {
15609 err_printf(m, "Pipe [%d]:\n", i);
15610 err_printf(m, " Power: %s\n",
15611 error->pipe[i].power_domain_on ? "on" : "off");
15612 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15613 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15614
15615 err_printf(m, "Plane [%d]:\n", i);
15616 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15617 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15618 if (INTEL_INFO(dev)->gen <= 3) {
15619 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15620 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15621 }
15622 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15623 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15624 if (INTEL_INFO(dev)->gen >= 4) {
15625 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15626 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15627 }
15628
15629 err_printf(m, "Cursor [%d]:\n", i);
15630 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15631 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15632 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15633 }
15634
15635 for (i = 0; i < error->num_transcoders; i++) {
15636 err_printf(m, "CPU transcoder: %c\n",
15637 transcoder_name(error->transcoder[i].cpu_transcoder));
15638 err_printf(m, " Power: %s\n",
15639 error->transcoder[i].power_domain_on ? "on" : "off");
15640 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15641 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15642 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15643 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15644 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15645 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15646 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15647 }
15648}
15649
15650void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15651{
15652 struct intel_crtc *crtc;
15653
15654 for_each_intel_crtc(dev, crtc) {
15655 struct intel_unpin_work *work;
15656
15657 spin_lock_irq(&dev->event_lock);
15658
15659 work = crtc->unpin_work;
15660
15661 if (work && work->event &&
15662 work->event->base.file_priv == file) {
15663 kfree(work->event);
15664 work->event = NULL;
15665 }
15666
15667 spin_unlock_irq(&dev->event_lock);
15668 }
15669}
Linux kernel - Deliverables
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