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drm/i915: Remove use of gtt_mappable_entries
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
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1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
29#include <linux/slab.h>
30#include <linux/export.h>
31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
35#include "intel_drv.h"
36#include <drm/i915_drm.h>
37#include "i915_drv.h"
38
39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
41/**
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
44 *
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
47 */
48static bool is_edp(struct intel_dp *intel_dp)
49{
50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
51
52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
53}
54
55/**
56 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
57 * @intel_dp: DP struct
58 *
59 * Returns true if the given DP struct corresponds to a PCH DP port attached
60 * to an eDP panel, false otherwise. Helpful for determining whether we
61 * may need FDI resources for a given DP output or not.
62 */
63static bool is_pch_edp(struct intel_dp *intel_dp)
64{
65 return intel_dp->is_pch_edp;
66}
67
68/**
69 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
70 * @intel_dp: DP struct
71 *
72 * Returns true if the given DP struct corresponds to a CPU eDP port.
73 */
74static bool is_cpu_edp(struct intel_dp *intel_dp)
75{
76 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
77}
78
79static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
80{
81 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
82
83 return intel_dig_port->base.base.dev;
84}
85
86static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
87{
88 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
89}
90
91/**
92 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
93 * @encoder: DRM encoder
94 *
95 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
96 * by intel_display.c.
97 */
98bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
99{
100 struct intel_dp *intel_dp;
101
102 if (!encoder)
103 return false;
104
105 intel_dp = enc_to_intel_dp(encoder);
106
107 return is_pch_edp(intel_dp);
108}
109
110static void intel_dp_link_down(struct intel_dp *intel_dp);
111
112void
113intel_edp_link_config(struct intel_encoder *intel_encoder,
114 int *lane_num, int *link_bw)
115{
116 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
117
118 *lane_num = intel_dp->lane_count;
119 *link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
120}
121
122int
123intel_edp_target_clock(struct intel_encoder *intel_encoder,
124 struct drm_display_mode *mode)
125{
126 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
127 struct intel_connector *intel_connector = intel_dp->attached_connector;
128
129 if (intel_connector->panel.fixed_mode)
130 return intel_connector->panel.fixed_mode->clock;
131 else
132 return mode->clock;
133}
134
135static int
136intel_dp_max_link_bw(struct intel_dp *intel_dp)
137{
138 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
139
140 switch (max_link_bw) {
141 case DP_LINK_BW_1_62:
142 case DP_LINK_BW_2_7:
143 break;
144 default:
145 max_link_bw = DP_LINK_BW_1_62;
146 break;
147 }
148 return max_link_bw;
149}
150
151/*
152 * The units on the numbers in the next two are... bizarre. Examples will
153 * make it clearer; this one parallels an example in the eDP spec.
154 *
155 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
156 *
157 * 270000 * 1 * 8 / 10 == 216000
158 *
159 * The actual data capacity of that configuration is 2.16Gbit/s, so the
160 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
161 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
162 * 119000. At 18bpp that's 2142000 kilobits per second.
163 *
164 * Thus the strange-looking division by 10 in intel_dp_link_required, to
165 * get the result in decakilobits instead of kilobits.
166 */
167
168static int
169intel_dp_link_required(int pixel_clock, int bpp)
170{
171 return (pixel_clock * bpp + 9) / 10;
172}
173
174static int
175intel_dp_max_data_rate(int max_link_clock, int max_lanes)
176{
177 return (max_link_clock * max_lanes * 8) / 10;
178}
179
180static bool
181intel_dp_adjust_dithering(struct intel_dp *intel_dp,
182 struct drm_display_mode *mode,
183 bool adjust_mode)
184{
185 int max_link_clock =
186 drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
187 int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
188 int max_rate, mode_rate;
189
190 mode_rate = intel_dp_link_required(mode->clock, 24);
191 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
192
193 if (mode_rate > max_rate) {
194 mode_rate = intel_dp_link_required(mode->clock, 18);
195 if (mode_rate > max_rate)
196 return false;
197
198 if (adjust_mode)
199 mode->private_flags
200 |= INTEL_MODE_DP_FORCE_6BPC;
201
202 return true;
203 }
204
205 return true;
206}
207
208static int
209intel_dp_mode_valid(struct drm_connector *connector,
210 struct drm_display_mode *mode)
211{
212 struct intel_dp *intel_dp = intel_attached_dp(connector);
213 struct intel_connector *intel_connector = to_intel_connector(connector);
214 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
215
216 if (is_edp(intel_dp) && fixed_mode) {
217 if (mode->hdisplay > fixed_mode->hdisplay)
218 return MODE_PANEL;
219
220 if (mode->vdisplay > fixed_mode->vdisplay)
221 return MODE_PANEL;
222 }
223
224 if (!intel_dp_adjust_dithering(intel_dp, mode, false))
225 return MODE_CLOCK_HIGH;
226
227 if (mode->clock < 10000)
228 return MODE_CLOCK_LOW;
229
230 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
231 return MODE_H_ILLEGAL;
232
233 return MODE_OK;
234}
235
236static uint32_t
237pack_aux(uint8_t *src, int src_bytes)
238{
239 int i;
240 uint32_t v = 0;
241
242 if (src_bytes > 4)
243 src_bytes = 4;
244 for (i = 0; i < src_bytes; i++)
245 v |= ((uint32_t) src[i]) << ((3-i) * 8);
246 return v;
247}
248
249static void
250unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
251{
252 int i;
253 if (dst_bytes > 4)
254 dst_bytes = 4;
255 for (i = 0; i < dst_bytes; i++)
256 dst[i] = src >> ((3-i) * 8);
257}
258
259/* hrawclock is 1/4 the FSB frequency */
260static int
261intel_hrawclk(struct drm_device *dev)
262{
263 struct drm_i915_private *dev_priv = dev->dev_private;
264 uint32_t clkcfg;
265
266 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
267 if (IS_VALLEYVIEW(dev))
268 return 200;
269
270 clkcfg = I915_READ(CLKCFG);
271 switch (clkcfg & CLKCFG_FSB_MASK) {
272 case CLKCFG_FSB_400:
273 return 100;
274 case CLKCFG_FSB_533:
275 return 133;
276 case CLKCFG_FSB_667:
277 return 166;
278 case CLKCFG_FSB_800:
279 return 200;
280 case CLKCFG_FSB_1067:
281 return 266;
282 case CLKCFG_FSB_1333:
283 return 333;
284 /* these two are just a guess; one of them might be right */
285 case CLKCFG_FSB_1600:
286 case CLKCFG_FSB_1600_ALT:
287 return 400;
288 default:
289 return 133;
290 }
291}
292
293static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
294{
295 struct drm_device *dev = intel_dp_to_dev(intel_dp);
296 struct drm_i915_private *dev_priv = dev->dev_private;
297
298 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
299}
300
301static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
302{
303 struct drm_device *dev = intel_dp_to_dev(intel_dp);
304 struct drm_i915_private *dev_priv = dev->dev_private;
305
306 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
307}
308
309static void
310intel_dp_check_edp(struct intel_dp *intel_dp)
311{
312 struct drm_device *dev = intel_dp_to_dev(intel_dp);
313 struct drm_i915_private *dev_priv = dev->dev_private;
314
315 if (!is_edp(intel_dp))
316 return;
317 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
318 WARN(1, "eDP powered off while attempting aux channel communication.\n");
319 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
320 I915_READ(PCH_PP_STATUS),
321 I915_READ(PCH_PP_CONTROL));
322 }
323}
324
325static uint32_t
326intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
327{
328 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
329 struct drm_device *dev = intel_dig_port->base.base.dev;
330 struct drm_i915_private *dev_priv = dev->dev_private;
331 uint32_t ch_ctl = intel_dp->output_reg + 0x10;
332 uint32_t status;
333 bool done;
334
335 if (IS_HASWELL(dev)) {
336 switch (intel_dig_port->port) {
337 case PORT_A:
338 ch_ctl = DPA_AUX_CH_CTL;
339 break;
340 case PORT_B:
341 ch_ctl = PCH_DPB_AUX_CH_CTL;
342 break;
343 case PORT_C:
344 ch_ctl = PCH_DPC_AUX_CH_CTL;
345 break;
346 case PORT_D:
347 ch_ctl = PCH_DPD_AUX_CH_CTL;
348 break;
349 default:
350 BUG();
351 }
352 }
353
354#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
355 if (has_aux_irq)
356 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 10);
357 else
358 done = wait_for_atomic(C, 10) == 0;
359 if (!done)
360 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
361 has_aux_irq);
362#undef C
363
364 return status;
365}
366
367static int
368intel_dp_aux_ch(struct intel_dp *intel_dp,
369 uint8_t *send, int send_bytes,
370 uint8_t *recv, int recv_size)
371{
372 uint32_t output_reg = intel_dp->output_reg;
373 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
374 struct drm_device *dev = intel_dig_port->base.base.dev;
375 struct drm_i915_private *dev_priv = dev->dev_private;
376 uint32_t ch_ctl = output_reg + 0x10;
377 uint32_t ch_data = ch_ctl + 4;
378 int i, ret, recv_bytes;
379 uint32_t status;
380 uint32_t aux_clock_divider;
381 int try, precharge;
382 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
383
384 /* dp aux is extremely sensitive to irq latency, hence request the
385 * lowest possible wakeup latency and so prevent the cpu from going into
386 * deep sleep states.
387 */
388 pm_qos_update_request(&dev_priv->pm_qos, 0);
389
390 if (IS_HASWELL(dev)) {
391 switch (intel_dig_port->port) {
392 case PORT_A:
393 ch_ctl = DPA_AUX_CH_CTL;
394 ch_data = DPA_AUX_CH_DATA1;
395 break;
396 case PORT_B:
397 ch_ctl = PCH_DPB_AUX_CH_CTL;
398 ch_data = PCH_DPB_AUX_CH_DATA1;
399 break;
400 case PORT_C:
401 ch_ctl = PCH_DPC_AUX_CH_CTL;
402 ch_data = PCH_DPC_AUX_CH_DATA1;
403 break;
404 case PORT_D:
405 ch_ctl = PCH_DPD_AUX_CH_CTL;
406 ch_data = PCH_DPD_AUX_CH_DATA1;
407 break;
408 default:
409 BUG();
410 }
411 }
412
413 intel_dp_check_edp(intel_dp);
414 /* The clock divider is based off the hrawclk,
415 * and would like to run at 2MHz. So, take the
416 * hrawclk value and divide by 2 and use that
417 *
418 * Note that PCH attached eDP panels should use a 125MHz input
419 * clock divider.
420 */
421 if (is_cpu_edp(intel_dp)) {
422 if (HAS_DDI(dev))
423 aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
424 else if (IS_VALLEYVIEW(dev))
425 aux_clock_divider = 100;
426 else if (IS_GEN6(dev) || IS_GEN7(dev))
427 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
428 else
429 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
430 } else if (HAS_PCH_SPLIT(dev))
431 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
432 else
433 aux_clock_divider = intel_hrawclk(dev) / 2;
434
435 if (IS_GEN6(dev))
436 precharge = 3;
437 else
438 precharge = 5;
439
440 /* Try to wait for any previous AUX channel activity */
441 for (try = 0; try < 3; try++) {
442 status = I915_READ_NOTRACE(ch_ctl);
443 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
444 break;
445 msleep(1);
446 }
447
448 if (try == 3) {
449 WARN(1, "dp_aux_ch not started status 0x%08x\n",
450 I915_READ(ch_ctl));
451 ret = -EBUSY;
452 goto out;
453 }
454
455 /* Must try at least 3 times according to DP spec */
456 for (try = 0; try < 5; try++) {
457 /* Load the send data into the aux channel data registers */
458 for (i = 0; i < send_bytes; i += 4)
459 I915_WRITE(ch_data + i,
460 pack_aux(send + i, send_bytes - i));
461
462 /* Send the command and wait for it to complete */
463 I915_WRITE(ch_ctl,
464 DP_AUX_CH_CTL_SEND_BUSY |
465 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
466 DP_AUX_CH_CTL_TIME_OUT_400us |
467 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
468 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
469 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
470 DP_AUX_CH_CTL_DONE |
471 DP_AUX_CH_CTL_TIME_OUT_ERROR |
472 DP_AUX_CH_CTL_RECEIVE_ERROR);
473
474 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
475
476 /* Clear done status and any errors */
477 I915_WRITE(ch_ctl,
478 status |
479 DP_AUX_CH_CTL_DONE |
480 DP_AUX_CH_CTL_TIME_OUT_ERROR |
481 DP_AUX_CH_CTL_RECEIVE_ERROR);
482
483 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
484 DP_AUX_CH_CTL_RECEIVE_ERROR))
485 continue;
486 if (status & DP_AUX_CH_CTL_DONE)
487 break;
488 }
489
490 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
491 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
492 ret = -EBUSY;
493 goto out;
494 }
495
496 /* Check for timeout or receive error.
497 * Timeouts occur when the sink is not connected
498 */
499 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
500 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
501 ret = -EIO;
502 goto out;
503 }
504
505 /* Timeouts occur when the device isn't connected, so they're
506 * "normal" -- don't fill the kernel log with these */
507 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
508 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
509 ret = -ETIMEDOUT;
510 goto out;
511 }
512
513 /* Unload any bytes sent back from the other side */
514 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
515 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
516 if (recv_bytes > recv_size)
517 recv_bytes = recv_size;
518
519 for (i = 0; i < recv_bytes; i += 4)
520 unpack_aux(I915_READ(ch_data + i),
521 recv + i, recv_bytes - i);
522
523 ret = recv_bytes;
524out:
525 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
526
527 return ret;
528}
529
530/* Write data to the aux channel in native mode */
531static int
532intel_dp_aux_native_write(struct intel_dp *intel_dp,
533 uint16_t address, uint8_t *send, int send_bytes)
534{
535 int ret;
536 uint8_t msg[20];
537 int msg_bytes;
538 uint8_t ack;
539
540 intel_dp_check_edp(intel_dp);
541 if (send_bytes > 16)
542 return -1;
543 msg[0] = AUX_NATIVE_WRITE << 4;
544 msg[1] = address >> 8;
545 msg[2] = address & 0xff;
546 msg[3] = send_bytes - 1;
547 memcpy(&msg[4], send, send_bytes);
548 msg_bytes = send_bytes + 4;
549 for (;;) {
550 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
551 if (ret < 0)
552 return ret;
553 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
554 break;
555 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
556 udelay(100);
557 else
558 return -EIO;
559 }
560 return send_bytes;
561}
562
563/* Write a single byte to the aux channel in native mode */
564static int
565intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
566 uint16_t address, uint8_t byte)
567{
568 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
569}
570
571/* read bytes from a native aux channel */
572static int
573intel_dp_aux_native_read(struct intel_dp *intel_dp,
574 uint16_t address, uint8_t *recv, int recv_bytes)
575{
576 uint8_t msg[4];
577 int msg_bytes;
578 uint8_t reply[20];
579 int reply_bytes;
580 uint8_t ack;
581 int ret;
582
583 intel_dp_check_edp(intel_dp);
584 msg[0] = AUX_NATIVE_READ << 4;
585 msg[1] = address >> 8;
586 msg[2] = address & 0xff;
587 msg[3] = recv_bytes - 1;
588
589 msg_bytes = 4;
590 reply_bytes = recv_bytes + 1;
591
592 for (;;) {
593 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
594 reply, reply_bytes);
595 if (ret == 0)
596 return -EPROTO;
597 if (ret < 0)
598 return ret;
599 ack = reply[0];
600 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
601 memcpy(recv, reply + 1, ret - 1);
602 return ret - 1;
603 }
604 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
605 udelay(100);
606 else
607 return -EIO;
608 }
609}
610
611static int
612intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
613 uint8_t write_byte, uint8_t *read_byte)
614{
615 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
616 struct intel_dp *intel_dp = container_of(adapter,
617 struct intel_dp,
618 adapter);
619 uint16_t address = algo_data->address;
620 uint8_t msg[5];
621 uint8_t reply[2];
622 unsigned retry;
623 int msg_bytes;
624 int reply_bytes;
625 int ret;
626
627 intel_dp_check_edp(intel_dp);
628 /* Set up the command byte */
629 if (mode & MODE_I2C_READ)
630 msg[0] = AUX_I2C_READ << 4;
631 else
632 msg[0] = AUX_I2C_WRITE << 4;
633
634 if (!(mode & MODE_I2C_STOP))
635 msg[0] |= AUX_I2C_MOT << 4;
636
637 msg[1] = address >> 8;
638 msg[2] = address;
639
640 switch (mode) {
641 case MODE_I2C_WRITE:
642 msg[3] = 0;
643 msg[4] = write_byte;
644 msg_bytes = 5;
645 reply_bytes = 1;
646 break;
647 case MODE_I2C_READ:
648 msg[3] = 0;
649 msg_bytes = 4;
650 reply_bytes = 2;
651 break;
652 default:
653 msg_bytes = 3;
654 reply_bytes = 1;
655 break;
656 }
657
658 for (retry = 0; retry < 5; retry++) {
659 ret = intel_dp_aux_ch(intel_dp,
660 msg, msg_bytes,
661 reply, reply_bytes);
662 if (ret < 0) {
663 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
664 return ret;
665 }
666
667 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
668 case AUX_NATIVE_REPLY_ACK:
669 /* I2C-over-AUX Reply field is only valid
670 * when paired with AUX ACK.
671 */
672 break;
673 case AUX_NATIVE_REPLY_NACK:
674 DRM_DEBUG_KMS("aux_ch native nack\n");
675 return -EREMOTEIO;
676 case AUX_NATIVE_REPLY_DEFER:
677 udelay(100);
678 continue;
679 default:
680 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
681 reply[0]);
682 return -EREMOTEIO;
683 }
684
685 switch (reply[0] & AUX_I2C_REPLY_MASK) {
686 case AUX_I2C_REPLY_ACK:
687 if (mode == MODE_I2C_READ) {
688 *read_byte = reply[1];
689 }
690 return reply_bytes - 1;
691 case AUX_I2C_REPLY_NACK:
692 DRM_DEBUG_KMS("aux_i2c nack\n");
693 return -EREMOTEIO;
694 case AUX_I2C_REPLY_DEFER:
695 DRM_DEBUG_KMS("aux_i2c defer\n");
696 udelay(100);
697 break;
698 default:
699 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
700 return -EREMOTEIO;
701 }
702 }
703
704 DRM_ERROR("too many retries, giving up\n");
705 return -EREMOTEIO;
706}
707
708static int
709intel_dp_i2c_init(struct intel_dp *intel_dp,
710 struct intel_connector *intel_connector, const char *name)
711{
712 int ret;
713
714 DRM_DEBUG_KMS("i2c_init %s\n", name);
715 intel_dp->algo.running = false;
716 intel_dp->algo.address = 0;
717 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
718
719 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
720 intel_dp->adapter.owner = THIS_MODULE;
721 intel_dp->adapter.class = I2C_CLASS_DDC;
722 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
723 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
724 intel_dp->adapter.algo_data = &intel_dp->algo;
725 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
726
727 ironlake_edp_panel_vdd_on(intel_dp);
728 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
729 ironlake_edp_panel_vdd_off(intel_dp, false);
730 return ret;
731}
732
733bool
734intel_dp_mode_fixup(struct drm_encoder *encoder,
735 const struct drm_display_mode *mode,
736 struct drm_display_mode *adjusted_mode)
737{
738 struct drm_device *dev = encoder->dev;
739 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
740 struct intel_connector *intel_connector = intel_dp->attached_connector;
741 int lane_count, clock;
742 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
743 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
744 int bpp, mode_rate;
745 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
746
747 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
748 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
749 adjusted_mode);
750 intel_pch_panel_fitting(dev,
751 intel_connector->panel.fitting_mode,
752 mode, adjusted_mode);
753 }
754
755 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
756 return false;
757
758 DRM_DEBUG_KMS("DP link computation with max lane count %i "
759 "max bw %02x pixel clock %iKHz\n",
760 max_lane_count, bws[max_clock], adjusted_mode->clock);
761
762 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
763 return false;
764
765 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
766 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
767
768 for (clock = 0; clock <= max_clock; clock++) {
769 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
770 int link_bw_clock =
771 drm_dp_bw_code_to_link_rate(bws[clock]);
772 int link_avail = intel_dp_max_data_rate(link_bw_clock,
773 lane_count);
774
775 if (mode_rate <= link_avail) {
776 intel_dp->link_bw = bws[clock];
777 intel_dp->lane_count = lane_count;
778 adjusted_mode->clock = link_bw_clock;
779 DRM_DEBUG_KMS("DP link bw %02x lane "
780 "count %d clock %d bpp %d\n",
781 intel_dp->link_bw, intel_dp->lane_count,
782 adjusted_mode->clock, bpp);
783 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
784 mode_rate, link_avail);
785 return true;
786 }
787 }
788 }
789
790 return false;
791}
792
793void
794intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
795 struct drm_display_mode *adjusted_mode)
796{
797 struct drm_device *dev = crtc->dev;
798 struct intel_encoder *intel_encoder;
799 struct intel_dp *intel_dp;
800 struct drm_i915_private *dev_priv = dev->dev_private;
801 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
802 int lane_count = 4;
803 struct intel_link_m_n m_n;
804 int pipe = intel_crtc->pipe;
805 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
806
807 /*
808 * Find the lane count in the intel_encoder private
809 */
810 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
811 intel_dp = enc_to_intel_dp(&intel_encoder->base);
812
813 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
814 intel_encoder->type == INTEL_OUTPUT_EDP)
815 {
816 lane_count = intel_dp->lane_count;
817 break;
818 }
819 }
820
821 /*
822 * Compute the GMCH and Link ratios. The '3' here is
823 * the number of bytes_per_pixel post-LUT, which we always
824 * set up for 8-bits of R/G/B, or 3 bytes total.
825 */
826 intel_link_compute_m_n(intel_crtc->bpp, lane_count,
827 mode->clock, adjusted_mode->clock, &m_n);
828
829 if (IS_HASWELL(dev)) {
830 I915_WRITE(PIPE_DATA_M1(cpu_transcoder),
831 TU_SIZE(m_n.tu) | m_n.gmch_m);
832 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
833 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
834 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
835 } else if (HAS_PCH_SPLIT(dev)) {
836 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
837 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
838 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
839 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
840 } else if (IS_VALLEYVIEW(dev)) {
841 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
842 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
843 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
844 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
845 } else {
846 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
847 TU_SIZE(m_n.tu) | m_n.gmch_m);
848 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
849 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
850 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
851 }
852}
853
854void intel_dp_init_link_config(struct intel_dp *intel_dp)
855{
856 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
857 intel_dp->link_configuration[0] = intel_dp->link_bw;
858 intel_dp->link_configuration[1] = intel_dp->lane_count;
859 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
860 /*
861 * Check for DPCD version > 1.1 and enhanced framing support
862 */
863 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
864 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
865 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
866 }
867}
868
869static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
870{
871 struct drm_device *dev = crtc->dev;
872 struct drm_i915_private *dev_priv = dev->dev_private;
873 u32 dpa_ctl;
874
875 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
876 dpa_ctl = I915_READ(DP_A);
877 dpa_ctl &= ~DP_PLL_FREQ_MASK;
878
879 if (clock < 200000) {
880 /* For a long time we've carried around a ILK-DevA w/a for the
881 * 160MHz clock. If we're really unlucky, it's still required.
882 */
883 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
884 dpa_ctl |= DP_PLL_FREQ_160MHZ;
885 } else {
886 dpa_ctl |= DP_PLL_FREQ_270MHZ;
887 }
888
889 I915_WRITE(DP_A, dpa_ctl);
890
891 POSTING_READ(DP_A);
892 udelay(500);
893}
894
895static void
896intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
897 struct drm_display_mode *adjusted_mode)
898{
899 struct drm_device *dev = encoder->dev;
900 struct drm_i915_private *dev_priv = dev->dev_private;
901 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
902 struct drm_crtc *crtc = encoder->crtc;
903 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
904
905 /*
906 * There are four kinds of DP registers:
907 *
908 * IBX PCH
909 * SNB CPU
910 * IVB CPU
911 * CPT PCH
912 *
913 * IBX PCH and CPU are the same for almost everything,
914 * except that the CPU DP PLL is configured in this
915 * register
916 *
917 * CPT PCH is quite different, having many bits moved
918 * to the TRANS_DP_CTL register instead. That
919 * configuration happens (oddly) in ironlake_pch_enable
920 */
921
922 /* Preserve the BIOS-computed detected bit. This is
923 * supposed to be read-only.
924 */
925 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
926
927 /* Handle DP bits in common between all three register formats */
928 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
929
930 switch (intel_dp->lane_count) {
931 case 1:
932 intel_dp->DP |= DP_PORT_WIDTH_1;
933 break;
934 case 2:
935 intel_dp->DP |= DP_PORT_WIDTH_2;
936 break;
937 case 4:
938 intel_dp->DP |= DP_PORT_WIDTH_4;
939 break;
940 }
941 if (intel_dp->has_audio) {
942 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
943 pipe_name(intel_crtc->pipe));
944 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
945 intel_write_eld(encoder, adjusted_mode);
946 }
947
948 intel_dp_init_link_config(intel_dp);
949
950 /* Split out the IBX/CPU vs CPT settings */
951
952 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
953 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
954 intel_dp->DP |= DP_SYNC_HS_HIGH;
955 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
956 intel_dp->DP |= DP_SYNC_VS_HIGH;
957 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
958
959 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
960 intel_dp->DP |= DP_ENHANCED_FRAMING;
961
962 intel_dp->DP |= intel_crtc->pipe << 29;
963
964 /* don't miss out required setting for eDP */
965 if (adjusted_mode->clock < 200000)
966 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
967 else
968 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
969 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
970 intel_dp->DP |= intel_dp->color_range;
971
972 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
973 intel_dp->DP |= DP_SYNC_HS_HIGH;
974 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
975 intel_dp->DP |= DP_SYNC_VS_HIGH;
976 intel_dp->DP |= DP_LINK_TRAIN_OFF;
977
978 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
979 intel_dp->DP |= DP_ENHANCED_FRAMING;
980
981 if (intel_crtc->pipe == 1)
982 intel_dp->DP |= DP_PIPEB_SELECT;
983
984 if (is_cpu_edp(intel_dp)) {
985 /* don't miss out required setting for eDP */
986 if (adjusted_mode->clock < 200000)
987 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
988 else
989 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
990 }
991 } else {
992 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
993 }
994
995 if (is_cpu_edp(intel_dp))
996 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
997}
998
999#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1000#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1001
1002#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1003#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1004
1005#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1006#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1007
1008static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
1009 u32 mask,
1010 u32 value)
1011{
1012 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1013 struct drm_i915_private *dev_priv = dev->dev_private;
1014
1015 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1016 mask, value,
1017 I915_READ(PCH_PP_STATUS),
1018 I915_READ(PCH_PP_CONTROL));
1019
1020 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
1021 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1022 I915_READ(PCH_PP_STATUS),
1023 I915_READ(PCH_PP_CONTROL));
1024 }
1025}
1026
1027static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
1028{
1029 DRM_DEBUG_KMS("Wait for panel power on\n");
1030 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1031}
1032
1033static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1034{
1035 DRM_DEBUG_KMS("Wait for panel power off time\n");
1036 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1037}
1038
1039static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1040{
1041 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1042 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1043}
1044
1045
1046/* Read the current pp_control value, unlocking the register if it
1047 * is locked
1048 */
1049
1050static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
1051{
1052 u32 control = I915_READ(PCH_PP_CONTROL);
1053
1054 control &= ~PANEL_UNLOCK_MASK;
1055 control |= PANEL_UNLOCK_REGS;
1056 return control;
1057}
1058
1059void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1060{
1061 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1062 struct drm_i915_private *dev_priv = dev->dev_private;
1063 u32 pp;
1064
1065 if (!is_edp(intel_dp))
1066 return;
1067 DRM_DEBUG_KMS("Turn eDP VDD on\n");
1068
1069 WARN(intel_dp->want_panel_vdd,
1070 "eDP VDD already requested on\n");
1071
1072 intel_dp->want_panel_vdd = true;
1073
1074 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1075 DRM_DEBUG_KMS("eDP VDD already on\n");
1076 return;
1077 }
1078
1079 if (!ironlake_edp_have_panel_power(intel_dp))
1080 ironlake_wait_panel_power_cycle(intel_dp);
1081
1082 pp = ironlake_get_pp_control(dev_priv);
1083 pp |= EDP_FORCE_VDD;
1084 I915_WRITE(PCH_PP_CONTROL, pp);
1085 POSTING_READ(PCH_PP_CONTROL);
1086 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1087 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1088
1089 /*
1090 * If the panel wasn't on, delay before accessing aux channel
1091 */
1092 if (!ironlake_edp_have_panel_power(intel_dp)) {
1093 DRM_DEBUG_KMS("eDP was not running\n");
1094 msleep(intel_dp->panel_power_up_delay);
1095 }
1096}
1097
1098static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1099{
1100 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1101 struct drm_i915_private *dev_priv = dev->dev_private;
1102 u32 pp;
1103
1104 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1105 pp = ironlake_get_pp_control(dev_priv);
1106 pp &= ~EDP_FORCE_VDD;
1107 I915_WRITE(PCH_PP_CONTROL, pp);
1108 POSTING_READ(PCH_PP_CONTROL);
1109
1110 /* Make sure sequencer is idle before allowing subsequent activity */
1111 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1112 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1113
1114 msleep(intel_dp->panel_power_down_delay);
1115 }
1116}
1117
1118static void ironlake_panel_vdd_work(struct work_struct *__work)
1119{
1120 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1121 struct intel_dp, panel_vdd_work);
1122 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1123
1124 mutex_lock(&dev->mode_config.mutex);
1125 ironlake_panel_vdd_off_sync(intel_dp);
1126 mutex_unlock(&dev->mode_config.mutex);
1127}
1128
1129void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1130{
1131 if (!is_edp(intel_dp))
1132 return;
1133
1134 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1135 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1136
1137 intel_dp->want_panel_vdd = false;
1138
1139 if (sync) {
1140 ironlake_panel_vdd_off_sync(intel_dp);
1141 } else {
1142 /*
1143 * Queue the timer to fire a long
1144 * time from now (relative to the power down delay)
1145 * to keep the panel power up across a sequence of operations
1146 */
1147 schedule_delayed_work(&intel_dp->panel_vdd_work,
1148 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1149 }
1150}
1151
1152void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1153{
1154 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1155 struct drm_i915_private *dev_priv = dev->dev_private;
1156 u32 pp;
1157
1158 if (!is_edp(intel_dp))
1159 return;
1160
1161 DRM_DEBUG_KMS("Turn eDP power on\n");
1162
1163 if (ironlake_edp_have_panel_power(intel_dp)) {
1164 DRM_DEBUG_KMS("eDP power already on\n");
1165 return;
1166 }
1167
1168 ironlake_wait_panel_power_cycle(intel_dp);
1169
1170 pp = ironlake_get_pp_control(dev_priv);
1171 if (IS_GEN5(dev)) {
1172 /* ILK workaround: disable reset around power sequence */
1173 pp &= ~PANEL_POWER_RESET;
1174 I915_WRITE(PCH_PP_CONTROL, pp);
1175 POSTING_READ(PCH_PP_CONTROL);
1176 }
1177
1178 pp |= POWER_TARGET_ON;
1179 if (!IS_GEN5(dev))
1180 pp |= PANEL_POWER_RESET;
1181
1182 I915_WRITE(PCH_PP_CONTROL, pp);
1183 POSTING_READ(PCH_PP_CONTROL);
1184
1185 ironlake_wait_panel_on(intel_dp);
1186
1187 if (IS_GEN5(dev)) {
1188 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1189 I915_WRITE(PCH_PP_CONTROL, pp);
1190 POSTING_READ(PCH_PP_CONTROL);
1191 }
1192}
1193
1194void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1195{
1196 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1197 struct drm_i915_private *dev_priv = dev->dev_private;
1198 u32 pp;
1199
1200 if (!is_edp(intel_dp))
1201 return;
1202
1203 DRM_DEBUG_KMS("Turn eDP power off\n");
1204
1205 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1206
1207 pp = ironlake_get_pp_control(dev_priv);
1208 /* We need to switch off panel power _and_ force vdd, for otherwise some
1209 * panels get very unhappy and cease to work. */
1210 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1211 I915_WRITE(PCH_PP_CONTROL, pp);
1212 POSTING_READ(PCH_PP_CONTROL);
1213
1214 intel_dp->want_panel_vdd = false;
1215
1216 ironlake_wait_panel_off(intel_dp);
1217}
1218
1219void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1220{
1221 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1222 struct drm_device *dev = intel_dig_port->base.base.dev;
1223 struct drm_i915_private *dev_priv = dev->dev_private;
1224 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1225 u32 pp;
1226
1227 if (!is_edp(intel_dp))
1228 return;
1229
1230 DRM_DEBUG_KMS("\n");
1231 /*
1232 * If we enable the backlight right away following a panel power
1233 * on, we may see slight flicker as the panel syncs with the eDP
1234 * link. So delay a bit to make sure the image is solid before
1235 * allowing it to appear.
1236 */
1237 msleep(intel_dp->backlight_on_delay);
1238 pp = ironlake_get_pp_control(dev_priv);
1239 pp |= EDP_BLC_ENABLE;
1240 I915_WRITE(PCH_PP_CONTROL, pp);
1241 POSTING_READ(PCH_PP_CONTROL);
1242
1243 intel_panel_enable_backlight(dev, pipe);
1244}
1245
1246void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1247{
1248 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1249 struct drm_i915_private *dev_priv = dev->dev_private;
1250 u32 pp;
1251
1252 if (!is_edp(intel_dp))
1253 return;
1254
1255 intel_panel_disable_backlight(dev);
1256
1257 DRM_DEBUG_KMS("\n");
1258 pp = ironlake_get_pp_control(dev_priv);
1259 pp &= ~EDP_BLC_ENABLE;
1260 I915_WRITE(PCH_PP_CONTROL, pp);
1261 POSTING_READ(PCH_PP_CONTROL);
1262 msleep(intel_dp->backlight_off_delay);
1263}
1264
1265static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1266{
1267 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1268 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1269 struct drm_device *dev = crtc->dev;
1270 struct drm_i915_private *dev_priv = dev->dev_private;
1271 u32 dpa_ctl;
1272
1273 assert_pipe_disabled(dev_priv,
1274 to_intel_crtc(crtc)->pipe);
1275
1276 DRM_DEBUG_KMS("\n");
1277 dpa_ctl = I915_READ(DP_A);
1278 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1279 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1280
1281 /* We don't adjust intel_dp->DP while tearing down the link, to
1282 * facilitate link retraining (e.g. after hotplug). Hence clear all
1283 * enable bits here to ensure that we don't enable too much. */
1284 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1285 intel_dp->DP |= DP_PLL_ENABLE;
1286 I915_WRITE(DP_A, intel_dp->DP);
1287 POSTING_READ(DP_A);
1288 udelay(200);
1289}
1290
1291static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1292{
1293 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1294 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1295 struct drm_device *dev = crtc->dev;
1296 struct drm_i915_private *dev_priv = dev->dev_private;
1297 u32 dpa_ctl;
1298
1299 assert_pipe_disabled(dev_priv,
1300 to_intel_crtc(crtc)->pipe);
1301
1302 dpa_ctl = I915_READ(DP_A);
1303 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1304 "dp pll off, should be on\n");
1305 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1306
1307 /* We can't rely on the value tracked for the DP register in
1308 * intel_dp->DP because link_down must not change that (otherwise link
1309 * re-training will fail. */
1310 dpa_ctl &= ~DP_PLL_ENABLE;
1311 I915_WRITE(DP_A, dpa_ctl);
1312 POSTING_READ(DP_A);
1313 udelay(200);
1314}
1315
1316/* If the sink supports it, try to set the power state appropriately */
1317void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1318{
1319 int ret, i;
1320
1321 /* Should have a valid DPCD by this point */
1322 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1323 return;
1324
1325 if (mode != DRM_MODE_DPMS_ON) {
1326 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1327 DP_SET_POWER_D3);
1328 if (ret != 1)
1329 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1330 } else {
1331 /*
1332 * When turning on, we need to retry for 1ms to give the sink
1333 * time to wake up.
1334 */
1335 for (i = 0; i < 3; i++) {
1336 ret = intel_dp_aux_native_write_1(intel_dp,
1337 DP_SET_POWER,
1338 DP_SET_POWER_D0);
1339 if (ret == 1)
1340 break;
1341 msleep(1);
1342 }
1343 }
1344}
1345
1346static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1347 enum pipe *pipe)
1348{
1349 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1350 struct drm_device *dev = encoder->base.dev;
1351 struct drm_i915_private *dev_priv = dev->dev_private;
1352 u32 tmp = I915_READ(intel_dp->output_reg);
1353
1354 if (!(tmp & DP_PORT_EN))
1355 return false;
1356
1357 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
1358 *pipe = PORT_TO_PIPE_CPT(tmp);
1359 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1360 *pipe = PORT_TO_PIPE(tmp);
1361 } else {
1362 u32 trans_sel;
1363 u32 trans_dp;
1364 int i;
1365
1366 switch (intel_dp->output_reg) {
1367 case PCH_DP_B:
1368 trans_sel = TRANS_DP_PORT_SEL_B;
1369 break;
1370 case PCH_DP_C:
1371 trans_sel = TRANS_DP_PORT_SEL_C;
1372 break;
1373 case PCH_DP_D:
1374 trans_sel = TRANS_DP_PORT_SEL_D;
1375 break;
1376 default:
1377 return true;
1378 }
1379
1380 for_each_pipe(i) {
1381 trans_dp = I915_READ(TRANS_DP_CTL(i));
1382 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1383 *pipe = i;
1384 return true;
1385 }
1386 }
1387
1388 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1389 intel_dp->output_reg);
1390 }
1391
1392 return true;
1393}
1394
1395static void intel_disable_dp(struct intel_encoder *encoder)
1396{
1397 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1398
1399 /* Make sure the panel is off before trying to change the mode. But also
1400 * ensure that we have vdd while we switch off the panel. */
1401 ironlake_edp_panel_vdd_on(intel_dp);
1402 ironlake_edp_backlight_off(intel_dp);
1403 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1404 ironlake_edp_panel_off(intel_dp);
1405
1406 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1407 if (!is_cpu_edp(intel_dp))
1408 intel_dp_link_down(intel_dp);
1409}
1410
1411static void intel_post_disable_dp(struct intel_encoder *encoder)
1412{
1413 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1414
1415 if (is_cpu_edp(intel_dp)) {
1416 intel_dp_link_down(intel_dp);
1417 ironlake_edp_pll_off(intel_dp);
1418 }
1419}
1420
1421static void intel_enable_dp(struct intel_encoder *encoder)
1422{
1423 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1424 struct drm_device *dev = encoder->base.dev;
1425 struct drm_i915_private *dev_priv = dev->dev_private;
1426 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1427
1428 if (WARN_ON(dp_reg & DP_PORT_EN))
1429 return;
1430
1431 ironlake_edp_panel_vdd_on(intel_dp);
1432 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1433 intel_dp_start_link_train(intel_dp);
1434 ironlake_edp_panel_on(intel_dp);
1435 ironlake_edp_panel_vdd_off(intel_dp, true);
1436 intel_dp_complete_link_train(intel_dp);
1437 ironlake_edp_backlight_on(intel_dp);
1438}
1439
1440static void intel_pre_enable_dp(struct intel_encoder *encoder)
1441{
1442 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1443
1444 if (is_cpu_edp(intel_dp))
1445 ironlake_edp_pll_on(intel_dp);
1446}
1447
1448/*
1449 * Native read with retry for link status and receiver capability reads for
1450 * cases where the sink may still be asleep.
1451 */
1452static bool
1453intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1454 uint8_t *recv, int recv_bytes)
1455{
1456 int ret, i;
1457
1458 /*
1459 * Sinks are *supposed* to come up within 1ms from an off state,
1460 * but we're also supposed to retry 3 times per the spec.
1461 */
1462 for (i = 0; i < 3; i++) {
1463 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1464 recv_bytes);
1465 if (ret == recv_bytes)
1466 return true;
1467 msleep(1);
1468 }
1469
1470 return false;
1471}
1472
1473/*
1474 * Fetch AUX CH registers 0x202 - 0x207 which contain
1475 * link status information
1476 */
1477static bool
1478intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1479{
1480 return intel_dp_aux_native_read_retry(intel_dp,
1481 DP_LANE0_1_STATUS,
1482 link_status,
1483 DP_LINK_STATUS_SIZE);
1484}
1485
1486#if 0
1487static char *voltage_names[] = {
1488 "0.4V", "0.6V", "0.8V", "1.2V"
1489};
1490static char *pre_emph_names[] = {
1491 "0dB", "3.5dB", "6dB", "9.5dB"
1492};
1493static char *link_train_names[] = {
1494 "pattern 1", "pattern 2", "idle", "off"
1495};
1496#endif
1497
1498/*
1499 * These are source-specific values; current Intel hardware supports
1500 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1501 */
1502
1503static uint8_t
1504intel_dp_voltage_max(struct intel_dp *intel_dp)
1505{
1506 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1507
1508 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1509 return DP_TRAIN_VOLTAGE_SWING_800;
1510 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1511 return DP_TRAIN_VOLTAGE_SWING_1200;
1512 else
1513 return DP_TRAIN_VOLTAGE_SWING_800;
1514}
1515
1516static uint8_t
1517intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1518{
1519 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1520
1521 if (IS_HASWELL(dev)) {
1522 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1523 case DP_TRAIN_VOLTAGE_SWING_400:
1524 return DP_TRAIN_PRE_EMPHASIS_9_5;
1525 case DP_TRAIN_VOLTAGE_SWING_600:
1526 return DP_TRAIN_PRE_EMPHASIS_6;
1527 case DP_TRAIN_VOLTAGE_SWING_800:
1528 return DP_TRAIN_PRE_EMPHASIS_3_5;
1529 case DP_TRAIN_VOLTAGE_SWING_1200:
1530 default:
1531 return DP_TRAIN_PRE_EMPHASIS_0;
1532 }
1533 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1534 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1535 case DP_TRAIN_VOLTAGE_SWING_400:
1536 return DP_TRAIN_PRE_EMPHASIS_6;
1537 case DP_TRAIN_VOLTAGE_SWING_600:
1538 case DP_TRAIN_VOLTAGE_SWING_800:
1539 return DP_TRAIN_PRE_EMPHASIS_3_5;
1540 default:
1541 return DP_TRAIN_PRE_EMPHASIS_0;
1542 }
1543 } else {
1544 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1545 case DP_TRAIN_VOLTAGE_SWING_400:
1546 return DP_TRAIN_PRE_EMPHASIS_6;
1547 case DP_TRAIN_VOLTAGE_SWING_600:
1548 return DP_TRAIN_PRE_EMPHASIS_6;
1549 case DP_TRAIN_VOLTAGE_SWING_800:
1550 return DP_TRAIN_PRE_EMPHASIS_3_5;
1551 case DP_TRAIN_VOLTAGE_SWING_1200:
1552 default:
1553 return DP_TRAIN_PRE_EMPHASIS_0;
1554 }
1555 }
1556}
1557
1558static void
1559intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1560{
1561 uint8_t v = 0;
1562 uint8_t p = 0;
1563 int lane;
1564 uint8_t voltage_max;
1565 uint8_t preemph_max;
1566
1567 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1568 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1569 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
1570
1571 if (this_v > v)
1572 v = this_v;
1573 if (this_p > p)
1574 p = this_p;
1575 }
1576
1577 voltage_max = intel_dp_voltage_max(intel_dp);
1578 if (v >= voltage_max)
1579 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1580
1581 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1582 if (p >= preemph_max)
1583 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1584
1585 for (lane = 0; lane < 4; lane++)
1586 intel_dp->train_set[lane] = v | p;
1587}
1588
1589static uint32_t
1590intel_gen4_signal_levels(uint8_t train_set)
1591{
1592 uint32_t signal_levels = 0;
1593
1594 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1595 case DP_TRAIN_VOLTAGE_SWING_400:
1596 default:
1597 signal_levels |= DP_VOLTAGE_0_4;
1598 break;
1599 case DP_TRAIN_VOLTAGE_SWING_600:
1600 signal_levels |= DP_VOLTAGE_0_6;
1601 break;
1602 case DP_TRAIN_VOLTAGE_SWING_800:
1603 signal_levels |= DP_VOLTAGE_0_8;
1604 break;
1605 case DP_TRAIN_VOLTAGE_SWING_1200:
1606 signal_levels |= DP_VOLTAGE_1_2;
1607 break;
1608 }
1609 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1610 case DP_TRAIN_PRE_EMPHASIS_0:
1611 default:
1612 signal_levels |= DP_PRE_EMPHASIS_0;
1613 break;
1614 case DP_TRAIN_PRE_EMPHASIS_3_5:
1615 signal_levels |= DP_PRE_EMPHASIS_3_5;
1616 break;
1617 case DP_TRAIN_PRE_EMPHASIS_6:
1618 signal_levels |= DP_PRE_EMPHASIS_6;
1619 break;
1620 case DP_TRAIN_PRE_EMPHASIS_9_5:
1621 signal_levels |= DP_PRE_EMPHASIS_9_5;
1622 break;
1623 }
1624 return signal_levels;
1625}
1626
1627/* Gen6's DP voltage swing and pre-emphasis control */
1628static uint32_t
1629intel_gen6_edp_signal_levels(uint8_t train_set)
1630{
1631 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1632 DP_TRAIN_PRE_EMPHASIS_MASK);
1633 switch (signal_levels) {
1634 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1635 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1636 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1637 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1638 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1639 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1640 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1641 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1642 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1643 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1644 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1645 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1646 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1647 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1648 default:
1649 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1650 "0x%x\n", signal_levels);
1651 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1652 }
1653}
1654
1655/* Gen7's DP voltage swing and pre-emphasis control */
1656static uint32_t
1657intel_gen7_edp_signal_levels(uint8_t train_set)
1658{
1659 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1660 DP_TRAIN_PRE_EMPHASIS_MASK);
1661 switch (signal_levels) {
1662 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1663 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1664 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1665 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1666 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1667 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1668
1669 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1670 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1671 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1672 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1673
1674 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1675 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1676 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1677 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1678
1679 default:
1680 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1681 "0x%x\n", signal_levels);
1682 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1683 }
1684}
1685
1686/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1687static uint32_t
1688intel_hsw_signal_levels(uint8_t train_set)
1689{
1690 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1691 DP_TRAIN_PRE_EMPHASIS_MASK);
1692 switch (signal_levels) {
1693 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1694 return DDI_BUF_EMP_400MV_0DB_HSW;
1695 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1696 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1697 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1698 return DDI_BUF_EMP_400MV_6DB_HSW;
1699 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1700 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1701
1702 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1703 return DDI_BUF_EMP_600MV_0DB_HSW;
1704 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1705 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1706 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1707 return DDI_BUF_EMP_600MV_6DB_HSW;
1708
1709 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1710 return DDI_BUF_EMP_800MV_0DB_HSW;
1711 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1712 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1713 default:
1714 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1715 "0x%x\n", signal_levels);
1716 return DDI_BUF_EMP_400MV_0DB_HSW;
1717 }
1718}
1719
1720/* Properly updates "DP" with the correct signal levels. */
1721static void
1722intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
1723{
1724 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1725 struct drm_device *dev = intel_dig_port->base.base.dev;
1726 uint32_t signal_levels, mask;
1727 uint8_t train_set = intel_dp->train_set[0];
1728
1729 if (IS_HASWELL(dev)) {
1730 signal_levels = intel_hsw_signal_levels(train_set);
1731 mask = DDI_BUF_EMP_MASK;
1732 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1733 signal_levels = intel_gen7_edp_signal_levels(train_set);
1734 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1735 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1736 signal_levels = intel_gen6_edp_signal_levels(train_set);
1737 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1738 } else {
1739 signal_levels = intel_gen4_signal_levels(train_set);
1740 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
1741 }
1742
1743 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
1744
1745 *DP = (*DP & ~mask) | signal_levels;
1746}
1747
1748static bool
1749intel_dp_set_link_train(struct intel_dp *intel_dp,
1750 uint32_t dp_reg_value,
1751 uint8_t dp_train_pat)
1752{
1753 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1754 struct drm_device *dev = intel_dig_port->base.base.dev;
1755 struct drm_i915_private *dev_priv = dev->dev_private;
1756 enum port port = intel_dig_port->port;
1757 int ret;
1758 uint32_t temp;
1759
1760 if (IS_HASWELL(dev)) {
1761 temp = I915_READ(DP_TP_CTL(port));
1762
1763 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1764 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1765 else
1766 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1767
1768 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1769 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1770 case DP_TRAINING_PATTERN_DISABLE:
1771 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1772 I915_WRITE(DP_TP_CTL(port), temp);
1773
1774 if (wait_for((I915_READ(DP_TP_STATUS(port)) &
1775 DP_TP_STATUS_IDLE_DONE), 1))
1776 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1777
1778 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1779 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1780
1781 break;
1782 case DP_TRAINING_PATTERN_1:
1783 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1784 break;
1785 case DP_TRAINING_PATTERN_2:
1786 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1787 break;
1788 case DP_TRAINING_PATTERN_3:
1789 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1790 break;
1791 }
1792 I915_WRITE(DP_TP_CTL(port), temp);
1793
1794 } else if (HAS_PCH_CPT(dev) &&
1795 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1796 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1797
1798 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1799 case DP_TRAINING_PATTERN_DISABLE:
1800 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1801 break;
1802 case DP_TRAINING_PATTERN_1:
1803 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1804 break;
1805 case DP_TRAINING_PATTERN_2:
1806 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1807 break;
1808 case DP_TRAINING_PATTERN_3:
1809 DRM_ERROR("DP training pattern 3 not supported\n");
1810 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1811 break;
1812 }
1813
1814 } else {
1815 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1816
1817 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1818 case DP_TRAINING_PATTERN_DISABLE:
1819 dp_reg_value |= DP_LINK_TRAIN_OFF;
1820 break;
1821 case DP_TRAINING_PATTERN_1:
1822 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1823 break;
1824 case DP_TRAINING_PATTERN_2:
1825 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1826 break;
1827 case DP_TRAINING_PATTERN_3:
1828 DRM_ERROR("DP training pattern 3 not supported\n");
1829 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1830 break;
1831 }
1832 }
1833
1834 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1835 POSTING_READ(intel_dp->output_reg);
1836
1837 intel_dp_aux_native_write_1(intel_dp,
1838 DP_TRAINING_PATTERN_SET,
1839 dp_train_pat);
1840
1841 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1842 DP_TRAINING_PATTERN_DISABLE) {
1843 ret = intel_dp_aux_native_write(intel_dp,
1844 DP_TRAINING_LANE0_SET,
1845 intel_dp->train_set,
1846 intel_dp->lane_count);
1847 if (ret != intel_dp->lane_count)
1848 return false;
1849 }
1850
1851 return true;
1852}
1853
1854/* Enable corresponding port and start training pattern 1 */
1855void
1856intel_dp_start_link_train(struct intel_dp *intel_dp)
1857{
1858 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
1859 struct drm_device *dev = encoder->dev;
1860 int i;
1861 uint8_t voltage;
1862 bool clock_recovery = false;
1863 int voltage_tries, loop_tries;
1864 uint32_t DP = intel_dp->DP;
1865
1866 if (HAS_DDI(dev))
1867 intel_ddi_prepare_link_retrain(encoder);
1868
1869 /* Write the link configuration data */
1870 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1871 intel_dp->link_configuration,
1872 DP_LINK_CONFIGURATION_SIZE);
1873
1874 DP |= DP_PORT_EN;
1875
1876 memset(intel_dp->train_set, 0, 4);
1877 voltage = 0xff;
1878 voltage_tries = 0;
1879 loop_tries = 0;
1880 clock_recovery = false;
1881 for (;;) {
1882 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1883 uint8_t link_status[DP_LINK_STATUS_SIZE];
1884
1885 intel_dp_set_signal_levels(intel_dp, &DP);
1886
1887 /* Set training pattern 1 */
1888 if (!intel_dp_set_link_train(intel_dp, DP,
1889 DP_TRAINING_PATTERN_1 |
1890 DP_LINK_SCRAMBLING_DISABLE))
1891 break;
1892
1893 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
1894 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1895 DRM_ERROR("failed to get link status\n");
1896 break;
1897 }
1898
1899 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1900 DRM_DEBUG_KMS("clock recovery OK\n");
1901 clock_recovery = true;
1902 break;
1903 }
1904
1905 /* Check to see if we've tried the max voltage */
1906 for (i = 0; i < intel_dp->lane_count; i++)
1907 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1908 break;
1909 if (i == intel_dp->lane_count && voltage_tries == 5) {
1910 ++loop_tries;
1911 if (loop_tries == 5) {
1912 DRM_DEBUG_KMS("too many full retries, give up\n");
1913 break;
1914 }
1915 memset(intel_dp->train_set, 0, 4);
1916 voltage_tries = 0;
1917 continue;
1918 }
1919
1920 /* Check to see if we've tried the same voltage 5 times */
1921 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1922 ++voltage_tries;
1923 if (voltage_tries == 5) {
1924 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1925 break;
1926 }
1927 } else
1928 voltage_tries = 0;
1929 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1930
1931 /* Compute new intel_dp->train_set as requested by target */
1932 intel_get_adjust_train(intel_dp, link_status);
1933 }
1934
1935 intel_dp->DP = DP;
1936}
1937
1938void
1939intel_dp_complete_link_train(struct intel_dp *intel_dp)
1940{
1941 bool channel_eq = false;
1942 int tries, cr_tries;
1943 uint32_t DP = intel_dp->DP;
1944
1945 /* channel equalization */
1946 tries = 0;
1947 cr_tries = 0;
1948 channel_eq = false;
1949 for (;;) {
1950 uint8_t link_status[DP_LINK_STATUS_SIZE];
1951
1952 if (cr_tries > 5) {
1953 DRM_ERROR("failed to train DP, aborting\n");
1954 intel_dp_link_down(intel_dp);
1955 break;
1956 }
1957
1958 intel_dp_set_signal_levels(intel_dp, &DP);
1959
1960 /* channel eq pattern */
1961 if (!intel_dp_set_link_train(intel_dp, DP,
1962 DP_TRAINING_PATTERN_2 |
1963 DP_LINK_SCRAMBLING_DISABLE))
1964 break;
1965
1966 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
1967 if (!intel_dp_get_link_status(intel_dp, link_status))
1968 break;
1969
1970 /* Make sure clock is still ok */
1971 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1972 intel_dp_start_link_train(intel_dp);
1973 cr_tries++;
1974 continue;
1975 }
1976
1977 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
1978 channel_eq = true;
1979 break;
1980 }
1981
1982 /* Try 5 times, then try clock recovery if that fails */
1983 if (tries > 5) {
1984 intel_dp_link_down(intel_dp);
1985 intel_dp_start_link_train(intel_dp);
1986 tries = 0;
1987 cr_tries++;
1988 continue;
1989 }
1990
1991 /* Compute new intel_dp->train_set as requested by target */
1992 intel_get_adjust_train(intel_dp, link_status);
1993 ++tries;
1994 }
1995
1996 if (channel_eq)
1997 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
1998
1999 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
2000}
2001
2002static void
2003intel_dp_link_down(struct intel_dp *intel_dp)
2004{
2005 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2006 struct drm_device *dev = intel_dig_port->base.base.dev;
2007 struct drm_i915_private *dev_priv = dev->dev_private;
2008 struct intel_crtc *intel_crtc =
2009 to_intel_crtc(intel_dig_port->base.base.crtc);
2010 uint32_t DP = intel_dp->DP;
2011
2012 /*
2013 * DDI code has a strict mode set sequence and we should try to respect
2014 * it, otherwise we might hang the machine in many different ways. So we
2015 * really should be disabling the port only on a complete crtc_disable
2016 * sequence. This function is just called under two conditions on DDI
2017 * code:
2018 * - Link train failed while doing crtc_enable, and on this case we
2019 * really should respect the mode set sequence and wait for a
2020 * crtc_disable.
2021 * - Someone turned the monitor off and intel_dp_check_link_status
2022 * called us. We don't need to disable the whole port on this case, so
2023 * when someone turns the monitor on again,
2024 * intel_ddi_prepare_link_retrain will take care of redoing the link
2025 * train.
2026 */
2027 if (HAS_DDI(dev))
2028 return;
2029
2030 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2031 return;
2032
2033 DRM_DEBUG_KMS("\n");
2034
2035 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
2036 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2037 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2038 } else {
2039 DP &= ~DP_LINK_TRAIN_MASK;
2040 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2041 }
2042 POSTING_READ(intel_dp->output_reg);
2043
2044 /* We don't really know why we're doing this */
2045 intel_wait_for_vblank(dev, intel_crtc->pipe);
2046
2047 if (HAS_PCH_IBX(dev) &&
2048 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2049 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2050
2051 /* Hardware workaround: leaving our transcoder select
2052 * set to transcoder B while it's off will prevent the
2053 * corresponding HDMI output on transcoder A.
2054 *
2055 * Combine this with another hardware workaround:
2056 * transcoder select bit can only be cleared while the
2057 * port is enabled.
2058 */
2059 DP &= ~DP_PIPEB_SELECT;
2060 I915_WRITE(intel_dp->output_reg, DP);
2061
2062 /* Changes to enable or select take place the vblank
2063 * after being written.
2064 */
2065 if (WARN_ON(crtc == NULL)) {
2066 /* We should never try to disable a port without a crtc
2067 * attached. For paranoia keep the code around for a
2068 * bit. */
2069 POSTING_READ(intel_dp->output_reg);
2070 msleep(50);
2071 } else
2072 intel_wait_for_vblank(dev, intel_crtc->pipe);
2073 }
2074
2075 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2076 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2077 POSTING_READ(intel_dp->output_reg);
2078 msleep(intel_dp->panel_power_down_delay);
2079}
2080
2081static bool
2082intel_dp_get_dpcd(struct intel_dp *intel_dp)
2083{
2084 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2085
2086 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2087 sizeof(intel_dp->dpcd)) == 0)
2088 return false; /* aux transfer failed */
2089
2090 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2091 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2092 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2093
2094 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2095 return false; /* DPCD not present */
2096
2097 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2098 DP_DWN_STRM_PORT_PRESENT))
2099 return true; /* native DP sink */
2100
2101 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2102 return true; /* no per-port downstream info */
2103
2104 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2105 intel_dp->downstream_ports,
2106 DP_MAX_DOWNSTREAM_PORTS) == 0)
2107 return false; /* downstream port status fetch failed */
2108
2109 return true;
2110}
2111
2112static void
2113intel_dp_probe_oui(struct intel_dp *intel_dp)
2114{
2115 u8 buf[3];
2116
2117 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2118 return;
2119
2120 ironlake_edp_panel_vdd_on(intel_dp);
2121
2122 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2123 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2124 buf[0], buf[1], buf[2]);
2125
2126 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2127 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2128 buf[0], buf[1], buf[2]);
2129
2130 ironlake_edp_panel_vdd_off(intel_dp, false);
2131}
2132
2133static bool
2134intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2135{
2136 int ret;
2137
2138 ret = intel_dp_aux_native_read_retry(intel_dp,
2139 DP_DEVICE_SERVICE_IRQ_VECTOR,
2140 sink_irq_vector, 1);
2141 if (!ret)
2142 return false;
2143
2144 return true;
2145}
2146
2147static void
2148intel_dp_handle_test_request(struct intel_dp *intel_dp)
2149{
2150 /* NAK by default */
2151 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2152}
2153
2154/*
2155 * According to DP spec
2156 * 5.1.2:
2157 * 1. Read DPCD
2158 * 2. Configure link according to Receiver Capabilities
2159 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2160 * 4. Check link status on receipt of hot-plug interrupt
2161 */
2162
2163void
2164intel_dp_check_link_status(struct intel_dp *intel_dp)
2165{
2166 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2167 u8 sink_irq_vector;
2168 u8 link_status[DP_LINK_STATUS_SIZE];
2169
2170 if (!intel_encoder->connectors_active)
2171 return;
2172
2173 if (WARN_ON(!intel_encoder->base.crtc))
2174 return;
2175
2176 /* Try to read receiver status if the link appears to be up */
2177 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2178 intel_dp_link_down(intel_dp);
2179 return;
2180 }
2181
2182 /* Now read the DPCD to see if it's actually running */
2183 if (!intel_dp_get_dpcd(intel_dp)) {
2184 intel_dp_link_down(intel_dp);
2185 return;
2186 }
2187
2188 /* Try to read the source of the interrupt */
2189 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2190 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2191 /* Clear interrupt source */
2192 intel_dp_aux_native_write_1(intel_dp,
2193 DP_DEVICE_SERVICE_IRQ_VECTOR,
2194 sink_irq_vector);
2195
2196 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2197 intel_dp_handle_test_request(intel_dp);
2198 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2199 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2200 }
2201
2202 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2203 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2204 drm_get_encoder_name(&intel_encoder->base));
2205 intel_dp_start_link_train(intel_dp);
2206 intel_dp_complete_link_train(intel_dp);
2207 }
2208}
2209
2210/* XXX this is probably wrong for multiple downstream ports */
2211static enum drm_connector_status
2212intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2213{
2214 uint8_t *dpcd = intel_dp->dpcd;
2215 bool hpd;
2216 uint8_t type;
2217
2218 if (!intel_dp_get_dpcd(intel_dp))
2219 return connector_status_disconnected;
2220
2221 /* if there's no downstream port, we're done */
2222 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2223 return connector_status_connected;
2224
2225 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2226 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2227 if (hpd) {
2228 uint8_t reg;
2229 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2230 &reg, 1))
2231 return connector_status_unknown;
2232 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2233 : connector_status_disconnected;
2234 }
2235
2236 /* If no HPD, poke DDC gently */
2237 if (drm_probe_ddc(&intel_dp->adapter))
2238 return connector_status_connected;
2239
2240 /* Well we tried, say unknown for unreliable port types */
2241 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2242 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2243 return connector_status_unknown;
2244
2245 /* Anything else is out of spec, warn and ignore */
2246 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2247 return connector_status_disconnected;
2248}
2249
2250static enum drm_connector_status
2251ironlake_dp_detect(struct intel_dp *intel_dp)
2252{
2253 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2254 struct drm_i915_private *dev_priv = dev->dev_private;
2255 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2256 enum drm_connector_status status;
2257
2258 /* Can't disconnect eDP, but you can close the lid... */
2259 if (is_edp(intel_dp)) {
2260 status = intel_panel_detect(dev);
2261 if (status == connector_status_unknown)
2262 status = connector_status_connected;
2263 return status;
2264 }
2265
2266 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2267 return connector_status_disconnected;
2268
2269 return intel_dp_detect_dpcd(intel_dp);
2270}
2271
2272static enum drm_connector_status
2273g4x_dp_detect(struct intel_dp *intel_dp)
2274{
2275 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2276 struct drm_i915_private *dev_priv = dev->dev_private;
2277 uint32_t bit;
2278
2279 switch (intel_dp->output_reg) {
2280 case DP_B:
2281 bit = DPB_HOTPLUG_LIVE_STATUS;
2282 break;
2283 case DP_C:
2284 bit = DPC_HOTPLUG_LIVE_STATUS;
2285 break;
2286 case DP_D:
2287 bit = DPD_HOTPLUG_LIVE_STATUS;
2288 break;
2289 default:
2290 return connector_status_unknown;
2291 }
2292
2293 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2294 return connector_status_disconnected;
2295
2296 return intel_dp_detect_dpcd(intel_dp);
2297}
2298
2299static struct edid *
2300intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2301{
2302 struct intel_connector *intel_connector = to_intel_connector(connector);
2303
2304 /* use cached edid if we have one */
2305 if (intel_connector->edid) {
2306 struct edid *edid;
2307 int size;
2308
2309 /* invalid edid */
2310 if (IS_ERR(intel_connector->edid))
2311 return NULL;
2312
2313 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2314 edid = kmalloc(size, GFP_KERNEL);
2315 if (!edid)
2316 return NULL;
2317
2318 memcpy(edid, intel_connector->edid, size);
2319 return edid;
2320 }
2321
2322 return drm_get_edid(connector, adapter);
2323}
2324
2325static int
2326intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2327{
2328 struct intel_connector *intel_connector = to_intel_connector(connector);
2329
2330 /* use cached edid if we have one */
2331 if (intel_connector->edid) {
2332 /* invalid edid */
2333 if (IS_ERR(intel_connector->edid))
2334 return 0;
2335
2336 return intel_connector_update_modes(connector,
2337 intel_connector->edid);
2338 }
2339
2340 return intel_ddc_get_modes(connector, adapter);
2341}
2342
2343static enum drm_connector_status
2344intel_dp_detect(struct drm_connector *connector, bool force)
2345{
2346 struct intel_dp *intel_dp = intel_attached_dp(connector);
2347 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2348 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2349 struct drm_device *dev = connector->dev;
2350 enum drm_connector_status status;
2351 struct edid *edid = NULL;
2352
2353 intel_dp->has_audio = false;
2354
2355 if (HAS_PCH_SPLIT(dev))
2356 status = ironlake_dp_detect(intel_dp);
2357 else
2358 status = g4x_dp_detect(intel_dp);
2359
2360 if (status != connector_status_connected)
2361 return status;
2362
2363 intel_dp_probe_oui(intel_dp);
2364
2365 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2366 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2367 } else {
2368 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2369 if (edid) {
2370 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2371 kfree(edid);
2372 }
2373 }
2374
2375 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2376 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2377 return connector_status_connected;
2378}
2379
2380static int intel_dp_get_modes(struct drm_connector *connector)
2381{
2382 struct intel_dp *intel_dp = intel_attached_dp(connector);
2383 struct intel_connector *intel_connector = to_intel_connector(connector);
2384 struct drm_device *dev = connector->dev;
2385 int ret;
2386
2387 /* We should parse the EDID data and find out if it has an audio sink
2388 */
2389
2390 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2391 if (ret)
2392 return ret;
2393
2394 /* if eDP has no EDID, fall back to fixed mode */
2395 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2396 struct drm_display_mode *mode;
2397 mode = drm_mode_duplicate(dev,
2398 intel_connector->panel.fixed_mode);
2399 if (mode) {
2400 drm_mode_probed_add(connector, mode);
2401 return 1;
2402 }
2403 }
2404 return 0;
2405}
2406
2407static bool
2408intel_dp_detect_audio(struct drm_connector *connector)
2409{
2410 struct intel_dp *intel_dp = intel_attached_dp(connector);
2411 struct edid *edid;
2412 bool has_audio = false;
2413
2414 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2415 if (edid) {
2416 has_audio = drm_detect_monitor_audio(edid);
2417 kfree(edid);
2418 }
2419
2420 return has_audio;
2421}
2422
2423static int
2424intel_dp_set_property(struct drm_connector *connector,
2425 struct drm_property *property,
2426 uint64_t val)
2427{
2428 struct drm_i915_private *dev_priv = connector->dev->dev_private;
2429 struct intel_connector *intel_connector = to_intel_connector(connector);
2430 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2431 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2432 int ret;
2433
2434 ret = drm_object_property_set_value(&connector->base, property, val);
2435 if (ret)
2436 return ret;
2437
2438 if (property == dev_priv->force_audio_property) {
2439 int i = val;
2440 bool has_audio;
2441
2442 if (i == intel_dp->force_audio)
2443 return 0;
2444
2445 intel_dp->force_audio = i;
2446
2447 if (i == HDMI_AUDIO_AUTO)
2448 has_audio = intel_dp_detect_audio(connector);
2449 else
2450 has_audio = (i == HDMI_AUDIO_ON);
2451
2452 if (has_audio == intel_dp->has_audio)
2453 return 0;
2454
2455 intel_dp->has_audio = has_audio;
2456 goto done;
2457 }
2458
2459 if (property == dev_priv->broadcast_rgb_property) {
2460 if (val == !!intel_dp->color_range)
2461 return 0;
2462
2463 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2464 goto done;
2465 }
2466
2467 if (is_edp(intel_dp) &&
2468 property == connector->dev->mode_config.scaling_mode_property) {
2469 if (val == DRM_MODE_SCALE_NONE) {
2470 DRM_DEBUG_KMS("no scaling not supported\n");
2471 return -EINVAL;
2472 }
2473
2474 if (intel_connector->panel.fitting_mode == val) {
2475 /* the eDP scaling property is not changed */
2476 return 0;
2477 }
2478 intel_connector->panel.fitting_mode = val;
2479
2480 goto done;
2481 }
2482
2483 return -EINVAL;
2484
2485done:
2486 if (intel_encoder->base.crtc)
2487 intel_crtc_restore_mode(intel_encoder->base.crtc);
2488
2489 return 0;
2490}
2491
2492static void
2493intel_dp_destroy(struct drm_connector *connector)
2494{
2495 struct drm_device *dev = connector->dev;
2496 struct intel_dp *intel_dp = intel_attached_dp(connector);
2497 struct intel_connector *intel_connector = to_intel_connector(connector);
2498
2499 if (!IS_ERR_OR_NULL(intel_connector->edid))
2500 kfree(intel_connector->edid);
2501
2502 if (is_edp(intel_dp)) {
2503 intel_panel_destroy_backlight(dev);
2504 intel_panel_fini(&intel_connector->panel);
2505 }
2506
2507 drm_sysfs_connector_remove(connector);
2508 drm_connector_cleanup(connector);
2509 kfree(connector);
2510}
2511
2512void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2513{
2514 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2515 struct intel_dp *intel_dp = &intel_dig_port->dp;
2516
2517 i2c_del_adapter(&intel_dp->adapter);
2518 drm_encoder_cleanup(encoder);
2519 if (is_edp(intel_dp)) {
2520 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2521 ironlake_panel_vdd_off_sync(intel_dp);
2522 }
2523 kfree(intel_dig_port);
2524}
2525
2526static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2527 .mode_fixup = intel_dp_mode_fixup,
2528 .mode_set = intel_dp_mode_set,
2529 .disable = intel_encoder_noop,
2530};
2531
2532static const struct drm_connector_funcs intel_dp_connector_funcs = {
2533 .dpms = intel_connector_dpms,
2534 .detect = intel_dp_detect,
2535 .fill_modes = drm_helper_probe_single_connector_modes,
2536 .set_property = intel_dp_set_property,
2537 .destroy = intel_dp_destroy,
2538};
2539
2540static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2541 .get_modes = intel_dp_get_modes,
2542 .mode_valid = intel_dp_mode_valid,
2543 .best_encoder = intel_best_encoder,
2544};
2545
2546static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2547 .destroy = intel_dp_encoder_destroy,
2548};
2549
2550static void
2551intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2552{
2553 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2554
2555 intel_dp_check_link_status(intel_dp);
2556}
2557
2558/* Return which DP Port should be selected for Transcoder DP control */
2559int
2560intel_trans_dp_port_sel(struct drm_crtc *crtc)
2561{
2562 struct drm_device *dev = crtc->dev;
2563 struct intel_encoder *intel_encoder;
2564 struct intel_dp *intel_dp;
2565
2566 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2567 intel_dp = enc_to_intel_dp(&intel_encoder->base);
2568
2569 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2570 intel_encoder->type == INTEL_OUTPUT_EDP)
2571 return intel_dp->output_reg;
2572 }
2573
2574 return -1;
2575}
2576
2577/* check the VBT to see whether the eDP is on DP-D port */
2578bool intel_dpd_is_edp(struct drm_device *dev)
2579{
2580 struct drm_i915_private *dev_priv = dev->dev_private;
2581 struct child_device_config *p_child;
2582 int i;
2583
2584 if (!dev_priv->child_dev_num)
2585 return false;
2586
2587 for (i = 0; i < dev_priv->child_dev_num; i++) {
2588 p_child = dev_priv->child_dev + i;
2589
2590 if (p_child->dvo_port == PORT_IDPD &&
2591 p_child->device_type == DEVICE_TYPE_eDP)
2592 return true;
2593 }
2594 return false;
2595}
2596
2597static void
2598intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2599{
2600 struct intel_connector *intel_connector = to_intel_connector(connector);
2601
2602 intel_attach_force_audio_property(connector);
2603 intel_attach_broadcast_rgb_property(connector);
2604
2605 if (is_edp(intel_dp)) {
2606 drm_mode_create_scaling_mode_property(connector->dev);
2607 drm_object_attach_property(
2608 &connector->base,
2609 connector->dev->mode_config.scaling_mode_property,
2610 DRM_MODE_SCALE_ASPECT);
2611 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
2612 }
2613}
2614
2615static void
2616intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2617 struct intel_dp *intel_dp)
2618{
2619 struct drm_i915_private *dev_priv = dev->dev_private;
2620 struct edp_power_seq cur, vbt, spec, final;
2621 u32 pp_on, pp_off, pp_div, pp;
2622
2623 /* Workaround: Need to write PP_CONTROL with the unlock key as
2624 * the very first thing. */
2625 pp = ironlake_get_pp_control(dev_priv);
2626 I915_WRITE(PCH_PP_CONTROL, pp);
2627
2628 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2629 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2630 pp_div = I915_READ(PCH_PP_DIVISOR);
2631
2632 /* Pull timing values out of registers */
2633 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2634 PANEL_POWER_UP_DELAY_SHIFT;
2635
2636 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2637 PANEL_LIGHT_ON_DELAY_SHIFT;
2638
2639 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2640 PANEL_LIGHT_OFF_DELAY_SHIFT;
2641
2642 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2643 PANEL_POWER_DOWN_DELAY_SHIFT;
2644
2645 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2646 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2647
2648 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2649 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2650
2651 vbt = dev_priv->edp.pps;
2652
2653 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2654 * our hw here, which are all in 100usec. */
2655 spec.t1_t3 = 210 * 10;
2656 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2657 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2658 spec.t10 = 500 * 10;
2659 /* This one is special and actually in units of 100ms, but zero
2660 * based in the hw (so we need to add 100 ms). But the sw vbt
2661 * table multiplies it with 1000 to make it in units of 100usec,
2662 * too. */
2663 spec.t11_t12 = (510 + 100) * 10;
2664
2665 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2666 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2667
2668 /* Use the max of the register settings and vbt. If both are
2669 * unset, fall back to the spec limits. */
2670#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2671 spec.field : \
2672 max(cur.field, vbt.field))
2673 assign_final(t1_t3);
2674 assign_final(t8);
2675 assign_final(t9);
2676 assign_final(t10);
2677 assign_final(t11_t12);
2678#undef assign_final
2679
2680#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2681 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2682 intel_dp->backlight_on_delay = get_delay(t8);
2683 intel_dp->backlight_off_delay = get_delay(t9);
2684 intel_dp->panel_power_down_delay = get_delay(t10);
2685 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2686#undef get_delay
2687
2688 /* And finally store the new values in the power sequencer. */
2689 pp_on = (final.t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2690 (final.t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2691 pp_off = (final.t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2692 (final.t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2693 /* Compute the divisor for the pp clock, simply match the Bspec
2694 * formula. */
2695 pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
2696 << PP_REFERENCE_DIVIDER_SHIFT;
2697 pp_div |= (DIV_ROUND_UP(final.t11_t12, 1000)
2698 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2699
2700 /* Haswell doesn't have any port selection bits for the panel
2701 * power sequencer any more. */
2702 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2703 if (is_cpu_edp(intel_dp))
2704 pp_on |= PANEL_POWER_PORT_DP_A;
2705 else
2706 pp_on |= PANEL_POWER_PORT_DP_D;
2707 }
2708
2709 I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
2710 I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
2711 I915_WRITE(PCH_PP_DIVISOR, pp_div);
2712
2713
2714 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2715 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2716 intel_dp->panel_power_cycle_delay);
2717
2718 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2719 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2720
2721 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2722 I915_READ(PCH_PP_ON_DELAYS),
2723 I915_READ(PCH_PP_OFF_DELAYS),
2724 I915_READ(PCH_PP_DIVISOR));
2725}
2726
2727void
2728intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2729 struct intel_connector *intel_connector)
2730{
2731 struct drm_connector *connector = &intel_connector->base;
2732 struct intel_dp *intel_dp = &intel_dig_port->dp;
2733 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2734 struct drm_device *dev = intel_encoder->base.dev;
2735 struct drm_i915_private *dev_priv = dev->dev_private;
2736 struct drm_display_mode *fixed_mode = NULL;
2737 enum port port = intel_dig_port->port;
2738 const char *name = NULL;
2739 int type;
2740
2741 /* Preserve the current hw state. */
2742 intel_dp->DP = I915_READ(intel_dp->output_reg);
2743 intel_dp->attached_connector = intel_connector;
2744
2745 if (HAS_PCH_SPLIT(dev) && port == PORT_D)
2746 if (intel_dpd_is_edp(dev))
2747 intel_dp->is_pch_edp = true;
2748
2749 /*
2750 * FIXME : We need to initialize built-in panels before external panels.
2751 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2752 */
2753 if (IS_VALLEYVIEW(dev) && port == PORT_C) {
2754 type = DRM_MODE_CONNECTOR_eDP;
2755 intel_encoder->type = INTEL_OUTPUT_EDP;
2756 } else if (port == PORT_A || is_pch_edp(intel_dp)) {
2757 type = DRM_MODE_CONNECTOR_eDP;
2758 intel_encoder->type = INTEL_OUTPUT_EDP;
2759 } else {
2760 /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for
2761 * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't
2762 * rewrite it.
2763 */
2764 type = DRM_MODE_CONNECTOR_DisplayPort;
2765 }
2766
2767 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2768 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2769
2770 connector->polled = DRM_CONNECTOR_POLL_HPD;
2771 connector->interlace_allowed = true;
2772 connector->doublescan_allowed = 0;
2773
2774 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2775 ironlake_panel_vdd_work);
2776
2777 intel_connector_attach_encoder(intel_connector, intel_encoder);
2778 drm_sysfs_connector_add(connector);
2779
2780 if (HAS_DDI(dev))
2781 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2782 else
2783 intel_connector->get_hw_state = intel_connector_get_hw_state;
2784
2785
2786 /* Set up the DDC bus. */
2787 switch (port) {
2788 case PORT_A:
2789 name = "DPDDC-A";
2790 break;
2791 case PORT_B:
2792 dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS;
2793 name = "DPDDC-B";
2794 break;
2795 case PORT_C:
2796 dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS;
2797 name = "DPDDC-C";
2798 break;
2799 case PORT_D:
2800 dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS;
2801 name = "DPDDC-D";
2802 break;
2803 default:
2804 WARN(1, "Invalid port %c\n", port_name(port));
2805 break;
2806 }
2807
2808 if (is_edp(intel_dp))
2809 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2810
2811 intel_dp_i2c_init(intel_dp, intel_connector, name);
2812
2813 /* Cache DPCD and EDID for edp. */
2814 if (is_edp(intel_dp)) {
2815 bool ret;
2816 struct drm_display_mode *scan;
2817 struct edid *edid;
2818
2819 ironlake_edp_panel_vdd_on(intel_dp);
2820 ret = intel_dp_get_dpcd(intel_dp);
2821 ironlake_edp_panel_vdd_off(intel_dp, false);
2822
2823 if (ret) {
2824 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2825 dev_priv->no_aux_handshake =
2826 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2827 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2828 } else {
2829 /* if this fails, presume the device is a ghost */
2830 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2831 intel_dp_encoder_destroy(&intel_encoder->base);
2832 intel_dp_destroy(connector);
2833 return;
2834 }
2835
2836 ironlake_edp_panel_vdd_on(intel_dp);
2837 edid = drm_get_edid(connector, &intel_dp->adapter);
2838 if (edid) {
2839 if (drm_add_edid_modes(connector, edid)) {
2840 drm_mode_connector_update_edid_property(connector, edid);
2841 drm_edid_to_eld(connector, edid);
2842 } else {
2843 kfree(edid);
2844 edid = ERR_PTR(-EINVAL);
2845 }
2846 } else {
2847 edid = ERR_PTR(-ENOENT);
2848 }
2849 intel_connector->edid = edid;
2850
2851 /* prefer fixed mode from EDID if available */
2852 list_for_each_entry(scan, &connector->probed_modes, head) {
2853 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
2854 fixed_mode = drm_mode_duplicate(dev, scan);
2855 break;
2856 }
2857 }
2858
2859 /* fallback to VBT if available for eDP */
2860 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
2861 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2862 if (fixed_mode)
2863 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
2864 }
2865
2866 ironlake_edp_panel_vdd_off(intel_dp, false);
2867 }
2868
2869 if (is_edp(intel_dp)) {
2870 intel_panel_init(&intel_connector->panel, fixed_mode);
2871 intel_panel_setup_backlight(connector);
2872 }
2873
2874 intel_dp_add_properties(intel_dp, connector);
2875
2876 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2877 * 0xd. Failure to do so will result in spurious interrupts being
2878 * generated on the port when a cable is not attached.
2879 */
2880 if (IS_G4X(dev) && !IS_GM45(dev)) {
2881 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2882 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2883 }
2884}
2885
2886void
2887intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2888{
2889 struct intel_digital_port *intel_dig_port;
2890 struct intel_encoder *intel_encoder;
2891 struct drm_encoder *encoder;
2892 struct intel_connector *intel_connector;
2893
2894 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
2895 if (!intel_dig_port)
2896 return;
2897
2898 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2899 if (!intel_connector) {
2900 kfree(intel_dig_port);
2901 return;
2902 }
2903
2904 intel_encoder = &intel_dig_port->base;
2905 encoder = &intel_encoder->base;
2906
2907 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2908 DRM_MODE_ENCODER_TMDS);
2909 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2910
2911 intel_encoder->enable = intel_enable_dp;
2912 intel_encoder->pre_enable = intel_pre_enable_dp;
2913 intel_encoder->disable = intel_disable_dp;
2914 intel_encoder->post_disable = intel_post_disable_dp;
2915 intel_encoder->get_hw_state = intel_dp_get_hw_state;
2916
2917 intel_dig_port->port = port;
2918 intel_dig_port->dp.output_reg = output_reg;
2919
2920 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2921 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2922 intel_encoder->cloneable = false;
2923 intel_encoder->hot_plug = intel_dp_hot_plug;
2924
2925 intel_dp_init_connector(intel_dig_port, intel_connector);
2926}
Linux kernel - Deliverables
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