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drm/i915: Add output_types bitmask into the crtc state
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_drv.h
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1/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25#ifndef __INTEL_DRV_H__
26#define __INTEL_DRV_H__
27
28#include <linux/async.h>
29#include <linux/i2c.h>
30#include <linux/hdmi.h>
31#include <drm/i915_drm.h>
32#include "i915_drv.h"
33#include <drm/drm_crtc.h>
34#include <drm/drm_crtc_helper.h>
35#include <drm/drm_fb_helper.h>
36#include <drm/drm_dp_dual_mode_helper.h>
37#include <drm/drm_dp_mst_helper.h>
38#include <drm/drm_rect.h>
39#include <drm/drm_atomic.h>
40
41/**
42 * _wait_for - magic (register) wait macro
43 *
44 * Does the right thing for modeset paths when run under kdgb or similar atomic
45 * contexts. Note that it's important that we check the condition again after
46 * having timed out, since the timeout could be due to preemption or similar and
47 * we've never had a chance to check the condition before the timeout.
48 *
49 * TODO: When modesetting has fully transitioned to atomic, the below
50 * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
51 * added.
52 */
53#define _wait_for(COND, US, W) ({ \
54 unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1; \
55 int ret__ = 0; \
56 while (!(COND)) { \
57 if (time_after(jiffies, timeout__)) { \
58 if (!(COND)) \
59 ret__ = -ETIMEDOUT; \
60 break; \
61 } \
62 if ((W) && drm_can_sleep()) { \
63 usleep_range((W), (W)*2); \
64 } else { \
65 cpu_relax(); \
66 } \
67 } \
68 ret__; \
69})
70
71#define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 1000)
72
73/* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
74#if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
75# define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
76#else
77# define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
78#endif
79
80#define _wait_for_atomic(COND, US, ATOMIC) \
81({ \
82 int cpu, ret, timeout = (US) * 1000; \
83 u64 base; \
84 _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
85 BUILD_BUG_ON((US) > 50000); \
86 if (!(ATOMIC)) { \
87 preempt_disable(); \
88 cpu = smp_processor_id(); \
89 } \
90 base = local_clock(); \
91 for (;;) { \
92 u64 now = local_clock(); \
93 if (!(ATOMIC)) \
94 preempt_enable(); \
95 if (COND) { \
96 ret = 0; \
97 break; \
98 } \
99 if (now - base >= timeout) { \
100 ret = -ETIMEDOUT; \
101 break; \
102 } \
103 cpu_relax(); \
104 if (!(ATOMIC)) { \
105 preempt_disable(); \
106 if (unlikely(cpu != smp_processor_id())) { \
107 timeout -= now - base; \
108 cpu = smp_processor_id(); \
109 base = local_clock(); \
110 } \
111 } \
112 } \
113 ret; \
114})
115
116#define wait_for_us(COND, US) \
117({ \
118 int ret__; \
119 BUILD_BUG_ON(!__builtin_constant_p(US)); \
120 if ((US) > 10) \
121 ret__ = _wait_for((COND), (US), 10); \
122 else \
123 ret__ = _wait_for_atomic((COND), (US), 0); \
124 ret__; \
125})
126
127#define wait_for_atomic(COND, MS) _wait_for_atomic((COND), (MS) * 1000, 1)
128#define wait_for_atomic_us(COND, US) _wait_for_atomic((COND), (US), 1)
129
130#define KHz(x) (1000 * (x))
131#define MHz(x) KHz(1000 * (x))
132
133/*
134 * Display related stuff
135 */
136
137/* store information about an Ixxx DVO */
138/* The i830->i865 use multiple DVOs with multiple i2cs */
139/* the i915, i945 have a single sDVO i2c bus - which is different */
140#define MAX_OUTPUTS 6
141/* maximum connectors per crtcs in the mode set */
142
143/* Maximum cursor sizes */
144#define GEN2_CURSOR_WIDTH 64
145#define GEN2_CURSOR_HEIGHT 64
146#define MAX_CURSOR_WIDTH 256
147#define MAX_CURSOR_HEIGHT 256
148
149#define INTEL_I2C_BUS_DVO 1
150#define INTEL_I2C_BUS_SDVO 2
151
152/* these are outputs from the chip - integrated only
153 external chips are via DVO or SDVO output */
154enum intel_output_type {
155 INTEL_OUTPUT_UNUSED = 0,
156 INTEL_OUTPUT_ANALOG = 1,
157 INTEL_OUTPUT_DVO = 2,
158 INTEL_OUTPUT_SDVO = 3,
159 INTEL_OUTPUT_LVDS = 4,
160 INTEL_OUTPUT_TVOUT = 5,
161 INTEL_OUTPUT_HDMI = 6,
162 INTEL_OUTPUT_DISPLAYPORT = 7,
163 INTEL_OUTPUT_EDP = 8,
164 INTEL_OUTPUT_DSI = 9,
165 INTEL_OUTPUT_UNKNOWN = 10,
166 INTEL_OUTPUT_DP_MST = 11,
167};
168
169#define INTEL_DVO_CHIP_NONE 0
170#define INTEL_DVO_CHIP_LVDS 1
171#define INTEL_DVO_CHIP_TMDS 2
172#define INTEL_DVO_CHIP_TVOUT 4
173
174#define INTEL_DSI_VIDEO_MODE 0
175#define INTEL_DSI_COMMAND_MODE 1
176
177struct intel_framebuffer {
178 struct drm_framebuffer base;
179 struct drm_i915_gem_object *obj;
180 struct intel_rotation_info rot_info;
181};
182
183struct intel_fbdev {
184 struct drm_fb_helper helper;
185 struct intel_framebuffer *fb;
186 async_cookie_t cookie;
187 int preferred_bpp;
188};
189
190struct intel_encoder {
191 struct drm_encoder base;
192
193 enum intel_output_type type;
194 unsigned int cloneable;
195 void (*hot_plug)(struct intel_encoder *);
196 bool (*compute_config)(struct intel_encoder *,
197 struct intel_crtc_state *);
198 void (*pre_pll_enable)(struct intel_encoder *);
199 void (*pre_enable)(struct intel_encoder *);
200 void (*enable)(struct intel_encoder *);
201 void (*mode_set)(struct intel_encoder *intel_encoder);
202 void (*disable)(struct intel_encoder *);
203 void (*post_disable)(struct intel_encoder *);
204 void (*post_pll_disable)(struct intel_encoder *);
205 /* Read out the current hw state of this connector, returning true if
206 * the encoder is active. If the encoder is enabled it also set the pipe
207 * it is connected to in the pipe parameter. */
208 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
209 /* Reconstructs the equivalent mode flags for the current hardware
210 * state. This must be called _after_ display->get_pipe_config has
211 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
212 * be set correctly before calling this function. */
213 void (*get_config)(struct intel_encoder *,
214 struct intel_crtc_state *pipe_config);
215 /*
216 * Called during system suspend after all pending requests for the
217 * encoder are flushed (for example for DP AUX transactions) and
218 * device interrupts are disabled.
219 */
220 void (*suspend)(struct intel_encoder *);
221 int crtc_mask;
222 enum hpd_pin hpd_pin;
223};
224
225struct intel_panel {
226 struct drm_display_mode *fixed_mode;
227 struct drm_display_mode *downclock_mode;
228 int fitting_mode;
229
230 /* backlight */
231 struct {
232 bool present;
233 u32 level;
234 u32 min;
235 u32 max;
236 bool enabled;
237 bool combination_mode; /* gen 2/4 only */
238 bool active_low_pwm;
239
240 /* PWM chip */
241 bool util_pin_active_low; /* bxt+ */
242 u8 controller; /* bxt+ only */
243 struct pwm_device *pwm;
244
245 struct backlight_device *device;
246
247 /* Connector and platform specific backlight functions */
248 int (*setup)(struct intel_connector *connector, enum pipe pipe);
249 uint32_t (*get)(struct intel_connector *connector);
250 void (*set)(struct intel_connector *connector, uint32_t level);
251 void (*disable)(struct intel_connector *connector);
252 void (*enable)(struct intel_connector *connector);
253 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
254 uint32_t hz);
255 void (*power)(struct intel_connector *, bool enable);
256 } backlight;
257};
258
259struct intel_connector {
260 struct drm_connector base;
261 /*
262 * The fixed encoder this connector is connected to.
263 */
264 struct intel_encoder *encoder;
265
266 /* Reads out the current hw, returning true if the connector is enabled
267 * and active (i.e. dpms ON state). */
268 bool (*get_hw_state)(struct intel_connector *);
269
270 /* Panel info for eDP and LVDS */
271 struct intel_panel panel;
272
273 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
274 struct edid *edid;
275 struct edid *detect_edid;
276
277 /* since POLL and HPD connectors may use the same HPD line keep the native
278 state of connector->polled in case hotplug storm detection changes it */
279 u8 polled;
280
281 void *port; /* store this opaque as its illegal to dereference it */
282
283 struct intel_dp *mst_port;
284};
285
286struct dpll {
287 /* given values */
288 int n;
289 int m1, m2;
290 int p1, p2;
291 /* derived values */
292 int dot;
293 int vco;
294 int m;
295 int p;
296};
297
298struct intel_atomic_state {
299 struct drm_atomic_state base;
300
301 unsigned int cdclk;
302
303 /*
304 * Calculated device cdclk, can be different from cdclk
305 * only when all crtc's are DPMS off.
306 */
307 unsigned int dev_cdclk;
308
309 bool dpll_set, modeset;
310
311 /*
312 * Does this transaction change the pipes that are active? This mask
313 * tracks which CRTC's have changed their active state at the end of
314 * the transaction (not counting the temporary disable during modesets).
315 * This mask should only be non-zero when intel_state->modeset is true,
316 * but the converse is not necessarily true; simply changing a mode may
317 * not flip the final active status of any CRTC's
318 */
319 unsigned int active_pipe_changes;
320
321 unsigned int active_crtcs;
322 unsigned int min_pixclk[I915_MAX_PIPES];
323
324 /* SKL/KBL Only */
325 unsigned int cdclk_pll_vco;
326
327 struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
328
329 /*
330 * Current watermarks can't be trusted during hardware readout, so
331 * don't bother calculating intermediate watermarks.
332 */
333 bool skip_intermediate_wm;
334
335 /* Gen9+ only */
336 struct skl_wm_values wm_results;
337};
338
339struct intel_plane_state {
340 struct drm_plane_state base;
341 struct drm_rect src;
342 struct drm_rect dst;
343 struct drm_rect clip;
344 bool visible;
345
346 /*
347 * scaler_id
348 * = -1 : not using a scaler
349 * >= 0 : using a scalers
350 *
351 * plane requiring a scaler:
352 * - During check_plane, its bit is set in
353 * crtc_state->scaler_state.scaler_users by calling helper function
354 * update_scaler_plane.
355 * - scaler_id indicates the scaler it got assigned.
356 *
357 * plane doesn't require a scaler:
358 * - this can happen when scaling is no more required or plane simply
359 * got disabled.
360 * - During check_plane, corresponding bit is reset in
361 * crtc_state->scaler_state.scaler_users by calling helper function
362 * update_scaler_plane.
363 */
364 int scaler_id;
365
366 struct drm_intel_sprite_colorkey ckey;
367
368 /* async flip related structures */
369 struct drm_i915_gem_request *wait_req;
370};
371
372struct intel_initial_plane_config {
373 struct intel_framebuffer *fb;
374 unsigned int tiling;
375 int size;
376 u32 base;
377};
378
379#define SKL_MIN_SRC_W 8
380#define SKL_MAX_SRC_W 4096
381#define SKL_MIN_SRC_H 8
382#define SKL_MAX_SRC_H 4096
383#define SKL_MIN_DST_W 8
384#define SKL_MAX_DST_W 4096
385#define SKL_MIN_DST_H 8
386#define SKL_MAX_DST_H 4096
387
388struct intel_scaler {
389 int in_use;
390 uint32_t mode;
391};
392
393struct intel_crtc_scaler_state {
394#define SKL_NUM_SCALERS 2
395 struct intel_scaler scalers[SKL_NUM_SCALERS];
396
397 /*
398 * scaler_users: keeps track of users requesting scalers on this crtc.
399 *
400 * If a bit is set, a user is using a scaler.
401 * Here user can be a plane or crtc as defined below:
402 * bits 0-30 - plane (bit position is index from drm_plane_index)
403 * bit 31 - crtc
404 *
405 * Instead of creating a new index to cover planes and crtc, using
406 * existing drm_plane_index for planes which is well less than 31
407 * planes and bit 31 for crtc. This should be fine to cover all
408 * our platforms.
409 *
410 * intel_atomic_setup_scalers will setup available scalers to users
411 * requesting scalers. It will gracefully fail if request exceeds
412 * avilability.
413 */
414#define SKL_CRTC_INDEX 31
415 unsigned scaler_users;
416
417 /* scaler used by crtc for panel fitting purpose */
418 int scaler_id;
419};
420
421/* drm_mode->private_flags */
422#define I915_MODE_FLAG_INHERITED 1
423
424struct intel_pipe_wm {
425 struct intel_wm_level wm[5];
426 struct intel_wm_level raw_wm[5];
427 uint32_t linetime;
428 bool fbc_wm_enabled;
429 bool pipe_enabled;
430 bool sprites_enabled;
431 bool sprites_scaled;
432};
433
434struct skl_pipe_wm {
435 struct skl_wm_level wm[8];
436 struct skl_wm_level trans_wm;
437 uint32_t linetime;
438};
439
440struct intel_crtc_wm_state {
441 union {
442 struct {
443 /*
444 * Intermediate watermarks; these can be
445 * programmed immediately since they satisfy
446 * both the current configuration we're
447 * switching away from and the new
448 * configuration we're switching to.
449 */
450 struct intel_pipe_wm intermediate;
451
452 /*
453 * Optimal watermarks, programmed post-vblank
454 * when this state is committed.
455 */
456 struct intel_pipe_wm optimal;
457 } ilk;
458
459 struct {
460 /* gen9+ only needs 1-step wm programming */
461 struct skl_pipe_wm optimal;
462
463 /* cached plane data rate */
464 unsigned plane_data_rate[I915_MAX_PLANES];
465 unsigned plane_y_data_rate[I915_MAX_PLANES];
466
467 /* minimum block allocation */
468 uint16_t minimum_blocks[I915_MAX_PLANES];
469 uint16_t minimum_y_blocks[I915_MAX_PLANES];
470 } skl;
471 };
472
473 /*
474 * Platforms with two-step watermark programming will need to
475 * update watermark programming post-vblank to switch from the
476 * safe intermediate watermarks to the optimal final
477 * watermarks.
478 */
479 bool need_postvbl_update;
480};
481
482struct intel_crtc_state {
483 struct drm_crtc_state base;
484
485 /**
486 * quirks - bitfield with hw state readout quirks
487 *
488 * For various reasons the hw state readout code might not be able to
489 * completely faithfully read out the current state. These cases are
490 * tracked with quirk flags so that fastboot and state checker can act
491 * accordingly.
492 */
493#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
494 unsigned long quirks;
495
496 unsigned fb_bits; /* framebuffers to flip */
497 bool update_pipe; /* can a fast modeset be performed? */
498 bool disable_cxsr;
499 bool update_wm_pre, update_wm_post; /* watermarks are updated */
500 bool fb_changed; /* fb on any of the planes is changed */
501
502 /* Pipe source size (ie. panel fitter input size)
503 * All planes will be positioned inside this space,
504 * and get clipped at the edges. */
505 int pipe_src_w, pipe_src_h;
506
507 /* Whether to set up the PCH/FDI. Note that we never allow sharing
508 * between pch encoders and cpu encoders. */
509 bool has_pch_encoder;
510
511 /* Are we sending infoframes on the attached port */
512 bool has_infoframe;
513
514 /* CPU Transcoder for the pipe. Currently this can only differ from the
515 * pipe on Haswell and later (where we have a special eDP transcoder)
516 * and Broxton (where we have special DSI transcoders). */
517 enum transcoder cpu_transcoder;
518
519 /*
520 * Use reduced/limited/broadcast rbg range, compressing from the full
521 * range fed into the crtcs.
522 */
523 bool limited_color_range;
524
525 /* DP has a bunch of special case unfortunately, so mark the pipe
526 * accordingly. */
527 bool has_dp_encoder;
528
529 /* DSI has special cases */
530 bool has_dsi_encoder;
531
532 /* Bitmask of encoder types (enum intel_output_type)
533 * driven by the pipe.
534 */
535 unsigned int output_types;
536
537 /* Whether we should send NULL infoframes. Required for audio. */
538 bool has_hdmi_sink;
539
540 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
541 * has_dp_encoder is set. */
542 bool has_audio;
543
544 /*
545 * Enable dithering, used when the selected pipe bpp doesn't match the
546 * plane bpp.
547 */
548 bool dither;
549
550 /* Controls for the clock computation, to override various stages. */
551 bool clock_set;
552
553 /* SDVO TV has a bunch of special case. To make multifunction encoders
554 * work correctly, we need to track this at runtime.*/
555 bool sdvo_tv_clock;
556
557 /*
558 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
559 * required. This is set in the 2nd loop of calling encoder's
560 * ->compute_config if the first pick doesn't work out.
561 */
562 bool bw_constrained;
563
564 /* Settings for the intel dpll used on pretty much everything but
565 * haswell. */
566 struct dpll dpll;
567
568 /* Selected dpll when shared or NULL. */
569 struct intel_shared_dpll *shared_dpll;
570
571 /*
572 * - PORT_CLK_SEL for DDI ports on HSW/BDW.
573 * - enum skl_dpll on SKL
574 */
575 uint32_t ddi_pll_sel;
576
577 /* Actual register state of the dpll, for shared dpll cross-checking. */
578 struct intel_dpll_hw_state dpll_hw_state;
579
580 /* DSI PLL registers */
581 struct {
582 u32 ctrl, div;
583 } dsi_pll;
584
585 int pipe_bpp;
586 struct intel_link_m_n dp_m_n;
587
588 /* m2_n2 for eDP downclock */
589 struct intel_link_m_n dp_m2_n2;
590 bool has_drrs;
591
592 /*
593 * Frequence the dpll for the port should run at. Differs from the
594 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
595 * already multiplied by pixel_multiplier.
596 */
597 int port_clock;
598
599 /* Used by SDVO (and if we ever fix it, HDMI). */
600 unsigned pixel_multiplier;
601
602 uint8_t lane_count;
603
604 /*
605 * Used by platforms having DP/HDMI PHY with programmable lane
606 * latency optimization.
607 */
608 uint8_t lane_lat_optim_mask;
609
610 /* Panel fitter controls for gen2-gen4 + VLV */
611 struct {
612 u32 control;
613 u32 pgm_ratios;
614 u32 lvds_border_bits;
615 } gmch_pfit;
616
617 /* Panel fitter placement and size for Ironlake+ */
618 struct {
619 u32 pos;
620 u32 size;
621 bool enabled;
622 bool force_thru;
623 } pch_pfit;
624
625 /* FDI configuration, only valid if has_pch_encoder is set. */
626 int fdi_lanes;
627 struct intel_link_m_n fdi_m_n;
628
629 bool ips_enabled;
630
631 bool enable_fbc;
632
633 bool double_wide;
634
635 bool dp_encoder_is_mst;
636 int pbn;
637
638 struct intel_crtc_scaler_state scaler_state;
639
640 /* w/a for waiting 2 vblanks during crtc enable */
641 enum pipe hsw_workaround_pipe;
642
643 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
644 bool disable_lp_wm;
645
646 struct intel_crtc_wm_state wm;
647
648 /* Gamma mode programmed on the pipe */
649 uint32_t gamma_mode;
650};
651
652struct vlv_wm_state {
653 struct vlv_pipe_wm wm[3];
654 struct vlv_sr_wm sr[3];
655 uint8_t num_active_planes;
656 uint8_t num_levels;
657 uint8_t level;
658 bool cxsr;
659};
660
661struct intel_crtc {
662 struct drm_crtc base;
663 enum pipe pipe;
664 enum plane plane;
665 u8 lut_r[256], lut_g[256], lut_b[256];
666 /*
667 * Whether the crtc and the connected output pipeline is active. Implies
668 * that crtc->enabled is set, i.e. the current mode configuration has
669 * some outputs connected to this crtc.
670 */
671 bool active;
672 unsigned long enabled_power_domains;
673 bool lowfreq_avail;
674 struct intel_overlay *overlay;
675 struct intel_flip_work *flip_work;
676
677 atomic_t unpin_work_count;
678
679 /* Display surface base address adjustement for pageflips. Note that on
680 * gen4+ this only adjusts up to a tile, offsets within a tile are
681 * handled in the hw itself (with the TILEOFF register). */
682 u32 dspaddr_offset;
683 int adjusted_x;
684 int adjusted_y;
685
686 uint32_t cursor_addr;
687 uint32_t cursor_cntl;
688 uint32_t cursor_size;
689 uint32_t cursor_base;
690
691 struct intel_crtc_state *config;
692
693 /* reset counter value when the last flip was submitted */
694 unsigned int reset_counter;
695
696 /* Access to these should be protected by dev_priv->irq_lock. */
697 bool cpu_fifo_underrun_disabled;
698 bool pch_fifo_underrun_disabled;
699
700 /* per-pipe watermark state */
701 struct {
702 /* watermarks currently being used */
703 union {
704 struct intel_pipe_wm ilk;
705 struct skl_pipe_wm skl;
706 } active;
707
708 /* allow CxSR on this pipe */
709 bool cxsr_allowed;
710 } wm;
711
712 int scanline_offset;
713
714 struct {
715 unsigned start_vbl_count;
716 ktime_t start_vbl_time;
717 int min_vbl, max_vbl;
718 int scanline_start;
719 } debug;
720
721 /* scalers available on this crtc */
722 int num_scalers;
723
724 struct vlv_wm_state wm_state;
725};
726
727struct intel_plane_wm_parameters {
728 uint32_t horiz_pixels;
729 uint32_t vert_pixels;
730 /*
731 * For packed pixel formats:
732 * bytes_per_pixel - holds bytes per pixel
733 * For planar pixel formats:
734 * bytes_per_pixel - holds bytes per pixel for uv-plane
735 * y_bytes_per_pixel - holds bytes per pixel for y-plane
736 */
737 uint8_t bytes_per_pixel;
738 uint8_t y_bytes_per_pixel;
739 bool enabled;
740 bool scaled;
741 u64 tiling;
742 unsigned int rotation;
743 uint16_t fifo_size;
744};
745
746struct intel_plane {
747 struct drm_plane base;
748 int plane;
749 enum pipe pipe;
750 bool can_scale;
751 int max_downscale;
752 uint32_t frontbuffer_bit;
753
754 /* Since we need to change the watermarks before/after
755 * enabling/disabling the planes, we need to store the parameters here
756 * as the other pieces of the struct may not reflect the values we want
757 * for the watermark calculations. Currently only Haswell uses this.
758 */
759 struct intel_plane_wm_parameters wm;
760
761 /*
762 * NOTE: Do not place new plane state fields here (e.g., when adding
763 * new plane properties). New runtime state should now be placed in
764 * the intel_plane_state structure and accessed via plane_state.
765 */
766
767 void (*update_plane)(struct drm_plane *plane,
768 const struct intel_crtc_state *crtc_state,
769 const struct intel_plane_state *plane_state);
770 void (*disable_plane)(struct drm_plane *plane,
771 struct drm_crtc *crtc);
772 int (*check_plane)(struct drm_plane *plane,
773 struct intel_crtc_state *crtc_state,
774 struct intel_plane_state *state);
775};
776
777struct intel_watermark_params {
778 unsigned long fifo_size;
779 unsigned long max_wm;
780 unsigned long default_wm;
781 unsigned long guard_size;
782 unsigned long cacheline_size;
783};
784
785struct cxsr_latency {
786 int is_desktop;
787 int is_ddr3;
788 unsigned long fsb_freq;
789 unsigned long mem_freq;
790 unsigned long display_sr;
791 unsigned long display_hpll_disable;
792 unsigned long cursor_sr;
793 unsigned long cursor_hpll_disable;
794};
795
796#define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
797#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
798#define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
799#define to_intel_connector(x) container_of(x, struct intel_connector, base)
800#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
801#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
802#define to_intel_plane(x) container_of(x, struct intel_plane, base)
803#define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
804#define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
805
806struct intel_hdmi {
807 i915_reg_t hdmi_reg;
808 int ddc_bus;
809 struct {
810 enum drm_dp_dual_mode_type type;
811 int max_tmds_clock;
812 } dp_dual_mode;
813 bool limited_color_range;
814 bool color_range_auto;
815 bool has_hdmi_sink;
816 bool has_audio;
817 enum hdmi_force_audio force_audio;
818 bool rgb_quant_range_selectable;
819 enum hdmi_picture_aspect aspect_ratio;
820 struct intel_connector *attached_connector;
821 void (*write_infoframe)(struct drm_encoder *encoder,
822 enum hdmi_infoframe_type type,
823 const void *frame, ssize_t len);
824 void (*set_infoframes)(struct drm_encoder *encoder,
825 bool enable,
826 const struct drm_display_mode *adjusted_mode);
827 bool (*infoframe_enabled)(struct drm_encoder *encoder,
828 const struct intel_crtc_state *pipe_config);
829};
830
831struct intel_dp_mst_encoder;
832#define DP_MAX_DOWNSTREAM_PORTS 0x10
833
834/*
835 * enum link_m_n_set:
836 * When platform provides two set of M_N registers for dp, we can
837 * program them and switch between them incase of DRRS.
838 * But When only one such register is provided, we have to program the
839 * required divider value on that registers itself based on the DRRS state.
840 *
841 * M1_N1 : Program dp_m_n on M1_N1 registers
842 * dp_m2_n2 on M2_N2 registers (If supported)
843 *
844 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
845 * M2_N2 registers are not supported
846 */
847
848enum link_m_n_set {
849 /* Sets the m1_n1 and m2_n2 */
850 M1_N1 = 0,
851 M2_N2
852};
853
854struct intel_dp {
855 i915_reg_t output_reg;
856 i915_reg_t aux_ch_ctl_reg;
857 i915_reg_t aux_ch_data_reg[5];
858 uint32_t DP;
859 int link_rate;
860 uint8_t lane_count;
861 uint8_t sink_count;
862 bool has_audio;
863 bool detect_done;
864 enum hdmi_force_audio force_audio;
865 bool limited_color_range;
866 bool color_range_auto;
867 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
868 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
869 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
870 uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
871 /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
872 uint8_t num_sink_rates;
873 int sink_rates[DP_MAX_SUPPORTED_RATES];
874 struct drm_dp_aux aux;
875 uint8_t train_set[4];
876 int panel_power_up_delay;
877 int panel_power_down_delay;
878 int panel_power_cycle_delay;
879 int backlight_on_delay;
880 int backlight_off_delay;
881 struct delayed_work panel_vdd_work;
882 bool want_panel_vdd;
883 unsigned long last_power_on;
884 unsigned long last_backlight_off;
885 ktime_t panel_power_off_time;
886
887 struct notifier_block edp_notifier;
888
889 /*
890 * Pipe whose power sequencer is currently locked into
891 * this port. Only relevant on VLV/CHV.
892 */
893 enum pipe pps_pipe;
894 /*
895 * Set if the sequencer may be reset due to a power transition,
896 * requiring a reinitialization. Only relevant on BXT.
897 */
898 bool pps_reset;
899 struct edp_power_seq pps_delays;
900
901 bool can_mst; /* this port supports mst */
902 bool is_mst;
903 int active_mst_links;
904 /* connector directly attached - won't be use for modeset in mst world */
905 struct intel_connector *attached_connector;
906
907 /* mst connector list */
908 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
909 struct drm_dp_mst_topology_mgr mst_mgr;
910
911 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
912 /*
913 * This function returns the value we have to program the AUX_CTL
914 * register with to kick off an AUX transaction.
915 */
916 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
917 bool has_aux_irq,
918 int send_bytes,
919 uint32_t aux_clock_divider);
920
921 /* This is called before a link training is starterd */
922 void (*prepare_link_retrain)(struct intel_dp *intel_dp);
923
924 /* Displayport compliance testing */
925 unsigned long compliance_test_type;
926 unsigned long compliance_test_data;
927 bool compliance_test_active;
928};
929
930struct intel_digital_port {
931 struct intel_encoder base;
932 enum port port;
933 u32 saved_port_bits;
934 struct intel_dp dp;
935 struct intel_hdmi hdmi;
936 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
937 bool release_cl2_override;
938 uint8_t max_lanes;
939 /* for communication with audio component; protected by av_mutex */
940 const struct drm_connector *audio_connector;
941};
942
943struct intel_dp_mst_encoder {
944 struct intel_encoder base;
945 enum pipe pipe;
946 struct intel_digital_port *primary;
947 struct intel_connector *connector;
948};
949
950static inline enum dpio_channel
951vlv_dport_to_channel(struct intel_digital_port *dport)
952{
953 switch (dport->port) {
954 case PORT_B:
955 case PORT_D:
956 return DPIO_CH0;
957 case PORT_C:
958 return DPIO_CH1;
959 default:
960 BUG();
961 }
962}
963
964static inline enum dpio_phy
965vlv_dport_to_phy(struct intel_digital_port *dport)
966{
967 switch (dport->port) {
968 case PORT_B:
969 case PORT_C:
970 return DPIO_PHY0;
971 case PORT_D:
972 return DPIO_PHY1;
973 default:
974 BUG();
975 }
976}
977
978static inline enum dpio_channel
979vlv_pipe_to_channel(enum pipe pipe)
980{
981 switch (pipe) {
982 case PIPE_A:
983 case PIPE_C:
984 return DPIO_CH0;
985 case PIPE_B:
986 return DPIO_CH1;
987 default:
988 BUG();
989 }
990}
991
992static inline struct drm_crtc *
993intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
994{
995 struct drm_i915_private *dev_priv = to_i915(dev);
996 return dev_priv->pipe_to_crtc_mapping[pipe];
997}
998
999static inline struct drm_crtc *
1000intel_get_crtc_for_plane(struct drm_device *dev, int plane)
1001{
1002 struct drm_i915_private *dev_priv = to_i915(dev);
1003 return dev_priv->plane_to_crtc_mapping[plane];
1004}
1005
1006struct intel_flip_work {
1007 struct work_struct unpin_work;
1008 struct work_struct mmio_work;
1009
1010 struct drm_crtc *crtc;
1011 struct drm_framebuffer *old_fb;
1012 struct drm_i915_gem_object *pending_flip_obj;
1013 struct drm_pending_vblank_event *event;
1014 atomic_t pending;
1015 u32 flip_count;
1016 u32 gtt_offset;
1017 struct drm_i915_gem_request *flip_queued_req;
1018 u32 flip_queued_vblank;
1019 u32 flip_ready_vblank;
1020 unsigned int rotation;
1021};
1022
1023struct intel_load_detect_pipe {
1024 struct drm_atomic_state *restore_state;
1025};
1026
1027static inline struct intel_encoder *
1028intel_attached_encoder(struct drm_connector *connector)
1029{
1030 return to_intel_connector(connector)->encoder;
1031}
1032
1033static inline struct intel_digital_port *
1034enc_to_dig_port(struct drm_encoder *encoder)
1035{
1036 return container_of(encoder, struct intel_digital_port, base.base);
1037}
1038
1039static inline struct intel_dp_mst_encoder *
1040enc_to_mst(struct drm_encoder *encoder)
1041{
1042 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1043}
1044
1045static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1046{
1047 return &enc_to_dig_port(encoder)->dp;
1048}
1049
1050static inline struct intel_digital_port *
1051dp_to_dig_port(struct intel_dp *intel_dp)
1052{
1053 return container_of(intel_dp, struct intel_digital_port, dp);
1054}
1055
1056static inline struct intel_digital_port *
1057hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1058{
1059 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1060}
1061
1062/*
1063 * Returns the number of planes for this pipe, ie the number of sprites + 1
1064 * (primary plane). This doesn't count the cursor plane then.
1065 */
1066static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
1067{
1068 return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
1069}
1070
1071/* intel_fifo_underrun.c */
1072bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1073 enum pipe pipe, bool enable);
1074bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1075 enum transcoder pch_transcoder,
1076 bool enable);
1077void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1078 enum pipe pipe);
1079void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1080 enum transcoder pch_transcoder);
1081void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1082void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1083
1084/* i915_irq.c */
1085void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1086void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1087void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1088void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1089void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1090void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1091void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1092u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
1093void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1094void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1095static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1096{
1097 /*
1098 * We only use drm_irq_uninstall() at unload and VT switch, so
1099 * this is the only thing we need to check.
1100 */
1101 return dev_priv->pm.irqs_enabled;
1102}
1103
1104int intel_get_crtc_scanline(struct intel_crtc *crtc);
1105void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1106 unsigned int pipe_mask);
1107void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1108 unsigned int pipe_mask);
1109
1110/* intel_crt.c */
1111void intel_crt_init(struct drm_device *dev);
1112
1113
1114/* intel_ddi.c */
1115void intel_ddi_clk_select(struct intel_encoder *encoder,
1116 const struct intel_crtc_state *pipe_config);
1117void intel_prepare_ddi_buffer(struct intel_encoder *encoder);
1118void hsw_fdi_link_train(struct drm_crtc *crtc);
1119void intel_ddi_init(struct drm_device *dev, enum port port);
1120enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1121bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1122void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
1123void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1124 enum transcoder cpu_transcoder);
1125void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
1126void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
1127bool intel_ddi_pll_select(struct intel_crtc *crtc,
1128 struct intel_crtc_state *crtc_state);
1129void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
1130void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1131bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1132void intel_ddi_fdi_disable(struct drm_crtc *crtc);
1133void intel_ddi_get_config(struct intel_encoder *encoder,
1134 struct intel_crtc_state *pipe_config);
1135struct intel_encoder *
1136intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1137
1138void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1139void intel_ddi_clock_get(struct intel_encoder *encoder,
1140 struct intel_crtc_state *pipe_config);
1141void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
1142uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1143
1144/* intel_frontbuffer.c */
1145void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
1146 enum fb_op_origin origin);
1147void intel_frontbuffer_flip_prepare(struct drm_device *dev,
1148 unsigned frontbuffer_bits);
1149void intel_frontbuffer_flip_complete(struct drm_device *dev,
1150 unsigned frontbuffer_bits);
1151void intel_frontbuffer_flip(struct drm_device *dev,
1152 unsigned frontbuffer_bits);
1153unsigned int intel_fb_align_height(struct drm_device *dev,
1154 unsigned int height,
1155 uint32_t pixel_format,
1156 uint64_t fb_format_modifier);
1157void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire,
1158 enum fb_op_origin origin);
1159u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
1160 uint64_t fb_modifier, uint32_t pixel_format);
1161
1162/* intel_audio.c */
1163void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1164void intel_audio_codec_enable(struct intel_encoder *encoder);
1165void intel_audio_codec_disable(struct intel_encoder *encoder);
1166void i915_audio_component_init(struct drm_i915_private *dev_priv);
1167void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1168
1169/* intel_display.c */
1170void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco);
1171void intel_update_rawclk(struct drm_i915_private *dev_priv);
1172int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1173 const char *name, u32 reg, int ref_freq);
1174extern const struct drm_plane_funcs intel_plane_funcs;
1175void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1176unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1177bool intel_has_pending_fb_unpin(struct drm_device *dev);
1178void intel_mark_busy(struct drm_i915_private *dev_priv);
1179void intel_mark_idle(struct drm_i915_private *dev_priv);
1180void intel_crtc_restore_mode(struct drm_crtc *crtc);
1181int intel_display_suspend(struct drm_device *dev);
1182void intel_encoder_destroy(struct drm_encoder *encoder);
1183int intel_connector_init(struct intel_connector *);
1184struct intel_connector *intel_connector_alloc(void);
1185bool intel_connector_get_hw_state(struct intel_connector *connector);
1186void intel_connector_attach_encoder(struct intel_connector *connector,
1187 struct intel_encoder *encoder);
1188struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1189 struct drm_crtc *crtc);
1190enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1191int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1192 struct drm_file *file_priv);
1193enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1194 enum pipe pipe);
1195bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
1196static inline void
1197intel_wait_for_vblank(struct drm_device *dev, int pipe)
1198{
1199 drm_wait_one_vblank(dev, pipe);
1200}
1201static inline void
1202intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe)
1203{
1204 const struct intel_crtc *crtc =
1205 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
1206
1207 if (crtc->active)
1208 intel_wait_for_vblank(dev, pipe);
1209}
1210
1211u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1212
1213int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1214void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1215 struct intel_digital_port *dport,
1216 unsigned int expected_mask);
1217bool intel_get_load_detect_pipe(struct drm_connector *connector,
1218 struct drm_display_mode *mode,
1219 struct intel_load_detect_pipe *old,
1220 struct drm_modeset_acquire_ctx *ctx);
1221void intel_release_load_detect_pipe(struct drm_connector *connector,
1222 struct intel_load_detect_pipe *old,
1223 struct drm_modeset_acquire_ctx *ctx);
1224int intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1225 unsigned int rotation);
1226void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1227struct drm_framebuffer *
1228__intel_framebuffer_create(struct drm_device *dev,
1229 struct drm_mode_fb_cmd2 *mode_cmd,
1230 struct drm_i915_gem_object *obj);
1231void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe);
1232void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe);
1233void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe);
1234int intel_prepare_plane_fb(struct drm_plane *plane,
1235 const struct drm_plane_state *new_state);
1236void intel_cleanup_plane_fb(struct drm_plane *plane,
1237 const struct drm_plane_state *old_state);
1238int intel_plane_atomic_get_property(struct drm_plane *plane,
1239 const struct drm_plane_state *state,
1240 struct drm_property *property,
1241 uint64_t *val);
1242int intel_plane_atomic_set_property(struct drm_plane *plane,
1243 struct drm_plane_state *state,
1244 struct drm_property *property,
1245 uint64_t val);
1246int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1247 struct drm_plane_state *plane_state);
1248
1249unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
1250 uint64_t fb_modifier, unsigned int cpp);
1251
1252static inline bool
1253intel_rotation_90_or_270(unsigned int rotation)
1254{
1255 return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
1256}
1257
1258void intel_create_rotation_property(struct drm_device *dev,
1259 struct intel_plane *plane);
1260
1261void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1262 enum pipe pipe);
1263
1264int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1265 const struct dpll *dpll);
1266void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1267int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1268
1269/* modesetting asserts */
1270void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1271 enum pipe pipe);
1272void assert_pll(struct drm_i915_private *dev_priv,
1273 enum pipe pipe, bool state);
1274#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1275#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1276void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1277#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1278#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1279void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1280 enum pipe pipe, bool state);
1281#define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1282#define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1283void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1284#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1285#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1286u32 intel_compute_tile_offset(int *x, int *y,
1287 const struct drm_framebuffer *fb, int plane,
1288 unsigned int pitch,
1289 unsigned int rotation);
1290void intel_prepare_reset(struct drm_i915_private *dev_priv);
1291void intel_finish_reset(struct drm_i915_private *dev_priv);
1292void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1293void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1294void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1295void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1296void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
1297void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
1298bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
1299 enum dpio_phy phy);
1300bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
1301 enum dpio_phy phy);
1302void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1303void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1304void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1305void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1306void skl_init_cdclk(struct drm_i915_private *dev_priv);
1307void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1308unsigned int skl_cdclk_get_vco(unsigned int freq);
1309void skl_enable_dc6(struct drm_i915_private *dev_priv);
1310void skl_disable_dc6(struct drm_i915_private *dev_priv);
1311void intel_dp_get_m_n(struct intel_crtc *crtc,
1312 struct intel_crtc_state *pipe_config);
1313void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1314int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1315bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1316 struct dpll *best_clock);
1317int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1318
1319bool intel_crtc_active(struct drm_crtc *crtc);
1320void hsw_enable_ips(struct intel_crtc *crtc);
1321void hsw_disable_ips(struct intel_crtc *crtc);
1322enum intel_display_power_domain
1323intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1324enum intel_display_power_domain
1325intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
1326void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1327 struct intel_crtc_state *pipe_config);
1328
1329int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1330int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1331
1332u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
1333 struct drm_i915_gem_object *obj,
1334 unsigned int plane);
1335
1336u32 skl_plane_ctl_format(uint32_t pixel_format);
1337u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1338u32 skl_plane_ctl_rotation(unsigned int rotation);
1339
1340/* intel_csr.c */
1341void intel_csr_ucode_init(struct drm_i915_private *);
1342void intel_csr_load_program(struct drm_i915_private *);
1343void intel_csr_ucode_fini(struct drm_i915_private *);
1344void intel_csr_ucode_suspend(struct drm_i915_private *);
1345void intel_csr_ucode_resume(struct drm_i915_private *);
1346
1347/* intel_dp.c */
1348bool intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port);
1349bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1350 struct intel_connector *intel_connector);
1351void intel_dp_set_link_params(struct intel_dp *intel_dp,
1352 const struct intel_crtc_state *pipe_config);
1353void intel_dp_start_link_train(struct intel_dp *intel_dp);
1354void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1355void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1356void intel_dp_encoder_reset(struct drm_encoder *encoder);
1357void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1358void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1359int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1360bool intel_dp_compute_config(struct intel_encoder *encoder,
1361 struct intel_crtc_state *pipe_config);
1362bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1363enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1364 bool long_hpd);
1365void intel_edp_backlight_on(struct intel_dp *intel_dp);
1366void intel_edp_backlight_off(struct intel_dp *intel_dp);
1367void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1368void intel_edp_panel_on(struct intel_dp *intel_dp);
1369void intel_edp_panel_off(struct intel_dp *intel_dp);
1370void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1371void intel_dp_mst_suspend(struct drm_device *dev);
1372void intel_dp_mst_resume(struct drm_device *dev);
1373int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1374int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1375void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1376void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1377uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1378void intel_plane_destroy(struct drm_plane *plane);
1379void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1380void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1381void intel_edp_drrs_invalidate(struct drm_device *dev,
1382 unsigned frontbuffer_bits);
1383void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1384bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
1385 struct intel_digital_port *port);
1386
1387void
1388intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1389 uint8_t dp_train_pat);
1390void
1391intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1392void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1393uint8_t
1394intel_dp_voltage_max(struct intel_dp *intel_dp);
1395uint8_t
1396intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1397void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1398 uint8_t *link_bw, uint8_t *rate_select);
1399bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1400bool
1401intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1402
1403static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1404{
1405 return ~((1 << lane_count) - 1) & 0xf;
1406}
1407
1408/* intel_dp_aux_backlight.c */
1409int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1410
1411/* intel_dp_mst.c */
1412int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1413void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1414/* intel_dsi.c */
1415void intel_dsi_init(struct drm_device *dev);
1416
1417/* intel_dsi_dcs_backlight.c */
1418int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1419
1420/* intel_dvo.c */
1421void intel_dvo_init(struct drm_device *dev);
1422
1423
1424/* legacy fbdev emulation in intel_fbdev.c */
1425#ifdef CONFIG_DRM_FBDEV_EMULATION
1426extern int intel_fbdev_init(struct drm_device *dev);
1427extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1428extern void intel_fbdev_fini(struct drm_device *dev);
1429extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1430extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1431extern void intel_fbdev_restore_mode(struct drm_device *dev);
1432#else
1433static inline int intel_fbdev_init(struct drm_device *dev)
1434{
1435 return 0;
1436}
1437
1438static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1439{
1440}
1441
1442static inline void intel_fbdev_fini(struct drm_device *dev)
1443{
1444}
1445
1446static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1447{
1448}
1449
1450static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1451{
1452}
1453#endif
1454
1455/* intel_fbc.c */
1456void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1457 struct drm_atomic_state *state);
1458bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1459void intel_fbc_pre_update(struct intel_crtc *crtc,
1460 struct intel_crtc_state *crtc_state,
1461 struct intel_plane_state *plane_state);
1462void intel_fbc_post_update(struct intel_crtc *crtc);
1463void intel_fbc_init(struct drm_i915_private *dev_priv);
1464void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1465void intel_fbc_enable(struct intel_crtc *crtc,
1466 struct intel_crtc_state *crtc_state,
1467 struct intel_plane_state *plane_state);
1468void intel_fbc_disable(struct intel_crtc *crtc);
1469void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1470void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1471 unsigned int frontbuffer_bits,
1472 enum fb_op_origin origin);
1473void intel_fbc_flush(struct drm_i915_private *dev_priv,
1474 unsigned int frontbuffer_bits, enum fb_op_origin origin);
1475void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1476
1477/* intel_hdmi.c */
1478void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port);
1479void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1480 struct intel_connector *intel_connector);
1481struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1482bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1483 struct intel_crtc_state *pipe_config);
1484void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1485
1486
1487/* intel_lvds.c */
1488void intel_lvds_init(struct drm_device *dev);
1489struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1490bool intel_is_dual_link_lvds(struct drm_device *dev);
1491
1492
1493/* intel_modes.c */
1494int intel_connector_update_modes(struct drm_connector *connector,
1495 struct edid *edid);
1496int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1497void intel_attach_force_audio_property(struct drm_connector *connector);
1498void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1499void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1500
1501
1502/* intel_overlay.c */
1503void intel_setup_overlay(struct drm_i915_private *dev_priv);
1504void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1505int intel_overlay_switch_off(struct intel_overlay *overlay);
1506int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1507 struct drm_file *file_priv);
1508int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1509 struct drm_file *file_priv);
1510void intel_overlay_reset(struct drm_i915_private *dev_priv);
1511
1512
1513/* intel_panel.c */
1514int intel_panel_init(struct intel_panel *panel,
1515 struct drm_display_mode *fixed_mode,
1516 struct drm_display_mode *downclock_mode);
1517void intel_panel_fini(struct intel_panel *panel);
1518void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1519 struct drm_display_mode *adjusted_mode);
1520void intel_pch_panel_fitting(struct intel_crtc *crtc,
1521 struct intel_crtc_state *pipe_config,
1522 int fitting_mode);
1523void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1524 struct intel_crtc_state *pipe_config,
1525 int fitting_mode);
1526void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1527 u32 level, u32 max);
1528int intel_panel_setup_backlight(struct drm_connector *connector,
1529 enum pipe pipe);
1530void intel_panel_enable_backlight(struct intel_connector *connector);
1531void intel_panel_disable_backlight(struct intel_connector *connector);
1532void intel_panel_destroy_backlight(struct drm_connector *connector);
1533enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1534extern struct drm_display_mode *intel_find_panel_downclock(
1535 struct drm_device *dev,
1536 struct drm_display_mode *fixed_mode,
1537 struct drm_connector *connector);
1538
1539#if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1540int intel_backlight_device_register(struct intel_connector *connector);
1541void intel_backlight_device_unregister(struct intel_connector *connector);
1542#else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1543static int intel_backlight_device_register(struct intel_connector *connector)
1544{
1545 return 0;
1546}
1547static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1548{
1549}
1550#endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1551
1552
1553/* intel_psr.c */
1554void intel_psr_enable(struct intel_dp *intel_dp);
1555void intel_psr_disable(struct intel_dp *intel_dp);
1556void intel_psr_invalidate(struct drm_device *dev,
1557 unsigned frontbuffer_bits);
1558void intel_psr_flush(struct drm_device *dev,
1559 unsigned frontbuffer_bits,
1560 enum fb_op_origin origin);
1561void intel_psr_init(struct drm_device *dev);
1562void intel_psr_single_frame_update(struct drm_device *dev,
1563 unsigned frontbuffer_bits);
1564
1565/* intel_runtime_pm.c */
1566int intel_power_domains_init(struct drm_i915_private *);
1567void intel_power_domains_fini(struct drm_i915_private *);
1568void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1569void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1570void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1571void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1572void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1573const char *
1574intel_display_power_domain_str(enum intel_display_power_domain domain);
1575
1576bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1577 enum intel_display_power_domain domain);
1578bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1579 enum intel_display_power_domain domain);
1580void intel_display_power_get(struct drm_i915_private *dev_priv,
1581 enum intel_display_power_domain domain);
1582bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1583 enum intel_display_power_domain domain);
1584void intel_display_power_put(struct drm_i915_private *dev_priv,
1585 enum intel_display_power_domain domain);
1586
1587static inline void
1588assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1589{
1590 WARN_ONCE(dev_priv->pm.suspended,
1591 "Device suspended during HW access\n");
1592}
1593
1594static inline void
1595assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1596{
1597 assert_rpm_device_not_suspended(dev_priv);
1598 /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1599 * too much noise. */
1600 if (!atomic_read(&dev_priv->pm.wakeref_count))
1601 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1602}
1603
1604static inline int
1605assert_rpm_atomic_begin(struct drm_i915_private *dev_priv)
1606{
1607 int seq = atomic_read(&dev_priv->pm.atomic_seq);
1608
1609 assert_rpm_wakelock_held(dev_priv);
1610
1611 return seq;
1612}
1613
1614static inline void
1615assert_rpm_atomic_end(struct drm_i915_private *dev_priv, int begin_seq)
1616{
1617 WARN_ONCE(atomic_read(&dev_priv->pm.atomic_seq) != begin_seq,
1618 "HW access outside of RPM atomic section\n");
1619}
1620
1621/**
1622 * disable_rpm_wakeref_asserts - disable the RPM assert checks
1623 * @dev_priv: i915 device instance
1624 *
1625 * This function disable asserts that check if we hold an RPM wakelock
1626 * reference, while keeping the device-not-suspended checks still enabled.
1627 * It's meant to be used only in special circumstances where our rule about
1628 * the wakelock refcount wrt. the device power state doesn't hold. According
1629 * to this rule at any point where we access the HW or want to keep the HW in
1630 * an active state we must hold an RPM wakelock reference acquired via one of
1631 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1632 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1633 * forcewake release timer, and the GPU RPS and hangcheck works. All other
1634 * users should avoid using this function.
1635 *
1636 * Any calls to this function must have a symmetric call to
1637 * enable_rpm_wakeref_asserts().
1638 */
1639static inline void
1640disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1641{
1642 atomic_inc(&dev_priv->pm.wakeref_count);
1643}
1644
1645/**
1646 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1647 * @dev_priv: i915 device instance
1648 *
1649 * This function re-enables the RPM assert checks after disabling them with
1650 * disable_rpm_wakeref_asserts. It's meant to be used only in special
1651 * circumstances otherwise its use should be avoided.
1652 *
1653 * Any calls to this function must have a symmetric call to
1654 * disable_rpm_wakeref_asserts().
1655 */
1656static inline void
1657enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1658{
1659 atomic_dec(&dev_priv->pm.wakeref_count);
1660}
1661
1662/* TODO: convert users of these to rely instead on proper RPM refcounting */
1663#define DISABLE_RPM_WAKEREF_ASSERTS(dev_priv) \
1664 disable_rpm_wakeref_asserts(dev_priv)
1665
1666#define ENABLE_RPM_WAKEREF_ASSERTS(dev_priv) \
1667 enable_rpm_wakeref_asserts(dev_priv)
1668
1669void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1670bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1671void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1672void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1673
1674void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1675
1676void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1677 bool override, unsigned int mask);
1678bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1679 enum dpio_channel ch, bool override);
1680
1681
1682/* intel_pm.c */
1683void intel_init_clock_gating(struct drm_device *dev);
1684void intel_suspend_hw(struct drm_device *dev);
1685int ilk_wm_max_level(const struct drm_device *dev);
1686void intel_update_watermarks(struct drm_crtc *crtc);
1687void intel_init_pm(struct drm_device *dev);
1688void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1689void intel_pm_setup(struct drm_device *dev);
1690void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1691void intel_gpu_ips_teardown(void);
1692void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1693void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1694void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1695void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1696void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1697void intel_reset_gt_powersave(struct drm_i915_private *dev_priv);
1698void gen6_update_ring_freq(struct drm_i915_private *dev_priv);
1699void gen6_rps_busy(struct drm_i915_private *dev_priv);
1700void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1701void gen6_rps_idle(struct drm_i915_private *dev_priv);
1702void gen6_rps_boost(struct drm_i915_private *dev_priv,
1703 struct intel_rps_client *rps,
1704 unsigned long submitted);
1705void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
1706void vlv_wm_get_hw_state(struct drm_device *dev);
1707void ilk_wm_get_hw_state(struct drm_device *dev);
1708void skl_wm_get_hw_state(struct drm_device *dev);
1709void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1710 struct skl_ddb_allocation *ddb /* out */);
1711uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1712bool ilk_disable_lp_wm(struct drm_device *dev);
1713int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
1714static inline int intel_enable_rc6(void)
1715{
1716 return i915.enable_rc6;
1717}
1718
1719/* intel_sdvo.c */
1720bool intel_sdvo_init(struct drm_device *dev,
1721 i915_reg_t reg, enum port port);
1722
1723
1724/* intel_sprite.c */
1725int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1726int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1727 struct drm_file *file_priv);
1728void intel_pipe_update_start(struct intel_crtc *crtc);
1729void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work);
1730
1731/* intel_tv.c */
1732void intel_tv_init(struct drm_device *dev);
1733
1734/* intel_atomic.c */
1735int intel_connector_atomic_get_property(struct drm_connector *connector,
1736 const struct drm_connector_state *state,
1737 struct drm_property *property,
1738 uint64_t *val);
1739struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1740void intel_crtc_destroy_state(struct drm_crtc *crtc,
1741 struct drm_crtc_state *state);
1742struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1743void intel_atomic_state_clear(struct drm_atomic_state *);
1744struct intel_shared_dpll_config *
1745intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1746
1747static inline struct intel_crtc_state *
1748intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1749 struct intel_crtc *crtc)
1750{
1751 struct drm_crtc_state *crtc_state;
1752 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1753 if (IS_ERR(crtc_state))
1754 return ERR_CAST(crtc_state);
1755
1756 return to_intel_crtc_state(crtc_state);
1757}
1758
1759static inline struct intel_plane_state *
1760intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1761 struct intel_plane *plane)
1762{
1763 struct drm_plane_state *plane_state;
1764
1765 plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1766
1767 return to_intel_plane_state(plane_state);
1768}
1769
1770int intel_atomic_setup_scalers(struct drm_device *dev,
1771 struct intel_crtc *intel_crtc,
1772 struct intel_crtc_state *crtc_state);
1773
1774/* intel_atomic_plane.c */
1775struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1776struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1777void intel_plane_destroy_state(struct drm_plane *plane,
1778 struct drm_plane_state *state);
1779extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1780
1781/* intel_color.c */
1782void intel_color_init(struct drm_crtc *crtc);
1783int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
1784void intel_color_set_csc(struct drm_crtc_state *crtc_state);
1785void intel_color_load_luts(struct drm_crtc_state *crtc_state);
1786
1787#endif /* __INTEL_DRV_H__ */
Linux kernel - Deliverables
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