| 1 | /* |
| 2 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> |
| 3 | * Copyright (c) 2007-2008 Intel Corporation |
| 4 | * Jesse Barnes <jesse.barnes@intel.com> |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice (including the next |
| 14 | * paragraph) shall be included in all copies or substantial portions of the |
| 15 | * Software. |
| 16 | * |
| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 23 | * IN THE SOFTWARE. |
| 24 | */ |
| 25 | #ifndef __INTEL_DRV_H__ |
| 26 | #define __INTEL_DRV_H__ |
| 27 | |
| 28 | #include <linux/async.h> |
| 29 | #include <linux/i2c.h> |
| 30 | #include <linux/hdmi.h> |
| 31 | #include <drm/i915_drm.h> |
| 32 | #include "i915_drv.h" |
| 33 | #include <drm/drm_crtc.h> |
| 34 | #include <drm/drm_crtc_helper.h> |
| 35 | #include <drm/drm_fb_helper.h> |
| 36 | #include <drm/drm_dp_dual_mode_helper.h> |
| 37 | #include <drm/drm_dp_mst_helper.h> |
| 38 | #include <drm/drm_rect.h> |
| 39 | #include <drm/drm_atomic.h> |
| 40 | |
| 41 | /** |
| 42 | * _wait_for - magic (register) wait macro |
| 43 | * |
| 44 | * Does the right thing for modeset paths when run under kdgb or similar atomic |
| 45 | * contexts. Note that it's important that we check the condition again after |
| 46 | * having timed out, since the timeout could be due to preemption or similar and |
| 47 | * we've never had a chance to check the condition before the timeout. |
| 48 | * |
| 49 | * TODO: When modesetting has fully transitioned to atomic, the below |
| 50 | * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts |
| 51 | * added. |
| 52 | */ |
| 53 | #define _wait_for(COND, US, W) ({ \ |
| 54 | unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1; \ |
| 55 | int ret__ = 0; \ |
| 56 | while (!(COND)) { \ |
| 57 | if (time_after(jiffies, timeout__)) { \ |
| 58 | if (!(COND)) \ |
| 59 | ret__ = -ETIMEDOUT; \ |
| 60 | break; \ |
| 61 | } \ |
| 62 | if ((W) && drm_can_sleep()) { \ |
| 63 | usleep_range((W), (W)*2); \ |
| 64 | } else { \ |
| 65 | cpu_relax(); \ |
| 66 | } \ |
| 67 | } \ |
| 68 | ret__; \ |
| 69 | }) |
| 70 | |
| 71 | #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 1000) |
| 72 | #define wait_for_us(COND, US) _wait_for((COND), (US), 1) |
| 73 | |
| 74 | /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */ |
| 75 | #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT) |
| 76 | # define _WAIT_FOR_ATOMIC_CHECK WARN_ON_ONCE(!in_atomic()) |
| 77 | #else |
| 78 | # define _WAIT_FOR_ATOMIC_CHECK do { } while (0) |
| 79 | #endif |
| 80 | |
| 81 | #define _wait_for_atomic(COND, US) ({ \ |
| 82 | unsigned long end__; \ |
| 83 | int ret__ = 0; \ |
| 84 | _WAIT_FOR_ATOMIC_CHECK; \ |
| 85 | BUILD_BUG_ON((US) > 50000); \ |
| 86 | end__ = (local_clock() >> 10) + (US) + 1; \ |
| 87 | while (!(COND)) { \ |
| 88 | if (time_after((unsigned long)(local_clock() >> 10), end__)) { \ |
| 89 | /* Unlike the regular wait_for(), this atomic variant \ |
| 90 | * cannot be preempted (and we'll just ignore the issue\ |
| 91 | * of irq interruptions) and so we know that no time \ |
| 92 | * has passed since the last check of COND and can \ |
| 93 | * immediately report the timeout. \ |
| 94 | */ \ |
| 95 | ret__ = -ETIMEDOUT; \ |
| 96 | break; \ |
| 97 | } \ |
| 98 | cpu_relax(); \ |
| 99 | } \ |
| 100 | ret__; \ |
| 101 | }) |
| 102 | |
| 103 | #define wait_for_atomic(COND, MS) _wait_for_atomic((COND), (MS) * 1000) |
| 104 | #define wait_for_atomic_us(COND, US) _wait_for_atomic((COND), (US)) |
| 105 | |
| 106 | #define KHz(x) (1000 * (x)) |
| 107 | #define MHz(x) KHz(1000 * (x)) |
| 108 | |
| 109 | /* |
| 110 | * Display related stuff |
| 111 | */ |
| 112 | |
| 113 | /* store information about an Ixxx DVO */ |
| 114 | /* The i830->i865 use multiple DVOs with multiple i2cs */ |
| 115 | /* the i915, i945 have a single sDVO i2c bus - which is different */ |
| 116 | #define MAX_OUTPUTS 6 |
| 117 | /* maximum connectors per crtcs in the mode set */ |
| 118 | |
| 119 | /* Maximum cursor sizes */ |
| 120 | #define GEN2_CURSOR_WIDTH 64 |
| 121 | #define GEN2_CURSOR_HEIGHT 64 |
| 122 | #define MAX_CURSOR_WIDTH 256 |
| 123 | #define MAX_CURSOR_HEIGHT 256 |
| 124 | |
| 125 | #define INTEL_I2C_BUS_DVO 1 |
| 126 | #define INTEL_I2C_BUS_SDVO 2 |
| 127 | |
| 128 | /* these are outputs from the chip - integrated only |
| 129 | external chips are via DVO or SDVO output */ |
| 130 | enum intel_output_type { |
| 131 | INTEL_OUTPUT_UNUSED = 0, |
| 132 | INTEL_OUTPUT_ANALOG = 1, |
| 133 | INTEL_OUTPUT_DVO = 2, |
| 134 | INTEL_OUTPUT_SDVO = 3, |
| 135 | INTEL_OUTPUT_LVDS = 4, |
| 136 | INTEL_OUTPUT_TVOUT = 5, |
| 137 | INTEL_OUTPUT_HDMI = 6, |
| 138 | INTEL_OUTPUT_DISPLAYPORT = 7, |
| 139 | INTEL_OUTPUT_EDP = 8, |
| 140 | INTEL_OUTPUT_DSI = 9, |
| 141 | INTEL_OUTPUT_UNKNOWN = 10, |
| 142 | INTEL_OUTPUT_DP_MST = 11, |
| 143 | }; |
| 144 | |
| 145 | #define INTEL_DVO_CHIP_NONE 0 |
| 146 | #define INTEL_DVO_CHIP_LVDS 1 |
| 147 | #define INTEL_DVO_CHIP_TMDS 2 |
| 148 | #define INTEL_DVO_CHIP_TVOUT 4 |
| 149 | |
| 150 | #define INTEL_DSI_VIDEO_MODE 0 |
| 151 | #define INTEL_DSI_COMMAND_MODE 1 |
| 152 | |
| 153 | struct intel_framebuffer { |
| 154 | struct drm_framebuffer base; |
| 155 | struct drm_i915_gem_object *obj; |
| 156 | struct intel_rotation_info rot_info; |
| 157 | }; |
| 158 | |
| 159 | struct intel_fbdev { |
| 160 | struct drm_fb_helper helper; |
| 161 | struct intel_framebuffer *fb; |
| 162 | async_cookie_t cookie; |
| 163 | int preferred_bpp; |
| 164 | }; |
| 165 | |
| 166 | struct intel_encoder { |
| 167 | struct drm_encoder base; |
| 168 | |
| 169 | enum intel_output_type type; |
| 170 | unsigned int cloneable; |
| 171 | void (*hot_plug)(struct intel_encoder *); |
| 172 | bool (*compute_config)(struct intel_encoder *, |
| 173 | struct intel_crtc_state *); |
| 174 | void (*pre_pll_enable)(struct intel_encoder *); |
| 175 | void (*pre_enable)(struct intel_encoder *); |
| 176 | void (*enable)(struct intel_encoder *); |
| 177 | void (*mode_set)(struct intel_encoder *intel_encoder); |
| 178 | void (*disable)(struct intel_encoder *); |
| 179 | void (*post_disable)(struct intel_encoder *); |
| 180 | void (*post_pll_disable)(struct intel_encoder *); |
| 181 | /* Read out the current hw state of this connector, returning true if |
| 182 | * the encoder is active. If the encoder is enabled it also set the pipe |
| 183 | * it is connected to in the pipe parameter. */ |
| 184 | bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); |
| 185 | /* Reconstructs the equivalent mode flags for the current hardware |
| 186 | * state. This must be called _after_ display->get_pipe_config has |
| 187 | * pre-filled the pipe config. Note that intel_encoder->base.crtc must |
| 188 | * be set correctly before calling this function. */ |
| 189 | void (*get_config)(struct intel_encoder *, |
| 190 | struct intel_crtc_state *pipe_config); |
| 191 | /* |
| 192 | * Called during system suspend after all pending requests for the |
| 193 | * encoder are flushed (for example for DP AUX transactions) and |
| 194 | * device interrupts are disabled. |
| 195 | */ |
| 196 | void (*suspend)(struct intel_encoder *); |
| 197 | int crtc_mask; |
| 198 | enum hpd_pin hpd_pin; |
| 199 | }; |
| 200 | |
| 201 | struct intel_panel { |
| 202 | struct drm_display_mode *fixed_mode; |
| 203 | struct drm_display_mode *downclock_mode; |
| 204 | int fitting_mode; |
| 205 | |
| 206 | /* backlight */ |
| 207 | struct { |
| 208 | bool present; |
| 209 | u32 level; |
| 210 | u32 min; |
| 211 | u32 max; |
| 212 | bool enabled; |
| 213 | bool combination_mode; /* gen 2/4 only */ |
| 214 | bool active_low_pwm; |
| 215 | |
| 216 | /* PWM chip */ |
| 217 | bool util_pin_active_low; /* bxt+ */ |
| 218 | u8 controller; /* bxt+ only */ |
| 219 | struct pwm_device *pwm; |
| 220 | |
| 221 | struct backlight_device *device; |
| 222 | |
| 223 | /* Connector and platform specific backlight functions */ |
| 224 | int (*setup)(struct intel_connector *connector, enum pipe pipe); |
| 225 | uint32_t (*get)(struct intel_connector *connector); |
| 226 | void (*set)(struct intel_connector *connector, uint32_t level); |
| 227 | void (*disable)(struct intel_connector *connector); |
| 228 | void (*enable)(struct intel_connector *connector); |
| 229 | uint32_t (*hz_to_pwm)(struct intel_connector *connector, |
| 230 | uint32_t hz); |
| 231 | void (*power)(struct intel_connector *, bool enable); |
| 232 | } backlight; |
| 233 | }; |
| 234 | |
| 235 | struct intel_connector { |
| 236 | struct drm_connector base; |
| 237 | /* |
| 238 | * The fixed encoder this connector is connected to. |
| 239 | */ |
| 240 | struct intel_encoder *encoder; |
| 241 | |
| 242 | /* Reads out the current hw, returning true if the connector is enabled |
| 243 | * and active (i.e. dpms ON state). */ |
| 244 | bool (*get_hw_state)(struct intel_connector *); |
| 245 | |
| 246 | /* Panel info for eDP and LVDS */ |
| 247 | struct intel_panel panel; |
| 248 | |
| 249 | /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ |
| 250 | struct edid *edid; |
| 251 | struct edid *detect_edid; |
| 252 | |
| 253 | /* since POLL and HPD connectors may use the same HPD line keep the native |
| 254 | state of connector->polled in case hotplug storm detection changes it */ |
| 255 | u8 polled; |
| 256 | |
| 257 | void *port; /* store this opaque as its illegal to dereference it */ |
| 258 | |
| 259 | struct intel_dp *mst_port; |
| 260 | }; |
| 261 | |
| 262 | struct dpll { |
| 263 | /* given values */ |
| 264 | int n; |
| 265 | int m1, m2; |
| 266 | int p1, p2; |
| 267 | /* derived values */ |
| 268 | int dot; |
| 269 | int vco; |
| 270 | int m; |
| 271 | int p; |
| 272 | }; |
| 273 | |
| 274 | struct intel_atomic_state { |
| 275 | struct drm_atomic_state base; |
| 276 | |
| 277 | unsigned int cdclk; |
| 278 | |
| 279 | /* |
| 280 | * Calculated device cdclk, can be different from cdclk |
| 281 | * only when all crtc's are DPMS off. |
| 282 | */ |
| 283 | unsigned int dev_cdclk; |
| 284 | |
| 285 | bool dpll_set, modeset; |
| 286 | |
| 287 | /* |
| 288 | * Does this transaction change the pipes that are active? This mask |
| 289 | * tracks which CRTC's have changed their active state at the end of |
| 290 | * the transaction (not counting the temporary disable during modesets). |
| 291 | * This mask should only be non-zero when intel_state->modeset is true, |
| 292 | * but the converse is not necessarily true; simply changing a mode may |
| 293 | * not flip the final active status of any CRTC's |
| 294 | */ |
| 295 | unsigned int active_pipe_changes; |
| 296 | |
| 297 | unsigned int active_crtcs; |
| 298 | unsigned int min_pixclk[I915_MAX_PIPES]; |
| 299 | |
| 300 | /* SKL/KBL Only */ |
| 301 | unsigned int cdclk_pll_vco; |
| 302 | |
| 303 | struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS]; |
| 304 | |
| 305 | /* |
| 306 | * Current watermarks can't be trusted during hardware readout, so |
| 307 | * don't bother calculating intermediate watermarks. |
| 308 | */ |
| 309 | bool skip_intermediate_wm; |
| 310 | |
| 311 | /* Gen9+ only */ |
| 312 | struct skl_wm_values wm_results; |
| 313 | }; |
| 314 | |
| 315 | struct intel_plane_state { |
| 316 | struct drm_plane_state base; |
| 317 | struct drm_rect src; |
| 318 | struct drm_rect dst; |
| 319 | struct drm_rect clip; |
| 320 | bool visible; |
| 321 | |
| 322 | /* |
| 323 | * scaler_id |
| 324 | * = -1 : not using a scaler |
| 325 | * >= 0 : using a scalers |
| 326 | * |
| 327 | * plane requiring a scaler: |
| 328 | * - During check_plane, its bit is set in |
| 329 | * crtc_state->scaler_state.scaler_users by calling helper function |
| 330 | * update_scaler_plane. |
| 331 | * - scaler_id indicates the scaler it got assigned. |
| 332 | * |
| 333 | * plane doesn't require a scaler: |
| 334 | * - this can happen when scaling is no more required or plane simply |
| 335 | * got disabled. |
| 336 | * - During check_plane, corresponding bit is reset in |
| 337 | * crtc_state->scaler_state.scaler_users by calling helper function |
| 338 | * update_scaler_plane. |
| 339 | */ |
| 340 | int scaler_id; |
| 341 | |
| 342 | struct drm_intel_sprite_colorkey ckey; |
| 343 | |
| 344 | /* async flip related structures */ |
| 345 | struct drm_i915_gem_request *wait_req; |
| 346 | }; |
| 347 | |
| 348 | struct intel_initial_plane_config { |
| 349 | struct intel_framebuffer *fb; |
| 350 | unsigned int tiling; |
| 351 | int size; |
| 352 | u32 base; |
| 353 | }; |
| 354 | |
| 355 | #define SKL_MIN_SRC_W 8 |
| 356 | #define SKL_MAX_SRC_W 4096 |
| 357 | #define SKL_MIN_SRC_H 8 |
| 358 | #define SKL_MAX_SRC_H 4096 |
| 359 | #define SKL_MIN_DST_W 8 |
| 360 | #define SKL_MAX_DST_W 4096 |
| 361 | #define SKL_MIN_DST_H 8 |
| 362 | #define SKL_MAX_DST_H 4096 |
| 363 | |
| 364 | struct intel_scaler { |
| 365 | int in_use; |
| 366 | uint32_t mode; |
| 367 | }; |
| 368 | |
| 369 | struct intel_crtc_scaler_state { |
| 370 | #define SKL_NUM_SCALERS 2 |
| 371 | struct intel_scaler scalers[SKL_NUM_SCALERS]; |
| 372 | |
| 373 | /* |
| 374 | * scaler_users: keeps track of users requesting scalers on this crtc. |
| 375 | * |
| 376 | * If a bit is set, a user is using a scaler. |
| 377 | * Here user can be a plane or crtc as defined below: |
| 378 | * bits 0-30 - plane (bit position is index from drm_plane_index) |
| 379 | * bit 31 - crtc |
| 380 | * |
| 381 | * Instead of creating a new index to cover planes and crtc, using |
| 382 | * existing drm_plane_index for planes which is well less than 31 |
| 383 | * planes and bit 31 for crtc. This should be fine to cover all |
| 384 | * our platforms. |
| 385 | * |
| 386 | * intel_atomic_setup_scalers will setup available scalers to users |
| 387 | * requesting scalers. It will gracefully fail if request exceeds |
| 388 | * avilability. |
| 389 | */ |
| 390 | #define SKL_CRTC_INDEX 31 |
| 391 | unsigned scaler_users; |
| 392 | |
| 393 | /* scaler used by crtc for panel fitting purpose */ |
| 394 | int scaler_id; |
| 395 | }; |
| 396 | |
| 397 | /* drm_mode->private_flags */ |
| 398 | #define I915_MODE_FLAG_INHERITED 1 |
| 399 | |
| 400 | struct intel_pipe_wm { |
| 401 | struct intel_wm_level wm[5]; |
| 402 | struct intel_wm_level raw_wm[5]; |
| 403 | uint32_t linetime; |
| 404 | bool fbc_wm_enabled; |
| 405 | bool pipe_enabled; |
| 406 | bool sprites_enabled; |
| 407 | bool sprites_scaled; |
| 408 | }; |
| 409 | |
| 410 | struct skl_pipe_wm { |
| 411 | struct skl_wm_level wm[8]; |
| 412 | struct skl_wm_level trans_wm; |
| 413 | uint32_t linetime; |
| 414 | }; |
| 415 | |
| 416 | struct intel_crtc_wm_state { |
| 417 | union { |
| 418 | struct { |
| 419 | /* |
| 420 | * Intermediate watermarks; these can be |
| 421 | * programmed immediately since they satisfy |
| 422 | * both the current configuration we're |
| 423 | * switching away from and the new |
| 424 | * configuration we're switching to. |
| 425 | */ |
| 426 | struct intel_pipe_wm intermediate; |
| 427 | |
| 428 | /* |
| 429 | * Optimal watermarks, programmed post-vblank |
| 430 | * when this state is committed. |
| 431 | */ |
| 432 | struct intel_pipe_wm optimal; |
| 433 | } ilk; |
| 434 | |
| 435 | struct { |
| 436 | /* gen9+ only needs 1-step wm programming */ |
| 437 | struct skl_pipe_wm optimal; |
| 438 | |
| 439 | /* cached plane data rate */ |
| 440 | unsigned plane_data_rate[I915_MAX_PLANES]; |
| 441 | unsigned plane_y_data_rate[I915_MAX_PLANES]; |
| 442 | |
| 443 | /* minimum block allocation */ |
| 444 | uint16_t minimum_blocks[I915_MAX_PLANES]; |
| 445 | uint16_t minimum_y_blocks[I915_MAX_PLANES]; |
| 446 | } skl; |
| 447 | }; |
| 448 | |
| 449 | /* |
| 450 | * Platforms with two-step watermark programming will need to |
| 451 | * update watermark programming post-vblank to switch from the |
| 452 | * safe intermediate watermarks to the optimal final |
| 453 | * watermarks. |
| 454 | */ |
| 455 | bool need_postvbl_update; |
| 456 | }; |
| 457 | |
| 458 | struct intel_crtc_state { |
| 459 | struct drm_crtc_state base; |
| 460 | |
| 461 | /** |
| 462 | * quirks - bitfield with hw state readout quirks |
| 463 | * |
| 464 | * For various reasons the hw state readout code might not be able to |
| 465 | * completely faithfully read out the current state. These cases are |
| 466 | * tracked with quirk flags so that fastboot and state checker can act |
| 467 | * accordingly. |
| 468 | */ |
| 469 | #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ |
| 470 | unsigned long quirks; |
| 471 | |
| 472 | unsigned fb_bits; /* framebuffers to flip */ |
| 473 | bool update_pipe; /* can a fast modeset be performed? */ |
| 474 | bool disable_cxsr; |
| 475 | bool update_wm_pre, update_wm_post; /* watermarks are updated */ |
| 476 | bool fb_changed; /* fb on any of the planes is changed */ |
| 477 | |
| 478 | /* Pipe source size (ie. panel fitter input size) |
| 479 | * All planes will be positioned inside this space, |
| 480 | * and get clipped at the edges. */ |
| 481 | int pipe_src_w, pipe_src_h; |
| 482 | |
| 483 | /* Whether to set up the PCH/FDI. Note that we never allow sharing |
| 484 | * between pch encoders and cpu encoders. */ |
| 485 | bool has_pch_encoder; |
| 486 | |
| 487 | /* Are we sending infoframes on the attached port */ |
| 488 | bool has_infoframe; |
| 489 | |
| 490 | /* CPU Transcoder for the pipe. Currently this can only differ from the |
| 491 | * pipe on Haswell and later (where we have a special eDP transcoder) |
| 492 | * and Broxton (where we have special DSI transcoders). */ |
| 493 | enum transcoder cpu_transcoder; |
| 494 | |
| 495 | /* |
| 496 | * Use reduced/limited/broadcast rbg range, compressing from the full |
| 497 | * range fed into the crtcs. |
| 498 | */ |
| 499 | bool limited_color_range; |
| 500 | |
| 501 | /* DP has a bunch of special case unfortunately, so mark the pipe |
| 502 | * accordingly. */ |
| 503 | bool has_dp_encoder; |
| 504 | |
| 505 | /* DSI has special cases */ |
| 506 | bool has_dsi_encoder; |
| 507 | |
| 508 | /* Whether we should send NULL infoframes. Required for audio. */ |
| 509 | bool has_hdmi_sink; |
| 510 | |
| 511 | /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or |
| 512 | * has_dp_encoder is set. */ |
| 513 | bool has_audio; |
| 514 | |
| 515 | /* |
| 516 | * Enable dithering, used when the selected pipe bpp doesn't match the |
| 517 | * plane bpp. |
| 518 | */ |
| 519 | bool dither; |
| 520 | |
| 521 | /* Controls for the clock computation, to override various stages. */ |
| 522 | bool clock_set; |
| 523 | |
| 524 | /* SDVO TV has a bunch of special case. To make multifunction encoders |
| 525 | * work correctly, we need to track this at runtime.*/ |
| 526 | bool sdvo_tv_clock; |
| 527 | |
| 528 | /* |
| 529 | * crtc bandwidth limit, don't increase pipe bpp or clock if not really |
| 530 | * required. This is set in the 2nd loop of calling encoder's |
| 531 | * ->compute_config if the first pick doesn't work out. |
| 532 | */ |
| 533 | bool bw_constrained; |
| 534 | |
| 535 | /* Settings for the intel dpll used on pretty much everything but |
| 536 | * haswell. */ |
| 537 | struct dpll dpll; |
| 538 | |
| 539 | /* Selected dpll when shared or NULL. */ |
| 540 | struct intel_shared_dpll *shared_dpll; |
| 541 | |
| 542 | /* |
| 543 | * - PORT_CLK_SEL for DDI ports on HSW/BDW. |
| 544 | * - enum skl_dpll on SKL |
| 545 | */ |
| 546 | uint32_t ddi_pll_sel; |
| 547 | |
| 548 | /* Actual register state of the dpll, for shared dpll cross-checking. */ |
| 549 | struct intel_dpll_hw_state dpll_hw_state; |
| 550 | |
| 551 | /* DSI PLL registers */ |
| 552 | struct { |
| 553 | u32 ctrl, div; |
| 554 | } dsi_pll; |
| 555 | |
| 556 | int pipe_bpp; |
| 557 | struct intel_link_m_n dp_m_n; |
| 558 | |
| 559 | /* m2_n2 for eDP downclock */ |
| 560 | struct intel_link_m_n dp_m2_n2; |
| 561 | bool has_drrs; |
| 562 | |
| 563 | /* |
| 564 | * Frequence the dpll for the port should run at. Differs from the |
| 565 | * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also |
| 566 | * already multiplied by pixel_multiplier. |
| 567 | */ |
| 568 | int port_clock; |
| 569 | |
| 570 | /* Used by SDVO (and if we ever fix it, HDMI). */ |
| 571 | unsigned pixel_multiplier; |
| 572 | |
| 573 | uint8_t lane_count; |
| 574 | |
| 575 | /* |
| 576 | * Used by platforms having DP/HDMI PHY with programmable lane |
| 577 | * latency optimization. |
| 578 | */ |
| 579 | uint8_t lane_lat_optim_mask; |
| 580 | |
| 581 | /* Panel fitter controls for gen2-gen4 + VLV */ |
| 582 | struct { |
| 583 | u32 control; |
| 584 | u32 pgm_ratios; |
| 585 | u32 lvds_border_bits; |
| 586 | } gmch_pfit; |
| 587 | |
| 588 | /* Panel fitter placement and size for Ironlake+ */ |
| 589 | struct { |
| 590 | u32 pos; |
| 591 | u32 size; |
| 592 | bool enabled; |
| 593 | bool force_thru; |
| 594 | } pch_pfit; |
| 595 | |
| 596 | /* FDI configuration, only valid if has_pch_encoder is set. */ |
| 597 | int fdi_lanes; |
| 598 | struct intel_link_m_n fdi_m_n; |
| 599 | |
| 600 | bool ips_enabled; |
| 601 | |
| 602 | bool enable_fbc; |
| 603 | |
| 604 | bool double_wide; |
| 605 | |
| 606 | bool dp_encoder_is_mst; |
| 607 | int pbn; |
| 608 | |
| 609 | struct intel_crtc_scaler_state scaler_state; |
| 610 | |
| 611 | /* w/a for waiting 2 vblanks during crtc enable */ |
| 612 | enum pipe hsw_workaround_pipe; |
| 613 | |
| 614 | /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */ |
| 615 | bool disable_lp_wm; |
| 616 | |
| 617 | struct intel_crtc_wm_state wm; |
| 618 | |
| 619 | /* Gamma mode programmed on the pipe */ |
| 620 | uint32_t gamma_mode; |
| 621 | }; |
| 622 | |
| 623 | struct vlv_wm_state { |
| 624 | struct vlv_pipe_wm wm[3]; |
| 625 | struct vlv_sr_wm sr[3]; |
| 626 | uint8_t num_active_planes; |
| 627 | uint8_t num_levels; |
| 628 | uint8_t level; |
| 629 | bool cxsr; |
| 630 | }; |
| 631 | |
| 632 | struct intel_crtc { |
| 633 | struct drm_crtc base; |
| 634 | enum pipe pipe; |
| 635 | enum plane plane; |
| 636 | u8 lut_r[256], lut_g[256], lut_b[256]; |
| 637 | /* |
| 638 | * Whether the crtc and the connected output pipeline is active. Implies |
| 639 | * that crtc->enabled is set, i.e. the current mode configuration has |
| 640 | * some outputs connected to this crtc. |
| 641 | */ |
| 642 | bool active; |
| 643 | unsigned long enabled_power_domains; |
| 644 | bool lowfreq_avail; |
| 645 | struct intel_overlay *overlay; |
| 646 | struct intel_flip_work *flip_work; |
| 647 | |
| 648 | atomic_t unpin_work_count; |
| 649 | |
| 650 | /* Display surface base address adjustement for pageflips. Note that on |
| 651 | * gen4+ this only adjusts up to a tile, offsets within a tile are |
| 652 | * handled in the hw itself (with the TILEOFF register). */ |
| 653 | u32 dspaddr_offset; |
| 654 | int adjusted_x; |
| 655 | int adjusted_y; |
| 656 | |
| 657 | uint32_t cursor_addr; |
| 658 | uint32_t cursor_cntl; |
| 659 | uint32_t cursor_size; |
| 660 | uint32_t cursor_base; |
| 661 | |
| 662 | struct intel_crtc_state *config; |
| 663 | |
| 664 | /* reset counter value when the last flip was submitted */ |
| 665 | unsigned int reset_counter; |
| 666 | |
| 667 | /* Access to these should be protected by dev_priv->irq_lock. */ |
| 668 | bool cpu_fifo_underrun_disabled; |
| 669 | bool pch_fifo_underrun_disabled; |
| 670 | |
| 671 | /* per-pipe watermark state */ |
| 672 | struct { |
| 673 | /* watermarks currently being used */ |
| 674 | union { |
| 675 | struct intel_pipe_wm ilk; |
| 676 | struct skl_pipe_wm skl; |
| 677 | } active; |
| 678 | |
| 679 | /* allow CxSR on this pipe */ |
| 680 | bool cxsr_allowed; |
| 681 | } wm; |
| 682 | |
| 683 | int scanline_offset; |
| 684 | |
| 685 | struct { |
| 686 | unsigned start_vbl_count; |
| 687 | ktime_t start_vbl_time; |
| 688 | int min_vbl, max_vbl; |
| 689 | int scanline_start; |
| 690 | } debug; |
| 691 | |
| 692 | /* scalers available on this crtc */ |
| 693 | int num_scalers; |
| 694 | |
| 695 | struct vlv_wm_state wm_state; |
| 696 | }; |
| 697 | |
| 698 | struct intel_plane_wm_parameters { |
| 699 | uint32_t horiz_pixels; |
| 700 | uint32_t vert_pixels; |
| 701 | /* |
| 702 | * For packed pixel formats: |
| 703 | * bytes_per_pixel - holds bytes per pixel |
| 704 | * For planar pixel formats: |
| 705 | * bytes_per_pixel - holds bytes per pixel for uv-plane |
| 706 | * y_bytes_per_pixel - holds bytes per pixel for y-plane |
| 707 | */ |
| 708 | uint8_t bytes_per_pixel; |
| 709 | uint8_t y_bytes_per_pixel; |
| 710 | bool enabled; |
| 711 | bool scaled; |
| 712 | u64 tiling; |
| 713 | unsigned int rotation; |
| 714 | uint16_t fifo_size; |
| 715 | }; |
| 716 | |
| 717 | struct intel_plane { |
| 718 | struct drm_plane base; |
| 719 | int plane; |
| 720 | enum pipe pipe; |
| 721 | bool can_scale; |
| 722 | int max_downscale; |
| 723 | uint32_t frontbuffer_bit; |
| 724 | |
| 725 | /* Since we need to change the watermarks before/after |
| 726 | * enabling/disabling the planes, we need to store the parameters here |
| 727 | * as the other pieces of the struct may not reflect the values we want |
| 728 | * for the watermark calculations. Currently only Haswell uses this. |
| 729 | */ |
| 730 | struct intel_plane_wm_parameters wm; |
| 731 | |
| 732 | /* |
| 733 | * NOTE: Do not place new plane state fields here (e.g., when adding |
| 734 | * new plane properties). New runtime state should now be placed in |
| 735 | * the intel_plane_state structure and accessed via plane_state. |
| 736 | */ |
| 737 | |
| 738 | void (*update_plane)(struct drm_plane *plane, |
| 739 | const struct intel_crtc_state *crtc_state, |
| 740 | const struct intel_plane_state *plane_state); |
| 741 | void (*disable_plane)(struct drm_plane *plane, |
| 742 | struct drm_crtc *crtc); |
| 743 | int (*check_plane)(struct drm_plane *plane, |
| 744 | struct intel_crtc_state *crtc_state, |
| 745 | struct intel_plane_state *state); |
| 746 | }; |
| 747 | |
| 748 | struct intel_watermark_params { |
| 749 | unsigned long fifo_size; |
| 750 | unsigned long max_wm; |
| 751 | unsigned long default_wm; |
| 752 | unsigned long guard_size; |
| 753 | unsigned long cacheline_size; |
| 754 | }; |
| 755 | |
| 756 | struct cxsr_latency { |
| 757 | int is_desktop; |
| 758 | int is_ddr3; |
| 759 | unsigned long fsb_freq; |
| 760 | unsigned long mem_freq; |
| 761 | unsigned long display_sr; |
| 762 | unsigned long display_hpll_disable; |
| 763 | unsigned long cursor_sr; |
| 764 | unsigned long cursor_hpll_disable; |
| 765 | }; |
| 766 | |
| 767 | #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base) |
| 768 | #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) |
| 769 | #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base) |
| 770 | #define to_intel_connector(x) container_of(x, struct intel_connector, base) |
| 771 | #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) |
| 772 | #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) |
| 773 | #define to_intel_plane(x) container_of(x, struct intel_plane, base) |
| 774 | #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base) |
| 775 | #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL) |
| 776 | |
| 777 | struct intel_hdmi { |
| 778 | i915_reg_t hdmi_reg; |
| 779 | int ddc_bus; |
| 780 | struct { |
| 781 | enum drm_dp_dual_mode_type type; |
| 782 | int max_tmds_clock; |
| 783 | } dp_dual_mode; |
| 784 | bool limited_color_range; |
| 785 | bool color_range_auto; |
| 786 | bool has_hdmi_sink; |
| 787 | bool has_audio; |
| 788 | enum hdmi_force_audio force_audio; |
| 789 | bool rgb_quant_range_selectable; |
| 790 | enum hdmi_picture_aspect aspect_ratio; |
| 791 | struct intel_connector *attached_connector; |
| 792 | void (*write_infoframe)(struct drm_encoder *encoder, |
| 793 | enum hdmi_infoframe_type type, |
| 794 | const void *frame, ssize_t len); |
| 795 | void (*set_infoframes)(struct drm_encoder *encoder, |
| 796 | bool enable, |
| 797 | const struct drm_display_mode *adjusted_mode); |
| 798 | bool (*infoframe_enabled)(struct drm_encoder *encoder, |
| 799 | const struct intel_crtc_state *pipe_config); |
| 800 | }; |
| 801 | |
| 802 | struct intel_dp_mst_encoder; |
| 803 | #define DP_MAX_DOWNSTREAM_PORTS 0x10 |
| 804 | |
| 805 | /* |
| 806 | * enum link_m_n_set: |
| 807 | * When platform provides two set of M_N registers for dp, we can |
| 808 | * program them and switch between them incase of DRRS. |
| 809 | * But When only one such register is provided, we have to program the |
| 810 | * required divider value on that registers itself based on the DRRS state. |
| 811 | * |
| 812 | * M1_N1 : Program dp_m_n on M1_N1 registers |
| 813 | * dp_m2_n2 on M2_N2 registers (If supported) |
| 814 | * |
| 815 | * M2_N2 : Program dp_m2_n2 on M1_N1 registers |
| 816 | * M2_N2 registers are not supported |
| 817 | */ |
| 818 | |
| 819 | enum link_m_n_set { |
| 820 | /* Sets the m1_n1 and m2_n2 */ |
| 821 | M1_N1 = 0, |
| 822 | M2_N2 |
| 823 | }; |
| 824 | |
| 825 | struct intel_dp { |
| 826 | i915_reg_t output_reg; |
| 827 | i915_reg_t aux_ch_ctl_reg; |
| 828 | i915_reg_t aux_ch_data_reg[5]; |
| 829 | uint32_t DP; |
| 830 | int link_rate; |
| 831 | uint8_t lane_count; |
| 832 | uint8_t sink_count; |
| 833 | bool has_audio; |
| 834 | bool detect_done; |
| 835 | enum hdmi_force_audio force_audio; |
| 836 | bool limited_color_range; |
| 837 | bool color_range_auto; |
| 838 | uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; |
| 839 | uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; |
| 840 | uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; |
| 841 | uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]; |
| 842 | /* sink rates as reported by DP_SUPPORTED_LINK_RATES */ |
| 843 | uint8_t num_sink_rates; |
| 844 | int sink_rates[DP_MAX_SUPPORTED_RATES]; |
| 845 | struct drm_dp_aux aux; |
| 846 | uint8_t train_set[4]; |
| 847 | int panel_power_up_delay; |
| 848 | int panel_power_down_delay; |
| 849 | int panel_power_cycle_delay; |
| 850 | int backlight_on_delay; |
| 851 | int backlight_off_delay; |
| 852 | struct delayed_work panel_vdd_work; |
| 853 | bool want_panel_vdd; |
| 854 | unsigned long last_power_on; |
| 855 | unsigned long last_backlight_off; |
| 856 | ktime_t panel_power_off_time; |
| 857 | |
| 858 | struct notifier_block edp_notifier; |
| 859 | |
| 860 | /* |
| 861 | * Pipe whose power sequencer is currently locked into |
| 862 | * this port. Only relevant on VLV/CHV. |
| 863 | */ |
| 864 | enum pipe pps_pipe; |
| 865 | /* |
| 866 | * Set if the sequencer may be reset due to a power transition, |
| 867 | * requiring a reinitialization. Only relevant on BXT. |
| 868 | */ |
| 869 | bool pps_reset; |
| 870 | struct edp_power_seq pps_delays; |
| 871 | |
| 872 | bool can_mst; /* this port supports mst */ |
| 873 | bool is_mst; |
| 874 | int active_mst_links; |
| 875 | /* connector directly attached - won't be use for modeset in mst world */ |
| 876 | struct intel_connector *attached_connector; |
| 877 | |
| 878 | /* mst connector list */ |
| 879 | struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES]; |
| 880 | struct drm_dp_mst_topology_mgr mst_mgr; |
| 881 | |
| 882 | uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index); |
| 883 | /* |
| 884 | * This function returns the value we have to program the AUX_CTL |
| 885 | * register with to kick off an AUX transaction. |
| 886 | */ |
| 887 | uint32_t (*get_aux_send_ctl)(struct intel_dp *dp, |
| 888 | bool has_aux_irq, |
| 889 | int send_bytes, |
| 890 | uint32_t aux_clock_divider); |
| 891 | |
| 892 | /* This is called before a link training is starterd */ |
| 893 | void (*prepare_link_retrain)(struct intel_dp *intel_dp); |
| 894 | |
| 895 | /* Displayport compliance testing */ |
| 896 | unsigned long compliance_test_type; |
| 897 | unsigned long compliance_test_data; |
| 898 | bool compliance_test_active; |
| 899 | }; |
| 900 | |
| 901 | struct intel_digital_port { |
| 902 | struct intel_encoder base; |
| 903 | enum port port; |
| 904 | u32 saved_port_bits; |
| 905 | struct intel_dp dp; |
| 906 | struct intel_hdmi hdmi; |
| 907 | enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool); |
| 908 | bool release_cl2_override; |
| 909 | uint8_t max_lanes; |
| 910 | /* for communication with audio component; protected by av_mutex */ |
| 911 | const struct drm_connector *audio_connector; |
| 912 | }; |
| 913 | |
| 914 | struct intel_dp_mst_encoder { |
| 915 | struct intel_encoder base; |
| 916 | enum pipe pipe; |
| 917 | struct intel_digital_port *primary; |
| 918 | struct intel_connector *connector; |
| 919 | }; |
| 920 | |
| 921 | static inline enum dpio_channel |
| 922 | vlv_dport_to_channel(struct intel_digital_port *dport) |
| 923 | { |
| 924 | switch (dport->port) { |
| 925 | case PORT_B: |
| 926 | case PORT_D: |
| 927 | return DPIO_CH0; |
| 928 | case PORT_C: |
| 929 | return DPIO_CH1; |
| 930 | default: |
| 931 | BUG(); |
| 932 | } |
| 933 | } |
| 934 | |
| 935 | static inline enum dpio_phy |
| 936 | vlv_dport_to_phy(struct intel_digital_port *dport) |
| 937 | { |
| 938 | switch (dport->port) { |
| 939 | case PORT_B: |
| 940 | case PORT_C: |
| 941 | return DPIO_PHY0; |
| 942 | case PORT_D: |
| 943 | return DPIO_PHY1; |
| 944 | default: |
| 945 | BUG(); |
| 946 | } |
| 947 | } |
| 948 | |
| 949 | static inline enum dpio_channel |
| 950 | vlv_pipe_to_channel(enum pipe pipe) |
| 951 | { |
| 952 | switch (pipe) { |
| 953 | case PIPE_A: |
| 954 | case PIPE_C: |
| 955 | return DPIO_CH0; |
| 956 | case PIPE_B: |
| 957 | return DPIO_CH1; |
| 958 | default: |
| 959 | BUG(); |
| 960 | } |
| 961 | } |
| 962 | |
| 963 | static inline struct drm_crtc * |
| 964 | intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) |
| 965 | { |
| 966 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 967 | return dev_priv->pipe_to_crtc_mapping[pipe]; |
| 968 | } |
| 969 | |
| 970 | static inline struct drm_crtc * |
| 971 | intel_get_crtc_for_plane(struct drm_device *dev, int plane) |
| 972 | { |
| 973 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 974 | return dev_priv->plane_to_crtc_mapping[plane]; |
| 975 | } |
| 976 | |
| 977 | struct intel_flip_work { |
| 978 | struct work_struct unpin_work; |
| 979 | struct work_struct mmio_work; |
| 980 | |
| 981 | struct drm_crtc *crtc; |
| 982 | struct drm_framebuffer *old_fb; |
| 983 | struct drm_i915_gem_object *pending_flip_obj; |
| 984 | struct drm_pending_vblank_event *event; |
| 985 | atomic_t pending; |
| 986 | u32 flip_count; |
| 987 | u32 gtt_offset; |
| 988 | struct drm_i915_gem_request *flip_queued_req; |
| 989 | u32 flip_queued_vblank; |
| 990 | u32 flip_ready_vblank; |
| 991 | unsigned int rotation; |
| 992 | }; |
| 993 | |
| 994 | struct intel_load_detect_pipe { |
| 995 | struct drm_atomic_state *restore_state; |
| 996 | }; |
| 997 | |
| 998 | static inline struct intel_encoder * |
| 999 | intel_attached_encoder(struct drm_connector *connector) |
| 1000 | { |
| 1001 | return to_intel_connector(connector)->encoder; |
| 1002 | } |
| 1003 | |
| 1004 | static inline struct intel_digital_port * |
| 1005 | enc_to_dig_port(struct drm_encoder *encoder) |
| 1006 | { |
| 1007 | return container_of(encoder, struct intel_digital_port, base.base); |
| 1008 | } |
| 1009 | |
| 1010 | static inline struct intel_dp_mst_encoder * |
| 1011 | enc_to_mst(struct drm_encoder *encoder) |
| 1012 | { |
| 1013 | return container_of(encoder, struct intel_dp_mst_encoder, base.base); |
| 1014 | } |
| 1015 | |
| 1016 | static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
| 1017 | { |
| 1018 | return &enc_to_dig_port(encoder)->dp; |
| 1019 | } |
| 1020 | |
| 1021 | static inline struct intel_digital_port * |
| 1022 | dp_to_dig_port(struct intel_dp *intel_dp) |
| 1023 | { |
| 1024 | return container_of(intel_dp, struct intel_digital_port, dp); |
| 1025 | } |
| 1026 | |
| 1027 | static inline struct intel_digital_port * |
| 1028 | hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) |
| 1029 | { |
| 1030 | return container_of(intel_hdmi, struct intel_digital_port, hdmi); |
| 1031 | } |
| 1032 | |
| 1033 | /* |
| 1034 | * Returns the number of planes for this pipe, ie the number of sprites + 1 |
| 1035 | * (primary plane). This doesn't count the cursor plane then. |
| 1036 | */ |
| 1037 | static inline unsigned int intel_num_planes(struct intel_crtc *crtc) |
| 1038 | { |
| 1039 | return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1; |
| 1040 | } |
| 1041 | |
| 1042 | /* intel_fifo_underrun.c */ |
| 1043 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, |
| 1044 | enum pipe pipe, bool enable); |
| 1045 | bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, |
| 1046 | enum transcoder pch_transcoder, |
| 1047 | bool enable); |
| 1048 | void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, |
| 1049 | enum pipe pipe); |
| 1050 | void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, |
| 1051 | enum transcoder pch_transcoder); |
| 1052 | void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv); |
| 1053 | void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv); |
| 1054 | |
| 1055 | /* i915_irq.c */ |
| 1056 | void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
| 1057 | void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
| 1058 | void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
| 1059 | void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
| 1060 | void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv); |
| 1061 | void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv); |
| 1062 | void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv); |
| 1063 | u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask); |
| 1064 | void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv); |
| 1065 | void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv); |
| 1066 | static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv) |
| 1067 | { |
| 1068 | /* |
| 1069 | * We only use drm_irq_uninstall() at unload and VT switch, so |
| 1070 | * this is the only thing we need to check. |
| 1071 | */ |
| 1072 | return dev_priv->pm.irqs_enabled; |
| 1073 | } |
| 1074 | |
| 1075 | int intel_get_crtc_scanline(struct intel_crtc *crtc); |
| 1076 | void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, |
| 1077 | unsigned int pipe_mask); |
| 1078 | void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, |
| 1079 | unsigned int pipe_mask); |
| 1080 | |
| 1081 | /* intel_crt.c */ |
| 1082 | void intel_crt_init(struct drm_device *dev); |
| 1083 | |
| 1084 | |
| 1085 | /* intel_ddi.c */ |
| 1086 | void intel_ddi_clk_select(struct intel_encoder *encoder, |
| 1087 | const struct intel_crtc_state *pipe_config); |
| 1088 | void intel_prepare_ddi_buffer(struct intel_encoder *encoder); |
| 1089 | void hsw_fdi_link_train(struct drm_crtc *crtc); |
| 1090 | void intel_ddi_init(struct drm_device *dev, enum port port); |
| 1091 | enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder); |
| 1092 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe); |
| 1093 | void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc); |
| 1094 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
| 1095 | enum transcoder cpu_transcoder); |
| 1096 | void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); |
| 1097 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc); |
| 1098 | bool intel_ddi_pll_select(struct intel_crtc *crtc, |
| 1099 | struct intel_crtc_state *crtc_state); |
| 1100 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc); |
| 1101 | void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp); |
| 1102 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); |
| 1103 | void intel_ddi_fdi_disable(struct drm_crtc *crtc); |
| 1104 | void intel_ddi_get_config(struct intel_encoder *encoder, |
| 1105 | struct intel_crtc_state *pipe_config); |
| 1106 | struct intel_encoder * |
| 1107 | intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state); |
| 1108 | |
| 1109 | void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder); |
| 1110 | void intel_ddi_clock_get(struct intel_encoder *encoder, |
| 1111 | struct intel_crtc_state *pipe_config); |
| 1112 | void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state); |
| 1113 | uint32_t ddi_signal_levels(struct intel_dp *intel_dp); |
| 1114 | |
| 1115 | /* intel_frontbuffer.c */ |
| 1116 | void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj, |
| 1117 | enum fb_op_origin origin); |
| 1118 | void intel_frontbuffer_flip_prepare(struct drm_device *dev, |
| 1119 | unsigned frontbuffer_bits); |
| 1120 | void intel_frontbuffer_flip_complete(struct drm_device *dev, |
| 1121 | unsigned frontbuffer_bits); |
| 1122 | void intel_frontbuffer_flip(struct drm_device *dev, |
| 1123 | unsigned frontbuffer_bits); |
| 1124 | unsigned int intel_fb_align_height(struct drm_device *dev, |
| 1125 | unsigned int height, |
| 1126 | uint32_t pixel_format, |
| 1127 | uint64_t fb_format_modifier); |
| 1128 | void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire, |
| 1129 | enum fb_op_origin origin); |
| 1130 | u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv, |
| 1131 | uint64_t fb_modifier, uint32_t pixel_format); |
| 1132 | |
| 1133 | /* intel_audio.c */ |
| 1134 | void intel_init_audio_hooks(struct drm_i915_private *dev_priv); |
| 1135 | void intel_audio_codec_enable(struct intel_encoder *encoder); |
| 1136 | void intel_audio_codec_disable(struct intel_encoder *encoder); |
| 1137 | void i915_audio_component_init(struct drm_i915_private *dev_priv); |
| 1138 | void i915_audio_component_cleanup(struct drm_i915_private *dev_priv); |
| 1139 | |
| 1140 | /* intel_display.c */ |
| 1141 | void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco); |
| 1142 | void intel_update_rawclk(struct drm_i915_private *dev_priv); |
| 1143 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, |
| 1144 | const char *name, u32 reg, int ref_freq); |
| 1145 | extern const struct drm_plane_funcs intel_plane_funcs; |
| 1146 | void intel_init_display_hooks(struct drm_i915_private *dev_priv); |
| 1147 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info); |
| 1148 | bool intel_has_pending_fb_unpin(struct drm_device *dev); |
| 1149 | void intel_mark_busy(struct drm_i915_private *dev_priv); |
| 1150 | void intel_mark_idle(struct drm_i915_private *dev_priv); |
| 1151 | void intel_crtc_restore_mode(struct drm_crtc *crtc); |
| 1152 | int intel_display_suspend(struct drm_device *dev); |
| 1153 | void intel_encoder_destroy(struct drm_encoder *encoder); |
| 1154 | int intel_connector_init(struct intel_connector *); |
| 1155 | struct intel_connector *intel_connector_alloc(void); |
| 1156 | bool intel_connector_get_hw_state(struct intel_connector *connector); |
| 1157 | void intel_connector_attach_encoder(struct intel_connector *connector, |
| 1158 | struct intel_encoder *encoder); |
| 1159 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, |
| 1160 | struct drm_crtc *crtc); |
| 1161 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector); |
| 1162 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
| 1163 | struct drm_file *file_priv); |
| 1164 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
| 1165 | enum pipe pipe); |
| 1166 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type); |
| 1167 | static inline void |
| 1168 | intel_wait_for_vblank(struct drm_device *dev, int pipe) |
| 1169 | { |
| 1170 | drm_wait_one_vblank(dev, pipe); |
| 1171 | } |
| 1172 | static inline void |
| 1173 | intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe) |
| 1174 | { |
| 1175 | const struct intel_crtc *crtc = |
| 1176 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); |
| 1177 | |
| 1178 | if (crtc->active) |
| 1179 | intel_wait_for_vblank(dev, pipe); |
| 1180 | } |
| 1181 | |
| 1182 | u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc); |
| 1183 | |
| 1184 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); |
| 1185 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
| 1186 | struct intel_digital_port *dport, |
| 1187 | unsigned int expected_mask); |
| 1188 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
| 1189 | struct drm_display_mode *mode, |
| 1190 | struct intel_load_detect_pipe *old, |
| 1191 | struct drm_modeset_acquire_ctx *ctx); |
| 1192 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
| 1193 | struct intel_load_detect_pipe *old, |
| 1194 | struct drm_modeset_acquire_ctx *ctx); |
| 1195 | int intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, |
| 1196 | unsigned int rotation); |
| 1197 | void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation); |
| 1198 | struct drm_framebuffer * |
| 1199 | __intel_framebuffer_create(struct drm_device *dev, |
| 1200 | struct drm_mode_fb_cmd2 *mode_cmd, |
| 1201 | struct drm_i915_gem_object *obj); |
| 1202 | void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe); |
| 1203 | void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe); |
| 1204 | void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe); |
| 1205 | int intel_prepare_plane_fb(struct drm_plane *plane, |
| 1206 | const struct drm_plane_state *new_state); |
| 1207 | void intel_cleanup_plane_fb(struct drm_plane *plane, |
| 1208 | const struct drm_plane_state *old_state); |
| 1209 | int intel_plane_atomic_get_property(struct drm_plane *plane, |
| 1210 | const struct drm_plane_state *state, |
| 1211 | struct drm_property *property, |
| 1212 | uint64_t *val); |
| 1213 | int intel_plane_atomic_set_property(struct drm_plane *plane, |
| 1214 | struct drm_plane_state *state, |
| 1215 | struct drm_property *property, |
| 1216 | uint64_t val); |
| 1217 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
| 1218 | struct drm_plane_state *plane_state); |
| 1219 | |
| 1220 | unsigned int intel_tile_height(const struct drm_i915_private *dev_priv, |
| 1221 | uint64_t fb_modifier, unsigned int cpp); |
| 1222 | |
| 1223 | static inline bool |
| 1224 | intel_rotation_90_or_270(unsigned int rotation) |
| 1225 | { |
| 1226 | return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270)); |
| 1227 | } |
| 1228 | |
| 1229 | void intel_create_rotation_property(struct drm_device *dev, |
| 1230 | struct intel_plane *plane); |
| 1231 | |
| 1232 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
| 1233 | enum pipe pipe); |
| 1234 | |
| 1235 | int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, |
| 1236 | const struct dpll *dpll); |
| 1237 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe); |
| 1238 | int lpt_get_iclkip(struct drm_i915_private *dev_priv); |
| 1239 | |
| 1240 | /* modesetting asserts */ |
| 1241 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
| 1242 | enum pipe pipe); |
| 1243 | void assert_pll(struct drm_i915_private *dev_priv, |
| 1244 | enum pipe pipe, bool state); |
| 1245 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) |
| 1246 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) |
| 1247 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state); |
| 1248 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) |
| 1249 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) |
| 1250 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
| 1251 | enum pipe pipe, bool state); |
| 1252 | #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) |
| 1253 | #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) |
| 1254 | void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state); |
| 1255 | #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) |
| 1256 | #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) |
| 1257 | u32 intel_compute_tile_offset(int *x, int *y, |
| 1258 | const struct drm_framebuffer *fb, int plane, |
| 1259 | unsigned int pitch, |
| 1260 | unsigned int rotation); |
| 1261 | void intel_prepare_reset(struct drm_i915_private *dev_priv); |
| 1262 | void intel_finish_reset(struct drm_i915_private *dev_priv); |
| 1263 | void hsw_enable_pc8(struct drm_i915_private *dev_priv); |
| 1264 | void hsw_disable_pc8(struct drm_i915_private *dev_priv); |
| 1265 | void bxt_init_cdclk(struct drm_i915_private *dev_priv); |
| 1266 | void bxt_uninit_cdclk(struct drm_i915_private *dev_priv); |
| 1267 | void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy); |
| 1268 | void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy); |
| 1269 | bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv, |
| 1270 | enum dpio_phy phy); |
| 1271 | bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv, |
| 1272 | enum dpio_phy phy); |
| 1273 | void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv); |
| 1274 | void bxt_enable_dc9(struct drm_i915_private *dev_priv); |
| 1275 | void bxt_disable_dc9(struct drm_i915_private *dev_priv); |
| 1276 | void gen9_enable_dc5(struct drm_i915_private *dev_priv); |
| 1277 | void skl_init_cdclk(struct drm_i915_private *dev_priv); |
| 1278 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv); |
| 1279 | unsigned int skl_cdclk_get_vco(unsigned int freq); |
| 1280 | void skl_enable_dc6(struct drm_i915_private *dev_priv); |
| 1281 | void skl_disable_dc6(struct drm_i915_private *dev_priv); |
| 1282 | void intel_dp_get_m_n(struct intel_crtc *crtc, |
| 1283 | struct intel_crtc_state *pipe_config); |
| 1284 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n); |
| 1285 | int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); |
| 1286 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
| 1287 | struct dpll *best_clock); |
| 1288 | int chv_calc_dpll_params(int refclk, struct dpll *pll_clock); |
| 1289 | |
| 1290 | bool intel_crtc_active(struct drm_crtc *crtc); |
| 1291 | void hsw_enable_ips(struct intel_crtc *crtc); |
| 1292 | void hsw_disable_ips(struct intel_crtc *crtc); |
| 1293 | enum intel_display_power_domain |
| 1294 | intel_display_port_power_domain(struct intel_encoder *intel_encoder); |
| 1295 | enum intel_display_power_domain |
| 1296 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder); |
| 1297 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
| 1298 | struct intel_crtc_state *pipe_config); |
| 1299 | |
| 1300 | int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state); |
| 1301 | int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state); |
| 1302 | |
| 1303 | u32 intel_plane_obj_offset(struct intel_plane *intel_plane, |
| 1304 | struct drm_i915_gem_object *obj, |
| 1305 | unsigned int plane); |
| 1306 | |
| 1307 | u32 skl_plane_ctl_format(uint32_t pixel_format); |
| 1308 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier); |
| 1309 | u32 skl_plane_ctl_rotation(unsigned int rotation); |
| 1310 | |
| 1311 | /* intel_csr.c */ |
| 1312 | void intel_csr_ucode_init(struct drm_i915_private *); |
| 1313 | void intel_csr_load_program(struct drm_i915_private *); |
| 1314 | void intel_csr_ucode_fini(struct drm_i915_private *); |
| 1315 | void intel_csr_ucode_suspend(struct drm_i915_private *); |
| 1316 | void intel_csr_ucode_resume(struct drm_i915_private *); |
| 1317 | |
| 1318 | /* intel_dp.c */ |
| 1319 | bool intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port); |
| 1320 | bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
| 1321 | struct intel_connector *intel_connector); |
| 1322 | void intel_dp_set_link_params(struct intel_dp *intel_dp, |
| 1323 | const struct intel_crtc_state *pipe_config); |
| 1324 | void intel_dp_start_link_train(struct intel_dp *intel_dp); |
| 1325 | void intel_dp_stop_link_train(struct intel_dp *intel_dp); |
| 1326 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); |
| 1327 | void intel_dp_encoder_reset(struct drm_encoder *encoder); |
| 1328 | void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder); |
| 1329 | void intel_dp_encoder_destroy(struct drm_encoder *encoder); |
| 1330 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc); |
| 1331 | bool intel_dp_compute_config(struct intel_encoder *encoder, |
| 1332 | struct intel_crtc_state *pipe_config); |
| 1333 | bool intel_dp_is_edp(struct drm_device *dev, enum port port); |
| 1334 | enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, |
| 1335 | bool long_hpd); |
| 1336 | void intel_edp_backlight_on(struct intel_dp *intel_dp); |
| 1337 | void intel_edp_backlight_off(struct intel_dp *intel_dp); |
| 1338 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp); |
| 1339 | void intel_edp_panel_on(struct intel_dp *intel_dp); |
| 1340 | void intel_edp_panel_off(struct intel_dp *intel_dp); |
| 1341 | void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector); |
| 1342 | void intel_dp_mst_suspend(struct drm_device *dev); |
| 1343 | void intel_dp_mst_resume(struct drm_device *dev); |
| 1344 | int intel_dp_max_link_rate(struct intel_dp *intel_dp); |
| 1345 | int intel_dp_rate_select(struct intel_dp *intel_dp, int rate); |
| 1346 | void intel_dp_hot_plug(struct intel_encoder *intel_encoder); |
| 1347 | void intel_power_sequencer_reset(struct drm_i915_private *dev_priv); |
| 1348 | uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes); |
| 1349 | void intel_plane_destroy(struct drm_plane *plane); |
| 1350 | void intel_edp_drrs_enable(struct intel_dp *intel_dp); |
| 1351 | void intel_edp_drrs_disable(struct intel_dp *intel_dp); |
| 1352 | void intel_edp_drrs_invalidate(struct drm_device *dev, |
| 1353 | unsigned frontbuffer_bits); |
| 1354 | void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits); |
| 1355 | bool intel_digital_port_connected(struct drm_i915_private *dev_priv, |
| 1356 | struct intel_digital_port *port); |
| 1357 | |
| 1358 | void |
| 1359 | intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, |
| 1360 | uint8_t dp_train_pat); |
| 1361 | void |
| 1362 | intel_dp_set_signal_levels(struct intel_dp *intel_dp); |
| 1363 | void intel_dp_set_idle_link_train(struct intel_dp *intel_dp); |
| 1364 | uint8_t |
| 1365 | intel_dp_voltage_max(struct intel_dp *intel_dp); |
| 1366 | uint8_t |
| 1367 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing); |
| 1368 | void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, |
| 1369 | uint8_t *link_bw, uint8_t *rate_select); |
| 1370 | bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp); |
| 1371 | bool |
| 1372 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]); |
| 1373 | |
| 1374 | static inline unsigned int intel_dp_unused_lane_mask(int lane_count) |
| 1375 | { |
| 1376 | return ~((1 << lane_count) - 1) & 0xf; |
| 1377 | } |
| 1378 | |
| 1379 | /* intel_dp_aux_backlight.c */ |
| 1380 | int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector); |
| 1381 | |
| 1382 | /* intel_dp_mst.c */ |
| 1383 | int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id); |
| 1384 | void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port); |
| 1385 | /* intel_dsi.c */ |
| 1386 | void intel_dsi_init(struct drm_device *dev); |
| 1387 | |
| 1388 | /* intel_dsi_dcs_backlight.c */ |
| 1389 | int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector); |
| 1390 | |
| 1391 | /* intel_dvo.c */ |
| 1392 | void intel_dvo_init(struct drm_device *dev); |
| 1393 | |
| 1394 | |
| 1395 | /* legacy fbdev emulation in intel_fbdev.c */ |
| 1396 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
| 1397 | extern int intel_fbdev_init(struct drm_device *dev); |
| 1398 | extern void intel_fbdev_initial_config_async(struct drm_device *dev); |
| 1399 | extern void intel_fbdev_fini(struct drm_device *dev); |
| 1400 | extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous); |
| 1401 | extern void intel_fbdev_output_poll_changed(struct drm_device *dev); |
| 1402 | extern void intel_fbdev_restore_mode(struct drm_device *dev); |
| 1403 | #else |
| 1404 | static inline int intel_fbdev_init(struct drm_device *dev) |
| 1405 | { |
| 1406 | return 0; |
| 1407 | } |
| 1408 | |
| 1409 | static inline void intel_fbdev_initial_config_async(struct drm_device *dev) |
| 1410 | { |
| 1411 | } |
| 1412 | |
| 1413 | static inline void intel_fbdev_fini(struct drm_device *dev) |
| 1414 | { |
| 1415 | } |
| 1416 | |
| 1417 | static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous) |
| 1418 | { |
| 1419 | } |
| 1420 | |
| 1421 | static inline void intel_fbdev_restore_mode(struct drm_device *dev) |
| 1422 | { |
| 1423 | } |
| 1424 | #endif |
| 1425 | |
| 1426 | /* intel_fbc.c */ |
| 1427 | void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv, |
| 1428 | struct drm_atomic_state *state); |
| 1429 | bool intel_fbc_is_active(struct drm_i915_private *dev_priv); |
| 1430 | void intel_fbc_pre_update(struct intel_crtc *crtc, |
| 1431 | struct intel_crtc_state *crtc_state, |
| 1432 | struct intel_plane_state *plane_state); |
| 1433 | void intel_fbc_post_update(struct intel_crtc *crtc); |
| 1434 | void intel_fbc_init(struct drm_i915_private *dev_priv); |
| 1435 | void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv); |
| 1436 | void intel_fbc_enable(struct intel_crtc *crtc, |
| 1437 | struct intel_crtc_state *crtc_state, |
| 1438 | struct intel_plane_state *plane_state); |
| 1439 | void intel_fbc_disable(struct intel_crtc *crtc); |
| 1440 | void intel_fbc_global_disable(struct drm_i915_private *dev_priv); |
| 1441 | void intel_fbc_invalidate(struct drm_i915_private *dev_priv, |
| 1442 | unsigned int frontbuffer_bits, |
| 1443 | enum fb_op_origin origin); |
| 1444 | void intel_fbc_flush(struct drm_i915_private *dev_priv, |
| 1445 | unsigned int frontbuffer_bits, enum fb_op_origin origin); |
| 1446 | void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv); |
| 1447 | |
| 1448 | /* intel_hdmi.c */ |
| 1449 | void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port); |
| 1450 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
| 1451 | struct intel_connector *intel_connector); |
| 1452 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); |
| 1453 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
| 1454 | struct intel_crtc_state *pipe_config); |
| 1455 | void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable); |
| 1456 | |
| 1457 | |
| 1458 | /* intel_lvds.c */ |
| 1459 | void intel_lvds_init(struct drm_device *dev); |
| 1460 | struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev); |
| 1461 | bool intel_is_dual_link_lvds(struct drm_device *dev); |
| 1462 | |
| 1463 | |
| 1464 | /* intel_modes.c */ |
| 1465 | int intel_connector_update_modes(struct drm_connector *connector, |
| 1466 | struct edid *edid); |
| 1467 | int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); |
| 1468 | void intel_attach_force_audio_property(struct drm_connector *connector); |
| 1469 | void intel_attach_broadcast_rgb_property(struct drm_connector *connector); |
| 1470 | void intel_attach_aspect_ratio_property(struct drm_connector *connector); |
| 1471 | |
| 1472 | |
| 1473 | /* intel_overlay.c */ |
| 1474 | void intel_setup_overlay(struct drm_i915_private *dev_priv); |
| 1475 | void intel_cleanup_overlay(struct drm_i915_private *dev_priv); |
| 1476 | int intel_overlay_switch_off(struct intel_overlay *overlay); |
| 1477 | int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data, |
| 1478 | struct drm_file *file_priv); |
| 1479 | int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, |
| 1480 | struct drm_file *file_priv); |
| 1481 | void intel_overlay_reset(struct drm_i915_private *dev_priv); |
| 1482 | |
| 1483 | |
| 1484 | /* intel_panel.c */ |
| 1485 | int intel_panel_init(struct intel_panel *panel, |
| 1486 | struct drm_display_mode *fixed_mode, |
| 1487 | struct drm_display_mode *downclock_mode); |
| 1488 | void intel_panel_fini(struct intel_panel *panel); |
| 1489 | void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, |
| 1490 | struct drm_display_mode *adjusted_mode); |
| 1491 | void intel_pch_panel_fitting(struct intel_crtc *crtc, |
| 1492 | struct intel_crtc_state *pipe_config, |
| 1493 | int fitting_mode); |
| 1494 | void intel_gmch_panel_fitting(struct intel_crtc *crtc, |
| 1495 | struct intel_crtc_state *pipe_config, |
| 1496 | int fitting_mode); |
| 1497 | void intel_panel_set_backlight_acpi(struct intel_connector *connector, |
| 1498 | u32 level, u32 max); |
| 1499 | int intel_panel_setup_backlight(struct drm_connector *connector, |
| 1500 | enum pipe pipe); |
| 1501 | void intel_panel_enable_backlight(struct intel_connector *connector); |
| 1502 | void intel_panel_disable_backlight(struct intel_connector *connector); |
| 1503 | void intel_panel_destroy_backlight(struct drm_connector *connector); |
| 1504 | enum drm_connector_status intel_panel_detect(struct drm_device *dev); |
| 1505 | extern struct drm_display_mode *intel_find_panel_downclock( |
| 1506 | struct drm_device *dev, |
| 1507 | struct drm_display_mode *fixed_mode, |
| 1508 | struct drm_connector *connector); |
| 1509 | |
| 1510 | #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE) |
| 1511 | int intel_backlight_device_register(struct intel_connector *connector); |
| 1512 | void intel_backlight_device_unregister(struct intel_connector *connector); |
| 1513 | #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */ |
| 1514 | static int intel_backlight_device_register(struct intel_connector *connector) |
| 1515 | { |
| 1516 | return 0; |
| 1517 | } |
| 1518 | static inline void intel_backlight_device_unregister(struct intel_connector *connector) |
| 1519 | { |
| 1520 | } |
| 1521 | #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */ |
| 1522 | |
| 1523 | |
| 1524 | /* intel_psr.c */ |
| 1525 | void intel_psr_enable(struct intel_dp *intel_dp); |
| 1526 | void intel_psr_disable(struct intel_dp *intel_dp); |
| 1527 | void intel_psr_invalidate(struct drm_device *dev, |
| 1528 | unsigned frontbuffer_bits); |
| 1529 | void intel_psr_flush(struct drm_device *dev, |
| 1530 | unsigned frontbuffer_bits, |
| 1531 | enum fb_op_origin origin); |
| 1532 | void intel_psr_init(struct drm_device *dev); |
| 1533 | void intel_psr_single_frame_update(struct drm_device *dev, |
| 1534 | unsigned frontbuffer_bits); |
| 1535 | |
| 1536 | /* intel_runtime_pm.c */ |
| 1537 | int intel_power_domains_init(struct drm_i915_private *); |
| 1538 | void intel_power_domains_fini(struct drm_i915_private *); |
| 1539 | void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume); |
| 1540 | void intel_power_domains_suspend(struct drm_i915_private *dev_priv); |
| 1541 | void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume); |
| 1542 | void bxt_display_core_uninit(struct drm_i915_private *dev_priv); |
| 1543 | void intel_runtime_pm_enable(struct drm_i915_private *dev_priv); |
| 1544 | const char * |
| 1545 | intel_display_power_domain_str(enum intel_display_power_domain domain); |
| 1546 | |
| 1547 | bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, |
| 1548 | enum intel_display_power_domain domain); |
| 1549 | bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, |
| 1550 | enum intel_display_power_domain domain); |
| 1551 | void intel_display_power_get(struct drm_i915_private *dev_priv, |
| 1552 | enum intel_display_power_domain domain); |
| 1553 | bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, |
| 1554 | enum intel_display_power_domain domain); |
| 1555 | void intel_display_power_put(struct drm_i915_private *dev_priv, |
| 1556 | enum intel_display_power_domain domain); |
| 1557 | |
| 1558 | static inline void |
| 1559 | assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv) |
| 1560 | { |
| 1561 | WARN_ONCE(dev_priv->pm.suspended, |
| 1562 | "Device suspended during HW access\n"); |
| 1563 | } |
| 1564 | |
| 1565 | static inline void |
| 1566 | assert_rpm_wakelock_held(struct drm_i915_private *dev_priv) |
| 1567 | { |
| 1568 | assert_rpm_device_not_suspended(dev_priv); |
| 1569 | /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes |
| 1570 | * too much noise. */ |
| 1571 | if (!atomic_read(&dev_priv->pm.wakeref_count)) |
| 1572 | DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access"); |
| 1573 | } |
| 1574 | |
| 1575 | static inline int |
| 1576 | assert_rpm_atomic_begin(struct drm_i915_private *dev_priv) |
| 1577 | { |
| 1578 | int seq = atomic_read(&dev_priv->pm.atomic_seq); |
| 1579 | |
| 1580 | assert_rpm_wakelock_held(dev_priv); |
| 1581 | |
| 1582 | return seq; |
| 1583 | } |
| 1584 | |
| 1585 | static inline void |
| 1586 | assert_rpm_atomic_end(struct drm_i915_private *dev_priv, int begin_seq) |
| 1587 | { |
| 1588 | WARN_ONCE(atomic_read(&dev_priv->pm.atomic_seq) != begin_seq, |
| 1589 | "HW access outside of RPM atomic section\n"); |
| 1590 | } |
| 1591 | |
| 1592 | /** |
| 1593 | * disable_rpm_wakeref_asserts - disable the RPM assert checks |
| 1594 | * @dev_priv: i915 device instance |
| 1595 | * |
| 1596 | * This function disable asserts that check if we hold an RPM wakelock |
| 1597 | * reference, while keeping the device-not-suspended checks still enabled. |
| 1598 | * It's meant to be used only in special circumstances where our rule about |
| 1599 | * the wakelock refcount wrt. the device power state doesn't hold. According |
| 1600 | * to this rule at any point where we access the HW or want to keep the HW in |
| 1601 | * an active state we must hold an RPM wakelock reference acquired via one of |
| 1602 | * the intel_runtime_pm_get() helpers. Currently there are a few special spots |
| 1603 | * where this rule doesn't hold: the IRQ and suspend/resume handlers, the |
| 1604 | * forcewake release timer, and the GPU RPS and hangcheck works. All other |
| 1605 | * users should avoid using this function. |
| 1606 | * |
| 1607 | * Any calls to this function must have a symmetric call to |
| 1608 | * enable_rpm_wakeref_asserts(). |
| 1609 | */ |
| 1610 | static inline void |
| 1611 | disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv) |
| 1612 | { |
| 1613 | atomic_inc(&dev_priv->pm.wakeref_count); |
| 1614 | } |
| 1615 | |
| 1616 | /** |
| 1617 | * enable_rpm_wakeref_asserts - re-enable the RPM assert checks |
| 1618 | * @dev_priv: i915 device instance |
| 1619 | * |
| 1620 | * This function re-enables the RPM assert checks after disabling them with |
| 1621 | * disable_rpm_wakeref_asserts. It's meant to be used only in special |
| 1622 | * circumstances otherwise its use should be avoided. |
| 1623 | * |
| 1624 | * Any calls to this function must have a symmetric call to |
| 1625 | * disable_rpm_wakeref_asserts(). |
| 1626 | */ |
| 1627 | static inline void |
| 1628 | enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv) |
| 1629 | { |
| 1630 | atomic_dec(&dev_priv->pm.wakeref_count); |
| 1631 | } |
| 1632 | |
| 1633 | /* TODO: convert users of these to rely instead on proper RPM refcounting */ |
| 1634 | #define DISABLE_RPM_WAKEREF_ASSERTS(dev_priv) \ |
| 1635 | disable_rpm_wakeref_asserts(dev_priv) |
| 1636 | |
| 1637 | #define ENABLE_RPM_WAKEREF_ASSERTS(dev_priv) \ |
| 1638 | enable_rpm_wakeref_asserts(dev_priv) |
| 1639 | |
| 1640 | void intel_runtime_pm_get(struct drm_i915_private *dev_priv); |
| 1641 | bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv); |
| 1642 | void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv); |
| 1643 | void intel_runtime_pm_put(struct drm_i915_private *dev_priv); |
| 1644 | |
| 1645 | void intel_display_set_init_power(struct drm_i915_private *dev, bool enable); |
| 1646 | |
| 1647 | void chv_phy_powergate_lanes(struct intel_encoder *encoder, |
| 1648 | bool override, unsigned int mask); |
| 1649 | bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, |
| 1650 | enum dpio_channel ch, bool override); |
| 1651 | |
| 1652 | |
| 1653 | /* intel_pm.c */ |
| 1654 | void intel_init_clock_gating(struct drm_device *dev); |
| 1655 | void intel_suspend_hw(struct drm_device *dev); |
| 1656 | int ilk_wm_max_level(const struct drm_device *dev); |
| 1657 | void intel_update_watermarks(struct drm_crtc *crtc); |
| 1658 | void intel_init_pm(struct drm_device *dev); |
| 1659 | void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv); |
| 1660 | void intel_pm_setup(struct drm_device *dev); |
| 1661 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv); |
| 1662 | void intel_gpu_ips_teardown(void); |
| 1663 | void intel_init_gt_powersave(struct drm_i915_private *dev_priv); |
| 1664 | void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv); |
| 1665 | void intel_enable_gt_powersave(struct drm_i915_private *dev_priv); |
| 1666 | void intel_disable_gt_powersave(struct drm_i915_private *dev_priv); |
| 1667 | void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv); |
| 1668 | void intel_reset_gt_powersave(struct drm_i915_private *dev_priv); |
| 1669 | void gen6_update_ring_freq(struct drm_i915_private *dev_priv); |
| 1670 | void gen6_rps_busy(struct drm_i915_private *dev_priv); |
| 1671 | void gen6_rps_reset_ei(struct drm_i915_private *dev_priv); |
| 1672 | void gen6_rps_idle(struct drm_i915_private *dev_priv); |
| 1673 | void gen6_rps_boost(struct drm_i915_private *dev_priv, |
| 1674 | struct intel_rps_client *rps, |
| 1675 | unsigned long submitted); |
| 1676 | void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req); |
| 1677 | void vlv_wm_get_hw_state(struct drm_device *dev); |
| 1678 | void ilk_wm_get_hw_state(struct drm_device *dev); |
| 1679 | void skl_wm_get_hw_state(struct drm_device *dev); |
| 1680 | void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, |
| 1681 | struct skl_ddb_allocation *ddb /* out */); |
| 1682 | uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config); |
| 1683 | bool ilk_disable_lp_wm(struct drm_device *dev); |
| 1684 | int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6); |
| 1685 | static inline int intel_enable_rc6(void) |
| 1686 | { |
| 1687 | return i915.enable_rc6; |
| 1688 | } |
| 1689 | |
| 1690 | /* intel_sdvo.c */ |
| 1691 | bool intel_sdvo_init(struct drm_device *dev, |
| 1692 | i915_reg_t reg, enum port port); |
| 1693 | |
| 1694 | |
| 1695 | /* intel_sprite.c */ |
| 1696 | int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane); |
| 1697 | int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
| 1698 | struct drm_file *file_priv); |
| 1699 | void intel_pipe_update_start(struct intel_crtc *crtc); |
| 1700 | void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work); |
| 1701 | |
| 1702 | /* intel_tv.c */ |
| 1703 | void intel_tv_init(struct drm_device *dev); |
| 1704 | |
| 1705 | /* intel_atomic.c */ |
| 1706 | int intel_connector_atomic_get_property(struct drm_connector *connector, |
| 1707 | const struct drm_connector_state *state, |
| 1708 | struct drm_property *property, |
| 1709 | uint64_t *val); |
| 1710 | struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc); |
| 1711 | void intel_crtc_destroy_state(struct drm_crtc *crtc, |
| 1712 | struct drm_crtc_state *state); |
| 1713 | struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev); |
| 1714 | void intel_atomic_state_clear(struct drm_atomic_state *); |
| 1715 | struct intel_shared_dpll_config * |
| 1716 | intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s); |
| 1717 | |
| 1718 | static inline struct intel_crtc_state * |
| 1719 | intel_atomic_get_crtc_state(struct drm_atomic_state *state, |
| 1720 | struct intel_crtc *crtc) |
| 1721 | { |
| 1722 | struct drm_crtc_state *crtc_state; |
| 1723 | crtc_state = drm_atomic_get_crtc_state(state, &crtc->base); |
| 1724 | if (IS_ERR(crtc_state)) |
| 1725 | return ERR_CAST(crtc_state); |
| 1726 | |
| 1727 | return to_intel_crtc_state(crtc_state); |
| 1728 | } |
| 1729 | |
| 1730 | static inline struct intel_plane_state * |
| 1731 | intel_atomic_get_existing_plane_state(struct drm_atomic_state *state, |
| 1732 | struct intel_plane *plane) |
| 1733 | { |
| 1734 | struct drm_plane_state *plane_state; |
| 1735 | |
| 1736 | plane_state = drm_atomic_get_existing_plane_state(state, &plane->base); |
| 1737 | |
| 1738 | return to_intel_plane_state(plane_state); |
| 1739 | } |
| 1740 | |
| 1741 | int intel_atomic_setup_scalers(struct drm_device *dev, |
| 1742 | struct intel_crtc *intel_crtc, |
| 1743 | struct intel_crtc_state *crtc_state); |
| 1744 | |
| 1745 | /* intel_atomic_plane.c */ |
| 1746 | struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane); |
| 1747 | struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane); |
| 1748 | void intel_plane_destroy_state(struct drm_plane *plane, |
| 1749 | struct drm_plane_state *state); |
| 1750 | extern const struct drm_plane_helper_funcs intel_plane_helper_funcs; |
| 1751 | |
| 1752 | /* intel_color.c */ |
| 1753 | void intel_color_init(struct drm_crtc *crtc); |
| 1754 | int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state); |
| 1755 | void intel_color_set_csc(struct drm_crtc_state *crtc_state); |
| 1756 | void intel_color_load_luts(struct drm_crtc_state *crtc_state); |
| 1757 | |
| 1758 | #endif /* __INTEL_DRV_H__ */ |